drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  44                                      int ring, u32 cp_int_cntl);
  45
  46 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  47                              unsigned *bankh, unsigned *mtaspect,
  48                              unsigned *tile_split)
  49 {
  50         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  51         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  52         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  53         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  54         switch (*bankw) {
  55         default:
  56         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  57         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  58         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  59         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  60         }
  61         switch (*bankh) {
  62         default:
  63         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  64         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  65         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  66         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  67         }
  68         switch (*mtaspect) {
  69         default:
  70         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  71         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  72         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  73         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  74         }
  75 }
  76
  77 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  78 {
  79         u16 ctl, v;
  80         int cap, err;
  81
  82         cap = pci_pcie_cap(rdev->pdev);
  83         if (!cap)
  84                 return;
  85
  86         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
  87         if (err)
  88                 return;
  89
  90         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  91
  92         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  93          * to avoid hangs or perfomance issues
  94          */
  95         if ((v == 0) || (v == 6) || (v == 7)) {
  96                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
  97                 ctl |= (2 << 12);
  98                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
  99         }
 100 }
 101
 102 /**
 103  * dce4_wait_for_vblank - vblank wait asic callback.
 104  *
 105  * @rdev: radeon_device pointer
 106  * @crtc: crtc to wait for vblank on
 107  *
 108  * Wait for vblank on the requested crtc (evergreen+).
 109  */
 110 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 111 {
 112         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
 113         int i;
 114
 115         if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
 116                 for (i = 0; i < rdev->usec_timeout; i++) {
 117                         if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
 118                                 break;
 119                         udelay(1);
 120                 }
 121                 for (i = 0; i < rdev->usec_timeout; i++) {
 122                         if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
 123                                 break;
 124                         udelay(1);
 125                 }
 126         }
 127 }
 128
 129 /**
 130  * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
 131  *
 132  * @rdev: radeon_device pointer
 133  * @crtc: crtc to prepare for pageflip on
 134  *
 135  * Pre-pageflip callback (evergreen+).
 136  * Enables the pageflip irq (vblank irq).
 137  */
 138 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 139 {
 140         /* enable the pflip int */
 141         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 142 }
 143
 144 /**
 145  * evergreen_post_page_flip - pos-pageflip callback.
 146  *
 147  * @rdev: radeon_device pointer
 148  * @crtc: crtc to cleanup pageflip on
 149  *
 150  * Post-pageflip callback (evergreen+).
 151  * Disables the pageflip irq (vblank irq).
 152  */
 153 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
 154 {
 155         /* disable the pflip int */
 156         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 157 }
 158
 159 /**
 160  * evergreen_page_flip - pageflip callback.
 161  *
 162  * @rdev: radeon_device pointer
 163  * @crtc_id: crtc to cleanup pageflip on
 164  * @crtc_base: new address of the crtc (GPU MC address)
 165  *
 166  * Does the actual pageflip (evergreen+).
 167  * During vblank we take the crtc lock and wait for the update_pending
 168  * bit to go high, when it does, we release the lock, and allow the
 169  * double buffered update to take place.
 170  * Returns the current update pending status.
 171  */
 172 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 173 {
 174         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 175         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
 176         int i;
 177
 178         /* Lock the graphics update lock */
 179         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
 180         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 181
 182         /* update the scanout addresses */
 183         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 184                upper_32_bits(crtc_base));
 185         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 186                (u32)crtc_base);
 187
 188         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 189                upper_32_bits(crtc_base));
 190         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 191                (u32)crtc_base);
 192
 193         /* Wait for update_pending to go high. */
 194         for (i = 0; i < rdev->usec_timeout; i++) {
 195                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 196                         break;
 197                 udelay(1);
 198         }
 199         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 200
 201         /* Unlock the lock, so double-buffering can take place inside vblank */
 202         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 203         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 204
 205         /* Return current update_pending status: */
 206         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 207 }
 208
 209 /* get temperature in millidegrees */
 210 int evergreen_get_temp(struct radeon_device *rdev)
 211 {
 212         u32 temp, toffset;
 213         int actual_temp = 0;
 214
 215         if (rdev->family == CHIP_JUNIPER) {
 216                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 217                         TOFFSET_SHIFT;
 218                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 219                         TS0_ADC_DOUT_SHIFT;
 220
 221                 if (toffset & 0x100)
 222                         actual_temp = temp / 2 - (0x200 - toffset);
 223                 else
 224                         actual_temp = temp / 2 + toffset;
 225
 226                 actual_temp = actual_temp * 1000;
 227
 228         } else {
 229                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 230                         ASIC_T_SHIFT;
 231
 232                 if (temp & 0x400)
 233                         actual_temp = -256;
 234                 else if (temp & 0x200)
 235                         actual_temp = 255;
 236                 else if (temp & 0x100) {
 237                         actual_temp = temp & 0x1ff;
 238                         actual_temp |= ~0x1ff;
 239                 } else
 240                         actual_temp = temp & 0xff;
 241
 242                 actual_temp = (actual_temp * 1000) / 2;
 243         }
 244
 245         return actual_temp;
 246 }
 247
 248 int sumo_get_temp(struct radeon_device *rdev)
 249 {
 250         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 251         int actual_temp = temp - 49;
 252
 253         return actual_temp * 1000;
 254 }
 255
 256 /**
 257  * sumo_pm_init_profile - Initialize power profiles callback.
 258  *
 259  * @rdev: radeon_device pointer
 260  *
 261  * Initialize the power states used in profile mode
 262  * (sumo, trinity, SI).
 263  * Used for profile mode only.
 264  */
 265 void sumo_pm_init_profile(struct radeon_device *rdev)
 266 {
 267         int idx;
 268
 269         /* default */
 270         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 271         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 272         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 273         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 274
 275         /* low,mid sh/mh */
 276         if (rdev->flags & RADEON_IS_MOBILITY)
 277                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 278         else
 279                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 280
 281         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 282         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 283         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 284         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 285
 286         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 287         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 288         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 289         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 290
 291         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 292         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 293         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 294         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 295
 296         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 297         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 298         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 299         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 300
 301         /* high sh/mh */
 302         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 303         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 304         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 305         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 306         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 307                 rdev->pm.power_state[idx].num_clock_modes - 1;
 308
 309         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 310         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 311         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 312         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 313                 rdev->pm.power_state[idx].num_clock_modes - 1;
 314 }
 315
 316 /**
 317  * evergreen_pm_misc - set additional pm hw parameters callback.
 318  *
 319  * @rdev: radeon_device pointer
 320  *
 321  * Set non-clock parameters associated with a power state
 322  * (voltage, etc.) (evergreen+).
 323  */
 324 void evergreen_pm_misc(struct radeon_device *rdev)
 325 {
 326         int req_ps_idx = rdev->pm.requested_power_state_index;
 327         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 328         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 329         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 330
 331         if (voltage->type == VOLTAGE_SW) {
 332                 /* 0xff01 is a flag rather then an actual voltage */
 333                 if (voltage->voltage == 0xff01)
 334                         return;
 335                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 336                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 337                         rdev->pm.current_vddc = voltage->voltage;
 338                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 339                 }
 340                 /* 0xff01 is a flag rather then an actual voltage */
 341                 if (voltage->vddci == 0xff01)
 342                         return;
 343                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 344                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 345                         rdev->pm.current_vddci = voltage->vddci;
 346                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 347                 }
 348         }
 349 }
 350
 351 /**
 352  * evergreen_pm_prepare - pre-power state change callback.
 353  *
 354  * @rdev: radeon_device pointer
 355  *
 356  * Prepare for a power state change (evergreen+).
 357  */
 358 void evergreen_pm_prepare(struct radeon_device *rdev)
 359 {
 360         struct drm_device *ddev = rdev->ddev;
 361         struct drm_crtc *crtc;
 362         struct radeon_crtc *radeon_crtc;
 363         u32 tmp;
 364
 365         /* disable any active CRTCs */
 366         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 367                 radeon_crtc = to_radeon_crtc(crtc);
 368                 if (radeon_crtc->enabled) {
 369                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 370                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 371                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 372                 }
 373         }
 374 }
 375
 376 /**
 377  * evergreen_pm_finish - post-power state change callback.
 378  *
 379  * @rdev: radeon_device pointer
 380  *
 381  * Clean up after a power state change (evergreen+).
 382  */
 383 void evergreen_pm_finish(struct radeon_device *rdev)
 384 {
 385         struct drm_device *ddev = rdev->ddev;
 386         struct drm_crtc *crtc;
 387         struct radeon_crtc *radeon_crtc;
 388         u32 tmp;
 389
 390         /* enable any active CRTCs */
 391         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 392                 radeon_crtc = to_radeon_crtc(crtc);
 393                 if (radeon_crtc->enabled) {
 394                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 395                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 396                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 397                 }
 398         }
 399 }
 400
 401 /**
 402  * evergreen_hpd_sense - hpd sense callback.
 403  *
 404  * @rdev: radeon_device pointer
 405  * @hpd: hpd (hotplug detect) pin
 406  *
 407  * Checks if a digital monitor is connected (evergreen+).
 408  * Returns true if connected, false if not connected.
 409  */
 410 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 411 {
 412         bool connected = false;
 413
 414         switch (hpd) {
 415         case RADEON_HPD_1:
 416                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 417                         connected = true;
 418                 break;
 419         case RADEON_HPD_2:
 420                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 421                         connected = true;
 422                 break;
 423         case RADEON_HPD_3:
 424                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 425                         connected = true;
 426                 break;
 427         case RADEON_HPD_4:
 428                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 429                         connected = true;
 430                 break;
 431         case RADEON_HPD_5:
 432                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 433                         connected = true;
 434                 break;
 435         case RADEON_HPD_6:
 436                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 437                         connected = true;
 438                         break;
 439         default:
 440                 break;
 441         }
 442
 443         return connected;
 444 }
 445
 446 /**
 447  * evergreen_hpd_set_polarity - hpd set polarity callback.
 448  *
 449  * @rdev: radeon_device pointer
 450  * @hpd: hpd (hotplug detect) pin
 451  *
 452  * Set the polarity of the hpd pin (evergreen+).
 453  */
 454 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 455                                 enum radeon_hpd_id hpd)
 456 {
 457         u32 tmp;
 458         bool connected = evergreen_hpd_sense(rdev, hpd);
 459
 460         switch (hpd) {
 461         case RADEON_HPD_1:
 462                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 463                 if (connected)
 464                         tmp &= ~DC_HPDx_INT_POLARITY;
 465                 else
 466                         tmp |= DC_HPDx_INT_POLARITY;
 467                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 468                 break;
 469         case RADEON_HPD_2:
 470                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 471                 if (connected)
 472                         tmp &= ~DC_HPDx_INT_POLARITY;
 473                 else
 474                         tmp |= DC_HPDx_INT_POLARITY;
 475                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 476                 break;
 477         case RADEON_HPD_3:
 478                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 479                 if (connected)
 480                         tmp &= ~DC_HPDx_INT_POLARITY;
 481                 else
 482                         tmp |= DC_HPDx_INT_POLARITY;
 483                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 484                 break;
 485         case RADEON_HPD_4:
 486                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 487                 if (connected)
 488                         tmp &= ~DC_HPDx_INT_POLARITY;
 489                 else
 490                         tmp |= DC_HPDx_INT_POLARITY;
 491                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 492                 break;
 493         case RADEON_HPD_5:
 494                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 495                 if (connected)
 496                         tmp &= ~DC_HPDx_INT_POLARITY;
 497                 else
 498                         tmp |= DC_HPDx_INT_POLARITY;
 499                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 500                         break;
 501         case RADEON_HPD_6:
 502                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 503                 if (connected)
 504                         tmp &= ~DC_HPDx_INT_POLARITY;
 505                 else
 506                         tmp |= DC_HPDx_INT_POLARITY;
 507                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 508                 break;
 509         default:
 510                 break;
 511         }
 512 }
 513
 514 /**
 515  * evergreen_hpd_init - hpd setup callback.
 516  *
 517  * @rdev: radeon_device pointer
 518  *
 519  * Setup the hpd pins used by the card (evergreen+).
 520  * Enable the pin, set the polarity, and enable the hpd interrupts.
 521  */
 522 void evergreen_hpd_init(struct radeon_device *rdev)
 523 {
 524         struct drm_device *dev = rdev->ddev;
 525         struct drm_connector *connector;
 526         unsigned enabled = 0;
 527         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 528                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 529
 530         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 531                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 532                 switch (radeon_connector->hpd.hpd) {
 533                 case RADEON_HPD_1:
 534                         WREG32(DC_HPD1_CONTROL, tmp);
 535                         break;
 536                 case RADEON_HPD_2:
 537                         WREG32(DC_HPD2_CONTROL, tmp);
 538                         break;
 539                 case RADEON_HPD_3:
 540                         WREG32(DC_HPD3_CONTROL, tmp);
 541                         break;
 542                 case RADEON_HPD_4:
 543                         WREG32(DC_HPD4_CONTROL, tmp);
 544                         break;
 545                 case RADEON_HPD_5:
 546                         WREG32(DC_HPD5_CONTROL, tmp);
 547                         break;
 548                 case RADEON_HPD_6:
 549                         WREG32(DC_HPD6_CONTROL, tmp);
 550                         break;
 551                 default:
 552                         break;
 553                 }
 554                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 555                 enabled |= 1 << radeon_connector->hpd.hpd;
 556         }
 557         radeon_irq_kms_enable_hpd(rdev, enabled);
 558 }
 559
 560 /**
 561  * evergreen_hpd_fini - hpd tear down callback.
 562  *
 563  * @rdev: radeon_device pointer
 564  *
 565  * Tear down the hpd pins used by the card (evergreen+).
 566  * Disable the hpd interrupts.
 567  */
 568 void evergreen_hpd_fini(struct radeon_device *rdev)
 569 {
 570         struct drm_device *dev = rdev->ddev;
 571         struct drm_connector *connector;
 572         unsigned disabled = 0;
 573
 574         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 575                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 576                 switch (radeon_connector->hpd.hpd) {
 577                 case RADEON_HPD_1:
 578                         WREG32(DC_HPD1_CONTROL, 0);
 579                         break;
 580                 case RADEON_HPD_2:
 581                         WREG32(DC_HPD2_CONTROL, 0);
 582                         break;
 583                 case RADEON_HPD_3:
 584                         WREG32(DC_HPD3_CONTROL, 0);
 585                         break;
 586                 case RADEON_HPD_4:
 587                         WREG32(DC_HPD4_CONTROL, 0);
 588                         break;
 589                 case RADEON_HPD_5:
 590                         WREG32(DC_HPD5_CONTROL, 0);
 591                         break;
 592                 case RADEON_HPD_6:
 593                         WREG32(DC_HPD6_CONTROL, 0);
 594                         break;
 595                 default:
 596                         break;
 597                 }
 598                 disabled |= 1 << radeon_connector->hpd.hpd;
 599         }
 600         radeon_irq_kms_disable_hpd(rdev, disabled);
 601 }
 602
 603 /* watermark setup */
 604
 605 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 606                                         struct radeon_crtc *radeon_crtc,
 607                                         struct drm_display_mode *mode,
 608                                         struct drm_display_mode *other_mode)
 609 {
 610         u32 tmp;
 611         /*
 612          * Line Buffer Setup
 613          * There are 3 line buffers, each one shared by 2 display controllers.
 614          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 615          * the display controllers.  The paritioning is done via one of four
 616          * preset allocations specified in bits 2:0:
 617          * first display controller
 618          *  0 - first half of lb (3840 * 2)
 619          *  1 - first 3/4 of lb (5760 * 2)
 620          *  2 - whole lb (7680 * 2), other crtc must be disabled
 621          *  3 - first 1/4 of lb (1920 * 2)
 622          * second display controller
 623          *  4 - second half of lb (3840 * 2)
 624          *  5 - second 3/4 of lb (5760 * 2)
 625          *  6 - whole lb (7680 * 2), other crtc must be disabled
 626          *  7 - last 1/4 of lb (1920 * 2)
 627          */
 628         /* this can get tricky if we have two large displays on a paired group
 629          * of crtcs.  Ideally for multiple large displays we'd assign them to
 630          * non-linked crtcs for maximum line buffer allocation.
 631          */
 632         if (radeon_crtc->base.enabled && mode) {
 633                 if (other_mode)
 634                         tmp = 0; /* 1/2 */
 635                 else
 636                         tmp = 2; /* whole */
 637         } else
 638                 tmp = 0;
 639
 640         /* second controller of the pair uses second half of the lb */
 641         if (radeon_crtc->crtc_id % 2)
 642                 tmp += 4;
 643         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 644
 645         if (radeon_crtc->base.enabled && mode) {
 646                 switch (tmp) {
 647                 case 0:
 648                 case 4:
 649                 default:
 650                         if (ASIC_IS_DCE5(rdev))
 651                                 return 4096 * 2;
 652                         else
 653                                 return 3840 * 2;
 654                 case 1:
 655                 case 5:
 656                         if (ASIC_IS_DCE5(rdev))
 657                                 return 6144 * 2;
 658                         else
 659                                 return 5760 * 2;
 660                 case 2:
 661                 case 6:
 662                         if (ASIC_IS_DCE5(rdev))
 663                                 return 8192 * 2;
 664                         else
 665                                 return 7680 * 2;
 666                 case 3:
 667                 case 7:
 668                         if (ASIC_IS_DCE5(rdev))
 669                                 return 2048 * 2;
 670                         else
 671                                 return 1920 * 2;
 672                 }
 673         }
 674
 675         /* controller not enabled, so no lb used */
 676         return 0;
 677 }
 678
 679 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 680 {
 681         u32 tmp = RREG32(MC_SHARED_CHMAP);
 682
 683         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 684         case 0:
 685         default:
 686                 return 1;
 687         case 1:
 688                 return 2;
 689         case 2:
 690                 return 4;
 691         case 3:
 692                 return 8;
 693         }
 694 }
 695
 696 struct evergreen_wm_params {
 697         u32 dram_channels; /* number of dram channels */
 698         u32 yclk;          /* bandwidth per dram data pin in kHz */
 699         u32 sclk;          /* engine clock in kHz */
 700         u32 disp_clk;      /* display clock in kHz */
 701         u32 src_width;     /* viewport width */
 702         u32 active_time;   /* active display time in ns */
 703         u32 blank_time;    /* blank time in ns */
 704         bool interlaced;    /* mode is interlaced */
 705         fixed20_12 vsc;    /* vertical scale ratio */
 706         u32 num_heads;     /* number of active crtcs */
 707         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 708         u32 lb_size;       /* line buffer allocated to pipe */
 709         u32 vtaps;         /* vertical scaler taps */
 710 };
 711
 712 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 713 {
 714         /* Calculate DRAM Bandwidth and the part allocated to display. */
 715         fixed20_12 dram_efficiency; /* 0.7 */
 716         fixed20_12 yclk, dram_channels, bandwidth;
 717         fixed20_12 a;
 718
 719         a.full = dfixed_const(1000);
 720         yclk.full = dfixed_const(wm->yclk);
 721         yclk.full = dfixed_div(yclk, a);
 722         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 723         a.full = dfixed_const(10);
 724         dram_efficiency.full = dfixed_const(7);
 725         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 726         bandwidth.full = dfixed_mul(dram_channels, yclk);
 727         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 728
 729         return dfixed_trunc(bandwidth);
 730 }
 731
 732 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 733 {
 734         /* Calculate DRAM Bandwidth and the part allocated to display. */
 735         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 736         fixed20_12 yclk, dram_channels, bandwidth;
 737         fixed20_12 a;
 738
 739         a.full = dfixed_const(1000);
 740         yclk.full = dfixed_const(wm->yclk);
 741         yclk.full = dfixed_div(yclk, a);
 742         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 743         a.full = dfixed_const(10);
 744         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 745         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 746         bandwidth.full = dfixed_mul(dram_channels, yclk);
 747         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 748
 749         return dfixed_trunc(bandwidth);
 750 }
 751
 752 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 753 {
 754         /* Calculate the display Data return Bandwidth */
 755         fixed20_12 return_efficiency; /* 0.8 */
 756         fixed20_12 sclk, bandwidth;
 757         fixed20_12 a;
 758
 759         a.full = dfixed_const(1000);
 760         sclk.full = dfixed_const(wm->sclk);
 761         sclk.full = dfixed_div(sclk, a);
 762         a.full = dfixed_const(10);
 763         return_efficiency.full = dfixed_const(8);
 764         return_efficiency.full = dfixed_div(return_efficiency, a);
 765         a.full = dfixed_const(32);
 766         bandwidth.full = dfixed_mul(a, sclk);
 767         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 768
 769         return dfixed_trunc(bandwidth);
 770 }
 771
 772 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 773 {
 774         /* Calculate the DMIF Request Bandwidth */
 775         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 776         fixed20_12 disp_clk, bandwidth;
 777         fixed20_12 a;
 778
 779         a.full = dfixed_const(1000);
 780         disp_clk.full = dfixed_const(wm->disp_clk);
 781         disp_clk.full = dfixed_div(disp_clk, a);
 782         a.full = dfixed_const(10);
 783         disp_clk_request_efficiency.full = dfixed_const(8);
 784         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 785         a.full = dfixed_const(32);
 786         bandwidth.full = dfixed_mul(a, disp_clk);
 787         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 788
 789         return dfixed_trunc(bandwidth);
 790 }
 791
 792 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 793 {
 794         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 795         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 796         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 797         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 798
 799         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 800 }
 801
 802 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 803 {
 804         /* Calculate the display mode Average Bandwidth
 805          * DisplayMode should contain the source and destination dimensions,
 806          * timing, etc.
 807          */
 808         fixed20_12 bpp;
 809         fixed20_12 line_time;
 810         fixed20_12 src_width;
 811         fixed20_12 bandwidth;
 812         fixed20_12 a;
 813
 814         a.full = dfixed_const(1000);
 815         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 816         line_time.full = dfixed_div(line_time, a);
 817         bpp.full = dfixed_const(wm->bytes_per_pixel);
 818         src_width.full = dfixed_const(wm->src_width);
 819         bandwidth.full = dfixed_mul(src_width, bpp);
 820         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 821         bandwidth.full = dfixed_div(bandwidth, line_time);
 822
 823         return dfixed_trunc(bandwidth);
 824 }
 825
 826 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 827 {
 828         /* First calcualte the latency in ns */
 829         u32 mc_latency = 2000; /* 2000 ns. */
 830         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 831         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 832         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 833         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 834         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 835                 (wm->num_heads * cursor_line_pair_return_time);
 836         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 837         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 838         fixed20_12 a, b, c;
 839
 840         if (wm->num_heads == 0)
 841                 return 0;
 842
 843         a.full = dfixed_const(2);
 844         b.full = dfixed_const(1);
 845         if ((wm->vsc.full > a.full) ||
 846             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 847             (wm->vtaps >= 5) ||
 848             ((wm->vsc.full >= a.full) && wm->interlaced))
 849                 max_src_lines_per_dst_line = 4;
 850         else
 851                 max_src_lines_per_dst_line = 2;
 852
 853         a.full = dfixed_const(available_bandwidth);
 854         b.full = dfixed_const(wm->num_heads);
 855         a.full = dfixed_div(a, b);
 856
 857         b.full = dfixed_const(1000);
 858         c.full = dfixed_const(wm->disp_clk);
 859         b.full = dfixed_div(c, b);
 860         c.full = dfixed_const(wm->bytes_per_pixel);
 861         b.full = dfixed_mul(b, c);
 862
 863         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 864
 865         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 866         b.full = dfixed_const(1000);
 867         c.full = dfixed_const(lb_fill_bw);
 868         b.full = dfixed_div(c, b);
 869         a.full = dfixed_div(a, b);
 870         line_fill_time = dfixed_trunc(a);
 871
 872         if (line_fill_time < wm->active_time)
 873                 return latency;
 874         else
 875                 return latency + (line_fill_time - wm->active_time);
 876
 877 }
 878
 879 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 880 {
 881         if (evergreen_average_bandwidth(wm) <=
 882             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 883                 return true;
 884         else
 885                 return false;
 886 };
 887
 888 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 889 {
 890         if (evergreen_average_bandwidth(wm) <=
 891             (evergreen_available_bandwidth(wm) / wm->num_heads))
 892                 return true;
 893         else
 894                 return false;
 895 };
 896
 897 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 898 {
 899         u32 lb_partitions = wm->lb_size / wm->src_width;
 900         u32 line_time = wm->active_time + wm->blank_time;
 901         u32 latency_tolerant_lines;
 902         u32 latency_hiding;
 903         fixed20_12 a;
 904
 905         a.full = dfixed_const(1);
 906         if (wm->vsc.full > a.full)
 907                 latency_tolerant_lines = 1;
 908         else {
 909                 if (lb_partitions <= (wm->vtaps + 1))
 910                         latency_tolerant_lines = 1;
 911                 else
 912                         latency_tolerant_lines = 2;
 913         }
 914
 915         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 916
 917         if (evergreen_latency_watermark(wm) <= latency_hiding)
 918                 return true;
 919         else
 920                 return false;
 921 }
 922
 923 static void evergreen_program_watermarks(struct radeon_device *rdev,
 924                                          struct radeon_crtc *radeon_crtc,
 925                                          u32 lb_size, u32 num_heads)
 926 {
 927         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 928         struct evergreen_wm_params wm;
 929         u32 pixel_period;
 930         u32 line_time = 0;
 931         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 932         u32 priority_a_mark = 0, priority_b_mark = 0;
 933         u32 priority_a_cnt = PRIORITY_OFF;
 934         u32 priority_b_cnt = PRIORITY_OFF;
 935         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 936         u32 tmp, arb_control3;
 937         fixed20_12 a, b, c;
 938
 939         if (radeon_crtc->base.enabled && num_heads && mode) {
 940                 pixel_period = 1000000 / (u32)mode->clock;
 941                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 942                 priority_a_cnt = 0;
 943                 priority_b_cnt = 0;
 944
 945                 wm.yclk = rdev->pm.current_mclk * 10;
 946                 wm.sclk = rdev->pm.current_sclk * 10;
 947                 wm.disp_clk = mode->clock;
 948                 wm.src_width = mode->crtc_hdisplay;
 949                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 950                 wm.blank_time = line_time - wm.active_time;
 951                 wm.interlaced = false;
 952                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 953                         wm.interlaced = true;
 954                 wm.vsc = radeon_crtc->vsc;
 955                 wm.vtaps = 1;
 956                 if (radeon_crtc->rmx_type != RMX_OFF)
 957                         wm.vtaps = 2;
 958                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 959                 wm.lb_size = lb_size;
 960                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 961                 wm.num_heads = num_heads;
 962
 963                 /* set for high clocks */
 964                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 965                 /* set for low clocks */
 966                 /* wm.yclk = low clk; wm.sclk = low clk */
 967                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 968
 969                 /* possibly force display priority to high */
 970                 /* should really do this at mode validation time... */
 971                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 972                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 973                     !evergreen_check_latency_hiding(&wm) ||
 974                     (rdev->disp_priority == 2)) {
 975                         DRM_DEBUG_KMS("force priority to high\n");
 976                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 977                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 978                 }
 979
 980                 a.full = dfixed_const(1000);
 981                 b.full = dfixed_const(mode->clock);
 982                 b.full = dfixed_div(b, a);
 983                 c.full = dfixed_const(latency_watermark_a);
 984                 c.full = dfixed_mul(c, b);
 985                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 986                 c.full = dfixed_div(c, a);
 987                 a.full = dfixed_const(16);
 988                 c.full = dfixed_div(c, a);
 989                 priority_a_mark = dfixed_trunc(c);
 990                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 991
 992                 a.full = dfixed_const(1000);
 993                 b.full = dfixed_const(mode->clock);
 994                 b.full = dfixed_div(b, a);
 995                 c.full = dfixed_const(latency_watermark_b);
 996                 c.full = dfixed_mul(c, b);
 997                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 998                 c.full = dfixed_div(c, a);
 999                 a.full = dfixed_const(16);
1000                 c.full = dfixed_div(c, a);
1001                 priority_b_mark = dfixed_trunc(c);
1002                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1003         }
1004
1005         /* select wm A */
1006         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1007         tmp = arb_control3;
1008         tmp &= ~LATENCY_WATERMARK_MASK(3);
1009         tmp |= LATENCY_WATERMARK_MASK(1);
1010         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1011         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1012                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1013                 LATENCY_HIGH_WATERMARK(line_time)));
1014         /* select wm B */
1015         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1016         tmp &= ~LATENCY_WATERMARK_MASK(3);
1017         tmp |= LATENCY_WATERMARK_MASK(2);
1018         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1019         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1020                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1021                 LATENCY_HIGH_WATERMARK(line_time)));
1022         /* restore original selection */
1023         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1024
1025         /* write the priority marks */
1026         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1027         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1028
1029 }
1030
1031 /**
1032  * evergreen_bandwidth_update - update display watermarks callback.
1033  *
1034  * @rdev: radeon_device pointer
1035  *
1036  * Update the display watermarks based on the requested mode(s)
1037  * (evergreen+).
1038  */
1039 void evergreen_bandwidth_update(struct radeon_device *rdev)
1040 {
1041         struct drm_display_mode *mode0 = NULL;
1042         struct drm_display_mode *mode1 = NULL;
1043         u32 num_heads = 0, lb_size;
1044         int i;
1045
1046         radeon_update_display_priority(rdev);
1047
1048         for (i = 0; i < rdev->num_crtc; i++) {
1049                 if (rdev->mode_info.crtcs[i]->base.enabled)
1050                         num_heads++;
1051         }
1052         for (i = 0; i < rdev->num_crtc; i += 2) {
1053                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1054                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1055                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1056                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1057                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1058                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1059         }
1060 }
1061
1062 /**
1063  * evergreen_mc_wait_for_idle - wait for MC idle callback.
1064  *
1065  * @rdev: radeon_device pointer
1066  *
1067  * Wait for the MC (memory controller) to be idle.
1068  * (evergreen+).
1069  * Returns 0 if the MC is idle, -1 if not.
1070  */
1071 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1072 {
1073         unsigned i;
1074         u32 tmp;
1075
1076         for (i = 0; i < rdev->usec_timeout; i++) {
1077                 /* read MC_STATUS */
1078                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1079                 if (!tmp)
1080                         return 0;
1081                 udelay(1);
1082         }
1083         return -1;
1084 }
1085
1086 /*
1087  * GART
1088  */
1089 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1090 {
1091         unsigned i;
1092         u32 tmp;
1093
1094         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1095
1096         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1097         for (i = 0; i < rdev->usec_timeout; i++) {
1098                 /* read MC_STATUS */
1099                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1100                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1101                 if (tmp == 2) {
1102                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1103                         return;
1104                 }
1105                 if (tmp) {
1106                         return;
1107                 }
1108                 udelay(1);
1109         }
1110 }
1111
1112 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1113 {
1114         u32 tmp;
1115         int r;
1116
1117         if (rdev->gart.robj == NULL) {
1118                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1119                 return -EINVAL;
1120         }
1121         r = radeon_gart_table_vram_pin(rdev);
1122         if (r)
1123                 return r;
1124         radeon_gart_restore(rdev);
1125         /* Setup L2 cache */
1126         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1127                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1128                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1129         WREG32(VM_L2_CNTL2, 0);
1130         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1131         /* Setup TLB control */
1132         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1133                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1134                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1135                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1136         if (rdev->flags & RADEON_IS_IGP) {
1137                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1138                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1139                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1140         } else {
1141                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1142                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1143                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1144                 if ((rdev->family == CHIP_JUNIPER) ||
1145                     (rdev->family == CHIP_CYPRESS) ||
1146                     (rdev->family == CHIP_HEMLOCK) ||
1147                     (rdev->family == CHIP_BARTS))
1148                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1149         }
1150         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1151         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1152         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1153         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1154         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1155         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1156         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1157         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1158                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1159         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1160                         (u32)(rdev->dummy_page.addr >> 12));
1161         WREG32(VM_CONTEXT1_CNTL, 0);
1162
1163         evergreen_pcie_gart_tlb_flush(rdev);
1164         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1165                  (unsigned)(rdev->mc.gtt_size >> 20),
1166                  (unsigned long long)rdev->gart.table_addr);
1167         rdev->gart.ready = true;
1168         return 0;
1169 }
1170
1171 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1172 {
1173         u32 tmp;
1174
1175         /* Disable all tables */
1176         WREG32(VM_CONTEXT0_CNTL, 0);
1177         WREG32(VM_CONTEXT1_CNTL, 0);
1178
1179         /* Setup L2 cache */
1180         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1181                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1182         WREG32(VM_L2_CNTL2, 0);
1183         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1184         /* Setup TLB control */
1185         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1186         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1187         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1188         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1189         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1190         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1191         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1192         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1193         radeon_gart_table_vram_unpin(rdev);
1194 }
1195
1196 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1197 {
1198         evergreen_pcie_gart_disable(rdev);
1199         radeon_gart_table_vram_free(rdev);
1200         radeon_gart_fini(rdev);
1201 }
1202
1203
1204 void evergreen_agp_enable(struct radeon_device *rdev)
1205 {
1206         u32 tmp;
1207
1208         /* Setup L2 cache */
1209         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1210                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1211                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1212         WREG32(VM_L2_CNTL2, 0);
1213         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1214         /* Setup TLB control */
1215         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1216                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1217                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1218                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1219         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1220         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1221         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1222         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1223         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1224         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1225         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1226         WREG32(VM_CONTEXT0_CNTL, 0);
1227         WREG32(VM_CONTEXT1_CNTL, 0);
1228 }
1229
1230 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1231 {
1232         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1233         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1234
1235         /* Stop all video */
1236         WREG32(VGA_RENDER_CONTROL, 0);
1237         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1238         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1239         if (rdev->num_crtc >= 4) {
1240                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1241                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1242         }
1243         if (rdev->num_crtc >= 6) {
1244                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1245                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1246         }
1247         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1248         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1249         if (rdev->num_crtc >= 4) {
1250                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1251                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1252         }
1253         if (rdev->num_crtc >= 6) {
1254                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1255                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1256         }
1257         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1258         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1259         if (rdev->num_crtc >= 4) {
1260                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1261                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1262         }
1263         if (rdev->num_crtc >= 6) {
1264                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1265                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1266         }
1267
1268         WREG32(D1VGA_CONTROL, 0);
1269         WREG32(D2VGA_CONTROL, 0);
1270         if (rdev->num_crtc >= 4) {
1271                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1272                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1273         }
1274         if (rdev->num_crtc >= 6) {
1275                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1276                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1277         }
1278 }
1279
1280 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1281 {
1282         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1283                upper_32_bits(rdev->mc.vram_start));
1284         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1285                upper_32_bits(rdev->mc.vram_start));
1286         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1287                (u32)rdev->mc.vram_start);
1288         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1289                (u32)rdev->mc.vram_start);
1290
1291         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1292                upper_32_bits(rdev->mc.vram_start));
1293         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1294                upper_32_bits(rdev->mc.vram_start));
1295         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1296                (u32)rdev->mc.vram_start);
1297         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1298                (u32)rdev->mc.vram_start);
1299
1300         if (rdev->num_crtc >= 4) {
1301                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1302                        upper_32_bits(rdev->mc.vram_start));
1303                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1304                        upper_32_bits(rdev->mc.vram_start));
1305                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1306                        (u32)rdev->mc.vram_start);
1307                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1308                        (u32)rdev->mc.vram_start);
1309
1310                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1311                        upper_32_bits(rdev->mc.vram_start));
1312                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1313                        upper_32_bits(rdev->mc.vram_start));
1314                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1315                        (u32)rdev->mc.vram_start);
1316                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1317                        (u32)rdev->mc.vram_start);
1318         }
1319         if (rdev->num_crtc >= 6) {
1320                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1321                        upper_32_bits(rdev->mc.vram_start));
1322                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1323                        upper_32_bits(rdev->mc.vram_start));
1324                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1325                        (u32)rdev->mc.vram_start);
1326                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1327                        (u32)rdev->mc.vram_start);
1328
1329                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1330                        upper_32_bits(rdev->mc.vram_start));
1331                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1332                        upper_32_bits(rdev->mc.vram_start));
1333                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1334                        (u32)rdev->mc.vram_start);
1335                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1336                        (u32)rdev->mc.vram_start);
1337         }
1338
1339         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1340         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1341         /* Unlock host access */
1342         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1343         mdelay(1);
1344         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1345 }
1346
1347 void evergreen_mc_program(struct radeon_device *rdev)
1348 {
1349         struct evergreen_mc_save save;
1350         u32 tmp;
1351         int i, j;
1352
1353         /* Initialize HDP */
1354         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1355                 WREG32((0x2c14 + j), 0x00000000);
1356                 WREG32((0x2c18 + j), 0x00000000);
1357                 WREG32((0x2c1c + j), 0x00000000);
1358                 WREG32((0x2c20 + j), 0x00000000);
1359                 WREG32((0x2c24 + j), 0x00000000);
1360         }
1361         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1362
1363         evergreen_mc_stop(rdev, &save);
1364         if (evergreen_mc_wait_for_idle(rdev)) {
1365                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1366         }
1367         /* Lockout access through VGA aperture*/
1368         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1369         /* Update configuration */
1370         if (rdev->flags & RADEON_IS_AGP) {
1371                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1372                         /* VRAM before AGP */
1373                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1374                                 rdev->mc.vram_start >> 12);
1375                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1376                                 rdev->mc.gtt_end >> 12);
1377                 } else {
1378                         /* VRAM after AGP */
1379                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1380                                 rdev->mc.gtt_start >> 12);
1381                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1382                                 rdev->mc.vram_end >> 12);
1383                 }
1384         } else {
1385                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1386                         rdev->mc.vram_start >> 12);
1387                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1388                         rdev->mc.vram_end >> 12);
1389         }
1390         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1391         /* llano/ontario only */
1392         if ((rdev->family == CHIP_PALM) ||
1393             (rdev->family == CHIP_SUMO) ||
1394             (rdev->family == CHIP_SUMO2)) {
1395                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1396                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1397                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1398                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1399         }
1400         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1401         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1402         WREG32(MC_VM_FB_LOCATION, tmp);
1403         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1404         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1405         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1406         if (rdev->flags & RADEON_IS_AGP) {
1407                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1408                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1409                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1410         } else {
1411                 WREG32(MC_VM_AGP_BASE, 0);
1412                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1413                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1414         }
1415         if (evergreen_mc_wait_for_idle(rdev)) {
1416                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1417         }
1418         evergreen_mc_resume(rdev, &save);
1419         /* we need to own VRAM, so turn off the VGA renderer here
1420          * to stop it overwriting our objects */
1421         rv515_vga_render_disable(rdev);
1422 }
1423
1424 /*
1425  * CP.
1426  */
1427 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1428 {
1429         struct radeon_ring *ring = &rdev->ring[ib->ring];
1430         u32 next_rptr;
1431
1432         /* set to DX10/11 mode */
1433         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1434         radeon_ring_write(ring, 1);
1435
1436         if (ring->rptr_save_reg) {
1437                 next_rptr = ring->wptr + 3 + 4;
1438                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1439                 radeon_ring_write(ring, ((ring->rptr_save_reg -
1440                                           PACKET3_SET_CONFIG_REG_START) >> 2));
1441                 radeon_ring_write(ring, next_rptr);
1442         } else if (rdev->wb.enabled) {
1443                 next_rptr = ring->wptr + 5 + 4;
1444                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1445                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1446                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1447                 radeon_ring_write(ring, next_rptr);
1448                 radeon_ring_write(ring, 0);
1449         }
1450
1451         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1452         radeon_ring_write(ring,
1453 #ifdef __BIG_ENDIAN
1454                           (2 << 0) |
1455 #endif
1456                           (ib->gpu_addr & 0xFFFFFFFC));
1457         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1458         radeon_ring_write(ring, ib->length_dw);
1459 }
1460
1461
1462 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1463 {
1464         const __be32 *fw_data;
1465         int i;
1466
1467         if (!rdev->me_fw || !rdev->pfp_fw)
1468                 return -EINVAL;
1469
1470         r700_cp_stop(rdev);
1471         WREG32(CP_RB_CNTL,
1472 #ifdef __BIG_ENDIAN
1473                BUF_SWAP_32BIT |
1474 #endif
1475                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1476
1477         fw_data = (const __be32 *)rdev->pfp_fw->data;
1478         WREG32(CP_PFP_UCODE_ADDR, 0);
1479         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1480                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1481         WREG32(CP_PFP_UCODE_ADDR, 0);
1482
1483         fw_data = (const __be32 *)rdev->me_fw->data;
1484         WREG32(CP_ME_RAM_WADDR, 0);
1485         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1486                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1487
1488         WREG32(CP_PFP_UCODE_ADDR, 0);
1489         WREG32(CP_ME_RAM_WADDR, 0);
1490         WREG32(CP_ME_RAM_RADDR, 0);
1491         return 0;
1492 }
1493
1494 static int evergreen_cp_start(struct radeon_device *rdev)
1495 {
1496         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1497         int r, i;
1498         uint32_t cp_me;
1499
1500         r = radeon_ring_lock(rdev, ring, 7);
1501         if (r) {
1502                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1503                 return r;
1504         }
1505         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1506         radeon_ring_write(ring, 0x1);
1507         radeon_ring_write(ring, 0x0);
1508         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1509         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1510         radeon_ring_write(ring, 0);
1511         radeon_ring_write(ring, 0);
1512         radeon_ring_unlock_commit(rdev, ring);
1513
1514         cp_me = 0xff;
1515         WREG32(CP_ME_CNTL, cp_me);
1516
1517         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1518         if (r) {
1519                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1520                 return r;
1521         }
1522
1523         /* setup clear context state */
1524         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1525         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1526
1527         for (i = 0; i < evergreen_default_size; i++)
1528                 radeon_ring_write(ring, evergreen_default_state[i]);
1529
1530         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1531         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1532
1533         /* set clear context state */
1534         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1535         radeon_ring_write(ring, 0);
1536
1537         /* SQ_VTX_BASE_VTX_LOC */
1538         radeon_ring_write(ring, 0xc0026f00);
1539         radeon_ring_write(ring, 0x00000000);
1540         radeon_ring_write(ring, 0x00000000);
1541         radeon_ring_write(ring, 0x00000000);
1542
1543         /* Clear consts */
1544         radeon_ring_write(ring, 0xc0036f00);
1545         radeon_ring_write(ring, 0x00000bc4);
1546         radeon_ring_write(ring, 0xffffffff);
1547         radeon_ring_write(ring, 0xffffffff);
1548         radeon_ring_write(ring, 0xffffffff);
1549
1550         radeon_ring_write(ring, 0xc0026900);
1551         radeon_ring_write(ring, 0x00000316);
1552         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1553         radeon_ring_write(ring, 0x00000010); /*  */
1554
1555         radeon_ring_unlock_commit(rdev, ring);
1556
1557         return 0;
1558 }
1559
1560 int evergreen_cp_resume(struct radeon_device *rdev)
1561 {
1562         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1563         u32 tmp;
1564         u32 rb_bufsz;
1565         int r;
1566
1567         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1568         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1569                                  SOFT_RESET_PA |
1570                                  SOFT_RESET_SH |
1571                                  SOFT_RESET_VGT |
1572                                  SOFT_RESET_SPI |
1573                                  SOFT_RESET_SX));
1574         RREG32(GRBM_SOFT_RESET);
1575         mdelay(15);
1576         WREG32(GRBM_SOFT_RESET, 0);
1577         RREG32(GRBM_SOFT_RESET);
1578
1579         /* Set ring buffer size */
1580         rb_bufsz = drm_order(ring->ring_size / 8);
1581         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1582 #ifdef __BIG_ENDIAN
1583         tmp |= BUF_SWAP_32BIT;
1584 #endif
1585         WREG32(CP_RB_CNTL, tmp);
1586         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1587         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1588
1589         /* Set the write pointer delay */
1590         WREG32(CP_RB_WPTR_DELAY, 0);
1591
1592         /* Initialize the ring buffer's read and write pointers */
1593         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1594         WREG32(CP_RB_RPTR_WR, 0);
1595         ring->wptr = 0;
1596         WREG32(CP_RB_WPTR, ring->wptr);
1597
1598         /* set the wb address wether it's enabled or not */
1599         WREG32(CP_RB_RPTR_ADDR,
1600                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1601         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1602         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1603
1604         if (rdev->wb.enabled)
1605                 WREG32(SCRATCH_UMSK, 0xff);
1606         else {
1607                 tmp |= RB_NO_UPDATE;
1608                 WREG32(SCRATCH_UMSK, 0);
1609         }
1610
1611         mdelay(1);
1612         WREG32(CP_RB_CNTL, tmp);
1613
1614         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1615         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1616
1617         ring->rptr = RREG32(CP_RB_RPTR);
1618
1619         evergreen_cp_start(rdev);
1620         ring->ready = true;
1621         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1622         if (r) {
1623                 ring->ready = false;
1624                 return r;
1625         }
1626         return 0;
1627 }
1628
1629 /*
1630  * Core functions
1631  */
1632 static void evergreen_gpu_init(struct radeon_device *rdev)
1633 {
1634         u32 gb_addr_config;
1635         u32 mc_shared_chmap, mc_arb_ramcfg;
1636         u32 sx_debug_1;
1637         u32 smx_dc_ctl0;
1638         u32 sq_config;
1639         u32 sq_lds_resource_mgmt;
1640         u32 sq_gpr_resource_mgmt_1;
1641         u32 sq_gpr_resource_mgmt_2;
1642         u32 sq_gpr_resource_mgmt_3;
1643         u32 sq_thread_resource_mgmt;
1644         u32 sq_thread_resource_mgmt_2;
1645         u32 sq_stack_resource_mgmt_1;
1646         u32 sq_stack_resource_mgmt_2;
1647         u32 sq_stack_resource_mgmt_3;
1648         u32 vgt_cache_invalidation;
1649         u32 hdp_host_path_cntl, tmp;
1650         u32 disabled_rb_mask;
1651         int i, j, num_shader_engines, ps_thread_count;
1652
1653         switch (rdev->family) {
1654         case CHIP_CYPRESS:
1655         case CHIP_HEMLOCK:
1656                 rdev->config.evergreen.num_ses = 2;
1657                 rdev->config.evergreen.max_pipes = 4;
1658                 rdev->config.evergreen.max_tile_pipes = 8;
1659                 rdev->config.evergreen.max_simds = 10;
1660                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1661                 rdev->config.evergreen.max_gprs = 256;
1662                 rdev->config.evergreen.max_threads = 248;
1663                 rdev->config.evergreen.max_gs_threads = 32;
1664                 rdev->config.evergreen.max_stack_entries = 512;
1665                 rdev->config.evergreen.sx_num_of_sets = 4;
1666                 rdev->config.evergreen.sx_max_export_size = 256;
1667                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1668                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1669                 rdev->config.evergreen.max_hw_contexts = 8;
1670                 rdev->config.evergreen.sq_num_cf_insts = 2;
1671
1672                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1673                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1674                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1675                 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1676                 break;
1677         case CHIP_JUNIPER:
1678                 rdev->config.evergreen.num_ses = 1;
1679                 rdev->config.evergreen.max_pipes = 4;
1680                 rdev->config.evergreen.max_tile_pipes = 4;
1681                 rdev->config.evergreen.max_simds = 10;
1682                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1683                 rdev->config.evergreen.max_gprs = 256;
1684                 rdev->config.evergreen.max_threads = 248;
1685                 rdev->config.evergreen.max_gs_threads = 32;
1686                 rdev->config.evergreen.max_stack_entries = 512;
1687                 rdev->config.evergreen.sx_num_of_sets = 4;
1688                 rdev->config.evergreen.sx_max_export_size = 256;
1689                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1690                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1691                 rdev->config.evergreen.max_hw_contexts = 8;
1692                 rdev->config.evergreen.sq_num_cf_insts = 2;
1693
1694                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1695                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1696                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1697                 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1698                 break;
1699         case CHIP_REDWOOD:
1700                 rdev->config.evergreen.num_ses = 1;
1701                 rdev->config.evergreen.max_pipes = 4;
1702                 rdev->config.evergreen.max_tile_pipes = 4;
1703                 rdev->config.evergreen.max_simds = 5;
1704                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1705                 rdev->config.evergreen.max_gprs = 256;
1706                 rdev->config.evergreen.max_threads = 248;
1707                 rdev->config.evergreen.max_gs_threads = 32;
1708                 rdev->config.evergreen.max_stack_entries = 256;
1709                 rdev->config.evergreen.sx_num_of_sets = 4;
1710                 rdev->config.evergreen.sx_max_export_size = 256;
1711                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1712                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1713                 rdev->config.evergreen.max_hw_contexts = 8;
1714                 rdev->config.evergreen.sq_num_cf_insts = 2;
1715
1716                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1717                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1718                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1719                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1720                 break;
1721         case CHIP_CEDAR:
1722         default:
1723                 rdev->config.evergreen.num_ses = 1;
1724                 rdev->config.evergreen.max_pipes = 2;
1725                 rdev->config.evergreen.max_tile_pipes = 2;
1726                 rdev->config.evergreen.max_simds = 2;
1727                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1728                 rdev->config.evergreen.max_gprs = 256;
1729                 rdev->config.evergreen.max_threads = 192;
1730                 rdev->config.evergreen.max_gs_threads = 16;
1731                 rdev->config.evergreen.max_stack_entries = 256;
1732                 rdev->config.evergreen.sx_num_of_sets = 4;
1733                 rdev->config.evergreen.sx_max_export_size = 128;
1734                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1735                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1736                 rdev->config.evergreen.max_hw_contexts = 4;
1737                 rdev->config.evergreen.sq_num_cf_insts = 1;
1738
1739                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1740                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1741                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1742                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1743                 break;
1744         case CHIP_PALM:
1745                 rdev->config.evergreen.num_ses = 1;
1746                 rdev->config.evergreen.max_pipes = 2;
1747                 rdev->config.evergreen.max_tile_pipes = 2;
1748                 rdev->config.evergreen.max_simds = 2;
1749                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1750                 rdev->config.evergreen.max_gprs = 256;
1751                 rdev->config.evergreen.max_threads = 192;
1752                 rdev->config.evergreen.max_gs_threads = 16;
1753                 rdev->config.evergreen.max_stack_entries = 256;
1754                 rdev->config.evergreen.sx_num_of_sets = 4;
1755                 rdev->config.evergreen.sx_max_export_size = 128;
1756                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1757                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1758                 rdev->config.evergreen.max_hw_contexts = 4;
1759                 rdev->config.evergreen.sq_num_cf_insts = 1;
1760
1761                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1762                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1763                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1764                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1765                 break;
1766         case CHIP_SUMO:
1767                 rdev->config.evergreen.num_ses = 1;
1768                 rdev->config.evergreen.max_pipes = 4;
1769                 rdev->config.evergreen.max_tile_pipes = 2;
1770                 if (rdev->pdev->device == 0x9648)
1771                         rdev->config.evergreen.max_simds = 3;
1772                 else if ((rdev->pdev->device == 0x9647) ||
1773                          (rdev->pdev->device == 0x964a))
1774                         rdev->config.evergreen.max_simds = 4;
1775                 else
1776                         rdev->config.evergreen.max_simds = 5;
1777                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1778                 rdev->config.evergreen.max_gprs = 256;
1779                 rdev->config.evergreen.max_threads = 248;
1780                 rdev->config.evergreen.max_gs_threads = 32;
1781                 rdev->config.evergreen.max_stack_entries = 256;
1782                 rdev->config.evergreen.sx_num_of_sets = 4;
1783                 rdev->config.evergreen.sx_max_export_size = 256;
1784                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1785                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1786                 rdev->config.evergreen.max_hw_contexts = 8;
1787                 rdev->config.evergreen.sq_num_cf_insts = 2;
1788
1789                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1790                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1791                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1792                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1793                 break;
1794         case CHIP_SUMO2:
1795                 rdev->config.evergreen.num_ses = 1;
1796                 rdev->config.evergreen.max_pipes = 4;
1797                 rdev->config.evergreen.max_tile_pipes = 4;
1798                 rdev->config.evergreen.max_simds = 2;
1799                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1800                 rdev->config.evergreen.max_gprs = 256;
1801                 rdev->config.evergreen.max_threads = 248;
1802                 rdev->config.evergreen.max_gs_threads = 32;
1803                 rdev->config.evergreen.max_stack_entries = 512;
1804                 rdev->config.evergreen.sx_num_of_sets = 4;
1805                 rdev->config.evergreen.sx_max_export_size = 256;
1806                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1807                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1808                 rdev->config.evergreen.max_hw_contexts = 8;
1809                 rdev->config.evergreen.sq_num_cf_insts = 2;
1810
1811                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1812                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1813                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1814                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1815                 break;
1816         case CHIP_BARTS:
1817                 rdev->config.evergreen.num_ses = 2;
1818                 rdev->config.evergreen.max_pipes = 4;
1819                 rdev->config.evergreen.max_tile_pipes = 8;
1820                 rdev->config.evergreen.max_simds = 7;
1821                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1822                 rdev->config.evergreen.max_gprs = 256;
1823                 rdev->config.evergreen.max_threads = 248;
1824                 rdev->config.evergreen.max_gs_threads = 32;
1825                 rdev->config.evergreen.max_stack_entries = 512;
1826                 rdev->config.evergreen.sx_num_of_sets = 4;
1827                 rdev->config.evergreen.sx_max_export_size = 256;
1828                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1829                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1830                 rdev->config.evergreen.max_hw_contexts = 8;
1831                 rdev->config.evergreen.sq_num_cf_insts = 2;
1832
1833                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1834                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1835                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1836                 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1837                 break;
1838         case CHIP_TURKS:
1839                 rdev->config.evergreen.num_ses = 1;
1840                 rdev->config.evergreen.max_pipes = 4;
1841                 rdev->config.evergreen.max_tile_pipes = 4;
1842                 rdev->config.evergreen.max_simds = 6;
1843                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1844                 rdev->config.evergreen.max_gprs = 256;
1845                 rdev->config.evergreen.max_threads = 248;
1846                 rdev->config.evergreen.max_gs_threads = 32;
1847                 rdev->config.evergreen.max_stack_entries = 256;
1848                 rdev->config.evergreen.sx_num_of_sets = 4;
1849                 rdev->config.evergreen.sx_max_export_size = 256;
1850                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1851                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1852                 rdev->config.evergreen.max_hw_contexts = 8;
1853                 rdev->config.evergreen.sq_num_cf_insts = 2;
1854
1855                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1856                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1857                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1858                 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1859                 break;
1860         case CHIP_CAICOS:
1861                 rdev->config.evergreen.num_ses = 1;
1862                 rdev->config.evergreen.max_pipes = 4;
1863                 rdev->config.evergreen.max_tile_pipes = 2;
1864                 rdev->config.evergreen.max_simds = 2;
1865                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1866                 rdev->config.evergreen.max_gprs = 256;
1867                 rdev->config.evergreen.max_threads = 192;
1868                 rdev->config.evergreen.max_gs_threads = 16;
1869                 rdev->config.evergreen.max_stack_entries = 256;
1870                 rdev->config.evergreen.sx_num_of_sets = 4;
1871                 rdev->config.evergreen.sx_max_export_size = 128;
1872                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1873                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1874                 rdev->config.evergreen.max_hw_contexts = 4;
1875                 rdev->config.evergreen.sq_num_cf_insts = 1;
1876
1877                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1878                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1879                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1880                 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1881                 break;
1882         }
1883
1884         /* Initialize HDP */
1885         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1886                 WREG32((0x2c14 + j), 0x00000000);
1887                 WREG32((0x2c18 + j), 0x00000000);
1888                 WREG32((0x2c1c + j), 0x00000000);
1889                 WREG32((0x2c20 + j), 0x00000000);
1890                 WREG32((0x2c24 + j), 0x00000000);
1891         }
1892
1893         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1894
1895         evergreen_fix_pci_max_read_req_size(rdev);
1896
1897         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1898         if ((rdev->family == CHIP_PALM) ||
1899             (rdev->family == CHIP_SUMO) ||
1900             (rdev->family == CHIP_SUMO2))
1901                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1902         else
1903                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1904
1905         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1906          * not have bank info, so create a custom tiling dword.
1907          * bits 3:0   num_pipes
1908          * bits 7:4   num_banks
1909          * bits 11:8  group_size
1910          * bits 15:12 row_size
1911          */
1912         rdev->config.evergreen.tile_config = 0;
1913         switch (rdev->config.evergreen.max_tile_pipes) {
1914         case 1:
1915         default:
1916                 rdev->config.evergreen.tile_config |= (0 << 0);
1917                 break;
1918         case 2:
1919                 rdev->config.evergreen.tile_config |= (1 << 0);
1920                 break;
1921         case 4:
1922                 rdev->config.evergreen.tile_config |= (2 << 0);
1923                 break;
1924         case 8:
1925                 rdev->config.evergreen.tile_config |= (3 << 0);
1926                 break;
1927         }
1928         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1929         if (rdev->flags & RADEON_IS_IGP)
1930                 rdev->config.evergreen.tile_config |= 1 << 4;
1931         else {
1932                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1933                 case 0: /* four banks */
1934                         rdev->config.evergreen.tile_config |= 0 << 4;
1935                         break;
1936                 case 1: /* eight banks */
1937                         rdev->config.evergreen.tile_config |= 1 << 4;
1938                         break;
1939                 case 2: /* sixteen banks */
1940                 default:
1941                         rdev->config.evergreen.tile_config |= 2 << 4;
1942                         break;
1943                 }
1944         }
1945         rdev->config.evergreen.tile_config |= 0 << 8;
1946         rdev->config.evergreen.tile_config |=
1947                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1948
1949         num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
1950
1951         if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
1952                 u32 efuse_straps_4;
1953                 u32 efuse_straps_3;
1954
1955                 WREG32(RCU_IND_INDEX, 0x204);
1956                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1957                 WREG32(RCU_IND_INDEX, 0x203);
1958                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1959                 tmp = (((efuse_straps_4 & 0xf) << 4) |
1960                       ((efuse_straps_3 & 0xf0000000) >> 28));
1961         } else {
1962                 tmp = 0;
1963                 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
1964                         u32 rb_disable_bitmap;
1965
1966                         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1967                         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1968                         rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1969                         tmp <<= 4;
1970                         tmp |= rb_disable_bitmap;
1971                 }
1972         }
1973         /* enabled rb are just the one not disabled :) */
1974         disabled_rb_mask = tmp;
1975
1976         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1977         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1978
1979         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1980         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1981         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1982
1983         tmp = gb_addr_config & NUM_PIPES_MASK;
1984         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
1985                                         EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
1986         WREG32(GB_BACKEND_MAP, tmp);
1987
1988         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1989         WREG32(CGTS_TCC_DISABLE, 0);
1990         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1991         WREG32(CGTS_USER_TCC_DISABLE, 0);
1992
1993         /* set HW defaults for 3D engine */
1994         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1995                                      ROQ_IB2_START(0x2b)));
1996
1997         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1998
1999         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2000                              SYNC_GRADIENT |
2001                              SYNC_WALKER |
2002                              SYNC_ALIGNER));
2003
2004         sx_debug_1 = RREG32(SX_DEBUG_1);
2005         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2006         WREG32(SX_DEBUG_1, sx_debug_1);
2007
2008
2009         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2010         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2011         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2012         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2013
2014         if (rdev->family <= CHIP_SUMO2)
2015                 WREG32(SMX_SAR_CTL0, 0x00010000);
2016
2017         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2018                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2019                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2020
2021         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2022                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2023                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2024
2025         WREG32(VGT_NUM_INSTANCES, 1);
2026         WREG32(SPI_CONFIG_CNTL, 0);
2027         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2028         WREG32(CP_PERFMON_CNTL, 0);
2029
2030         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2031                                   FETCH_FIFO_HIWATER(0x4) |
2032                                   DONE_FIFO_HIWATER(0xe0) |
2033                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2034
2035         sq_config = RREG32(SQ_CONFIG);
2036         sq_config &= ~(PS_PRIO(3) |
2037                        VS_PRIO(3) |
2038                        GS_PRIO(3) |
2039                        ES_PRIO(3));
2040         sq_config |= (VC_ENABLE |
2041                       EXPORT_SRC_C |
2042                       PS_PRIO(0) |
2043                       VS_PRIO(1) |
2044                       GS_PRIO(2) |
2045                       ES_PRIO(3));
2046
2047         switch (rdev->family) {
2048         case CHIP_CEDAR:
2049         case CHIP_PALM:
2050         case CHIP_SUMO:
2051         case CHIP_SUMO2:
2052         case CHIP_CAICOS:
2053                 /* no vertex cache */
2054                 sq_config &= ~VC_ENABLE;
2055                 break;
2056         default:
2057                 break;
2058         }
2059
2060         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2061
2062         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2063         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2064         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2065         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2066         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2067         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2068         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2069
2070         switch (rdev->family) {
2071         case CHIP_CEDAR:
2072         case CHIP_PALM:
2073         case CHIP_SUMO:
2074         case CHIP_SUMO2:
2075                 ps_thread_count = 96;
2076                 break;
2077         default:
2078                 ps_thread_count = 128;
2079                 break;
2080         }
2081
2082         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2083         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2084         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2085         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2086         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2087         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2088
2089         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2090         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2091         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2092         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2093         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2094         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2095
2096         WREG32(SQ_CONFIG, sq_config);
2097         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2098         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2099         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2100         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2101         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2102         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2103         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2104         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2105         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2106         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2107
2108         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2109                                           FORCE_EOV_MAX_REZ_CNT(255)));
2110
2111         switch (rdev->family) {
2112         case CHIP_CEDAR:
2113         case CHIP_PALM:
2114         case CHIP_SUMO:
2115         case CHIP_SUMO2:
2116         case CHIP_CAICOS:
2117                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2118                 break;
2119         default:
2120                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2121                 break;
2122         }
2123         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2124         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2125
2126         WREG32(VGT_GS_VERTEX_REUSE, 16);
2127         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2128         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2129
2130         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2131         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2132
2133         WREG32(CB_PERF_CTR0_SEL_0, 0);
2134         WREG32(CB_PERF_CTR0_SEL_1, 0);
2135         WREG32(CB_PERF_CTR1_SEL_0, 0);
2136         WREG32(CB_PERF_CTR1_SEL_1, 0);
2137         WREG32(CB_PERF_CTR2_SEL_0, 0);
2138         WREG32(CB_PERF_CTR2_SEL_1, 0);
2139         WREG32(CB_PERF_CTR3_SEL_0, 0);
2140         WREG32(CB_PERF_CTR3_SEL_1, 0);
2141
2142         /* clear render buffer base addresses */
2143         WREG32(CB_COLOR0_BASE, 0);
2144         WREG32(CB_COLOR1_BASE, 0);
2145         WREG32(CB_COLOR2_BASE, 0);
2146         WREG32(CB_COLOR3_BASE, 0);
2147         WREG32(CB_COLOR4_BASE, 0);
2148         WREG32(CB_COLOR5_BASE, 0);
2149         WREG32(CB_COLOR6_BASE, 0);
2150         WREG32(CB_COLOR7_BASE, 0);
2151         WREG32(CB_COLOR8_BASE, 0);
2152         WREG32(CB_COLOR9_BASE, 0);
2153         WREG32(CB_COLOR10_BASE, 0);
2154         WREG32(CB_COLOR11_BASE, 0);
2155
2156         /* set the shader const cache sizes to 0 */
2157         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2158                 WREG32(i, 0);
2159         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2160                 WREG32(i, 0);
2161
2162         tmp = RREG32(HDP_MISC_CNTL);
2163         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2164         WREG32(HDP_MISC_CNTL, tmp);
2165
2166         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2167         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2168
2169         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2170
2171         udelay(50);
2172
2173 }
2174
2175 int evergreen_mc_init(struct radeon_device *rdev)
2176 {
2177         u32 tmp;
2178         int chansize, numchan;
2179
2180         /* Get VRAM informations */
2181         rdev->mc.vram_is_ddr = true;
2182         if ((rdev->family == CHIP_PALM) ||
2183             (rdev->family == CHIP_SUMO) ||
2184             (rdev->family == CHIP_SUMO2))
2185                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2186         else
2187                 tmp = RREG32(MC_ARB_RAMCFG);
2188         if (tmp & CHANSIZE_OVERRIDE) {
2189                 chansize = 16;
2190         } else if (tmp & CHANSIZE_MASK) {
2191                 chansize = 64;
2192         } else {
2193                 chansize = 32;
2194         }
2195         tmp = RREG32(MC_SHARED_CHMAP);
2196         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2197         case 0:
2198         default:
2199                 numchan = 1;
2200                 break;
2201         case 1:
2202                 numchan = 2;
2203                 break;
2204         case 2:
2205                 numchan = 4;
2206                 break;
2207         case 3:
2208                 numchan = 8;
2209                 break;
2210         }
2211         rdev->mc.vram_width = numchan * chansize;
2212         /* Could aper size report 0 ? */
2213         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2214         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2215         /* Setup GPU memory space */
2216         if ((rdev->family == CHIP_PALM) ||
2217             (rdev->family == CHIP_SUMO) ||
2218             (rdev->family == CHIP_SUMO2)) {
2219                 /* size in bytes on fusion */
2220                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2221                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2222         } else {
2223                 /* size in MB on evergreen/cayman/tn */
2224                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2225                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2226         }
2227         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2228         r700_vram_gtt_location(rdev, &rdev->mc);
2229         radeon_update_bandwidth_info(rdev);
2230
2231         return 0;
2232 }
2233
2234 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2235 {
2236         u32 srbm_status;
2237         u32 grbm_status;
2238         u32 grbm_status_se0, grbm_status_se1;
2239
2240         srbm_status = RREG32(SRBM_STATUS);
2241         grbm_status = RREG32(GRBM_STATUS);
2242         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2243         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2244         if (!(grbm_status & GUI_ACTIVE)) {
2245                 radeon_ring_lockup_update(ring);
2246                 return false;
2247         }
2248         /* force CP activities */
2249         radeon_ring_force_activity(rdev, ring);
2250         return radeon_ring_test_lockup(rdev, ring);
2251 }
2252
2253 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2254 {
2255         struct evergreen_mc_save save;
2256         u32 grbm_reset = 0;
2257
2258         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2259                 return 0;
2260
2261         dev_info(rdev->dev, "GPU softreset \n");
2262         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2263                 RREG32(GRBM_STATUS));
2264         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2265                 RREG32(GRBM_STATUS_SE0));
2266         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2267                 RREG32(GRBM_STATUS_SE1));
2268         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2269                 RREG32(SRBM_STATUS));
2270         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2271                 RREG32(CP_STALLED_STAT1));
2272         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2273                 RREG32(CP_STALLED_STAT2));
2274         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2275                 RREG32(CP_BUSY_STAT));
2276         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2277                 RREG32(CP_STAT));
2278         evergreen_mc_stop(rdev, &save);
2279         if (evergreen_mc_wait_for_idle(rdev)) {
2280                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2281         }
2282         /* Disable CP parsing/prefetching */
2283         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2284
2285         /* reset all the gfx blocks */
2286         grbm_reset = (SOFT_RESET_CP |
2287                       SOFT_RESET_CB |
2288                       SOFT_RESET_DB |
2289                       SOFT_RESET_PA |
2290                       SOFT_RESET_SC |
2291                       SOFT_RESET_SPI |
2292                       SOFT_RESET_SH |
2293                       SOFT_RESET_SX |
2294                       SOFT_RESET_TC |
2295                       SOFT_RESET_TA |
2296                       SOFT_RESET_VC |
2297                       SOFT_RESET_VGT);
2298
2299         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2300         WREG32(GRBM_SOFT_RESET, grbm_reset);
2301         (void)RREG32(GRBM_SOFT_RESET);
2302         udelay(50);
2303         WREG32(GRBM_SOFT_RESET, 0);
2304         (void)RREG32(GRBM_SOFT_RESET);
2305         /* Wait a little for things to settle down */
2306         udelay(50);
2307         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2308                 RREG32(GRBM_STATUS));
2309         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2310                 RREG32(GRBM_STATUS_SE0));
2311         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2312                 RREG32(GRBM_STATUS_SE1));
2313         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2314                 RREG32(SRBM_STATUS));
2315         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2316                 RREG32(CP_STALLED_STAT1));
2317         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2318                 RREG32(CP_STALLED_STAT2));
2319         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2320                 RREG32(CP_BUSY_STAT));
2321         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2322                 RREG32(CP_STAT));
2323         evergreen_mc_resume(rdev, &save);
2324         return 0;
2325 }
2326
2327 int evergreen_asic_reset(struct radeon_device *rdev)
2328 {
2329         return evergreen_gpu_soft_reset(rdev);
2330 }
2331
2332 /* Interrupts */
2333
2334 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2335 {
2336         switch (crtc) {
2337         case 0:
2338                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2339         case 1:
2340                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2341         case 2:
2342                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2343         case 3:
2344                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2345         case 4:
2346                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2347         case 5:
2348                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2349         default:
2350                 return 0;
2351         }
2352 }
2353
2354 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2355 {
2356         u32 tmp;
2357
2358         if (rdev->family >= CHIP_CAYMAN) {
2359                 cayman_cp_int_cntl_setup(rdev, 0,
2360                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2361                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2362                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2363         } else
2364                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2365         WREG32(GRBM_INT_CNTL, 0);
2366         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2367         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2368         if (rdev->num_crtc >= 4) {
2369                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2370                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2371         }
2372         if (rdev->num_crtc >= 6) {
2373                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2374                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2375         }
2376
2377         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2378         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2379         if (rdev->num_crtc >= 4) {
2380                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2381                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2382         }
2383         if (rdev->num_crtc >= 6) {
2384                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2385                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2386         }
2387
2388         /* only one DAC on DCE6 */
2389         if (!ASIC_IS_DCE6(rdev))
2390                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2391         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2392
2393         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2394         WREG32(DC_HPD1_INT_CONTROL, tmp);
2395         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2396         WREG32(DC_HPD2_INT_CONTROL, tmp);
2397         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2398         WREG32(DC_HPD3_INT_CONTROL, tmp);
2399         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2400         WREG32(DC_HPD4_INT_CONTROL, tmp);
2401         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2402         WREG32(DC_HPD5_INT_CONTROL, tmp);
2403         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2404         WREG32(DC_HPD6_INT_CONTROL, tmp);
2405
2406 }
2407
2408 int evergreen_irq_set(struct radeon_device *rdev)
2409 {
2410         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2411         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2412         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2413         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2414         u32 grbm_int_cntl = 0;
2415         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2416         u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2417
2418         if (!rdev->irq.installed) {
2419                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2420                 return -EINVAL;
2421         }
2422         /* don't enable anything if the ih is disabled */
2423         if (!rdev->ih.enabled) {
2424                 r600_disable_interrupts(rdev);
2425                 /* force the active interrupt state to all disabled */
2426                 evergreen_disable_interrupt_state(rdev);
2427                 return 0;
2428         }
2429
2430         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2431         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2432         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2433         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2434         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2435         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2436
2437         afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2438         afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2439         afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2440         afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2441         afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2442         afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2443
2444         if (rdev->family >= CHIP_CAYMAN) {
2445                 /* enable CP interrupts on all rings */
2446                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2447                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2448                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2449                 }
2450                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2451                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2452                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2453                 }
2454                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2455                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2456                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2457                 }
2458         } else {
2459                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2460                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2461                         cp_int_cntl |= RB_INT_ENABLE;
2462                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2463                 }
2464         }
2465
2466         if (rdev->irq.crtc_vblank_int[0] ||
2467             atomic_read(&rdev->irq.pflip[0])) {
2468                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2469                 crtc1 |= VBLANK_INT_MASK;
2470         }
2471         if (rdev->irq.crtc_vblank_int[1] ||
2472             atomic_read(&rdev->irq.pflip[1])) {
2473                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2474                 crtc2 |= VBLANK_INT_MASK;
2475         }
2476         if (rdev->irq.crtc_vblank_int[2] ||
2477             atomic_read(&rdev->irq.pflip[2])) {
2478                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2479                 crtc3 |= VBLANK_INT_MASK;
2480         }
2481         if (rdev->irq.crtc_vblank_int[3] ||
2482             atomic_read(&rdev->irq.pflip[3])) {
2483                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2484                 crtc4 |= VBLANK_INT_MASK;
2485         }
2486         if (rdev->irq.crtc_vblank_int[4] ||
2487             atomic_read(&rdev->irq.pflip[4])) {
2488                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2489                 crtc5 |= VBLANK_INT_MASK;
2490         }
2491         if (rdev->irq.crtc_vblank_int[5] ||
2492             atomic_read(&rdev->irq.pflip[5])) {
2493                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2494                 crtc6 |= VBLANK_INT_MASK;
2495         }
2496         if (rdev->irq.hpd[0]) {
2497                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2498                 hpd1 |= DC_HPDx_INT_EN;
2499         }
2500         if (rdev->irq.hpd[1]) {
2501                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2502                 hpd2 |= DC_HPDx_INT_EN;
2503         }
2504         if (rdev->irq.hpd[2]) {
2505                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2506                 hpd3 |= DC_HPDx_INT_EN;
2507         }
2508         if (rdev->irq.hpd[3]) {
2509                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2510                 hpd4 |= DC_HPDx_INT_EN;
2511         }
2512         if (rdev->irq.hpd[4]) {
2513                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2514                 hpd5 |= DC_HPDx_INT_EN;
2515         }
2516         if (rdev->irq.hpd[5]) {
2517                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2518                 hpd6 |= DC_HPDx_INT_EN;
2519         }
2520         if (rdev->irq.afmt[0]) {
2521                 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2522                 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2523         }
2524         if (rdev->irq.afmt[1]) {
2525                 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2526                 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2527         }
2528         if (rdev->irq.afmt[2]) {
2529                 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2530                 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2531         }
2532         if (rdev->irq.afmt[3]) {
2533                 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2534                 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2535         }
2536         if (rdev->irq.afmt[4]) {
2537                 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2538                 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2539         }
2540         if (rdev->irq.afmt[5]) {
2541                 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2542                 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2543         }
2544         if (rdev->irq.gui_idle) {
2545                 DRM_DEBUG("gui idle\n");
2546                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2547         }
2548
2549         if (rdev->family >= CHIP_CAYMAN) {
2550                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2551                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2552                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2553         } else
2554                 WREG32(CP_INT_CNTL, cp_int_cntl);
2555         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2556
2557         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2558         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2559         if (rdev->num_crtc >= 4) {
2560                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2561                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2562         }
2563         if (rdev->num_crtc >= 6) {
2564                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2565                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2566         }
2567
2568         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2569         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2570         if (rdev->num_crtc >= 4) {
2571                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2572                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2573         }
2574         if (rdev->num_crtc >= 6) {
2575                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2576                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2577         }
2578
2579         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2580         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2581         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2582         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2583         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2584         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2585
2586         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2587         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2588         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2589         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2590         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2591         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2592
2593         return 0;
2594 }
2595
2596 static void evergreen_irq_ack(struct radeon_device *rdev)
2597 {
2598         u32 tmp;
2599
2600         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2601         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2602         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2603         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2604         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2605         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2606         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2607         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2608         if (rdev->num_crtc >= 4) {
2609                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2610                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2611         }
2612         if (rdev->num_crtc >= 6) {
2613                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2614                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2615         }
2616
2617         rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2618         rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2619         rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2620         rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2621         rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2622         rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2623
2624         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2625                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2626         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2627                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2628         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2629                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2630         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2631                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2632         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2633                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2634         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2635                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2636
2637         if (rdev->num_crtc >= 4) {
2638                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2639                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2640                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2641                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2642                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2643                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2644                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2645                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2646                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2647                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2648                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2649                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2650         }
2651
2652         if (rdev->num_crtc >= 6) {
2653                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2654                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2655                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2656                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2657                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2658                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2659                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2660                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2661                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2662                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2663                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2664                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2665         }
2666
2667         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2668                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2669                 tmp |= DC_HPDx_INT_ACK;
2670                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2671         }
2672         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2673                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2674                 tmp |= DC_HPDx_INT_ACK;
2675                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2676         }
2677         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2678                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2679                 tmp |= DC_HPDx_INT_ACK;
2680                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2681         }
2682         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2683                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2684                 tmp |= DC_HPDx_INT_ACK;
2685                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2686         }
2687         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2688                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2689                 tmp |= DC_HPDx_INT_ACK;
2690                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2691         }
2692         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2693                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2694                 tmp |= DC_HPDx_INT_ACK;
2695                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2696         }
2697         if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2698                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2699                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2700                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2701         }
2702         if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2703                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2704                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2705                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2706         }
2707         if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2708                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2709                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2710                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2711         }
2712         if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2713                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2714                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2715                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2716         }
2717         if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2718                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2719                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2720                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2721         }
2722         if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2723                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2724                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2725                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2726         }
2727 }
2728
2729 void evergreen_irq_disable(struct radeon_device *rdev)
2730 {
2731         r600_disable_interrupts(rdev);
2732         /* Wait and acknowledge irq */
2733         mdelay(1);
2734         evergreen_irq_ack(rdev);
2735         evergreen_disable_interrupt_state(rdev);
2736 }
2737
2738 void evergreen_irq_suspend(struct radeon_device *rdev)
2739 {
2740         evergreen_irq_disable(rdev);
2741         r600_rlc_stop(rdev);
2742 }
2743
2744 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2745 {
2746         u32 wptr, tmp;
2747
2748         if (rdev->wb.enabled)
2749                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2750         else
2751                 wptr = RREG32(IH_RB_WPTR);
2752
2753         if (wptr & RB_OVERFLOW) {
2754                 /* When a ring buffer overflow happen start parsing interrupt
2755                  * from the last not overwritten vector (wptr + 16). Hopefully
2756                  * this should allow us to catchup.
2757                  */
2758                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2759                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2760                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2761                 tmp = RREG32(IH_RB_CNTL);
2762                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2763                 WREG32(IH_RB_CNTL, tmp);
2764         }
2765         return (wptr & rdev->ih.ptr_mask);
2766 }
2767
2768 int evergreen_irq_process(struct radeon_device *rdev)
2769 {
2770         u32 wptr;
2771         u32 rptr;
2772         u32 src_id, src_data;
2773         u32 ring_index;
2774         bool queue_hotplug = false;
2775         bool queue_hdmi = false;
2776
2777         if (!rdev->ih.enabled || rdev->shutdown)
2778                 return IRQ_NONE;
2779
2780         wptr = evergreen_get_ih_wptr(rdev);
2781
2782 restart_ih:
2783         /* is somebody else already processing irqs? */
2784         if (atomic_xchg(&rdev->ih.lock, 1))
2785                 return IRQ_NONE;
2786
2787         rptr = rdev->ih.rptr;
2788         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2789
2790         /* Order reading of wptr vs. reading of IH ring data */
2791         rmb();
2792
2793         /* display interrupts */
2794         evergreen_irq_ack(rdev);
2795
2796         while (rptr != wptr) {
2797                 /* wptr/rptr are in bytes! */
2798                 ring_index = rptr / 4;
2799                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2800                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2801
2802                 switch (src_id) {
2803                 case 1: /* D1 vblank/vline */
2804                         switch (src_data) {
2805                         case 0: /* D1 vblank */
2806                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2807                                         if (rdev->irq.crtc_vblank_int[0]) {
2808                                                 drm_handle_vblank(rdev->ddev, 0);
2809                                                 rdev->pm.vblank_sync = true;
2810                                                 wake_up(&rdev->irq.vblank_queue);
2811                                         }
2812                                         if (atomic_read(&rdev->irq.pflip[0]))
2813                                                 radeon_crtc_handle_flip(rdev, 0);
2814                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2815                                         DRM_DEBUG("IH: D1 vblank\n");
2816                                 }
2817                                 break;
2818                         case 1: /* D1 vline */
2819                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2820                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2821                                         DRM_DEBUG("IH: D1 vline\n");
2822                                 }
2823                                 break;
2824                         default:
2825                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2826                                 break;
2827                         }
2828                         break;
2829                 case 2: /* D2 vblank/vline */
2830                         switch (src_data) {
2831                         case 0: /* D2 vblank */
2832                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2833                                         if (rdev->irq.crtc_vblank_int[1]) {
2834                                                 drm_handle_vblank(rdev->ddev, 1);
2835                                                 rdev->pm.vblank_sync = true;
2836                                                 wake_up(&rdev->irq.vblank_queue);
2837                                         }
2838                                         if (atomic_read(&rdev->irq.pflip[1]))
2839                                                 radeon_crtc_handle_flip(rdev, 1);
2840                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2841                                         DRM_DEBUG("IH: D2 vblank\n");
2842                                 }
2843                                 break;
2844                         case 1: /* D2 vline */
2845                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2846                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2847                                         DRM_DEBUG("IH: D2 vline\n");
2848                                 }
2849                                 break;
2850                         default:
2851                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2852                                 break;
2853                         }
2854                         break;
2855                 case 3: /* D3 vblank/vline */
2856                         switch (src_data) {
2857                         case 0: /* D3 vblank */
2858                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2859                                         if (rdev->irq.crtc_vblank_int[2]) {
2860                                                 drm_handle_vblank(rdev->ddev, 2);
2861                                                 rdev->pm.vblank_sync = true;
2862                                                 wake_up(&rdev->irq.vblank_queue);
2863                                         }
2864                                         if (atomic_read(&rdev->irq.pflip[2]))
2865                                                 radeon_crtc_handle_flip(rdev, 2);
2866                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2867                                         DRM_DEBUG("IH: D3 vblank\n");
2868                                 }
2869                                 break;
2870                         case 1: /* D3 vline */
2871                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2872                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2873                                         DRM_DEBUG("IH: D3 vline\n");
2874                                 }
2875                                 break;
2876                         default:
2877                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2878                                 break;
2879                         }
2880                         break;
2881                 case 4: /* D4 vblank/vline */
2882                         switch (src_data) {
2883                         case 0: /* D4 vblank */
2884                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2885                                         if (rdev->irq.crtc_vblank_int[3]) {
2886                                                 drm_handle_vblank(rdev->ddev, 3);
2887                                                 rdev->pm.vblank_sync = true;
2888                                                 wake_up(&rdev->irq.vblank_queue);
2889                                         }
2890                                         if (atomic_read(&rdev->irq.pflip[3]))
2891                                                 radeon_crtc_handle_flip(rdev, 3);
2892                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2893                                         DRM_DEBUG("IH: D4 vblank\n");
2894                                 }
2895                                 break;
2896                         case 1: /* D4 vline */
2897                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2898                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2899                                         DRM_DEBUG("IH: D4 vline\n");
2900                                 }
2901                                 break;
2902                         default:
2903                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2904                                 break;
2905                         }
2906                         break;
2907                 case 5: /* D5 vblank/vline */
2908                         switch (src_data) {
2909                         case 0: /* D5 vblank */
2910                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2911                                         if (rdev->irq.crtc_vblank_int[4]) {
2912                                                 drm_handle_vblank(rdev->ddev, 4);
2913                                                 rdev->pm.vblank_sync = true;
2914                                                 wake_up(&rdev->irq.vblank_queue);
2915                                         }
2916                                         if (atomic_read(&rdev->irq.pflip[4]))
2917                                                 radeon_crtc_handle_flip(rdev, 4);
2918                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2919                                         DRM_DEBUG("IH: D5 vblank\n");
2920                                 }
2921                                 break;
2922                         case 1: /* D5 vline */
2923                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2924                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2925                                         DRM_DEBUG("IH: D5 vline\n");
2926                                 }
2927                                 break;
2928                         default:
2929                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2930                                 break;
2931                         }
2932                         break;
2933                 case 6: /* D6 vblank/vline */
2934                         switch (src_data) {
2935                         case 0: /* D6 vblank */
2936                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2937                                         if (rdev->irq.crtc_vblank_int[5]) {
2938                                                 drm_handle_vblank(rdev->ddev, 5);
2939                                                 rdev->pm.vblank_sync = true;
2940                                                 wake_up(&rdev->irq.vblank_queue);
2941                                         }
2942                                         if (atomic_read(&rdev->irq.pflip[5]))
2943                                                 radeon_crtc_handle_flip(rdev, 5);
2944                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2945                                         DRM_DEBUG("IH: D6 vblank\n");
2946                                 }
2947                                 break;
2948                         case 1: /* D6 vline */
2949                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2950                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2951                                         DRM_DEBUG("IH: D6 vline\n");
2952                                 }
2953                                 break;
2954                         default:
2955                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2956                                 break;
2957                         }
2958                         break;
2959                 case 42: /* HPD hotplug */
2960                         switch (src_data) {
2961                         case 0:
2962                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2963                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2964                                         queue_hotplug = true;
2965                                         DRM_DEBUG("IH: HPD1\n");
2966                                 }
2967                                 break;
2968                         case 1:
2969                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2970                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2971                                         queue_hotplug = true;
2972                                         DRM_DEBUG("IH: HPD2\n");
2973                                 }
2974                                 break;
2975                         case 2:
2976                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2977                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2978                                         queue_hotplug = true;
2979                                         DRM_DEBUG("IH: HPD3\n");
2980                                 }
2981                                 break;
2982                         case 3:
2983                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2984                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2985                                         queue_hotplug = true;
2986                                         DRM_DEBUG("IH: HPD4\n");
2987                                 }
2988                                 break;
2989                         case 4:
2990                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2991                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2992                                         queue_hotplug = true;
2993                                         DRM_DEBUG("IH: HPD5\n");
2994                                 }
2995                                 break;
2996                         case 5:
2997                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2998                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2999                                         queue_hotplug = true;
3000                                         DRM_DEBUG("IH: HPD6\n");
3001                                 }
3002                                 break;
3003                         default:
3004                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3005                                 break;
3006                         }
3007                         break;
3008                 case 44: /* hdmi */
3009                         switch (src_data) {
3010                         case 0:
3011                                 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3012                                         rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3013                                         queue_hdmi = true;
3014                                         DRM_DEBUG("IH: HDMI0\n");
3015                                 }
3016                                 break;
3017                         case 1:
3018                                 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3019                                         rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3020                                         queue_hdmi = true;
3021                                         DRM_DEBUG("IH: HDMI1\n");
3022                                 }
3023                                 break;
3024                         case 2:
3025                                 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3026                                         rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3027                                         queue_hdmi = true;
3028                                         DRM_DEBUG("IH: HDMI2\n");
3029                                 }
3030                                 break;
3031                         case 3:
3032                                 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3033                                         rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3034                                         queue_hdmi = true;
3035                                         DRM_DEBUG("IH: HDMI3\n");
3036                                 }
3037                                 break;
3038                         case 4:
3039                                 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3040                                         rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3041                                         queue_hdmi = true;
3042                                         DRM_DEBUG("IH: HDMI4\n");
3043                                 }
3044                                 break;
3045                         case 5:
3046                                 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3047                                         rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3048                                         queue_hdmi = true;
3049                                         DRM_DEBUG("IH: HDMI5\n");
3050                                 }
3051                                 break;
3052                         default:
3053                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3054                                 break;
3055                         }
3056                         break;
3057                 case 176: /* CP_INT in ring buffer */
3058                 case 177: /* CP_INT in IB1 */
3059                 case 178: /* CP_INT in IB2 */
3060                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3061                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3062                         break;
3063                 case 181: /* CP EOP event */
3064                         DRM_DEBUG("IH: CP EOP\n");
3065                         if (rdev->family >= CHIP_CAYMAN) {
3066                                 switch (src_data) {
3067                                 case 0:
3068                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3069                                         break;
3070                                 case 1:
3071                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3072                                         break;
3073                                 case 2:
3074                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3075                                         break;
3076                                 }
3077                         } else
3078                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3079                         break;
3080                 case 233: /* GUI IDLE */
3081                         DRM_DEBUG("IH: GUI idle\n");
3082                         wake_up(&rdev->irq.idle_queue);
3083                         break;
3084                 default:
3085                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3086                         break;
3087                 }
3088
3089                 /* wptr/rptr are in bytes! */
3090                 rptr += 16;
3091                 rptr &= rdev->ih.ptr_mask;
3092         }
3093         if (queue_hotplug)
3094                 schedule_work(&rdev->hotplug_work);
3095         if (queue_hdmi)
3096                 schedule_work(&rdev->audio_work);
3097         rdev->ih.rptr = rptr;
3098         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3099         atomic_set(&rdev->ih.lock, 0);
3100
3101         /* make sure wptr hasn't changed while processing */
3102         wptr = evergreen_get_ih_wptr(rdev);
3103         if (wptr != rptr)
3104                 goto restart_ih;
3105
3106         return IRQ_HANDLED;
3107 }
3108
3109 static int evergreen_startup(struct radeon_device *rdev)
3110 {
3111         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3112         int r;
3113
3114         /* enable pcie gen2 link */
3115         evergreen_pcie_gen2_enable(rdev);
3116
3117         if (ASIC_IS_DCE5(rdev)) {
3118                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3119                         r = ni_init_microcode(rdev);
3120                         if (r) {
3121                                 DRM_ERROR("Failed to load firmware!\n");
3122                                 return r;
3123                         }
3124                 }
3125                 r = ni_mc_load_microcode(rdev);
3126                 if (r) {
3127                         DRM_ERROR("Failed to load MC firmware!\n");
3128                         return r;
3129                 }
3130         } else {
3131                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3132                         r = r600_init_microcode(rdev);
3133                         if (r) {
3134                                 DRM_ERROR("Failed to load firmware!\n");
3135                                 return r;
3136                         }
3137                 }
3138         }
3139
3140         r = r600_vram_scratch_init(rdev);
3141         if (r)
3142                 return r;
3143
3144         evergreen_mc_program(rdev);
3145         if (rdev->flags & RADEON_IS_AGP) {
3146                 evergreen_agp_enable(rdev);
3147         } else {
3148                 r = evergreen_pcie_gart_enable(rdev);
3149                 if (r)
3150                         return r;
3151         }
3152         evergreen_gpu_init(rdev);
3153
3154         r = evergreen_blit_init(rdev);
3155         if (r) {
3156                 r600_blit_fini(rdev);
3157                 rdev->asic->copy.copy = NULL;
3158                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3159         }
3160
3161         /* allocate wb buffer */
3162         r = radeon_wb_init(rdev);
3163         if (r)
3164                 return r;
3165
3166         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3167         if (r) {
3168                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3169                 return r;
3170         }
3171
3172         /* Enable IRQ */
3173         r = r600_irq_init(rdev);
3174         if (r) {
3175                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3176                 radeon_irq_kms_fini(rdev);
3177                 return r;
3178         }
3179         evergreen_irq_set(rdev);
3180
3181         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3182                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3183                              0, 0xfffff, RADEON_CP_PACKET2);
3184         if (r)
3185                 return r;
3186         r = evergreen_cp_load_microcode(rdev);
3187         if (r)
3188                 return r;
3189         r = evergreen_cp_resume(rdev);
3190         if (r)
3191                 return r;
3192
3193         r = radeon_ib_pool_init(rdev);
3194         if (r) {
3195                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3196                 return r;
3197         }
3198
3199         r = r600_audio_init(rdev);
3200         if (r) {
3201                 DRM_ERROR("radeon: audio init failed\n");
3202                 return r;
3203         }
3204
3205         return 0;
3206 }
3207
3208 int evergreen_resume(struct radeon_device *rdev)
3209 {
3210         int r;
3211
3212         /* reset the asic, the gfx blocks are often in a bad state
3213          * after the driver is unloaded or after a resume
3214          */
3215         if (radeon_asic_reset(rdev))
3216                 dev_warn(rdev->dev, "GPU reset failed !\n");
3217         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3218          * posting will perform necessary task to bring back GPU into good
3219          * shape.
3220          */
3221         /* post card */
3222         atom_asic_init(rdev->mode_info.atom_context);
3223
3224         rdev->accel_working = true;
3225         r = evergreen_startup(rdev);
3226         if (r) {
3227                 DRM_ERROR("evergreen startup failed on resume\n");
3228                 rdev->accel_working = false;
3229                 return r;
3230         }
3231
3232         return r;
3233
3234 }
3235
3236 int evergreen_suspend(struct radeon_device *rdev)
3237 {
3238         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3239
3240         r600_audio_fini(rdev);
3241         r700_cp_stop(rdev);
3242         ring->ready = false;
3243         evergreen_irq_suspend(rdev);
3244         radeon_wb_disable(rdev);
3245         evergreen_pcie_gart_disable(rdev);
3246
3247         return 0;
3248 }
3249
3250 /* Plan is to move initialization in that function and use
3251  * helper function so that radeon_device_init pretty much
3252  * do nothing more than calling asic specific function. This
3253  * should also allow to remove a bunch of callback function
3254  * like vram_info.
3255  */
3256 int evergreen_init(struct radeon_device *rdev)
3257 {
3258         int r;
3259
3260         /* Read BIOS */
3261         if (!radeon_get_bios(rdev)) {
3262                 if (ASIC_IS_AVIVO(rdev))
3263                         return -EINVAL;
3264         }
3265         /* Must be an ATOMBIOS */
3266         if (!rdev->is_atom_bios) {
3267                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3268                 return -EINVAL;
3269         }
3270         r = radeon_atombios_init(rdev);
3271         if (r)
3272                 return r;
3273         /* reset the asic, the gfx blocks are often in a bad state
3274          * after the driver is unloaded or after a resume
3275          */
3276         if (radeon_asic_reset(rdev))
3277                 dev_warn(rdev->dev, "GPU reset failed !\n");
3278         /* Post card if necessary */
3279         if (!radeon_card_posted(rdev)) {
3280                 if (!rdev->bios) {
3281                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3282                         return -EINVAL;
3283                 }
3284                 DRM_INFO("GPU not posted. posting now...\n");
3285                 atom_asic_init(rdev->mode_info.atom_context);
3286         }
3287         /* Initialize scratch registers */
3288         r600_scratch_init(rdev);
3289         /* Initialize surface registers */
3290         radeon_surface_init(rdev);
3291         /* Initialize clocks */
3292         radeon_get_clock_info(rdev->ddev);
3293         /* Fence driver */
3294         r = radeon_fence_driver_init(rdev);
3295         if (r)
3296                 return r;
3297         /* initialize AGP */
3298         if (rdev->flags & RADEON_IS_AGP) {
3299                 r = radeon_agp_init(rdev);
3300                 if (r)
3301                         radeon_agp_disable(rdev);
3302         }
3303         /* initialize memory controller */
3304         r = evergreen_mc_init(rdev);
3305         if (r)
3306                 return r;
3307         /* Memory manager */
3308         r = radeon_bo_init(rdev);
3309         if (r)
3310                 return r;
3311
3312         r = radeon_irq_kms_init(rdev);
3313         if (r)
3314                 return r;
3315
3316         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3317         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3318
3319         rdev->ih.ring_obj = NULL;
3320         r600_ih_ring_init(rdev, 64 * 1024);
3321
3322         r = r600_pcie_gart_init(rdev);
3323         if (r)
3324                 return r;
3325
3326         rdev->accel_working = true;
3327         r = evergreen_startup(rdev);
3328         if (r) {
3329                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3330                 r700_cp_fini(rdev);
3331                 r600_irq_fini(rdev);
3332                 radeon_wb_fini(rdev);
3333                 radeon_ib_pool_fini(rdev);
3334                 radeon_irq_kms_fini(rdev);
3335                 evergreen_pcie_gart_fini(rdev);
3336                 rdev->accel_working = false;
3337         }
3338
3339         /* Don't start up if the MC ucode is missing on BTC parts.
3340          * The default clocks and voltages before the MC ucode
3341          * is loaded are not suffient for advanced operations.
3342          */
3343         if (ASIC_IS_DCE5(rdev)) {
3344                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3345                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3346                         return -EINVAL;
3347                 }
3348         }
3349
3350         return 0;
3351 }
3352
3353 void evergreen_fini(struct radeon_device *rdev)
3354 {
3355         r600_audio_fini(rdev);
3356         r600_blit_fini(rdev);
3357         r700_cp_fini(rdev);
3358         r600_irq_fini(rdev);
3359         radeon_wb_fini(rdev);
3360         radeon_ib_pool_fini(rdev);
3361         radeon_irq_kms_fini(rdev);
3362         evergreen_pcie_gart_fini(rdev);
3363         r600_vram_scratch_fini(rdev);
3364         radeon_gem_fini(rdev);
3365         radeon_fence_driver_fini(rdev);
3366         radeon_agp_fini(rdev);
3367         radeon_bo_fini(rdev);
3368         radeon_atombios_fini(rdev);
3369         kfree(rdev->bios);
3370         rdev->bios = NULL;
3371 }
3372
3373 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3374 {
3375         u32 link_width_cntl, speed_cntl, mask;
3376         int ret;
3377
3378         if (radeon_pcie_gen2 == 0)
3379                 return;
3380
3381         if (rdev->flags & RADEON_IS_IGP)
3382                 return;
3383
3384         if (!(rdev->flags & RADEON_IS_PCIE))
3385                 return;
3386
3387         /* x2 cards have a special sequence */
3388         if (ASIC_IS_X2(rdev))
3389                 return;
3390
3391         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3392         if (ret != 0)
3393                 return;
3394
3395         if (!(mask & DRM_PCIE_SPEED_50))
3396                 return;
3397
3398         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3399
3400         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3401         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3402             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3403
3404                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3405                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3406                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3407
3408                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3409                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3410                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3411
3412                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3413                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3414                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3415
3416                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3417                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3418                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3419
3420                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3421                 speed_cntl |= LC_GEN2_EN_STRAP;
3422                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3423
3424         } else {
3425                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3426                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3427                 if (1)
3428                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3429                 else
3430                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3431                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3432         }
3433 }