drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38
  39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
  40 {
  41         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  42         switch (radeon_encoder->encoder_id) {
  43         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  44         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  45         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  46         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  47         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  48         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  49         case ENCODER_OBJECT_ID_INTERNAL_DDI:
  50         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  51         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  52         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  53         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  54                 return true;
  55         default:
  56                 return false;
  57         }
  58 }
  59
  60 static struct drm_connector *
  61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
  62 {
  63         struct drm_device *dev = encoder->dev;
  64         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  65         struct drm_connector *connector;
  66         struct radeon_connector *radeon_connector;
  67
  68         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  69                 radeon_connector = to_radeon_connector(connector);
  70                 if (radeon_encoder->devices & radeon_connector->devices)
  71                         return connector;
  72         }
  73         return NULL;
  74 }
  75
  76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
  77                                    struct drm_display_mode *mode,
  78                                    struct drm_display_mode *adjusted_mode)
  79 {
  80         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  81         struct drm_device *dev = encoder->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83
  84         /* set the active encoder to connector routing */
  85         radeon_encoder_set_active_device(encoder);
  86         drm_mode_set_crtcinfo(adjusted_mode, 0);
  87
  88         /* hw bug */
  89         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
  90             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
  91                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
  92
  93         /* vertical FP must be at least 1 */
  94         if (mode->crtc_vsync_start == mode->crtc_vdisplay)
  95                 adjusted_mode->crtc_vsync_start++;
  96
  97         /* get the native mode for LVDS */
  98         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  99                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 100
 101         /* get the native mode for TV */
 102         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 103                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 104                 if (tv_dac) {
 105                         if (tv_dac->tv_std == TV_STD_NTSC ||
 106                             tv_dac->tv_std == TV_STD_NTSC_J ||
 107                             tv_dac->tv_std == TV_STD_PAL_M)
 108                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 109                         else
 110                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 111                 }
 112         }
 113
 114         if (ASIC_IS_DCE3(rdev) &&
 115             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 116              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 117                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 118                 radeon_dp_set_link_config(connector, adjusted_mode);
 119         }
 120
 121         return true;
 122 }
 123
 124 static void
 125 atombios_dac_setup(struct drm_encoder *encoder, int action)
 126 {
 127         struct drm_device *dev = encoder->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 130         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 131         int index = 0;
 132         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 133
 134         memset(&args, 0, sizeof(args));
 135
 136         switch (radeon_encoder->encoder_id) {
 137         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 138         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 139                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 140                 break;
 141         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 142         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 143                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 144                 break;
 145         }
 146
 147         args.ucAction = action;
 148
 149         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 150                 args.ucDacStandard = ATOM_DAC1_PS2;
 151         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 152                 args.ucDacStandard = ATOM_DAC1_CV;
 153         else {
 154                 switch (dac_info->tv_std) {
 155                 case TV_STD_PAL:
 156                 case TV_STD_PAL_M:
 157                 case TV_STD_SCART_PAL:
 158                 case TV_STD_SECAM:
 159                 case TV_STD_PAL_CN:
 160                         args.ucDacStandard = ATOM_DAC1_PAL;
 161                         break;
 162                 case TV_STD_NTSC:
 163                 case TV_STD_NTSC_J:
 164                 case TV_STD_PAL_60:
 165                 default:
 166                         args.ucDacStandard = ATOM_DAC1_NTSC;
 167                         break;
 168                 }
 169         }
 170         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 171
 172         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 173
 174 }
 175
 176 static void
 177 atombios_tv_setup(struct drm_encoder *encoder, int action)
 178 {
 179         struct drm_device *dev = encoder->dev;
 180         struct radeon_device *rdev = dev->dev_private;
 181         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 182         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 183         int index = 0;
 184         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 185
 186         memset(&args, 0, sizeof(args));
 187
 188         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 189
 190         args.sTVEncoder.ucAction = action;
 191
 192         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 193                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 194         else {
 195                 switch (dac_info->tv_std) {
 196                 case TV_STD_NTSC:
 197                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 198                         break;
 199                 case TV_STD_PAL:
 200                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 201                         break;
 202                 case TV_STD_PAL_M:
 203                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 204                         break;
 205                 case TV_STD_PAL_60:
 206                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 207                         break;
 208                 case TV_STD_NTSC_J:
 209                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 210                         break;
 211                 case TV_STD_SCART_PAL:
 212                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 213                         break;
 214                 case TV_STD_SECAM:
 215                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 216                         break;
 217                 case TV_STD_PAL_CN:
 218                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 219                         break;
 220                 default:
 221                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 222                         break;
 223                 }
 224         }
 225
 226         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 227
 228         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 229
 230 }
 231
 232 union dvo_encoder_control {
 233         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 234         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 235         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 236 };
 237
 238 void
 239 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 240 {
 241         struct drm_device *dev = encoder->dev;
 242         struct radeon_device *rdev = dev->dev_private;
 243         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 244         union dvo_encoder_control args;
 245         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 246         uint8_t frev, crev;
 247
 248         memset(&args, 0, sizeof(args));
 249
 250         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 251                 return;
 252
 253         /* some R4xx chips have the wrong frev */
 254         if (rdev->family <= CHIP_RV410)
 255                 frev = 1;
 256
 257         switch (frev) {
 258         case 1:
 259                 switch (crev) {
 260                 case 1:
 261                         /* R4xx, R5xx */
 262                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 263
 264                         if (radeon_encoder->pixel_clock > 165000)
 265                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 266
 267                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 268                         break;
 269                 case 2:
 270                         /* RS600/690/740 */
 271                         args.dvo.sDVOEncoder.ucAction = action;
 272                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 273                         /* DFP1, CRT1, TV1 depending on the type of port */
 274                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 275
 276                         if (radeon_encoder->pixel_clock > 165000)
 277                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 278                         break;
 279                 case 3:
 280                         /* R6xx */
 281                         args.dvo_v3.ucAction = action;
 282                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 283                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 284                         break;
 285                 default:
 286                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 287                         break;
 288                 }
 289                 break;
 290         default:
 291                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 292                 break;
 293         }
 294
 295         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 296 }
 297
 298 union lvds_encoder_control {
 299         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 300         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 301 };
 302
 303 void
 304 atombios_digital_setup(struct drm_encoder *encoder, int action)
 305 {
 306         struct drm_device *dev = encoder->dev;
 307         struct radeon_device *rdev = dev->dev_private;
 308         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 309         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 310         union lvds_encoder_control args;
 311         int index = 0;
 312         int hdmi_detected = 0;
 313         uint8_t frev, crev;
 314
 315         if (!dig)
 316                 return;
 317
 318         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 319                 hdmi_detected = 1;
 320
 321         memset(&args, 0, sizeof(args));
 322
 323         switch (radeon_encoder->encoder_id) {
 324         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 325                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 326                 break;
 327         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 328         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 329                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 330                 break;
 331         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 332                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 333                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 334                 else
 335                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 336                 break;
 337         }
 338
 339         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 340                 return;
 341
 342         switch (frev) {
 343         case 1:
 344         case 2:
 345                 switch (crev) {
 346                 case 1:
 347                         args.v1.ucMisc = 0;
 348                         args.v1.ucAction = action;
 349                         if (hdmi_detected)
 350                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 351                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 352                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 353                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 354                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 355                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 356                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 357                         } else {
 358                                 if (dig->linkb)
 359                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 360                                 if (radeon_encoder->pixel_clock > 165000)
 361                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 362                                 /*if (pScrn->rgbBits == 8) */
 363                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 364                         }
 365                         break;
 366                 case 2:
 367                 case 3:
 368                         args.v2.ucMisc = 0;
 369                         args.v2.ucAction = action;
 370                         if (crev == 3) {
 371                                 if (dig->coherent_mode)
 372                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 373                         }
 374                         if (hdmi_detected)
 375                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 376                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 377                         args.v2.ucTruncate = 0;
 378                         args.v2.ucSpatial = 0;
 379                         args.v2.ucTemporal = 0;
 380                         args.v2.ucFRC = 0;
 381                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 382                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 383                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 384                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 385                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 386                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 387                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 388                                 }
 389                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 390                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 391                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 392                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 393                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 394                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 395                                 }
 396                         } else {
 397                                 if (dig->linkb)
 398                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 399                                 if (radeon_encoder->pixel_clock > 165000)
 400                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 401                         }
 402                         break;
 403                 default:
 404                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 405                         break;
 406                 }
 407                 break;
 408         default:
 409                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 410                 break;
 411         }
 412
 413         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 414 }
 415
 416 int
 417 atombios_get_encoder_mode(struct drm_encoder *encoder)
 418 {
 419         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 420         struct drm_device *dev = encoder->dev;
 421         struct radeon_device *rdev = dev->dev_private;
 422         struct drm_connector *connector;
 423         struct radeon_connector *radeon_connector;
 424         struct radeon_connector_atom_dig *dig_connector;
 425
 426         /* dp bridges are always DP */
 427         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 428                 return ATOM_ENCODER_MODE_DP;
 429
 430         /* DVO is always DVO */
 431         if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
 432                 return ATOM_ENCODER_MODE_DVO;
 433
 434         connector = radeon_get_connector_for_encoder(encoder);
 435         /* if we don't have an active device yet, just use one of
 436          * the connectors tied to the encoder.
 437          */
 438         if (!connector)
 439                 connector = radeon_get_connector_for_encoder_init(encoder);
 440         radeon_connector = to_radeon_connector(connector);
 441
 442         switch (connector->connector_type) {
 443         case DRM_MODE_CONNECTOR_DVII:
 444         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 445                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 446                         /* fix me */
 447                         if (ASIC_IS_DCE4(rdev))
 448                                 return ATOM_ENCODER_MODE_DVI;
 449                         else
 450                                 return ATOM_ENCODER_MODE_HDMI;
 451                 } else if (radeon_connector->use_digital)
 452                         return ATOM_ENCODER_MODE_DVI;
 453                 else
 454                         return ATOM_ENCODER_MODE_CRT;
 455                 break;
 456         case DRM_MODE_CONNECTOR_DVID:
 457         case DRM_MODE_CONNECTOR_HDMIA:
 458         default:
 459                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 460                         /* fix me */
 461                         if (ASIC_IS_DCE4(rdev))
 462                                 return ATOM_ENCODER_MODE_DVI;
 463                         else
 464                                 return ATOM_ENCODER_MODE_HDMI;
 465                 } else
 466                         return ATOM_ENCODER_MODE_DVI;
 467                 break;
 468         case DRM_MODE_CONNECTOR_LVDS:
 469                 return ATOM_ENCODER_MODE_LVDS;
 470                 break;
 471         case DRM_MODE_CONNECTOR_DisplayPort:
 472                 dig_connector = radeon_connector->con_priv;
 473                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 474                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 475                         return ATOM_ENCODER_MODE_DP;
 476                 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 477                         /* fix me */
 478                         if (ASIC_IS_DCE4(rdev))
 479                                 return ATOM_ENCODER_MODE_DVI;
 480                         else
 481                                 return ATOM_ENCODER_MODE_HDMI;
 482                 } else
 483                         return ATOM_ENCODER_MODE_DVI;
 484                 break;
 485         case DRM_MODE_CONNECTOR_eDP:
 486                 return ATOM_ENCODER_MODE_DP;
 487         case DRM_MODE_CONNECTOR_DVIA:
 488         case DRM_MODE_CONNECTOR_VGA:
 489                 return ATOM_ENCODER_MODE_CRT;
 490                 break;
 491         case DRM_MODE_CONNECTOR_Composite:
 492         case DRM_MODE_CONNECTOR_SVIDEO:
 493         case DRM_MODE_CONNECTOR_9PinDIN:
 494                 /* fix me */
 495                 return ATOM_ENCODER_MODE_TV;
 496                 /*return ATOM_ENCODER_MODE_CV;*/
 497                 break;
 498         }
 499 }
 500
 501 /*
 502  * DIG Encoder/Transmitter Setup
 503  *
 504  * DCE 3.0/3.1
 505  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 506  * Supports up to 3 digital outputs
 507  * - 2 DIG encoder blocks.
 508  * DIG1 can drive UNIPHY link A or link B
 509  * DIG2 can drive UNIPHY link B or LVTMA
 510  *
 511  * DCE 3.2
 512  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 513  * Supports up to 5 digital outputs
 514  * - 2 DIG encoder blocks.
 515  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 516  *
 517  * DCE 4.0/5.0
 518  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 519  * Supports up to 6 digital outputs
 520  * - 6 DIG encoder blocks.
 521  * - DIG to PHY mapping is hardcoded
 522  * DIG1 drives UNIPHY0 link A, A+B
 523  * DIG2 drives UNIPHY0 link B
 524  * DIG3 drives UNIPHY1 link A, A+B
 525  * DIG4 drives UNIPHY1 link B
 526  * DIG5 drives UNIPHY2 link A, A+B
 527  * DIG6 drives UNIPHY2 link B
 528  *
 529  * DCE 4.1
 530  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 531  * Supports up to 6 digital outputs
 532  * - 2 DIG encoder blocks.
 533  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 534  *
 535  * Routing
 536  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 537  * Examples:
 538  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 539  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 540  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 541  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 542  */
 543
 544 union dig_encoder_control {
 545         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 546         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 547         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 548         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 549 };
 550
 551 void
 552 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 553 {
 554         struct drm_device *dev = encoder->dev;
 555         struct radeon_device *rdev = dev->dev_private;
 556         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 557         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 558         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 559         union dig_encoder_control args;
 560         int index = 0;
 561         uint8_t frev, crev;
 562         int dp_clock = 0;
 563         int dp_lane_count = 0;
 564         int hpd_id = RADEON_HPD_NONE;
 565         int bpc = 8;
 566
 567         if (connector) {
 568                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 569                 struct radeon_connector_atom_dig *dig_connector =
 570                         radeon_connector->con_priv;
 571
 572                 dp_clock = dig_connector->dp_clock;
 573                 dp_lane_count = dig_connector->dp_lane_count;
 574                 hpd_id = radeon_connector->hpd.hpd;
 575                 bpc = connector->display_info.bpc;
 576         }
 577
 578         /* no dig encoder assigned */
 579         if (dig->dig_encoder == -1)
 580                 return;
 581
 582         memset(&args, 0, sizeof(args));
 583
 584         if (ASIC_IS_DCE4(rdev))
 585                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 586         else {
 587                 if (dig->dig_encoder)
 588                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 589                 else
 590                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 591         }
 592
 593         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 594                 return;
 595
 596         switch (frev) {
 597         case 1:
 598                 switch (crev) {
 599                 case 1:
 600                         args.v1.ucAction = action;
 601                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 602                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 603                                 args.v3.ucPanelMode = panel_mode;
 604                         else
 605                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 606
 607                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 608                                 args.v1.ucLaneNum = dp_lane_count;
 609                         else if (radeon_encoder->pixel_clock > 165000)
 610                                 args.v1.ucLaneNum = 8;
 611                         else
 612                                 args.v1.ucLaneNum = 4;
 613
 614                         switch (radeon_encoder->encoder_id) {
 615                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 616                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 617                                 break;
 618                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 619                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 620                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 621                                 break;
 622                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 623                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 624                                 break;
 625                         }
 626                         if (dig->linkb)
 627                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 628                         else
 629                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 630
 631                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 632                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 633
 634                         break;
 635                 case 2:
 636                 case 3:
 637                         args.v3.ucAction = action;
 638                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 639                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 640                                 args.v3.ucPanelMode = panel_mode;
 641                         else
 642                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 643
 644                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 645                                 args.v3.ucLaneNum = dp_lane_count;
 646                         else if (radeon_encoder->pixel_clock > 165000)
 647                                 args.v3.ucLaneNum = 8;
 648                         else
 649                                 args.v3.ucLaneNum = 4;
 650
 651                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 652                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 653                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 654                         switch (bpc) {
 655                         case 0:
 656                                 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
 657                                 break;
 658                         case 6:
 659                                 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 660                                 break;
 661                         case 8:
 662                         default:
 663                                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 664                                 break;
 665                         case 10:
 666                                 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 667                                 break;
 668                         case 12:
 669                                 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 670                                 break;
 671                         case 16:
 672                                 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 673                                 break;
 674                         }
 675                         break;
 676                 case 4:
 677                         args.v4.ucAction = action;
 678                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 679                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 680                                 args.v4.ucPanelMode = panel_mode;
 681                         else
 682                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 683
 684                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 685                                 args.v4.ucLaneNum = dp_lane_count;
 686                         else if (radeon_encoder->pixel_clock > 165000)
 687                                 args.v4.ucLaneNum = 8;
 688                         else
 689                                 args.v4.ucLaneNum = 4;
 690
 691                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
 692                                 if (dp_clock == 270000)
 693                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 694                                 else if (dp_clock == 540000)
 695                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 696                         }
 697                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 698                         switch (bpc) {
 699                         case 0:
 700                                 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
 701                                 break;
 702                         case 6:
 703                                 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 704                                 break;
 705                         case 8:
 706                         default:
 707                                 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 708                                 break;
 709                         case 10:
 710                                 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 711                                 break;
 712                         case 12:
 713                                 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 714                                 break;
 715                         case 16:
 716                                 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 717                                 break;
 718                         }
 719                         if (hpd_id == RADEON_HPD_NONE)
 720                                 args.v4.ucHPD_ID = 0;
 721                         else
 722                                 args.v4.ucHPD_ID = hpd_id + 1;
 723                         break;
 724                 default:
 725                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 726                         break;
 727                 }
 728                 break;
 729         default:
 730                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 731                 break;
 732         }
 733
 734         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 735
 736 }
 737
 738 union dig_transmitter_control {
 739         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 740         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 741         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 742         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 743 };
 744
 745 void
 746 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 747 {
 748         struct drm_device *dev = encoder->dev;
 749         struct radeon_device *rdev = dev->dev_private;
 750         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 751         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 752         struct drm_connector *connector;
 753         union dig_transmitter_control args;
 754         int index = 0;
 755         uint8_t frev, crev;
 756         bool is_dp = false;
 757         int pll_id = 0;
 758         int dp_clock = 0;
 759         int dp_lane_count = 0;
 760         int connector_object_id = 0;
 761         int igp_lane_info = 0;
 762         int dig_encoder = dig->dig_encoder;
 763
 764         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 765                 connector = radeon_get_connector_for_encoder_init(encoder);
 766                 /* just needed to avoid bailing in the encoder check.  the encoder
 767                  * isn't used for init
 768                  */
 769                 dig_encoder = 0;
 770         } else
 771                 connector = radeon_get_connector_for_encoder(encoder);
 772
 773         if (connector) {
 774                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 775                 struct radeon_connector_atom_dig *dig_connector =
 776                         radeon_connector->con_priv;
 777
 778                 dp_clock = dig_connector->dp_clock;
 779                 dp_lane_count = dig_connector->dp_lane_count;
 780                 connector_object_id =
 781                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 782                 igp_lane_info = dig_connector->igp_lane_info;
 783         }
 784
 785         if (encoder->crtc) {
 786                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 787                 pll_id = radeon_crtc->pll_id;
 788         }
 789
 790         /* no dig encoder assigned */
 791         if (dig_encoder == -1)
 792                 return;
 793
 794         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
 795                 is_dp = true;
 796
 797         memset(&args, 0, sizeof(args));
 798
 799         switch (radeon_encoder->encoder_id) {
 800         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 801                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 802                 break;
 803         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 804         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 805         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 806                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 807                 break;
 808         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 809                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 810                 break;
 811         }
 812
 813         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 814                 return;
 815
 816         switch (frev) {
 817         case 1:
 818                 switch (crev) {
 819                 case 1:
 820                         args.v1.ucAction = action;
 821                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 822                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
 823                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 824                                 args.v1.asMode.ucLaneSel = lane_num;
 825                                 args.v1.asMode.ucLaneSet = lane_set;
 826                         } else {
 827                                 if (is_dp)
 828                                         args.v1.usPixelClock =
 829                                                 cpu_to_le16(dp_clock / 10);
 830                                 else if (radeon_encoder->pixel_clock > 165000)
 831                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 832                                 else
 833                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 834                         }
 835
 836                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 837
 838                         if (dig_encoder)
 839                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 840                         else
 841                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 842
 843                         if ((rdev->flags & RADEON_IS_IGP) &&
 844                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 845                                 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 846                                         if (igp_lane_info & 0x1)
 847                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 848                                         else if (igp_lane_info & 0x2)
 849                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 850                                         else if (igp_lane_info & 0x4)
 851                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 852                                         else if (igp_lane_info & 0x8)
 853                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 854                                 } else {
 855                                         if (igp_lane_info & 0x3)
 856                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 857                                         else if (igp_lane_info & 0xc)
 858                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 859                                 }
 860                         }
 861
 862                         if (dig->linkb)
 863                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 864                         else
 865                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 866
 867                         if (is_dp)
 868                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 869                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 870                                 if (dig->coherent_mode)
 871                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 872                                 if (radeon_encoder->pixel_clock > 165000)
 873                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 874                         }
 875                         break;
 876                 case 2:
 877                         args.v2.ucAction = action;
 878                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 879                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
 880                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 881                                 args.v2.asMode.ucLaneSel = lane_num;
 882                                 args.v2.asMode.ucLaneSet = lane_set;
 883                         } else {
 884                                 if (is_dp)
 885                                         args.v2.usPixelClock =
 886                                                 cpu_to_le16(dp_clock / 10);
 887                                 else if (radeon_encoder->pixel_clock > 165000)
 888                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 889                                 else
 890                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 891                         }
 892
 893                         args.v2.acConfig.ucEncoderSel = dig_encoder;
 894                         if (dig->linkb)
 895                                 args.v2.acConfig.ucLinkSel = 1;
 896
 897                         switch (radeon_encoder->encoder_id) {
 898                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 899                                 args.v2.acConfig.ucTransmitterSel = 0;
 900                                 break;
 901                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 902                                 args.v2.acConfig.ucTransmitterSel = 1;
 903                                 break;
 904                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 905                                 args.v2.acConfig.ucTransmitterSel = 2;
 906                                 break;
 907                         }
 908
 909                         if (is_dp) {
 910                                 args.v2.acConfig.fCoherentMode = 1;
 911                                 args.v2.acConfig.fDPConnector = 1;
 912                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 913                                 if (dig->coherent_mode)
 914                                         args.v2.acConfig.fCoherentMode = 1;
 915                                 if (radeon_encoder->pixel_clock > 165000)
 916                                         args.v2.acConfig.fDualLinkConnector = 1;
 917                         }
 918                         break;
 919                 case 3:
 920                         args.v3.ucAction = action;
 921                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 922                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
 923                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 924                                 args.v3.asMode.ucLaneSel = lane_num;
 925                                 args.v3.asMode.ucLaneSet = lane_set;
 926                         } else {
 927                                 if (is_dp)
 928                                         args.v3.usPixelClock =
 929                                                 cpu_to_le16(dp_clock / 10);
 930                                 else if (radeon_encoder->pixel_clock > 165000)
 931                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 932                                 else
 933                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 934                         }
 935
 936                         if (is_dp)
 937                                 args.v3.ucLaneNum = dp_lane_count;
 938                         else if (radeon_encoder->pixel_clock > 165000)
 939                                 args.v3.ucLaneNum = 8;
 940                         else
 941                                 args.v3.ucLaneNum = 4;
 942
 943                         if (dig->linkb)
 944                                 args.v3.acConfig.ucLinkSel = 1;
 945                         if (dig_encoder & 1)
 946                                 args.v3.acConfig.ucEncoderSel = 1;
 947
 948                         /* Select the PLL for the PHY
 949                          * DP PHY should be clocked from external src if there is
 950                          * one.
 951                          */
 952                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
 953                         if (is_dp && rdev->clock.dp_extclk)
 954                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
 955                         else
 956                                 args.v3.acConfig.ucRefClkSource = pll_id;
 957
 958                         switch (radeon_encoder->encoder_id) {
 959                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 960                                 args.v3.acConfig.ucTransmitterSel = 0;
 961                                 break;
 962                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 963                                 args.v3.acConfig.ucTransmitterSel = 1;
 964                                 break;
 965                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 966                                 args.v3.acConfig.ucTransmitterSel = 2;
 967                                 break;
 968                         }
 969
 970                         if (is_dp)
 971                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 972                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 973                                 if (dig->coherent_mode)
 974                                         args.v3.acConfig.fCoherentMode = 1;
 975                                 if (radeon_encoder->pixel_clock > 165000)
 976                                         args.v3.acConfig.fDualLinkConnector = 1;
 977                         }
 978                         break;
 979                 case 4:
 980                         args.v4.ucAction = action;
 981                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 982                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
 983                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 984                                 args.v4.asMode.ucLaneSel = lane_num;
 985                                 args.v4.asMode.ucLaneSet = lane_set;
 986                         } else {
 987                                 if (is_dp)
 988                                         args.v4.usPixelClock =
 989                                                 cpu_to_le16(dp_clock / 10);
 990                                 else if (radeon_encoder->pixel_clock > 165000)
 991                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 992                                 else
 993                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 994                         }
 995
 996                         if (is_dp)
 997                                 args.v4.ucLaneNum = dp_lane_count;
 998                         else if (radeon_encoder->pixel_clock > 165000)
 999                                 args.v4.ucLaneNum = 8;
1000                         else
1001                                 args.v4.ucLaneNum = 4;
1002
1003                         if (dig->linkb)
1004                                 args.v4.acConfig.ucLinkSel = 1;
1005                         if (dig_encoder & 1)
1006                                 args.v4.acConfig.ucEncoderSel = 1;
1007
1008                         /* Select the PLL for the PHY
1009                          * DP PHY should be clocked from external src if there is
1010                          * one.
1011                          */
1012                         /* On DCE5 DCPLL usually generates the DP ref clock */
1013                         if (is_dp) {
1014                                 if (rdev->clock.dp_extclk)
1015                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1016                                 else
1017                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1018                         } else
1019                                 args.v4.acConfig.ucRefClkSource = pll_id;
1020
1021                         switch (radeon_encoder->encoder_id) {
1022                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1023                                 args.v4.acConfig.ucTransmitterSel = 0;
1024                                 break;
1025                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1026                                 args.v4.acConfig.ucTransmitterSel = 1;
1027                                 break;
1028                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1029                                 args.v4.acConfig.ucTransmitterSel = 2;
1030                                 break;
1031                         }
1032
1033                         if (is_dp)
1034                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1035                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1036                                 if (dig->coherent_mode)
1037                                         args.v4.acConfig.fCoherentMode = 1;
1038                                 if (radeon_encoder->pixel_clock > 165000)
1039                                         args.v4.acConfig.fDualLinkConnector = 1;
1040                         }
1041                         break;
1042                 default:
1043                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1044                         break;
1045                 }
1046                 break;
1047         default:
1048                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1049                 break;
1050         }
1051
1052         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1053 }
1054
1055 bool
1056 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1057 {
1058         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1059         struct drm_device *dev = radeon_connector->base.dev;
1060         struct radeon_device *rdev = dev->dev_private;
1061         union dig_transmitter_control args;
1062         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1063         uint8_t frev, crev;
1064
1065         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1066                 goto done;
1067
1068         if (!ASIC_IS_DCE4(rdev))
1069                 goto done;
1070
1071         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1072             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1073                 goto done;
1074
1075         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1076                 goto done;
1077
1078         memset(&args, 0, sizeof(args));
1079
1080         args.v1.ucAction = action;
1081
1082         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1083
1084         /* wait for the panel to power up */
1085         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1086                 int i;
1087
1088                 for (i = 0; i < 300; i++) {
1089                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1090                                 return true;
1091                         mdelay(1);
1092                 }
1093                 return false;
1094         }
1095 done:
1096         return true;
1097 }
1098
1099 union external_encoder_control {
1100         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1101         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1102 };
1103
1104 static void
1105 atombios_external_encoder_setup(struct drm_encoder *encoder,
1106                                 struct drm_encoder *ext_encoder,
1107                                 int action)
1108 {
1109         struct drm_device *dev = encoder->dev;
1110         struct radeon_device *rdev = dev->dev_private;
1111         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1112         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1113         union external_encoder_control args;
1114         struct drm_connector *connector;
1115         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1116         u8 frev, crev;
1117         int dp_clock = 0;
1118         int dp_lane_count = 0;
1119         int connector_object_id = 0;
1120         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1121         int bpc = 8;
1122
1123         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1124                 connector = radeon_get_connector_for_encoder_init(encoder);
1125         else
1126                 connector = radeon_get_connector_for_encoder(encoder);
1127
1128         if (connector) {
1129                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1130                 struct radeon_connector_atom_dig *dig_connector =
1131                         radeon_connector->con_priv;
1132
1133                 dp_clock = dig_connector->dp_clock;
1134                 dp_lane_count = dig_connector->dp_lane_count;
1135                 connector_object_id =
1136                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1137                 bpc = connector->display_info.bpc;
1138         }
1139
1140         memset(&args, 0, sizeof(args));
1141
1142         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1143                 return;
1144
1145         switch (frev) {
1146         case 1:
1147                 /* no params on frev 1 */
1148                 break;
1149         case 2:
1150                 switch (crev) {
1151                 case 1:
1152                 case 2:
1153                         args.v1.sDigEncoder.ucAction = action;
1154                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1155                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1156
1157                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1158                                 if (dp_clock == 270000)
1159                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1160                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1161                         } else if (radeon_encoder->pixel_clock > 165000)
1162                                 args.v1.sDigEncoder.ucLaneNum = 8;
1163                         else
1164                                 args.v1.sDigEncoder.ucLaneNum = 4;
1165                         break;
1166                 case 3:
1167                         args.v3.sExtEncoder.ucAction = action;
1168                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1169                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1170                         else
1171                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1172                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1173
1174                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1175                                 if (dp_clock == 270000)
1176                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1177                                 else if (dp_clock == 540000)
1178                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1179                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1180                         } else if (radeon_encoder->pixel_clock > 165000)
1181                                 args.v3.sExtEncoder.ucLaneNum = 8;
1182                         else
1183                                 args.v3.sExtEncoder.ucLaneNum = 4;
1184                         switch (ext_enum) {
1185                         case GRAPH_OBJECT_ENUM_ID1:
1186                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1187                                 break;
1188                         case GRAPH_OBJECT_ENUM_ID2:
1189                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1190                                 break;
1191                         case GRAPH_OBJECT_ENUM_ID3:
1192                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1193                                 break;
1194                         }
1195                         switch (bpc) {
1196                         case 0:
1197                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1198                                 break;
1199                         case 6:
1200                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1201                                 break;
1202                         case 8:
1203                         default:
1204                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1205                                 break;
1206                         case 10:
1207                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1208                                 break;
1209                         case 12:
1210                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1211                                 break;
1212                         case 16:
1213                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1214                                 break;
1215                         }
1216                         break;
1217                 default:
1218                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1219                         return;
1220                 }
1221                 break;
1222         default:
1223                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1224                 return;
1225         }
1226         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1227 }
1228
1229 static void
1230 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1231 {
1232         struct drm_device *dev = encoder->dev;
1233         struct radeon_device *rdev = dev->dev_private;
1234         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1235         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1236         ENABLE_YUV_PS_ALLOCATION args;
1237         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1238         uint32_t temp, reg;
1239
1240         memset(&args, 0, sizeof(args));
1241
1242         if (rdev->family >= CHIP_R600)
1243                 reg = R600_BIOS_3_SCRATCH;
1244         else
1245                 reg = RADEON_BIOS_3_SCRATCH;
1246
1247         /* XXX: fix up scratch reg handling */
1248         temp = RREG32(reg);
1249         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1250                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1251                              (radeon_crtc->crtc_id << 18)));
1252         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1253                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1254         else
1255                 WREG32(reg, 0);
1256
1257         if (enable)
1258                 args.ucEnable = ATOM_ENABLE;
1259         args.ucCRTC = radeon_crtc->crtc_id;
1260
1261         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1262
1263         WREG32(reg, temp);
1264 }
1265
1266 static void
1267 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1268 {
1269         struct drm_device *dev = encoder->dev;
1270         struct radeon_device *rdev = dev->dev_private;
1271         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1272         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1273         int index = 0;
1274
1275         memset(&args, 0, sizeof(args));
1276
1277         switch (radeon_encoder->encoder_id) {
1278         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1279         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1280                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1281                 break;
1282         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1283         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1284         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1285                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1286                 break;
1287         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1288                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1289                 break;
1290         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1291                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1292                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1293                 else
1294                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1295                 break;
1296         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1297         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1298                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1299                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1300                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1301                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1302                 else
1303                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1304                 break;
1305         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1306         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1307                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1308                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1309                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1310                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1311                 else
1312                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1313                 break;
1314         default:
1315                 return;
1316         }
1317
1318         switch (mode) {
1319         case DRM_MODE_DPMS_ON:
1320                 args.ucAction = ATOM_ENABLE;
1321                 /* workaround for DVOOutputControl on some RS690 systems */
1322                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1323                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1324                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1325                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1326                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1327                 } else
1328                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1329                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1330                         args.ucAction = ATOM_LCD_BLON;
1331                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1332                 }
1333                 break;
1334         case DRM_MODE_DPMS_STANDBY:
1335         case DRM_MODE_DPMS_SUSPEND:
1336         case DRM_MODE_DPMS_OFF:
1337                 args.ucAction = ATOM_DISABLE;
1338                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1339                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1340                         args.ucAction = ATOM_LCD_BLOFF;
1341                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1342                 }
1343                 break;
1344         }
1345 }
1346
1347 static void
1348 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1349 {
1350         struct drm_device *dev = encoder->dev;
1351         struct radeon_device *rdev = dev->dev_private;
1352         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1353         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1354         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1355         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1356         struct radeon_connector *radeon_connector = NULL;
1357         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1358
1359         if (connector) {
1360                 radeon_connector = to_radeon_connector(connector);
1361                 radeon_dig_connector = radeon_connector->con_priv;
1362         }
1363
1364         switch (mode) {
1365         case DRM_MODE_DPMS_ON:
1366                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1367                         if (!connector)
1368                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1369                         else
1370                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1371
1372                         /* setup and enable the encoder */
1373                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1374                         atombios_dig_encoder_setup(encoder,
1375                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1376                                                    dig->panel_mode);
1377                         if (ext_encoder) {
1378                                 if (ASIC_IS_DCE41(rdev))
1379                                         atombios_external_encoder_setup(encoder, ext_encoder,
1380                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1381                         }
1382                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1383                 } else if (ASIC_IS_DCE4(rdev)) {
1384                         /* setup and enable the encoder */
1385                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1386                         /* enable the transmitter */
1387                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1388                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1389                 } else {
1390                         /* setup and enable the encoder and transmitter */
1391                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1392                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1393                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1394                         /* some dce3.x boards have a bug in their transmitter control table.
1395                          * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1396                          * does the same thing and more.
1397                          */
1398                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1399                             (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1400                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1401                 }
1402                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1403                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1404                                 atombios_set_edp_panel_power(connector,
1405                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1406                                 radeon_dig_connector->edp_on = true;
1407                         }
1408                         radeon_dp_link_train(encoder, connector);
1409                         if (ASIC_IS_DCE4(rdev))
1410                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1411                 }
1412                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1413                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1414                 break;
1415         case DRM_MODE_DPMS_STANDBY:
1416         case DRM_MODE_DPMS_SUSPEND:
1417         case DRM_MODE_DPMS_OFF:
1418                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1419                         /* disable the transmitter */
1420                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1421                 } else if (ASIC_IS_DCE4(rdev)) {
1422                         /* disable the transmitter */
1423                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1424                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1425                 } else {
1426                         /* disable the encoder and transmitter */
1427                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1428                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1429                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1430                 }
1431                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1432                         if (ASIC_IS_DCE4(rdev))
1433                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1434                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1435                                 atombios_set_edp_panel_power(connector,
1436                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1437                                 radeon_dig_connector->edp_on = false;
1438                         }
1439                 }
1440                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1441                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1442                 break;
1443         }
1444 }
1445
1446 static void
1447 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1448                              struct drm_encoder *ext_encoder,
1449                              int mode)
1450 {
1451         struct drm_device *dev = encoder->dev;
1452         struct radeon_device *rdev = dev->dev_private;
1453
1454         switch (mode) {
1455         case DRM_MODE_DPMS_ON:
1456         default:
1457                 if (ASIC_IS_DCE41(rdev)) {
1458                         atombios_external_encoder_setup(encoder, ext_encoder,
1459                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1460                         atombios_external_encoder_setup(encoder, ext_encoder,
1461                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1462                 } else
1463                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1464                 break;
1465         case DRM_MODE_DPMS_STANDBY:
1466         case DRM_MODE_DPMS_SUSPEND:
1467         case DRM_MODE_DPMS_OFF:
1468                 if (ASIC_IS_DCE41(rdev)) {
1469                         atombios_external_encoder_setup(encoder, ext_encoder,
1470                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1471                         atombios_external_encoder_setup(encoder, ext_encoder,
1472                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1473                 } else
1474                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1475                 break;
1476         }
1477 }
1478
1479 static void
1480 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1481 {
1482         struct drm_device *dev = encoder->dev;
1483         struct radeon_device *rdev = dev->dev_private;
1484         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1485         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1486
1487         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1488                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1489                   radeon_encoder->active_device);
1490         switch (radeon_encoder->encoder_id) {
1491         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1492         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1493         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1494         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1495         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1496         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1497         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1498         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1499                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1500                 break;
1501         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1502         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1503         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1504         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1505                 radeon_atom_encoder_dpms_dig(encoder, mode);
1506                 break;
1507         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1508                 if (ASIC_IS_DCE5(rdev)) {
1509                         switch (mode) {
1510                         case DRM_MODE_DPMS_ON:
1511                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1512                                 break;
1513                         case DRM_MODE_DPMS_STANDBY:
1514                         case DRM_MODE_DPMS_SUSPEND:
1515                         case DRM_MODE_DPMS_OFF:
1516                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1517                                 break;
1518                         }
1519                 } else if (ASIC_IS_DCE3(rdev))
1520                         radeon_atom_encoder_dpms_dig(encoder, mode);
1521                 else
1522                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1523                 break;
1524         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1525         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1526                 if (ASIC_IS_DCE5(rdev)) {
1527                         switch (mode) {
1528                         case DRM_MODE_DPMS_ON:
1529                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1530                                 break;
1531                         case DRM_MODE_DPMS_STANDBY:
1532                         case DRM_MODE_DPMS_SUSPEND:
1533                         case DRM_MODE_DPMS_OFF:
1534                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1535                                 break;
1536                         }
1537                 } else
1538                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1539                 break;
1540         default:
1541                 return;
1542         }
1543
1544         if (ext_encoder)
1545                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1546
1547         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1548
1549 }
1550
1551 union crtc_source_param {
1552         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1553         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1554 };
1555
1556 static void
1557 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1558 {
1559         struct drm_device *dev = encoder->dev;
1560         struct radeon_device *rdev = dev->dev_private;
1561         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1562         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1563         union crtc_source_param args;
1564         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1565         uint8_t frev, crev;
1566         struct radeon_encoder_atom_dig *dig;
1567
1568         memset(&args, 0, sizeof(args));
1569
1570         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1571                 return;
1572
1573         switch (frev) {
1574         case 1:
1575                 switch (crev) {
1576                 case 1:
1577                 default:
1578                         if (ASIC_IS_AVIVO(rdev))
1579                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1580                         else {
1581                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1582                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1583                                 } else {
1584                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1585                                 }
1586                         }
1587                         switch (radeon_encoder->encoder_id) {
1588                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1589                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1590                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1591                                 break;
1592                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1593                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1594                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1595                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1596                                 else
1597                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1598                                 break;
1599                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1600                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1601                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1602                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1603                                 break;
1604                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1605                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1606                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1607                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1608                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1609                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1610                                 else
1611                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1612                                 break;
1613                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1614                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1615                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1616                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1617                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1618                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1619                                 else
1620                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1621                                 break;
1622                         }
1623                         break;
1624                 case 2:
1625                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1626                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1627                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1628
1629                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1630                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1631                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1632                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1633                                 else
1634                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1635                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1636                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1637                         } else {
1638                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1639                         }
1640                         switch (radeon_encoder->encoder_id) {
1641                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1642                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1643                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1644                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1645                                 dig = radeon_encoder->enc_priv;
1646                                 switch (dig->dig_encoder) {
1647                                 case 0:
1648                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1649                                         break;
1650                                 case 1:
1651                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1652                                         break;
1653                                 case 2:
1654                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1655                                         break;
1656                                 case 3:
1657                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1658                                         break;
1659                                 case 4:
1660                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1661                                         break;
1662                                 case 5:
1663                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1664                                         break;
1665                                 }
1666                                 break;
1667                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1668                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1669                                 break;
1670                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1671                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1672                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1673                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1674                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1675                                 else
1676                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1677                                 break;
1678                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1679                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1680                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1681                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1682                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1683                                 else
1684                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1685                                 break;
1686                         }
1687                         break;
1688                 }
1689                 break;
1690         default:
1691                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1692                 return;
1693         }
1694
1695         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1696
1697         /* update scratch regs with new routing */
1698         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1699 }
1700
1701 static void
1702 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1703                               struct drm_display_mode *mode)
1704 {
1705         struct drm_device *dev = encoder->dev;
1706         struct radeon_device *rdev = dev->dev_private;
1707         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1708         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1709
1710         /* Funky macbooks */
1711         if ((dev->pdev->device == 0x71C5) &&
1712             (dev->pdev->subsystem_vendor == 0x106b) &&
1713             (dev->pdev->subsystem_device == 0x0080)) {
1714                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1715                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1716
1717                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1718                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1719
1720                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1721                 }
1722         }
1723
1724         /* set scaler clears this on some chips */
1725         if (ASIC_IS_AVIVO(rdev) &&
1726             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1727                 if (ASIC_IS_DCE4(rdev)) {
1728                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1729                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1730                                        EVERGREEN_INTERLEAVE_EN);
1731                         else
1732                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1733                 } else {
1734                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1735                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1736                                        AVIVO_D1MODE_INTERLEAVE_EN);
1737                         else
1738                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1739                 }
1740         }
1741 }
1742
1743 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1744 {
1745         struct drm_device *dev = encoder->dev;
1746         struct radeon_device *rdev = dev->dev_private;
1747         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1748         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1749         struct drm_encoder *test_encoder;
1750         struct radeon_encoder_atom_dig *dig;
1751         uint32_t dig_enc_in_use = 0;
1752
1753         /* DCE4/5 */
1754         if (ASIC_IS_DCE4(rdev)) {
1755                 dig = radeon_encoder->enc_priv;
1756                 if (ASIC_IS_DCE41(rdev)) {
1757                         /* ontario follows DCE4 */
1758                         if (rdev->family == CHIP_PALM) {
1759                                 if (dig->linkb)
1760                                         return 1;
1761                                 else
1762                                         return 0;
1763                         } else
1764                                 /* llano follows DCE3.2 */
1765                                 return radeon_crtc->crtc_id;
1766                 } else {
1767                         switch (radeon_encoder->encoder_id) {
1768                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1769                                 if (dig->linkb)
1770                                         return 1;
1771                                 else
1772                                         return 0;
1773                                 break;
1774                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1775                                 if (dig->linkb)
1776                                         return 3;
1777                                 else
1778                                         return 2;
1779                                 break;
1780                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1781                                 if (dig->linkb)
1782                                         return 5;
1783                                 else
1784                                         return 4;
1785                                 break;
1786                         }
1787                 }
1788         }
1789
1790         /* on DCE32 and encoder can driver any block so just crtc id */
1791         if (ASIC_IS_DCE32(rdev)) {
1792                 return radeon_crtc->crtc_id;
1793         }
1794
1795         /* on DCE3 - LVTMA can only be driven by DIGB */
1796         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1797                 struct radeon_encoder *radeon_test_encoder;
1798
1799                 if (encoder == test_encoder)
1800                         continue;
1801
1802                 if (!radeon_encoder_is_digital(test_encoder))
1803                         continue;
1804
1805                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1806                 dig = radeon_test_encoder->enc_priv;
1807
1808                 if (dig->dig_encoder >= 0)
1809                         dig_enc_in_use |= (1 << dig->dig_encoder);
1810         }
1811
1812         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1813                 if (dig_enc_in_use & 0x2)
1814                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1815                 return 1;
1816         }
1817         if (!(dig_enc_in_use & 1))
1818                 return 0;
1819         return 1;
1820 }
1821
1822 /* This only needs to be called once at startup */
1823 void
1824 radeon_atom_encoder_init(struct radeon_device *rdev)
1825 {
1826         struct drm_device *dev = rdev->ddev;
1827         struct drm_encoder *encoder;
1828
1829         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1830                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1831                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1832
1833                 switch (radeon_encoder->encoder_id) {
1834                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1835                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1836                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1837                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1838                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1839                         break;
1840                 default:
1841                         break;
1842                 }
1843
1844                 if (ext_encoder && ASIC_IS_DCE41(rdev))
1845                         atombios_external_encoder_setup(encoder, ext_encoder,
1846                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1847         }
1848 }
1849
1850 static void
1851 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1852                              struct drm_display_mode *mode,
1853                              struct drm_display_mode *adjusted_mode)
1854 {
1855         struct drm_device *dev = encoder->dev;
1856         struct radeon_device *rdev = dev->dev_private;
1857         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1858
1859         radeon_encoder->pixel_clock = adjusted_mode->clock;
1860
1861         /* need to call this here rather than in prepare() since we need some crtc info */
1862         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1863
1864         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1865                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1866                         atombios_yuv_setup(encoder, true);
1867                 else
1868                         atombios_yuv_setup(encoder, false);
1869         }
1870
1871         switch (radeon_encoder->encoder_id) {
1872         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1873         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1874         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1875         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1876                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1877                 break;
1878         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1879         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1880         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1881         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1882                 /* handled in dpms */
1883                 break;
1884         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1885         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1886         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1887                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1888                 break;
1889         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1890         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1891         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1892         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1893                 atombios_dac_setup(encoder, ATOM_ENABLE);
1894                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1895                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1896                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1897                         else
1898                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1899                 }
1900                 break;
1901         }
1902
1903         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1904
1905         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1906                 r600_hdmi_enable(encoder);
1907                 r600_hdmi_setmode(encoder, adjusted_mode);
1908         }
1909 }
1910
1911 static bool
1912 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1913 {
1914         struct drm_device *dev = encoder->dev;
1915         struct radeon_device *rdev = dev->dev_private;
1916         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1917         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1918
1919         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1920                                        ATOM_DEVICE_CV_SUPPORT |
1921                                        ATOM_DEVICE_CRT_SUPPORT)) {
1922                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1923                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1924                 uint8_t frev, crev;
1925
1926                 memset(&args, 0, sizeof(args));
1927
1928                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1929                         return false;
1930
1931                 args.sDacload.ucMisc = 0;
1932
1933                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1934                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1935                         args.sDacload.ucDacType = ATOM_DAC_A;
1936                 else
1937                         args.sDacload.ucDacType = ATOM_DAC_B;
1938
1939                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1940                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1941                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1942                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1943                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1944                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1945                         if (crev >= 3)
1946                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1947                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1948                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1949                         if (crev >= 3)
1950                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1951                 }
1952
1953                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1954
1955                 return true;
1956         } else
1957                 return false;
1958 }
1959
1960 static enum drm_connector_status
1961 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1962 {
1963         struct drm_device *dev = encoder->dev;
1964         struct radeon_device *rdev = dev->dev_private;
1965         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1966         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1967         uint32_t bios_0_scratch;
1968
1969         if (!atombios_dac_load_detect(encoder, connector)) {
1970                 DRM_DEBUG_KMS("detect returned false \n");
1971                 return connector_status_unknown;
1972         }
1973
1974         if (rdev->family >= CHIP_R600)
1975                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1976         else
1977                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1978
1979         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1980         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1981                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1982                         return connector_status_connected;
1983         }
1984         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1985                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1986                         return connector_status_connected;
1987         }
1988         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1989                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1990                         return connector_status_connected;
1991         }
1992         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1993                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1994                         return connector_status_connected; /* CTV */
1995                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1996                         return connector_status_connected; /* STV */
1997         }
1998         return connector_status_disconnected;
1999 }
2000
2001 static enum drm_connector_status
2002 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2003 {
2004         struct drm_device *dev = encoder->dev;
2005         struct radeon_device *rdev = dev->dev_private;
2006         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2007         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2008         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2009         u32 bios_0_scratch;
2010
2011         if (!ASIC_IS_DCE4(rdev))
2012                 return connector_status_unknown;
2013
2014         if (!ext_encoder)
2015                 return connector_status_unknown;
2016
2017         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2018                 return connector_status_unknown;
2019
2020         /* load detect on the dp bridge */
2021         atombios_external_encoder_setup(encoder, ext_encoder,
2022                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2023
2024         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2025
2026         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2027         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2028                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2029                         return connector_status_connected;
2030         }
2031         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2032                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2033                         return connector_status_connected;
2034         }
2035         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2036                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2037                         return connector_status_connected;
2038         }
2039         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2040                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2041                         return connector_status_connected; /* CTV */
2042                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2043                         return connector_status_connected; /* STV */
2044         }
2045         return connector_status_disconnected;
2046 }
2047
2048 void
2049 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2050 {
2051         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2052
2053         if (ext_encoder)
2054                 /* ddc_setup on the dp bridge */
2055                 atombios_external_encoder_setup(encoder, ext_encoder,
2056                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2057
2058 }
2059
2060 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2061 {
2062         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2063         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2064
2065         if ((radeon_encoder->active_device &
2066              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2067             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2068              ENCODER_OBJECT_ID_NONE)) {
2069                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2070                 if (dig)
2071                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2072         }
2073
2074         radeon_atom_output_lock(encoder, true);
2075
2076         if (connector) {
2077                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2078
2079                 /* select the clock/data port if it uses a router */
2080                 if (radeon_connector->router.cd_valid)
2081                         radeon_router_select_cd_port(radeon_connector);
2082
2083                 /* turn eDP panel on for mode set */
2084                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2085                         atombios_set_edp_panel_power(connector,
2086                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2087         }
2088
2089         /* this is needed for the pll/ss setup to work correctly in some cases */
2090         atombios_set_encoder_crtc_source(encoder);
2091 }
2092
2093 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2094 {
2095         /* need to call this here as we need the crtc set up */
2096         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2097         radeon_atom_output_lock(encoder, false);
2098 }
2099
2100 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2101 {
2102         struct drm_device *dev = encoder->dev;
2103         struct radeon_device *rdev = dev->dev_private;
2104         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2105         struct radeon_encoder_atom_dig *dig;
2106
2107         /* check for pre-DCE3 cards with shared encoders;
2108          * can't really use the links individually, so don't disable
2109          * the encoder if it's in use by another connector
2110          */
2111         if (!ASIC_IS_DCE3(rdev)) {
2112                 struct drm_encoder *other_encoder;
2113                 struct radeon_encoder *other_radeon_encoder;
2114
2115                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2116                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2117                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2118                             drm_helper_encoder_in_use(other_encoder))
2119                                 goto disable_done;
2120                 }
2121         }
2122
2123         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2124
2125         switch (radeon_encoder->encoder_id) {
2126         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2127         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2128         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2129         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2130                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2131                 break;
2132         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2133         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2134         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2135         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2136                 /* handled in dpms */
2137                 break;
2138         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2139         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2140         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2141                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2142                 break;
2143         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2144         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2145         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2146         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2147                 atombios_dac_setup(encoder, ATOM_DISABLE);
2148                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2149                         atombios_tv_setup(encoder, ATOM_DISABLE);
2150                 break;
2151         }
2152
2153 disable_done:
2154         if (radeon_encoder_is_digital(encoder)) {
2155                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2156                         r600_hdmi_disable(encoder);
2157                 dig = radeon_encoder->enc_priv;
2158                 dig->dig_encoder = -1;
2159         }
2160         radeon_encoder->active_device = 0;
2161 }
2162
2163 /* these are handled by the primary encoders */
2164 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2165 {
2166
2167 }
2168
2169 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2170 {
2171
2172 }
2173
2174 static void
2175 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2176                          struct drm_display_mode *mode,
2177                          struct drm_display_mode *adjusted_mode)
2178 {
2179
2180 }
2181
2182 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2183 {
2184
2185 }
2186
2187 static void
2188 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2189 {
2190
2191 }
2192
2193 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2194                                        struct drm_display_mode *mode,
2195                                        struct drm_display_mode *adjusted_mode)
2196 {
2197         return true;
2198 }
2199
2200 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2201         .dpms = radeon_atom_ext_dpms,
2202         .mode_fixup = radeon_atom_ext_mode_fixup,
2203         .prepare = radeon_atom_ext_prepare,
2204         .mode_set = radeon_atom_ext_mode_set,
2205         .commit = radeon_atom_ext_commit,
2206         .disable = radeon_atom_ext_disable,
2207         /* no detect for TMDS/LVDS yet */
2208 };
2209
2210 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2211         .dpms = radeon_atom_encoder_dpms,
2212         .mode_fixup = radeon_atom_mode_fixup,
2213         .prepare = radeon_atom_encoder_prepare,
2214         .mode_set = radeon_atom_encoder_mode_set,
2215         .commit = radeon_atom_encoder_commit,
2216         .disable = radeon_atom_encoder_disable,
2217         .detect = radeon_atom_dig_detect,
2218 };
2219
2220 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2221         .dpms = radeon_atom_encoder_dpms,
2222         .mode_fixup = radeon_atom_mode_fixup,
2223         .prepare = radeon_atom_encoder_prepare,
2224         .mode_set = radeon_atom_encoder_mode_set,
2225         .commit = radeon_atom_encoder_commit,
2226         .detect = radeon_atom_dac_detect,
2227 };
2228
2229 void radeon_enc_destroy(struct drm_encoder *encoder)
2230 {
2231         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2232         kfree(radeon_encoder->enc_priv);
2233         drm_encoder_cleanup(encoder);
2234         kfree(radeon_encoder);
2235 }
2236
2237 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2238         .destroy = radeon_enc_destroy,
2239 };
2240
2241 struct radeon_encoder_atom_dac *
2242 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2243 {
2244         struct drm_device *dev = radeon_encoder->base.dev;
2245         struct radeon_device *rdev = dev->dev_private;
2246         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2247
2248         if (!dac)
2249                 return NULL;
2250
2251         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2252         return dac;
2253 }
2254
2255 struct radeon_encoder_atom_dig *
2256 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2257 {
2258         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2259         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2260
2261         if (!dig)
2262                 return NULL;
2263
2264         /* coherent mode by default */
2265         dig->coherent_mode = true;
2266         dig->dig_encoder = -1;
2267
2268         if (encoder_enum == 2)
2269                 dig->linkb = true;
2270         else
2271                 dig->linkb = false;
2272
2273         return dig;
2274 }
2275
2276 void
2277 radeon_add_atom_encoder(struct drm_device *dev,
2278                         uint32_t encoder_enum,
2279                         uint32_t supported_device,
2280                         u16 caps)
2281 {
2282         struct radeon_device *rdev = dev->dev_private;
2283         struct drm_encoder *encoder;
2284         struct radeon_encoder *radeon_encoder;
2285
2286         /* see if we already added it */
2287         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2288                 radeon_encoder = to_radeon_encoder(encoder);
2289                 if (radeon_encoder->encoder_enum == encoder_enum) {
2290                         radeon_encoder->devices |= supported_device;
2291                         return;
2292                 }
2293
2294         }
2295
2296         /* add a new one */
2297         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2298         if (!radeon_encoder)
2299                 return;
2300
2301         encoder = &radeon_encoder->base;
2302         switch (rdev->num_crtc) {
2303         case 1:
2304                 encoder->possible_crtcs = 0x1;
2305                 break;
2306         case 2:
2307         default:
2308                 encoder->possible_crtcs = 0x3;
2309                 break;
2310         case 4:
2311                 encoder->possible_crtcs = 0xf;
2312                 break;
2313         case 6:
2314                 encoder->possible_crtcs = 0x3f;
2315                 break;
2316         }
2317
2318         radeon_encoder->enc_priv = NULL;
2319
2320         radeon_encoder->encoder_enum = encoder_enum;
2321         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2322         radeon_encoder->devices = supported_device;
2323         radeon_encoder->rmx_type = RMX_OFF;
2324         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2325         radeon_encoder->is_ext_encoder = false;
2326         radeon_encoder->caps = caps;
2327
2328         switch (radeon_encoder->encoder_id) {
2329         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2330         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2332         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2333                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2334                         radeon_encoder->rmx_type = RMX_FULL;
2335                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2336                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2337                 } else {
2338                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2339                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2340                 }
2341                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2342                 break;
2343         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2344                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2345                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2346                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2347                 break;
2348         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2349         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2350         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2351                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2352                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2353                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2354                 break;
2355         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2356         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2357         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2358         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2359         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2360         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2361         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2362                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2363                         radeon_encoder->rmx_type = RMX_FULL;
2364                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2365                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2366                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2367                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2368                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2369                 } else {
2370                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2371                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2372                 }
2373                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2374                 break;
2375         case ENCODER_OBJECT_ID_SI170B:
2376         case ENCODER_OBJECT_ID_CH7303:
2377         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2378         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2379         case ENCODER_OBJECT_ID_TITFP513:
2380         case ENCODER_OBJECT_ID_VT1623:
2381         case ENCODER_OBJECT_ID_HDMI_SI1930:
2382         case ENCODER_OBJECT_ID_TRAVIS:
2383         case ENCODER_OBJECT_ID_NUTMEG:
2384                 /* these are handled by the primary encoders */
2385                 radeon_encoder->is_ext_encoder = true;
2386                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2387                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2388                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2389                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2390                 else
2391                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2392                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2393                 break;
2394         }
2395 }