drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.usOverscanRight = 0;
  48         args.usOverscanLeft = 0;
  49         args.usOverscanBottom = 0;
  50         args.usOverscanTop = 0;
  51         args.ucCRTC = radeon_crtc->crtc_id;
  52
  53         switch (radeon_crtc->rmx_type) {
  54         case RMX_CENTER:
  55                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  56                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  57                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  58                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  59                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  60                 break;
  61         case RMX_ASPECT:
  62                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  63                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  64
  65                 if (a1 > a2) {
  66                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  67                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  68                 } else if (a2 > a1) {
  69                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  70                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  71                 }
  72                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  73                 break;
  74         case RMX_FULL:
  75         default:
  76                 args.usOverscanRight = 0;
  77                 args.usOverscanLeft = 0;
  78                 args.usOverscanBottom = 0;
  79                 args.usOverscanTop = 0;
  80                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  81                 break;
  82         }
  83 }
  84
  85 static void atombios_scaler_setup(struct drm_crtc *crtc)
  86 {
  87         struct drm_device *dev = crtc->dev;
  88         struct radeon_device *rdev = dev->dev_private;
  89         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  90         ENABLE_SCALER_PS_ALLOCATION args;
  91         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  92
  93         /* fixme - fill in enc_priv for atom dac */
  94         enum radeon_tv_std tv_std = TV_STD_NTSC;
  95         bool is_tv = false, is_cv = false;
  96         struct drm_encoder *encoder;
  97
  98         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  99                 return;
 100
 101         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 102                 /* find tv std */
 103                 if (encoder->crtc == crtc) {
 104                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 105                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 106                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 107                                 tv_std = tv_dac->tv_std;
 108                                 is_tv = true;
 109                         }
 110                 }
 111         }
 112
 113         memset(&args, 0, sizeof(args));
 114
 115         args.ucScaler = radeon_crtc->crtc_id;
 116
 117         if (is_tv) {
 118                 switch (tv_std) {
 119                 case TV_STD_NTSC:
 120                 default:
 121                         args.ucTVStandard = ATOM_TV_NTSC;
 122                         break;
 123                 case TV_STD_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL;
 125                         break;
 126                 case TV_STD_PAL_M:
 127                         args.ucTVStandard = ATOM_TV_PALM;
 128                         break;
 129                 case TV_STD_PAL_60:
 130                         args.ucTVStandard = ATOM_TV_PAL60;
 131                         break;
 132                 case TV_STD_NTSC_J:
 133                         args.ucTVStandard = ATOM_TV_NTSCJ;
 134                         break;
 135                 case TV_STD_SCART_PAL:
 136                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 137                         break;
 138                 case TV_STD_SECAM:
 139                         args.ucTVStandard = ATOM_TV_SECAM;
 140                         break;
 141                 case TV_STD_PAL_CN:
 142                         args.ucTVStandard = ATOM_TV_PALCN;
 143                         break;
 144                 }
 145                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 146         } else if (is_cv) {
 147                 args.ucTVStandard = ATOM_TV_CV;
 148                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 149         } else {
 150                 switch (radeon_crtc->rmx_type) {
 151                 case RMX_FULL:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 case RMX_CENTER:
 155                         args.ucEnable = ATOM_SCALER_CENTER;
 156                         break;
 157                 case RMX_ASPECT:
 158                         args.ucEnable = ATOM_SCALER_EXPANSION;
 159                         break;
 160                 default:
 161                         if (ASIC_IS_AVIVO(rdev))
 162                                 args.ucEnable = ATOM_SCALER_DISABLE;
 163                         else
 164                                 args.ucEnable = ATOM_SCALER_CENTER;
 165                         break;
 166                 }
 167         }
 168         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 169         if ((is_tv || is_cv)
 170             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 171                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 172         }
 173 }
 174
 175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 176 {
 177         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 178         struct drm_device *dev = crtc->dev;
 179         struct radeon_device *rdev = dev->dev_private;
 180         int index =
 181             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 182         ENABLE_CRTC_PS_ALLOCATION args;
 183
 184         memset(&args, 0, sizeof(args));
 185
 186         args.ucCRTC = radeon_crtc->crtc_id;
 187         args.ucEnable = lock;
 188
 189         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 190 }
 191
 192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 193 {
 194         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 195         struct drm_device *dev = crtc->dev;
 196         struct radeon_device *rdev = dev->dev_private;
 197         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 198         ENABLE_CRTC_PS_ALLOCATION args;
 199
 200         memset(&args, 0, sizeof(args));
 201
 202         args.ucCRTC = radeon_crtc->crtc_id;
 203         args.ucEnable = state;
 204
 205         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 206 }
 207
 208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 209 {
 210         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 211         struct drm_device *dev = crtc->dev;
 212         struct radeon_device *rdev = dev->dev_private;
 213         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 214         ENABLE_CRTC_PS_ALLOCATION args;
 215
 216         memset(&args, 0, sizeof(args));
 217
 218         args.ucCRTC = radeon_crtc->crtc_id;
 219         args.ucEnable = state;
 220
 221         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 222 }
 223
 224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 225 {
 226         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 227         struct drm_device *dev = crtc->dev;
 228         struct radeon_device *rdev = dev->dev_private;
 229         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 230         BLANK_CRTC_PS_ALLOCATION args;
 231
 232         memset(&args, 0, sizeof(args));
 233
 234         args.ucCRTC = radeon_crtc->crtc_id;
 235         args.ucBlanking = state;
 236
 237         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 238 }
 239
 240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 241 {
 242         struct drm_device *dev = crtc->dev;
 243         struct radeon_device *rdev = dev->dev_private;
 244         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 245
 246         switch (mode) {
 247         case DRM_MODE_DPMS_ON:
 248                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 249                 if (ASIC_IS_DCE3(rdev))
 250                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 251                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 252                 /* XXX re-enable when interrupt support is added */
 253                 if (!ASIC_IS_DCE4(rdev))
 254                         drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 255                 radeon_crtc_load_lut(crtc);
 256                 break;
 257         case DRM_MODE_DPMS_STANDBY:
 258         case DRM_MODE_DPMS_SUSPEND:
 259         case DRM_MODE_DPMS_OFF:
 260                 /* XXX re-enable when interrupt support is added */
 261                 if (!ASIC_IS_DCE4(rdev))
 262                         drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 263                 atombios_blank_crtc(crtc, ATOM_ENABLE);
 264                 if (ASIC_IS_DCE3(rdev))
 265                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 266                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 267                 break;
 268         }
 269 }
 270
 271 static void
 272 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 273                              struct drm_display_mode *mode)
 274 {
 275         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 276         struct drm_device *dev = crtc->dev;
 277         struct radeon_device *rdev = dev->dev_private;
 278         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 279         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 280         u16 misc = 0;
 281
 282         memset(&args, 0, sizeof(args));
 283         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
 284         args.usH_Blanking_Time =
 285                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
 286         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
 287         args.usV_Blanking_Time =
 288             cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
 289         args.usH_SyncOffset =
 290                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
 291         args.usH_SyncWidth =
 292                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 293         args.usV_SyncOffset =
 294                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
 295         args.usV_SyncWidth =
 296                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 297         /*args.ucH_Border = mode->hborder;*/
 298         /*args.ucV_Border = mode->vborder;*/
 299
 300         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 301                 misc |= ATOM_VSYNC_POLARITY;
 302         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 303                 misc |= ATOM_HSYNC_POLARITY;
 304         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 305                 misc |= ATOM_COMPOSITESYNC;
 306         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 307                 misc |= ATOM_INTERLACE;
 308         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 309                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 310
 311         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 312         args.ucCRTC = radeon_crtc->crtc_id;
 313
 314         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 315 }
 316
 317 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 318                                      struct drm_display_mode *mode)
 319 {
 320         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 321         struct drm_device *dev = crtc->dev;
 322         struct radeon_device *rdev = dev->dev_private;
 323         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 324         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 325         u16 misc = 0;
 326
 327         memset(&args, 0, sizeof(args));
 328         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 329         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 330         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 331         args.usH_SyncWidth =
 332                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 333         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 334         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 335         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 336         args.usV_SyncWidth =
 337                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 338
 339         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 340                 misc |= ATOM_VSYNC_POLARITY;
 341         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 342                 misc |= ATOM_HSYNC_POLARITY;
 343         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 344                 misc |= ATOM_COMPOSITESYNC;
 345         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 346                 misc |= ATOM_INTERLACE;
 347         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 348                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 349
 350         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 351         args.ucCRTC = radeon_crtc->crtc_id;
 352
 353         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 354 }
 355
 356 static void atombios_disable_ss(struct drm_crtc *crtc)
 357 {
 358         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 359         struct drm_device *dev = crtc->dev;
 360         struct radeon_device *rdev = dev->dev_private;
 361         u32 ss_cntl;
 362
 363         if (ASIC_IS_DCE4(rdev)) {
 364                 switch (radeon_crtc->pll_id) {
 365                 case ATOM_PPLL1:
 366                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 367                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 368                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 369                         break;
 370                 case ATOM_PPLL2:
 371                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 372                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 373                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 374                         break;
 375                 case ATOM_DCPLL:
 376                 case ATOM_PPLL_INVALID:
 377                         return;
 378                 }
 379         } else if (ASIC_IS_AVIVO(rdev)) {
 380                 switch (radeon_crtc->pll_id) {
 381                 case ATOM_PPLL1:
 382                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 383                         ss_cntl &= ~1;
 384                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 385                         break;
 386                 case ATOM_PPLL2:
 387                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 388                         ss_cntl &= ~1;
 389                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 390                         break;
 391                 case ATOM_DCPLL:
 392                 case ATOM_PPLL_INVALID:
 393                         return;
 394                 }
 395         }
 396 }
 397
 398
 399 union atom_enable_ss {
 400         ENABLE_LVDS_SS_PARAMETERS legacy;
 401         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 402 };
 403
 404 static void atombios_enable_ss(struct drm_crtc *crtc)
 405 {
 406         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 407         struct drm_device *dev = crtc->dev;
 408         struct radeon_device *rdev = dev->dev_private;
 409         struct drm_encoder *encoder = NULL;
 410         struct radeon_encoder *radeon_encoder = NULL;
 411         struct radeon_encoder_atom_dig *dig = NULL;
 412         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 413         union atom_enable_ss args;
 414         uint16_t percentage = 0;
 415         uint8_t type = 0, step = 0, delay = 0, range = 0;
 416
 417         /* XXX add ss support for DCE4 */
 418         if (ASIC_IS_DCE4(rdev))
 419                 return;
 420
 421         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 422                 if (encoder->crtc == crtc) {
 423                         radeon_encoder = to_radeon_encoder(encoder);
 424                         /* only enable spread spectrum on LVDS */
 425                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 426                                 dig = radeon_encoder->enc_priv;
 427                                 if (dig && dig->ss) {
 428                                         percentage = dig->ss->percentage;
 429                                         type = dig->ss->type;
 430                                         step = dig->ss->step;
 431                                         delay = dig->ss->delay;
 432                                         range = dig->ss->range;
 433                                 } else
 434                                         return;
 435                         } else
 436                                 return;
 437                         break;
 438                 }
 439         }
 440
 441         if (!radeon_encoder)
 442                 return;
 443
 444         memset(&args, 0, sizeof(args));
 445         if (ASIC_IS_AVIVO(rdev)) {
 446                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 447                 args.v1.ucSpreadSpectrumType = type;
 448                 args.v1.ucSpreadSpectrumStep = step;
 449                 args.v1.ucSpreadSpectrumDelay = delay;
 450                 args.v1.ucSpreadSpectrumRange = range;
 451                 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 452                 args.v1.ucEnable = ATOM_ENABLE;
 453         } else {
 454                 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 455                 args.legacy.ucSpreadSpectrumType = type;
 456                 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
 457                 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
 458                 args.legacy.ucEnable = ATOM_ENABLE;
 459         }
 460         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 461 }
 462
 463 union adjust_pixel_clock {
 464         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 465         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 466 };
 467
 468 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 469                                struct drm_display_mode *mode,
 470                                struct radeon_pll *pll)
 471 {
 472         struct drm_device *dev = crtc->dev;
 473         struct radeon_device *rdev = dev->dev_private;
 474         struct drm_encoder *encoder = NULL;
 475         struct radeon_encoder *radeon_encoder = NULL;
 476         u32 adjusted_clock = mode->clock;
 477         int encoder_mode = 0;
 478
 479         /* reset the pll flags */
 480         pll->flags = 0;
 481
 482         /* select the PLL algo */
 483         if (ASIC_IS_AVIVO(rdev)) {
 484                 if (radeon_new_pll == 0)
 485                         pll->algo = PLL_ALGO_LEGACY;
 486                 else
 487                         pll->algo = PLL_ALGO_NEW;
 488         } else {
 489                 if (radeon_new_pll == 1)
 490                         pll->algo = PLL_ALGO_NEW;
 491                 else
 492                         pll->algo = PLL_ALGO_LEGACY;
 493         }
 494
 495         if (ASIC_IS_AVIVO(rdev)) {
 496                 if ((rdev->family == CHIP_RS600) ||
 497                     (rdev->family == CHIP_RS690) ||
 498                     (rdev->family == CHIP_RS740))
 499                         pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
 500                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 501
 502                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 503                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 504                 else
 505                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 506         } else {
 507                 pll->flags |= RADEON_PLL_LEGACY;
 508
 509                 if (mode->clock > 200000)       /* range limits??? */
 510                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 511                 else
 512                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 513
 514         }
 515
 516         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 517                 if (encoder->crtc == crtc) {
 518                         radeon_encoder = to_radeon_encoder(encoder);
 519                         encoder_mode = atombios_get_encoder_mode(encoder);
 520                         if (ASIC_IS_AVIVO(rdev)) {
 521                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 522                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 523                                         adjusted_clock = mode->clock * 2;
 524                         } else {
 525                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 526                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 527                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 528                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 529                         }
 530                         break;
 531                 }
 532         }
 533
 534         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 535          * accordingly based on the encoder/transmitter to work around
 536          * special hw requirements.
 537          */
 538         if (ASIC_IS_DCE3(rdev)) {
 539                 union adjust_pixel_clock args;
 540                 u8 frev, crev;
 541                 int index;
 542
 543                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 544                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 545                                       &crev);
 546
 547                 memset(&args, 0, sizeof(args));
 548
 549                 switch (frev) {
 550                 case 1:
 551                         switch (crev) {
 552                         case 1:
 553                         case 2:
 554                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 555                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 556                                 args.v1.ucEncodeMode = encoder_mode;
 557
 558                                 atom_execute_table(rdev->mode_info.atom_context,
 559                                                    index, (uint32_t *)&args);
 560                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 561                                 break;
 562                         case 3:
 563                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 564                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 565                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 566                                 args.v3.sInput.ucDispPllConfig = 0;
 567                                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 568                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 569
 570                                         if (encoder_mode == ATOM_ENCODER_MODE_DP)
 571                                                 args.v3.sInput.ucDispPllConfig |=
 572                                                         DISPPLL_CONFIG_COHERENT_MODE;
 573                                         else {
 574                                                 if (dig->coherent_mode)
 575                                                         args.v3.sInput.ucDispPllConfig |=
 576                                                                 DISPPLL_CONFIG_COHERENT_MODE;
 577                                                 if (mode->clock > 165000)
 578                                                         args.v3.sInput.ucDispPllConfig |=
 579                                                                 DISPPLL_CONFIG_DUAL_LINK;
 580                                         }
 581                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 582                                         /* may want to enable SS on DP/eDP eventually */
 583                                         args.v3.sInput.ucDispPllConfig |=
 584                                                 DISPPLL_CONFIG_SS_ENABLE;
 585                                         if (mode->clock > 165000)
 586                                                 args.v3.sInput.ucDispPllConfig |=
 587                                                         DISPPLL_CONFIG_DUAL_LINK;
 588                                 }
 589                                 atom_execute_table(rdev->mode_info.atom_context,
 590                                                    index, (uint32_t *)&args);
 591                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 592                                 if (args.v3.sOutput.ucRefDiv) {
 593                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 594                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 595                                 }
 596                                 if (args.v3.sOutput.ucPostDiv) {
 597                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 598                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 599                                 }
 600                                 break;
 601                         default:
 602                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 603                                 return adjusted_clock;
 604                         }
 605                         break;
 606                 default:
 607                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 608                         return adjusted_clock;
 609                 }
 610         }
 611         return adjusted_clock;
 612 }
 613
 614 union set_pixel_clock {
 615         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 616         PIXEL_CLOCK_PARAMETERS v1;
 617         PIXEL_CLOCK_PARAMETERS_V2 v2;
 618         PIXEL_CLOCK_PARAMETERS_V3 v3;
 619         PIXEL_CLOCK_PARAMETERS_V5 v5;
 620 };
 621
 622 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
 623 {
 624         struct drm_device *dev = crtc->dev;
 625         struct radeon_device *rdev = dev->dev_private;
 626         u8 frev, crev;
 627         int index;
 628         union set_pixel_clock args;
 629
 630         memset(&args, 0, sizeof(args));
 631
 632         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 633         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 634                               &crev);
 635
 636         switch (frev) {
 637         case 1:
 638                 switch (crev) {
 639                 case 5:
 640                         /* if the default dcpll clock is specified,
 641                          * SetPixelClock provides the dividers
 642                          */
 643                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 644                         args.v5.usPixelClock = rdev->clock.default_dispclk;
 645                         args.v5.ucPpll = ATOM_DCPLL;
 646                         break;
 647                 default:
 648                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 649                         return;
 650                 }
 651                 break;
 652         default:
 653                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 654                 return;
 655         }
 656         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 657 }
 658
 659 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 660 {
 661         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 662         struct drm_device *dev = crtc->dev;
 663         struct radeon_device *rdev = dev->dev_private;
 664         struct drm_encoder *encoder = NULL;
 665         struct radeon_encoder *radeon_encoder = NULL;
 666         u8 frev, crev;
 667         int index;
 668         union set_pixel_clock args;
 669         u32 pll_clock = mode->clock;
 670         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 671         struct radeon_pll *pll;
 672         u32 adjusted_clock;
 673         int encoder_mode = 0;
 674
 675         memset(&args, 0, sizeof(args));
 676
 677         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 678                 if (encoder->crtc == crtc) {
 679                         radeon_encoder = to_radeon_encoder(encoder);
 680                         encoder_mode = atombios_get_encoder_mode(encoder);
 681                         break;
 682                 }
 683         }
 684
 685         if (!radeon_encoder)
 686                 return;
 687
 688         switch (radeon_crtc->pll_id) {
 689         case ATOM_PPLL1:
 690                 pll = &rdev->clock.p1pll;
 691                 break;
 692         case ATOM_PPLL2:
 693                 pll = &rdev->clock.p2pll;
 694                 break;
 695         case ATOM_DCPLL:
 696         case ATOM_PPLL_INVALID:
 697                 pll = &rdev->clock.dcpll;
 698                 break;
 699         }
 700
 701         /* adjust pixel clock as needed */
 702         adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
 703
 704         radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
 705                            &ref_div, &post_div);
 706
 707         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 708         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 709                               &crev);
 710
 711         switch (frev) {
 712         case 1:
 713                 switch (crev) {
 714                 case 1:
 715                         args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 716                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 717                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 718                         args.v1.ucFracFbDiv = frac_fb_div;
 719                         args.v1.ucPostDiv = post_div;
 720                         args.v1.ucPpll = radeon_crtc->pll_id;
 721                         args.v1.ucCRTC = radeon_crtc->crtc_id;
 722                         args.v1.ucRefDivSrc = 1;
 723                         break;
 724                 case 2:
 725                         args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
 726                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 727                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 728                         args.v2.ucFracFbDiv = frac_fb_div;
 729                         args.v2.ucPostDiv = post_div;
 730                         args.v2.ucPpll = radeon_crtc->pll_id;
 731                         args.v2.ucCRTC = radeon_crtc->crtc_id;
 732                         args.v2.ucRefDivSrc = 1;
 733                         break;
 734                 case 3:
 735                         args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
 736                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 737                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 738                         args.v3.ucFracFbDiv = frac_fb_div;
 739                         args.v3.ucPostDiv = post_div;
 740                         args.v3.ucPpll = radeon_crtc->pll_id;
 741                         args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
 742                         args.v3.ucTransmitterId = radeon_encoder->encoder_id;
 743                         args.v3.ucEncoderMode = encoder_mode;
 744                         break;
 745                 case 5:
 746                         args.v5.ucCRTC = radeon_crtc->crtc_id;
 747                         args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
 748                         args.v5.ucRefDiv = ref_div;
 749                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 750                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 751                         args.v5.ucPostDiv = post_div;
 752                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 753                         args.v5.ucTransmitterID = radeon_encoder->encoder_id;
 754                         args.v5.ucEncoderMode = encoder_mode;
 755                         args.v5.ucPpll = radeon_crtc->pll_id;
 756                         break;
 757                 default:
 758                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 759                         return;
 760                 }
 761                 break;
 762         default:
 763                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 764                 return;
 765         }
 766
 767         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 768 }
 769
 770 static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 771                                    struct drm_framebuffer *old_fb)
 772 {
 773         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 774         struct drm_device *dev = crtc->dev;
 775         struct radeon_device *rdev = dev->dev_private;
 776         struct radeon_framebuffer *radeon_fb;
 777         struct drm_gem_object *obj;
 778         struct radeon_bo *rbo;
 779         uint64_t fb_location;
 780         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 781         int r;
 782
 783         /* no fb bound */
 784         if (!crtc->fb) {
 785                 DRM_DEBUG("No FB bound\n");
 786                 return 0;
 787         }
 788
 789         radeon_fb = to_radeon_framebuffer(crtc->fb);
 790
 791         /* Pin framebuffer & get tilling informations */
 792         obj = radeon_fb->obj;
 793         rbo = obj->driver_private;
 794         r = radeon_bo_reserve(rbo, false);
 795         if (unlikely(r != 0))
 796                 return r;
 797         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 798         if (unlikely(r != 0)) {
 799                 radeon_bo_unreserve(rbo);
 800                 return -EINVAL;
 801         }
 802         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 803         radeon_bo_unreserve(rbo);
 804
 805         switch (crtc->fb->bits_per_pixel) {
 806         case 8:
 807                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
 808                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
 809                 break;
 810         case 15:
 811                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 812                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
 813                 break;
 814         case 16:
 815                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 816                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
 817                 break;
 818         case 24:
 819         case 32:
 820                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
 821                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
 822                 break;
 823         default:
 824                 DRM_ERROR("Unsupported screen depth %d\n",
 825                           crtc->fb->bits_per_pixel);
 826                 return -EINVAL;
 827         }
 828
 829         switch (radeon_crtc->crtc_id) {
 830         case 0:
 831                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 832                 break;
 833         case 1:
 834                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 835                 break;
 836         case 2:
 837                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
 838                 break;
 839         case 3:
 840                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
 841                 break;
 842         case 4:
 843                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
 844                 break;
 845         case 5:
 846                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
 847                 break;
 848         default:
 849                 break;
 850         }
 851
 852         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 853                upper_32_bits(fb_location));
 854         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 855                upper_32_bits(fb_location));
 856         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 857                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 858         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 859                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 860         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 861
 862         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 863         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 864         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
 865         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 866         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
 867         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
 868
 869         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 870         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 871         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 872
 873         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 874                crtc->mode.vdisplay);
 875         x &= ~3;
 876         y &= ~1;
 877         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
 878                (x << 16) | y);
 879         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 880                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 881
 882         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 883                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
 884                        EVERGREEN_INTERLEAVE_EN);
 885         else
 886                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
 887
 888         if (old_fb && old_fb != crtc->fb) {
 889                 radeon_fb = to_radeon_framebuffer(old_fb);
 890                 rbo = radeon_fb->obj->driver_private;
 891                 r = radeon_bo_reserve(rbo, false);
 892                 if (unlikely(r != 0))
 893                         return r;
 894                 radeon_bo_unpin(rbo);
 895                 radeon_bo_unreserve(rbo);
 896         }
 897
 898         /* Bytes per pixel may have changed */
 899         radeon_bandwidth_update(rdev);
 900
 901         return 0;
 902 }
 903
 904 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 905                                struct drm_framebuffer *old_fb)
 906 {
 907         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 908         struct drm_device *dev = crtc->dev;
 909         struct radeon_device *rdev = dev->dev_private;
 910         struct radeon_framebuffer *radeon_fb;
 911         struct drm_gem_object *obj;
 912         struct radeon_bo *rbo;
 913         uint64_t fb_location;
 914         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 915         int r;
 916
 917         /* no fb bound */
 918         if (!crtc->fb) {
 919                 DRM_DEBUG("No FB bound\n");
 920                 return 0;
 921         }
 922
 923         radeon_fb = to_radeon_framebuffer(crtc->fb);
 924
 925         /* Pin framebuffer & get tilling informations */
 926         obj = radeon_fb->obj;
 927         rbo = obj->driver_private;
 928         r = radeon_bo_reserve(rbo, false);
 929         if (unlikely(r != 0))
 930                 return r;
 931         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 932         if (unlikely(r != 0)) {
 933                 radeon_bo_unreserve(rbo);
 934                 return -EINVAL;
 935         }
 936         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 937         radeon_bo_unreserve(rbo);
 938
 939         switch (crtc->fb->bits_per_pixel) {
 940         case 8:
 941                 fb_format =
 942                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
 943                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
 944                 break;
 945         case 15:
 946                 fb_format =
 947                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 948                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 949                 break;
 950         case 16:
 951                 fb_format =
 952                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 953                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 954                 break;
 955         case 24:
 956         case 32:
 957                 fb_format =
 958                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
 959                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 960                 break;
 961         default:
 962                 DRM_ERROR("Unsupported screen depth %d\n",
 963                           crtc->fb->bits_per_pixel);
 964                 return -EINVAL;
 965         }
 966
 967         if (tiling_flags & RADEON_TILING_MACRO)
 968                 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 969
 970         if (tiling_flags & RADEON_TILING_MICRO)
 971                 fb_format |= AVIVO_D1GRPH_TILED;
 972
 973         if (radeon_crtc->crtc_id == 0)
 974                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 975         else
 976                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 977
 978         if (rdev->family >= CHIP_RV770) {
 979                 if (radeon_crtc->crtc_id) {
 980                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 981                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
 982                 } else {
 983                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 984                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
 985                 }
 986         }
 987         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 988                (u32) fb_location);
 989         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
 990                radeon_crtc->crtc_offset, (u32) fb_location);
 991         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 992
 993         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 994         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 995         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
 996         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 997         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
 998         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
 999
1000         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1001         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1002         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1003
1004         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1005                crtc->mode.vdisplay);
1006         x &= ~3;
1007         y &= ~1;
1008         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1009                (x << 16) | y);
1010         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1011                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1012
1013         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1014                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1015                        AVIVO_D1MODE_INTERLEAVE_EN);
1016         else
1017                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1018
1019         if (old_fb && old_fb != crtc->fb) {
1020                 radeon_fb = to_radeon_framebuffer(old_fb);
1021                 rbo = radeon_fb->obj->driver_private;
1022                 r = radeon_bo_reserve(rbo, false);
1023                 if (unlikely(r != 0))
1024                         return r;
1025                 radeon_bo_unpin(rbo);
1026                 radeon_bo_unreserve(rbo);
1027         }
1028
1029         /* Bytes per pixel may have changed */
1030         radeon_bandwidth_update(rdev);
1031
1032         return 0;
1033 }
1034
1035 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1036                            struct drm_framebuffer *old_fb)
1037 {
1038         struct drm_device *dev = crtc->dev;
1039         struct radeon_device *rdev = dev->dev_private;
1040
1041         if (ASIC_IS_DCE4(rdev))
1042                 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1043         else if (ASIC_IS_AVIVO(rdev))
1044                 return avivo_crtc_set_base(crtc, x, y, old_fb);
1045         else
1046                 return radeon_crtc_set_base(crtc, x, y, old_fb);
1047 }
1048
1049 /* properly set additional regs when using atombios */
1050 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1051 {
1052         struct drm_device *dev = crtc->dev;
1053         struct radeon_device *rdev = dev->dev_private;
1054         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1055         u32 disp_merge_cntl;
1056
1057         switch (radeon_crtc->crtc_id) {
1058         case 0:
1059                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1060                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1061                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1062                 break;
1063         case 1:
1064                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1065                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1066                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1067                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1068                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1069                 break;
1070         }
1071 }
1072
1073 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1074 {
1075         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1076         struct drm_device *dev = crtc->dev;
1077         struct radeon_device *rdev = dev->dev_private;
1078         struct drm_encoder *test_encoder;
1079         struct drm_crtc *test_crtc;
1080         uint32_t pll_in_use = 0;
1081
1082         if (ASIC_IS_DCE4(rdev)) {
1083                 /* if crtc is driving DP and we have an ext clock, use that */
1084                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1085                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1086                                 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1087                                         if (rdev->clock.dp_extclk)
1088                                                 return ATOM_PPLL_INVALID;
1089                                 }
1090                         }
1091                 }
1092
1093                 /* otherwise, pick one of the plls */
1094                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1095                         struct radeon_crtc *radeon_test_crtc;
1096
1097                         if (crtc == test_crtc)
1098                                 continue;
1099
1100                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1101                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1102                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1103                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1104                 }
1105                 if (!(pll_in_use & 1))
1106                         return ATOM_PPLL1;
1107                 return ATOM_PPLL2;
1108         } else
1109                 return radeon_crtc->crtc_id;
1110
1111 }
1112
1113 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1114                            struct drm_display_mode *mode,
1115                            struct drm_display_mode *adjusted_mode,
1116                            int x, int y, struct drm_framebuffer *old_fb)
1117 {
1118         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1119         struct drm_device *dev = crtc->dev;
1120         struct radeon_device *rdev = dev->dev_private;
1121
1122         /* TODO color tiling */
1123
1124         atombios_disable_ss(crtc);
1125         /* always set DCPLL */
1126         if (ASIC_IS_DCE4(rdev))
1127                 atombios_crtc_set_dcpll(crtc);
1128         atombios_crtc_set_pll(crtc, adjusted_mode);
1129         atombios_enable_ss(crtc);
1130
1131         if (ASIC_IS_DCE4(rdev))
1132                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1133         else if (ASIC_IS_AVIVO(rdev))
1134                 atombios_crtc_set_timing(crtc, adjusted_mode);
1135         else {
1136                 atombios_crtc_set_timing(crtc, adjusted_mode);
1137                 if (radeon_crtc->crtc_id == 0)
1138                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1139                 radeon_legacy_atom_fixup(crtc);
1140         }
1141         atombios_crtc_set_base(crtc, x, y, old_fb);
1142         atombios_overscan_setup(crtc, mode, adjusted_mode);
1143         atombios_scaler_setup(crtc);
1144         return 0;
1145 }
1146
1147 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1148                                      struct drm_display_mode *mode,
1149                                      struct drm_display_mode *adjusted_mode)
1150 {
1151         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1152                 return false;
1153         return true;
1154 }
1155
1156 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1157 {
1158         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1159
1160         /* pick pll */
1161         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1162
1163         atombios_lock_crtc(crtc, ATOM_ENABLE);
1164         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1165 }
1166
1167 static void atombios_crtc_commit(struct drm_crtc *crtc)
1168 {
1169         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1170         atombios_lock_crtc(crtc, ATOM_DISABLE);
1171 }
1172
1173 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1174         .dpms = atombios_crtc_dpms,
1175         .mode_fixup = atombios_crtc_mode_fixup,
1176         .mode_set = atombios_crtc_mode_set,
1177         .mode_set_base = atombios_crtc_set_base,
1178         .prepare = atombios_crtc_prepare,
1179         .commit = atombios_crtc_commit,
1180         .load_lut = radeon_crtc_load_lut,
1181 };
1182
1183 void radeon_atombios_init_crtc(struct drm_device *dev,
1184                                struct radeon_crtc *radeon_crtc)
1185 {
1186         struct radeon_device *rdev = dev->dev_private;
1187
1188         if (ASIC_IS_DCE4(rdev)) {
1189                 switch (radeon_crtc->crtc_id) {
1190                 case 0:
1191                 default:
1192                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1193                         break;
1194                 case 1:
1195                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1196                         break;
1197                 case 2:
1198                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1199                         break;
1200                 case 3:
1201                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1202                         break;
1203                 case 4:
1204                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1205                         break;
1206                 case 5:
1207                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1208                         break;
1209                 }
1210         } else {
1211                 if (radeon_crtc->crtc_id == 1)
1212                         radeon_crtc->crtc_offset =
1213                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1214                 else
1215                         radeon_crtc->crtc_offset = 0;
1216         }
1217         radeon_crtc->pll_id = -1;
1218         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1219 }