2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 /****************************************************************************/
25 /*Portion I: Definitions shared between VBIOS and Driver */
26 /****************************************************************************/
32 #define ATOM_VERSION_MAJOR 0x00020000
33 #define ATOM_VERSION_MINOR 0x00000002
35 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
37 /* Endianness should be specified before inclusion,
38 * default to little endian
40 #ifndef ATOM_BIG_ENDIAN
41 #error Endian not specified
46 typedef unsigned long ULONG;
50 typedef unsigned char UCHAR;
54 typedef unsigned short USHORT;
60 #define ATOM_EXT_DAC 2
68 #define ATOM_CRTC_INVALID 0xFF
77 #define ATOM_EXT_PLL1 8
78 #define ATOM_EXT_PLL2 9
79 #define ATOM_EXT_CLOCK 10
80 #define ATOM_PPLL_INVALID 0xFF
82 #define ENCODER_REFCLK_SRC_P1PLL 0
83 #define ENCODER_REFCLK_SRC_P2PLL 1
84 #define ENCODER_REFCLK_SRC_DCPLL 2
85 #define ENCODER_REFCLK_SRC_EXTCLK 3
86 #define ENCODER_REFCLK_SRC_INVALID 0xFF
88 #define ATOM_SCALER1 0
89 #define ATOM_SCALER2 1
91 #define ATOM_SCALER_DISABLE 0
92 #define ATOM_SCALER_CENTER 1
93 #define ATOM_SCALER_EXPANSION 2
94 #define ATOM_SCALER_MULTI_EX 3
96 #define ATOM_DISABLE 0
98 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
99 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
100 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
101 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
102 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
103 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
104 #define ATOM_INIT (ATOM_DISABLE+7)
105 #define ATOM_GET_STATUS (ATOM_DISABLE+8)
107 #define ATOM_BLANKING 1
108 #define ATOM_BLANKING_OFF 0
110 #define ATOM_CURSOR1 0
111 #define ATOM_CURSOR2 1
119 #define ATOM_TV_NTSC 1
120 #define ATOM_TV_NTSCJ 2
121 #define ATOM_TV_PAL 3
122 #define ATOM_TV_PALM 4
123 #define ATOM_TV_PALCN 5
124 #define ATOM_TV_PALN 6
125 #define ATOM_TV_PAL60 7
126 #define ATOM_TV_SECAM 8
127 #define ATOM_TV_CV 16
129 #define ATOM_DAC1_PS2 1
130 #define ATOM_DAC1_CV 2
131 #define ATOM_DAC1_NTSC 3
132 #define ATOM_DAC1_PAL 4
134 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2
135 #define ATOM_DAC2_CV ATOM_DAC1_CV
136 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
137 #define ATOM_DAC2_PAL ATOM_DAC1_PAL
140 #define ATOM_PM_STANDBY 1
141 #define ATOM_PM_SUSPEND 2
142 #define ATOM_PM_OFF 3
144 /* Bit0:{=0:single, =1:dual},
145 Bit1 {=0:666RGB, =1:888RGB},
147 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
149 #define ATOM_PANEL_MISC_DUAL 0x00000001
150 #define ATOM_PANEL_MISC_888RGB 0x00000002
151 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
152 #define ATOM_PANEL_MISC_FPDI 0x00000010
153 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
154 #define ATOM_PANEL_MISC_SPATIAL 0x00000020
155 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040
156 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080
159 #define MEMTYPE_DDR1 "DDR1"
160 #define MEMTYPE_DDR2 "DDR2"
161 #define MEMTYPE_DDR3 "DDR3"
162 #define MEMTYPE_DDR4 "DDR4"
164 #define ASIC_BUS_TYPE_PCI "PCI"
165 #define ASIC_BUS_TYPE_AGP "AGP"
166 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
168 /* Maximum size of that FireGL flag string */
170 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
171 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
173 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
174 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
176 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
177 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
179 #define HW_ASSISTED_I2C_STATUS_FAILURE 2
180 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1
182 #pragma pack(1) /* BIOS data must use byte aligment */
184 /* Define offset to location of ROM header. */
186 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
187 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
189 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
190 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
191 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
192 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
194 /* Common header for all ROM Data tables.
195 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
196 And the pointer actually points to this header. */
198 typedef struct _ATOM_COMMON_TABLE_HEADER
200 USHORT usStructureSize;
201 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
202 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
203 /*Image can't be updated, while Driver needs to carry the new table! */
204 }ATOM_COMMON_TABLE_HEADER;
206 /****************************************************************************/
207 // Structure stores the ROM header.
208 /****************************************************************************/
209 typedef struct _ATOM_ROM_HEADER
211 ATOM_COMMON_TABLE_HEADER sHeader;
212 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
213 atombios should init it as "ATOM", don't change the position */
214 USHORT usBiosRuntimeSegmentAddress;
215 USHORT usProtectedModeInfoOffset;
216 USHORT usConfigFilenameOffset;
217 USHORT usCRC_BlockOffset;
218 USHORT usBIOS_BootupMessageOffset;
219 USHORT usInt10Offset;
220 USHORT usPciBusDevInitCode;
221 USHORT usIoBaseAddress;
222 USHORT usSubsystemVendorID;
223 USHORT usSubsystemID;
224 USHORT usPCI_InfoOffset;
225 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
226 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
227 UCHAR ucExtendedFunctionCode;
231 /*==============================Command Table Portion==================================== */
238 /****************************************************************************/
239 // Structures used in Command.mtb
240 /****************************************************************************/
241 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
242 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
243 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
244 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
245 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
246 USHORT DIGxEncoderControl; //Only used by Bios
247 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
248 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
249 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
250 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
251 USHORT GPIOPinControl; //Atomic Table, only used by Bios
252 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
253 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
254 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
255 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
256 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
257 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
258 USHORT MemoryPLLInit; //Atomic Table, used only by Bios
259 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
260 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
261 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
262 USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios
263 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
264 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
265 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
266 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
267 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
268 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
269 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
270 USHORT GetConditionalGoldenSetting; //Only used by Bios
271 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
272 USHORT PatchMCSetting; //only used by BIOS
273 USHORT MC_SEQ_Control; //only used by BIOS
274 USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
275 USHORT EnableScaler; //Atomic Table, used only by Bios
276 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
277 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
278 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
279 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
280 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
281 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
282 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
283 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
284 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
285 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
286 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
287 USHORT LUT_AutoFill; //Atomic Table, only used by Bios
288 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
289 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
290 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
291 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
292 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
293 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
294 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
295 USHORT MemoryCleanUp; //Atomic Table, only used by Bios
296 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
297 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
298 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
299 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
300 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
301 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
302 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
303 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
304 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
305 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
306 USHORT MemoryTraining; //Atomic Table, used only by Bios
307 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
308 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
309 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
310 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
311 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
312 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
313 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
314 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
315 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
316 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
317 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
318 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
319 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
320 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
321 USHORT DPEncoderService; //Function Table,only used by Bios
322 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
323 }ATOM_MASTER_LIST_OF_COMMAND_TABLES;
325 // For backward compatible
326 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
327 #define DPTranslatorControl DIG2EncoderControl
328 #define UNIPHYTransmitterControl DIG1TransmitterControl
329 #define LVTMATransmitterControl DIG2TransmitterControl
330 #define SetCRTC_DPM_State GetConditionalGoldenSetting
331 #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange
332 #define HPDInterruptService ReadHWAssistedI2CStatus
333 #define EnableVGA_Access GetSCLKOverMCLKRatio
334 #define EnableYUV GetDispObjectInfo
335 #define DynamicClockGating EnableDispPowerGating
336 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam
338 #define TMDSAEncoderControl PatchMCSetting
339 #define LVDSEncoderControl MC_SEQ_Control
340 #define LCD1OutputControl HW_Misc_Operation
343 typedef struct _ATOM_MASTER_COMMAND_TABLE
345 ATOM_COMMON_TABLE_HEADER sHeader;
346 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
347 }ATOM_MASTER_COMMAND_TABLE;
349 /****************************************************************************/
350 // Structures used in every command table
351 /****************************************************************************/
352 typedef struct _ATOM_TABLE_ATTRIBUTE
355 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
356 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
357 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
360 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
361 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
363 }ATOM_TABLE_ATTRIBUTE;
365 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
367 ATOM_TABLE_ATTRIBUTE sbfAccess;
369 }ATOM_TABLE_ATTRIBUTE_ACCESS;
371 /****************************************************************************/
372 // Common header for all command tables.
373 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
374 // And the pointer actually points to this header.
375 /****************************************************************************/
376 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
378 ATOM_COMMON_TABLE_HEADER CommonHeader;
379 ATOM_TABLE_ATTRIBUTE TableAttribute;
380 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
382 /****************************************************************************/
383 // Structures used by ComputeMemoryEnginePLLTable
384 /****************************************************************************/
385 #define COMPUTE_MEMORY_PLL_PARAM 1
386 #define COMPUTE_ENGINE_PLL_PARAM 2
387 #define ADJUST_MC_SETTING_PARAM 3
389 /****************************************************************************/
390 // Structures used by AdjustMemoryControllerTable
391 /****************************************************************************/
392 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
395 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
396 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
397 ULONG ulClockFreq:24;
399 ULONG ulClockFreq:24;
400 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
401 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
403 }ATOM_ADJUST_MEMORY_CLOCK_FREQ;
404 #define POINTER_RETURN_FLAG 0x80
406 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
408 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
409 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
410 UCHAR ucReserved; //may expand to return larger Fbdiv later
411 UCHAR ucFbDiv; //return value
412 UCHAR ucPostDiv; //return value
413 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
415 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
417 ULONG ulClock; //When return, [23:0] return real clock
418 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
419 USHORT usFbDiv; //return Feedback value to be written to register
420 UCHAR ucPostDiv; //return post div to be written to register
421 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
422 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
425 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
426 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
427 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
428 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
429 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
430 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
431 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
433 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
434 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
435 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
436 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
437 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
439 typedef struct _ATOM_COMPUTE_CLOCK_FREQ
442 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
443 ULONG ulClockFreq:24; // in unit of 10kHz
445 ULONG ulClockFreq:24; // in unit of 10kHz
446 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
448 }ATOM_COMPUTE_CLOCK_FREQ;
450 typedef struct _ATOM_S_MPLL_FB_DIVIDER
454 }ATOM_S_MPLL_FB_DIVIDER;
456 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
460 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
461 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
463 UCHAR ucRefDiv; //Output Parameter
464 UCHAR ucPostDiv; //Output Parameter
465 UCHAR ucCntlFlag; //Output Parameter
467 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
470 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
471 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
472 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
473 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
476 // V4 are only used for APU which PLL outside GPU
477 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
480 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
481 ULONG ulClock:24; //Input= target clock, output = actual clock
483 ULONG ulClock:24; //Input= target clock, output = actual clock
484 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
486 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
488 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
492 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
493 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
495 UCHAR ucRefDiv; //Output Parameter
496 UCHAR ucPostDiv; //Output Parameter
499 UCHAR ucCntlFlag; //Output Flags
500 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
503 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
506 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
508 // use for ComputeMemoryClockParamTable
509 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
514 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
516 UCHAR ucDllSpeed; //Output
517 UCHAR ucPostDiv; //Output
519 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
520 UCHAR ucPllCntlFlag; //Output:
523 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
525 // definition of ucInputFlag
526 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
527 // definition of ucPllCntlFlag
528 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
529 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
530 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
531 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
533 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
534 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
536 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
538 ATOM_COMPUTE_CLOCK_FREQ ulClock;
540 }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
542 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
544 ATOM_COMPUTE_CLOCK_FREQ ulClock;
547 }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
549 /****************************************************************************/
550 // Structures used by SetEngineClockTable
551 /****************************************************************************/
552 typedef struct _SET_ENGINE_CLOCK_PARAMETERS
554 ULONG ulTargetEngineClock; //In 10Khz unit
555 }SET_ENGINE_CLOCK_PARAMETERS;
557 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
559 ULONG ulTargetEngineClock; //In 10Khz unit
560 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
561 }SET_ENGINE_CLOCK_PS_ALLOCATION;
563 /****************************************************************************/
564 // Structures used by SetMemoryClockTable
565 /****************************************************************************/
566 typedef struct _SET_MEMORY_CLOCK_PARAMETERS
568 ULONG ulTargetMemoryClock; //In 10Khz unit
569 }SET_MEMORY_CLOCK_PARAMETERS;
571 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
573 ULONG ulTargetMemoryClock; //In 10Khz unit
574 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
575 }SET_MEMORY_CLOCK_PS_ALLOCATION;
577 /****************************************************************************/
578 // Structures used by ASIC_Init.ctb
579 /****************************************************************************/
580 typedef struct _ASIC_INIT_PARAMETERS
582 ULONG ulDefaultEngineClock; //In 10Khz unit
583 ULONG ulDefaultMemoryClock; //In 10Khz unit
584 }ASIC_INIT_PARAMETERS;
586 typedef struct _ASIC_INIT_PS_ALLOCATION
588 ASIC_INIT_PARAMETERS sASICInitClocks;
589 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
590 }ASIC_INIT_PS_ALLOCATION;
592 /****************************************************************************/
593 // Structure used by DynamicClockGatingTable.ctb
594 /****************************************************************************/
595 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
597 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
599 }DYNAMIC_CLOCK_GATING_PARAMETERS;
600 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
602 /****************************************************************************/
603 // Structure used by EnableDispPowerGatingTable.ctb
604 /****************************************************************************/
605 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
607 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
608 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
610 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
612 /****************************************************************************/
613 // Structure used by EnableASIC_StaticPwrMgtTable.ctb
614 /****************************************************************************/
615 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
617 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
619 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
620 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
622 /****************************************************************************/
623 // Structures used by DAC_LoadDetectionTable.ctb
624 /****************************************************************************/
625 typedef struct _DAC_LOAD_DETECTION_PARAMETERS
627 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
628 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
629 UCHAR ucMisc; //Valid only when table revision =1.3 and above
630 }DAC_LOAD_DETECTION_PARAMETERS;
632 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
633 #define DAC_LOAD_MISC_YPrPb 0x01
635 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
637 DAC_LOAD_DETECTION_PARAMETERS sDacload;
638 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
639 }DAC_LOAD_DETECTION_PS_ALLOCATION;
641 /****************************************************************************/
642 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
643 /****************************************************************************/
644 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
646 USHORT usPixelClock; // in 10KHz; for bios convenient
647 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
648 UCHAR ucAction; // 0: turn off encoder
649 // 1: setup and turn on encoder
650 // 7: ATOM_ENCODER_INIT Initialize DAC
651 }DAC_ENCODER_CONTROL_PARAMETERS;
653 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
655 /****************************************************************************/
656 // Structures used by DIG1EncoderControlTable
657 // DIG2EncoderControlTable
658 // ExternalEncoderControlTable
659 /****************************************************************************/
660 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
662 USHORT usPixelClock; // in 10KHz; for bios convenient
665 // =0: PHY linkA if bfLane<3
666 // =1: PHY linkB if bfLanes<3
667 // =0: PHY linkA+B if bfLanes=3
668 // [3] Transmitter Sel
669 // =0: UNIPHY or PCIEPHY
671 UCHAR ucAction; // =0: turn off encoder
672 // =1: turn on encoder
679 UCHAR ucLaneNum; // how many lanes to enable
681 }DIG_ENCODER_CONTROL_PARAMETERS;
682 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
683 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
686 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
687 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
688 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
689 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
690 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
691 #define ATOM_ENCODER_CONFIG_LINKA 0x00
692 #define ATOM_ENCODER_CONFIG_LINKB 0x04
693 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
694 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
695 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
696 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00
697 #define ATOM_ENCODER_CONFIG_LVTMA 0x08
698 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
699 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
700 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
702 // ATOM_ENABLE: Enable Encoder
703 // ATOM_DISABLE: Disable Encoder
706 #define ATOM_ENCODER_MODE_DP 0
707 #define ATOM_ENCODER_MODE_LVDS 1
708 #define ATOM_ENCODER_MODE_DVI 2
709 #define ATOM_ENCODER_MODE_HDMI 3
710 #define ATOM_ENCODER_MODE_SDVO 4
711 #define ATOM_ENCODER_MODE_DP_AUDIO 5
712 #define ATOM_ENCODER_MODE_TV 13
713 #define ATOM_ENCODER_MODE_CV 14
714 #define ATOM_ENCODER_MODE_CRT 15
715 #define ATOM_ENCODER_MODE_DVO 16
716 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
717 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
719 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
723 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
724 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
726 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
728 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
730 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
731 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
734 }ATOM_DIG_ENCODER_CONFIG_V2;
737 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
739 USHORT usPixelClock; // in 10KHz; for bios convenient
740 ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
748 UCHAR ucLaneNum; // how many lanes to enable
749 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
751 }DIG_ENCODER_CONTROL_PARAMETERS_V2;
754 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
755 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
756 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
757 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
758 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
759 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
760 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
761 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
762 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
763 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
768 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
769 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
770 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
771 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
772 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
773 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
774 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
775 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
776 #define ATOM_ENCODER_CMD_SETUP 0x0f
777 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
780 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
781 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
783 //ucTableFormatRevision=1
784 //ucTableContentRevision=3
785 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
786 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
790 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
792 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
794 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
796 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
799 }ATOM_DIG_ENCODER_CONFIG_V3;
801 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
802 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
803 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
804 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
805 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
806 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
807 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
808 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
809 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
810 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
812 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
814 USHORT usPixelClock; // in 10KHz; for bios convenient
815 ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
825 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
828 // =0x11: internal DP1 for NutMeg/Travis DP translator
830 UCHAR ucLaneNum; // how many lanes to enable
831 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
833 }DIG_ENCODER_CONTROL_PARAMETERS_V3;
835 //ucTableFormatRevision=1
836 //ucTableContentRevision=4
838 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
839 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
843 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
845 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
847 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
849 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
852 }ATOM_DIG_ENCODER_CONFIG_V4;
854 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
855 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
856 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
857 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
858 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
859 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
860 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
861 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
862 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
863 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
864 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
865 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
866 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
868 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
870 USHORT usPixelClock; // in 10KHz; for bios convenient
872 ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
884 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
887 // =0x11: internal DP1 for NutMeg/Travis DP translator
889 UCHAR ucLaneNum; // how many lanes to enable
890 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
891 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
892 }DIG_ENCODER_CONTROL_PARAMETERS_V4;
894 // define ucBitPerColor:
895 #define PANEL_BPC_UNDEFINE 0x00
896 #define PANEL_6BIT_PER_COLOR 0x01
897 #define PANEL_8BIT_PER_COLOR 0x02
898 #define PANEL_10BIT_PER_COLOR 0x03
899 #define PANEL_12BIT_PER_COLOR 0x04
900 #define PANEL_16BIT_PER_COLOR 0x05
903 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
904 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
905 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
907 /****************************************************************************/
908 // Structures used by UNIPHYTransmitterControlTable
909 // LVTMATransmitterControlTable
910 // DVOOutputControlTable
911 /****************************************************************************/
912 typedef struct _ATOM_DP_VS_MODE
918 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
922 USHORT usPixelClock; // in 10KHz; for bios convenient
923 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
924 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
927 // [0]=0: 4 lane Link,
928 // =1: 8 lane Link ( Dual Links TMDS )
929 // [1]=0: InCoherent mode
932 // =0: PHY linkA if bfLane<3
933 // =1: PHY linkB if bfLanes<3
934 // =0: PHY linkA+B if bfLanes=3
935 // [5:4]PCIE lane Sel
936 // =0: lane 0~3 or 0~7
938 // =2: lane 8~11 or 8~15
940 UCHAR ucAction; // =0: turn off encoder
941 // =1: turn on encoder
943 }DIG_TRANSMITTER_CONTROL_PARAMETERS;
945 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
948 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
951 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
952 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
953 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
954 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
955 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
956 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
957 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
959 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
960 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
961 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
963 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
964 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
965 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
966 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
967 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
968 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
969 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
970 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
971 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
972 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
973 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
976 #define ATOM_TRANSMITTER_ACTION_DISABLE 0
977 #define ATOM_TRANSMITTER_ACTION_ENABLE 1
978 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
979 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
980 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
981 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
982 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
983 #define ATOM_TRANSMITTER_ACTION_INIT 7
984 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
985 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
986 #define ATOM_TRANSMITTER_ACTION_SETUP 10
987 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
988 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12
989 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
991 // Following are used for DigTransmitterControlTable ver1.2
992 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
995 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
996 // =1 Dig Transmitter 2 ( Uniphy CD )
997 // =2 Dig Transmitter 3 ( Uniphy EF )
999 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1000 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1001 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1002 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1004 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1005 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1007 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1008 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1009 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1010 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1011 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1012 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1014 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1015 // =1 Dig Transmitter 2 ( Uniphy CD )
1016 // =2 Dig Transmitter 3 ( Uniphy EF )
1018 }ATOM_DIG_TRANSMITTER_CONFIG_V2;
1022 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
1025 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
1028 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
1029 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
1030 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
1033 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
1034 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1035 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1038 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
1041 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
1042 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
1043 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
1044 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
1046 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
1050 USHORT usPixelClock; // in 10KHz; for bios convenient
1051 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1052 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1054 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1055 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1056 UCHAR ucReserved[4];
1057 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1059 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1062 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1063 // =1 Dig Transmitter 2 ( Uniphy CD )
1064 // =2 Dig Transmitter 3 ( Uniphy EF )
1065 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1066 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1067 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1068 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1069 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1070 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1072 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1073 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1074 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1075 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1076 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1077 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1078 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1079 // =1 Dig Transmitter 2 ( Uniphy CD )
1080 // =2 Dig Transmitter 3 ( Uniphy EF )
1082 }ATOM_DIG_TRANSMITTER_CONFIG_V3;
1085 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
1089 USHORT usPixelClock; // in 10KHz; for bios convenient
1090 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1091 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1093 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
1094 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1096 UCHAR ucReserved[3];
1097 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
1101 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
1104 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
1107 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
1108 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
1109 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
1112 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
1113 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
1114 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
1117 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
1118 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
1119 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
1120 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
1123 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
1124 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
1125 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
1126 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
1129 /****************************************************************************/
1130 // Structures used by UNIPHYTransmitterControlTable V1.4
1131 // ASIC Families: NI
1132 // ucTableFormatRevision=1
1133 // ucTableContentRevision=4
1134 /****************************************************************************/
1135 typedef struct _ATOM_DP_VS_MODE_V4
1143 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1144 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1145 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1147 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1148 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1149 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1153 }ATOM_DP_VS_MODE_V4;
1155 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1158 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1159 // =1 Dig Transmitter 2 ( Uniphy CD )
1160 // =2 Dig Transmitter 3 ( Uniphy EF )
1161 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1162 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1163 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1164 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1165 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1166 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1168 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1169 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1170 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1171 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1172 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1173 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1174 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1175 // =1 Dig Transmitter 2 ( Uniphy CD )
1176 // =2 Dig Transmitter 3 ( Uniphy EF )
1178 }ATOM_DIG_TRANSMITTER_CONFIG_V4;
1180 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1184 USHORT usPixelClock; // in 10KHz; for bios convenient
1185 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1186 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1190 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1193 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1195 UCHAR ucReserved[3];
1196 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1200 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
1202 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
1204 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
1205 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
1206 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
1208 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
1209 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
1210 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
1212 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
1213 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
1214 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
1215 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
1216 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
1218 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
1219 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
1220 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
1221 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
1224 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
1229 UCHAR ucPhyClkSrcId:2;
1230 UCHAR ucCoherentMode:1;
1234 UCHAR ucCoherentMode:1;
1235 UCHAR ucPhyClkSrcId:2;
1239 }ATOM_DIG_TRANSMITTER_CONFIG_V5;
1241 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1243 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1244 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1245 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1246 UCHAR ucLaneNum; // indicate lane number 1-8
1247 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1248 UCHAR ucDigMode; // indicate DIG mode
1250 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1253 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1257 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
1260 #define ATOM_PHY_ID_UNIPHYA 0
1261 #define ATOM_PHY_ID_UNIPHYB 1
1262 #define ATOM_PHY_ID_UNIPHYC 2
1263 #define ATOM_PHY_ID_UNIPHYD 3
1264 #define ATOM_PHY_ID_UNIPHYE 4
1265 #define ATOM_PHY_ID_UNIPHYF 5
1266 #define ATOM_PHY_ID_UNIPHYG 6
1269 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
1270 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
1271 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
1272 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
1273 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
1274 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
1275 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
1278 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
1279 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1280 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1281 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
1282 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1283 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
1286 #define DP_LANE_SET__0DB_0_4V 0x00
1287 #define DP_LANE_SET__0DB_0_6V 0x01
1288 #define DP_LANE_SET__0DB_0_8V 0x02
1289 #define DP_LANE_SET__0DB_1_2V 0x03
1290 #define DP_LANE_SET__3_5DB_0_4V 0x08
1291 #define DP_LANE_SET__3_5DB_0_6V 0x09
1292 #define DP_LANE_SET__3_5DB_0_8V 0x0a
1293 #define DP_LANE_SET__6DB_0_4V 0x10
1294 #define DP_LANE_SET__6DB_0_6V 0x11
1295 #define DP_LANE_SET__9_5DB_0_4V 0x18
1297 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1299 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
1302 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
1303 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
1305 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
1306 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
1307 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
1308 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
1310 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
1311 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
1313 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
1314 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
1315 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
1316 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
1317 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
1318 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
1319 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
1321 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1324 /****************************************************************************/
1325 // Structures used by ExternalEncoderControlTable V1.3
1326 // ASIC Families: Evergreen, Llano, NI
1327 // ucTableFormatRevision=1
1328 // ucTableContentRevision=3
1329 /****************************************************************************/
1331 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1334 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1335 USHORT usConnectorId; // connector id, valid when ucAction = INIT
1337 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1339 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1340 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1341 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1343 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1346 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
1347 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
1348 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
1349 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
1350 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1351 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1352 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1353 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1356 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
1357 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
1358 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
1359 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
1360 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70
1361 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
1362 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
1363 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
1365 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1367 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1368 ULONG ulReserved[2];
1369 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1372 /****************************************************************************/
1373 // Structures used by DAC1OuputControlTable
1374 // DAC2OuputControlTable
1375 // LVTMAOutputControlTable (Before DEC30)
1376 // TMDSAOutputControlTable (Before DEC30)
1377 /****************************************************************************/
1378 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1380 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1381 // When the display is LCD, in addition to above:
1382 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1383 // ATOM_LCD_SELFTEST_STOP
1385 UCHAR aucPadding[3]; // padding to DWORD aligned
1386 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1388 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1391 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1392 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1394 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1395 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1397 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1398 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1400 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1401 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1403 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1404 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1406 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1407 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1409 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1410 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1412 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1413 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1414 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
1416 /****************************************************************************/
1417 // Structures used by BlankCRTCTable
1418 /****************************************************************************/
1419 typedef struct _BLANK_CRTC_PARAMETERS
1421 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1422 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1423 USHORT usBlackColorRCr;
1424 USHORT usBlackColorGY;
1425 USHORT usBlackColorBCb;
1426 }BLANK_CRTC_PARAMETERS;
1427 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
1429 /****************************************************************************/
1430 // Structures used by EnableCRTCTable
1431 // EnableCRTCMemReqTable
1432 // UpdateCRTC_DoubleBufferRegistersTable
1433 /****************************************************************************/
1434 typedef struct _ENABLE_CRTC_PARAMETERS
1436 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1437 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1439 }ENABLE_CRTC_PARAMETERS;
1440 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
1442 /****************************************************************************/
1443 // Structures used by SetCRTC_OverScanTable
1444 /****************************************************************************/
1445 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1447 USHORT usOverscanRight; // right
1448 USHORT usOverscanLeft; // left
1449 USHORT usOverscanBottom; // bottom
1450 USHORT usOverscanTop; // top
1451 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1453 }SET_CRTC_OVERSCAN_PARAMETERS;
1454 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
1456 /****************************************************************************/
1457 // Structures used by SetCRTC_ReplicationTable
1458 /****************************************************************************/
1459 typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1461 UCHAR ucH_Replication; // horizontal replication
1462 UCHAR ucV_Replication; // vertical replication
1463 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1465 }SET_CRTC_REPLICATION_PARAMETERS;
1466 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
1468 /****************************************************************************/
1469 // Structures used by SelectCRTC_SourceTable
1470 /****************************************************************************/
1471 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1473 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1474 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1476 }SELECT_CRTC_SOURCE_PARAMETERS;
1477 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
1479 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1481 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1482 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1483 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1485 }SELECT_CRTC_SOURCE_PARAMETERS_V2;
1488 //#define ASIC_INT_DAC1_ENCODER_ID 0x00
1489 //#define ASIC_INT_TV_ENCODER_ID 0x02
1490 //#define ASIC_INT_DIG1_ENCODER_ID 0x03
1491 //#define ASIC_INT_DAC2_ENCODER_ID 0x04
1492 //#define ASIC_EXT_TV_ENCODER_ID 0x06
1493 //#define ASIC_INT_DVO_ENCODER_ID 0x07
1494 //#define ASIC_INT_DIG2_ENCODER_ID 0x09
1495 //#define ASIC_EXT_DIG_ENCODER_ID 0x05
1498 //#define ATOM_ENCODER_MODE_DP 0
1499 //#define ATOM_ENCODER_MODE_LVDS 1
1500 //#define ATOM_ENCODER_MODE_DVI 2
1501 //#define ATOM_ENCODER_MODE_HDMI 3
1502 //#define ATOM_ENCODER_MODE_SDVO 4
1503 //#define ATOM_ENCODER_MODE_TV 13
1504 //#define ATOM_ENCODER_MODE_CV 14
1505 //#define ATOM_ENCODER_MODE_CRT 15
1507 /****************************************************************************/
1508 // Structures used by SetPixelClockTable
1509 // GetPixelClockTable
1510 /****************************************************************************/
1511 //Major revision=1., Minor revision=1
1512 typedef struct _PIXEL_CLOCK_PARAMETERS
1514 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1515 // 0 means disable PPLL
1516 USHORT usRefDiv; // Reference divider
1517 USHORT usFbDiv; // feedback divider
1518 UCHAR ucPostDiv; // post divider
1519 UCHAR ucFracFbDiv; // fractional feedback divider
1520 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1521 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1522 UCHAR ucCRTC; // Which CRTC uses this Ppll
1524 }PIXEL_CLOCK_PARAMETERS;
1526 //Major revision=1., Minor revision=2, add ucMiscIfno
1528 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1529 #define MISC_DEVICE_INDEX_MASK 0xF0
1530 #define MISC_DEVICE_INDEX_SHIFT 4
1532 typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1534 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1535 // 0 means disable PPLL
1536 USHORT usRefDiv; // Reference divider
1537 USHORT usFbDiv; // feedback divider
1538 UCHAR ucPostDiv; // post divider
1539 UCHAR ucFracFbDiv; // fractional feedback divider
1540 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1541 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1542 UCHAR ucCRTC; // Which CRTC uses this Ppll
1543 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1544 }PIXEL_CLOCK_PARAMETERS_V2;
1546 //Major revision=1., Minor revision=3, structure/definition change
1548 //ATOM_ENCODER_MODE_DP
1549 //ATOM_ENOCDER_MODE_LVDS
1550 //ATOM_ENOCDER_MODE_DVI
1551 //ATOM_ENOCDER_MODE_HDMI
1552 //ATOM_ENOCDER_MODE_SDVO
1553 //ATOM_ENCODER_MODE_TV 13
1554 //ATOM_ENCODER_MODE_CV 14
1555 //ATOM_ENCODER_MODE_CRT 15
1558 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
1559 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
1560 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
1561 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
1562 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
1563 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
1564 //#define DVO_ENCODER_CONFIG_24BIT 0x08
1566 //ucMiscInfo: also changed, see below
1567 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
1568 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02
1569 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
1570 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
1571 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
1572 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
1573 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
1574 // V1.4 for RoadRunner
1575 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
1576 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1579 typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1581 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1582 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1583 USHORT usRefDiv; // Reference divider
1584 USHORT usFbDiv; // feedback divider
1585 UCHAR ucPostDiv; // post divider
1586 UCHAR ucFracFbDiv; // fractional feedback divider
1587 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1588 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1591 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1592 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1594 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1595 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1596 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1597 }PIXEL_CLOCK_PARAMETERS_V3;
1599 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
1600 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
1602 typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1604 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1605 // drive the pixel clock. not used for DCPLL case.
1608 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1610 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1611 // 0 means disable PPLL/DCPLL.
1612 USHORT usFbDiv; // feedback divider integer part.
1613 UCHAR ucPostDiv; // post divider.
1614 UCHAR ucRefDiv; // Reference divider
1615 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1616 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1617 // indicate which graphic encoder will be used.
1618 UCHAR ucEncoderMode; // Encoder mode:
1619 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1620 // bit[1]= when VGA timing is used.
1621 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1622 // bit[4]= RefClock source for PPLL.
1623 // =0: XTLAIN( default mode )
1624 // =1: other external clock source, which is pre-defined
1625 // by VBIOS depend on the feature required.
1626 // bit[7:5]: reserved.
1627 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1629 }PIXEL_CLOCK_PARAMETERS_V5;
1631 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
1632 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
1633 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
1634 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
1635 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
1636 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
1637 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
1639 typedef struct _CRTC_PIXEL_CLOCK_FREQ
1642 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1643 // drive the pixel clock. not used for DCPLL case.
1644 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1645 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1647 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1648 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1649 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1650 // drive the pixel clock. not used for DCPLL case.
1652 }CRTC_PIXEL_CLOCK_FREQ;
1654 typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1657 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
1658 ULONG ulDispEngClkFreq; // dispclk frequency
1660 USHORT usFbDiv; // feedback divider integer part.
1661 UCHAR ucPostDiv; // post divider.
1662 UCHAR ucRefDiv; // Reference divider
1663 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1664 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1665 // indicate which graphic encoder will be used.
1666 UCHAR ucEncoderMode; // Encoder mode:
1667 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1668 // bit[1]= when VGA timing is used.
1669 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1670 // bit[4]= RefClock source for PPLL.
1671 // =0: XTLAIN( default mode )
1672 // =1: other external clock source, which is pre-defined
1673 // by VBIOS depend on the feature required.
1674 // bit[7:5]: reserved.
1675 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1677 }PIXEL_CLOCK_PARAMETERS_V6;
1679 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
1680 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
1681 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1682 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1683 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1684 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1685 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1686 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1688 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1690 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1691 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1693 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1696 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1697 UCHAR ucReserved[2];
1698 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
1700 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
1702 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
1703 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
1705 /****************************************************************************/
1706 // Structures used by AdjustDisplayPllTable
1707 /****************************************************************************/
1708 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
1710 USHORT usPixelClock;
1711 UCHAR ucTransmitterID;
1715 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
1716 UCHAR ucConfig; //if none DVO, not defined yet
1718 UCHAR ucReserved[3];
1719 }ADJUST_DISPLAY_PLL_PARAMETERS;
1721 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
1722 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
1724 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
1726 USHORT usPixelClock; // target pixel clock
1727 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1728 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1729 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1730 UCHAR ucExtTransmitterID; // external encoder id.
1731 UCHAR ucReserved[2];
1732 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
1734 // usDispPllConfig v1.2 for RoadRunner
1735 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
1736 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
1737 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
1738 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
1739 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
1740 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
1741 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
1742 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
1743 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
1744 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
1747 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
1749 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1750 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1751 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1752 UCHAR ucReserved[2];
1753 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
1755 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
1759 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
1760 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
1762 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
1764 /****************************************************************************/
1765 // Structures used by EnableYUVTable
1766 /****************************************************************************/
1767 typedef struct _ENABLE_YUV_PARAMETERS
1769 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1770 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1772 }ENABLE_YUV_PARAMETERS;
1773 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
1775 /****************************************************************************/
1776 // Structures used by GetMemoryClockTable
1777 /****************************************************************************/
1778 typedef struct _GET_MEMORY_CLOCK_PARAMETERS
1780 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1781 } GET_MEMORY_CLOCK_PARAMETERS;
1782 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
1784 /****************************************************************************/
1785 // Structures used by GetEngineClockTable
1786 /****************************************************************************/
1787 typedef struct _GET_ENGINE_CLOCK_PARAMETERS
1789 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1790 } GET_ENGINE_CLOCK_PARAMETERS;
1791 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
1793 /****************************************************************************/
1794 // Following Structures and constant may be obsolete
1795 /****************************************************************************/
1796 //Maxium 8 bytes,the data read in will be placed in the parameter space.
1797 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1798 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1800 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1801 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID
1802 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
1803 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
1804 UCHAR ucSlaveAddr; //Read from which slave
1805 UCHAR ucLineNumber; //Read from which HW assisted line
1806 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
1807 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1810 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
1811 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
1812 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
1813 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
1814 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
1816 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1818 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1819 USHORT usByteOffset; //Write to which byte
1820 //Upper portion of usByteOffset is Format of data
1825 //blockID+counterID+offsetID
1826 UCHAR ucData; //PS data1
1827 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1828 UCHAR ucSlaveAddr; //Write to which slave
1829 UCHAR ucLineNumber; //Write from which HW assisted line
1830 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
1832 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1834 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
1836 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1837 UCHAR ucSlaveAddr; //Write to which slave
1838 UCHAR ucLineNumber; //Write from which HW assisted line
1839 }SET_UP_HW_I2C_DATA_PARAMETERS;
1842 /**************************************************************************/
1843 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1846 /****************************************************************************/
1847 // Structures used by PowerConnectorDetectionTable
1848 /****************************************************************************/
1849 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
1851 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1852 UCHAR ucPwrBehaviorId;
1853 USHORT usPwrBudget; //how much power currently boot to in unit of watt
1854 }POWER_CONNECTOR_DETECTION_PARAMETERS;
1856 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
1858 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1860 USHORT usPwrBudget; //how much power currently boot to in unit of watt
1861 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1862 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
1864 /****************************LVDS SS Command Table Definitions**********************/
1866 /****************************************************************************/
1867 // Structures used by EnableSpreadSpectrumOnPPLLTable
1868 /****************************************************************************/
1869 typedef struct _ENABLE_LVDS_SS_PARAMETERS
1871 USHORT usSpreadSpectrumPercentage;
1872 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1873 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1874 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1876 }ENABLE_LVDS_SS_PARAMETERS;
1878 //ucTableFormatRevision=1,ucTableContentRevision=2
1879 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
1881 USHORT usSpreadSpectrumPercentage;
1882 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1883 UCHAR ucSpreadSpectrumStep; //
1884 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1885 UCHAR ucSpreadSpectrumDelay;
1886 UCHAR ucSpreadSpectrumRange;
1888 }ENABLE_LVDS_SS_PARAMETERS_V2;
1890 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
1891 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
1893 USHORT usSpreadSpectrumPercentage;
1894 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1895 UCHAR ucSpreadSpectrumStep; //
1896 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1897 UCHAR ucSpreadSpectrumDelay;
1898 UCHAR ucSpreadSpectrumRange;
1899 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
1900 }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
1902 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
1904 USHORT usSpreadSpectrumPercentage;
1905 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1906 // Bit[1]: 1-Ext. 0-Int.
1907 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1908 // Bits[7:4] reserved
1909 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1910 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1911 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1912 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
1914 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
1915 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
1916 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
1917 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
1918 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
1919 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
1920 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
1921 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
1922 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
1923 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
1924 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
1927 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
1929 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
1930 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1931 // Bit[1]: 1-Ext. 0-Int.
1932 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1933 // Bits[7:4] reserved
1934 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1935 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1936 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1937 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
1939 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
1940 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
1941 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
1942 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
1943 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
1944 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
1945 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
1946 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
1947 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
1948 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
1949 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
1950 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
1952 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
1954 /**************************************************************************/
1956 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
1958 PIXEL_CLOCK_PARAMETERS sPCLKInput;
1959 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
1960 }SET_PIXEL_CLOCK_PS_ALLOCATION;
1962 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
1964 /****************************************************************************/
1965 // Structures used by ###
1966 /****************************************************************************/
1967 typedef struct _MEMORY_TRAINING_PARAMETERS
1969 ULONG ulTargetMemoryClock; //In 10Khz unit
1970 }MEMORY_TRAINING_PARAMETERS;
1971 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
1974 /****************************LVDS and other encoder command table definitions **********************/
1977 /****************************************************************************/
1978 // Structures used by LVDSEncoderControlTable (Before DCE30)
1979 // LVTMAEncoderControlTable (Before DCE30)
1980 // TMDSAEncoderControlTable (Before DCE30)
1981 /****************************************************************************/
1982 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
1984 USHORT usPixelClock; // in 10KHz; for bios convenient
1985 UCHAR ucMisc; // bit0=0: Enable single link
1986 // =1: Enable dual link
1989 UCHAR ucAction; // 0: turn off encoder
1990 // 1: setup and turn on encoder
1991 }LVDS_ENCODER_CONTROL_PARAMETERS;
1993 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
1995 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
1996 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
1998 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
1999 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2002 //ucTableFormatRevision=1,ucTableContentRevision=2
2003 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
2005 USHORT usPixelClock; // in 10KHz; for bios convenient
2006 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2007 UCHAR ucAction; // 0: turn off encoder
2008 // 1: setup and turn on encoder
2009 UCHAR ucTruncate; // bit0=0: Disable truncate
2010 // =1: Enable truncate
2013 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2014 // =1: Enable spatial dithering
2017 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2018 // =1: Enable temporal dithering
2021 // bit5=0: Gray level 2
2023 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2024 // =1: 25FRC_SEL pattern F
2025 // bit6:5=0: 50FRC_SEL pattern A
2026 // =1: 50FRC_SEL pattern B
2027 // =2: 50FRC_SEL pattern C
2028 // =3: 50FRC_SEL pattern D
2029 // bit7=0: 75FRC_SEL pattern E
2030 // =1: 75FRC_SEL pattern F
2031 }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
2033 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2035 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2036 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2038 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2039 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2041 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2042 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2044 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2045 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2047 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2048 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2050 /****************************************************************************/
2051 // Structures used by ###
2052 /****************************************************************************/
2053 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
2055 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2056 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2058 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
2060 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
2062 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
2063 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2064 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
2066 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2068 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
2070 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
2071 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2072 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
2074 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
2076 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
2077 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2078 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
2080 /****************************************************************************/
2081 // Structures used by DVOEncoderControlTable
2082 /****************************************************************************/
2083 //ucTableFormatRevision=1,ucTableContentRevision=3
2086 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01
2087 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
2088 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
2089 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
2090 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00
2091 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
2092 #define DVO_ENCODER_CONFIG_24BIT 0x08
2094 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
2096 USHORT usPixelClock;
2098 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2100 }DVO_ENCODER_CONTROL_PARAMETERS_V3;
2101 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
2103 //ucTableFormatRevision=1
2104 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2105 // bit1=0: non-coherent mode
2106 // =1: coherent mode
2108 //==========================================================================================
2109 //Only change is here next time when changing encoder parameter definitions again!
2110 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2111 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2113 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2114 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2116 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2117 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2119 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
2120 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
2122 //==========================================================================================
2123 #define PANEL_ENCODER_MISC_DUAL 0x01
2124 #define PANEL_ENCODER_MISC_COHERENT 0x02
2125 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
2126 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
2128 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
2129 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
2130 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2132 #define PANEL_ENCODER_TRUNCATE_EN 0x01
2133 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
2134 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
2135 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
2136 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
2137 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
2138 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
2139 #define PANEL_ENCODER_25FRC_MASK 0x10
2140 #define PANEL_ENCODER_25FRC_E 0x00
2141 #define PANEL_ENCODER_25FRC_F 0x10
2142 #define PANEL_ENCODER_50FRC_MASK 0x60
2143 #define PANEL_ENCODER_50FRC_A 0x00
2144 #define PANEL_ENCODER_50FRC_B 0x20
2145 #define PANEL_ENCODER_50FRC_C 0x40
2146 #define PANEL_ENCODER_50FRC_D 0x60
2147 #define PANEL_ENCODER_75FRC_MASK 0x80
2148 #define PANEL_ENCODER_75FRC_E 0x00
2149 #define PANEL_ENCODER_75FRC_F 0x80
2151 /****************************************************************************/
2152 // Structures used by SetVoltageTable
2153 /****************************************************************************/
2154 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2155 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2156 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
2157 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2158 #define SET_VOLTAGE_INIT_MODE 5
2159 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2161 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
2162 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
2163 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
2165 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
2166 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
2167 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
2169 typedef struct _SET_VOLTAGE_PARAMETERS
2171 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2172 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2173 UCHAR ucVoltageIndex; // An index to tell which voltage level
2175 }SET_VOLTAGE_PARAMETERS;
2177 typedef struct _SET_VOLTAGE_PARAMETERS_V2
2179 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2180 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2181 USHORT usVoltageLevel; // real voltage level
2182 }SET_VOLTAGE_PARAMETERS_V2;
2185 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
2187 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2188 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2189 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2190 }SET_VOLTAGE_PARAMETERS_V1_3;
2193 #define VOLTAGE_TYPE_VDDC 1
2194 #define VOLTAGE_TYPE_MVDDC 2
2195 #define VOLTAGE_TYPE_MVDDQ 3
2196 #define VOLTAGE_TYPE_VDDCI 4
2198 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2199 #define ATOM_SET_VOLTAGE 0 //Set voltage Level
2200 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
2201 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase
2202 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3
2203 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID
2205 // define vitual voltage id in usVoltageLevel
2206 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
2207 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
2208 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
2209 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
2211 typedef struct _SET_VOLTAGE_PS_ALLOCATION
2213 SET_VOLTAGE_PARAMETERS sASICSetVoltage;
2214 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2215 }SET_VOLTAGE_PS_ALLOCATION;
2217 // New Added from SI for GetVoltageInfoTable, input parameter structure
2218 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
2220 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2221 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2222 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2224 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
2226 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2227 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2229 ULONG ulVotlageGpioState;
2230 ULONG ulVoltageGPioMask;
2231 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2233 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2234 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2236 USHORT usVoltageLevel;
2237 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2239 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2242 // GetVoltageInfo v1.1 ucVoltageMode
2243 #define ATOM_GET_VOLTAGE_VID 0x00
2244 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
2245 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
2246 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2247 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2249 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2250 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2251 // undefined power state
2252 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2253 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2255 /****************************************************************************/
2256 // Structures used by TVEncoderControlTable
2257 /****************************************************************************/
2258 typedef struct _TV_ENCODER_CONTROL_PARAMETERS
2260 USHORT usPixelClock; // in 10KHz; for bios convenient
2261 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2262 UCHAR ucAction; // 0: turn off encoder
2263 // 1: setup and turn on encoder
2264 }TV_ENCODER_CONTROL_PARAMETERS;
2266 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
2268 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
2269 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
2270 }TV_ENCODER_CONTROL_PS_ALLOCATION;
2272 //==============================Data Table Portion====================================
2274 /****************************************************************************/
2275 // Structure used in Data.mtb
2276 /****************************************************************************/
2277 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
2279 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
2280 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2281 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2282 USHORT StandardVESA_Timing; // Only used by Bios
2283 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2284 USHORT PaletteData; // Only used by BIOS
2285 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2286 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
2287 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2288 USHORT SupportedDevicesInfo; // Will be obsolete from R600
2289 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2290 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2291 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2292 USHORT VESA_ToInternalModeLUT; // Only used by Bios
2293 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
2294 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2295 USHORT CompassionateData; // Will be obsolete from R600
2296 USHORT SaveRestoreInfo; // Only used by Bios
2297 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2298 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2299 USHORT XTMDS_Info; // Will be obsolete from R600
2300 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2301 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2302 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
2303 USHORT MC_InitParameter; // Only used by command table
2304 USHORT ASIC_VDDC_Info; // Will be obsolete from R600
2305 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2306 USHORT TV_VideoMode; // Only used by command table
2307 USHORT VRAM_Info; // Only used by command table, latest version 1.3
2308 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2309 USHORT IntegratedSystemInfo; // Shared by various SW components
2310 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2311 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2312 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2313 }ATOM_MASTER_LIST_OF_DATA_TABLES;
2315 typedef struct _ATOM_MASTER_DATA_TABLE
2317 ATOM_COMMON_TABLE_HEADER sHeader;
2318 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
2319 }ATOM_MASTER_DATA_TABLE;
2321 // For backward compatible
2322 #define LVDS_Info LCD_Info
2323 #define DAC_Info PaletteData
2324 #define TMDS_Info DIGTransmitterInfo
2326 /****************************************************************************/
2327 // Structure used in MultimediaCapabilityInfoTable
2328 /****************************************************************************/
2329 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
2331 ATOM_COMMON_TABLE_HEADER sHeader;
2332 ULONG ulSignature; // HW info table signature string "$ATI"
2333 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2334 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2335 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2336 UCHAR ucHostPortInfo; // Provides host port configuration information
2337 }ATOM_MULTIMEDIA_CAPABILITY_INFO;
2339 /****************************************************************************/
2340 // Structure used in MultimediaConfigInfoTable
2341 /****************************************************************************/
2342 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2344 ATOM_COMMON_TABLE_HEADER sHeader;
2345 ULONG ulSignature; // MM info table signature sting "$MMT"
2346 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2347 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2348 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2349 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2350 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2351 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2352 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2353 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2354 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2355 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2356 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2357 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2358 }ATOM_MULTIMEDIA_CONFIG_INFO;
2361 /****************************************************************************/
2362 // Structures used in FirmwareInfoTable
2363 /****************************************************************************/
2365 // usBIOSCapability Definition:
2366 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2367 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2368 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2370 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
2371 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
2372 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
2373 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2374 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2375 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
2376 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
2377 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
2378 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
2379 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
2380 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2381 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
2382 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2383 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2387 //Please don't add or expand this bitfield structure below, this one will retire soon.!
2388 typedef struct _ATOM_FIRMWARE_CAPABILITY
2392 USHORT SCL2Redefined:1;
2393 USHORT PostWithoutModeSet:1;
2394 USHORT HyperMemory_Size:4;
2395 USHORT HyperMemory_Support:1;
2396 USHORT PPMode_Assigned:1;
2397 USHORT WMI_SUPPORT:1;
2398 USHORT GPUControlsBL:1;
2399 USHORT EngineClockSS_Support:1;
2400 USHORT MemoryClockSS_Support:1;
2401 USHORT ExtendedDesktopSupport:1;
2402 USHORT DualCRTC_Support:1;
2403 USHORT FirmwarePosted:1;
2405 USHORT FirmwarePosted:1;
2406 USHORT DualCRTC_Support:1;
2407 USHORT ExtendedDesktopSupport:1;
2408 USHORT MemoryClockSS_Support:1;
2409 USHORT EngineClockSS_Support:1;
2410 USHORT GPUControlsBL:1;
2411 USHORT WMI_SUPPORT:1;
2412 USHORT PPMode_Assigned:1;
2413 USHORT HyperMemory_Support:1;
2414 USHORT HyperMemory_Size:4;
2415 USHORT PostWithoutModeSet:1;
2416 USHORT SCL2Redefined:1;
2419 }ATOM_FIRMWARE_CAPABILITY;
2421 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2423 ATOM_FIRMWARE_CAPABILITY sbfAccess;
2425 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2429 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2432 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2436 typedef struct _ATOM_FIRMWARE_INFO
2438 ATOM_COMMON_TABLE_HEADER sHeader;
2439 ULONG ulFirmwareRevision;
2440 ULONG ulDefaultEngineClock; //In 10Khz unit
2441 ULONG ulDefaultMemoryClock; //In 10Khz unit
2442 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2443 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2444 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2445 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2446 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2447 ULONG ulASICMaxEngineClock; //In 10Khz unit
2448 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2449 UCHAR ucASICMaxTemperature;
2450 UCHAR ucPadding[3]; //Don't use them
2451 ULONG aulReservedForBIOS[3]; //Don't use them
2452 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2453 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2454 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2455 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2456 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2457 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2458 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2459 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2460 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2461 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
2462 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2463 USHORT usReferenceClock; //In 10Khz unit
2464 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2465 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2466 UCHAR ucDesign_ID; //Indicate what is the board design
2467 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2468 }ATOM_FIRMWARE_INFO;
2470 typedef struct _ATOM_FIRMWARE_INFO_V1_2
2472 ATOM_COMMON_TABLE_HEADER sHeader;
2473 ULONG ulFirmwareRevision;
2474 ULONG ulDefaultEngineClock; //In 10Khz unit
2475 ULONG ulDefaultMemoryClock; //In 10Khz unit
2476 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2477 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2478 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2479 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2480 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2481 ULONG ulASICMaxEngineClock; //In 10Khz unit
2482 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2483 UCHAR ucASICMaxTemperature;
2484 UCHAR ucMinAllowedBL_Level;
2485 UCHAR ucPadding[2]; //Don't use them
2486 ULONG aulReservedForBIOS[2]; //Don't use them
2487 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2488 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2489 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2490 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2491 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2492 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2493 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2494 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2495 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2496 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2497 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2498 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2499 USHORT usReferenceClock; //In 10Khz unit
2500 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2501 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2502 UCHAR ucDesign_ID; //Indicate what is the board design
2503 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2504 }ATOM_FIRMWARE_INFO_V1_2;
2506 typedef struct _ATOM_FIRMWARE_INFO_V1_3
2508 ATOM_COMMON_TABLE_HEADER sHeader;
2509 ULONG ulFirmwareRevision;
2510 ULONG ulDefaultEngineClock; //In 10Khz unit
2511 ULONG ulDefaultMemoryClock; //In 10Khz unit
2512 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2513 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2514 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2515 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2516 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2517 ULONG ulASICMaxEngineClock; //In 10Khz unit
2518 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2519 UCHAR ucASICMaxTemperature;
2520 UCHAR ucMinAllowedBL_Level;
2521 UCHAR ucPadding[2]; //Don't use them
2522 ULONG aulReservedForBIOS; //Don't use them
2523 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2524 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2525 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2526 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2527 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2528 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2529 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2530 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2531 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2532 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2533 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2534 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2535 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2536 USHORT usReferenceClock; //In 10Khz unit
2537 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2538 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2539 UCHAR ucDesign_ID; //Indicate what is the board design
2540 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2541 }ATOM_FIRMWARE_INFO_V1_3;
2543 typedef struct _ATOM_FIRMWARE_INFO_V1_4
2545 ATOM_COMMON_TABLE_HEADER sHeader;
2546 ULONG ulFirmwareRevision;
2547 ULONG ulDefaultEngineClock; //In 10Khz unit
2548 ULONG ulDefaultMemoryClock; //In 10Khz unit
2549 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2550 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2551 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2552 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2553 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2554 ULONG ulASICMaxEngineClock; //In 10Khz unit
2555 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2556 UCHAR ucASICMaxTemperature;
2557 UCHAR ucMinAllowedBL_Level;
2558 USHORT usBootUpVDDCVoltage; //In MV unit
2559 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2560 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2561 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2562 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2563 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2564 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2565 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2566 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2567 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2568 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2569 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2570 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2571 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2572 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2573 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2574 USHORT usReferenceClock; //In 10Khz unit
2575 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2576 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2577 UCHAR ucDesign_ID; //Indicate what is the board design
2578 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2579 }ATOM_FIRMWARE_INFO_V1_4;
2581 //the structure below to be used from Cypress
2582 typedef struct _ATOM_FIRMWARE_INFO_V2_1
2584 ATOM_COMMON_TABLE_HEADER sHeader;
2585 ULONG ulFirmwareRevision;
2586 ULONG ulDefaultEngineClock; //In 10Khz unit
2587 ULONG ulDefaultMemoryClock; //In 10Khz unit
2590 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2591 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2592 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2593 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2594 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2595 UCHAR ucReserved1; //Was ucASICMaxTemperature;
2596 UCHAR ucMinAllowedBL_Level;
2597 USHORT usBootUpVDDCVoltage; //In MV unit
2598 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2599 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2600 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2601 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2602 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2603 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2604 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2605 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2606 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2607 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2608 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2609 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2610 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2611 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2612 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2613 USHORT usCoreReferenceClock; //In 10Khz unit
2614 USHORT usMemoryReferenceClock; //In 10Khz unit
2615 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2616 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2617 UCHAR ucReserved4[3];
2618 }ATOM_FIRMWARE_INFO_V2_1;
2620 //the structure below to be used from NI
2621 //ucTableFormatRevision=2
2622 //ucTableContentRevision=2
2623 typedef struct _ATOM_FIRMWARE_INFO_V2_2
2625 ATOM_COMMON_TABLE_HEADER sHeader;
2626 ULONG ulFirmwareRevision;
2627 ULONG ulDefaultEngineClock; //In 10Khz unit
2628 ULONG ulDefaultMemoryClock; //In 10Khz unit
2629 ULONG ulReserved[2];
2630 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2631 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2632 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2633 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2634 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2635 UCHAR ucReserved3; //Was ucASICMaxTemperature;
2636 UCHAR ucMinAllowedBL_Level;
2637 USHORT usBootUpVDDCVoltage; //In MV unit
2638 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2639 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2640 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2641 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2642 UCHAR ucRemoteDisplayConfig;
2643 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2644 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2645 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2646 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
2647 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2648 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2649 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2650 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2651 USHORT usCoreReferenceClock; //In 10Khz unit
2652 USHORT usMemoryReferenceClock; //In 10Khz unit
2653 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2654 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2655 UCHAR ucReserved9[3];
2656 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2657 USHORT usReserved12;
2658 ULONG ulReserved10[3]; // New added comparing to previous version
2659 }ATOM_FIRMWARE_INFO_V2_2;
2661 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
2664 // definition of ucRemoteDisplayConfig
2665 #define REMOTE_DISPLAY_DISABLE 0x00
2666 #define REMOTE_DISPLAY_ENABLE 0x01
2668 /****************************************************************************/
2669 // Structures used in IntegratedSystemInfoTable
2670 /****************************************************************************/
2671 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
2672 #define IGP_CAP_FLAG_AC_CARD 0x4
2673 #define IGP_CAP_FLAG_SDVO_CARD 0x8
2674 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
2676 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
2678 ATOM_COMMON_TABLE_HEADER sHeader;
2679 ULONG ulBootUpEngineClock; //in 10kHz unit
2680 ULONG ulBootUpMemoryClock; //in 10kHz unit
2681 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2682 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2683 UCHAR ucNumberOfCyclesInPeriodHi;
2684 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2686 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
2687 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
2688 ULONG ulReserved[2];
2690 USHORT usFSBClock; //In MHz unit
2691 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2692 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2693 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2694 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2695 USHORT usK8MemoryClock; //in MHz unit
2696 USHORT usK8SyncStartDelay; //in 0.01 us unit
2697 USHORT usK8DataReturnTime; //in 0.01 us unit
2698 UCHAR ucMaxNBVoltage;
2699 UCHAR ucMinNBVoltage;
2700 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2701 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2702 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2703 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2704 UCHAR ucMaxNBVoltageHigh;
2705 UCHAR ucMinNBVoltageHigh;
2706 }ATOM_INTEGRATED_SYSTEM_INFO;
2708 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2709 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
2710 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2711 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2712 For AMD IGP,for now this can be 0
2713 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2714 For AMD IGP,for now this can be 0
2716 usFSBClock: For Intel IGP,it's FSB Freq
2717 For AMD IGP,it's HT Link Speed
2719 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
2720 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2721 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2724 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2725 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2727 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2728 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2730 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2731 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2734 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2735 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2740 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
2741 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2742 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2744 SW components can access the IGP system infor structure in the same way as before
2748 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
2750 ATOM_COMMON_TABLE_HEADER sHeader;
2751 ULONG ulBootUpEngineClock; //in 10kHz unit
2752 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2753 ULONG ulBootUpUMAClock; //in 10kHz unit
2754 ULONG ulBootUpSidePortClock; //in 10kHz unit
2755 ULONG ulMinSidePortClock; //in 10kHz unit
2756 ULONG ulReserved2[6]; //must be 0x0 for the reserved
2757 ULONG ulSystemConfig; //see explanation below
2758 ULONG ulBootUpReqDisplayVector;
2759 ULONG ulOtherDisplayMisc;
2760 ULONG ulDDISlot1Config;
2761 ULONG ulDDISlot2Config;
2762 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2763 UCHAR ucUMAChannelNumber;
2764 UCHAR ucDockingPinBit;
2765 UCHAR ucDockingPinPolarity;
2766 ULONG ulDockingPinCFGInfo;
2768 USHORT usNumberOfCyclesInPeriod;
2769 USHORT usMaxNBVoltage;
2770 USHORT usMinNBVoltage;
2771 USHORT usBootUpNBVoltage;
2772 ULONG ulHTLinkFreq; //in 10Khz
2773 USHORT usMinHTLinkWidth;
2774 USHORT usMaxHTLinkWidth;
2775 USHORT usUMASyncStartDelay;
2776 USHORT usUMADataReturnTime;
2777 USHORT usLinkStatusZeroTime;
2778 USHORT usDACEfuse; //for storing badgap value (for RS880 only)
2779 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2780 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2781 USHORT usMaxUpStreamHTLinkWidth;
2782 USHORT usMaxDownStreamHTLinkWidth;
2783 USHORT usMinUpStreamHTLinkWidth;
2784 USHORT usMinDownStreamHTLinkWidth;
2785 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2786 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2787 ULONG ulReserved3[96]; //must be 0x0
2788 }ATOM_INTEGRATED_SYSTEM_INFO_V2;
2791 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2792 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2793 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
2796 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2797 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
2798 =0: system boots up at driver control state. Power state depends on PowerPlay table.
2799 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2800 Bit[3]=1: Only one power state(Performance) will be supported.
2801 =0: Multiple power states supported from PowerPlay table.
2802 Bit[4]=1: CLMC is supported and enabled on current system.
2803 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
2804 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
2805 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
2806 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
2807 =0: Voltage settings is determined by powerplay table.
2808 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
2809 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2810 Bit[8]=1: CDLF is supported and enabled on current system.
2811 =0: CDLF is not supported or enabled on current system.
2812 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2813 =0: DLL Shut Down feature is not enabled or supported on current system.
2815 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
2817 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2818 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
2820 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
2821 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2822 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2823 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
2824 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
2825 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2827 [15:8] - Lane configuration attribute;
2828 [23:16]- Connector type, possible value:
2829 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
2830 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
2831 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
2832 CONNECTOR_OBJECT_ID_DISPLAYPORT
2833 CONNECTOR_OBJECT_ID_eDP
2836 ulDDISlot2Config: Same as Slot1.
2837 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
2838 For IGP, Hypermemory is the only memory type showed in CCC.
2840 ucUMAChannelNumber: how many channels for the UMA;
2842 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
2843 ucDockingPinBit: which bit in this register to read the pin status;
2844 ucDockingPinPolarity:Polarity of the pin when docked;
2846 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
2848 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2850 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2851 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2852 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
2853 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2854 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
2856 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2858 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
2859 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
2860 If CDLW enabled, both upstream and downstream width should be the same during bootup.
2861 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
2862 If CDLW enabled, both upstream and downstream width should be the same during bootup.
2864 usUMASyncStartDelay: Memory access latency, required for watermark calculation
2865 usUMADataReturnTime: Memory access latency, required for watermark calculation
2866 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
2867 for Griffin or Greyhound. SBIOS needs to convert to actual time by:
2868 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
2869 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
2870 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
2871 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
2873 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
2874 This must be less than or equal to ulHTLinkFreq(bootup frequency).
2875 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
2876 This must be less than or equal to ulHighVoltageHTLinkFreq.
2878 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
2879 usMaxDownStreamHTLinkWidth: same as above.
2880 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
2881 usMinDownStreamHTLinkWidth: same as above.
2884 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2885 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
2886 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
2887 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
2888 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
2889 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
2890 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5
2892 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
2894 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
2895 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
2896 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
2897 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
2898 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
2899 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
2900 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
2901 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
2902 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
2903 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
2905 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
2907 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
2908 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
2909 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
2910 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
2911 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
2912 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
2914 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
2915 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
2916 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
2918 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
2920 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
2921 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
2923 ATOM_COMMON_TABLE_HEADER sHeader;
2924 ULONG ulBootUpEngineClock; //in 10kHz unit
2925 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2926 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2927 ULONG ulBootUpUMAClock; //in 10kHz unit
2928 ULONG ulReserved1[8]; //must be 0x0 for the reserved
2929 ULONG ulBootUpReqDisplayVector;
2930 ULONG ulOtherDisplayMisc;
2931 ULONG ulReserved2[4]; //must be 0x0 for the reserved
2932 ULONG ulSystemConfig; //TBD
2933 ULONG ulCPUCapInfo; //TBD
2934 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2935 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2936 USHORT usBootUpNBVoltage; //boot up NB voltage
2937 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
2938 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
2939 ULONG ulReserved3[4]; //must be 0x0 for the reserved
2940 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
2941 ULONG ulDDISlot2Config;
2942 ULONG ulDDISlot3Config;
2943 ULONG ulDDISlot4Config;
2944 ULONG ulReserved4[4]; //must be 0x0 for the reserved
2945 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2946 UCHAR ucUMAChannelNumber;
2948 ULONG ulReserved5[4]; //must be 0x0 for the reserved
2949 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
2950 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
2951 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
2952 ULONG ulReserved6[61]; //must be 0x0
2953 }ATOM_INTEGRATED_SYSTEM_INFO_V5;
2955 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
2956 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
2957 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
2958 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
2959 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
2960 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
2961 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
2962 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
2963 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
2964 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
2965 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
2966 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
2967 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
2968 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
2970 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
2971 #define ASIC_INT_DAC1_ENCODER_ID 0x00
2972 #define ASIC_INT_TV_ENCODER_ID 0x02
2973 #define ASIC_INT_DIG1_ENCODER_ID 0x03
2974 #define ASIC_INT_DAC2_ENCODER_ID 0x04
2975 #define ASIC_EXT_TV_ENCODER_ID 0x06
2976 #define ASIC_INT_DVO_ENCODER_ID 0x07
2977 #define ASIC_INT_DIG2_ENCODER_ID 0x09
2978 #define ASIC_EXT_DIG_ENCODER_ID 0x05
2979 #define ASIC_EXT_DIG2_ENCODER_ID 0x08
2980 #define ASIC_INT_DIG3_ENCODER_ID 0x0a
2981 #define ASIC_INT_DIG4_ENCODER_ID 0x0b
2982 #define ASIC_INT_DIG5_ENCODER_ID 0x0c
2983 #define ASIC_INT_DIG6_ENCODER_ID 0x0d
2984 #define ASIC_INT_DIG7_ENCODER_ID 0x0e
2986 //define Encoder attribute
2987 #define ATOM_ANALOG_ENCODER 0
2988 #define ATOM_DIGITAL_ENCODER 1
2989 #define ATOM_DP_ENCODER 2
2991 #define ATOM_ENCODER_ENUM_MASK 0x70
2992 #define ATOM_ENCODER_ENUM_ID1 0x00
2993 #define ATOM_ENCODER_ENUM_ID2 0x10
2994 #define ATOM_ENCODER_ENUM_ID3 0x20
2995 #define ATOM_ENCODER_ENUM_ID4 0x30
2996 #define ATOM_ENCODER_ENUM_ID5 0x40
2997 #define ATOM_ENCODER_ENUM_ID6 0x50
2999 #define ATOM_DEVICE_CRT1_INDEX 0x00000000
3000 #define ATOM_DEVICE_LCD1_INDEX 0x00000001
3001 #define ATOM_DEVICE_TV1_INDEX 0x00000002
3002 #define ATOM_DEVICE_DFP1_INDEX 0x00000003
3003 #define ATOM_DEVICE_CRT2_INDEX 0x00000004
3004 #define ATOM_DEVICE_LCD2_INDEX 0x00000005
3005 #define ATOM_DEVICE_DFP6_INDEX 0x00000006
3006 #define ATOM_DEVICE_DFP2_INDEX 0x00000007
3007 #define ATOM_DEVICE_CV_INDEX 0x00000008
3008 #define ATOM_DEVICE_DFP3_INDEX 0x00000009
3009 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A
3010 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B
3012 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
3013 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
3014 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
3015 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
3016 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3017 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
3018 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3020 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3022 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
3023 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
3024 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
3025 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
3026 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
3027 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
3028 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
3029 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
3030 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
3031 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
3032 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
3033 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
3035 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3036 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3037 #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT)
3038 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3040 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
3041 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
3042 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
3043 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
3044 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
3045 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
3046 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
3047 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
3048 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
3049 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
3050 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
3051 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
3052 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
3053 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
3054 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
3057 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
3058 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
3059 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
3060 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
3061 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
3062 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
3064 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
3066 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
3067 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
3069 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070
3070 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
3071 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
3072 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
3073 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
3074 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
3076 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
3077 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
3078 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
3079 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
3082 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3083 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3084 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3085 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3086 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3087 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3088 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3089 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3090 // Bit 8 = 0 - no CV support= 1- CV is supported
3091 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3092 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3093 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3097 /****************************************************************************/
3098 /* Structure used in MclkSS_InfoTable */
3099 /****************************************************************************/
3101 // [7:0] - I2C LINE Associate ID
3103 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3104 // = 0, [6:0]=SW assisted I2C ID
3105 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3106 // = 2, HW engine for Multimedia use
3107 // = 3-7 Reserved for future I2C engines
3108 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3110 typedef struct _ATOM_I2C_ID_CONFIG
3113 UCHAR bfHW_Capable:1;
3114 UCHAR bfHW_EngineID:3;
3115 UCHAR bfI2C_LineMux:4;
3117 UCHAR bfI2C_LineMux:4;
3118 UCHAR bfHW_EngineID:3;
3119 UCHAR bfHW_Capable:1;
3121 }ATOM_I2C_ID_CONFIG;
3123 typedef union _ATOM_I2C_ID_CONFIG_ACCESS
3125 ATOM_I2C_ID_CONFIG sbfAccess;
3127 }ATOM_I2C_ID_CONFIG_ACCESS;
3130 /****************************************************************************/
3131 // Structure used in GPIO_I2C_InfoTable
3132 /****************************************************************************/
3133 typedef struct _ATOM_GPIO_I2C_ASSIGMENT
3135 USHORT usClkMaskRegisterIndex;
3136 USHORT usClkEnRegisterIndex;
3137 USHORT usClkY_RegisterIndex;
3138 USHORT usClkA_RegisterIndex;
3139 USHORT usDataMaskRegisterIndex;
3140 USHORT usDataEnRegisterIndex;
3141 USHORT usDataY_RegisterIndex;
3142 USHORT usDataA_RegisterIndex;
3143 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3144 UCHAR ucClkMaskShift;
3148 UCHAR ucDataMaskShift;
3149 UCHAR ucDataEnShift;
3150 UCHAR ucDataY_Shift;
3151 UCHAR ucDataA_Shift;
3154 }ATOM_GPIO_I2C_ASSIGMENT;
3156 typedef struct _ATOM_GPIO_I2C_INFO
3158 ATOM_COMMON_TABLE_HEADER sHeader;
3159 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
3160 }ATOM_GPIO_I2C_INFO;
3162 /****************************************************************************/
3163 // Common Structure used in other structures
3164 /****************************************************************************/
3168 //Please don't add or expand this bitfield structure below, this one will retire soon.!
3169 typedef struct _ATOM_MODE_MISC_INFO
3174 USHORT DoubleClock:1;
3176 USHORT CompositeSync:1;
3177 USHORT V_ReplicationBy2:1;
3178 USHORT H_ReplicationBy2:1;
3179 USHORT VerticalCutOff:1;
3180 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3181 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3182 USHORT HorizontalCutOff:1;
3184 USHORT HorizontalCutOff:1;
3185 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3186 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3187 USHORT VerticalCutOff:1;
3188 USHORT H_ReplicationBy2:1;
3189 USHORT V_ReplicationBy2:1;
3190 USHORT CompositeSync:1;
3192 USHORT DoubleClock:1;
3196 }ATOM_MODE_MISC_INFO;
3198 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3200 ATOM_MODE_MISC_INFO sbfAccess;
3202 }ATOM_MODE_MISC_INFO_ACCESS;
3206 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3209 }ATOM_MODE_MISC_INFO_ACCESS;
3214 #define ATOM_H_CUTOFF 0x01
3215 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3216 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3217 #define ATOM_V_CUTOFF 0x08
3218 #define ATOM_H_REPLICATIONBY2 0x10
3219 #define ATOM_V_REPLICATIONBY2 0x20
3220 #define ATOM_COMPOSITESYNC 0x40
3221 #define ATOM_INTERLACE 0x80
3222 #define ATOM_DOUBLE_CLOCK_MODE 0x100
3223 #define ATOM_RGB888_MODE 0x200
3226 #define ATOM_REFRESH_43 43
3227 #define ATOM_REFRESH_47 47
3228 #define ATOM_REFRESH_56 56
3229 #define ATOM_REFRESH_60 60
3230 #define ATOM_REFRESH_65 65
3231 #define ATOM_REFRESH_70 70
3232 #define ATOM_REFRESH_72 72
3233 #define ATOM_REFRESH_75 75
3234 #define ATOM_REFRESH_85 85
3236 // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3237 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3239 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3240 // = EDID_HA + EDID_HBL
3241 // VESA_HDISP = VESA_ACTIVE = EDID_HA
3242 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3243 // = EDID_HA + EDID_HSO
3244 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
3245 // VESA_BORDER = EDID_BORDER
3247 /****************************************************************************/
3248 // Structure used in SetCRTC_UsingDTDTimingTable
3249 /****************************************************************************/
3250 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
3253 USHORT usH_Blanking_Time;
3255 USHORT usV_Blanking_Time;
3256 USHORT usH_SyncOffset;
3257 USHORT usH_SyncWidth;
3258 USHORT usV_SyncOffset;
3259 USHORT usV_SyncWidth;
3260 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3261 UCHAR ucH_Border; // From DFP EDID
3263 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3265 }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
3267 /****************************************************************************/
3268 // Structure used in SetCRTC_TimingTable
3269 /****************************************************************************/
3270 typedef struct _SET_CRTC_TIMING_PARAMETERS
3272 USHORT usH_Total; // horizontal total
3273 USHORT usH_Disp; // horizontal display
3274 USHORT usH_SyncStart; // horozontal Sync start
3275 USHORT usH_SyncWidth; // horizontal Sync width
3276 USHORT usV_Total; // vertical total
3277 USHORT usV_Disp; // vertical display
3278 USHORT usV_SyncStart; // vertical Sync start
3279 USHORT usV_SyncWidth; // vertical Sync width
3280 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3281 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3282 UCHAR ucOverscanRight; // right
3283 UCHAR ucOverscanLeft; // left
3284 UCHAR ucOverscanBottom; // bottom
3285 UCHAR ucOverscanTop; // top
3287 }SET_CRTC_TIMING_PARAMETERS;
3288 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3290 /****************************************************************************/
3291 // Structure used in StandardVESA_TimingTable
3292 // AnalogTV_InfoTable
3293 // ComponentVideoInfoTable
3294 /****************************************************************************/
3295 typedef struct _ATOM_MODE_TIMING
3297 USHORT usCRTC_H_Total;
3298 USHORT usCRTC_H_Disp;
3299 USHORT usCRTC_H_SyncStart;
3300 USHORT usCRTC_H_SyncWidth;
3301 USHORT usCRTC_V_Total;
3302 USHORT usCRTC_V_Disp;
3303 USHORT usCRTC_V_SyncStart;
3304 USHORT usCRTC_V_SyncWidth;
3305 USHORT usPixelClock; //in 10Khz unit
3306 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3307 USHORT usCRTC_OverscanRight;
3308 USHORT usCRTC_OverscanLeft;
3309 USHORT usCRTC_OverscanBottom;
3310 USHORT usCRTC_OverscanTop;
3312 UCHAR ucInternalModeNumber;
3313 UCHAR ucRefreshRate;
3316 typedef struct _ATOM_DTD_FORMAT
3320 USHORT usHBlanking_Time;
3322 USHORT usVBlanking_Time;
3323 USHORT usHSyncOffset;
3324 USHORT usHSyncWidth;
3325 USHORT usVSyncOffset;
3326 USHORT usVSyncWidth;
3327 USHORT usImageHSize;
3328 USHORT usImageVSize;
3331 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3332 UCHAR ucInternalModeNumber;
3333 UCHAR ucRefreshRate;
3336 /****************************************************************************/
3337 // Structure used in LVDS_InfoTable
3338 // * Need a document to describe this table
3339 /****************************************************************************/
3340 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
3341 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
3342 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
3343 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
3345 //ucTableFormatRevision=1
3346 //ucTableContentRevision=1
3347 typedef struct _ATOM_LVDS_INFO
3349 ATOM_COMMON_TABLE_HEADER sHeader;
3350 ATOM_DTD_FORMAT sLCDTiming;
3351 USHORT usModePatchTableOffset;
3352 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3353 USHORT usOffDelayInMs;
3354 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3355 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3356 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3357 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3358 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3359 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3360 UCHAR ucPanelDefaultRefreshRate;
3361 UCHAR ucPanelIdentification;
3365 //ucTableFormatRevision=1
3366 //ucTableContentRevision=2
3367 typedef struct _ATOM_LVDS_INFO_V12
3369 ATOM_COMMON_TABLE_HEADER sHeader;
3370 ATOM_DTD_FORMAT sLCDTiming;
3371 USHORT usExtInfoTableOffset;
3372 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3373 USHORT usOffDelayInMs;
3374 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3375 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3376 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3377 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3378 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3379 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3380 UCHAR ucPanelDefaultRefreshRate;
3381 UCHAR ucPanelIdentification;
3383 USHORT usLCDVenderID;
3384 USHORT usLCDProductID;
3385 UCHAR ucLCDPanel_SpecialHandlingCap;
3386 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3387 UCHAR ucReserved[2];
3388 }ATOM_LVDS_INFO_V12;
3390 //Definitions for ucLCDPanel_SpecialHandlingCap:
3392 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3393 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3394 #define LCDPANEL_CAP_READ_EDID 0x1
3396 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3397 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3398 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3399 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2
3401 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3402 #define LCDPANEL_CAP_eDP 0x4
3405 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3407 // 0 0 0 - Color bit depth is undefined
3408 // 0 0 1 - 6 Bits per Primary Color
3409 // 0 1 0 - 8 Bits per Primary Color
3410 // 0 1 1 - 10 Bits per Primary Color
3411 // 1 0 0 - 12 Bits per Primary Color
3412 // 1 0 1 - 14 Bits per Primary Color
3413 // 1 1 0 - 16 Bits per Primary Color
3416 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70
3418 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3419 #define PANEL_RANDOM_DITHER 0x80
3420 #define PANEL_RANDOM_DITHER_MASK 0x80
3422 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
3424 /****************************************************************************/
3425 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
3426 // ASIC Families: NI
3427 // ucTableFormatRevision=1
3428 // ucTableContentRevision=3
3429 /****************************************************************************/
3430 typedef struct _ATOM_LCD_INFO_V13
3432 ATOM_COMMON_TABLE_HEADER sHeader;
3433 ATOM_DTD_FORMAT sLCDTiming;
3434 USHORT usExtInfoTableOffset;
3435 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3437 UCHAR ucLCD_Misc; // Reorganized in V13
3438 // Bit0: {=0:single, =1:dual},
3439 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3440 // Bit3:2: {Grey level}
3441 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3442 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3443 UCHAR ucPanelDefaultRefreshRate;
3444 UCHAR ucPanelIdentification;
3446 USHORT usLCDVenderID;
3447 USHORT usLCDProductID;
3448 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3449 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3450 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
3451 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3453 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3454 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
3456 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
3457 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
3458 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
3459 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
3461 UCHAR ucOffDelay_in4Ms;
3462 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
3463 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
3466 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
3467 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
3468 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
3469 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
3471 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
3472 UCHAR uceDPToLVDSRxId;
3474 ULONG ulReserved[2];
3477 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13
3479 //Definitions for ucLCD_Misc
3480 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001
3481 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002
3482 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C
3483 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
3484 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70
3485 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10
3486 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20
3488 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3490 // 0 0 0 - Color bit depth is undefined
3491 // 0 0 1 - 6 Bits per Primary Color
3492 // 0 1 0 - 8 Bits per Primary Color
3493 // 0 1 1 - 10 Bits per Primary Color
3494 // 1 0 0 - 12 Bits per Primary Color
3495 // 1 0 1 - 14 Bits per Primary Color
3496 // 1 1 0 - 16 Bits per Primary Color
3499 //Definitions for ucLCDPanel_SpecialHandlingCap:
3501 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3502 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3503 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
3505 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3506 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3507 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3508 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
3510 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3511 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
3514 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3515 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
3516 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
3518 typedef struct _ATOM_PATCH_RECORD_MODE
3523 }ATOM_PATCH_RECORD_MODE;
3525 typedef struct _ATOM_LCD_RTS_RECORD
3529 }ATOM_LCD_RTS_RECORD;
3531 //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
3532 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
3533 typedef struct _ATOM_LCD_MODE_CONTROL_CAP
3537 }ATOM_LCD_MODE_CONTROL_CAP;
3539 #define LCD_MODE_CAP_BL_OFF 1
3540 #define LCD_MODE_CAP_CRTC_OFF 2
3541 #define LCD_MODE_CAP_PANEL_OFF 4
3543 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
3546 UCHAR ucFakeEDIDLength;
3547 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
3548 } ATOM_FAKE_EDID_PATCH_RECORD;
3550 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
3555 }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
3557 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
3558 #define LCD_RTS_RECORD_TYPE 2
3559 #define LCD_CAP_RECORD_TYPE 3
3560 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
3561 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
3562 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6
3563 #define ATOM_RECORD_END_TYPE 0xFF
3565 /****************************Spread Spectrum Info Table Definitions **********************/
3567 //ucTableFormatRevision=1
3568 //ucTableContentRevision=2
3569 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
3571 USHORT usSpreadSpectrumPercentage;
3572 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
3576 UCHAR ucRecommendedRef_Div;
3577 UCHAR ucSS_Range; //it was reserved for V11
3578 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
3580 #define ATOM_MAX_SS_ENTRY 16
3581 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3582 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3583 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
3584 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
3587 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
3588 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
3589 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
3590 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
3591 #define ATOM_INTERNAL_SS_MASK 0x00000000
3592 #define ATOM_EXTERNAL_SS_MASK 0x00000002
3593 #define EXEC_SS_STEP_SIZE_SHIFT 2
3594 #define EXEC_SS_DELAY_SHIFT 4
3595 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
3597 typedef struct _ATOM_SPREAD_SPECTRUM_INFO
3599 ATOM_COMMON_TABLE_HEADER sHeader;
3600 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
3601 }ATOM_SPREAD_SPECTRUM_INFO;
3603 /****************************************************************************/
3604 // Structure used in AnalogTV_InfoTable (Top level)
3605 /****************************************************************************/
3606 //ucTVBootUpDefaultStd definition:
3617 //ucTVSupportedStd definition:
3618 #define NTSC_SUPPORT 0x1
3619 #define NTSCJ_SUPPORT 0x2
3621 #define PAL_SUPPORT 0x4
3622 #define PALM_SUPPORT 0x8
3623 #define PALCN_SUPPORT 0x10
3624 #define PALN_SUPPORT 0x20
3625 #define PAL60_SUPPORT 0x40
3626 #define SECAM_SUPPORT 0x80
3628 #define MAX_SUPPORTED_TV_TIMING 2
3630 typedef struct _ATOM_ANALOG_TV_INFO
3632 ATOM_COMMON_TABLE_HEADER sHeader;
3633 UCHAR ucTV_SupportedStandard;
3634 UCHAR ucTV_BootUpDefaultStandard;
3635 UCHAR ucExt_TV_ASIC_ID;
3636 UCHAR ucExt_TV_ASIC_SlaveAddr;
3637 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
3638 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
3639 }ATOM_ANALOG_TV_INFO;
3641 #define MAX_SUPPORTED_TV_TIMING_V1_2 3
3643 typedef struct _ATOM_ANALOG_TV_INFO_V1_2
3645 ATOM_COMMON_TABLE_HEADER sHeader;
3646 UCHAR ucTV_SupportedStandard;
3647 UCHAR ucTV_BootUpDefaultStandard;
3648 UCHAR ucExt_TV_ASIC_ID;
3649 UCHAR ucExt_TV_ASIC_SlaveAddr;
3650 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
3651 }ATOM_ANALOG_TV_INFO_V1_2;
3653 typedef struct _ATOM_DPCD_INFO
3655 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
3656 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3657 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3658 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
3661 #define ATOM_DPCD_MAX_LANE_MASK 0x1F
3663 /**************************************************************************/
3664 // VRAM usage and their defintions
3666 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
3667 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
3668 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
3669 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
3670 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3672 #ifndef VESA_MEMORY_IN_64K_BLOCK
3673 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
3676 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
3677 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
3678 #define ATOM_HWICON_INFOTABLE_SIZE 32
3679 #define MAX_DTD_MODE_IN_VRAM 6
3680 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
3681 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
3682 //20 bytes for Encoder Type and DPCD in STD EDID area
3683 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3684 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
3686 #define ATOM_HWICON1_SURFACE_ADDR 0
3687 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3688 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3689 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
3690 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3691 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3693 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3694 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3695 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3697 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3699 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3700 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3701 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3703 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3704 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3705 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3707 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3708 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3709 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3711 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3712 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3713 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3715 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3716 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3717 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3719 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3720 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3721 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3723 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3724 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3725 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3727 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3728 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3729 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3731 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3732 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3733 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3735 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3737 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)
3738 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512
3740 //The size below is in Kb!
3741 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
3743 #define ATOM_VRAM_RESERVE_V2_SIZE 32
3745 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
3746 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
3747 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
3748 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
3750 /***********************************************************************************/
3751 // Structure used in VRAM_UsageByFirmwareTable
3752 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
3754 // note2: From RV770, the memory is more than 32bit addressable, so we will change
3755 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
3756 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
3757 // (in offset to start of memory address) is KB aligned instead of byte aligend.
3758 /***********************************************************************************/
3760 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
3761 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
3763 If (ulStartAddrUsedByFirmware!=0)
3764 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3765 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
3768 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3770 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3772 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
3774 /***********************************************************************************/
3775 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
3777 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
3779 ULONG ulStartAddrUsedByFirmware;
3780 USHORT usFirmwareUseInKb;
3782 }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
3784 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
3786 ATOM_COMMON_TABLE_HEADER sHeader;
3787 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3788 }ATOM_VRAM_USAGE_BY_FIRMWARE;
3790 // change verion to 1.5, when allow driver to allocate the vram area for command table access.
3791 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
3793 ULONG ulStartAddrUsedByFirmware;
3794 USHORT usFirmwareUseInKb;
3795 USHORT usFBUsedByDrvInKb;
3796 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
3798 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
3800 ATOM_COMMON_TABLE_HEADER sHeader;
3801 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3802 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
3804 /****************************************************************************/
3805 // Structure used in GPIO_Pin_LUTTable
3806 /****************************************************************************/
3807 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
3809 USHORT usGpioPin_AIndex;
3810 UCHAR ucGpioPinBitShift;
3812 }ATOM_GPIO_PIN_ASSIGNMENT;
3814 typedef struct _ATOM_GPIO_PIN_LUT
3816 ATOM_COMMON_TABLE_HEADER sHeader;
3817 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
3820 /****************************************************************************/
3821 // Structure used in ComponentVideoInfoTable
3822 /****************************************************************************/
3823 #define GPIO_PIN_ACTIVE_HIGH 0x1
3825 #define MAX_SUPPORTED_CV_STANDARDS 5
3827 // definitions for ATOM_D_INFO.ucSettings
3828 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
3829 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
3830 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
3832 typedef struct _ATOM_GPIO_INFO
3839 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
3840 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
3842 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
3843 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
3844 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
3846 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
3847 //Line 3 out put 5V.
3848 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
3849 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
3850 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
3852 //Line 3 out put 2.2V
3853 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
3854 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
3855 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
3858 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
3859 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
3860 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
3862 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
3864 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
3866 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
3867 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3868 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3871 typedef struct _ATOM_COMPONENT_VIDEO_INFO
3873 ATOM_COMMON_TABLE_HEADER sHeader;
3874 USHORT usMask_PinRegisterIndex;
3875 USHORT usEN_PinRegisterIndex;
3876 USHORT usY_PinRegisterIndex;
3877 USHORT usA_PinRegisterIndex;
3879 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
3880 ATOM_DTD_FORMAT sReserved; // must be zeroed out
3886 UCHAR ucLetterBoxMode;
3887 UCHAR ucReserved[3];
3888 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3889 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
3890 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
3891 }ATOM_COMPONENT_VIDEO_INFO;
3893 //ucTableFormatRevision=2
3894 //ucTableContentRevision=1
3895 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
3897 ATOM_COMMON_TABLE_HEADER sHeader;
3904 UCHAR ucLetterBoxMode;
3905 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3906 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
3907 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
3908 }ATOM_COMPONENT_VIDEO_INFO_V21;
3910 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
3912 /****************************************************************************/
3913 // Structure used in object_InfoTable
3914 /****************************************************************************/
3915 typedef struct _ATOM_OBJECT_HEADER
3917 ATOM_COMMON_TABLE_HEADER sHeader;
3918 USHORT usDeviceSupport;
3919 USHORT usConnectorObjectTableOffset;
3920 USHORT usRouterObjectTableOffset;
3921 USHORT usEncoderObjectTableOffset;
3922 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
3923 USHORT usDisplayPathTableOffset;
3924 }ATOM_OBJECT_HEADER;
3926 typedef struct _ATOM_OBJECT_HEADER_V3
3928 ATOM_COMMON_TABLE_HEADER sHeader;
3929 USHORT usDeviceSupport;
3930 USHORT usConnectorObjectTableOffset;
3931 USHORT usRouterObjectTableOffset;
3932 USHORT usEncoderObjectTableOffset;
3933 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
3934 USHORT usDisplayPathTableOffset;
3935 USHORT usMiscObjectTableOffset;
3936 }ATOM_OBJECT_HEADER_V3;
3938 typedef struct _ATOM_DISPLAY_OBJECT_PATH
3940 USHORT usDeviceTag; //supported device
3941 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
3942 USHORT usConnObjectId; //Connector Object ID
3943 USHORT usGPUObjectId; //GPU ID
3944 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
3945 }ATOM_DISPLAY_OBJECT_PATH;
3947 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
3949 USHORT usDeviceTag; //supported device
3950 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
3951 USHORT usConnObjectId; //Connector Object ID
3952 USHORT usGPUObjectId; //GPU ID
3953 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
3954 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
3956 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
3958 UCHAR ucNumOfDispPath;
3961 ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
3962 }ATOM_DISPLAY_OBJECT_PATH_TABLE;
3965 typedef struct _ATOM_OBJECT //each object has this structure
3968 USHORT usSrcDstTableOffset;
3969 USHORT usRecordOffset; //this pointing to a bunch of records defined below
3973 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
3975 UCHAR ucNumberOfObjects;
3977 ATOM_OBJECT asObjects[1];
3980 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
3982 UCHAR ucNumberOfSrc;
3983 USHORT usSrcObjectID[1];
3984 UCHAR ucNumberOfDst;
3985 USHORT usDstObjectID[1];
3986 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
3989 //Two definitions below are for OPM on MXM module designs
3991 #define EXT_HPDPIN_LUTINDEX_0 0
3992 #define EXT_HPDPIN_LUTINDEX_1 1
3993 #define EXT_HPDPIN_LUTINDEX_2 2
3994 #define EXT_HPDPIN_LUTINDEX_3 3
3995 #define EXT_HPDPIN_LUTINDEX_4 4
3996 #define EXT_HPDPIN_LUTINDEX_5 5
3997 #define EXT_HPDPIN_LUTINDEX_6 6
3998 #define EXT_HPDPIN_LUTINDEX_7 7
3999 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
4001 #define EXT_AUXDDC_LUTINDEX_0 0
4002 #define EXT_AUXDDC_LUTINDEX_1 1
4003 #define EXT_AUXDDC_LUTINDEX_2 2
4004 #define EXT_AUXDDC_LUTINDEX_3 3
4005 #define EXT_AUXDDC_LUTINDEX_4 4
4006 #define EXT_AUXDDC_LUTINDEX_5 5
4007 #define EXT_AUXDDC_LUTINDEX_6 6
4008 #define EXT_AUXDDC_LUTINDEX_7 7
4009 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
4011 //ucChannelMapping are defined as following
4012 //for DP connector, eDP, DP to VGA/LVDS
4013 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4014 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4015 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4016 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4017 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
4020 UCHAR ucDP_Lane3_Source:2;
4021 UCHAR ucDP_Lane2_Source:2;
4022 UCHAR ucDP_Lane1_Source:2;
4023 UCHAR ucDP_Lane0_Source:2;
4025 UCHAR ucDP_Lane0_Source:2;
4026 UCHAR ucDP_Lane1_Source:2;
4027 UCHAR ucDP_Lane2_Source:2;
4028 UCHAR ucDP_Lane3_Source:2;
4030 }ATOM_DP_CONN_CHANNEL_MAPPING;
4032 //for DVI/HDMI, in dual link case, both links have to have same mapping.
4033 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4034 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4035 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4036 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4037 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
4040 UCHAR ucDVI_CLK_Source:2;
4041 UCHAR ucDVI_DATA0_Source:2;
4042 UCHAR ucDVI_DATA1_Source:2;
4043 UCHAR ucDVI_DATA2_Source:2;
4045 UCHAR ucDVI_DATA2_Source:2;
4046 UCHAR ucDVI_DATA1_Source:2;
4047 UCHAR ucDVI_DATA0_Source:2;
4048 UCHAR ucDVI_CLK_Source:2;
4050 }ATOM_DVI_CONN_CHANNEL_MAPPING;
4052 typedef struct _EXT_DISPLAY_PATH
4054 USHORT usDeviceTag; //A bit vector to show what devices are supported
4055 USHORT usDeviceACPIEnum; //16bit device ACPI id.
4056 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
4057 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4058 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4059 USHORT usExtEncoderObjId; //external encoder object id
4061 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
4062 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
4063 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
4065 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4070 #define NUMBER_OF_UCHAR_FOR_GUID 16
4071 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
4074 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01
4076 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
4078 ATOM_COMMON_TABLE_HEADER sHeader;
4079 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4080 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4081 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
4082 UCHAR uc3DStereoPinId; // use for eDP panel
4083 UCHAR ucRemoteDisplayConfig;
4084 UCHAR uceDPToLVDSRxId;
4085 UCHAR Reserved[4]; // for potential expansion
4086 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
4088 //Related definitions, all records are different but they have a commond header
4089 typedef struct _ATOM_COMMON_RECORD_HEADER
4091 UCHAR ucRecordType; //An emun to indicate the record type
4092 UCHAR ucRecordSize; //The size of the whole record in byte
4093 }ATOM_COMMON_RECORD_HEADER;
4096 #define ATOM_I2C_RECORD_TYPE 1
4097 #define ATOM_HPD_INT_RECORD_TYPE 2
4098 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
4099 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
4100 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4101 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4102 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
4103 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4104 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
4105 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
4106 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11
4107 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
4108 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
4109 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
4110 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
4111 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table
4112 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
4113 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
4114 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
4115 #define ATOM_ENCODER_CAP_RECORD_TYPE 20
4118 //Must be updated when new record type is added,equal to that record definition!
4119 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE
4121 typedef struct _ATOM_I2C_RECORD
4123 ATOM_COMMON_RECORD_HEADER sheader;
4124 ATOM_I2C_ID_CONFIG sucI2cId;
4125 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
4128 typedef struct _ATOM_HPD_INT_RECORD
4130 ATOM_COMMON_RECORD_HEADER sheader;
4131 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4132 UCHAR ucPlugged_PinState;
4133 }ATOM_HPD_INT_RECORD;
4136 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
4138 ATOM_COMMON_RECORD_HEADER sheader;
4139 UCHAR ucProtectionFlag;
4141 }ATOM_OUTPUT_PROTECTION_RECORD;
4143 typedef struct _ATOM_CONNECTOR_DEVICE_TAG
4145 ULONG ulACPIDeviceEnum; //Reserved for now
4146 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
4148 }ATOM_CONNECTOR_DEVICE_TAG;
4150 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
4152 ATOM_COMMON_RECORD_HEADER sheader;
4153 UCHAR ucNumberOfDevice;
4155 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
4156 }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
4159 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
4161 ATOM_COMMON_RECORD_HEADER sheader;
4162 UCHAR ucConfigGPIOID;
4163 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4164 UCHAR ucFlowinGPIPID;
4165 UCHAR ucExtInGPIPID;
4166 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
4168 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
4170 ATOM_COMMON_RECORD_HEADER sheader;
4171 UCHAR ucCTL1GPIO_ID;
4172 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4173 UCHAR ucCTL2GPIO_ID;
4174 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4175 UCHAR ucCTL3GPIO_ID;
4176 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4177 UCHAR ucCTLFPGA_IN_ID;
4179 }ATOM_ENCODER_FPGA_CONTROL_RECORD;
4181 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
4183 ATOM_COMMON_RECORD_HEADER sheader;
4184 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4185 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
4186 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
4188 typedef struct _ATOM_JTAG_RECORD
4190 ATOM_COMMON_RECORD_HEADER sheader;
4192 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4194 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4196 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4198 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4203 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
4204 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
4206 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
4207 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4208 }ATOM_GPIO_PIN_CONTROL_PAIR;
4210 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
4212 ATOM_COMMON_RECORD_HEADER sheader;
4213 UCHAR ucFlags; // Future expnadibility
4214 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
4215 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
4216 }ATOM_OBJECT_GPIO_CNTL_RECORD;
4218 //Definitions for GPIO pin state
4219 #define GPIO_PIN_TYPE_INPUT 0x00
4220 #define GPIO_PIN_TYPE_OUTPUT 0x10
4221 #define GPIO_PIN_TYPE_HW_CONTROL 0x20
4223 //For GPIO_PIN_TYPE_OUTPUT the following is defined
4224 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01
4225 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0
4226 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0
4227 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
4229 // Indexes to GPIO array in GLSync record
4230 // GLSync record is for Frame Lock/Gen Lock feature.
4231 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0
4232 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
4233 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
4234 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3
4235 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
4236 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
4237 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6
4238 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4239 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8
4240 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9
4242 typedef struct _ATOM_ENCODER_DVO_CF_RECORD
4244 ATOM_COMMON_RECORD_HEADER sheader;
4245 ULONG ulStrengthControl; // DVOA strength control for CF
4247 }ATOM_ENCODER_DVO_CF_RECORD;
4249 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
4250 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder
4251 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
4253 typedef struct _ATOM_ENCODER_CAP_RECORD
4255 ATOM_COMMON_RECORD_HEADER sheader;
4257 USHORT usEncoderCap;
4260 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4261 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4262 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4264 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4265 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4266 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4270 }ATOM_ENCODER_CAP_RECORD;
4272 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
4273 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
4274 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
4276 typedef struct _ATOM_CONNECTOR_CF_RECORD
4278 ATOM_COMMON_RECORD_HEADER sheader;
4280 UCHAR ucFlowCntlGpioId;
4281 UCHAR ucSwapCntlGpioId;
4282 UCHAR ucConnectedDvoBundle;
4284 }ATOM_CONNECTOR_CF_RECORD;
4286 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
4288 ATOM_COMMON_RECORD_HEADER sheader;
4289 ATOM_DTD_FORMAT asTiming;
4290 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
4292 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
4294 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
4295 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4297 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
4300 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
4302 ATOM_COMMON_RECORD_HEADER sheader;
4303 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4304 UCHAR ucMuxControlPin;
4305 UCHAR ucMuxState[2]; //for alligment purpose
4306 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
4308 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
4310 ATOM_COMMON_RECORD_HEADER sheader;
4312 UCHAR ucMuxControlPin;
4313 UCHAR ucMuxState[2]; //for alligment purpose
4314 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
4317 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
4318 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
4320 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
4322 ATOM_COMMON_RECORD_HEADER sheader;
4323 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4324 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
4326 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
4328 ATOM_COMMON_RECORD_HEADER sheader;
4329 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
4330 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
4332 typedef struct _ATOM_OBJECT_LINK_RECORD
4334 ATOM_COMMON_RECORD_HEADER sheader;
4335 USHORT usObjectID; //could be connector, encorder or other object in object.h
4336 }ATOM_OBJECT_LINK_RECORD;
4338 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
4340 ATOM_COMMON_RECORD_HEADER sheader;
4342 }ATOM_CONNECTOR_REMOTE_CAP_RECORD;
4344 /****************************************************************************/
4345 // ASIC voltage data table
4346 /****************************************************************************/
4347 typedef struct _ATOM_VOLTAGE_INFO_HEADER
4349 USHORT usVDDCBaseLevel; //In number of 50mv unit
4350 USHORT usReserved; //For possible extension table offset
4351 UCHAR ucNumOfVoltageEntries;
4352 UCHAR ucBytesPerVoltageEntry;
4353 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
4354 UCHAR ucDefaultVoltageEntry;
4355 UCHAR ucVoltageControlI2cLine;
4356 UCHAR ucVoltageControlAddress;
4357 UCHAR ucVoltageControlOffset;
4358 }ATOM_VOLTAGE_INFO_HEADER;
4360 typedef struct _ATOM_VOLTAGE_INFO
4362 ATOM_COMMON_TABLE_HEADER sHeader;
4363 ATOM_VOLTAGE_INFO_HEADER viHeader;
4364 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
4368 typedef struct _ATOM_VOLTAGE_FORMULA
4370 USHORT usVoltageBaseLevel; // In number of 1mv unit
4371 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
4372 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4373 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
4374 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
4376 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
4377 }ATOM_VOLTAGE_FORMULA;
4379 typedef struct _VOLTAGE_LUT_ENTRY
4381 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
4382 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
4385 typedef struct _ATOM_VOLTAGE_FORMULA_V2
4387 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4388 UCHAR ucReserved[3];
4389 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
4390 }ATOM_VOLTAGE_FORMULA_V2;
4392 typedef struct _ATOM_VOLTAGE_CONTROL
4394 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
4395 UCHAR ucVoltageControlI2cLine;
4396 UCHAR ucVoltageControlAddress;
4397 UCHAR ucVoltageControlOffset;
4398 USHORT usGpioPin_AIndex; //GPIO_PAD register index
4399 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
4401 }ATOM_VOLTAGE_CONTROL;
4403 // Define ucVoltageControlId
4404 #define VOLTAGE_CONTROLLED_BY_HW 0x00
4405 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
4406 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80
4407 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
4408 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
4409 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
4410 #define VOLTAGE_CONTROL_ID_DS4402 0x04
4411 #define VOLTAGE_CONTROL_ID_UP6266 0x05
4412 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06
4413 #define VOLTAGE_CONTROL_ID_VT1556M 0x07
4414 #define VOLTAGE_CONTROL_ID_CHL822x 0x08
4415 #define VOLTAGE_CONTROL_ID_VT1586M 0x09
4416 #define VOLTAGE_CONTROL_ID_UP1637 0x0A
4418 typedef struct _ATOM_VOLTAGE_OBJECT
4420 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4421 UCHAR ucSize; //Size of Object
4422 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
4423 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
4424 }ATOM_VOLTAGE_OBJECT;
4426 typedef struct _ATOM_VOLTAGE_OBJECT_V2
4428 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4429 UCHAR ucSize; //Size of Object
4430 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
4431 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
4432 }ATOM_VOLTAGE_OBJECT_V2;
4434 typedef struct _ATOM_VOLTAGE_OBJECT_INFO
4436 ATOM_COMMON_TABLE_HEADER sHeader;
4437 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
4438 }ATOM_VOLTAGE_OBJECT_INFO;
4440 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2
4442 ATOM_COMMON_TABLE_HEADER sHeader;
4443 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
4444 }ATOM_VOLTAGE_OBJECT_INFO_V2;
4446 typedef struct _ATOM_LEAKID_VOLTAGE
4451 }ATOM_LEAKID_VOLTAGE;
4453 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
4454 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4455 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
4456 USHORT usSize; //Size of Object
4457 }ATOM_VOLTAGE_OBJECT_HEADER_V3;
4459 typedef struct _VOLTAGE_LUT_ENTRY_V2
4461 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
4462 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
4463 }VOLTAGE_LUT_ENTRY_V2;
4465 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
4467 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register
4469 USHORT usLeakageId; // The corresponding Voltage Value, in mV
4470 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
4472 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3
4474 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4475 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
4476 UCHAR ucVoltageControlI2cLine;
4477 UCHAR ucVoltageControlAddress;
4478 UCHAR ucVoltageControlOffset;
4480 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
4481 }ATOM_I2C_VOLTAGE_OBJECT_V3;
4483 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3
4485 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4486 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
4487 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
4488 UCHAR ucPhaseDelay; // phase delay in unit of micro second
4490 ULONG ulGpioMaskVal; // GPIO Mask value
4491 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
4492 }ATOM_GPIO_VOLTAGE_OBJECT_V3;
4494 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4496 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4497 UCHAR ucLeakageCntlId; // default is 0
4498 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
4499 UCHAR ucReserved[2];
4500 ULONG ulMaxVoltageLevel;
4501 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
4502 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
4504 typedef union _ATOM_VOLTAGE_OBJECT_V3{
4505 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
4506 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
4507 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
4508 }ATOM_VOLTAGE_OBJECT_V3;
4510 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1
4512 ATOM_COMMON_TABLE_HEADER sHeader;
4513 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control
4514 }ATOM_VOLTAGE_OBJECT_INFO_V3_1;
4516 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
4521 USHORT usEfuseSpareStartAddr;
4522 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
4523 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
4524 }ATOM_ASIC_PROFILE_VOLTAGE;
4527 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
4528 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
4529 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
4531 typedef struct _ATOM_ASIC_PROFILING_INFO
4533 ATOM_COMMON_TABLE_HEADER asHeader;
4534 ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
4535 }ATOM_ASIC_PROFILING_INFO;
4537 typedef struct _ATOM_POWER_SOURCE_OBJECT
4539 UCHAR ucPwrSrcId; // Power source
4540 UCHAR ucPwrSensorType; // GPIO, I2C or none
4541 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
4542 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
4543 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
4544 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
4545 UCHAR ucPwrSensActiveState; // high active or low active
4546 UCHAR ucReserve[3]; // reserve
4547 USHORT usSensPwr; // in unit of watt
4548 }ATOM_POWER_SOURCE_OBJECT;
4550 typedef struct _ATOM_POWER_SOURCE_INFO
4552 ATOM_COMMON_TABLE_HEADER asHeader;
4553 UCHAR asPwrbehave[16];
4554 ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
4555 }ATOM_POWER_SOURCE_INFO;
4559 #define POWERSOURCE_PCIE_ID1 0x00
4560 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
4561 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
4562 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
4563 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
4565 //define ucPwrSensorId
4566 #define POWER_SENSOR_ALWAYS 0x00
4567 #define POWER_SENSOR_GPIO 0x01
4568 #define POWER_SENSOR_I2C 0x02
4570 typedef struct _ATOM_CLK_VOLT_CAPABILITY
4572 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
4573 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4574 }ATOM_CLK_VOLT_CAPABILITY;
4576 typedef struct _ATOM_AVAILABLE_SCLK_LIST
4578 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4579 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
4580 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
4581 }ATOM_AVAILABLE_SCLK_LIST;
4583 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
4584 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
4586 // this IntegrateSystemInfoTable is used for Liano/Ontario APU
4587 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
4589 ATOM_COMMON_TABLE_HEADER sHeader;
4590 ULONG ulBootUpEngineClock;
4591 ULONG ulDentistVCOFreq;
4592 ULONG ulBootUpUMAClock;
4593 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
4594 ULONG ulBootUpReqDisplayVector;
4595 ULONG ulOtherDisplayMisc;
4597 ULONG ulSB_MMIO_Base_Addr;
4598 USHORT usRequestedPWMFreqInHz;
4601 ULONG ulMinEngineClock;
4602 ULONG ulSystemConfig;
4604 USHORT usNBP0Voltage;
4605 USHORT usNBP1Voltage;
4606 USHORT usBootUpNBVoltage;
4607 USHORT usExtDispConnInfoOffset;
4608 USHORT usPanelRefreshRateRange;
4610 UCHAR ucUMAChannelNumber;
4611 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
4612 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
4613 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
4614 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
4615 ULONG ulGMCRestoreResetTime;
4616 ULONG ulMinimumNClk;
4618 ULONG ulDDR_DLL_PowerUpTime;
4619 ULONG ulDDR_PLL_PowerUpTime;
4620 USHORT usPCIEClkSSPercentage;
4621 USHORT usPCIEClkSSType;
4622 USHORT usLvdsSSPercentage;
4623 USHORT usLvdsSSpreadRateIn10Hz;
4624 USHORT usHDMISSPercentage;
4625 USHORT usHDMISSpreadRateIn10Hz;
4626 USHORT usDVISSPercentage;
4627 USHORT usDVISSpreadRateIn10Hz;
4628 ULONG SclkDpmBoostMargin;
4629 ULONG SclkDpmThrottleMargin;
4630 USHORT SclkDpmTdpLimitPG;
4631 USHORT SclkDpmTdpLimitBoost;
4632 ULONG ulBoostEngineCLock;
4633 UCHAR ulBoostVid_2bit;
4636 USHORT usMaxLVDSPclkFreqInSingleLink;
4638 UCHAR ucLVDSReserved;
4639 ULONG ulReserved3[15];
4640 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
4641 }ATOM_INTEGRATED_SYSTEM_INFO_V6;
4644 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
4645 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08
4648 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01
4649 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02
4650 #define SYS_INFO_LVDSMISC__888_BPC 0x04
4651 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08
4652 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10
4654 // not used any more
4655 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04
4656 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08
4658 /**********************************************************************************************************************
4659 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
4660 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
4661 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
4662 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
4663 sDISPCLK_Voltage: Report Display clock voltage requirement.
4665 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
4666 ATOM_DEVICE_CRT1_SUPPORT 0x0001
4667 ATOM_DEVICE_CRT2_SUPPORT 0x0010
4668 ATOM_DEVICE_DFP1_SUPPORT 0x0008
4669 ATOM_DEVICE_DFP6_SUPPORT 0x0040
4670 ATOM_DEVICE_DFP2_SUPPORT 0x0080
4671 ATOM_DEVICE_DFP3_SUPPORT 0x0200
4672 ATOM_DEVICE_DFP4_SUPPORT 0x0400
4673 ATOM_DEVICE_DFP5_SUPPORT 0x0800
4674 ATOM_DEVICE_LCD1_SUPPORT 0x0002
4675 ulOtherDisplayMisc: Other display related flags, not defined yet.
4676 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4677 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4678 bit[3]=0: Enable HW AUX mode detection logic
4679 =1: Disable HW AUX mode dettion logic
4680 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
4682 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4683 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
4685 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
4686 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4687 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4688 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4689 and enabling VariBri under the driver environment from PP table is optional.
4691 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
4692 that BL control from GPU is expected.
4693 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4694 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
4696 and enabling VariBri under the driver environment from PP table is optional.
4698 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4699 Threshold on value to enter HTC_active state.
4700 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
4701 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
4702 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
4703 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
4704 =1: PCIE Power Gating Enabled
4705 Bit[1]=0: DDR-DLL shut-down feature disabled.
4706 1: DDR-DLL shut-down feature enabled.
4707 Bit[2]=0: DDR-PLL Power down feature disabled.
4708 1: DDR-PLL Power down feature enabled.
4710 usNBP0Voltage: VID for voltage on NB P0 State
4711 usNBP1Voltage: VID for voltage on NB P1 State
4712 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
4713 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
4714 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4715 to indicate a range.
4716 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
4717 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
4718 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
4719 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
4720 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4721 ucUMAChannelNumber: System memory channel numbers.
4722 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
4723 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
4724 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4725 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
4726 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4727 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4728 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4729 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4730 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4731 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
4732 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4733 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4734 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4735 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4736 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4737 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4738 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4739 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
4740 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
4741 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
4742 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
4743 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
4744 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
4745 **********************************************************************************************************************/
4747 // this Table is used for Liano/Ontario APU
4748 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
4750 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo;
4751 ULONG ulPowerplayTable[128];
4752 }ATOM_FUSION_SYSTEM_INFO_V1;
4753 /**********************************************************************************************************************
4754 ATOM_FUSION_SYSTEM_INFO_V1 Description
4755 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
4756 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
4757 **********************************************************************************************************************/
4759 // this IntegrateSystemInfoTable is used for Trinity APU
4760 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
4762 ATOM_COMMON_TABLE_HEADER sHeader;
4763 ULONG ulBootUpEngineClock;
4764 ULONG ulDentistVCOFreq;
4765 ULONG ulBootUpUMAClock;
4766 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
4767 ULONG ulBootUpReqDisplayVector;
4768 ULONG ulOtherDisplayMisc;
4770 ULONG ulSB_MMIO_Base_Addr;
4771 USHORT usRequestedPWMFreqInHz;
4774 ULONG ulMinEngineClock;
4775 ULONG ulSystemConfig;
4777 USHORT usNBP0Voltage;
4778 USHORT usNBP1Voltage;
4779 USHORT usBootUpNBVoltage;
4780 USHORT usExtDispConnInfoOffset;
4781 USHORT usPanelRefreshRateRange;
4783 UCHAR ucUMAChannelNumber;
4784 UCHAR strVBIOSMsg[40];
4785 ULONG ulReserved[20];
4786 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
4787 ULONG ulGMCRestoreResetTime;
4788 ULONG ulMinimumNClk;
4790 ULONG ulDDR_DLL_PowerUpTime;
4791 ULONG ulDDR_PLL_PowerUpTime;
4792 USHORT usPCIEClkSSPercentage;
4793 USHORT usPCIEClkSSType;
4794 USHORT usLvdsSSPercentage;
4795 USHORT usLvdsSSpreadRateIn10Hz;
4796 USHORT usHDMISSPercentage;
4797 USHORT usHDMISSpreadRateIn10Hz;
4798 USHORT usDVISSPercentage;
4799 USHORT usDVISSpreadRateIn10Hz;
4800 ULONG SclkDpmBoostMargin;
4801 ULONG SclkDpmThrottleMargin;
4802 USHORT SclkDpmTdpLimitPG;
4803 USHORT SclkDpmTdpLimitBoost;
4804 ULONG ulBoostEngineCLock;
4805 UCHAR ulBoostVid_2bit;
4808 USHORT usMaxLVDSPclkFreqInSingleLink;
4810 UCHAR ucLVDSReserved;
4811 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
4812 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
4813 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
4814 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
4815 UCHAR ucLVDSOffToOnDelay_in4Ms;
4816 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
4817 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
4818 UCHAR ucLVDSReserved1;
4819 ULONG ulLCDBitDepthControlVal;
4820 ULONG ulNbpStateMemclkFreq[4];
4821 USHORT usNBP2Voltage;
4822 USHORT usNBP3Voltage;
4823 ULONG ulNbpStateNClkFreq[4];
4824 UCHAR ucNBDPMEnable;
4825 UCHAR ucReserved[3];
4826 UCHAR ucDPMState0VclkFid;
4827 UCHAR ucDPMState0DclkFid;
4828 UCHAR ucDPMState1VclkFid;
4829 UCHAR ucDPMState1DclkFid;
4830 UCHAR ucDPMState2VclkFid;
4831 UCHAR ucDPMState2DclkFid;
4832 UCHAR ucDPMState3VclkFid;
4833 UCHAR ucDPMState3DclkFid;
4834 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
4835 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
4837 // ulOtherDisplayMisc
4838 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01
4839 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02
4840 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04
4841 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08
4844 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
4845 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02
4846 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08
4848 /**********************************************************************************************************************
4849 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
4850 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
4851 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
4852 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
4853 sDISPCLK_Voltage: Report Display clock voltage requirement.
4855 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
4856 ATOM_DEVICE_CRT1_SUPPORT 0x0001
4857 ATOM_DEVICE_DFP1_SUPPORT 0x0008
4858 ATOM_DEVICE_DFP6_SUPPORT 0x0040
4859 ATOM_DEVICE_DFP2_SUPPORT 0x0080
4860 ATOM_DEVICE_DFP3_SUPPORT 0x0200
4861 ATOM_DEVICE_DFP4_SUPPORT 0x0400
4862 ATOM_DEVICE_DFP5_SUPPORT 0x0800
4863 ATOM_DEVICE_LCD1_SUPPORT 0x0002
4864 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
4865 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
4866 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
4867 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
4868 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
4869 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
4870 bit[3]=0: VBIOS fast boot is disable
4871 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
4872 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4873 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4874 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
4875 =1: DP mode use single PLL mode
4876 bit[3]=0: Enable AUX HW mode detection logic
4877 =1: Disable AUX HW mode detection logic
4879 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
4881 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4882 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
4884 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
4885 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4886 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4887 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4888 and enabling VariBri under the driver environment from PP table is optional.
4890 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
4891 that BL control from GPU is expected.
4892 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4893 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
4895 and enabling VariBri under the driver environment from PP table is optional.
4897 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4898 Threshold on value to enter HTC_active state.
4899 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
4900 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
4901 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
4902 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
4903 =1: PCIE Power Gating Enabled
4904 Bit[1]=0: DDR-DLL shut-down feature disabled.
4905 1: DDR-DLL shut-down feature enabled.
4906 Bit[2]=0: DDR-PLL Power down feature disabled.
4907 1: DDR-PLL Power down feature enabled.
4909 usNBP0Voltage: VID for voltage on NB P0 State
4910 usNBP1Voltage: VID for voltage on NB P1 State
4911 usNBP2Voltage: VID for voltage on NB P2 State
4912 usNBP3Voltage: VID for voltage on NB P3 State
4913 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
4914 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
4915 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4916 to indicate a range.
4917 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
4918 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
4919 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
4920 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
4921 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4922 ucUMAChannelNumber: System memory channel numbers.
4923 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
4924 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
4925 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4926 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
4927 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4928 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4929 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4930 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4931 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4932 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
4933 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4934 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4935 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4936 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4937 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4938 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4939 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4940 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
4941 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
4942 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
4943 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
4944 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
4945 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
4946 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
4947 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
4948 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4949 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
4950 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
4951 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4953 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
4954 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
4955 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4957 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
4958 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
4959 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4961 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
4962 =0 means to use VBIOS default delay which is 125 ( 500ms ).
4963 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4965 ucLVDSPwrOnVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
4966 =0 means to use VBIOS default delay which is 0 ( 0ms ).
4967 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4969 ucLVDSPwrOffBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
4970 =0 means to use VBIOS default delay which is 0 ( 0ms ).
4971 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4973 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate.
4975 **********************************************************************************************************************/
4977 /**************************************************************************/
4978 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
4979 //Memory SS Info Table
4980 //Define Memory Clock SS chip ID
4984 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
4985 typedef struct _ATOM_I2C_DATA_RECORD
4987 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
4988 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
4989 }ATOM_I2C_DATA_RECORD;
4992 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
4993 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
4995 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
4996 UCHAR ucSSChipID; //SS chip being used
4997 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
4998 UCHAR ucNumOfI2CDataRecords; //number of data block
4999 ATOM_I2C_DATA_RECORD asI2CData[1];
5000 }ATOM_I2C_DEVICE_SETUP_INFO;
5002 //==========================================================================================
5003 typedef struct _ATOM_ASIC_MVDD_INFO
5005 ATOM_COMMON_TABLE_HEADER sHeader;
5006 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
5007 }ATOM_ASIC_MVDD_INFO;
5009 //==========================================================================================
5010 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
5012 //==========================================================================================
5013 /**************************************************************************/
5015 typedef struct _ATOM_ASIC_SS_ASSIGNMENT
5017 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5018 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
5019 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
5020 UCHAR ucClockIndication; //Indicate which clock source needs SS
5021 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
5022 UCHAR ucReserved[2];
5023 }ATOM_ASIC_SS_ASSIGNMENT;
5025 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
5026 //SS is not required or enabled if a match is not found.
5027 #define ASIC_INTERNAL_MEMORY_SS 1
5028 #define ASIC_INTERNAL_ENGINE_SS 2
5029 #define ASIC_INTERNAL_UVD_SS 3
5030 #define ASIC_INTERNAL_SS_ON_TMDS 4
5031 #define ASIC_INTERNAL_SS_ON_HDMI 5
5032 #define ASIC_INTERNAL_SS_ON_LVDS 6
5033 #define ASIC_INTERNAL_SS_ON_DP 7
5034 #define ASIC_INTERNAL_SS_ON_DCPLL 8
5035 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
5036 #define ASIC_INTERNAL_VCE_SS 10
5038 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
5040 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5041 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5042 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
5043 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
5044 UCHAR ucClockIndication; //Indicate which clock source needs SS
5045 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5046 UCHAR ucReserved[2];
5047 }ATOM_ASIC_SS_ASSIGNMENT_V2;
5049 //ucSpreadSpectrumMode
5050 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
5051 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
5052 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
5053 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
5054 //#define ATOM_INTERNAL_SS_MASK 0x00000000
5055 //#define ATOM_EXTERNAL_SS_MASK 0x00000002
5057 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
5059 ATOM_COMMON_TABLE_HEADER sHeader;
5060 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
5061 }ATOM_ASIC_INTERNAL_SS_INFO;
5063 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
5065 ATOM_COMMON_TABLE_HEADER sHeader;
5066 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
5067 }ATOM_ASIC_INTERNAL_SS_INFO_V2;
5069 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
5071 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5072 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5073 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
5074 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
5075 UCHAR ucClockIndication; //Indicate which clock source needs SS
5076 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5077 UCHAR ucReserved[2];
5078 }ATOM_ASIC_SS_ASSIGNMENT_V3;
5080 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
5082 ATOM_COMMON_TABLE_HEADER sHeader;
5083 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
5084 }ATOM_ASIC_INTERNAL_SS_INFO_V3;
5087 //==============================Scratch Pad Definition Portion===============================
5088 #define ATOM_DEVICE_CONNECT_INFO_DEF 0
5089 #define ATOM_ROM_LOCATION_DEF 1
5090 #define ATOM_TV_STANDARD_DEF 2
5091 #define ATOM_ACTIVE_INFO_DEF 3
5092 #define ATOM_LCD_INFO_DEF 4
5093 #define ATOM_DOS_REQ_INFO_DEF 5
5094 #define ATOM_ACC_CHANGE_INFO_DEF 6
5095 #define ATOM_DOS_MODE_INFO_DEF 7
5096 #define ATOM_I2C_CHANNEL_STATUS_DEF 8
5097 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9
5098 #define ATOM_INTERNAL_TIMER_DEF 10
5100 // BIOS_0_SCRATCH Definition
5101 #define ATOM_S0_CRT1_MONO 0x00000001L
5102 #define ATOM_S0_CRT1_COLOR 0x00000002L
5103 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
5105 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
5106 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L
5107 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
5109 #define ATOM_S0_CV_A 0x00000010L
5110 #define ATOM_S0_CV_DIN_A 0x00000020L
5111 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
5114 #define ATOM_S0_CRT2_MONO 0x00000100L
5115 #define ATOM_S0_CRT2_COLOR 0x00000200L
5116 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
5118 #define ATOM_S0_TV1_COMPOSITE 0x00000400L
5119 #define ATOM_S0_TV1_SVIDEO 0x00000800L
5120 #define ATOM_S0_TV1_SCART 0x00004000L
5121 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
5123 #define ATOM_S0_CV 0x00001000L
5124 #define ATOM_S0_CV_DIN 0x00002000L
5125 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
5127 #define ATOM_S0_DFP1 0x00010000L
5128 #define ATOM_S0_DFP2 0x00020000L
5129 #define ATOM_S0_LCD1 0x00040000L
5130 #define ATOM_S0_LCD2 0x00080000L
5131 #define ATOM_S0_DFP6 0x00100000L
5132 #define ATOM_S0_DFP3 0x00200000L
5133 #define ATOM_S0_DFP4 0x00400000L
5134 #define ATOM_S0_DFP5 0x00800000L
5136 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
5138 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
5139 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
5141 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
5142 #define ATOM_S0_THERMAL_STATE_SHIFT 26
5144 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
5145 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
5147 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
5148 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
5149 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
5150 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
5152 //Byte aligned definition for BIOS usage
5153 #define ATOM_S0_CRT1_MONOb0 0x01
5154 #define ATOM_S0_CRT1_COLORb0 0x02
5155 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
5157 #define ATOM_S0_TV1_COMPOSITEb0 0x04
5158 #define ATOM_S0_TV1_SVIDEOb0 0x08
5159 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
5161 #define ATOM_S0_CVb0 0x10
5162 #define ATOM_S0_CV_DINb0 0x20
5163 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
5165 #define ATOM_S0_CRT2_MONOb1 0x01
5166 #define ATOM_S0_CRT2_COLORb1 0x02
5167 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
5169 #define ATOM_S0_TV1_COMPOSITEb1 0x04
5170 #define ATOM_S0_TV1_SVIDEOb1 0x08
5171 #define ATOM_S0_TV1_SCARTb1 0x40
5172 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
5174 #define ATOM_S0_CVb1 0x10
5175 #define ATOM_S0_CV_DINb1 0x20
5176 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
5178 #define ATOM_S0_DFP1b2 0x01
5179 #define ATOM_S0_DFP2b2 0x02
5180 #define ATOM_S0_LCD1b2 0x04
5181 #define ATOM_S0_LCD2b2 0x08
5182 #define ATOM_S0_DFP6b2 0x10
5183 #define ATOM_S0_DFP3b2 0x20
5184 #define ATOM_S0_DFP4b2 0x40
5185 #define ATOM_S0_DFP5b2 0x80
5188 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
5189 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2
5191 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
5192 #define ATOM_S0_LCD1_SHIFT 18
5194 // BIOS_1_SCRATCH Definition
5195 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
5196 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
5198 // BIOS_2_SCRATCH Definition
5199 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
5200 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
5201 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
5203 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
5204 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
5205 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
5207 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L
5208 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
5210 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
5211 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
5212 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
5213 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
5214 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
5215 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
5218 //Byte aligned definition for BIOS usage
5219 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
5220 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
5221 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
5223 #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
5224 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
5225 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10
5226 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
5227 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
5228 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
5231 // BIOS_3_SCRATCH Definition
5232 #define ATOM_S3_CRT1_ACTIVE 0x00000001L
5233 #define ATOM_S3_LCD1_ACTIVE 0x00000002L
5234 #define ATOM_S3_TV1_ACTIVE 0x00000004L
5235 #define ATOM_S3_DFP1_ACTIVE 0x00000008L
5236 #define ATOM_S3_CRT2_ACTIVE 0x00000010L
5237 #define ATOM_S3_LCD2_ACTIVE 0x00000020L
5238 #define ATOM_S3_DFP6_ACTIVE 0x00000040L
5239 #define ATOM_S3_DFP2_ACTIVE 0x00000080L
5240 #define ATOM_S3_CV_ACTIVE 0x00000100L
5241 #define ATOM_S3_DFP3_ACTIVE 0x00000200L
5242 #define ATOM_S3_DFP4_ACTIVE 0x00000400L
5243 #define ATOM_S3_DFP5_ACTIVE 0x00000800L
5245 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL
5247 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
5248 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
5250 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
5251 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
5252 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
5253 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
5254 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
5255 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
5256 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L
5257 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
5258 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
5259 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
5260 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L
5261 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L
5263 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
5264 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
5265 //Below two definitions are not supported in pplib, but in the old powerplay in DAL
5266 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
5267 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
5269 //Byte aligned definition for BIOS usage
5270 #define ATOM_S3_CRT1_ACTIVEb0 0x01
5271 #define ATOM_S3_LCD1_ACTIVEb0 0x02
5272 #define ATOM_S3_TV1_ACTIVEb0 0x04
5273 #define ATOM_S3_DFP1_ACTIVEb0 0x08
5274 #define ATOM_S3_CRT2_ACTIVEb0 0x10
5275 #define ATOM_S3_LCD2_ACTIVEb0 0x20
5276 #define ATOM_S3_DFP6_ACTIVEb0 0x40
5277 #define ATOM_S3_DFP2_ACTIVEb0 0x80
5278 #define ATOM_S3_CV_ACTIVEb1 0x01
5279 #define ATOM_S3_DFP3_ACTIVEb1 0x02
5280 #define ATOM_S3_DFP4_ACTIVEb1 0x04
5281 #define ATOM_S3_DFP5_ACTIVEb1 0x08
5283 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF
5285 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
5286 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
5287 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
5288 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
5289 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
5290 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
5291 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40
5292 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
5293 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
5294 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
5295 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04
5296 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08
5298 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
5300 // BIOS_4_SCRATCH Definition
5301 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
5302 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
5303 #define ATOM_S4_LCD1_REFRESH_SHIFT 8
5305 //Byte aligned definition for BIOS usage
5306 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
5307 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
5308 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
5310 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
5311 #define ATOM_S5_DOS_REQ_CRT1b0 0x01
5312 #define ATOM_S5_DOS_REQ_LCD1b0 0x02
5313 #define ATOM_S5_DOS_REQ_TV1b0 0x04
5314 #define ATOM_S5_DOS_REQ_DFP1b0 0x08
5315 #define ATOM_S5_DOS_REQ_CRT2b0 0x10
5316 #define ATOM_S5_DOS_REQ_LCD2b0 0x20
5317 #define ATOM_S5_DOS_REQ_DFP6b0 0x40
5318 #define ATOM_S5_DOS_REQ_DFP2b0 0x80
5319 #define ATOM_S5_DOS_REQ_CVb1 0x01
5320 #define ATOM_S5_DOS_REQ_DFP3b1 0x02
5321 #define ATOM_S5_DOS_REQ_DFP4b1 0x04
5322 #define ATOM_S5_DOS_REQ_DFP5b1 0x08
5324 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF
5326 #define ATOM_S5_DOS_REQ_CRT1 0x0001
5327 #define ATOM_S5_DOS_REQ_LCD1 0x0002
5328 #define ATOM_S5_DOS_REQ_TV1 0x0004
5329 #define ATOM_S5_DOS_REQ_DFP1 0x0008
5330 #define ATOM_S5_DOS_REQ_CRT2 0x0010
5331 #define ATOM_S5_DOS_REQ_LCD2 0x0020
5332 #define ATOM_S5_DOS_REQ_DFP6 0x0040
5333 #define ATOM_S5_DOS_REQ_DFP2 0x0080
5334 #define ATOM_S5_DOS_REQ_CV 0x0100
5335 #define ATOM_S5_DOS_REQ_DFP3 0x0200
5336 #define ATOM_S5_DOS_REQ_DFP4 0x0400
5337 #define ATOM_S5_DOS_REQ_DFP5 0x0800
5339 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
5340 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
5341 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
5342 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
5343 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
5344 (ATOM_S5_DOS_FORCE_CVb3<<8))
5346 // BIOS_6_SCRATCH Definition
5347 #define ATOM_S6_DEVICE_CHANGE 0x00000001L
5348 #define ATOM_S6_SCALER_CHANGE 0x00000002L
5349 #define ATOM_S6_LID_CHANGE 0x00000004L
5350 #define ATOM_S6_DOCKING_CHANGE 0x00000008L
5351 #define ATOM_S6_ACC_MODE 0x00000010L
5352 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
5353 #define ATOM_S6_LID_STATE 0x00000040L
5354 #define ATOM_S6_DOCK_STATE 0x00000080L
5355 #define ATOM_S6_CRITICAL_STATE 0x00000100L
5356 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
5357 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
5358 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
5359 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
5360 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
5362 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
5363 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
5365 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L
5366 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L
5367 #define ATOM_S6_ACC_REQ_TV1 0x00040000L
5368 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L
5369 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L
5370 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L
5371 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L
5372 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L
5373 #define ATOM_S6_ACC_REQ_CV 0x01000000L
5374 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L
5375 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L
5376 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L
5378 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L
5379 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
5380 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
5381 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
5382 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
5384 //Byte aligned definition for BIOS usage
5385 #define ATOM_S6_DEVICE_CHANGEb0 0x01
5386 #define ATOM_S6_SCALER_CHANGEb0 0x02
5387 #define ATOM_S6_LID_CHANGEb0 0x04
5388 #define ATOM_S6_DOCKING_CHANGEb0 0x08
5389 #define ATOM_S6_ACC_MODEb0 0x10
5390 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
5391 #define ATOM_S6_LID_STATEb0 0x40
5392 #define ATOM_S6_DOCK_STATEb0 0x80
5393 #define ATOM_S6_CRITICAL_STATEb1 0x01
5394 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
5395 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
5396 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
5397 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
5398 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
5400 #define ATOM_S6_ACC_REQ_CRT1b2 0x01
5401 #define ATOM_S6_ACC_REQ_LCD1b2 0x02
5402 #define ATOM_S6_ACC_REQ_TV1b2 0x04
5403 #define ATOM_S6_ACC_REQ_DFP1b2 0x08
5404 #define ATOM_S6_ACC_REQ_CRT2b2 0x10
5405 #define ATOM_S6_ACC_REQ_LCD2b2 0x20
5406 #define ATOM_S6_ACC_REQ_DFP6b2 0x40
5407 #define ATOM_S6_ACC_REQ_DFP2b2 0x80
5408 #define ATOM_S6_ACC_REQ_CVb3 0x01
5409 #define ATOM_S6_ACC_REQ_DFP3b3 0x02
5410 #define ATOM_S6_ACC_REQ_DFP4b3 0x04
5411 #define ATOM_S6_ACC_REQ_DFP5b3 0x08
5413 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
5414 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
5415 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
5416 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
5417 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
5419 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0
5420 #define ATOM_S6_SCALER_CHANGE_SHIFT 1
5421 #define ATOM_S6_LID_CHANGE_SHIFT 2
5422 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3
5423 #define ATOM_S6_ACC_MODE_SHIFT 4
5424 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
5425 #define ATOM_S6_LID_STATE_SHIFT 6
5426 #define ATOM_S6_DOCK_STATE_SHIFT 7
5427 #define ATOM_S6_CRITICAL_STATE_SHIFT 8
5428 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
5429 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
5430 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
5431 #define ATOM_S6_REQ_SCALER_SHIFT 12
5432 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
5433 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
5434 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
5435 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
5436 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
5437 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
5438 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
5440 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
5441 #define ATOM_S7_DOS_MODE_TYPEb0 0x03
5442 #define ATOM_S7_DOS_MODE_VGAb0 0x00
5443 #define ATOM_S7_DOS_MODE_VESAb0 0x01
5444 #define ATOM_S7_DOS_MODE_EXTb0 0x02
5445 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
5446 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
5447 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
5448 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
5450 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
5452 // BIOS_8_SCRATCH Definition
5453 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
5454 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
5456 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
5457 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
5459 // BIOS_9_SCRATCH Definition
5460 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
5461 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
5463 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
5464 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
5466 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
5467 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
5469 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
5470 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
5474 #define ATOM_FLAG_SET 0x20
5475 #define ATOM_FLAG_CLEAR 0
5476 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
5477 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
5478 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
5479 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
5480 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
5482 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
5483 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
5485 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
5486 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
5487 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
5489 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
5490 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
5491 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
5493 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
5494 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
5496 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
5497 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
5499 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
5500 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
5502 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
5504 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
5506 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
5507 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
5508 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
5509 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
5511 /****************************************************************************/
5512 //Portion II: Definitinos only used in Driver
5513 /****************************************************************************/
5515 // Macros used by driver
5517 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
5519 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
5520 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
5521 #else // not __cplusplus
5522 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
5524 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
5525 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
5526 #endif // __cplusplus
5528 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
5529 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
5531 /****************************************************************************/
5532 //Portion III: Definitinos only used in VBIOS
5533 /****************************************************************************/
5534 #define ATOM_DAC_SRC 0x80
5535 #define ATOM_SRC_DAC1 0
5536 #define ATOM_SRC_DAC2 0x80
5538 typedef struct _MEMORY_PLLINIT_PARAMETERS
5540 ULONG ulTargetMemoryClock; //In 10Khz unit
5541 UCHAR ucAction; //not define yet
5542 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
5543 UCHAR ucFbDiv; //FB value
5544 UCHAR ucPostDiv; //Post div
5545 }MEMORY_PLLINIT_PARAMETERS;
5547 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
5550 #define GPIO_PIN_WRITE 0x01
5551 #define GPIO_PIN_READ 0x00
5553 typedef struct _GPIO_PIN_CONTROL_PARAMETERS
5555 UCHAR ucGPIO_ID; //return value, read from GPIO pins
5556 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
5557 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
5558 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
5559 }GPIO_PIN_CONTROL_PARAMETERS;
5561 typedef struct _ENABLE_SCALER_PARAMETERS
5563 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
5564 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
5565 UCHAR ucTVStandard; //
5567 }ENABLE_SCALER_PARAMETERS;
5568 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
5571 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
5572 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
5573 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2
5574 #define SCALER_ENABLE_MULTITAP_MODE 3
5576 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
5578 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
5579 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
5580 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
5581 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
5582 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5583 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
5585 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
5587 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
5588 ENABLE_CRTC_PARAMETERS sReserved;
5589 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
5591 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
5593 USHORT usHight; // Image Hight
5594 USHORT usWidth; // Image Width
5595 UCHAR ucSurface; // Surface 1 or 2
5597 }ENABLE_GRAPH_SURFACE_PARAMETERS;
5599 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
5601 USHORT usHight; // Image Hight
5602 USHORT usWidth; // Image Width
5603 UCHAR ucSurface; // Surface 1 or 2
5604 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5606 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
5608 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
5610 USHORT usHight; // Image Hight
5611 USHORT usWidth; // Image Width
5612 UCHAR ucSurface; // Surface 1 or 2
5613 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5614 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
5615 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
5617 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
5619 USHORT usHight; // Image Hight
5620 USHORT usWidth; // Image Width
5621 USHORT usGraphPitch;
5623 UCHAR ucPixelFormat;
5624 UCHAR ucSurface; // Surface 1 or 2
5625 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5628 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
5631 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f
5632 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10
5634 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
5636 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
5637 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
5638 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
5640 typedef struct _MEMORY_CLEAN_UP_PARAMETERS
5642 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address
5643 USHORT usMemorySize; //8Kb blocks aligned
5644 }MEMORY_CLEAN_UP_PARAMETERS;
5645 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
5647 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
5649 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
5651 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
5653 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
5656 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
5660 USHORT usDispXStart;
5661 USHORT usDispYStart;
5662 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
5665 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
5669 USHORT usLutStartIndex;
5671 USHORT usLutOffsetInVram;
5672 }PALETTE_DATA_CONTROL_PARAMETERS_V3;
5675 #define PALETTE_DATA_AUTO_FILL 1
5676 #define PALETTE_DATA_READ 2
5677 #define PALETTE_DATA_WRITE 3
5680 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
5682 UCHAR ucInterruptId;
5686 }INTERRUPT_SERVICE_PARAMETER_V2;
5689 #define HDP1_INTERRUPT_ID 1
5690 #define HDP2_INTERRUPT_ID 2
5691 #define HDP3_INTERRUPT_ID 3
5692 #define HDP4_INTERRUPT_ID 4
5693 #define HDP5_INTERRUPT_ID 5
5694 #define HDP6_INTERRUPT_ID 6
5695 #define SW_INTERRUPT_ID 11
5698 #define INTERRUPT_SERVICE_GEN_SW_INT 1
5699 #define INTERRUPT_SERVICE_GET_STATUS 2
5702 #define INTERRUPT_STATUS__INT_TRIGGER 1
5703 #define INTERRUPT_STATUS__HPD_HIGH 2
5705 typedef struct _INDIRECT_IO_ACCESS
5707 ATOM_COMMON_TABLE_HEADER sHeader;
5708 UCHAR IOAccessSequence[256];
5709 } INDIRECT_IO_ACCESS;
5711 #define INDIRECT_READ 0x00
5712 #define INDIRECT_WRITE 0x80
5714 #define INDIRECT_IO_MM 0
5715 #define INDIRECT_IO_PLL 1
5716 #define INDIRECT_IO_MC 2
5717 #define INDIRECT_IO_PCIE 3
5718 #define INDIRECT_IO_PCIEP 4
5719 #define INDIRECT_IO_NBMISC 5
5721 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ
5722 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE
5723 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ
5724 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE
5725 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ
5726 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE
5727 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ
5728 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE
5729 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ
5730 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE
5732 typedef struct _ATOM_OEM_INFO
5734 ATOM_COMMON_TABLE_HEADER sHeader;
5735 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
5738 typedef struct _ATOM_TV_MODE
5740 UCHAR ucVMode_Num; //Video mode number
5741 UCHAR ucTV_Mode_Num; //Internal TV mode number
5744 typedef struct _ATOM_BIOS_INT_TVSTD_MODE
5746 ATOM_COMMON_TABLE_HEADER sHeader;
5747 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
5748 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
5749 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
5750 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
5751 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
5752 }ATOM_BIOS_INT_TVSTD_MODE;
5755 typedef struct _ATOM_TV_MODE_SCALER_PTR
5757 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
5758 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
5759 UCHAR ucTV_Mode_Num;
5760 }ATOM_TV_MODE_SCALER_PTR;
5762 typedef struct _ATOM_STANDARD_VESA_TIMING
5764 ATOM_COMMON_TABLE_HEADER sHeader;
5765 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation
5766 }ATOM_STANDARD_VESA_TIMING;
5769 typedef struct _ATOM_STD_FORMAT
5773 USHORT usSTD_RefreshRate;
5777 typedef struct _ATOM_VESA_TO_EXTENDED_MODE
5779 USHORT usVESA_ModeNumber;
5780 USHORT usExtendedModeNumber;
5781 }ATOM_VESA_TO_EXTENDED_MODE;
5783 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
5785 ATOM_COMMON_TABLE_HEADER sHeader;
5786 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
5787 }ATOM_VESA_TO_INTENAL_MODE_LUT;
5789 /*************** ATOM Memory Related Data Structure ***********************/
5790 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
5792 UCHAR ucMemoryVendor;
5795 ULONG ulDllResetClkRange;
5796 }ATOM_MEMORY_VENDOR_BLOCK;
5799 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
5802 ULONG ulMemClockRange:24;
5804 ULONG ulMemClockRange:24;
5807 }ATOM_MEMORY_SETTING_ID_CONFIG;
5809 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
5811 ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
5813 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
5816 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
5817 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
5818 ULONG aulMemData[1];
5819 }ATOM_MEMORY_SETTING_DATA_BLOCK;
5822 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
5823 USHORT usRegIndex; // MC register index
5824 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
5825 }ATOM_INIT_REG_INDEX_FORMAT;
5828 typedef struct _ATOM_INIT_REG_BLOCK{
5829 USHORT usRegIndexTblSize; //size of asRegIndexBuf
5830 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
5831 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
5832 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
5833 }ATOM_INIT_REG_BLOCK;
5835 #define END_OF_REG_INDEX_BLOCK 0x0ffff
5836 #define END_OF_REG_DATA_BLOCK 0x00000000
5837 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS
5838 #define CLOCK_RANGE_HIGHEST 0x00ffffff
5840 #define VALUE_DWORD SIZEOF ULONG
5841 #define VALUE_SAME_AS_ABOVE 0
5842 #define VALUE_MASK_DWORD 0x84
5844 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
5845 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
5846 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
5847 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code
5848 #define ACCESS_PLACEHOLDER 0x80
5850 typedef struct _ATOM_MC_INIT_PARAM_TABLE
5852 ATOM_COMMON_TABLE_HEADER sHeader;
5853 USHORT usAdjustARB_SEQDataOffset;
5854 USHORT usMCInitMemTypeTblOffset;
5855 USHORT usMCInitCommonTblOffset;
5856 USHORT usMCInitPowerDownTblOffset;
5857 ULONG ulARB_SEQDataBuf[32];
5858 ATOM_INIT_REG_BLOCK asMCInitMemType;
5859 ATOM_INIT_REG_BLOCK asMCInitCommon;
5860 }ATOM_MC_INIT_PARAM_TABLE;
5867 #define _16Mx16 0x22
5868 #define _16Mx32 0x23
5869 #define _32Mx16 0x32
5870 #define _32Mx32 0x33
5872 #define _64Mx16 0x42
5873 #define _64Mx32 0x43
5874 #define _128Mx8 0x51
5875 #define _128Mx16 0x52
5876 #define _256Mx8 0x61
5877 #define _256Mx16 0x62
5880 #define INFINEON 0x2
5890 #define QIMONDA INFINEON
5891 #define PROMOS MOSEL
5892 #define KRETON INFINEON
5893 #define ELIXIR NANYA
5895 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
5897 #define UCODE_ROM_START_ADDRESS 0x1b800
5898 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
5900 //uCode block header for reference
5902 typedef struct _MCuCodeHeader
5909 USHORT usParametersLength;
5910 USHORT usUCodeLength;
5915 //////////////////////////////////////////////////////////////////////////////////
5917 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
5919 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
5920 typedef struct _ATOM_VRAM_MODULE_V1
5926 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5927 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
5928 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
5929 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5930 UCHAR ucRow; // Number of Row,in power of 2;
5931 UCHAR ucColumn; // Number of Column,in power of 2;
5932 UCHAR ucBank; // Nunber of Bank;
5933 UCHAR ucRank; // Number of Rank, in power of 2
5934 UCHAR ucChannelNum; // Number of channel;
5935 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5936 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5937 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5938 UCHAR ucReserved[2];
5939 }ATOM_VRAM_MODULE_V1;
5942 typedef struct _ATOM_VRAM_MODULE_V2
5945 ULONG ulFlags; // To enable/disable functionalities based on memory type
5946 ULONG ulEngineClock; // Override of default engine clock for particular memory type
5947 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
5948 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
5949 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
5953 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5954 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
5955 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
5956 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5957 UCHAR ucRow; // Number of Row,in power of 2;
5958 UCHAR ucColumn; // Number of Column,in power of 2;
5959 UCHAR ucBank; // Nunber of Bank;
5960 UCHAR ucRank; // Number of Rank, in power of 2
5961 UCHAR ucChannelNum; // Number of channel;
5962 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5963 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5964 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5965 UCHAR ucRefreshRateFactor;
5966 UCHAR ucReserved[3];
5967 }ATOM_VRAM_MODULE_V2;
5970 typedef struct _ATOM_MEMORY_TIMING_FORMAT
5972 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
5974 USHORT usMRS; // mode register
5978 USHORT usEMRS; // extended mode register
5981 UCHAR ucCL; // CAS latency
5982 UCHAR ucWL; // WRITE Latency
5983 UCHAR uctRAS; // tRAS
5985 UCHAR uctRFC; // tRFC
5986 UCHAR uctRCDR; // tRCDR
5987 UCHAR uctRCDW; // tRCDW
5989 UCHAR uctRRD; // tRRD
5991 UCHAR uctWTR; // tWTR
5992 UCHAR uctPDIX; // tPDIX
5993 UCHAR uctFAW; // tFAW
5994 UCHAR uctAOND; // tAOND
5998 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6003 }ATOM_MEMORY_TIMING_FORMAT;
6006 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
6008 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6009 USHORT usMRS; // mode register
6010 USHORT usEMRS; // extended mode register
6011 UCHAR ucCL; // CAS latency
6012 UCHAR ucWL; // WRITE Latency
6013 UCHAR uctRAS; // tRAS
6015 UCHAR uctRFC; // tRFC
6016 UCHAR uctRCDR; // tRCDR
6017 UCHAR uctRCDW; // tRCDW
6019 UCHAR uctRRD; // tRRD
6021 UCHAR uctWTR; // tWTR
6022 UCHAR uctPDIX; // tPDIX
6023 UCHAR uctFAW; // tFAW
6024 UCHAR uctAOND; // tAOND
6025 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6026 ////////////////////////////////////GDDR parameters///////////////////////////////////
6037 }ATOM_MEMORY_TIMING_FORMAT_V1;
6039 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
6041 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6042 USHORT usMRS; // mode register
6043 USHORT usEMRS; // extended mode register
6044 UCHAR ucCL; // CAS latency
6045 UCHAR ucWL; // WRITE Latency
6046 UCHAR uctRAS; // tRAS
6048 UCHAR uctRFC; // tRFC
6049 UCHAR uctRCDR; // tRCDR
6050 UCHAR uctRCDW; // tRCDW
6052 UCHAR uctRRD; // tRRD
6054 UCHAR uctWTR; // tWTR
6055 UCHAR uctPDIX; // tPDIX
6056 UCHAR uctFAW; // tFAW
6057 UCHAR uctAOND; // tAOND
6058 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6059 ////////////////////////////////////GDDR parameters///////////////////////////////////
6073 }ATOM_MEMORY_TIMING_FORMAT_V2;
6075 typedef struct _ATOM_MEMORY_FORMAT
6077 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
6079 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6080 USHORT usDDR3_Reserved; // Not used for DDR3 memory
6083 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6084 USHORT usDDR3_MR3; // Used for DDR3 memory
6086 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
6087 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
6088 UCHAR ucRow; // Number of Row,in power of 2;
6089 UCHAR ucColumn; // Number of Column,in power of 2;
6090 UCHAR ucBank; // Nunber of Bank;
6091 UCHAR ucRank; // Number of Rank, in power of 2
6092 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
6093 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
6094 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
6095 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6096 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
6097 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
6098 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock
6099 }ATOM_MEMORY_FORMAT;
6102 typedef struct _ATOM_VRAM_MODULE_V3
6104 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
6105 USHORT usSize; // size of ATOM_VRAM_MODULE_V3
6106 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
6107 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
6108 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6109 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
6110 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
6111 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6112 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6113 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6114 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
6115 }ATOM_VRAM_MODULE_V3;
6118 //ATOM_VRAM_MODULE_V3.ucNPL_RT
6119 #define NPL_RT_MASK 0x0f
6120 #define BATTERY_ODT_MASK 0xc0
6122 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
6124 typedef struct _ATOM_VRAM_MODULE_V4
6126 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6127 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6128 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6129 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6131 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6132 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6133 UCHAR ucChannelNum; // Number of channels present in this module config
6134 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6135 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6136 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6137 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6138 UCHAR ucVREFI; // board dependent parameter
6139 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6140 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6141 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6142 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6143 UCHAR ucReserved[3];
6145 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6147 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6148 USHORT usDDR3_Reserved;
6151 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6152 USHORT usDDR3_MR3; // Used for DDR3 memory
6154 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6155 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6156 UCHAR ucReserved2[2];
6157 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6158 }ATOM_VRAM_MODULE_V4;
6160 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
6161 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
6162 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4
6163 #define VRAM_MODULE_V4_MISC_BL8 0x4
6164 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
6166 typedef struct _ATOM_VRAM_MODULE_V5
6168 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6169 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6170 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6171 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6173 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6174 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6175 UCHAR ucChannelNum; // Number of channels present in this module config
6176 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6177 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6178 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6179 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6180 UCHAR ucVREFI; // board dependent parameter
6181 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6182 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6183 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6184 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6185 UCHAR ucReserved[3];
6187 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6188 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6189 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6190 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6191 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6192 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6193 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6194 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6195 }ATOM_VRAM_MODULE_V5;
6197 typedef struct _ATOM_VRAM_MODULE_V6
6199 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6200 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6201 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6202 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6204 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6205 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6206 UCHAR ucChannelNum; // Number of channels present in this module config
6207 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6208 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6209 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6210 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6211 UCHAR ucVREFI; // board dependent parameter
6212 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6213 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6214 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6215 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6216 UCHAR ucReserved[3];
6218 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6219 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6220 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6221 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6222 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6223 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6224 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6225 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6226 }ATOM_VRAM_MODULE_V6;
6228 typedef struct _ATOM_VRAM_MODULE_V7
6230 // Design Specific Values
6231 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
6232 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
6233 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6234 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
6235 UCHAR ucExtMemoryID; // Current memory module ID
6236 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
6237 UCHAR ucChannelNum; // Number of mem. channels supported in this module
6238 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
6239 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6240 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
6241 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
6242 UCHAR ucVREFI; // Not used.
6243 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6244 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6245 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6246 USHORT usSEQSettingOffset;
6248 // Memory Module specific values
6249 USHORT usEMRS2Value; // EMRS2/MR2 Value.
6250 USHORT usEMRS3Value; // EMRS3/MR3 Value.
6251 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
6252 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6253 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
6254 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6255 char strMemPNString[20]; // part number end with '0'.
6256 }ATOM_VRAM_MODULE_V7;
6258 typedef struct _ATOM_VRAM_INFO_V2
6260 ATOM_COMMON_TABLE_HEADER sHeader;
6261 UCHAR ucNumOfVRAMModule;
6262 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6265 typedef struct _ATOM_VRAM_INFO_V3
6267 ATOM_COMMON_TABLE_HEADER sHeader;
6268 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6269 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6271 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
6272 UCHAR ucNumOfVRAMModule;
6273 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6274 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
6275 // ATOM_INIT_REG_BLOCK aMemAdjust;
6278 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
6280 typedef struct _ATOM_VRAM_INFO_V4
6282 ATOM_COMMON_TABLE_HEADER sHeader;
6283 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6284 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6286 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
6287 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
6288 UCHAR ucReservde[4];
6289 UCHAR ucNumOfVRAMModule;
6290 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6291 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
6292 // ATOM_INIT_REG_BLOCK aMemAdjust;
6295 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
6297 ATOM_COMMON_TABLE_HEADER sHeader;
6298 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6299 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6300 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
6301 USHORT usReserved[3];
6302 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
6303 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
6304 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
6306 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6307 }ATOM_VRAM_INFO_HEADER_V2_1;
6310 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
6312 ATOM_COMMON_TABLE_HEADER sHeader;
6313 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
6314 }ATOM_VRAM_GPIO_DETECTION_INFO;
6317 typedef struct _ATOM_MEMORY_TRAINING_INFO
6319 ATOM_COMMON_TABLE_HEADER sHeader;
6320 UCHAR ucTrainingLoop;
6321 UCHAR ucReserved[3];
6322 ATOM_INIT_REG_BLOCK asMemTrainingSetting;
6323 }ATOM_MEMORY_TRAINING_INFO;
6326 typedef struct SW_I2C_CNTL_DATA_PARAMETERS
6332 } SW_I2C_CNTL_DATA_PARAMETERS;
6334 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
6336 typedef struct _SW_I2C_IO_DATA_PARAMETERS
6341 } SW_I2C_IO_DATA_PARAMETERS;
6343 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
6345 /****************************SW I2C CNTL DEFINITIONS**********************/
6346 #define SW_I2C_IO_RESET 0
6347 #define SW_I2C_IO_GET 1
6348 #define SW_I2C_IO_DRIVE 2
6349 #define SW_I2C_IO_SET 3
6350 #define SW_I2C_IO_START 4
6352 #define SW_I2C_IO_CLOCK 0
6353 #define SW_I2C_IO_DATA 0x80
6355 #define SW_I2C_IO_ZERO 0
6356 #define SW_I2C_IO_ONE 0x100
6358 #define SW_I2C_CNTL_READ 0
6359 #define SW_I2C_CNTL_WRITE 1
6360 #define SW_I2C_CNTL_START 2
6361 #define SW_I2C_CNTL_STOP 3
6362 #define SW_I2C_CNTL_OPEN 4
6363 #define SW_I2C_CNTL_CLOSE 5
6364 #define SW_I2C_CNTL_WRITE1BIT 6
6366 //==============================VESA definition Portion===============================
6367 #define VESA_OEM_PRODUCT_REV "01.00"
6368 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
6369 #define VESA_MODE_WIN_ATTRIBUTE 7
6370 #define VESA_WIN_SIZE 64
6372 typedef struct _PTR_32_BIT_STRUCTURE
6376 } PTR_32_BIT_STRUCTURE;
6378 typedef union _PTR_32_BIT_UNION
6380 PTR_32_BIT_STRUCTURE SegmentOffset;
6384 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
6386 UCHAR VbeSignature[4];
6388 PTR_32_BIT_UNION OemStringPtr;
6389 UCHAR Capabilities[4];
6390 PTR_32_BIT_UNION VideoModePtr;
6392 } VBE_1_2_INFO_BLOCK_UPDATABLE;
6395 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
6397 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
6399 PTR_32_BIT_UNION OemVendorNamePtr;
6400 PTR_32_BIT_UNION OemProductNamePtr;
6401 PTR_32_BIT_UNION OemProductRevPtr;
6402 } VBE_2_0_INFO_BLOCK_UPDATABLE;
6404 typedef union _VBE_VERSION_UNION
6406 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
6407 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
6408 } VBE_VERSION_UNION;
6410 typedef struct _VBE_INFO_BLOCK
6412 VBE_VERSION_UNION UpdatableVBE_Info;
6413 UCHAR Reserved[222];
6417 typedef struct _VBE_FP_INFO
6426 ULONG RsvdOffScrnMemSize;
6427 ULONG RsvdOffScrnMEmPtr;
6431 typedef struct _VESA_MODE_INFO_BLOCK
6433 // Mandatory information for all VBE revisions
6434 USHORT ModeAttributes; // dw ? ; mode attributes
6435 UCHAR WinAAttributes; // db ? ; window A attributes
6436 UCHAR WinBAttributes; // db ? ; window B attributes
6437 USHORT WinGranularity; // dw ? ; window granularity
6438 USHORT WinSize; // dw ? ; window size
6439 USHORT WinASegment; // dw ? ; window A start segment
6440 USHORT WinBSegment; // dw ? ; window B start segment
6441 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
6442 USHORT BytesPerScanLine;// dw ? ; bytes per scan line
6444 //; Mandatory information for VBE 1.2 and above
6445 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
6446 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
6447 UCHAR XCharSize; // db ? ; character cell width in pixels
6448 UCHAR YCharSize; // db ? ; character cell height in pixels
6449 UCHAR NumberOfPlanes; // db ? ; number of memory planes
6450 UCHAR BitsPerPixel; // db ? ; bits per pixel
6451 UCHAR NumberOfBanks; // db ? ; number of banks
6452 UCHAR MemoryModel; // db ? ; memory model type
6453 UCHAR BankSize; // db ? ; bank size in KB
6454 UCHAR NumberOfImagePages;// db ? ; number of images
6455 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
6457 //; Direct Color fields(required for direct/6 and YUV/7 memory models)
6458 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
6459 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
6460 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
6461 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
6462 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
6463 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
6464 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
6465 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
6466 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
6468 //; Mandatory information for VBE 2.0 and above
6469 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
6470 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6471 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
6473 //; Mandatory information for VBE 3.0 and above
6474 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
6475 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
6476 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
6477 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
6478 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
6479 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
6480 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
6481 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
6482 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
6483 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
6484 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
6485 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
6486 UCHAR Reserved; // db 190 dup (0)
6487 } VESA_MODE_INFO_BLOCK;
6489 // BIOS function CALLS
6490 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
6491 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00
6492 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
6493 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
6494 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
6495 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
6496 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
6497 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
6498 #define ATOM_BIOS_FUNCTION_STV_STD 0x16
6499 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
6500 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
6502 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
6503 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
6504 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
6505 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
6506 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
6507 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
6508 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
6510 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
6511 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
6512 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
6513 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
6514 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
6515 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
6516 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
6517 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
6518 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
6519 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
6522 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
6523 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
6524 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
6525 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
6526 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
6527 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
6528 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
6529 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
6531 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
6532 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
6533 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
6535 // structure used for VBIOS only
6538 typedef struct _ASIC_TRANSMITTER_INFO
6540 USHORT usTransmitterObjId;
6541 USHORT usSupportDevice;
6542 UCHAR ucTransmitterCmdTblId;
6544 UCHAR ucEncoderID; //available 1st encoder ( default )
6545 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
6546 UCHAR uc2ndEncoderID;
6548 }ASIC_TRANSMITTER_INFO;
6550 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01
6551 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02
6552 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4
6553 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00
6554 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04
6555 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40
6556 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44
6557 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80
6558 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84
6560 typedef struct _ASIC_ENCODER_INFO
6563 UCHAR ucEncoderConfig;
6564 USHORT usEncoderCmdTblId;
6567 typedef struct _ATOM_DISP_OUT_INFO
6569 ATOM_COMMON_TABLE_HEADER sHeader;
6570 USHORT ptrTransmitterInfo;
6571 USHORT ptrEncoderInfo;
6572 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
6573 ASIC_ENCODER_INFO asEncoderInfo[1];
6574 }ATOM_DISP_OUT_INFO;
6576 typedef struct _ATOM_DISP_OUT_INFO_V2
6578 ATOM_COMMON_TABLE_HEADER sHeader;
6579 USHORT ptrTransmitterInfo;
6580 USHORT ptrEncoderInfo;
6581 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
6582 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
6583 ASIC_ENCODER_INFO asEncoderInfo[1];
6584 }ATOM_DISP_OUT_INFO_V2;
6587 typedef struct _ATOM_DISP_CLOCK_ID {
6589 UCHAR ucPpllAttribute;
6590 }ATOM_DISP_CLOCK_ID;
6593 #define CLOCK_SOURCE_SHAREABLE 0x01
6594 #define CLOCK_SOURCE_DP_MODE 0x02
6595 #define CLOCK_SOURCE_NONE_DP_MODE 0x04
6598 typedef struct _ASIC_TRANSMITTER_INFO_V2
6600 USHORT usTransmitterObjId;
6601 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object
6602 UCHAR ucTransmitterCmdTblId;
6604 UCHAR ucEncoderID; // available 1st encoder ( default )
6605 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
6606 UCHAR uc2ndEncoderID;
6608 }ASIC_TRANSMITTER_INFO_V2;
6610 typedef struct _ATOM_DISP_OUT_INFO_V3
6612 ATOM_COMMON_TABLE_HEADER sHeader;
6613 USHORT ptrTransmitterInfo;
6614 USHORT ptrEncoderInfo;
6615 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
6617 UCHAR ucDCERevision;
6618 UCHAR ucMaxDispEngineNum;
6619 UCHAR ucMaxActiveDispEngineNum;
6621 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
6622 UCHAR ucReserved[3];
6623 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
6624 }ATOM_DISP_OUT_INFO_V3;
6626 typedef enum CORE_REF_CLK_SOURCE{
6630 }CORE_REF_CLK_SOURCE;
6632 // DispDevicePriorityInfo
6633 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
6635 ATOM_COMMON_TABLE_HEADER sHeader;
6636 USHORT asDevicePriority[16];
6637 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
6639 //ProcessAuxChannelTransactionTable
6640 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
6642 USHORT lpAuxRequest;
6647 UCHAR ucReplyStatus;
6652 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
6654 //ProcessAuxChannelTransactionTable
6655 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
6657 USHORT lpAuxRequest;
6662 UCHAR ucReplyStatus;
6666 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
6667 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
6669 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
6673 typedef struct _DP_ENCODER_SERVICE_PARAMETERS
6678 UCHAR ucConfig; // for DP training command
6679 UCHAR ucI2cId; // use for GET_SINK_TYPE command
6684 UCHAR ucReserved[2];
6685 }DP_ENCODER_SERVICE_PARAMETERS;
6688 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
6690 #define ATOM_DP_ACTION_TRAINING_START 0x02
6691 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
6692 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
6693 #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05
6694 #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06
6695 #define ATOM_DP_ACTION_BLANKING 0x07
6698 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03
6699 #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00
6700 #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01
6701 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02
6702 #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
6703 #define ATOM_DP_CONFIG_LINK_A 0x00
6704 #define ATOM_DP_CONFIG_LINK_B 0x04
6706 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
6709 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
6711 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6714 UCHAR ucSinkType; // Iput and Output parameters.
6715 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6716 UCHAR ucReserved[2];
6717 }DP_ENCODER_SERVICE_PARAMETERS_V2;
6719 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
6721 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
6722 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
6723 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
6726 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01
6727 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02
6730 // DP_TRAINING_TABLE
6731 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
6732 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
6733 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
6734 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
6735 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
6736 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
6737 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
6738 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
6739 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
6740 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
6741 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
6742 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
6743 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)
6745 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
6753 USHORT lpI2CDataOut;
6758 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
6760 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
6763 #define HW_I2C_WRITE 1
6764 #define HW_I2C_READ 0
6765 #define I2C_2BYTE_ADDR 0x02
6767 /****************************************************************************/
6768 // Structures used by HW_Misc_OperationTable
6769 /****************************************************************************/
6770 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
6772 UCHAR ucCmd; // Input: To tell which action to take
6773 UCHAR ucReserved[3];
6775 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
6777 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
6779 UCHAR ucReturnCode; // Output: Return value base on action was taken
6780 UCHAR ucReserved[3];
6782 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
6785 #define ATOM_GET_SDI_SUPPORT 0xF0
6788 #define ATOM_UNKNOWN_CMD 0
6789 #define ATOM_FEATURE_NOT_SUPPORTED 1
6790 #define ATOM_FEATURE_SUPPORTED 2
6792 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
6794 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output;
6795 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved;
6796 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
6798 /****************************************************************************/
6800 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
6802 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
6803 UCHAR ucReserved[3];
6804 }SET_HWBLOCK_INSTANCE_PARAMETER_V2;
6806 #define HWBLKINST_INSTANCE_MASK 0x07
6807 #define HWBLKINST_HWBLK_MASK 0xF0
6808 #define HWBLKINST_HWBLK_SHIFT 0x04
6811 #define SELECT_DISP_ENGINE 0
6812 #define SELECT_DISP_PLL 1
6813 #define SELECT_DCIO_UNIPHY_LINK0 2
6814 #define SELECT_DCIO_UNIPHY_LINK1 3
6815 #define SELECT_DCIO_IMPCAL 4
6816 #define SELECT_DCIO_DIG 6
6817 #define SELECT_CRTC_PIXEL_RATE 7
6818 #define SELECT_VGA_BLK 8
6820 // DIGTransmitterInfoTable structure used to program UNIPHY settings
6821 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
6822 ATOM_COMMON_TABLE_HEADER sHeader;
6823 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
6824 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
6825 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
6826 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
6827 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
6828 }DIG_TRANSMITTER_INFO_HEADER_V3_1;
6830 typedef struct _CLOCK_CONDITION_REGESTER_INFO{
6831 USHORT usRegisterIndex;
6834 }CLOCK_CONDITION_REGESTER_INFO;
6836 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
6837 USHORT usMaxClockFreq;
6840 ULONG ulAnalogSetting[1];
6841 }CLOCK_CONDITION_SETTING_ENTRY;
6843 typedef struct _CLOCK_CONDITION_SETTING_INFO{
6845 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
6846 }CLOCK_CONDITION_SETTING_INFO;
6848 typedef struct _PHY_CONDITION_REG_VAL{
6851 }PHY_CONDITION_REG_VAL;
6853 typedef struct _PHY_CONDITION_REG_INFO{
6856 PHY_CONDITION_REG_VAL asRegVal[1];
6857 }PHY_CONDITION_REG_INFO;
6859 typedef struct _PHY_ANALOG_SETTING_INFO{
6863 PHY_CONDITION_REG_INFO asAnalogSetting[1];
6864 }PHY_ANALOG_SETTING_INFO;
6866 /****************************************************************************/
6867 //Portion VI: Definitinos for vbios MC scratch registers that driver used
6868 /****************************************************************************/
6870 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000
6871 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000
6872 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000
6873 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000
6874 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000
6875 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000
6876 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000
6878 /****************************************************************************/
6879 //Portion VI: Definitinos being oboselete
6880 /****************************************************************************/
6882 //==========================================================================================
6883 //Remove the definitions below when driver is ready!
6884 typedef struct _ATOM_DAC_INFO
6886 ATOM_COMMON_TABLE_HEADER sHeader;
6887 USHORT usMaxFrequency; // in 10kHz unit
6892 typedef struct _COMPASSIONATE_DATA
6894 ATOM_COMMON_TABLE_HEADER sHeader;
6896 //============================== DAC1 portion
6897 UCHAR ucDAC1_BG_Adjustment;
6898 UCHAR ucDAC1_DAC_Adjustment;
6899 USHORT usDAC1_FORCE_Data;
6900 //============================== DAC2 portion
6901 UCHAR ucDAC2_CRT2_BG_Adjustment;
6902 UCHAR ucDAC2_CRT2_DAC_Adjustment;
6903 USHORT usDAC2_CRT2_FORCE_Data;
6904 USHORT usDAC2_CRT2_MUX_RegisterIndex;
6905 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6906 UCHAR ucDAC2_NTSC_BG_Adjustment;
6907 UCHAR ucDAC2_NTSC_DAC_Adjustment;
6908 USHORT usDAC2_TV1_FORCE_Data;
6909 USHORT usDAC2_TV1_MUX_RegisterIndex;
6910 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6911 UCHAR ucDAC2_CV_BG_Adjustment;
6912 UCHAR ucDAC2_CV_DAC_Adjustment;
6913 USHORT usDAC2_CV_FORCE_Data;
6914 USHORT usDAC2_CV_MUX_RegisterIndex;
6915 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6916 UCHAR ucDAC2_PAL_BG_Adjustment;
6917 UCHAR ucDAC2_PAL_DAC_Adjustment;
6918 USHORT usDAC2_TV2_FORCE_Data;
6919 }COMPASSIONATE_DATA;
6921 /****************************Supported Device Info Table Definitions**********************/
6923 // [7:4] - connector type
6924 // = 1 - VGA connector
6931 // = 8 - DIGITAL LINK
6933 // = 0xA - HDMI_type A
6934 // = 0xB - HDMI_type B
6935 // = 0xE - Special case1 (DVI+DIN)
6937 // [3:0] - DAC Associated
6941 // = 3 - External DAC
6945 typedef struct _ATOM_CONNECTOR_INFO
6948 UCHAR bfConnectorType:4;
6949 UCHAR bfAssociatedDAC:4;
6951 UCHAR bfAssociatedDAC:4;
6952 UCHAR bfConnectorType:4;
6954 }ATOM_CONNECTOR_INFO;
6956 typedef union _ATOM_CONNECTOR_INFO_ACCESS
6958 ATOM_CONNECTOR_INFO sbfAccess;
6960 }ATOM_CONNECTOR_INFO_ACCESS;
6962 typedef struct _ATOM_CONNECTOR_INFO_I2C
6964 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
6965 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
6966 }ATOM_CONNECTOR_INFO_I2C;
6969 typedef struct _ATOM_SUPPORTED_DEVICES_INFO
6971 ATOM_COMMON_TABLE_HEADER sHeader;
6972 USHORT usDeviceSupport;
6973 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
6974 }ATOM_SUPPORTED_DEVICES_INFO;
6976 #define NO_INT_SRC_MAPPED 0xFF
6978 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
6980 UCHAR ucIntSrcBitmap;
6981 }ATOM_CONNECTOR_INC_SRC_BITMAP;
6983 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
6985 ATOM_COMMON_TABLE_HEADER sHeader;
6986 USHORT usDeviceSupport;
6987 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
6988 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
6989 }ATOM_SUPPORTED_DEVICES_INFO_2;
6991 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
6993 ATOM_COMMON_TABLE_HEADER sHeader;
6994 USHORT usDeviceSupport;
6995 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
6996 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
6997 }ATOM_SUPPORTED_DEVICES_INFO_2d1;
6999 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
7003 typedef struct _ATOM_MISC_CONTROL_INFO
7006 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7007 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
7008 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
7009 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
7010 }ATOM_MISC_CONTROL_INFO;
7013 #define ATOM_MAX_MISC_INFO 4
7015 typedef struct _ATOM_TMDS_INFO
7017 ATOM_COMMON_TABLE_HEADER sHeader;
7018 USHORT usMaxFrequency; // in 10Khz
7019 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
7023 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
7025 UCHAR ucTVStandard; //Same as TV standards defined above,
7027 }ATOM_ENCODER_ANALOG_ATTRIBUTE;
7029 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
7031 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
7033 }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
7035 typedef union _ATOM_ENCODER_ATTRIBUTE
7037 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
7038 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
7039 }ATOM_ENCODER_ATTRIBUTE;
7042 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
7044 USHORT usPixelClock;
7046 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
7047 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
7048 ATOM_ENCODER_ATTRIBUTE usDevAttr;
7049 }DVO_ENCODER_CONTROL_PARAMETERS;
7051 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
7053 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
7054 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
7055 }DVO_ENCODER_CONTROL_PS_ALLOCATION;
7058 #define ATOM_XTMDS_ASIC_SI164_ID 1
7059 #define ATOM_XTMDS_ASIC_SI178_ID 2
7060 #define ATOM_XTMDS_ASIC_TFP513_ID 3
7061 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
7062 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
7063 #define ATOM_XTMDS_MVPU_FPGA 0x00000004
7066 typedef struct _ATOM_XTMDS_INFO
7068 ATOM_COMMON_TABLE_HEADER sHeader;
7069 USHORT usSingleLinkMaxFrequency;
7070 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
7071 UCHAR ucXtransimitterID;
7072 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
7073 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
7074 // due to design. This ID is used to alert driver that the sequence is not "standard"!
7075 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
7076 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
7079 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
7081 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
7082 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
7084 }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
7086 /****************************Legacy Power Play Table Definitions **********************/
7088 //Definitions for ulPowerPlayMiscInfo
7089 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
7090 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
7091 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
7093 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
7094 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
7096 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
7098 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
7099 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
7100 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
7102 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
7103 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
7104 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
7105 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
7106 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
7107 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
7108 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
7110 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
7111 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
7112 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
7113 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
7114 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
7116 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
7117 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
7119 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
7120 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
7121 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
7122 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
7123 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
7124 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
7126 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
7127 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
7128 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
7130 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
7131 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
7132 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
7133 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
7134 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
7135 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
7136 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
7137 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
7138 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
7139 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
7140 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
7142 //ucTableFormatRevision=1
7143 //ucTableContentRevision=1
7144 typedef struct _ATOM_POWERMODE_INFO
7146 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7147 ULONG ulReserved1; // must set to 0
7148 ULONG ulReserved2; // must set to 0
7149 USHORT usEngineClock;
7150 USHORT usMemoryClock;
7151 UCHAR ucVoltageDropIndex; // index to GPIO table
7152 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7153 UCHAR ucMinTemperature;
7154 UCHAR ucMaxTemperature;
7155 UCHAR ucNumPciELanes; // number of PCIE lanes
7156 }ATOM_POWERMODE_INFO;
7158 //ucTableFormatRevision=2
7159 //ucTableContentRevision=1
7160 typedef struct _ATOM_POWERMODE_INFO_V2
7162 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7164 ULONG ulEngineClock;
7165 ULONG ulMemoryClock;
7166 UCHAR ucVoltageDropIndex; // index to GPIO table
7167 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7168 UCHAR ucMinTemperature;
7169 UCHAR ucMaxTemperature;
7170 UCHAR ucNumPciELanes; // number of PCIE lanes
7171 }ATOM_POWERMODE_INFO_V2;
7173 //ucTableFormatRevision=2
7174 //ucTableContentRevision=2
7175 typedef struct _ATOM_POWERMODE_INFO_V3
7177 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7179 ULONG ulEngineClock;
7180 ULONG ulMemoryClock;
7181 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
7182 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7183 UCHAR ucMinTemperature;
7184 UCHAR ucMaxTemperature;
7185 UCHAR ucNumPciELanes; // number of PCIE lanes
7186 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
7187 }ATOM_POWERMODE_INFO_V3;
7190 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
7192 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
7193 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
7195 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
7196 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
7197 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
7198 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
7199 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
7200 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
7201 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
7204 typedef struct _ATOM_POWERPLAY_INFO
7206 ATOM_COMMON_TABLE_HEADER sHeader;
7207 UCHAR ucOverdriveThermalController;
7208 UCHAR ucOverdriveI2cLine;
7209 UCHAR ucOverdriveIntBitmap;
7210 UCHAR ucOverdriveControllerAddress;
7211 UCHAR ucSizeOfPowerModeEntry;
7212 UCHAR ucNumOfPowerModeEntries;
7213 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7214 }ATOM_POWERPLAY_INFO;
7216 typedef struct _ATOM_POWERPLAY_INFO_V2
7218 ATOM_COMMON_TABLE_HEADER sHeader;
7219 UCHAR ucOverdriveThermalController;
7220 UCHAR ucOverdriveI2cLine;
7221 UCHAR ucOverdriveIntBitmap;
7222 UCHAR ucOverdriveControllerAddress;
7223 UCHAR ucSizeOfPowerModeEntry;
7224 UCHAR ucNumOfPowerModeEntries;
7225 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7226 }ATOM_POWERPLAY_INFO_V2;
7228 typedef struct _ATOM_POWERPLAY_INFO_V3
7230 ATOM_COMMON_TABLE_HEADER sHeader;
7231 UCHAR ucOverdriveThermalController;
7232 UCHAR ucOverdriveI2cLine;
7233 UCHAR ucOverdriveIntBitmap;
7234 UCHAR ucOverdriveControllerAddress;
7235 UCHAR ucSizeOfPowerModeEntry;
7236 UCHAR ucNumOfPowerModeEntries;
7237 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7238 }ATOM_POWERPLAY_INFO_V3;
7241 /**************************************************************************/
7242 typedef struct _ATOM_PPLIB_THERMALCONTROLLER
7245 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
7246 UCHAR ucI2cLine; // as interpreted by DAL I2C
7248 UCHAR ucFanParameters; // Fan Control Parameters.
7249 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
7250 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
7251 UCHAR ucReserved; // ----
7252 UCHAR ucFlags; // to be defined
7253 } ATOM_PPLIB_THERMALCONTROLLER;
7255 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
7256 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller.
7258 #define ATOM_PP_THERMALCONTROLLER_NONE 0
7259 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib
7260 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib
7261 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib
7262 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib
7263 #define ATOM_PP_THERMALCONTROLLER_LM64 5
7264 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib
7265 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7
7266 #define ATOM_PP_THERMALCONTROLLER_RV770 8
7267 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9
7268 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11
7269 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
7270 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
7271 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally
7272 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15
7274 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
7275 // We probably should reserve the bit 0x80 for this use.
7276 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
7277 // The driver can pick the correct internal controller based on the ASIC.
7279 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller
7280 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller
7282 typedef struct _ATOM_PPLIB_STATE
7284 UCHAR ucNonClockStateIndex;
7285 UCHAR ucClockStateIndices[1]; // variable-sized
7288 typedef struct _ATOM_PPLIB_FANTABLE
7290 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same.
7291 UCHAR ucTHyst; // Temperature hysteresis. Integer.
7292 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
7293 USHORT usTMed; // The middle temperature where we change slopes.
7294 USHORT usTHigh; // The high point above TMed for adjusting the second slope.
7295 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments).
7296 USHORT usPWMMed; // The PWM value (in percent) at TMed.
7297 USHORT usPWMHigh; // The PWM value at THigh.
7298 } ATOM_PPLIB_FANTABLE;
7300 typedef struct _ATOM_PPLIB_EXTENDEDHEADER
7303 ULONG ulMaxEngineClock; // For Overdrive.
7304 ULONG ulMaxMemoryClock; // For Overdrive.
7305 // Add extra system parameters here, always adjust size to include all fields.
7306 } ATOM_PPLIB_EXTENDEDHEADER;
7308 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
7309 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
7310 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
7311 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
7312 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
7313 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
7314 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
7315 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
7316 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
7317 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
7318 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
7319 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
7320 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
7321 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
7322 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition.
7323 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
7324 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC.
7325 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
7326 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
7328 typedef struct _ATOM_PPLIB_POWERPLAYTABLE
7330 ATOM_COMMON_TABLE_HEADER sHeader;
7332 UCHAR ucDataRevision;
7335 UCHAR ucStateEntrySize;
7336 UCHAR ucClockInfoSize;
7337 UCHAR ucNonClockSize;
7339 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
7340 USHORT usStateArrayOffset;
7342 // offset from start of this table to array of ASIC-specific structures,
7343 // currently ATOM_PPLIB_CLOCK_INFO.
7344 USHORT usClockInfoArrayOffset;
7346 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
7347 USHORT usNonClockInfoArrayOffset;
7349 USHORT usBackbiasTime; // in microseconds
7350 USHORT usVoltageTime; // in microseconds
7351 USHORT usTableSize; //the size of this structure, or the extended structure
7353 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
7355 ATOM_PPLIB_THERMALCONTROLLER sThermalController;
7357 USHORT usBootClockInfoOffset;
7358 USHORT usBootNonClockInfoOffset;
7360 } ATOM_PPLIB_POWERPLAYTABLE;
7362 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2
7364 ATOM_PPLIB_POWERPLAYTABLE basicTable;
7365 UCHAR ucNumCustomThermalPolicy;
7366 USHORT usCustomThermalPolicyArrayOffset;
7367 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2;
7369 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
7371 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2;
7372 USHORT usFormatID; // To be used ONLY by PPGen.
7373 USHORT usFanTableOffset;
7374 USHORT usExtendendedHeaderOffset;
7375 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
7377 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
7379 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
7380 ULONG ulGoldenPPID; // PPGen use only
7381 ULONG ulGoldenRevision; // PPGen use only
7382 USHORT usVddcDependencyOnSCLKOffset;
7383 USHORT usVddciDependencyOnMCLKOffset;
7384 USHORT usVddcDependencyOnMCLKOffset;
7385 USHORT usMaxClockVoltageOnDCOffset;
7386 USHORT usReserved[2];
7387 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
7389 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
7391 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4;
7393 ULONG ulNearTDPLimit;
7394 ULONG ulSQRampingThreshold;
7395 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table
7396 ULONG ulCACLeakage; // TBD, this parameter is still under discussion. Change to ulReserved if not needed.
7398 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
7400 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification
7401 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
7402 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
7403 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
7404 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
7405 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
7406 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
7407 // 2, 4, 6, 7 are reserved
7409 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
7410 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
7411 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
7412 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
7413 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
7414 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
7415 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
7416 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
7417 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
7418 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
7419 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000
7420 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000
7421 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000
7423 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
7424 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
7425 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002
7427 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
7428 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
7429 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
7431 // 0 is 2.5Gb/s, 1 is 5Gb/s
7432 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004
7433 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2
7435 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
7436 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8
7437 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3
7439 // lookup into reduced refresh-rate table
7440 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00
7441 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
7443 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0
7444 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1
7445 // 2-15 TBD as needed.
7447 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
7448 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
7449 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
7450 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
7452 //memory related flags
7453 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000
7455 //M3 Arb //2bits, current 3 sets of parameters in total
7456 #define ATOM_PPLIB_M3ARB_MASK 0x00060000
7457 #define ATOM_PPLIB_M3ARB_SHIFT 17
7459 #define ATOM_PPLIB_ENABLE_DRR 0x00080000
7461 // remaining 16 bits are reserved
7462 typedef struct _ATOM_PPLIB_THERMAL_STATE
7464 UCHAR ucMinTemperature;
7465 UCHAR ucMaxTemperature;
7466 UCHAR ucThermalAction;
7467 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE;
7469 // Contained in an array starting at the offset
7470 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
7471 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
7472 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12
7473 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24
7474 typedef struct _ATOM_PPLIB_NONCLOCK_INFO
7476 USHORT usClassification;
7477 UCHAR ucMinTemperature;
7478 UCHAR ucMaxTemperature;
7479 ULONG ulCapsAndSettings;
7480 UCHAR ucRequiredPower;
7481 USHORT usClassification2;
7485 } ATOM_PPLIB_NONCLOCK_INFO;
7487 // Contained in an array starting at the offset
7488 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
7489 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices
7490 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
7492 USHORT usEngineClockLow;
7493 UCHAR ucEngineClockHigh;
7495 USHORT usMemoryClockLow;
7496 UCHAR ucMemoryClockHigh;
7502 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7504 } ATOM_PPLIB_R600_CLOCK_INFO;
7506 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
7507 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1
7508 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
7509 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
7510 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
7511 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
7512 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0).
7514 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
7516 USHORT usEngineClockLow;
7517 UCHAR ucEngineClockHigh;
7519 USHORT usMemoryClockLow;
7520 UCHAR ucMemoryClockHigh;
7526 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7528 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
7530 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
7533 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600).
7534 UCHAR ucLowEngineClockHigh;
7535 USHORT usHighEngineClockLow; // High Engine clock in MHz.
7536 UCHAR ucHighEngineClockHigh;
7537 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
7538 UCHAR ucMemoryClockHigh; // Currentyl unused.
7539 UCHAR ucPadding; // For proper alignment and size.
7540 USHORT usVDDC; // For the 780, use: None, Low, High, Variable
7541 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
7542 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement.
7543 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
7545 } ATOM_PPLIB_RS780_CLOCK_INFO;
7547 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
7548 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
7549 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
7550 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
7552 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
7553 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1
7554 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
7556 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
7557 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
7558 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
7560 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
7561 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
7562 UCHAR ucEngineClockHigh; //clockfrequency >> 16.
7563 UCHAR vddcIndex; //2-bit vddc index;
7564 UCHAR leakage; //please use 8-bit absolute value, not the 6-bit % value
7565 //please initalize to 0
7567 //please initalize to 0
7569 //please initialize to 0s
7571 }ATOM_PPLIB_SUMO_CLOCK_INFO;
7575 typedef struct _ATOM_PPLIB_STATE_V2
7577 //number of valid dpm levels in this state; Driver uses it to calculate the whole
7578 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
7579 UCHAR ucNumDPMLevels;
7581 //a index to the array of nonClockInfos
7582 UCHAR nonClockInfoIndex;
7584 * Driver will read the first ucNumDPMLevels in this array
7586 UCHAR clockInfoIndex[1];
7587 } ATOM_PPLIB_STATE_V2;
7589 typedef struct StateArray{
7590 //how many states we have
7593 ATOM_PPLIB_STATE_V2 states[1];
7597 typedef struct ClockInfoArray{
7598 //how many clock levels we have
7601 //sizeof(ATOM_PPLIB_SUMO_CLOCK_INFO)
7605 ATOM_PPLIB_SUMO_CLOCK_INFO clockInfo[1];
7608 typedef struct NonClockInfoArray{
7610 //how many non-clock levels we have. normally should be same as number of states
7612 //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
7615 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
7618 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
7623 }ATOM_PPLIB_Clock_Voltage_Dependency_Record;
7625 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
7627 UCHAR ucNumEntries; // Number of entries.
7628 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries.
7629 }ATOM_PPLIB_Clock_Voltage_Dependency_Table;
7631 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
7639 }ATOM_PPLIB_Clock_Voltage_Limit_Record;
7641 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
7643 UCHAR ucNumEntries; // Number of entries.
7644 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries.
7645 }ATOM_PPLIB_Clock_Voltage_Limit_Table;
7647 /**************************************************************************/
7650 // Following definitions are for compatibility issue in different SW components.
7651 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01
7652 #define Object_Info Object_Header
7653 #define AdjustARB_SEQ MC_InitParameter
7654 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo
7655 #define ASIC_VDDCI_Info ASIC_ProfilingInfo
7656 #define ASIC_MVDDQ_Info MemoryTrainingInfo
7657 #define SS_Info PPLL_SS_Info
7658 #define ASIC_MVDDC_Info ASIC_InternalSS_Info
7659 #define DispDevicePriorityInfo SaveRestoreInfo
7660 #define DispOutInfo TV_VideoMode
7663 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
7664 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
7666 //New device naming, remove them when both DAL/VBIOS is ready
7667 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
7668 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
7670 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
7671 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
7673 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
7674 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
7676 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
7677 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
7679 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
7680 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
7682 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009
7683 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
7685 #define ATOM_S0_DFP1I ATOM_S0_DFP1
7686 #define ATOM_S0_DFP1X ATOM_S0_DFP2
7688 #define ATOM_S0_DFP2I 0x00200000L
7689 #define ATOM_S0_DFP2Ib2 0x20
7691 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
7692 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
7694 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
7695 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
7697 #define ATOM_S3_DFP2I_ACTIVEb1 0x02
7699 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
7700 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
7702 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L
7704 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
7705 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
7706 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
7708 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
7709 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
7711 #define ATOM_S5_DOS_REQ_DFP2I 0x0200
7712 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
7713 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
7715 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
7716 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
7718 #define TMDS1XEncoderControl DVOEncoderControl
7719 #define DFP1XOutputControl DVOOutputControl
7721 #define ExternalDFPOutputControl DFP1XOutputControl
7722 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl
7724 #define DFP1IOutputControl TMDSAOutputControl
7725 #define DFP2IOutputControl LVTMAOutputControl
7727 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
7728 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
7730 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
7731 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
7733 #define ucDac1Standard ucDacStandard
7734 #define ucDac2Standard ucDacStandard
7736 #define TMDS1EncoderControl TMDSAEncoderControl
7737 #define TMDS2EncoderControl LVTMAEncoderControl
7739 #define DFP1OutputControl TMDSAOutputControl
7740 #define DFP2OutputControl LVTMAOutputControl
7741 #define CRT1OutputControl DAC1OutputControl
7742 #define CRT2OutputControl DAC2OutputControl
7744 //These two lines will be removed for sure in a few days, will follow up with Michael V.
7745 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
7746 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
7748 //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
7749 //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7750 //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7751 //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7752 //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7754 #define ATOM_S6_ACC_REQ_TV2 0x00400000L
7755 #define ATOM_DEVICE_TV2_INDEX 0x00000006
7756 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
7757 #define ATOM_S0_TV2 0x00100000L
7758 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE
7759 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE
7762 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
7763 #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
7764 #define ATOM_S2_TV1_DPMS_STATE 0x00040000L
7765 #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
7766 #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
7767 #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
7768 #define ATOM_S2_TV2_DPMS_STATE 0x00400000L
7769 #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
7770 #define ATOM_S2_CV_DPMS_STATE 0x01000000L
7771 #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
7772 #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L
7773 #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L
7775 #define ATOM_S2_CRT1_DPMS_STATEb2 0x01
7776 #define ATOM_S2_LCD1_DPMS_STATEb2 0x02
7777 #define ATOM_S2_TV1_DPMS_STATEb2 0x04
7778 #define ATOM_S2_DFP1_DPMS_STATEb2 0x08
7779 #define ATOM_S2_CRT2_DPMS_STATEb2 0x10
7780 #define ATOM_S2_LCD2_DPMS_STATEb2 0x20
7781 #define ATOM_S2_TV2_DPMS_STATEb2 0x40
7782 #define ATOM_S2_DFP2_DPMS_STATEb2 0x80
7783 #define ATOM_S2_CV_DPMS_STATEb3 0x01
7784 #define ATOM_S2_DFP3_DPMS_STATEb3 0x02
7785 #define ATOM_S2_DFP4_DPMS_STATEb3 0x04
7786 #define ATOM_S2_DFP5_DPMS_STATEb3 0x08
7788 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
7789 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
7790 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
7792 /*********************************************************************************/
7794 #pragma pack() // BIOS data must use byte aligment
7803 ULONG TableLength; //Length
7807 UCHAR OemTableId[8]; //UINT64 OemTableId;
7810 ULONG CreatorRevision;
7811 } AMD_ACPI_DESCRIPTION_HEADER;
7813 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
7815 UINT32 Signature; //0x0
7816 UINT32 Length; //0x4
7817 UINT8 Revision; //0x8
7818 UINT8 Checksum; //0x9
7819 UINT8 OemId[6]; //0xA
7820 UINT64 OemTableId; //0x10
7821 UINT32 OemRevision; //0x18
7822 UINT32 CreatorId; //0x1C
7823 UINT32 CreatorRevision; //0x20
7824 }EFI_ACPI_DESCRIPTION_HEADER;
7827 AMD_ACPI_DESCRIPTION_HEADER SHeader;
7828 UCHAR TableUUID[16]; //0x24
7829 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
7830 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
7831 ULONG Reserved[4]; //0x3C
7835 ULONG PCIBus; //0x4C
7836 ULONG PCIDevice; //0x50
7837 ULONG PCIFunction; //0x54
7838 USHORT VendorID; //0x58
7839 USHORT DeviceID; //0x5A
7840 USHORT SSVID; //0x5C
7842 ULONG Revision; //0x60
7843 ULONG ImageLength; //0x64
7848 VFCT_IMAGE_HEADER VbiosHeader;
7849 UCHAR VbiosContent[1];
7853 VFCT_IMAGE_HEADER Lib1Header;
7854 UCHAR Lib1Content[1];
7860 #endif /* _ATOMBIOS_H */
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