drivers/gpu/drm/nouveau/nvif/class.h

   1 #ifndef __NVIF_CLASS_H__
   2 #define __NVIF_CLASS_H__
   3
   4 /*******************************************************************************
   5  * class identifiers
   6  ******************************************************************************/
   7
   8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
   9 #define NV_DEVICE                                                    0x00000080
  10
  11 #define NV_DMA_FROM_MEMORY                                           0x00000002
  12 #define NV_DMA_TO_MEMORY                                             0x00000003
  13 #define NV_DMA_IN_MEMORY                                             0x0000003d
  14
  15
  16 /*******************************************************************************
  17  * client
  18  ******************************************************************************/
  19
  20 #define NV_CLIENT_DEVLIST                                                  0x00
  21
  22 struct nv_client_devlist_v0 {
  23         __u8  version;
  24         __u8  count;
  25         __u8  pad02[6];
  26         __u64 device[];
  27 };
  28
  29
  30 /*******************************************************************************
  31  * device
  32  ******************************************************************************/
  33
  34 struct nv_device_v0 {
  35         __u8  version;
  36         __u8  pad01[7];
  37         __u64 device;   /* device identifier, ~0 for client default */
  38 #define NV_DEVICE_V0_DISABLE_IDENTIFY                     0x0000000000000001ULL
  39 #define NV_DEVICE_V0_DISABLE_MMIO                         0x0000000000000002ULL
  40 #define NV_DEVICE_V0_DISABLE_VBIOS                        0x0000000000000004ULL
  41 #define NV_DEVICE_V0_DISABLE_CORE                         0x0000000000000008ULL
  42 #define NV_DEVICE_V0_DISABLE_DISP                         0x0000000000010000ULL
  43 #define NV_DEVICE_V0_DISABLE_FIFO                         0x0000000000020000ULL
  44 #define NV_DEVICE_V0_DISABLE_GRAPH                        0x0000000100000000ULL
  45 #define NV_DEVICE_V0_DISABLE_MPEG                         0x0000000200000000ULL
  46 #define NV_DEVICE_V0_DISABLE_ME                           0x0000000400000000ULL
  47 #define NV_DEVICE_V0_DISABLE_VP                           0x0000000800000000ULL
  48 #define NV_DEVICE_V0_DISABLE_CRYPT                        0x0000001000000000ULL
  49 #define NV_DEVICE_V0_DISABLE_BSP                          0x0000002000000000ULL
  50 #define NV_DEVICE_V0_DISABLE_PPP                          0x0000004000000000ULL
  51 #define NV_DEVICE_V0_DISABLE_COPY0                        0x0000008000000000ULL
  52 #define NV_DEVICE_V0_DISABLE_COPY1                        0x0000010000000000ULL
  53 #define NV_DEVICE_V0_DISABLE_VIC                          0x0000020000000000ULL
  54 #define NV_DEVICE_V0_DISABLE_VENC                         0x0000040000000000ULL
  55         __u64 disable;  /* disable particular subsystems */
  56         __u64 debug0;   /* as above, but *internal* ids, and *NOT* ABI */
  57 };
  58
  59 #define NV_DEVICE_V0_INFO                                                  0x00
  60
  61 struct nv_device_info_v0 {
  62         __u8  version;
  63 #define NV_DEVICE_INFO_V0_IGP                                              0x00
  64 #define NV_DEVICE_INFO_V0_PCI                                              0x01
  65 #define NV_DEVICE_INFO_V0_AGP                                              0x02
  66 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
  67 #define NV_DEVICE_INFO_V0_SOC                                              0x04
  68         __u8  platform;
  69         __u16 chipset;  /* from NV_PMC_BOOT_0 */
  70         __u8  revision; /* from NV_PMC_BOOT_0 */
  71 #define NV_DEVICE_INFO_V0_TNT                                              0x01
  72 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
  73 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
  74 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
  75 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
  76 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
  77 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
  78 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
  79 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
  80         __u8  family;
  81         __u8  pad06[2];
  82         __u64 ram_size;
  83         __u64 ram_user;
  84 };
  85
  86
  87 /*******************************************************************************
  88  * context dma
  89  ******************************************************************************/
  90
  91 struct nv_dma_v0 {
  92         __u8  version;
  93 #define NV_DMA_V0_TARGET_VM                                                0x00
  94 #define NV_DMA_V0_TARGET_VRAM                                              0x01
  95 #define NV_DMA_V0_TARGET_PCI                                               0x02
  96 #define NV_DMA_V0_TARGET_PCI_US                                            0x03
  97 #define NV_DMA_V0_TARGET_AGP                                               0x04
  98         __u8  target;
  99 #define NV_DMA_V0_ACCESS_VM                                                0x00
 100 #define NV_DMA_V0_ACCESS_RD                                                0x01
 101 #define NV_DMA_V0_ACCESS_WR                                                0x02
 102 #define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
 103         __u8  access;
 104         __u8  pad03[5];
 105         __u64 start;
 106         __u64 limit;
 107         /* ... chipset-specific class data */
 108 };
 109
 110 struct nv50_dma_v0 {
 111         __u8  version;
 112 #define NV50_DMA_V0_PRIV_VM                                                0x00
 113 #define NV50_DMA_V0_PRIV_US                                                0x01
 114 #define NV50_DMA_V0_PRIV__S                                                0x02
 115         __u8  priv;
 116 #define NV50_DMA_V0_PART_VM                                                0x00
 117 #define NV50_DMA_V0_PART_256                                               0x01
 118 #define NV50_DMA_V0_PART_1KB                                               0x02
 119         __u8  part;
 120 #define NV50_DMA_V0_COMP_NONE                                              0x00
 121 #define NV50_DMA_V0_COMP_1                                                 0x01
 122 #define NV50_DMA_V0_COMP_2                                                 0x02
 123 #define NV50_DMA_V0_COMP_VM                                                0x03
 124         __u8  comp;
 125 #define NV50_DMA_V0_KIND_PITCH                                             0x00
 126 #define NV50_DMA_V0_KIND_VM                                                0x7f
 127         __u8  kind;
 128         __u8  pad05[3];
 129 };
 130
 131 struct gf100_dma_v0 {
 132         __u8  version;
 133 #define GF100_DMA_V0_PRIV_VM                                               0x00
 134 #define GF100_DMA_V0_PRIV_US                                               0x01
 135 #define GF100_DMA_V0_PRIV__S                                               0x02
 136         __u8  priv;
 137 #define GF100_DMA_V0_KIND_PITCH                                            0x00
 138 #define GF100_DMA_V0_KIND_VM                                               0xff
 139         __u8  kind;
 140         __u8  pad03[5];
 141 };
 142
 143 struct gf110_dma_v0 {
 144         __u8  version;
 145 #define GF110_DMA_V0_PAGE_LP                                               0x00
 146 #define GF110_DMA_V0_PAGE_SP                                               0x01
 147         __u8  page;
 148 #define GF110_DMA_V0_KIND_PITCH                                            0x00
 149 #define GF110_DMA_V0_KIND_VM                                               0xff
 150         __u8  kind;
 151         __u8  pad03[5];
 152 };
 153
 154
 155 /*******************************************************************************
 156  * perfmon
 157  ******************************************************************************/
 158
 159 struct nvif_perfctr_v0 {
 160         __u8  version;
 161         __u8  pad01[1];
 162         __u16 logic_op;
 163         __u8  pad04[4];
 164         char  name[4][64];
 165 };
 166
 167 #define NVIF_PERFCTR_V0_QUERY                                              0x00
 168 #define NVIF_PERFCTR_V0_SAMPLE                                             0x01
 169 #define NVIF_PERFCTR_V0_READ                                               0x02
 170
 171 struct nvif_perfctr_query_v0 {
 172         __u8  version;
 173         __u8  pad01[3];
 174         __u32 iter;
 175         char  name[64];
 176 };
 177
 178 struct nvif_perfctr_sample {
 179 };
 180
 181 struct nvif_perfctr_read_v0 {
 182         __u8  version;
 183         __u8  pad01[7];
 184         __u32 ctr;
 185         __u32 clk;
 186 };
 187
 188 #endif