drivers/gpu/drm/nouveau/nvd0_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_encoder.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_fb.h"
  35 #include "nv50_display.h"
  36
  37 #define MEM_SYNC 0xe0000001
  38 #define MEM_VRAM 0xe0010000
  39 #include "nouveau_dma.h"
  40
  41 struct nvd0_display {
  42         struct nouveau_gpuobj *mem;
  43         struct {
  44                 dma_addr_t handle;
  45                 u32 *ptr;
  46         } evo[1];
  47
  48         struct tasklet_struct tasklet;
  49         u32 modeset;
  50 };
  51
  52 static struct nvd0_display *
  53 nvd0_display(struct drm_device *dev)
  54 {
  55         struct drm_nouveau_private *dev_priv = dev->dev_private;
  56         return dev_priv->engine.display.priv;
  57 }
  58
  59 static int
  60 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
  61 {
  62         int ret = 0;
  63         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
  64         nv_wr32(dev, 0x610704 + (id * 0x10), data);
  65         nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
  66         if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
  67                 ret = -EBUSY;
  68         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
  69         return ret;
  70 }
  71
  72 static u32 *
  73 evo_wait(struct drm_device *dev, int id, int nr)
  74 {
  75         struct nvd0_display *disp = nvd0_display(dev);
  76         u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
  77
  78         if (put + nr >= (PAGE_SIZE / 4)) {
  79                 disp->evo[id].ptr[put] = 0x20000000;
  80
  81                 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
  82                 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
  83                         NV_ERROR(dev, "evo %d dma stalled\n", id);
  84                         return NULL;
  85                 }
  86
  87                 put = 0;
  88         }
  89
  90         return disp->evo[id].ptr + put;
  91 }
  92
  93 static void
  94 evo_kick(u32 *push, struct drm_device *dev, int id)
  95 {
  96         struct nvd0_display *disp = nvd0_display(dev);
  97         nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
  98 }
  99
 100 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 101 #define evo_data(p,d)   *((p)++) = (d)
 102
 103 static struct drm_crtc *
 104 nvd0_display_crtc_get(struct drm_encoder *encoder)
 105 {
 106         return nouveau_encoder(encoder)->crtc;
 107 }
 108
 109 /******************************************************************************
 110  * CRTC
 111  *****************************************************************************/
 112 static int
 113 nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
 114 {
 115         struct drm_device *dev = nv_crtc->base.dev;
 116         u32 *push, mode;
 117
 118         mode = 0x00000000;
 119         if (on) {
 120                 /* 0x11: 6bpc dynamic 2x2
 121                  * 0x13: 8bpc dynamic 2x2
 122                  * 0x19: 6bpc static 2x2
 123                  * 0x1b: 8bpc static 2x2
 124                  * 0x21: 6bpc temporal
 125                  * 0x23: 8bpc temporal
 126                  */
 127                 mode = 0x00000011;
 128         }
 129
 130         push = evo_wait(dev, 0, 4);
 131         if (push) {
 132                 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x300), 1);
 133                 evo_data(push, mode);
 134                 if (update) {
 135                         evo_mthd(push, 0x0080, 1);
 136                         evo_data(push, 0x00000000);
 137                 }
 138                 evo_kick(push, dev, 0);
 139         }
 140
 141         return 0;
 142 }
 143
 144 static int
 145 nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, int type, bool update)
 146 {
 147         struct drm_display_mode *mode = &nv_crtc->base.mode;
 148         struct drm_device *dev = nv_crtc->base.dev;
 149         struct nouveau_connector *nv_connector;
 150         u32 *push, outX, outY;
 151
 152         outX = mode->hdisplay;
 153         outY = mode->vdisplay;
 154
 155         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 156         if (nv_connector && nv_connector->native_mode) {
 157                 struct drm_display_mode *native = nv_connector->native_mode;
 158                 u32 xratio = (native->hdisplay << 19) / mode->hdisplay;
 159                 u32 yratio = (native->vdisplay << 19) / mode->vdisplay;
 160
 161                 switch (type) {
 162                 case DRM_MODE_SCALE_ASPECT:
 163                         if (xratio > yratio) {
 164                                 outX = (mode->hdisplay * yratio) >> 19;
 165                                 outY = (mode->vdisplay * yratio) >> 19;
 166                         } else {
 167                                 outX = (mode->hdisplay * xratio) >> 19;
 168                                 outY = (mode->vdisplay * xratio) >> 19;
 169                         }
 170                         break;
 171                 case DRM_MODE_SCALE_FULLSCREEN:
 172                         outX = native->hdisplay;
 173                         outY = native->vdisplay;
 174                         break;
 175                 default:
 176                         break;
 177                 }
 178         }
 179
 180         push = evo_wait(dev, 0, 16);
 181         if (push) {
 182                 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 183                 evo_data(push, (outY << 16) | outX);
 184                 evo_data(push, (outY << 16) | outX);
 185                 evo_data(push, (outY << 16) | outX);
 186                 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 187                 evo_data(push, 0x00000000);
 188                 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 189                 evo_data(push, (mode->vdisplay << 16) | mode->hdisplay);
 190                 if (update) {
 191                         evo_mthd(push, 0x0080, 1);
 192                         evo_data(push, 0x00000000);
 193                 }
 194                 evo_kick(push, dev, 0);
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int
 201 nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 202                     int x, int y, bool update)
 203 {
 204         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 205         u32 *push;
 206
 207         push = evo_wait(fb->dev, 0, 16);
 208         if (push) {
 209                 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 210                 evo_data(push, nvfb->nvbo->bo.offset >> 8);
 211                 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 212                 evo_data(push, (fb->height << 16) | fb->width);
 213                 evo_data(push, nvfb->r_pitch);
 214                 evo_data(push, nvfb->r_format);
 215                 evo_data(push, nvfb->r_dma);
 216                 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 217                 evo_data(push, (y << 16) | x);
 218                 if (update) {
 219                         evo_mthd(push, 0x0080, 1);
 220                         evo_data(push, 0x00000000);
 221                 }
 222                 evo_kick(push, fb->dev, 0);
 223         }
 224
 225         nv_crtc->fb.tile_flags = nvfb->r_dma;
 226         return 0;
 227 }
 228
 229 static void
 230 nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
 231 {
 232         struct drm_device *dev = nv_crtc->base.dev;
 233         u32 *push = evo_wait(dev, 0, 16);
 234         if (push) {
 235                 if (show) {
 236                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 237                         evo_data(push, 0x85000000);
 238                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 239                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 240                         evo_data(push, MEM_VRAM);
 241                 } else {
 242                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 243                         evo_data(push, 0x05000000);
 244                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 245                         evo_data(push, 0x00000000);
 246                 }
 247
 248                 if (update) {
 249                         evo_mthd(push, 0x0080, 1);
 250                         evo_data(push, 0x00000000);
 251                 }
 252
 253                 evo_kick(push, dev, 0);
 254         }
 255 }
 256
 257 static void
 258 nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
 259 {
 260 }
 261
 262 static void
 263 nvd0_crtc_prepare(struct drm_crtc *crtc)
 264 {
 265         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 266         u32 *push;
 267
 268         push = evo_wait(crtc->dev, 0, 2);
 269         if (push) {
 270                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 271                 evo_data(push, 0x00000000);
 272                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 273                 evo_data(push, 0x03000000);
 274                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 275                 evo_data(push, 0x00000000);
 276                 evo_kick(push, crtc->dev, 0);
 277         }
 278
 279         nvd0_crtc_cursor_show(nv_crtc, false, false);
 280 }
 281
 282 static void
 283 nvd0_crtc_commit(struct drm_crtc *crtc)
 284 {
 285         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 286         u32 *push;
 287
 288         push = evo_wait(crtc->dev, 0, 32);
 289         if (push) {
 290                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 291                 evo_data(push, nv_crtc->fb.tile_flags);
 292                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 293                 evo_data(push, 0x83000000);
 294                 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 295                 evo_data(push, 0x00000000);
 296                 evo_data(push, 0x00000000);
 297                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 298                 evo_data(push, MEM_VRAM);
 299                 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 300                 evo_data(push, 0xffffff00);
 301                 evo_kick(push, crtc->dev, 0);
 302         }
 303
 304         nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
 305 }
 306
 307 static bool
 308 nvd0_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
 309                      struct drm_display_mode *adjusted_mode)
 310 {
 311         return true;
 312 }
 313
 314 static int
 315 nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 316 {
 317         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 318         int ret;
 319
 320         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 321         if (ret)
 322                 return ret;
 323
 324         if (old_fb) {
 325                 nvfb = nouveau_framebuffer(old_fb);
 326                 nouveau_bo_unpin(nvfb->nvbo);
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int
 333 nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 334                    struct drm_display_mode *mode, int x, int y,
 335                    struct drm_framebuffer *old_fb)
 336 {
 337         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 338         struct nouveau_connector *nv_connector;
 339         u32 htotal = mode->htotal;
 340         u32 vtotal = mode->vtotal;
 341         u32 hsyncw = mode->hsync_end - mode->hsync_start - 1;
 342         u32 vsyncw = mode->vsync_end - mode->vsync_start - 1;
 343         u32 hfrntp = mode->hsync_start - mode->hdisplay;
 344         u32 vfrntp = mode->vsync_start - mode->vdisplay;
 345         u32 hbackp = mode->htotal - mode->hsync_end;
 346         u32 vbackp = mode->vtotal - mode->vsync_end;
 347         u32 hss2be = hsyncw + hbackp;
 348         u32 vss2be = vsyncw + vbackp;
 349         u32 hss2de = htotal - hfrntp;
 350         u32 vss2de = vtotal - vfrntp;
 351         u32 syncs, *push;
 352         int ret;
 353
 354         syncs = 0x00000001;
 355         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 356                 syncs |= 0x00000008;
 357         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 358                 syncs |= 0x00000010;
 359
 360         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 361         if (ret)
 362                 return ret;
 363
 364         push = evo_wait(crtc->dev, 0, 64);
 365         if (push) {
 366                 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 5);
 367                 evo_data(push, 0x00000000);
 368                 evo_data(push, (vtotal << 16) | htotal);
 369                 evo_data(push, (vsyncw << 16) | hsyncw);
 370                 evo_data(push, (vss2be << 16) | hss2be);
 371                 evo_data(push, (vss2de << 16) | hss2de);
 372                 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 373                 evo_data(push, 0x00000000); /* ??? */
 374                 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 375                 evo_data(push, mode->clock * 1000);
 376                 evo_data(push, 0x00200000); /* ??? */
 377                 evo_data(push, mode->clock * 1000);
 378                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 1);
 379                 evo_data(push, syncs);
 380                 evo_kick(push, crtc->dev, 0);
 381         }
 382
 383         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 384         nvd0_crtc_set_dither(nv_crtc, nv_connector->use_dithering, false);
 385         nvd0_crtc_set_scale(nv_crtc, nv_connector->scaling_mode, false);
 386         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 387         return 0;
 388 }
 389
 390 static int
 391 nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 392                         struct drm_framebuffer *old_fb)
 393 {
 394         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 395         int ret;
 396
 397         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 398         if (ret)
 399                 return ret;
 400
 401         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 402         return 0;
 403 }
 404
 405 static int
 406 nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 407                                struct drm_framebuffer *fb, int x, int y,
 408                                enum mode_set_atomic state)
 409 {
 410         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 411         nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
 412         return 0;
 413 }
 414
 415 static void
 416 nvd0_crtc_lut_load(struct drm_crtc *crtc)
 417 {
 418         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 419         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 420         int i;
 421
 422         for (i = 0; i < 256; i++) {
 423                 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
 424                 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
 425                 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
 426         }
 427 }
 428
 429 static int
 430 nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 431                      uint32_t handle, uint32_t width, uint32_t height)
 432 {
 433         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 434         struct drm_device *dev = crtc->dev;
 435         struct drm_gem_object *gem;
 436         struct nouveau_bo *nvbo;
 437         bool visible = (handle != 0);
 438         int i, ret = 0;
 439
 440         if (visible) {
 441                 if (width != 64 || height != 64)
 442                         return -EINVAL;
 443
 444                 gem = drm_gem_object_lookup(dev, file_priv, handle);
 445                 if (unlikely(!gem))
 446                         return -ENOENT;
 447                 nvbo = nouveau_gem_object(gem);
 448
 449                 ret = nouveau_bo_map(nvbo);
 450                 if (ret == 0) {
 451                         for (i = 0; i < 64 * 64; i++) {
 452                                 u32 v = nouveau_bo_rd32(nvbo, i);
 453                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 454                         }
 455                         nouveau_bo_unmap(nvbo);
 456                 }
 457
 458                 drm_gem_object_unreference_unlocked(gem);
 459         }
 460
 461         if (visible != nv_crtc->cursor.visible) {
 462                 nvd0_crtc_cursor_show(nv_crtc, visible, true);
 463                 nv_crtc->cursor.visible = visible;
 464         }
 465
 466         return ret;
 467 }
 468
 469 static int
 470 nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 471 {
 472         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 473         const u32 data = (y << 16) | x;
 474
 475         nv_wr32(crtc->dev, 0x64d084 + (nv_crtc->index * 0x1000), data);
 476         nv_wr32(crtc->dev, 0x64d080 + (nv_crtc->index * 0x1000), 0x00000000);
 477         return 0;
 478 }
 479
 480 static void
 481 nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 482                     uint32_t start, uint32_t size)
 483 {
 484         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 485         u32 end = max(start + size, (u32)256);
 486         u32 i;
 487
 488         for (i = start; i < end; i++) {
 489                 nv_crtc->lut.r[i] = r[i];
 490                 nv_crtc->lut.g[i] = g[i];
 491                 nv_crtc->lut.b[i] = b[i];
 492         }
 493
 494         nvd0_crtc_lut_load(crtc);
 495 }
 496
 497 static void
 498 nvd0_crtc_destroy(struct drm_crtc *crtc)
 499 {
 500         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 501         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 502         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 503         nouveau_bo_unmap(nv_crtc->lut.nvbo);
 504         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 505         drm_crtc_cleanup(crtc);
 506         kfree(crtc);
 507 }
 508
 509 static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
 510         .dpms = nvd0_crtc_dpms,
 511         .prepare = nvd0_crtc_prepare,
 512         .commit = nvd0_crtc_commit,
 513         .mode_fixup = nvd0_crtc_mode_fixup,
 514         .mode_set = nvd0_crtc_mode_set,
 515         .mode_set_base = nvd0_crtc_mode_set_base,
 516         .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
 517         .load_lut = nvd0_crtc_lut_load,
 518 };
 519
 520 static const struct drm_crtc_funcs nvd0_crtc_func = {
 521         .cursor_set = nvd0_crtc_cursor_set,
 522         .cursor_move = nvd0_crtc_cursor_move,
 523         .gamma_set = nvd0_crtc_gamma_set,
 524         .set_config = drm_crtc_helper_set_config,
 525         .destroy = nvd0_crtc_destroy,
 526 };
 527
 528 static int
 529 nvd0_crtc_create(struct drm_device *dev, int index)
 530 {
 531         struct nouveau_crtc *nv_crtc;
 532         struct drm_crtc *crtc;
 533         int ret, i;
 534
 535         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
 536         if (!nv_crtc)
 537                 return -ENOMEM;
 538
 539         nv_crtc->index = index;
 540         nv_crtc->set_dither = nvd0_crtc_set_dither;
 541         nv_crtc->set_scale = nvd0_crtc_set_scale;
 542         for (i = 0; i < 256; i++) {
 543                 nv_crtc->lut.r[i] = i << 8;
 544                 nv_crtc->lut.g[i] = i << 8;
 545                 nv_crtc->lut.b[i] = i << 8;
 546         }
 547
 548         crtc = &nv_crtc->base;
 549         drm_crtc_init(dev, crtc, &nvd0_crtc_func);
 550         drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
 551         drm_mode_crtc_set_gamma_size(crtc, 256);
 552
 553         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 554                              0, 0x0000, &nv_crtc->cursor.nvbo);
 555         if (!ret) {
 556                 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
 557                 if (!ret)
 558                         ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
 559                 if (ret)
 560                         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 561         }
 562
 563         if (ret)
 564                 goto out;
 565
 566         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 567                              0, 0x0000, &nv_crtc->lut.nvbo);
 568         if (!ret) {
 569                 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
 570                 if (!ret)
 571                         ret = nouveau_bo_map(nv_crtc->lut.nvbo);
 572                 if (ret)
 573                         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 574         }
 575
 576         if (ret)
 577                 goto out;
 578
 579         nvd0_crtc_lut_load(crtc);
 580
 581 out:
 582         if (ret)
 583                 nvd0_crtc_destroy(crtc);
 584         return ret;
 585 }
 586
 587 /******************************************************************************
 588  * DAC
 589  *****************************************************************************/
 590 static void
 591 nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
 592 {
 593         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 594         struct drm_device *dev = encoder->dev;
 595         int or = nv_encoder->or;
 596         u32 dpms_ctrl;
 597
 598         dpms_ctrl = 0x80000000;
 599         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 600                 dpms_ctrl |= 0x00000001;
 601         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 602                 dpms_ctrl |= 0x00000004;
 603
 604         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 605         nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
 606         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 607 }
 608
 609 static bool
 610 nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 611                     struct drm_display_mode *adjusted_mode)
 612 {
 613         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 614         struct nouveau_connector *nv_connector;
 615
 616         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 617         if (nv_connector && nv_connector->native_mode) {
 618                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 619                         int id = adjusted_mode->base.id;
 620                         *adjusted_mode = *nv_connector->native_mode;
 621                         adjusted_mode->base.id = id;
 622                 }
 623         }
 624
 625         return true;
 626 }
 627
 628 static void
 629 nvd0_dac_prepare(struct drm_encoder *encoder)
 630 {
 631 }
 632
 633 static void
 634 nvd0_dac_commit(struct drm_encoder *encoder)
 635 {
 636 }
 637
 638 static void
 639 nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 640                   struct drm_display_mode *adjusted_mode)
 641 {
 642         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 643         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 644         u32 *push;
 645
 646         nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 647
 648         push = evo_wait(encoder->dev, 0, 4);
 649         if (push) {
 650                 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 2);
 651                 evo_data(push, 1 << nv_crtc->index);
 652                 evo_data(push, 0x00ff);
 653                 evo_kick(push, encoder->dev, 0);
 654         }
 655
 656         nv_encoder->crtc = encoder->crtc;
 657 }
 658
 659 static void
 660 nvd0_dac_disconnect(struct drm_encoder *encoder)
 661 {
 662         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 663         struct drm_device *dev = encoder->dev;
 664         u32 *push;
 665
 666         if (nv_encoder->crtc) {
 667                 nvd0_crtc_prepare(nv_encoder->crtc);
 668
 669                 push = evo_wait(dev, 0, 4);
 670                 if (push) {
 671                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
 672                         evo_data(push, 0x00000000);
 673                         evo_mthd(push, 0x0080, 1);
 674                         evo_data(push, 0x00000000);
 675                         evo_kick(push, dev, 0);
 676                 }
 677
 678                 nv_encoder->crtc = NULL;
 679         }
 680 }
 681
 682 static enum drm_connector_status
 683 nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 684 {
 685         enum drm_connector_status status = connector_status_disconnected;
 686         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 687         struct drm_device *dev = encoder->dev;
 688         int or = nv_encoder->or;
 689         u32 load;
 690
 691         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000);
 692         udelay(9500);
 693         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000);
 694
 695         load = nv_rd32(dev, 0x61a00c + (or * 0x800));
 696         if ((load & 0x38000000) == 0x38000000)
 697                 status = connector_status_connected;
 698
 699         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000);
 700         return status;
 701 }
 702
 703 static void
 704 nvd0_dac_destroy(struct drm_encoder *encoder)
 705 {
 706         drm_encoder_cleanup(encoder);
 707         kfree(encoder);
 708 }
 709
 710 static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
 711         .dpms = nvd0_dac_dpms,
 712         .mode_fixup = nvd0_dac_mode_fixup,
 713         .prepare = nvd0_dac_prepare,
 714         .commit = nvd0_dac_commit,
 715         .mode_set = nvd0_dac_mode_set,
 716         .disable = nvd0_dac_disconnect,
 717         .get_crtc = nvd0_display_crtc_get,
 718         .detect = nvd0_dac_detect
 719 };
 720
 721 static const struct drm_encoder_funcs nvd0_dac_func = {
 722         .destroy = nvd0_dac_destroy,
 723 };
 724
 725 static int
 726 nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe)
 727 {
 728         struct drm_device *dev = connector->dev;
 729         struct nouveau_encoder *nv_encoder;
 730         struct drm_encoder *encoder;
 731
 732         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 733         if (!nv_encoder)
 734                 return -ENOMEM;
 735         nv_encoder->dcb = dcbe;
 736         nv_encoder->or = ffs(dcbe->or) - 1;
 737
 738         encoder = to_drm_encoder(nv_encoder);
 739         encoder->possible_crtcs = dcbe->heads;
 740         encoder->possible_clones = 0;
 741         drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
 742         drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
 743
 744         drm_mode_connector_attach_encoder(connector, encoder);
 745         return 0;
 746 }
 747
 748 /******************************************************************************
 749  * SOR
 750  *****************************************************************************/
 751 static void
 752 nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
 753 {
 754         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 755         struct drm_device *dev = encoder->dev;
 756         struct drm_encoder *partner;
 757         int or = nv_encoder->or;
 758         u32 dpms_ctrl;
 759
 760         nv_encoder->last_dpms = mode;
 761
 762         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
 763                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
 764
 765                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
 766                         continue;
 767
 768                 if (nv_partner != nv_encoder &&
 769                     nv_partner->dcb->or == nv_encoder->or) {
 770                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
 771                                 return;
 772                         break;
 773                 }
 774         }
 775
 776         dpms_ctrl  = (mode == DRM_MODE_DPMS_ON);
 777         dpms_ctrl |= 0x80000000;
 778
 779         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
 780         nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
 781         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
 782         nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
 783 }
 784
 785 static bool
 786 nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 787                     struct drm_display_mode *adjusted_mode)
 788 {
 789         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 790         struct nouveau_connector *nv_connector;
 791
 792         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 793         if (nv_connector && nv_connector->native_mode) {
 794                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 795                         int id = adjusted_mode->base.id;
 796                         *adjusted_mode = *nv_connector->native_mode;
 797                         adjusted_mode->base.id = id;
 798                 }
 799         }
 800
 801         return true;
 802 }
 803
 804 static void
 805 nvd0_sor_prepare(struct drm_encoder *encoder)
 806 {
 807 }
 808
 809 static void
 810 nvd0_sor_commit(struct drm_encoder *encoder)
 811 {
 812 }
 813
 814 static void
 815 nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
 816                   struct drm_display_mode *mode)
 817 {
 818         struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
 819         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 820         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 821         struct nouveau_connector *nv_connector;
 822         struct nvbios *bios = &dev_priv->vbios;
 823         u32 mode_ctrl = (1 << nv_crtc->index);
 824         u32 *push, or_config;
 825
 826         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 827         switch (nv_encoder->dcb->type) {
 828         case OUTPUT_TMDS:
 829                 if (nv_encoder->dcb->sorconf.link & 1) {
 830                         if (mode->clock < 165000)
 831                                 mode_ctrl |= 0x00000100;
 832                         else
 833                                 mode_ctrl |= 0x00000500;
 834                 } else {
 835                         mode_ctrl |= 0x00000200;
 836                 }
 837
 838                 or_config = (mode_ctrl & 0x00000f00) >> 8;
 839                 if (mode->clock >= 165000)
 840                         or_config |= 0x0100;
 841                 break;
 842         case OUTPUT_LVDS:
 843                 or_config = (mode_ctrl & 0x00000f00) >> 8;
 844                 if (bios->fp_no_ddc) {
 845                         if (bios->fp.dual_link)
 846                                 or_config |= 0x0100;
 847                         if (bios->fp.if_is_24bit)
 848                                 or_config |= 0x0200;
 849                 } else {
 850                         if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS_SPWG) {
 851                                 if (((u8 *)nv_connector->edid)[121] == 2)
 852                                         or_config |= 0x0100;
 853                         } else
 854                         if (mode->clock >= bios->fp.duallink_transition_clk) {
 855                                 or_config |= 0x0100;
 856                         }
 857
 858                         if (or_config & 0x0100) {
 859                                 if (bios->fp.strapless_is_24bit & 2)
 860                                         or_config |= 0x0200;
 861                         } else {
 862                                 if (bios->fp.strapless_is_24bit & 1)
 863                                         or_config |= 0x0200;
 864                         }
 865
 866                         if (nv_connector->base.display_info.bpc == 8)
 867                                 or_config |= 0x0200;
 868
 869                 }
 870                 break;
 871         default:
 872                 BUG_ON(1);
 873                 break;
 874         }
 875
 876         nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
 877
 878         push = evo_wait(encoder->dev, 0, 4);
 879         if (push) {
 880                 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 2);
 881                 evo_data(push, mode_ctrl);
 882                 evo_data(push, or_config);
 883                 evo_kick(push, encoder->dev, 0);
 884         }
 885
 886         nv_encoder->crtc = encoder->crtc;
 887 }
 888
 889 static void
 890 nvd0_sor_disconnect(struct drm_encoder *encoder)
 891 {
 892         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 893         struct drm_device *dev = encoder->dev;
 894         u32 *push;
 895
 896         if (nv_encoder->crtc) {
 897                 nvd0_crtc_prepare(nv_encoder->crtc);
 898
 899                 push = evo_wait(dev, 0, 4);
 900                 if (push) {
 901                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
 902                         evo_data(push, 0x00000000);
 903                         evo_mthd(push, 0x0080, 1);
 904                         evo_data(push, 0x00000000);
 905                         evo_kick(push, dev, 0);
 906                 }
 907
 908                 nv_encoder->crtc = NULL;
 909                 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 910         }
 911 }
 912
 913 static void
 914 nvd0_sor_destroy(struct drm_encoder *encoder)
 915 {
 916         drm_encoder_cleanup(encoder);
 917         kfree(encoder);
 918 }
 919
 920 static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
 921         .dpms = nvd0_sor_dpms,
 922         .mode_fixup = nvd0_sor_mode_fixup,
 923         .prepare = nvd0_sor_prepare,
 924         .commit = nvd0_sor_commit,
 925         .mode_set = nvd0_sor_mode_set,
 926         .disable = nvd0_sor_disconnect,
 927         .get_crtc = nvd0_display_crtc_get,
 928 };
 929
 930 static const struct drm_encoder_funcs nvd0_sor_func = {
 931         .destroy = nvd0_sor_destroy,
 932 };
 933
 934 static int
 935 nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
 936 {
 937         struct drm_device *dev = connector->dev;
 938         struct nouveau_encoder *nv_encoder;
 939         struct drm_encoder *encoder;
 940
 941         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 942         if (!nv_encoder)
 943                 return -ENOMEM;
 944         nv_encoder->dcb = dcbe;
 945         nv_encoder->or = ffs(dcbe->or) - 1;
 946         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 947
 948         encoder = to_drm_encoder(nv_encoder);
 949         encoder->possible_crtcs = dcbe->heads;
 950         encoder->possible_clones = 0;
 951         drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
 952         drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
 953
 954         drm_mode_connector_attach_encoder(connector, encoder);
 955         return 0;
 956 }
 957
 958 /******************************************************************************
 959  * IRQ
 960  *****************************************************************************/
 961 static void
 962 debug_irq(struct drm_device *dev, int i)
 963 {
 964         if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
 965                 NV_INFO(dev, "PDISP: modeset req %d\n", i);
 966                 NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
 967                          nv_rd32(dev, 0x6101d0),
 968                          nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
 969                 for (i = 0; i < 8; i++) {
 970                         NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
 971                                 i < 4 ? "DAC" : "SOR", i,
 972                                 nv_rd32(dev, 0x640180 + (i * 0x20)),
 973                                 nv_rd32(dev, 0x660180 + (i * 0x20)));
 974                 }
 975         }
 976 }
 977
 978 static struct dcb_entry *
 979 lookup_dcb(struct drm_device *dev, int id, u32 mc)
 980 {
 981         struct drm_nouveau_private *dev_priv = dev->dev_private;
 982         int type, or, i;
 983
 984         if (id < 4) {
 985                 type = OUTPUT_ANALOG;
 986                 or   = id;
 987         } else {
 988                 switch (mc & 0x00000f00) {
 989                 case 0x00000000: type = OUTPUT_LVDS; break;
 990                 case 0x00000100: type = OUTPUT_TMDS; break;
 991                 case 0x00000200: type = OUTPUT_TMDS; break;
 992                 case 0x00000500: type = OUTPUT_TMDS; break;
 993                 default:
 994                         NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc);
 995                         return NULL;
 996                 }
 997
 998                 or = id - 4;
 999         }
1000
1001         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
1002                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
1003                 if (dcb->type == type && (dcb->or & (1 << or)))
1004                         return dcb;
1005         }
1006
1007         NV_ERROR(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
1008         return NULL;
1009 }
1010
1011 static void
1012 nvd0_display_unk1_handler(struct drm_device *dev)
1013 {
1014         struct dcb_entry *dcb;
1015         u32 mask, crtc;
1016         int i;
1017
1018         mask = nv_rd32(dev, 0x6101d4);
1019         crtc = 0;
1020         if (!mask) {
1021                 mask = nv_rd32(dev, 0x6109d4);
1022                 crtc = 1;
1023         }
1024         debug_irq(dev, 1);
1025
1026         for (i = 0; mask && i < 8; i++) {
1027                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1028                 if (!(mcc & (1 << crtc)))
1029                         continue;
1030
1031                 dcb = lookup_dcb(dev, i, mcc);
1032                 if (!dcb)
1033                         continue;
1034
1035                 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
1036         }
1037
1038         nv_wr32(dev, 0x6101d4, 0x00000000);
1039         nv_wr32(dev, 0x6109d4, 0x00000000);
1040         nv_wr32(dev, 0x6101d0, 0x80000000);
1041 }
1042
1043 static void
1044 nvd0_display_unk2_handler(struct drm_device *dev)
1045 {
1046         struct dcb_entry *dcb;
1047         u32 mask, crtc, pclk;
1048         u32 or, tmp;
1049         int i;
1050
1051         mask = nv_rd32(dev, 0x6101d4);
1052         crtc = 0;
1053         if (!mask) {
1054                 mask = nv_rd32(dev, 0x6109d4);
1055                 crtc = 1;
1056         }
1057         debug_irq(dev, 2);
1058
1059         for (i = 0; mask && i < 8; i++) {
1060                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1061                 if (!(mcc & (1 << crtc)))
1062                         continue;
1063
1064                 dcb = lookup_dcb(dev, i, mcc);
1065                 if (!dcb)
1066                         continue;
1067
1068                 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1069         }
1070
1071         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1072         if (mask & 0x00010000) {
1073                 nv50_crtc_set_clock(dev, crtc, pclk);
1074         }
1075
1076         for (i = 0; mask && i < 8; i++) {
1077                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1078                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1079                 if (!(mcp & (1 << crtc)))
1080                         continue;
1081
1082                 dcb = lookup_dcb(dev, i, mcp);
1083                 if (!dcb)
1084                         continue;
1085                 or = ffs(dcb->or) - 1;
1086
1087                 nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc);
1088
1089                 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1090                 switch (dcb->type) {
1091                 case OUTPUT_ANALOG:
1092                         nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1093                         break;
1094                 case OUTPUT_TMDS:
1095                 case OUTPUT_LVDS:
1096                         if (cfg & 0x00000100)
1097                                 tmp = 0x00000101;
1098                         else
1099                                 tmp = 0x00000000;
1100
1101                         nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
1102                         break;
1103                 default:
1104                         break;
1105                 }
1106
1107                 break;
1108         }
1109
1110         nv_wr32(dev, 0x6101d4, 0x00000000);
1111         nv_wr32(dev, 0x6109d4, 0x00000000);
1112         nv_wr32(dev, 0x6101d0, 0x80000000);
1113 }
1114
1115 static void
1116 nvd0_display_unk4_handler(struct drm_device *dev)
1117 {
1118         struct dcb_entry *dcb;
1119         u32 mask, crtc;
1120         int pclk, i;
1121
1122         mask = nv_rd32(dev, 0x6101d4);
1123         crtc = 0;
1124         if (!mask) {
1125                 mask = nv_rd32(dev, 0x6109d4);
1126                 crtc = 1;
1127         }
1128         debug_irq(dev, 4);
1129
1130         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1131
1132         for (i = 0; mask && i < 8; i++) {
1133                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1134                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1135                 if (!(mcp & (1 << crtc)))
1136                         continue;
1137
1138                 dcb = lookup_dcb(dev, i, mcp);
1139                 if (!dcb)
1140                         continue;
1141
1142                 nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc);
1143         }
1144
1145         nv_wr32(dev, 0x6101d4, 0x00000000);
1146         nv_wr32(dev, 0x6109d4, 0x00000000);
1147         nv_wr32(dev, 0x6101d0, 0x80000000);
1148 }
1149
1150 static void
1151 nvd0_display_bh(unsigned long data)
1152 {
1153         struct drm_device *dev = (struct drm_device *)data;
1154         struct nvd0_display *disp = nvd0_display(dev);
1155
1156         if (disp->modeset & 0x00000001)
1157                 nvd0_display_unk1_handler(dev);
1158         if (disp->modeset & 0x00000002)
1159                 nvd0_display_unk2_handler(dev);
1160         if (disp->modeset & 0x00000004)
1161                 nvd0_display_unk4_handler(dev);
1162 }
1163
1164 static void
1165 nvd0_display_intr(struct drm_device *dev)
1166 {
1167         struct nvd0_display *disp = nvd0_display(dev);
1168         u32 intr = nv_rd32(dev, 0x610088);
1169
1170         if (intr & 0x00000002) {
1171                 u32 stat = nv_rd32(dev, 0x61009c);
1172                 int chid = ffs(stat) - 1;
1173                 if (chid >= 0) {
1174                         u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1175                         u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1176                         u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1177
1178                         NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1179                                      "0x%08x 0x%08x\n",
1180                                 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1181                         nv_wr32(dev, 0x61009c, (1 << chid));
1182                         nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1183                 }
1184
1185                 intr &= ~0x00000002;
1186         }
1187
1188         if (intr & 0x00100000) {
1189                 u32 stat = nv_rd32(dev, 0x6100ac);
1190
1191                 if (stat & 0x00000007) {
1192                         disp->modeset = stat;
1193                         tasklet_schedule(&disp->tasklet);
1194
1195                         nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1196                         stat &= ~0x00000007;
1197                 }
1198
1199                 if (stat) {
1200                         NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1201                         nv_wr32(dev, 0x6100ac, stat);
1202                 }
1203
1204                 intr &= ~0x00100000;
1205         }
1206
1207         if (intr & 0x01000000) {
1208                 u32 stat = nv_rd32(dev, 0x6100bc);
1209                 nv_wr32(dev, 0x6100bc, stat);
1210                 intr &= ~0x01000000;
1211         }
1212
1213         if (intr & 0x02000000) {
1214                 u32 stat = nv_rd32(dev, 0x6108bc);
1215                 nv_wr32(dev, 0x6108bc, stat);
1216                 intr &= ~0x02000000;
1217         }
1218
1219         if (intr)
1220                 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1221 }
1222
1223 /******************************************************************************
1224  * Init
1225  *****************************************************************************/
1226 static void
1227 nvd0_display_fini(struct drm_device *dev)
1228 {
1229         int i;
1230
1231         /* fini cursors */
1232         for (i = 14; i >= 13; i--) {
1233                 if (!(nv_rd32(dev, 0x610490 + (i * 0x10)) & 0x00000001))
1234                         continue;
1235
1236                 nv_mask(dev, 0x610490 + (i * 0x10), 0x00000001, 0x00000000);
1237                 nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00000000);
1238                 nv_mask(dev, 0x610090, 1 << i, 0x00000000);
1239                 nv_mask(dev, 0x6100a0, 1 << i, 0x00000000);
1240         }
1241
1242         /* fini master */
1243         if (nv_rd32(dev, 0x610490) & 0x00000010) {
1244                 nv_mask(dev, 0x610490, 0x00000010, 0x00000000);
1245                 nv_mask(dev, 0x610490, 0x00000003, 0x00000000);
1246                 nv_wait(dev, 0x610490, 0x80000000, 0x00000000);
1247                 nv_mask(dev, 0x610090, 0x00000001, 0x00000000);
1248                 nv_mask(dev, 0x6100a0, 0x00000001, 0x00000000);
1249         }
1250 }
1251
1252 int
1253 nvd0_display_init(struct drm_device *dev)
1254 {
1255         struct nvd0_display *disp = nvd0_display(dev);
1256         u32 *push;
1257         int i;
1258
1259         if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1260                 nv_wr32(dev, 0x6100ac, 0x00000100);
1261                 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1262                 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1263                         NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1264                                  nv_rd32(dev, 0x6194e8));
1265                         return -EBUSY;
1266                 }
1267         }
1268
1269         /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1270          * work at all unless you do the SOR part below.
1271          */
1272         for (i = 0; i < 3; i++) {
1273                 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1274                 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1275         }
1276
1277         for (i = 0; i < 4; i++) {
1278                 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1279                 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1280         }
1281
1282         for (i = 0; i < 2; i++) {
1283                 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1284                 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1285                 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1286                 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1287                 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1288                 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
1289         }
1290
1291         /* point at our hash table / objects, enable interrupts */
1292         nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
1293         nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
1294
1295         /* init master */
1296         nv_wr32(dev, 0x610494, (disp->evo[0].handle >> 8) | 3);
1297         nv_wr32(dev, 0x610498, 0x00010000);
1298         nv_wr32(dev, 0x61049c, 0x00000001);
1299         nv_mask(dev, 0x610490, 0x00000010, 0x00000010);
1300         nv_wr32(dev, 0x640000, 0x00000000);
1301         nv_wr32(dev, 0x610490, 0x01000013);
1302         if (!nv_wait(dev, 0x610490, 0x80000000, 0x00000000)) {
1303                 NV_ERROR(dev, "PDISP: master 0x%08x\n",
1304                          nv_rd32(dev, 0x610490));
1305                 return -EBUSY;
1306         }
1307         nv_mask(dev, 0x610090, 0x00000001, 0x00000001);
1308         nv_mask(dev, 0x6100a0, 0x00000001, 0x00000001);
1309
1310         /* init cursors */
1311         for (i = 13; i <= 14; i++) {
1312                 nv_wr32(dev, 0x610490 + (i * 0x10), 0x00000001);
1313                 if (!nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00010000)) {
1314                         NV_ERROR(dev, "PDISP: curs%d 0x%08x\n", i,
1315                                  nv_rd32(dev, 0x610490 + (i * 0x10)));
1316                         return -EBUSY;
1317                 }
1318
1319                 nv_mask(dev, 0x610090, 1 << i, 1 << i);
1320                 nv_mask(dev, 0x6100a0, 1 << i, 1 << i);
1321         }
1322
1323         push = evo_wait(dev, 0, 32);
1324         if (!push)
1325                 return -EBUSY;
1326         evo_mthd(push, 0x0088, 1);
1327         evo_data(push, MEM_SYNC);
1328         evo_mthd(push, 0x0084, 1);
1329         evo_data(push, 0x00000000);
1330         evo_mthd(push, 0x0084, 1);
1331         evo_data(push, 0x80000000);
1332         evo_mthd(push, 0x008c, 1);
1333         evo_data(push, 0x00000000);
1334         evo_kick(push, dev, 0);
1335
1336         return 0;
1337 }
1338
1339 void
1340 nvd0_display_destroy(struct drm_device *dev)
1341 {
1342         struct drm_nouveau_private *dev_priv = dev->dev_private;
1343         struct nvd0_display *disp = nvd0_display(dev);
1344         struct pci_dev *pdev = dev->pdev;
1345
1346         nvd0_display_fini(dev);
1347
1348         pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
1349         nouveau_gpuobj_ref(NULL, &disp->mem);
1350         nouveau_irq_unregister(dev, 26);
1351
1352         dev_priv->engine.display.priv = NULL;
1353         kfree(disp);
1354 }
1355
1356 int
1357 nvd0_display_create(struct drm_device *dev)
1358 {
1359         struct drm_nouveau_private *dev_priv = dev->dev_private;
1360         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
1361         struct dcb_table *dcb = &dev_priv->vbios.dcb;
1362         struct drm_connector *connector, *tmp;
1363         struct pci_dev *pdev = dev->pdev;
1364         struct nvd0_display *disp;
1365         struct dcb_entry *dcbe;
1366         int ret, i;
1367
1368         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1369         if (!disp)
1370                 return -ENOMEM;
1371         dev_priv->engine.display.priv = disp;
1372
1373         /* create crtc objects to represent the hw heads */
1374         for (i = 0; i < 2; i++) {
1375                 ret = nvd0_crtc_create(dev, i);
1376                 if (ret)
1377                         goto out;
1378         }
1379
1380         /* create encoder/connector objects based on VBIOS DCB table */
1381         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1382                 connector = nouveau_connector_create(dev, dcbe->connector);
1383                 if (IS_ERR(connector))
1384                         continue;
1385
1386                 if (dcbe->location != DCB_LOC_ON_CHIP) {
1387                         NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1388                                 dcbe->type, ffs(dcbe->or) - 1);
1389                         continue;
1390                 }
1391
1392                 switch (dcbe->type) {
1393                 case OUTPUT_TMDS:
1394                 case OUTPUT_LVDS:
1395                         nvd0_sor_create(connector, dcbe);
1396                         break;
1397                 case OUTPUT_ANALOG:
1398                         nvd0_dac_create(connector, dcbe);
1399                         break;
1400                 default:
1401                         NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
1402                                 dcbe->type, ffs(dcbe->or) - 1);
1403                         continue;
1404                 }
1405         }
1406
1407         /* cull any connectors we created that don't have an encoder */
1408         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
1409                 if (connector->encoder_ids[0])
1410                         continue;
1411
1412                 NV_WARN(dev, "%s has no encoders, removing\n",
1413                         drm_get_connector_name(connector));
1414                 connector->funcs->destroy(connector);
1415         }
1416
1417         /* setup interrupt handling */
1418         tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev);
1419         nouveau_irq_register(dev, 26, nvd0_display_intr);
1420
1421         /* hash table and dma objects for the memory areas we care about */
1422         ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
1423                                  NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
1424         if (ret)
1425                 goto out;
1426
1427         nv_wo32(disp->mem, 0x1000, 0x00000049);
1428         nv_wo32(disp->mem, 0x1004, (disp->mem->vinst + 0x2000) >> 8);
1429         nv_wo32(disp->mem, 0x1008, (disp->mem->vinst + 0x2fff) >> 8);
1430         nv_wo32(disp->mem, 0x100c, 0x00000000);
1431         nv_wo32(disp->mem, 0x1010, 0x00000000);
1432         nv_wo32(disp->mem, 0x1014, 0x00000000);
1433         nv_wo32(disp->mem, 0x0000, MEM_SYNC);
1434         nv_wo32(disp->mem, 0x0004, (0x1000 << 9) | 0x00000001);
1435
1436         nv_wo32(disp->mem, 0x1020, 0x00000049);
1437         nv_wo32(disp->mem, 0x1024, 0x00000000);
1438         nv_wo32(disp->mem, 0x1028, (dev_priv->vram_size - 1) >> 8);
1439         nv_wo32(disp->mem, 0x102c, 0x00000000);
1440         nv_wo32(disp->mem, 0x1030, 0x00000000);
1441         nv_wo32(disp->mem, 0x1034, 0x00000000);
1442         nv_wo32(disp->mem, 0x0008, MEM_VRAM);
1443         nv_wo32(disp->mem, 0x000c, (0x1020 << 9) | 0x00000001);
1444
1445         nv_wo32(disp->mem, 0x1040, 0x00000009);
1446         nv_wo32(disp->mem, 0x1044, 0x00000000);
1447         nv_wo32(disp->mem, 0x1048, (dev_priv->vram_size - 1) >> 8);
1448         nv_wo32(disp->mem, 0x104c, 0x00000000);
1449         nv_wo32(disp->mem, 0x1050, 0x00000000);
1450         nv_wo32(disp->mem, 0x1054, 0x00000000);
1451         nv_wo32(disp->mem, 0x0010, NvEvoVRAM_LP);
1452         nv_wo32(disp->mem, 0x0014, (0x1040 << 9) | 0x00000001);
1453
1454         nv_wo32(disp->mem, 0x1060, 0x0fe00009);
1455         nv_wo32(disp->mem, 0x1064, 0x00000000);
1456         nv_wo32(disp->mem, 0x1068, (dev_priv->vram_size - 1) >> 8);
1457         nv_wo32(disp->mem, 0x106c, 0x00000000);
1458         nv_wo32(disp->mem, 0x1070, 0x00000000);
1459         nv_wo32(disp->mem, 0x1074, 0x00000000);
1460         nv_wo32(disp->mem, 0x0018, NvEvoFB32);
1461         nv_wo32(disp->mem, 0x001c, (0x1060 << 9) | 0x00000001);
1462
1463         pinstmem->flush(dev);
1464
1465         /* push buffers for evo channels */
1466         disp->evo[0].ptr =
1467                 pci_alloc_consistent(pdev, PAGE_SIZE, &disp->evo[0].handle);
1468         if (!disp->evo[0].ptr) {
1469                 ret = -ENOMEM;
1470                 goto out;
1471         }
1472
1473         ret = nvd0_display_init(dev);
1474         if (ret)
1475                 goto out;
1476
1477 out:
1478         if (ret)
1479                 nvd0_display_destroy(dev);
1480         return ret;
1481 }