drivers/gpu/drm/nouveau/nvd0_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_encoder.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_fb.h"
  35 #include "nv50_display.h"
  36
  37 #define MEM_SYNC 0xe0000001
  38 #define MEM_VRAM 0xe0010000
  39 #include "nouveau_dma.h"
  40
  41 struct nvd0_display {
  42         struct nouveau_gpuobj *mem;
  43         struct {
  44                 dma_addr_t handle;
  45                 u32 *ptr;
  46         } evo[1];
  47         struct {
  48                 struct dcb_entry *dis;
  49                 struct dcb_entry *ena;
  50                 int crtc;
  51                 int pclk;
  52                 u16 script;
  53         } irq;
  54 };
  55
  56 static struct nvd0_display *
  57 nvd0_display(struct drm_device *dev)
  58 {
  59         struct drm_nouveau_private *dev_priv = dev->dev_private;
  60         return dev_priv->engine.display.priv;
  61 }
  62
  63 static int
  64 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
  65 {
  66         int ret = 0;
  67         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
  68         nv_wr32(dev, 0x610704 + (id * 0x10), data);
  69         nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
  70         if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
  71                 ret = -EBUSY;
  72         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
  73         return ret;
  74 }
  75
  76 static u32 *
  77 evo_wait(struct drm_device *dev, int id, int nr)
  78 {
  79         struct nvd0_display *disp = nvd0_display(dev);
  80         u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
  81
  82         if (put + nr >= (PAGE_SIZE / 4)) {
  83                 disp->evo[id].ptr[put] = 0x20000000;
  84
  85                 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
  86                 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
  87                         NV_ERROR(dev, "evo %d dma stalled\n", id);
  88                         return NULL;
  89                 }
  90
  91                 put = 0;
  92         }
  93
  94         return disp->evo[id].ptr + put;
  95 }
  96
  97 static void
  98 evo_kick(u32 *push, struct drm_device *dev, int id)
  99 {
 100         struct nvd0_display *disp = nvd0_display(dev);
 101         nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
 102 }
 103
 104 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 105 #define evo_data(p,d)   *((p)++) = (d)
 106
 107 static struct drm_crtc *
 108 nvd0_display_crtc_get(struct drm_encoder *encoder)
 109 {
 110         return nouveau_encoder(encoder)->crtc;
 111 }
 112
 113 /******************************************************************************
 114  * CRTC
 115  *****************************************************************************/
 116 static int
 117 nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
 118 {
 119         struct drm_device *dev = nv_crtc->base.dev;
 120         u32 *push, mode;
 121
 122         mode = 0x00000000;
 123         if (on) {
 124                 /* 0x11: 6bpc dynamic 2x2
 125                  * 0x13: 8bpc dynamic 2x2
 126                  * 0x19: 6bpc static 2x2
 127                  * 0x1b: 8bpc static 2x2
 128                  * 0x21: 6bpc temporal
 129                  * 0x23: 8bpc temporal
 130                  */
 131                 mode = 0x00000011;
 132         }
 133
 134         push = evo_wait(dev, 0, 4);
 135         if (push) {
 136                 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x300), 1);
 137                 evo_data(push, mode);
 138                 if (update) {
 139                         evo_mthd(push, 0x0080, 1);
 140                         evo_data(push, 0x00000000);
 141                 }
 142                 evo_kick(push, dev, 0);
 143         }
 144
 145         return 0;
 146 }
 147
 148 static int
 149 nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, int type, bool update)
 150 {
 151         struct drm_display_mode *mode = &nv_crtc->base.mode;
 152         struct drm_device *dev = nv_crtc->base.dev;
 153         u32 *push;
 154
 155         /*XXX: actually handle scaling */
 156
 157         push = evo_wait(dev, 0, 16);
 158         if (push) {
 159                 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 160                 evo_data(push, (mode->vdisplay << 16) | mode->hdisplay);
 161                 evo_data(push, (mode->vdisplay << 16) | mode->hdisplay);
 162                 evo_data(push, (mode->vdisplay << 16) | mode->hdisplay);
 163                 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 164                 evo_data(push, 0x00000000);
 165                 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 166                 evo_data(push, 0x00000000);
 167                 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 168                 evo_data(push, (mode->vdisplay << 16) | mode->hdisplay);
 169                 if (update) {
 170                         evo_mthd(push, 0x0080, 1);
 171                         evo_data(push, 0x00000000);
 172                 }
 173                 evo_kick(push, dev, 0);
 174         }
 175
 176         return 0;
 177 }
 178
 179 static int
 180 nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 181                     int x, int y, bool update)
 182 {
 183         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 184         u32 *push;
 185
 186         push = evo_wait(fb->dev, 0, 16);
 187         if (push) {
 188                 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 189                 evo_data(push, nvfb->nvbo->bo.offset >> 8);
 190                 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 191                 evo_data(push, (fb->height << 16) | fb->width);
 192                 evo_data(push, nvfb->r_pitch);
 193                 evo_data(push, nvfb->r_format);
 194                 evo_data(push, nvfb->r_dma);
 195                 if (update) {
 196                         evo_mthd(push, 0x0080, 1);
 197                         evo_data(push, 0x00000000);
 198                 }
 199                 evo_kick(push, fb->dev, 0);
 200         }
 201
 202         nv_crtc->fb.tile_flags = nvfb->r_dma;
 203         return 0;
 204 }
 205
 206 static void
 207 nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
 208 {
 209         struct drm_device *dev = nv_crtc->base.dev;
 210         u32 *push = evo_wait(dev, 0, 16);
 211         if (push) {
 212                 if (show) {
 213                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 214                         evo_data(push, 0x85000000);
 215                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 216                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 217                         evo_data(push, MEM_VRAM);
 218                 } else {
 219                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 220                         evo_data(push, 0x05000000);
 221                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 222                         evo_data(push, 0x00000000);
 223                 }
 224
 225                 if (update) {
 226                         evo_mthd(push, 0x0080, 1);
 227                         evo_data(push, 0x00000000);
 228                 }
 229
 230                 evo_kick(push, dev, 0);
 231         }
 232 }
 233
 234 static void
 235 nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
 236 {
 237 }
 238
 239 static void
 240 nvd0_crtc_prepare(struct drm_crtc *crtc)
 241 {
 242         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 243         u32 *push;
 244
 245         push = evo_wait(crtc->dev, 0, 2);
 246         if (push) {
 247                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 248                 evo_data(push, 0x00000000);
 249                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 250                 evo_data(push, 0x03000000);
 251                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 252                 evo_data(push, 0x00000000);
 253                 evo_kick(push, crtc->dev, 0);
 254         }
 255
 256         nvd0_crtc_cursor_show(nv_crtc, false, false);
 257 }
 258
 259 static void
 260 nvd0_crtc_commit(struct drm_crtc *crtc)
 261 {
 262         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 263         u32 *push;
 264
 265         push = evo_wait(crtc->dev, 0, 32);
 266         if (push) {
 267                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 268                 evo_data(push, nv_crtc->fb.tile_flags);
 269                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 270                 evo_data(push, 0x83000000);
 271                 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 272                 evo_data(push, 0x00000000);
 273                 evo_data(push, 0x00000000);
 274                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 275                 evo_data(push, MEM_VRAM);
 276                 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 277                 evo_data(push, 0xffffff00);
 278                 evo_kick(push, crtc->dev, 0);
 279         }
 280
 281         nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
 282 }
 283
 284 static bool
 285 nvd0_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
 286                      struct drm_display_mode *adjusted_mode)
 287 {
 288         return true;
 289 }
 290
 291 static int
 292 nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 293 {
 294         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 295         int ret;
 296
 297         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 298         if (ret)
 299                 return ret;
 300
 301         if (old_fb) {
 302                 nvfb = nouveau_framebuffer(old_fb);
 303                 nouveau_bo_unpin(nvfb->nvbo);
 304         }
 305
 306         return 0;
 307 }
 308
 309 static int
 310 nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 311                    struct drm_display_mode *mode, int x, int y,
 312                    struct drm_framebuffer *old_fb)
 313 {
 314         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 315         struct nouveau_connector *nv_connector;
 316         u32 htotal = mode->htotal;
 317         u32 vtotal = mode->vtotal;
 318         u32 hsyncw = mode->hsync_end - mode->hsync_start - 1;
 319         u32 vsyncw = mode->vsync_end - mode->vsync_start - 1;
 320         u32 hfrntp = mode->hsync_start - mode->hdisplay;
 321         u32 vfrntp = mode->vsync_start - mode->vdisplay;
 322         u32 hbackp = mode->htotal - mode->hsync_end;
 323         u32 vbackp = mode->vtotal - mode->vsync_end;
 324         u32 hss2be = hsyncw + hbackp;
 325         u32 vss2be = vsyncw + vbackp;
 326         u32 hss2de = htotal - hfrntp;
 327         u32 vss2de = vtotal - vfrntp;
 328         u32 hstart = 0;
 329         u32 vstart = 0;
 330         u32 *push;
 331         int ret;
 332
 333         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 334         if (ret)
 335                 return ret;
 336
 337         push = evo_wait(crtc->dev, 0, 64);
 338         if (push) {
 339                 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 5);
 340                 evo_data(push, (vstart << 16) | hstart);
 341                 evo_data(push, (vtotal << 16) | htotal);
 342                 evo_data(push, (vsyncw << 16) | hsyncw);
 343                 evo_data(push, (vss2be << 16) | hss2be);
 344                 evo_data(push, (vss2de << 16) | hss2de);
 345                 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 346                 evo_data(push, 0x00000000); /* ??? */
 347                 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 348                 evo_data(push, mode->clock * 1000);
 349                 evo_data(push, 0x00200000); /* ??? */
 350                 evo_data(push, mode->clock * 1000);
 351                 evo_mthd(push, 0x0408 + (nv_crtc->index * 0x300), 1);
 352                 evo_data(push, 0x31ec6000); /* ??? */
 353                 evo_kick(push, crtc->dev, 0);
 354         }
 355
 356         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 357         nvd0_crtc_set_dither(nv_crtc, nv_connector->use_dithering, false);
 358         nvd0_crtc_set_scale(nv_crtc, nv_connector->scaling_mode, false);
 359         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 360         return 0;
 361 }
 362
 363 static int
 364 nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 365                         struct drm_framebuffer *old_fb)
 366 {
 367         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 368         int ret;
 369
 370         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 371         if (ret)
 372                 return ret;
 373
 374         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 375         return 0;
 376 }
 377
 378 static int
 379 nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 380                                struct drm_framebuffer *fb, int x, int y,
 381                                enum mode_set_atomic state)
 382 {
 383         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 384         nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
 385         return 0;
 386 }
 387
 388 static void
 389 nvd0_crtc_lut_load(struct drm_crtc *crtc)
 390 {
 391         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 392         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 393         int i;
 394
 395         for (i = 0; i < 256; i++) {
 396                 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
 397                 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
 398                 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
 399         }
 400 }
 401
 402 static int
 403 nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 404                      uint32_t handle, uint32_t width, uint32_t height)
 405 {
 406         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 407         struct drm_device *dev = crtc->dev;
 408         struct drm_gem_object *gem;
 409         struct nouveau_bo *nvbo;
 410         bool visible = (handle != 0);
 411         int i, ret = 0;
 412
 413         if (visible) {
 414                 if (width != 64 || height != 64)
 415                         return -EINVAL;
 416
 417                 gem = drm_gem_object_lookup(dev, file_priv, handle);
 418                 if (unlikely(!gem))
 419                         return -ENOENT;
 420                 nvbo = nouveau_gem_object(gem);
 421
 422                 ret = nouveau_bo_map(nvbo);
 423                 if (ret == 0) {
 424                         for (i = 0; i < 64 * 64; i++) {
 425                                 u32 v = nouveau_bo_rd32(nvbo, i);
 426                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 427                         }
 428                         nouveau_bo_unmap(nvbo);
 429                 }
 430
 431                 drm_gem_object_unreference_unlocked(gem);
 432         }
 433
 434         if (visible != nv_crtc->cursor.visible) {
 435                 nvd0_crtc_cursor_show(nv_crtc, visible, true);
 436                 nv_crtc->cursor.visible = visible;
 437         }
 438
 439         return ret;
 440 }
 441
 442 static int
 443 nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 444 {
 445         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 446         const u32 data = (y << 16) | x;
 447
 448         nv_wr32(crtc->dev, 0x64d084 + (nv_crtc->index * 0x1000), data);
 449         nv_wr32(crtc->dev, 0x64d080 + (nv_crtc->index * 0x1000), 0x00000000);
 450         return 0;
 451 }
 452
 453 static void
 454 nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 455                     uint32_t start, uint32_t size)
 456 {
 457         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 458         u32 end = max(start + size, (u32)256);
 459         u32 i;
 460
 461         for (i = start; i < end; i++) {
 462                 nv_crtc->lut.r[i] = r[i];
 463                 nv_crtc->lut.g[i] = g[i];
 464                 nv_crtc->lut.b[i] = b[i];
 465         }
 466
 467         nvd0_crtc_lut_load(crtc);
 468 }
 469
 470 static void
 471 nvd0_crtc_destroy(struct drm_crtc *crtc)
 472 {
 473         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 474         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 475         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 476         nouveau_bo_unmap(nv_crtc->lut.nvbo);
 477         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 478         drm_crtc_cleanup(crtc);
 479         kfree(crtc);
 480 }
 481
 482 static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
 483         .dpms = nvd0_crtc_dpms,
 484         .prepare = nvd0_crtc_prepare,
 485         .commit = nvd0_crtc_commit,
 486         .mode_fixup = nvd0_crtc_mode_fixup,
 487         .mode_set = nvd0_crtc_mode_set,
 488         .mode_set_base = nvd0_crtc_mode_set_base,
 489         .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
 490         .load_lut = nvd0_crtc_lut_load,
 491 };
 492
 493 static const struct drm_crtc_funcs nvd0_crtc_func = {
 494         .cursor_set = nvd0_crtc_cursor_set,
 495         .cursor_move = nvd0_crtc_cursor_move,
 496         .gamma_set = nvd0_crtc_gamma_set,
 497         .set_config = drm_crtc_helper_set_config,
 498         .destroy = nvd0_crtc_destroy,
 499 };
 500
 501 static int
 502 nvd0_crtc_create(struct drm_device *dev, int index)
 503 {
 504         struct nouveau_crtc *nv_crtc;
 505         struct drm_crtc *crtc;
 506         int ret, i;
 507
 508         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
 509         if (!nv_crtc)
 510                 return -ENOMEM;
 511
 512         nv_crtc->index = index;
 513         nv_crtc->set_dither = nvd0_crtc_set_dither;
 514         nv_crtc->set_scale = nvd0_crtc_set_scale;
 515         for (i = 0; i < 256; i++) {
 516                 nv_crtc->lut.r[i] = i << 8;
 517                 nv_crtc->lut.g[i] = i << 8;
 518                 nv_crtc->lut.b[i] = i << 8;
 519         }
 520
 521         crtc = &nv_crtc->base;
 522         drm_crtc_init(dev, crtc, &nvd0_crtc_func);
 523         drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
 524         drm_mode_crtc_set_gamma_size(crtc, 256);
 525
 526         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 527                              0, 0x0000, &nv_crtc->cursor.nvbo);
 528         if (!ret) {
 529                 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
 530                 if (!ret)
 531                         ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
 532                 if (ret)
 533                         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 534         }
 535
 536         if (ret)
 537                 goto out;
 538
 539         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 540                              0, 0x0000, &nv_crtc->lut.nvbo);
 541         if (!ret) {
 542                 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
 543                 if (!ret)
 544                         ret = nouveau_bo_map(nv_crtc->lut.nvbo);
 545                 if (ret)
 546                         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 547         }
 548
 549         if (ret)
 550                 goto out;
 551
 552         nvd0_crtc_lut_load(crtc);
 553
 554 out:
 555         if (ret)
 556                 nvd0_crtc_destroy(crtc);
 557         return ret;
 558 }
 559
 560 /******************************************************************************
 561  * DAC
 562  *****************************************************************************/
 563 static void
 564 nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
 565 {
 566         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 567         struct drm_device *dev = encoder->dev;
 568         int or = nv_encoder->or;
 569         u32 dpms_ctrl;
 570
 571         dpms_ctrl = 0x80000000;
 572         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 573                 dpms_ctrl |= 0x00000001;
 574         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 575                 dpms_ctrl |= 0x00000004;
 576
 577         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 578         nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
 579         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 580 }
 581
 582 static bool
 583 nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 584                     struct drm_display_mode *adjusted_mode)
 585 {
 586         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 587         struct nouveau_connector *nv_connector;
 588
 589         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 590         if (nv_connector && nv_connector->native_mode) {
 591                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 592                         int id = adjusted_mode->base.id;
 593                         *adjusted_mode = *nv_connector->native_mode;
 594                         adjusted_mode->base.id = id;
 595                 }
 596         }
 597
 598         return true;
 599 }
 600
 601 static void
 602 nvd0_dac_prepare(struct drm_encoder *encoder)
 603 {
 604 }
 605
 606 static void
 607 nvd0_dac_commit(struct drm_encoder *encoder)
 608 {
 609 }
 610
 611 static void
 612 nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 613                   struct drm_display_mode *adjusted_mode)
 614 {
 615         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 616         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 617         u32 *push;
 618
 619         nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 620
 621         push = evo_wait(encoder->dev, 0, 2);
 622         if (push) {
 623                 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
 624                 evo_data(push, 1 << nv_crtc->index);
 625                 evo_kick(push, encoder->dev, 0);
 626         }
 627
 628         nv_encoder->crtc = encoder->crtc;
 629 }
 630
 631 static void
 632 nvd0_dac_disconnect(struct drm_encoder *encoder)
 633 {
 634         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 635         struct drm_device *dev = encoder->dev;
 636         u32 *push;
 637
 638         if (nv_encoder->crtc) {
 639                 nvd0_crtc_prepare(nv_encoder->crtc);
 640
 641                 push = evo_wait(dev, 0, 4);
 642                 if (push) {
 643                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
 644                         evo_data(push, 0x00000000);
 645                         evo_mthd(push, 0x0080, 1);
 646                         evo_data(push, 0x00000000);
 647                         evo_kick(push, dev, 0);
 648                 }
 649
 650                 nv_encoder->crtc = NULL;
 651         }
 652 }
 653
 654 static enum drm_connector_status
 655 nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 656 {
 657         return connector_status_disconnected;
 658 }
 659
 660 static void
 661 nvd0_dac_destroy(struct drm_encoder *encoder)
 662 {
 663         drm_encoder_cleanup(encoder);
 664         kfree(encoder);
 665 }
 666
 667 static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
 668         .dpms = nvd0_dac_dpms,
 669         .mode_fixup = nvd0_dac_mode_fixup,
 670         .prepare = nvd0_dac_prepare,
 671         .commit = nvd0_dac_commit,
 672         .mode_set = nvd0_dac_mode_set,
 673         .disable = nvd0_dac_disconnect,
 674         .get_crtc = nvd0_display_crtc_get,
 675         .detect = nvd0_dac_detect
 676 };
 677
 678 static const struct drm_encoder_funcs nvd0_dac_func = {
 679         .destroy = nvd0_dac_destroy,
 680 };
 681
 682 static int
 683 nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe)
 684 {
 685         struct drm_device *dev = connector->dev;
 686         struct nouveau_encoder *nv_encoder;
 687         struct drm_encoder *encoder;
 688
 689         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 690         if (!nv_encoder)
 691                 return -ENOMEM;
 692         nv_encoder->dcb = dcbe;
 693         nv_encoder->or = ffs(dcbe->or) - 1;
 694
 695         encoder = to_drm_encoder(nv_encoder);
 696         encoder->possible_crtcs = dcbe->heads;
 697         encoder->possible_clones = 0;
 698         drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
 699         drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
 700
 701         drm_mode_connector_attach_encoder(connector, encoder);
 702         return 0;
 703 }
 704
 705 /******************************************************************************
 706  * SOR
 707  *****************************************************************************/
 708 static void
 709 nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
 710 {
 711         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 712         struct drm_device *dev = encoder->dev;
 713         struct drm_encoder *partner;
 714         int or = nv_encoder->or;
 715         u32 dpms_ctrl;
 716
 717         nv_encoder->last_dpms = mode;
 718
 719         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
 720                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
 721
 722                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
 723                         continue;
 724
 725                 if (nv_partner != nv_encoder &&
 726                     nv_partner->dcb->or == nv_encoder->or) {
 727                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
 728                                 return;
 729                         break;
 730                 }
 731         }
 732
 733         dpms_ctrl  = (mode == DRM_MODE_DPMS_ON);
 734         dpms_ctrl |= 0x80000000;
 735
 736         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
 737         nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
 738         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
 739         nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
 740 }
 741
 742 static bool
 743 nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 744                     struct drm_display_mode *adjusted_mode)
 745 {
 746         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 747         struct nouveau_connector *nv_connector;
 748
 749         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 750         if (nv_connector && nv_connector->native_mode) {
 751                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 752                         int id = adjusted_mode->base.id;
 753                         *adjusted_mode = *nv_connector->native_mode;
 754                         adjusted_mode->base.id = id;
 755                 }
 756         }
 757
 758         return true;
 759 }
 760
 761 static void
 762 nvd0_sor_prepare(struct drm_encoder *encoder)
 763 {
 764 }
 765
 766 static void
 767 nvd0_sor_commit(struct drm_encoder *encoder)
 768 {
 769 }
 770
 771 static void
 772 nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 773                   struct drm_display_mode *adjusted_mode)
 774 {
 775         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 776         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 777         u32 mode_ctrl = (1 << nv_crtc->index);
 778         u32 *push;
 779
 780         if (nv_encoder->dcb->sorconf.link & 1) {
 781                 if (adjusted_mode->clock < 165000)
 782                         mode_ctrl |= 0x00000100;
 783                 else
 784                         mode_ctrl |= 0x00000500;
 785         } else {
 786                 mode_ctrl |= 0x00000200;
 787         }
 788
 789         nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
 790
 791         push = evo_wait(encoder->dev, 0, 2);
 792         if (push) {
 793                 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
 794                 evo_data(push, mode_ctrl);
 795                 evo_kick(push, encoder->dev, 0);
 796         }
 797
 798         nv_encoder->crtc = encoder->crtc;
 799 }
 800
 801 static void
 802 nvd0_sor_disconnect(struct drm_encoder *encoder)
 803 {
 804         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 805         struct drm_device *dev = encoder->dev;
 806         u32 *push;
 807
 808         if (nv_encoder->crtc) {
 809                 nvd0_crtc_prepare(nv_encoder->crtc);
 810
 811                 push = evo_wait(dev, 0, 4);
 812                 if (push) {
 813                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
 814                         evo_data(push, 0x00000000);
 815                         evo_mthd(push, 0x0080, 1);
 816                         evo_data(push, 0x00000000);
 817                         evo_kick(push, dev, 0);
 818                 }
 819
 820                 nv_encoder->crtc = NULL;
 821                 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 822         }
 823 }
 824
 825 static void
 826 nvd0_sor_destroy(struct drm_encoder *encoder)
 827 {
 828         drm_encoder_cleanup(encoder);
 829         kfree(encoder);
 830 }
 831
 832 static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
 833         .dpms = nvd0_sor_dpms,
 834         .mode_fixup = nvd0_sor_mode_fixup,
 835         .prepare = nvd0_sor_prepare,
 836         .commit = nvd0_sor_commit,
 837         .mode_set = nvd0_sor_mode_set,
 838         .disable = nvd0_sor_disconnect,
 839         .get_crtc = nvd0_display_crtc_get,
 840 };
 841
 842 static const struct drm_encoder_funcs nvd0_sor_func = {
 843         .destroy = nvd0_sor_destroy,
 844 };
 845
 846 static int
 847 nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
 848 {
 849         struct drm_device *dev = connector->dev;
 850         struct nouveau_encoder *nv_encoder;
 851         struct drm_encoder *encoder;
 852
 853         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 854         if (!nv_encoder)
 855                 return -ENOMEM;
 856         nv_encoder->dcb = dcbe;
 857         nv_encoder->or = ffs(dcbe->or) - 1;
 858         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 859
 860         encoder = to_drm_encoder(nv_encoder);
 861         encoder->possible_crtcs = dcbe->heads;
 862         encoder->possible_clones = 0;
 863         drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
 864         drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
 865
 866         drm_mode_connector_attach_encoder(connector, encoder);
 867         return 0;
 868 }
 869
 870 /******************************************************************************
 871  * IRQ
 872  *****************************************************************************/
 873 static struct dcb_entry *
 874 lookup_dcb(struct drm_device *dev, int id, u32 mc)
 875 {
 876         struct drm_nouveau_private *dev_priv = dev->dev_private;
 877         int type, or, i;
 878
 879         if (id < 4) {
 880                 type = OUTPUT_ANALOG;
 881                 or   = id;
 882         } else {
 883                 type = OUTPUT_TMDS;
 884                 or   = id - 4;
 885         }
 886
 887         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 888                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 889                 if (dcb->type == type && (dcb->or & (1 << or)))
 890                         return dcb;
 891         }
 892
 893         NV_INFO(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
 894         return NULL;
 895 }
 896
 897 static void
 898 nvd0_display_unk1_handler(struct drm_device *dev)
 899 {
 900         struct nvd0_display *disp = nvd0_display(dev);
 901         struct dcb_entry *dcb;
 902         u32 unkn, crtc = 0;
 903         int i;
 904
 905         NV_INFO(dev, "PDISP: 1 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
 906                 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
 907
 908         unkn = nv_rd32(dev, 0x6101d4);
 909         if (!unkn) {
 910                 unkn = nv_rd32(dev, 0x6109d4);
 911                 crtc = 1;
 912         }
 913
 914         disp->irq.ena = NULL;
 915         disp->irq.dis = NULL;
 916         disp->irq.crtc = crtc;
 917         disp->irq.pclk = nv_rd32(dev, 0x660450 + (disp->irq.crtc * 0x300));
 918         disp->irq.pclk /= 1000;
 919
 920         for (i = 0; i < 8; i++) {
 921                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
 922                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
 923
 924                 if (mcc & (1 << crtc))
 925                         disp->irq.dis = lookup_dcb(dev, i, mcc);
 926
 927                 if (mcp & (1 << crtc)) {
 928                         disp->irq.ena = lookup_dcb(dev, i, mcp);
 929                         switch (disp->irq.ena->type) {
 930                         case OUTPUT_ANALOG:
 931                                 disp->irq.script = 0x00ff;
 932                                 break;
 933                         case OUTPUT_TMDS:
 934                                 disp->irq.script = (mcp & 0x00000f00) >> 8;
 935                                 if (disp->irq.pclk >= 165000)
 936                                         disp->irq.script |= 0x0100;
 937                                 break;
 938                         default:
 939                                 disp->irq.script = 0xbeef;
 940                                 break;
 941                         }
 942                 }
 943         }
 944
 945         dcb = disp->irq.dis;
 946         if (dcb)
 947                 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
 948
 949         nv_wr32(dev, 0x6101d4, 0x00000000);
 950         nv_wr32(dev, 0x6109d4, 0x00000000);
 951         nv_wr32(dev, 0x6101d0, 0x80000000);
 952 }
 953
 954 static void
 955 nvd0_display_unk2_handler(struct drm_device *dev)
 956 {
 957         struct nvd0_display *disp = nvd0_display(dev);
 958         struct dcb_entry *dcb;
 959         int crtc = disp->irq.crtc;
 960         int pclk = disp->irq.pclk;
 961         int or;
 962         u32 tmp;
 963
 964         NV_INFO(dev, "PDISP: 2 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
 965                 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
 966
 967         dcb = disp->irq.dis;
 968         disp->irq.dis = NULL;
 969         if (dcb)
 970                 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
 971
 972         nv50_crtc_set_clock(dev, crtc, pclk);
 973
 974         dcb = disp->irq.ena;
 975         if (!dcb)
 976                 goto ack;
 977         or = ffs(dcb->or) - 1;
 978
 979         nouveau_bios_run_display_table(dev, disp->irq.script, pclk, dcb, crtc);
 980
 981         nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
 982         switch (dcb->type) {
 983         case OUTPUT_ANALOG:
 984                 nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
 985                 break;
 986         case OUTPUT_TMDS:
 987                 if (disp->irq.pclk >= 165000)
 988                         tmp = 0x00000101;
 989                 else
 990                         tmp = 0x00000000;
 991
 992                 nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
 993                 break;
 994         default:
 995                 break;
 996         }
 997
 998 ack:
 999         nv_wr32(dev, 0x6101d4, 0x00000000);
1000         nv_wr32(dev, 0x6109d4, 0x00000000);
1001         nv_wr32(dev, 0x6101d0, 0x80000000);
1002 }
1003
1004 static void
1005 nvd0_display_unk4_handler(struct drm_device *dev)
1006 {
1007         struct nvd0_display *disp = nvd0_display(dev);
1008         struct dcb_entry *dcb;
1009         int crtc = disp->irq.crtc;
1010         int pclk = disp->irq.pclk;
1011
1012         NV_INFO(dev, "PDISP: 4 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
1013                 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
1014
1015         dcb = disp->irq.ena;
1016         disp->irq.ena = NULL;
1017         if (!dcb)
1018                 goto ack;
1019
1020         nouveau_bios_run_display_table(dev, disp->irq.script, pclk, dcb, crtc);
1021
1022 ack:
1023         nv_wr32(dev, 0x6101d4, 0x00000000);
1024         nv_wr32(dev, 0x6109d4, 0x00000000);
1025         nv_wr32(dev, 0x6101d0, 0x80000000);
1026 }
1027
1028 static void
1029 nvd0_display_intr(struct drm_device *dev)
1030 {
1031         u32 intr = nv_rd32(dev, 0x610088);
1032
1033         if (intr & 0x00000002) {
1034                 u32 stat = nv_rd32(dev, 0x61009c);
1035                 int chid = ffs(stat) - 1;
1036                 if (chid >= 0) {
1037                         u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1038                         u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1039                         u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1040
1041                         NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1042                                      "0x%08x 0x%08x\n",
1043                                 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1044                         nv_wr32(dev, 0x61009c, (1 << chid));
1045                         nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1046                 }
1047
1048                 intr &= ~0x00000002;
1049         }
1050
1051         if (intr & 0x00100000) {
1052                 u32 stat = nv_rd32(dev, 0x6100ac);
1053
1054                 if (stat & 0x00000007) {
1055                         nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1056
1057                         if (stat & 0x00000001)
1058                                 nvd0_display_unk1_handler(dev);
1059                         if (stat & 0x00000002)
1060                                 nvd0_display_unk2_handler(dev);
1061                         if (stat & 0x00000004)
1062                                 nvd0_display_unk4_handler(dev);
1063                         stat &= ~0x00000007;
1064                 }
1065
1066                 if (stat) {
1067                         NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1068                         nv_wr32(dev, 0x6100ac, stat);
1069                 }
1070
1071                 intr &= ~0x00100000;
1072         }
1073
1074         if (intr & 0x01000000) {
1075                 u32 stat = nv_rd32(dev, 0x6100bc);
1076                 nv_wr32(dev, 0x6100bc, stat);
1077                 intr &= ~0x01000000;
1078         }
1079
1080         if (intr & 0x02000000) {
1081                 u32 stat = nv_rd32(dev, 0x6108bc);
1082                 nv_wr32(dev, 0x6108bc, stat);
1083                 intr &= ~0x02000000;
1084         }
1085
1086         if (intr)
1087                 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1088 }
1089
1090 /******************************************************************************
1091  * Init
1092  *****************************************************************************/
1093 static void
1094 nvd0_display_fini(struct drm_device *dev)
1095 {
1096         int i;
1097
1098         /* fini cursors */
1099         for (i = 14; i >= 13; i--) {
1100                 if (!(nv_rd32(dev, 0x610490 + (i * 0x10)) & 0x00000001))
1101                         continue;
1102
1103                 nv_mask(dev, 0x610490 + (i * 0x10), 0x00000001, 0x00000000);
1104                 nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00000000);
1105                 nv_mask(dev, 0x610090, 1 << i, 0x00000000);
1106                 nv_mask(dev, 0x6100a0, 1 << i, 0x00000000);
1107         }
1108
1109         /* fini master */
1110         if (nv_rd32(dev, 0x610490) & 0x00000010) {
1111                 nv_mask(dev, 0x610490, 0x00000010, 0x00000000);
1112                 nv_mask(dev, 0x610490, 0x00000003, 0x00000000);
1113                 nv_wait(dev, 0x610490, 0x80000000, 0x00000000);
1114                 nv_mask(dev, 0x610090, 0x00000001, 0x00000000);
1115                 nv_mask(dev, 0x6100a0, 0x00000001, 0x00000000);
1116         }
1117 }
1118
1119 int
1120 nvd0_display_init(struct drm_device *dev)
1121 {
1122         struct nvd0_display *disp = nvd0_display(dev);
1123         u32 *push;
1124         int i;
1125
1126         if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1127                 nv_wr32(dev, 0x6100ac, 0x00000100);
1128                 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1129                 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1130                         NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1131                                  nv_rd32(dev, 0x6194e8));
1132                         return -EBUSY;
1133                 }
1134         }
1135
1136         /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1137          * work at all unless you do the SOR part below.
1138          */
1139         for (i = 0; i < 3; i++) {
1140                 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1141                 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1142         }
1143
1144         for (i = 0; i < 4; i++) {
1145                 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1146                 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1147         }
1148
1149         for (i = 0; i < 2; i++) {
1150                 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1151                 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1152                 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1153                 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1154                 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1155                 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
1156         }
1157
1158         /* point at our hash table / objects, enable interrupts */
1159         nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
1160         nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
1161
1162         /* init master */
1163         nv_wr32(dev, 0x610494, (disp->evo[0].handle >> 8) | 3);
1164         nv_wr32(dev, 0x610498, 0x00010000);
1165         nv_wr32(dev, 0x61049c, 0x00000001);
1166         nv_mask(dev, 0x610490, 0x00000010, 0x00000010);
1167         nv_wr32(dev, 0x640000, 0x00000000);
1168         nv_wr32(dev, 0x610490, 0x01000013);
1169         if (!nv_wait(dev, 0x610490, 0x80000000, 0x00000000)) {
1170                 NV_ERROR(dev, "PDISP: master 0x%08x\n",
1171                          nv_rd32(dev, 0x610490));
1172                 return -EBUSY;
1173         }
1174         nv_mask(dev, 0x610090, 0x00000001, 0x00000001);
1175         nv_mask(dev, 0x6100a0, 0x00000001, 0x00000001);
1176
1177         /* init cursors */
1178         for (i = 13; i <= 14; i++) {
1179                 nv_wr32(dev, 0x610490 + (i * 0x10), 0x00000001);
1180                 if (!nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00010000)) {
1181                         NV_ERROR(dev, "PDISP: curs%d 0x%08x\n", i,
1182                                  nv_rd32(dev, 0x610490 + (i * 0x10)));
1183                         return -EBUSY;
1184                 }
1185
1186                 nv_mask(dev, 0x610090, 1 << i, 1 << i);
1187                 nv_mask(dev, 0x6100a0, 1 << i, 1 << i);
1188         }
1189
1190         push = evo_wait(dev, 0, 32);
1191         if (!push)
1192                 return -EBUSY;
1193         evo_mthd(push, 0x0088, 1);
1194         evo_data(push, MEM_SYNC);
1195         evo_mthd(push, 0x0084, 1);
1196         evo_data(push, 0x00000000);
1197         evo_mthd(push, 0x0084, 1);
1198         evo_data(push, 0x80000000);
1199         evo_mthd(push, 0x008c, 1);
1200         evo_data(push, 0x00000000);
1201         evo_kick(push, dev, 0);
1202
1203         return 0;
1204 }
1205
1206 void
1207 nvd0_display_destroy(struct drm_device *dev)
1208 {
1209         struct drm_nouveau_private *dev_priv = dev->dev_private;
1210         struct nvd0_display *disp = nvd0_display(dev);
1211         struct pci_dev *pdev = dev->pdev;
1212
1213         nvd0_display_fini(dev);
1214
1215         pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
1216         nouveau_gpuobj_ref(NULL, &disp->mem);
1217         nouveau_irq_unregister(dev, 26);
1218
1219         dev_priv->engine.display.priv = NULL;
1220         kfree(disp);
1221 }
1222
1223 int
1224 nvd0_display_create(struct drm_device *dev)
1225 {
1226         struct drm_nouveau_private *dev_priv = dev->dev_private;
1227         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
1228         struct dcb_table *dcb = &dev_priv->vbios.dcb;
1229         struct drm_connector *connector, *tmp;
1230         struct pci_dev *pdev = dev->pdev;
1231         struct nvd0_display *disp;
1232         struct dcb_entry *dcbe;
1233         int ret, i;
1234
1235         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1236         if (!disp)
1237                 return -ENOMEM;
1238         dev_priv->engine.display.priv = disp;
1239
1240         /* create crtc objects to represent the hw heads */
1241         for (i = 0; i < 2; i++) {
1242                 ret = nvd0_crtc_create(dev, i);
1243                 if (ret)
1244                         goto out;
1245         }
1246
1247         /* create encoder/connector objects based on VBIOS DCB table */
1248         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1249                 connector = nouveau_connector_create(dev, dcbe->connector);
1250                 if (IS_ERR(connector))
1251                         continue;
1252
1253                 if (dcbe->location != DCB_LOC_ON_CHIP) {
1254                         NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1255                                 dcbe->type, ffs(dcbe->or) - 1);
1256                         continue;
1257                 }
1258
1259                 switch (dcbe->type) {
1260                 case OUTPUT_TMDS:
1261                         nvd0_sor_create(connector, dcbe);
1262                         break;
1263                 case OUTPUT_ANALOG:
1264                         nvd0_dac_create(connector, dcbe);
1265                         break;
1266                 default:
1267                         NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
1268                                 dcbe->type, ffs(dcbe->or) - 1);
1269                         continue;
1270                 }
1271         }
1272
1273         /* cull any connectors we created that don't have an encoder */
1274         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
1275                 if (connector->encoder_ids[0])
1276                         continue;
1277
1278                 NV_WARN(dev, "%s has no encoders, removing\n",
1279                         drm_get_connector_name(connector));
1280                 connector->funcs->destroy(connector);
1281         }
1282
1283         /* setup interrupt handling */
1284         nouveau_irq_register(dev, 26, nvd0_display_intr);
1285
1286         /* hash table and dma objects for the memory areas we care about */
1287         ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
1288                                  NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
1289         if (ret)
1290                 goto out;
1291
1292         nv_wo32(disp->mem, 0x1000, 0x00000049);
1293         nv_wo32(disp->mem, 0x1004, (disp->mem->vinst + 0x2000) >> 8);
1294         nv_wo32(disp->mem, 0x1008, (disp->mem->vinst + 0x2fff) >> 8);
1295         nv_wo32(disp->mem, 0x100c, 0x00000000);
1296         nv_wo32(disp->mem, 0x1010, 0x00000000);
1297         nv_wo32(disp->mem, 0x1014, 0x00000000);
1298         nv_wo32(disp->mem, 0x0000, MEM_SYNC);
1299         nv_wo32(disp->mem, 0x0004, (0x1000 << 9) | 0x00000001);
1300
1301         nv_wo32(disp->mem, 0x1020, 0x00000049);
1302         nv_wo32(disp->mem, 0x1024, 0x00000000);
1303         nv_wo32(disp->mem, 0x1028, (dev_priv->vram_size - 1) >> 8);
1304         nv_wo32(disp->mem, 0x102c, 0x00000000);
1305         nv_wo32(disp->mem, 0x1030, 0x00000000);
1306         nv_wo32(disp->mem, 0x1034, 0x00000000);
1307         nv_wo32(disp->mem, 0x0008, MEM_VRAM);
1308         nv_wo32(disp->mem, 0x000c, (0x1020 << 9) | 0x00000001);
1309
1310         nv_wo32(disp->mem, 0x1040, 0x00000009);
1311         nv_wo32(disp->mem, 0x1044, 0x00000000);
1312         nv_wo32(disp->mem, 0x1048, (dev_priv->vram_size - 1) >> 8);
1313         nv_wo32(disp->mem, 0x104c, 0x00000000);
1314         nv_wo32(disp->mem, 0x1050, 0x00000000);
1315         nv_wo32(disp->mem, 0x1054, 0x00000000);
1316         nv_wo32(disp->mem, 0x0010, NvEvoVRAM_LP);
1317         nv_wo32(disp->mem, 0x0014, (0x1040 << 9) | 0x00000001);
1318
1319         nv_wo32(disp->mem, 0x1060, 0x0fe00009);
1320         nv_wo32(disp->mem, 0x1064, 0x00000000);
1321         nv_wo32(disp->mem, 0x1068, (dev_priv->vram_size - 1) >> 8);
1322         nv_wo32(disp->mem, 0x106c, 0x00000000);
1323         nv_wo32(disp->mem, 0x1070, 0x00000000);
1324         nv_wo32(disp->mem, 0x1074, 0x00000000);
1325         nv_wo32(disp->mem, 0x0018, NvEvoFB32);
1326         nv_wo32(disp->mem, 0x001c, (0x1060 << 9) | 0x00000001);
1327
1328         pinstmem->flush(dev);
1329
1330         /* push buffers for evo channels */
1331         disp->evo[0].ptr =
1332                 pci_alloc_consistent(pdev, PAGE_SIZE, &disp->evo[0].handle);
1333         if (!disp->evo[0].ptr) {
1334                 ret = -ENOMEM;
1335                 goto out;
1336         }
1337
1338         ret = nvd0_display_init(dev);
1339         if (ret)
1340                 goto out;
1341
1342 out:
1343         if (ret)
1344                 nvd0_display_destroy(dev);
1345         return ret;
1346 }