drivers/gpu/drm/nouveau/nv50_instmem.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "nouveau_drv.h"
  31
  32 struct nv50_instmem_priv {
  33         uint32_t save1700[5]; /* 0x1700->0x1710 */
  34
  35         struct nouveau_gpuobj_ref *pramin_pt;
  36         struct nouveau_gpuobj_ref *pramin_bar;
  37         struct nouveau_gpuobj_ref *fb_bar;
  38
  39         bool last_access_wr;
  40 };
  41
  42 #define NV50_INSTMEM_PAGE_SHIFT 12
  43 #define NV50_INSTMEM_PAGE_SIZE  (1 << NV50_INSTMEM_PAGE_SHIFT)
  44 #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
  45
  46 /*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
  47  */
  48 #define BAR0_WI32(g, o, v) do {                                   \
  49         uint32_t offset;                                          \
  50         if ((g)->im_backing) {                                    \
  51                 offset = (g)->im_backing_start;                   \
  52         } else {                                                  \
  53                 offset  = chan->ramin->gpuobj->im_backing_start;  \
  54                 offset += (g)->im_pramin->start;                  \
  55         }                                                         \
  56         offset += (o);                                            \
  57         nv_wr32(dev, NV_RAMIN + (offset & 0xfffff), (v));              \
  58 } while (0)
  59
  60 int
  61 nv50_instmem_init(struct drm_device *dev)
  62 {
  63         struct drm_nouveau_private *dev_priv = dev->dev_private;
  64         struct nouveau_channel *chan;
  65         uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
  66         struct nv50_instmem_priv *priv;
  67         int ret, i;
  68         uint32_t v, save_nv001700;
  69
  70         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  71         if (!priv)
  72                 return -ENOMEM;
  73         dev_priv->engine.instmem.priv = priv;
  74
  75         /* Save state, will restore at takedown. */
  76         for (i = 0x1700; i <= 0x1710; i += 4)
  77                 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
  78
  79         if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
  80                 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
  81         else
  82                 dev_priv->vram_sys_base = 0;
  83
  84         /* Reserve the last MiB of VRAM, we should probably try to avoid
  85          * setting up the below tables over the top of the VBIOS image at
  86          * some point.
  87          */
  88         dev_priv->ramin_rsvd_vram = 1 << 20;
  89         c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram;
  90         c_size   = 128 << 10;
  91         c_vmpd   = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
  92         c_ramfc  = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
  93         c_base   = c_vmpd + 0x4000;
  94         pt_size  = NV50_INSTMEM_PT_SIZE(dev_priv->ramin_size);
  95
  96         NV_DEBUG(dev, " Rsvd VRAM base: 0x%08x\n", c_offset);
  97         NV_DEBUG(dev, "    VBIOS image: 0x%08x\n",
  98                                 (nv_rd32(dev, 0x619f04) & ~0xff) << 8);
  99         NV_DEBUG(dev, "  Aperture size: %d MiB\n", dev_priv->ramin_size >> 20);
 100         NV_DEBUG(dev, "        PT size: %d KiB\n", pt_size >> 10);
 101
 102         /* Determine VM layout, we need to do this first to make sure
 103          * we allocate enough memory for all the page tables.
 104          */
 105         dev_priv->vm_gart_base = roundup(NV50_VM_BLOCK, NV50_VM_BLOCK);
 106         dev_priv->vm_gart_size = NV50_VM_BLOCK;
 107
 108         dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size;
 109         dev_priv->vm_vram_size = nouveau_mem_fb_amount(dev);
 110         if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM)
 111                 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM;
 112         dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK);
 113         dev_priv->vm_vram_pt_nr = dev_priv->vm_vram_size / NV50_VM_BLOCK;
 114
 115         dev_priv->vm_end = dev_priv->vm_vram_base + dev_priv->vm_vram_size;
 116
 117         NV_DEBUG(dev, "NV50VM: GART 0x%016llx-0x%016llx\n",
 118                  dev_priv->vm_gart_base,
 119                  dev_priv->vm_gart_base + dev_priv->vm_gart_size - 1);
 120         NV_DEBUG(dev, "NV50VM: VRAM 0x%016llx-0x%016llx\n",
 121                  dev_priv->vm_vram_base,
 122                  dev_priv->vm_vram_base + dev_priv->vm_vram_size - 1);
 123
 124         c_size += dev_priv->vm_vram_pt_nr * (NV50_VM_BLOCK / 65536 * 8);
 125
 126         /* Map BAR0 PRAMIN aperture over the memory we want to use */
 127         save_nv001700 = nv_rd32(dev, NV50_PUNK_BAR0_PRAMIN);
 128         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
 129
 130         /* Create a fake channel, and use it as our "dummy" channels 0/127.
 131          * The main reason for creating a channel is so we can use the gpuobj
 132          * code.  However, it's probably worth noting that NVIDIA also setup
 133          * their channels 0/127 with the same values they configure here.
 134          * So, there may be some other reason for doing this.
 135          *
 136          * Have to create the entire channel manually, as the real channel
 137          * creation code assumes we have PRAMIN access, and we don't until
 138          * we're done here.
 139          */
 140         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
 141         if (!chan)
 142                 return -ENOMEM;
 143         chan->id = 0;
 144         chan->dev = dev;
 145         chan->file_priv = (struct drm_file *)-2;
 146         dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
 147
 148         /* Channel's PRAMIN object + heap */
 149         ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0,
 150                                                         NULL, &chan->ramin);
 151         if (ret)
 152                 return ret;
 153
 154         if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base))
 155                 return -ENOMEM;
 156
 157         /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
 158         ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
 159                                                 0x4000, 0, NULL, &chan->ramfc);
 160         if (ret)
 161                 return ret;
 162
 163         for (i = 0; i < c_vmpd; i += 4)
 164                 BAR0_WI32(chan->ramin->gpuobj, i, 0);
 165
 166         /* VM page directory */
 167         ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
 168                                            0x4000, 0, &chan->vm_pd, NULL);
 169         if (ret)
 170                 return ret;
 171         for (i = 0; i < 0x4000; i += 8) {
 172                 BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000);
 173                 BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000);
 174         }
 175
 176         /* PRAMIN page table, cheat and map into VM at 0x0000000000.
 177          * We map the entire fake channel into the start of the PRAMIN BAR
 178          */
 179         ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
 180                                      0, &priv->pramin_pt);
 181         if (ret)
 182                 return ret;
 183
 184         v = c_offset | 1;
 185         if (dev_priv->vram_sys_base) {
 186                 v += dev_priv->vram_sys_base;
 187                 v |= 0x30;
 188         }
 189
 190         i = 0;
 191         while (v < dev_priv->vram_sys_base + c_offset + c_size) {
 192                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v);
 193                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
 194                 v += 0x1000;
 195                 i += 8;
 196         }
 197
 198         while (i < pt_size) {
 199                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);
 200                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
 201                 i += 8;
 202         }
 203
 204         BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
 205         BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
 206
 207         /* VRAM page table(s), mapped into VM at +1GiB  */
 208         for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
 209                 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
 210                                              NV50_VM_BLOCK/65536*8, 0, 0,
 211                                              &chan->vm_vram_pt[i]);
 212                 if (ret) {
 213                         NV_ERROR(dev, "Error creating VRAM page tables: %d\n",
 214                                                                         ret);
 215                         dev_priv->vm_vram_pt_nr = i;
 216                         return ret;
 217                 }
 218                 dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i]->gpuobj;
 219
 220                 for (v = 0; v < dev_priv->vm_vram_pt[i]->im_pramin->size;
 221                                                                 v += 4)
 222                         BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0);
 223
 224                 BAR0_WI32(chan->vm_pd, 0x10 + (i*8),
 225                           chan->vm_vram_pt[i]->instance | 0x61);
 226                 BAR0_WI32(chan->vm_pd, 0x14 + (i*8), 0);
 227         }
 228
 229         /* DMA object for PRAMIN BAR */
 230         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
 231                                                         &priv->pramin_bar);
 232         if (ret)
 233                 return ret;
 234         BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000);
 235         BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin_size - 1);
 236         BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000);
 237         BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000);
 238         BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000);
 239         BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
 240
 241         /* DMA object for FB BAR */
 242         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
 243                                                         &priv->fb_bar);
 244         if (ret)
 245                 return ret;
 246         BAR0_WI32(priv->fb_bar->gpuobj, 0x00, 0x7fc00000);
 247         BAR0_WI32(priv->fb_bar->gpuobj, 0x04, 0x40000000 +
 248                                               drm_get_resource_len(dev, 1) - 1);
 249         BAR0_WI32(priv->fb_bar->gpuobj, 0x08, 0x40000000);
 250         BAR0_WI32(priv->fb_bar->gpuobj, 0x0c, 0x00000000);
 251         BAR0_WI32(priv->fb_bar->gpuobj, 0x10, 0x00000000);
 252         BAR0_WI32(priv->fb_bar->gpuobj, 0x14, 0x00000000);
 253
 254         /* Poke the relevant regs, and pray it works :) */
 255         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
 256         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 257         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
 258                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 259         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
 260                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 261         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
 262                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 263
 264         for (i = 0; i < 8; i++)
 265                 nv_wr32(dev, 0x1900 + (i*4), 0);
 266
 267         /* Assume that praying isn't enough, check that we can re-read the
 268          * entire fake channel back from the PRAMIN BAR */
 269         dev_priv->engine.instmem.prepare_access(dev, false);
 270         for (i = 0; i < c_size; i += 4) {
 271                 if (nv_rd32(dev, NV_RAMIN + i) != nv_ri32(dev, i)) {
 272                         NV_ERROR(dev, "Error reading back PRAMIN at 0x%08x\n",
 273                                                                         i);
 274                         dev_priv->engine.instmem.finish_access(dev);
 275                         return -EINVAL;
 276                 }
 277         }
 278         dev_priv->engine.instmem.finish_access(dev);
 279
 280         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, save_nv001700);
 281
 282         /* Global PRAMIN heap */
 283         if (nouveau_mem_init_heap(&dev_priv->ramin_heap,
 284                                   c_size, dev_priv->ramin_size - c_size)) {
 285                 dev_priv->ramin_heap = NULL;
 286                 NV_ERROR(dev, "Failed to init RAMIN heap\n");
 287         }
 288
 289         /*XXX: incorrect, but needed to make hash func "work" */
 290         dev_priv->ramht_offset = 0x10000;
 291         dev_priv->ramht_bits   = 9;
 292         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
 293         return 0;
 294 }
 295
 296 void
 297 nv50_instmem_takedown(struct drm_device *dev)
 298 {
 299         struct drm_nouveau_private *dev_priv = dev->dev_private;
 300         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 301         struct nouveau_channel *chan = dev_priv->fifos[0];
 302         int i;
 303
 304         NV_DEBUG(dev, "\n");
 305
 306         if (!priv)
 307                 return;
 308
 309         /* Restore state from before init */
 310         for (i = 0x1700; i <= 0x1710; i += 4)
 311                 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
 312
 313         nouveau_gpuobj_ref_del(dev, &priv->fb_bar);
 314         nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
 315         nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
 316
 317         /* Destroy dummy channel */
 318         if (chan) {
 319                 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
 320                         nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt[i]);
 321                         dev_priv->vm_vram_pt[i] = NULL;
 322                 }
 323                 dev_priv->vm_vram_pt_nr = 0;
 324
 325                 nouveau_gpuobj_del(dev, &chan->vm_pd);
 326                 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 327                 nouveau_gpuobj_ref_del(dev, &chan->ramin);
 328                 nouveau_mem_takedown(&chan->ramin_heap);
 329
 330                 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
 331                 kfree(chan);
 332         }
 333
 334         dev_priv->engine.instmem.priv = NULL;
 335         kfree(priv);
 336 }
 337
 338 int
 339 nv50_instmem_suspend(struct drm_device *dev)
 340 {
 341         struct drm_nouveau_private *dev_priv = dev->dev_private;
 342         struct nouveau_channel *chan = dev_priv->fifos[0];
 343         struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
 344         int i;
 345
 346         ramin->im_backing_suspend = vmalloc(ramin->im_pramin->size);
 347         if (!ramin->im_backing_suspend)
 348                 return -ENOMEM;
 349
 350         for (i = 0; i < ramin->im_pramin->size; i += 4)
 351                 ramin->im_backing_suspend[i/4] = nv_ri32(dev, i);
 352         return 0;
 353 }
 354
 355 void
 356 nv50_instmem_resume(struct drm_device *dev)
 357 {
 358         struct drm_nouveau_private *dev_priv = dev->dev_private;
 359         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 360         struct nouveau_channel *chan = dev_priv->fifos[0];
 361         struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
 362         int i;
 363
 364         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->im_backing_start >> 16));
 365         for (i = 0; i < ramin->im_pramin->size; i += 4)
 366                 BAR0_WI32(ramin, i, ramin->im_backing_suspend[i/4]);
 367         vfree(ramin->im_backing_suspend);
 368         ramin->im_backing_suspend = NULL;
 369
 370         /* Poke the relevant regs, and pray it works :) */
 371         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
 372         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 373         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
 374                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 375         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
 376                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 377         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
 378                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 379
 380         for (i = 0; i < 8; i++)
 381                 nv_wr32(dev, 0x1900 + (i*4), 0);
 382 }
 383
 384 int
 385 nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
 386                       uint32_t *sz)
 387 {
 388         int ret;
 389
 390         if (gpuobj->im_backing)
 391                 return -EINVAL;
 392
 393         *sz = ALIGN(*sz, NV50_INSTMEM_PAGE_SIZE);
 394         if (*sz == 0)
 395                 return -EINVAL;
 396
 397         ret = nouveau_bo_new(dev, NULL, *sz, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
 398                              true, false, &gpuobj->im_backing);
 399         if (ret) {
 400                 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
 401                 return ret;
 402         }
 403
 404         ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
 405         if (ret) {
 406                 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
 407                 nouveau_bo_ref(NULL, &gpuobj->im_backing);
 408                 return ret;
 409         }
 410
 411         gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
 412         gpuobj->im_backing_start <<= PAGE_SHIFT;
 413
 414         return 0;
 415 }
 416
 417 void
 418 nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 419 {
 420         struct drm_nouveau_private *dev_priv = dev->dev_private;
 421
 422         if (gpuobj && gpuobj->im_backing) {
 423                 if (gpuobj->im_bound)
 424                         dev_priv->engine.instmem.unbind(dev, gpuobj);
 425                 nouveau_bo_unpin(gpuobj->im_backing);
 426                 nouveau_bo_ref(NULL, &gpuobj->im_backing);
 427                 gpuobj->im_backing = NULL;
 428         }
 429 }
 430
 431 int
 432 nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 433 {
 434         struct drm_nouveau_private *dev_priv = dev->dev_private;
 435         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 436         struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;
 437         uint32_t pte, pte_end;
 438         uint64_t vram;
 439
 440         if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
 441                 return -EINVAL;
 442
 443         NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
 444                  gpuobj->im_pramin->start, gpuobj->im_pramin->size);
 445
 446         pte     = (gpuobj->im_pramin->start >> 12) << 1;
 447         pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
 448         vram    = gpuobj->im_backing_start;
 449
 450         NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
 451                  gpuobj->im_pramin->start, pte, pte_end);
 452         NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
 453
 454         vram |= 1;
 455         if (dev_priv->vram_sys_base) {
 456                 vram += dev_priv->vram_sys_base;
 457                 vram |= 0x30;
 458         }
 459
 460         dev_priv->engine.instmem.prepare_access(dev, true);
 461         while (pte < pte_end) {
 462                 nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));
 463                 nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));
 464                 vram += NV50_INSTMEM_PAGE_SIZE;
 465         }
 466         dev_priv->engine.instmem.finish_access(dev);
 467
 468         nv_wr32(dev, 0x100c80, 0x00040001);
 469         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
 470                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (1)\n");
 471                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
 472                 return -EBUSY;
 473         }
 474
 475         nv_wr32(dev, 0x100c80, 0x00060001);
 476         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
 477                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
 478                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
 479                 return -EBUSY;
 480         }
 481
 482         gpuobj->im_bound = 1;
 483         return 0;
 484 }
 485
 486 int
 487 nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 488 {
 489         struct drm_nouveau_private *dev_priv = dev->dev_private;
 490         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 491         uint32_t pte, pte_end;
 492
 493         if (gpuobj->im_bound == 0)
 494                 return -EINVAL;
 495
 496         pte     = (gpuobj->im_pramin->start >> 12) << 1;
 497         pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
 498
 499         dev_priv->engine.instmem.prepare_access(dev, true);
 500         while (pte < pte_end) {
 501                 nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
 502                 nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
 503         }
 504         dev_priv->engine.instmem.finish_access(dev);
 505
 506         gpuobj->im_bound = 0;
 507         return 0;
 508 }
 509
 510 void
 511 nv50_instmem_prepare_access(struct drm_device *dev, bool write)
 512 {
 513         struct drm_nouveau_private *dev_priv = dev->dev_private;
 514         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 515
 516         priv->last_access_wr = write;
 517 }
 518
 519 void
 520 nv50_instmem_finish_access(struct drm_device *dev)
 521 {
 522         struct drm_nouveau_private *dev_priv = dev->dev_private;
 523         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 524
 525         if (priv->last_access_wr) {
 526                 nv_wr32(dev, 0x070000, 0x00000001);
 527                 if (!nv_wait(0x070000, 0x00000001, 0x00000000))
 528                         NV_ERROR(dev, "PRAMIN flush timeout\n");
 529         }
 530 }
 531