drivers/gpu/drm/nouveau/nv50_instmem.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "nouveau_drv.h"
  31
  32 struct nv50_instmem_priv {
  33         uint32_t save1700[5]; /* 0x1700->0x1710 */
  34
  35         struct nouveau_gpuobj_ref *pramin_pt;
  36         struct nouveau_gpuobj_ref *pramin_bar;
  37         struct nouveau_gpuobj_ref *fb_bar;
  38
  39         bool last_access_wr;
  40 };
  41
  42 #define NV50_INSTMEM_PAGE_SHIFT 12
  43 #define NV50_INSTMEM_PAGE_SIZE  (1 << NV50_INSTMEM_PAGE_SHIFT)
  44 #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
  45
  46 /*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
  47  */
  48 #define BAR0_WI32(g, o, v) do {                                   \
  49         uint32_t offset;                                          \
  50         if ((g)->im_backing) {                                    \
  51                 offset = (g)->im_backing_start;                   \
  52         } else {                                                  \
  53                 offset  = chan->ramin->gpuobj->im_backing_start;  \
  54                 offset += (g)->im_pramin->start;                  \
  55         }                                                         \
  56         offset += (o);                                            \
  57         nv_wr32(dev, NV_RAMIN + (offset & 0xfffff), (v));              \
  58 } while (0)
  59
  60 int
  61 nv50_instmem_init(struct drm_device *dev)
  62 {
  63         struct drm_nouveau_private *dev_priv = dev->dev_private;
  64         struct nouveau_channel *chan;
  65         uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
  66         struct nv50_instmem_priv *priv;
  67         int ret, i;
  68         uint32_t v, save_nv001700;
  69
  70         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  71         if (!priv)
  72                 return -ENOMEM;
  73         dev_priv->engine.instmem.priv = priv;
  74
  75         /* Save state, will restore at takedown. */
  76         for (i = 0x1700; i <= 0x1710; i += 4)
  77                 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
  78
  79         /* Reserve the last MiB of VRAM, we should probably try to avoid
  80          * setting up the below tables over the top of the VBIOS image at
  81          * some point.
  82          */
  83         dev_priv->ramin_rsvd_vram = 1 << 20;
  84         c_offset = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
  85         c_size   = 128 << 10;
  86         c_vmpd   = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
  87         c_ramfc  = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
  88         c_base   = c_vmpd + 0x4000;
  89         pt_size  = NV50_INSTMEM_PT_SIZE(dev_priv->ramin_size);
  90
  91         NV_DEBUG(dev, " Rsvd VRAM base: 0x%08x\n", c_offset);
  92         NV_DEBUG(dev, "    VBIOS image: 0x%08x\n",
  93                                 (nv_rd32(dev, 0x619f04) & ~0xff) << 8);
  94         NV_DEBUG(dev, "  Aperture size: %d MiB\n", dev_priv->ramin_size >> 20);
  95         NV_DEBUG(dev, "        PT size: %d KiB\n", pt_size >> 10);
  96
  97         /* Determine VM layout, we need to do this first to make sure
  98          * we allocate enough memory for all the page tables.
  99          */
 100         dev_priv->vm_gart_base = roundup(NV50_VM_BLOCK, NV50_VM_BLOCK);
 101         dev_priv->vm_gart_size = NV50_VM_BLOCK;
 102
 103         dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size;
 104         dev_priv->vm_vram_size = dev_priv->vram_size;
 105         if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM)
 106                 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM;
 107         dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK);
 108         dev_priv->vm_vram_pt_nr = dev_priv->vm_vram_size / NV50_VM_BLOCK;
 109
 110         dev_priv->vm_end = dev_priv->vm_vram_base + dev_priv->vm_vram_size;
 111
 112         NV_DEBUG(dev, "NV50VM: GART 0x%016llx-0x%016llx\n",
 113                  dev_priv->vm_gart_base,
 114                  dev_priv->vm_gart_base + dev_priv->vm_gart_size - 1);
 115         NV_DEBUG(dev, "NV50VM: VRAM 0x%016llx-0x%016llx\n",
 116                  dev_priv->vm_vram_base,
 117                  dev_priv->vm_vram_base + dev_priv->vm_vram_size - 1);
 118
 119         c_size += dev_priv->vm_vram_pt_nr * (NV50_VM_BLOCK / 65536 * 8);
 120
 121         /* Map BAR0 PRAMIN aperture over the memory we want to use */
 122         save_nv001700 = nv_rd32(dev, NV50_PUNK_BAR0_PRAMIN);
 123         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
 124
 125         /* Create a fake channel, and use it as our "dummy" channels 0/127.
 126          * The main reason for creating a channel is so we can use the gpuobj
 127          * code.  However, it's probably worth noting that NVIDIA also setup
 128          * their channels 0/127 with the same values they configure here.
 129          * So, there may be some other reason for doing this.
 130          *
 131          * Have to create the entire channel manually, as the real channel
 132          * creation code assumes we have PRAMIN access, and we don't until
 133          * we're done here.
 134          */
 135         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
 136         if (!chan)
 137                 return -ENOMEM;
 138         chan->id = 0;
 139         chan->dev = dev;
 140         chan->file_priv = (struct drm_file *)-2;
 141         dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
 142
 143         /* Channel's PRAMIN object + heap */
 144         ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0,
 145                                                         NULL, &chan->ramin);
 146         if (ret)
 147                 return ret;
 148
 149         if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base))
 150                 return -ENOMEM;
 151
 152         /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
 153         ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
 154                                                 0x4000, 0, NULL, &chan->ramfc);
 155         if (ret)
 156                 return ret;
 157
 158         for (i = 0; i < c_vmpd; i += 4)
 159                 BAR0_WI32(chan->ramin->gpuobj, i, 0);
 160
 161         /* VM page directory */
 162         ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
 163                                            0x4000, 0, &chan->vm_pd, NULL);
 164         if (ret)
 165                 return ret;
 166         for (i = 0; i < 0x4000; i += 8) {
 167                 BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000);
 168                 BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000);
 169         }
 170
 171         /* PRAMIN page table, cheat and map into VM at 0x0000000000.
 172          * We map the entire fake channel into the start of the PRAMIN BAR
 173          */
 174         ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
 175                                      0, &priv->pramin_pt);
 176         if (ret)
 177                 return ret;
 178
 179         v = c_offset | 1;
 180         if (dev_priv->vram_sys_base) {
 181                 v += dev_priv->vram_sys_base;
 182                 v |= 0x30;
 183         }
 184
 185         i = 0;
 186         while (v < dev_priv->vram_sys_base + c_offset + c_size) {
 187                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v);
 188                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
 189                 v += 0x1000;
 190                 i += 8;
 191         }
 192
 193         while (i < pt_size) {
 194                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);
 195                 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
 196                 i += 8;
 197         }
 198
 199         BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
 200         BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
 201
 202         /* VRAM page table(s), mapped into VM at +1GiB  */
 203         for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
 204                 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
 205                                              NV50_VM_BLOCK/65536*8, 0, 0,
 206                                              &chan->vm_vram_pt[i]);
 207                 if (ret) {
 208                         NV_ERROR(dev, "Error creating VRAM page tables: %d\n",
 209                                                                         ret);
 210                         dev_priv->vm_vram_pt_nr = i;
 211                         return ret;
 212                 }
 213                 dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i]->gpuobj;
 214
 215                 for (v = 0; v < dev_priv->vm_vram_pt[i]->im_pramin->size;
 216                                                                 v += 4)
 217                         BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0);
 218
 219                 BAR0_WI32(chan->vm_pd, 0x10 + (i*8),
 220                           chan->vm_vram_pt[i]->instance | 0x61);
 221                 BAR0_WI32(chan->vm_pd, 0x14 + (i*8), 0);
 222         }
 223
 224         /* DMA object for PRAMIN BAR */
 225         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
 226                                                         &priv->pramin_bar);
 227         if (ret)
 228                 return ret;
 229         BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000);
 230         BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin_size - 1);
 231         BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000);
 232         BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000);
 233         BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000);
 234         BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
 235
 236         /* DMA object for FB BAR */
 237         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
 238                                                         &priv->fb_bar);
 239         if (ret)
 240                 return ret;
 241         BAR0_WI32(priv->fb_bar->gpuobj, 0x00, 0x7fc00000);
 242         BAR0_WI32(priv->fb_bar->gpuobj, 0x04, 0x40000000 +
 243                                               drm_get_resource_len(dev, 1) - 1);
 244         BAR0_WI32(priv->fb_bar->gpuobj, 0x08, 0x40000000);
 245         BAR0_WI32(priv->fb_bar->gpuobj, 0x0c, 0x00000000);
 246         BAR0_WI32(priv->fb_bar->gpuobj, 0x10, 0x00000000);
 247         BAR0_WI32(priv->fb_bar->gpuobj, 0x14, 0x00000000);
 248
 249         /* Poke the relevant regs, and pray it works :) */
 250         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
 251         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 252         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
 253                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 254         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
 255                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 256         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
 257                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 258
 259         for (i = 0; i < 8; i++)
 260                 nv_wr32(dev, 0x1900 + (i*4), 0);
 261
 262         /* Assume that praying isn't enough, check that we can re-read the
 263          * entire fake channel back from the PRAMIN BAR */
 264         dev_priv->engine.instmem.prepare_access(dev, false);
 265         for (i = 0; i < c_size; i += 4) {
 266                 if (nv_rd32(dev, NV_RAMIN + i) != nv_ri32(dev, i)) {
 267                         NV_ERROR(dev, "Error reading back PRAMIN at 0x%08x\n",
 268                                                                         i);
 269                         dev_priv->engine.instmem.finish_access(dev);
 270                         return -EINVAL;
 271                 }
 272         }
 273         dev_priv->engine.instmem.finish_access(dev);
 274
 275         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, save_nv001700);
 276
 277         /* Global PRAMIN heap */
 278         if (nouveau_mem_init_heap(&dev_priv->ramin_heap,
 279                                   c_size, dev_priv->ramin_size - c_size)) {
 280                 dev_priv->ramin_heap = NULL;
 281                 NV_ERROR(dev, "Failed to init RAMIN heap\n");
 282         }
 283
 284         /*XXX: incorrect, but needed to make hash func "work" */
 285         dev_priv->ramht_offset = 0x10000;
 286         dev_priv->ramht_bits   = 9;
 287         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
 288         return 0;
 289 }
 290
 291 void
 292 nv50_instmem_takedown(struct drm_device *dev)
 293 {
 294         struct drm_nouveau_private *dev_priv = dev->dev_private;
 295         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 296         struct nouveau_channel *chan = dev_priv->fifos[0];
 297         int i;
 298
 299         NV_DEBUG(dev, "\n");
 300
 301         if (!priv)
 302                 return;
 303
 304         /* Restore state from before init */
 305         for (i = 0x1700; i <= 0x1710; i += 4)
 306                 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
 307
 308         nouveau_gpuobj_ref_del(dev, &priv->fb_bar);
 309         nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
 310         nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
 311
 312         /* Destroy dummy channel */
 313         if (chan) {
 314                 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
 315                         nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt[i]);
 316                         dev_priv->vm_vram_pt[i] = NULL;
 317                 }
 318                 dev_priv->vm_vram_pt_nr = 0;
 319
 320                 nouveau_gpuobj_del(dev, &chan->vm_pd);
 321                 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 322                 nouveau_gpuobj_ref_del(dev, &chan->ramin);
 323                 nouveau_mem_takedown(&chan->ramin_heap);
 324
 325                 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
 326                 kfree(chan);
 327         }
 328
 329         dev_priv->engine.instmem.priv = NULL;
 330         kfree(priv);
 331 }
 332
 333 int
 334 nv50_instmem_suspend(struct drm_device *dev)
 335 {
 336         struct drm_nouveau_private *dev_priv = dev->dev_private;
 337         struct nouveau_channel *chan = dev_priv->fifos[0];
 338         struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
 339         int i;
 340
 341         ramin->im_backing_suspend = vmalloc(ramin->im_pramin->size);
 342         if (!ramin->im_backing_suspend)
 343                 return -ENOMEM;
 344
 345         for (i = 0; i < ramin->im_pramin->size; i += 4)
 346                 ramin->im_backing_suspend[i/4] = nv_ri32(dev, i);
 347         return 0;
 348 }
 349
 350 void
 351 nv50_instmem_resume(struct drm_device *dev)
 352 {
 353         struct drm_nouveau_private *dev_priv = dev->dev_private;
 354         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 355         struct nouveau_channel *chan = dev_priv->fifos[0];
 356         struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
 357         int i;
 358
 359         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->im_backing_start >> 16));
 360         for (i = 0; i < ramin->im_pramin->size; i += 4)
 361                 BAR0_WI32(ramin, i, ramin->im_backing_suspend[i/4]);
 362         vfree(ramin->im_backing_suspend);
 363         ramin->im_backing_suspend = NULL;
 364
 365         /* Poke the relevant regs, and pray it works :) */
 366         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
 367         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 368         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
 369                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 370         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
 371                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 372         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
 373                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 374
 375         for (i = 0; i < 8; i++)
 376                 nv_wr32(dev, 0x1900 + (i*4), 0);
 377 }
 378
 379 int
 380 nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
 381                       uint32_t *sz)
 382 {
 383         int ret;
 384
 385         if (gpuobj->im_backing)
 386                 return -EINVAL;
 387
 388         *sz = ALIGN(*sz, NV50_INSTMEM_PAGE_SIZE);
 389         if (*sz == 0)
 390                 return -EINVAL;
 391
 392         ret = nouveau_bo_new(dev, NULL, *sz, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
 393                              true, false, &gpuobj->im_backing);
 394         if (ret) {
 395                 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
 396                 return ret;
 397         }
 398
 399         ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
 400         if (ret) {
 401                 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
 402                 nouveau_bo_ref(NULL, &gpuobj->im_backing);
 403                 return ret;
 404         }
 405
 406         gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
 407         gpuobj->im_backing_start <<= PAGE_SHIFT;
 408
 409         return 0;
 410 }
 411
 412 void
 413 nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 414 {
 415         struct drm_nouveau_private *dev_priv = dev->dev_private;
 416
 417         if (gpuobj && gpuobj->im_backing) {
 418                 if (gpuobj->im_bound)
 419                         dev_priv->engine.instmem.unbind(dev, gpuobj);
 420                 nouveau_bo_unpin(gpuobj->im_backing);
 421                 nouveau_bo_ref(NULL, &gpuobj->im_backing);
 422                 gpuobj->im_backing = NULL;
 423         }
 424 }
 425
 426 int
 427 nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 428 {
 429         struct drm_nouveau_private *dev_priv = dev->dev_private;
 430         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 431         struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;
 432         uint32_t pte, pte_end;
 433         uint64_t vram;
 434
 435         if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
 436                 return -EINVAL;
 437
 438         NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
 439                  gpuobj->im_pramin->start, gpuobj->im_pramin->size);
 440
 441         pte     = (gpuobj->im_pramin->start >> 12) << 1;
 442         pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
 443         vram    = gpuobj->im_backing_start;
 444
 445         NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
 446                  gpuobj->im_pramin->start, pte, pte_end);
 447         NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
 448
 449         vram |= 1;
 450         if (dev_priv->vram_sys_base) {
 451                 vram += dev_priv->vram_sys_base;
 452                 vram |= 0x30;
 453         }
 454
 455         dev_priv->engine.instmem.prepare_access(dev, true);
 456         while (pte < pte_end) {
 457                 nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));
 458                 nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));
 459                 vram += NV50_INSTMEM_PAGE_SIZE;
 460         }
 461         dev_priv->engine.instmem.finish_access(dev);
 462
 463         nv_wr32(dev, 0x100c80, 0x00040001);
 464         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
 465                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (1)\n");
 466                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
 467                 return -EBUSY;
 468         }
 469
 470         nv_wr32(dev, 0x100c80, 0x00060001);
 471         if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
 472                 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
 473                 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
 474                 return -EBUSY;
 475         }
 476
 477         gpuobj->im_bound = 1;
 478         return 0;
 479 }
 480
 481 int
 482 nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 483 {
 484         struct drm_nouveau_private *dev_priv = dev->dev_private;
 485         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 486         uint32_t pte, pte_end;
 487
 488         if (gpuobj->im_bound == 0)
 489                 return -EINVAL;
 490
 491         pte     = (gpuobj->im_pramin->start >> 12) << 1;
 492         pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
 493
 494         dev_priv->engine.instmem.prepare_access(dev, true);
 495         while (pte < pte_end) {
 496                 nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
 497                 nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
 498         }
 499         dev_priv->engine.instmem.finish_access(dev);
 500
 501         gpuobj->im_bound = 0;
 502         return 0;
 503 }
 504
 505 void
 506 nv50_instmem_prepare_access(struct drm_device *dev, bool write)
 507 {
 508         struct drm_nouveau_private *dev_priv = dev->dev_private;
 509         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 510
 511         priv->last_access_wr = write;
 512 }
 513
 514 void
 515 nv50_instmem_finish_access(struct drm_device *dev)
 516 {
 517         struct drm_nouveau_private *dev_priv = dev->dev_private;
 518         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 519
 520         if (priv->last_access_wr) {
 521                 nv_wr32(dev, 0x070000, 0x00000001);
 522                 if (!nv_wait(0x070000, 0x00000001, 0x00000000))
 523                         NV_ERROR(dev, "PRAMIN flush timeout\n");
 524         }
 525 }
 526