drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_grctx.h"
  32 #include "nouveau_dma.h"
  33 #include "nouveau_vm.h"
  34 #include "nouveau_ramht.h"
  35 #include "nv50_evo.h"
  36
  37 static int  nv50_graph_register(struct drm_device *);
  38 static void nv50_graph_isr(struct drm_device *);
  39
  40 static void
  41 nv50_graph_init_reset(struct drm_device *dev)
  42 {
  43         uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
  44
  45         NV_DEBUG(dev, "\n");
  46
  47         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
  48         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
  49 }
  50
  51 static void
  52 nv50_graph_init_intr(struct drm_device *dev)
  53 {
  54         NV_DEBUG(dev, "\n");
  55
  56         nouveau_irq_register(dev, 12, nv50_graph_isr);
  57         nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
  58         nv_wr32(dev, 0x400138, 0xffffffff);
  59         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
  60 }
  61
  62 static void
  63 nv50_graph_init_regs__nv(struct drm_device *dev)
  64 {
  65         struct drm_nouveau_private *dev_priv = dev->dev_private;
  66         uint32_t units = nv_rd32(dev, 0x1540);
  67         int i;
  68
  69         NV_DEBUG(dev, "\n");
  70
  71         nv_wr32(dev, 0x400804, 0xc0000000);
  72         nv_wr32(dev, 0x406800, 0xc0000000);
  73         nv_wr32(dev, 0x400c04, 0xc0000000);
  74         nv_wr32(dev, 0x401800, 0xc0000000);
  75         nv_wr32(dev, 0x405018, 0xc0000000);
  76         nv_wr32(dev, 0x402000, 0xc0000000);
  77
  78         for (i = 0; i < 16; i++) {
  79                 if (units & 1 << i) {
  80                         if (dev_priv->chipset < 0xa0) {
  81                                 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
  82                                 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
  83                                 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
  84                         } else {
  85                                 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
  86                                 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
  87                                 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
  88                         }
  89                 }
  90         }
  91
  92         nv_wr32(dev, 0x400108, 0xffffffff);
  93
  94         nv_wr32(dev, 0x400824, 0x00004000);
  95         nv_wr32(dev, 0x400500, 0x00010001);
  96 }
  97
  98 static void
  99 nv50_graph_init_zcull(struct drm_device *dev)
 100 {
 101         struct drm_nouveau_private *dev_priv = dev->dev_private;
 102         int i;
 103
 104         NV_DEBUG(dev, "\n");
 105
 106         switch (dev_priv->chipset & 0xf0) {
 107         case 0x50:
 108         case 0x80:
 109         case 0x90:
 110                 nv_wr32(dev, 0x402ca8, 0x00000800);
 111                 break;
 112         case 0xa0:
 113         default:
 114                 nv_wr32(dev, 0x402cc0, 0x00000000);
 115                 if (dev_priv->chipset == 0xa0 ||
 116                     dev_priv->chipset == 0xaa ||
 117                     dev_priv->chipset == 0xac) {
 118                         nv_wr32(dev, 0x402ca8, 0x00000802);
 119                 } else {
 120                         nv_wr32(dev, 0x402cc0, 0x00000000);
 121                         nv_wr32(dev, 0x402ca8, 0x00000002);
 122                 }
 123
 124                 break;
 125         }
 126
 127         /* zero out zcull regions */
 128         for (i = 0; i < 8; i++) {
 129                 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
 130                 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
 131                 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
 132                 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
 133         }
 134 }
 135
 136 static int
 137 nv50_graph_init_ctxctl(struct drm_device *dev)
 138 {
 139         struct drm_nouveau_private *dev_priv = dev->dev_private;
 140         struct nouveau_grctx ctx = {};
 141         uint32_t *cp;
 142         int i;
 143
 144         NV_DEBUG(dev, "\n");
 145
 146         cp = kmalloc(512 * 4, GFP_KERNEL);
 147         if (!cp) {
 148                 NV_ERROR(dev, "failed to allocate ctxprog\n");
 149                 dev_priv->engine.graph.accel_blocked = true;
 150                 return 0;
 151         }
 152
 153         ctx.dev = dev;
 154         ctx.mode = NOUVEAU_GRCTX_PROG;
 155         ctx.data = cp;
 156         ctx.ctxprog_max = 512;
 157         if (!nv50_grctx_init(&ctx)) {
 158                 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 159
 160                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 161                 for (i = 0; i < ctx.ctxprog_len; i++)
 162                         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 163         } else {
 164                 dev_priv->engine.graph.accel_blocked = true;
 165         }
 166         kfree(cp);
 167
 168         nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
 169         nv_wr32(dev, 0x400320, 4);
 170         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
 171         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 172         return 0;
 173 }
 174
 175 int
 176 nv50_graph_init(struct drm_device *dev)
 177 {
 178         int ret;
 179
 180         NV_DEBUG(dev, "\n");
 181
 182         nv50_graph_init_reset(dev);
 183         nv50_graph_init_regs__nv(dev);
 184         nv50_graph_init_zcull(dev);
 185
 186         ret = nv50_graph_init_ctxctl(dev);
 187         if (ret)
 188                 return ret;
 189
 190         ret = nv50_graph_register(dev);
 191         if (ret)
 192                 return ret;
 193         nv50_graph_init_intr(dev);
 194         return 0;
 195 }
 196
 197 void
 198 nv50_graph_takedown(struct drm_device *dev)
 199 {
 200         NV_DEBUG(dev, "\n");
 201         nv_wr32(dev, 0x40013c, 0x00000000);
 202         nouveau_irq_unregister(dev, 12);
 203 }
 204
 205 void
 206 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
 207 {
 208         const uint32_t mask = 0x00010001;
 209
 210         if (enabled)
 211                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
 212         else
 213                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
 214 }
 215
 216 struct nouveau_channel *
 217 nv50_graph_channel(struct drm_device *dev)
 218 {
 219         struct drm_nouveau_private *dev_priv = dev->dev_private;
 220         uint32_t inst;
 221         int i;
 222
 223         /* Be sure we're not in the middle of a context switch or bad things
 224          * will happen, such as unloading the wrong pgraph context.
 225          */
 226         if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
 227                 NV_ERROR(dev, "Ctxprog is still running\n");
 228
 229         inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 230         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 231                 return NULL;
 232         inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
 233
 234         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 235                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 236
 237                 if (chan && chan->ramin && chan->ramin->vinst == inst)
 238                         return chan;
 239         }
 240
 241         return NULL;
 242 }
 243
 244 int
 245 nv50_graph_create_context(struct nouveau_channel *chan)
 246 {
 247         struct drm_device *dev = chan->dev;
 248         struct drm_nouveau_private *dev_priv = dev->dev_private;
 249         struct nouveau_gpuobj *ramin = chan->ramin;
 250         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 251         struct nouveau_grctx ctx = {};
 252         int hdr, ret;
 253
 254         NV_DEBUG(dev, "ch%d\n", chan->id);
 255
 256         ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
 257                                  NVOBJ_FLAG_ZERO_ALLOC |
 258                                  NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
 259         if (ret)
 260                 return ret;
 261
 262         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 263         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 264         nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
 265                                    pgraph->grctx_size - 1);
 266         nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
 267         nv_wo32(ramin, hdr + 0x0c, 0);
 268         nv_wo32(ramin, hdr + 0x10, 0);
 269         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 270
 271         ctx.dev = chan->dev;
 272         ctx.mode = NOUVEAU_GRCTX_VALS;
 273         ctx.data = chan->ramin_grctx;
 274         nv50_grctx_init(&ctx);
 275
 276         nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
 277
 278         dev_priv->engine.instmem.flush(dev);
 279         atomic_inc(&chan->vm->pgraph_refs);
 280         return 0;
 281 }
 282
 283 void
 284 nv50_graph_destroy_context(struct nouveau_channel *chan)
 285 {
 286         struct drm_device *dev = chan->dev;
 287         struct drm_nouveau_private *dev_priv = dev->dev_private;
 288         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 289         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 290         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 291         unsigned long flags;
 292
 293         NV_DEBUG(dev, "ch%d\n", chan->id);
 294
 295         if (!chan->ramin)
 296                 return;
 297
 298         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 299         pfifo->reassign(dev, false);
 300         pgraph->fifo_access(dev, false);
 301
 302         if (pgraph->channel(dev) == chan)
 303                 pgraph->unload_context(dev);
 304
 305         for (i = hdr; i < hdr + 24; i += 4)
 306                 nv_wo32(chan->ramin, i, 0);
 307         dev_priv->engine.instmem.flush(dev);
 308
 309         pgraph->fifo_access(dev, true);
 310         pfifo->reassign(dev, true);
 311         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 312
 313         nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
 314
 315         atomic_dec(&chan->vm->pgraph_refs);
 316 }
 317
 318 static int
 319 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
 320 {
 321         uint32_t fifo = nv_rd32(dev, 0x400500);
 322
 323         nv_wr32(dev, 0x400500, fifo & ~1);
 324         nv_wr32(dev, 0x400784, inst);
 325         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
 326         nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
 327         nv_wr32(dev, 0x400040, 0xffffffff);
 328         (void)nv_rd32(dev, 0x400040);
 329         nv_wr32(dev, 0x400040, 0x00000000);
 330         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
 331
 332         if (nouveau_wait_for_idle(dev))
 333                 nv_wr32(dev, 0x40032c, inst | (1<<31));
 334         nv_wr32(dev, 0x400500, fifo);
 335
 336         return 0;
 337 }
 338
 339 int
 340 nv50_graph_load_context(struct nouveau_channel *chan)
 341 {
 342         uint32_t inst = chan->ramin->vinst >> 12;
 343
 344         NV_DEBUG(chan->dev, "ch%d\n", chan->id);
 345         return nv50_graph_do_load_context(chan->dev, inst);
 346 }
 347
 348 int
 349 nv50_graph_unload_context(struct drm_device *dev)
 350 {
 351         uint32_t inst;
 352
 353         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 354         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 355                 return 0;
 356         inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 357
 358         nouveau_wait_for_idle(dev);
 359         nv_wr32(dev, 0x400784, inst);
 360         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
 361         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
 362         nouveau_wait_for_idle(dev);
 363
 364         nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
 365         return 0;
 366 }
 367
 368 int
 369 nv50_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
 370 {
 371         struct drm_device *dev = chan->dev;
 372         struct drm_nouveau_private *dev_priv = dev->dev_private;
 373         struct nouveau_gpuobj *obj = NULL;
 374         int ret;
 375
 376         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 377         if (ret)
 378                 return ret;
 379         obj->engine = 1;
 380         obj->class  = class;
 381
 382         nv_wo32(obj, 0x00, class);
 383         nv_wo32(obj, 0x04, 0x00000000);
 384         nv_wo32(obj, 0x08, 0x00000000);
 385         nv_wo32(obj, 0x0c, 0x00000000);
 386         dev_priv->engine.instmem.flush(dev);
 387
 388         ret = nouveau_ramht_insert(chan, handle, obj);
 389         nouveau_gpuobj_ref(NULL, &obj);
 390         return ret;
 391 }
 392
 393 static void
 394 nv50_graph_context_switch(struct drm_device *dev)
 395 {
 396         uint32_t inst;
 397
 398         nv50_graph_unload_context(dev);
 399
 400         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
 401         inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
 402         nv50_graph_do_load_context(dev, inst);
 403
 404         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
 405                 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
 406 }
 407
 408 static int
 409 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
 410                            u32 class, u32 mthd, u32 data)
 411 {
 412         struct nouveau_gpuobj *gpuobj;
 413
 414         gpuobj = nouveau_ramht_find(chan, data);
 415         if (!gpuobj)
 416                 return -ENOENT;
 417
 418         if (nouveau_notifier_offset(gpuobj, NULL))
 419                 return -EINVAL;
 420
 421         chan->nvsw.vblsem = gpuobj;
 422         chan->nvsw.vblsem_offset = ~0;
 423         return 0;
 424 }
 425
 426 static int
 427 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
 428                               u32 class, u32 mthd, u32 data)
 429 {
 430         if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
 431                 return -ERANGE;
 432
 433         chan->nvsw.vblsem_offset = data >> 2;
 434         return 0;
 435 }
 436
 437 static int
 438 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
 439                                    u32 class, u32 mthd, u32 data)
 440 {
 441         chan->nvsw.vblsem_rval = data;
 442         return 0;
 443 }
 444
 445 static int
 446 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
 447                                u32 class, u32 mthd, u32 data)
 448 {
 449         struct drm_device *dev = chan->dev;
 450         struct drm_nouveau_private *dev_priv = dev->dev_private;
 451
 452         if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
 453                 return -EINVAL;
 454
 455         drm_vblank_get(dev, data);
 456
 457         chan->nvsw.vblsem_head = data;
 458         list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
 459
 460         return 0;
 461 }
 462
 463 static int
 464 nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
 465                                u32 class, u32 mthd, u32 data)
 466 {
 467         nouveau_finish_page_flip(chan, NULL);
 468         return 0;
 469 }
 470
 471 static int
 472 nv50_graph_register(struct drm_device *dev)
 473 {
 474         struct drm_nouveau_private *dev_priv = dev->dev_private;
 475
 476         if (dev_priv->engine.graph.registered)
 477                 return 0;
 478
 479         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
 480         NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
 481         NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
 482         NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
 483         NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
 484         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
 485
 486         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 487         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
 488         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
 489
 490         /* tesla */
 491         if (dev_priv->chipset == 0x50)
 492                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
 493         else
 494         if (dev_priv->chipset < 0xa0)
 495                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
 496         else {
 497                 switch (dev_priv->chipset) {
 498                 case 0xa0:
 499                 case 0xaa:
 500                 case 0xac:
 501                         NVOBJ_CLASS(dev, 0x8397, GR);
 502                         break;
 503                 case 0xa3:
 504                 case 0xa5:
 505                 case 0xa8:
 506                         NVOBJ_CLASS(dev, 0x8597, GR);
 507                         break;
 508                 case 0xaf:
 509                         NVOBJ_CLASS(dev, 0x8697, GR);
 510                         break;
 511                 }
 512         }
 513
 514         /* compute */
 515         NVOBJ_CLASS(dev, 0x50c0, GR);
 516         if (dev_priv->chipset  > 0xa0 &&
 517             dev_priv->chipset != 0xaa &&
 518             dev_priv->chipset != 0xac)
 519                 NVOBJ_CLASS(dev, 0x85c0, GR);
 520
 521         dev_priv->engine.graph.registered = true;
 522         return 0;
 523 }
 524
 525 void
 526 nv50_graph_tlb_flush(struct drm_device *dev)
 527 {
 528         nv50_vm_flush_engine(dev, 0);
 529 }
 530
 531 void
 532 nv84_graph_tlb_flush(struct drm_device *dev)
 533 {
 534         struct drm_nouveau_private *dev_priv = dev->dev_private;
 535         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 536         bool idle, timeout = false;
 537         unsigned long flags;
 538         u64 start;
 539         u32 tmp;
 540
 541         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 542         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 543
 544         start = ptimer->read(dev);
 545         do {
 546                 idle = true;
 547
 548                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 549                         if ((tmp & 7) == 1)
 550                                 idle = false;
 551                 }
 552
 553                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 554                         if ((tmp & 7) == 1)
 555                                 idle = false;
 556                 }
 557
 558                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 559                         if ((tmp & 7) == 1)
 560                                 idle = false;
 561                 }
 562         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 563
 564         if (timeout) {
 565                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 566                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 567                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 568                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 569         }
 570
 571         nv50_vm_flush_engine(dev, 0);
 572
 573         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 574         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 575 }
 576
 577 static struct nouveau_enum nv50_mp_exec_error_names[] = {
 578         { 3, "STACK_UNDERFLOW", NULL },
 579         { 4, "QUADON_ACTIVE", NULL },
 580         { 8, "TIMEOUT", NULL },
 581         { 0x10, "INVALID_OPCODE", NULL },
 582         { 0x40, "BREAKPOINT", NULL },
 583         {}
 584 };
 585
 586 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
 587         { 0x00000001, "NOTIFY" },
 588         { 0x00000002, "IN" },
 589         { 0x00000004, "OUT" },
 590         {}
 591 };
 592
 593 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
 594         { 0x00000001, "FAULT" },
 595         {}
 596 };
 597
 598 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
 599         { 0x00000001, "FAULT" },
 600         {}
 601 };
 602
 603 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
 604         { 0x00000001, "FAULT" },
 605         {}
 606 };
 607
 608 /* There must be a *lot* of these. Will take some time to gather them up. */
 609 struct nouveau_enum nv50_data_error_names[] = {
 610         { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
 611         { 0x00000004, "INVALID_VALUE", NULL },
 612         { 0x00000005, "INVALID_ENUM", NULL },
 613         { 0x00000008, "INVALID_OBJECT", NULL },
 614         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 615         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 616         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 617         { 0x0000000c, "INVALID_BITFIELD", NULL },
 618         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 619         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 620         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 621         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 622         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 623         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 624         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 625         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 626         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 627         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 628         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 629         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 630         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 631         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 632         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 633         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 634         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 635         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 636         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 637         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 638         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 639         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 640         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 641         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 642         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 643         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 644         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 645         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 646         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 647         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 648         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 649         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 650         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 651         {}
 652 };
 653
 654 static struct nouveau_bitfield nv50_graph_intr[] = {
 655         { 0x00000001, "NOTIFY" },
 656         { 0x00000002, "COMPUTE_QUERY" },
 657         { 0x00000010, "ILLEGAL_MTHD" },
 658         { 0x00000020, "ILLEGAL_CLASS" },
 659         { 0x00000040, "DOUBLE_NOTIFY" },
 660         { 0x00001000, "CONTEXT_SWITCH" },
 661         { 0x00010000, "BUFFER_NOTIFY" },
 662         { 0x00100000, "DATA_ERROR" },
 663         { 0x00200000, "TRAP" },
 664         { 0x01000000, "SINGLE_STEP" },
 665         {}
 666 };
 667
 668 static void
 669 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 670 {
 671         struct drm_nouveau_private *dev_priv = dev->dev_private;
 672         uint32_t units = nv_rd32(dev, 0x1540);
 673         uint32_t addr, mp10, status, pc, oplow, ophigh;
 674         int i;
 675         int mps = 0;
 676         for (i = 0; i < 4; i++) {
 677                 if (!(units & 1 << (i+24)))
 678                         continue;
 679                 if (dev_priv->chipset < 0xa0)
 680                         addr = 0x408200 + (tpid << 12) + (i << 7);
 681                 else
 682                         addr = 0x408100 + (tpid << 11) + (i << 7);
 683                 mp10 = nv_rd32(dev, addr + 0x10);
 684                 status = nv_rd32(dev, addr + 0x14);
 685                 if (!status)
 686                         continue;
 687                 if (display) {
 688                         nv_rd32(dev, addr + 0x20);
 689                         pc = nv_rd32(dev, addr + 0x24);
 690                         oplow = nv_rd32(dev, addr + 0x70);
 691                         ophigh = nv_rd32(dev, addr + 0x74);
 692                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 693                                         "TP %d MP %d: ", tpid, i);
 694                         nouveau_enum_print(nv50_mp_exec_error_names, status);
 695                         printk(" at %06x warp %d, opcode %08x %08x\n",
 696                                         pc&0xffffff, pc >> 24,
 697                                         oplow, ophigh);
 698                 }
 699                 nv_wr32(dev, addr + 0x10, mp10);
 700                 nv_wr32(dev, addr + 0x14, 0);
 701                 mps++;
 702         }
 703         if (!mps && display)
 704                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 705                                 "No MPs claiming errors?\n", tpid);
 706 }
 707
 708 static void
 709 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 710                 uint32_t ustatus_new, int display, const char *name)
 711 {
 712         struct drm_nouveau_private *dev_priv = dev->dev_private;
 713         int tps = 0;
 714         uint32_t units = nv_rd32(dev, 0x1540);
 715         int i, r;
 716         uint32_t ustatus_addr, ustatus;
 717         for (i = 0; i < 16; i++) {
 718                 if (!(units & (1 << i)))
 719                         continue;
 720                 if (dev_priv->chipset < 0xa0)
 721                         ustatus_addr = ustatus_old + (i << 12);
 722                 else
 723                         ustatus_addr = ustatus_new + (i << 11);
 724                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 725                 if (!ustatus)
 726                         continue;
 727                 tps++;
 728                 switch (type) {
 729                 case 6: /* texture error... unknown for now */
 730                         if (display) {
 731                                 NV_ERROR(dev, "magic set %d:\n", i);
 732                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 733                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 734                                                 nv_rd32(dev, r));
 735                         }
 736                         break;
 737                 case 7: /* MP error */
 738                         if (ustatus & 0x00010000) {
 739                                 nv50_pgraph_mp_trap(dev, i, display);
 740                                 ustatus &= ~0x00010000;
 741                         }
 742                         break;
 743                 case 8: /* TPDMA error */
 744                         {
 745                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 746                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 747                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 748                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 749                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 750                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 751                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 752                         /* 2d engine destination */
 753                         if (ustatus & 0x00000010) {
 754                                 if (display) {
 755                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 756                                                         i, e14, e10);
 757                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 758                                                         i, e0c, e18, e1c, e20, e24);
 759                                 }
 760                                 ustatus &= ~0x00000010;
 761                         }
 762                         /* Render target */
 763                         if (ustatus & 0x00000040) {
 764                                 if (display) {
 765                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 766                                                         i, e14, e10);
 767                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 768                                                         i, e0c, e18, e1c, e20, e24);
 769                                 }
 770                                 ustatus &= ~0x00000040;
 771                         }
 772                         /* CUDA memory: l[], g[] or stack. */
 773                         if (ustatus & 0x00000080) {
 774                                 if (display) {
 775                                         if (e18 & 0x80000000) {
 776                                                 /* g[] read fault? */
 777                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 778                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 779                                                 e18 &= ~0x1f000000;
 780                                         } else if (e18 & 0xc) {
 781                                                 /* g[] write fault? */
 782                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 783                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 784                                                 e18 &= ~0x00000f80;
 785                                         } else {
 786                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 787                                                                 i, e14, e10);
 788                                         }
 789                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 790                                                         i, e0c, e18, e1c, e20, e24);
 791                                 }
 792                                 ustatus &= ~0x00000080;
 793                         }
 794                         }
 795                         break;
 796                 }
 797                 if (ustatus) {
 798                         if (display)
 799                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 800                 }
 801                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 802         }
 803
 804         if (!tps && display)
 805                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 806 }
 807
 808 static int
 809 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
 810 {
 811         u32 status = nv_rd32(dev, 0x400108);
 812         u32 ustatus;
 813
 814         if (!status && display) {
 815                 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
 816                 return 1;
 817         }
 818
 819         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 820          * COND, QUERY. If you get a trap from it, the command is still stuck
 821          * in DISPATCH and you need to do something about it. */
 822         if (status & 0x001) {
 823                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 824                 if (!ustatus && display) {
 825                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 826                 }
 827
 828                 nv_wr32(dev, 0x400500, 0x00000000);
 829
 830                 /* Known to be triggered by screwed up NOTIFY and COND... */
 831                 if (ustatus & 0x00000001) {
 832                         u32 addr = nv_rd32(dev, 0x400808);
 833                         u32 subc = (addr & 0x00070000) >> 16;
 834                         u32 mthd = (addr & 0x00001ffc);
 835                         u32 datal = nv_rd32(dev, 0x40080c);
 836                         u32 datah = nv_rd32(dev, 0x400810);
 837                         u32 class = nv_rd32(dev, 0x400814);
 838                         u32 r848 = nv_rd32(dev, 0x400848);
 839
 840                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
 841                         if (display && (addr & 0x80000000)) {
 842                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 843                                              "subc %d class 0x%04x mthd 0x%04x "
 844                                              "data 0x%08x%08x "
 845                                              "400808 0x%08x 400848 0x%08x\n",
 846                                         chid, inst, subc, class, mthd, datah,
 847                                         datal, addr, r848);
 848                         } else
 849                         if (display) {
 850                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 851                         }
 852
 853                         nv_wr32(dev, 0x400808, 0);
 854                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 855                         nv_wr32(dev, 0x400848, 0);
 856                         ustatus &= ~0x00000001;
 857                 }
 858
 859                 if (ustatus & 0x00000002) {
 860                         u32 addr = nv_rd32(dev, 0x40084c);
 861                         u32 subc = (addr & 0x00070000) >> 16;
 862                         u32 mthd = (addr & 0x00001ffc);
 863                         u32 data = nv_rd32(dev, 0x40085c);
 864                         u32 class = nv_rd32(dev, 0x400814);
 865
 866                         NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
 867                         if (display && (addr & 0x80000000)) {
 868                                 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
 869                                              "subc %d class 0x%04x mthd 0x%04x "
 870                                              "data 0x%08x 40084c 0x%08x\n",
 871                                         chid, inst, subc, class, mthd,
 872                                         data, addr);
 873                         } else
 874                         if (display) {
 875                                 NV_INFO(dev, "PGRAPH - no stuck command?\n");
 876                         }
 877
 878                         nv_wr32(dev, 0x40084c, 0);
 879                         ustatus &= ~0x00000002;
 880                 }
 881
 882                 if (ustatus && display) {
 883                         NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
 884                                       "0x%08x)\n", ustatus);
 885                 }
 886
 887                 nv_wr32(dev, 0x400804, 0xc0000000);
 888                 nv_wr32(dev, 0x400108, 0x001);
 889                 status &= ~0x001;
 890                 if (!status)
 891                         return 0;
 892         }
 893
 894         /* M2MF: Memory to memory copy engine. */
 895         if (status & 0x002) {
 896                 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 897                 if (display) {
 898                         NV_INFO(dev, "PGRAPH - TRAP_M2MF");
 899                         nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
 900                         printk("\n");
 901                         NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
 902                                 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
 903                                 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
 904
 905                 }
 906
 907                 /* No sane way found yet -- just reset the bugger. */
 908                 nv_wr32(dev, 0x400040, 2);
 909                 nv_wr32(dev, 0x400040, 0);
 910                 nv_wr32(dev, 0x406800, 0xc0000000);
 911                 nv_wr32(dev, 0x400108, 0x002);
 912                 status &= ~0x002;
 913         }
 914
 915         /* VFETCH: Fetches data from vertex buffers. */
 916         if (status & 0x004) {
 917                 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 918                 if (display) {
 919                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
 920                         nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
 921                         printk("\n");
 922                         NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
 923                                 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
 924                                 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
 925                 }
 926
 927                 nv_wr32(dev, 0x400c04, 0xc0000000);
 928                 nv_wr32(dev, 0x400108, 0x004);
 929                 status &= ~0x004;
 930         }
 931
 932         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 933         if (status & 0x008) {
 934                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 935                 if (display) {
 936                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
 937                         nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
 938                         printk("\n");
 939                         NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
 940                                 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
 941                                 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
 942
 943                 }
 944
 945                 /* No sane way found yet -- just reset the bugger. */
 946                 nv_wr32(dev, 0x400040, 0x80);
 947                 nv_wr32(dev, 0x400040, 0);
 948                 nv_wr32(dev, 0x401800, 0xc0000000);
 949                 nv_wr32(dev, 0x400108, 0x008);
 950                 status &= ~0x008;
 951         }
 952
 953         /* CCACHE: Handles code and c[] caches and fills them. */
 954         if (status & 0x010) {
 955                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 956                 if (display) {
 957                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
 958                         nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
 959                         printk("\n");
 960                         NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
 961                                      " %08x %08x %08x\n",
 962                                 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
 963                                 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
 964                                 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
 965                                 nv_rd32(dev, 0x40501c));
 966
 967                 }
 968
 969                 nv_wr32(dev, 0x405018, 0xc0000000);
 970                 nv_wr32(dev, 0x400108, 0x010);
 971                 status &= ~0x010;
 972         }
 973
 974         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 975          * remaining, so try to handle it anyway. Perhaps related to that
 976          * unknown DMA slot on tesla? */
 977         if (status & 0x20) {
 978                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 979                 if (display)
 980                         NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
 981                 nv_wr32(dev, 0x402000, 0xc0000000);
 982                 /* no status modifiction on purpose */
 983         }
 984
 985         /* TEXTURE: CUDA texturing units */
 986         if (status & 0x040) {
 987                 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
 988                                     "PGRAPH - TRAP_TEXTURE");
 989                 nv_wr32(dev, 0x400108, 0x040);
 990                 status &= ~0x040;
 991         }
 992
 993         /* MP: CUDA execution engines. */
 994         if (status & 0x080) {
 995                 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
 996                                     "PGRAPH - TRAP_MP");
 997                 nv_wr32(dev, 0x400108, 0x080);
 998                 status &= ~0x080;
 999         }
1000
1001         /* TPDMA:  Handles TP-initiated uncached memory accesses:
1002          * l[], g[], stack, 2d surfaces, render targets. */
1003         if (status & 0x100) {
1004                 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
1005                                     "PGRAPH - TRAP_TPDMA");
1006                 nv_wr32(dev, 0x400108, 0x100);
1007                 status &= ~0x100;
1008         }
1009
1010         if (status) {
1011                 if (display)
1012                         NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
1013                 nv_wr32(dev, 0x400108, status);
1014         }
1015
1016         return 1;
1017 }
1018
1019 static int
1020 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
1021 {
1022         struct drm_nouveau_private *dev_priv = dev->dev_private;
1023         struct nouveau_channel *chan;
1024         unsigned long flags;
1025         int i;
1026
1027         spin_lock_irqsave(&dev_priv->channels.lock, flags);
1028         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
1029                 chan = dev_priv->channels.ptr[i];
1030                 if (!chan || !chan->ramin)
1031                         continue;
1032
1033                 if (inst == chan->ramin->vinst)
1034                         break;
1035         }
1036         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
1037         return i;
1038 }
1039
1040 static void
1041 nv50_graph_isr(struct drm_device *dev)
1042 {
1043         u32 stat;
1044
1045         while ((stat = nv_rd32(dev, 0x400100))) {
1046                 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
1047                 u32 chid = nv50_graph_isr_chid(dev, inst);
1048                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1049                 u32 subc = (addr & 0x00070000) >> 16;
1050                 u32 mthd = (addr & 0x00001ffc);
1051                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1052                 u32 class = nv_rd32(dev, 0x400814);
1053                 u32 show = stat;
1054
1055                 if (stat & 0x00000010) {
1056                         if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
1057                                                        mthd, data))
1058                                 show &= ~0x00000010;
1059                 }
1060
1061                 if (stat & 0x00001000) {
1062                         nv_wr32(dev, 0x400500, 0x00000000);
1063                         nv_wr32(dev, 0x400100, 0x00001000);
1064                         nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
1065                         nv50_graph_context_switch(dev);
1066                         stat &= ~0x00001000;
1067                         show &= ~0x00001000;
1068                 }
1069
1070                 show = (show && nouveau_ratelimit()) ? show : 0;
1071
1072                 if (show & 0x00100000) {
1073                         u32 ecode = nv_rd32(dev, 0x400110);
1074                         NV_INFO(dev, "PGRAPH - DATA_ERROR ");
1075                         nouveau_enum_print(nv50_data_error_names, ecode);
1076                         printk("\n");
1077                 }
1078
1079                 if (stat & 0x00200000) {
1080                         if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
1081                                 show &= ~0x00200000;
1082                 }
1083
1084                 nv_wr32(dev, 0x400100, stat);
1085                 nv_wr32(dev, 0x400500, 0x00010001);
1086
1087                 if (show) {
1088                         NV_INFO(dev, "PGRAPH -");
1089                         nouveau_bitfield_print(nv50_graph_intr, show);
1090                         printk("\n");
1091                         NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1092                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
1093                                 chid, inst, subc, class, mthd, data);
1094                         nv50_fb_vm_trap(dev, 1);
1095                 }
1096         }
1097
1098         if (nv_rd32(dev, 0x400824) & (1 << 31))
1099                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1100 }