3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
7 nv50_fb_init(struct drm_device *dev)
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 /* Not a clue what this is exactly. Without pointing it at a
12 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
13 * cause IOMMU "read from address 0" errors (rh#561267)
15 nv_wr32(dev, 0x100c08, dev_priv->gart_info.sg_dummy_bus >> 8);
17 /* This is needed to get meaningful information from 100c90
18 * on traps. No idea what these values mean exactly. */
19 switch (dev_priv->chipset) {
21 nv_wr32(dev, 0x100c90, 0x0707ff);
26 nv_wr32(dev, 0x100c90, 0x0d0fff);
29 nv_wr32(dev, 0x100c90, 0x1d07ff);
37 nv50_fb_takedown(struct drm_device *dev)
42 nv50_fb_vm_trap(struct drm_device *dev, int display, const char *name)
44 struct drm_nouveau_private *dev_priv = dev->dev_private;
45 u32 trap[6], idx, chinst;
48 idx = nv_rd32(dev, 0x100c90);
49 if (!(idx & 0x80000000))
53 for (i = 0; i < 6; i++) {
54 nv_wr32(dev, 0x100c90, idx | i << 24);
55 trap[i] = nv_rd32(dev, 0x100c94);
57 nv_wr32(dev, 0x100c90, idx | 0x80000000);
62 chinst = (trap[2] << 16) | trap[1];
63 for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
64 struct nouveau_channel *chan = dev_priv->fifos[ch];
66 if (!chan || !chan->ramin)
69 if (chinst == chan->ramin->vinst >> 12)
73 NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x "
74 "channel %d (0x%08x)\n",
75 name, (trap[5] & 0x100 ? "read" : "write"),
76 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,