drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "nouveau_ramht.h"
  34 #include "drm_crtc_helper.h"
  35
  36 static void nv50_display_isr(struct drm_device *);
  37
  38 static inline int
  39 nv50_sor_nr(struct drm_device *dev)
  40 {
  41         struct drm_nouveau_private *dev_priv = dev->dev_private;
  42
  43         if (dev_priv->chipset  < 0x90 ||
  44             dev_priv->chipset == 0x92 ||
  45             dev_priv->chipset == 0xa0)
  46                 return 2;
  47
  48         return 4;
  49 }
  50
  51 int
  52 nv50_display_early_init(struct drm_device *dev)
  53 {
  54         return 0;
  55 }
  56
  57 void
  58 nv50_display_late_takedown(struct drm_device *dev)
  59 {
  60 }
  61
  62 int
  63 nv50_display_init(struct drm_device *dev)
  64 {
  65         struct drm_nouveau_private *dev_priv = dev->dev_private;
  66         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
  67         struct drm_connector *connector;
  68         struct nouveau_channel *evo;
  69         int ret, i;
  70         u32 val;
  71
  72         NV_DEBUG_KMS(dev, "\n");
  73
  74         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
  75
  76         /*
  77          * I think the 0x006101XX range is some kind of main control area
  78          * that enables things.
  79          */
  80         /* CRTC? */
  81         for (i = 0; i < 2; i++) {
  82                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
  83                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
  84                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
  85                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
  86                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
  87                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
  88                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
  89                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
  90         }
  91
  92         /* DAC */
  93         for (i = 0; i < 3; i++) {
  94                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
  95                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
  96         }
  97
  98         /* SOR */
  99         for (i = 0; i < nv50_sor_nr(dev); i++) {
 100                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 101                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 102         }
 103
 104         /* EXT */
 105         for (i = 0; i < 3; i++) {
 106                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 107                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 108         }
 109
 110         for (i = 0; i < 3; i++) {
 111                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 112                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 113                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 114         }
 115
 116         /* The precise purpose is unknown, i suspect it has something to do
 117          * with text mode.
 118          */
 119         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 120                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 121                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 122                 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
 123                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 124                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 125                                                 nv_rd32(dev, 0x6194e8));
 126                         return -EBUSY;
 127                 }
 128         }
 129
 130         for (i = 0; i < 2; i++) {
 131                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 132                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 133                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 134                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 135                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 136                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 137                         return -EBUSY;
 138                 }
 139
 140                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 141                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 142                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 143                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 144                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 145                         NV_ERROR(dev, "timeout: "
 146                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 147                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 148                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 149                         return -EBUSY;
 150                 }
 151         }
 152
 153         nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 154         nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 155         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 156         nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 157         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
 158                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 159                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 160                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 161
 162         /* enable hotplug interrupts */
 163         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 164                 struct nouveau_connector *conn = nouveau_connector(connector);
 165
 166                 if (conn->dcb->gpio_tag == 0xff)
 167                         continue;
 168
 169                 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
 170         }
 171
 172         ret = nv50_evo_init(dev);
 173         if (ret)
 174                 return ret;
 175         evo = dev_priv->evo;
 176
 177         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
 178
 179         ret = RING_SPACE(evo, 11);
 180         if (ret)
 181                 return ret;
 182         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 183         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 184         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 185         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 186         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 187         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 188         OUT_RING(evo, 0);
 189         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 190         OUT_RING(evo, 0);
 191         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 192         OUT_RING(evo, 0);
 193         FIRE_RING(evo);
 194         if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
 195                 NV_ERROR(dev, "evo pushbuf stalled\n");
 196
 197
 198         return 0;
 199 }
 200
 201 static int nv50_display_disable(struct drm_device *dev)
 202 {
 203         struct drm_nouveau_private *dev_priv = dev->dev_private;
 204         struct drm_crtc *drm_crtc;
 205         int ret, i;
 206
 207         NV_DEBUG_KMS(dev, "\n");
 208
 209         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 210                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 211
 212                 nv50_crtc_blank(crtc, true);
 213         }
 214
 215         ret = RING_SPACE(dev_priv->evo, 2);
 216         if (ret == 0) {
 217                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 218                 OUT_RING(dev_priv->evo, 0);
 219         }
 220         FIRE_RING(dev_priv->evo);
 221
 222         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 223          * cleaning up?
 224          */
 225         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 226                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 227                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 228
 229                 if (!crtc->base.enabled)
 230                         continue;
 231
 232                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 233                 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
 234                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 235                                       "0x%08x\n", mask, mask);
 236                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 237                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 238                 }
 239         }
 240
 241         nv50_evo_fini(dev);
 242
 243         for (i = 0; i < 3; i++) {
 244                 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 245                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 246                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 247                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 248                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 249                 }
 250         }
 251
 252         /* disable interrupts. */
 253         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 254
 255         /* disable hotplug interrupts */
 256         nv_wr32(dev, 0xe054, 0xffffffff);
 257         nv_wr32(dev, 0xe050, 0x00000000);
 258         if (dev_priv->chipset >= 0x90) {
 259                 nv_wr32(dev, 0xe074, 0xffffffff);
 260                 nv_wr32(dev, 0xe070, 0x00000000);
 261         }
 262         return 0;
 263 }
 264
 265 int nv50_display_create(struct drm_device *dev)
 266 {
 267         struct drm_nouveau_private *dev_priv = dev->dev_private;
 268         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 269         struct drm_connector *connector, *ct;
 270         int ret, i;
 271
 272         NV_DEBUG_KMS(dev, "\n");
 273
 274         /* init basic kernel modesetting */
 275         drm_mode_config_init(dev);
 276
 277         /* Initialise some optional connector properties. */
 278         drm_mode_create_scaling_mode_property(dev);
 279         drm_mode_create_dithering_property(dev);
 280
 281         dev->mode_config.min_width = 0;
 282         dev->mode_config.min_height = 0;
 283
 284         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 285
 286         dev->mode_config.max_width = 8192;
 287         dev->mode_config.max_height = 8192;
 288
 289         dev->mode_config.fb_base = dev_priv->fb_phys;
 290
 291         /* Create CRTC objects */
 292         for (i = 0; i < 2; i++)
 293                 nv50_crtc_create(dev, i);
 294
 295         /* We setup the encoders from the BIOS table */
 296         for (i = 0 ; i < dcb->entries; i++) {
 297                 struct dcb_entry *entry = &dcb->entry[i];
 298
 299                 if (entry->location != DCB_LOC_ON_CHIP) {
 300                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 301                                 entry->type, ffs(entry->or) - 1);
 302                         continue;
 303                 }
 304
 305                 connector = nouveau_connector_create(dev, entry->connector);
 306                 if (IS_ERR(connector))
 307                         continue;
 308
 309                 switch (entry->type) {
 310                 case OUTPUT_TMDS:
 311                 case OUTPUT_LVDS:
 312                 case OUTPUT_DP:
 313                         nv50_sor_create(connector, entry);
 314                         break;
 315                 case OUTPUT_ANALOG:
 316                         nv50_dac_create(connector, entry);
 317                         break;
 318                 default:
 319                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 320                         continue;
 321                 }
 322         }
 323
 324         list_for_each_entry_safe(connector, ct,
 325                                  &dev->mode_config.connector_list, head) {
 326                 if (!connector->encoder_ids[0]) {
 327                         NV_WARN(dev, "%s has no encoders, removing\n",
 328                                 drm_get_connector_name(connector));
 329                         connector->funcs->destroy(connector);
 330                 }
 331         }
 332
 333         INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
 334         nouveau_irq_register(dev, 26, nv50_display_isr);
 335
 336         ret = nv50_display_init(dev);
 337         if (ret) {
 338                 nv50_display_destroy(dev);
 339                 return ret;
 340         }
 341
 342         return 0;
 343 }
 344
 345 void
 346 nv50_display_destroy(struct drm_device *dev)
 347 {
 348         NV_DEBUG_KMS(dev, "\n");
 349
 350         drm_mode_config_cleanup(dev);
 351
 352         nv50_display_disable(dev);
 353         nouveau_irq_unregister(dev, 26);
 354 }
 355
 356 static u16
 357 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 358                            u32 mc, int pxclk)
 359 {
 360         struct drm_nouveau_private *dev_priv = dev->dev_private;
 361         struct nouveau_connector *nv_connector = NULL;
 362         struct drm_encoder *encoder;
 363         struct nvbios *bios = &dev_priv->vbios;
 364         u32 script = 0, or;
 365
 366         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 367                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 368
 369                 if (nv_encoder->dcb != dcb)
 370                         continue;
 371
 372                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 373                 break;
 374         }
 375
 376         or = ffs(dcb->or) - 1;
 377         switch (dcb->type) {
 378         case OUTPUT_LVDS:
 379                 script = (mc >> 8) & 0xf;
 380                 if (bios->fp_no_ddc) {
 381                         if (bios->fp.dual_link)
 382                                 script |= 0x0100;
 383                         if (bios->fp.if_is_24bit)
 384                                 script |= 0x0200;
 385                 } else {
 386                         if (pxclk >= bios->fp.duallink_transition_clk) {
 387                                 script |= 0x0100;
 388                                 if (bios->fp.strapless_is_24bit & 2)
 389                                         script |= 0x0200;
 390                         } else
 391                         if (bios->fp.strapless_is_24bit & 1)
 392                                 script |= 0x0200;
 393
 394                         if (nv_connector && nv_connector->edid &&
 395                             (nv_connector->edid->revision >= 4) &&
 396                             (nv_connector->edid->input & 0x70) >= 0x20)
 397                                 script |= 0x0200;
 398                 }
 399
 400                 if (nouveau_uscript_lvds >= 0) {
 401                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 402                                      "for output LVDS-%d\n", script,
 403                                      nouveau_uscript_lvds, or);
 404                         script = nouveau_uscript_lvds;
 405                 }
 406                 break;
 407         case OUTPUT_TMDS:
 408                 script = (mc >> 8) & 0xf;
 409                 if (pxclk >= 165000)
 410                         script |= 0x0100;
 411
 412                 if (nouveau_uscript_tmds >= 0) {
 413                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 414                                      "for output TMDS-%d\n", script,
 415                                      nouveau_uscript_tmds, or);
 416                         script = nouveau_uscript_tmds;
 417                 }
 418                 break;
 419         case OUTPUT_DP:
 420                 script = (mc >> 8) & 0xf;
 421                 break;
 422         case OUTPUT_ANALOG:
 423                 script = 0xff;
 424                 break;
 425         default:
 426                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 427                 break;
 428         }
 429
 430         return script;
 431 }
 432
 433 static void
 434 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 435 {
 436         struct drm_nouveau_private *dev_priv = dev->dev_private;
 437         struct nouveau_channel *chan, *tmp;
 438
 439         list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
 440                                  nvsw.vbl_wait) {
 441                 if (chan->nvsw.vblsem_head != crtc)
 442                         continue;
 443
 444                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 445                                                 chan->nvsw.vblsem_rval);
 446                 list_del(&chan->nvsw.vbl_wait);
 447                 drm_vblank_put(dev, crtc);
 448         }
 449
 450         drm_handle_vblank(dev, crtc);
 451 }
 452
 453 static void
 454 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 455 {
 456         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 457                 nv50_display_vblank_crtc_handler(dev, 0);
 458
 459         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 460                 nv50_display_vblank_crtc_handler(dev, 1);
 461
 462         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
 463 }
 464
 465 static void
 466 nv50_display_unk10_handler(struct drm_device *dev)
 467 {
 468         struct drm_nouveau_private *dev_priv = dev->dev_private;
 469         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 470         int i, crtc, or, type = OUTPUT_ANY;
 471
 472         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 473         dev_priv->evo_irq.dcb = NULL;
 474
 475         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 476
 477         /* Determine which CRTC we're dealing with, only 1 ever will be
 478          * signalled at the same time with the current nouveau code.
 479          */
 480         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 481         if (crtc < 0)
 482                 goto ack;
 483
 484         /* Nothing needs to be done for the encoder */
 485         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 486         if (crtc < 0)
 487                 goto ack;
 488
 489         /* Find which encoder was connected to the CRTC */
 490         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 491                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 492                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 493                 if (!(mc & (1 << crtc)))
 494                         continue;
 495
 496                 switch ((mc & 0x00000f00) >> 8) {
 497                 case 0: type = OUTPUT_ANALOG; break;
 498                 case 1: type = OUTPUT_TV; break;
 499                 default:
 500                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 501                         goto ack;
 502                 }
 503
 504                 or = i;
 505         }
 506
 507         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 508                 if (dev_priv->chipset  < 0x90 ||
 509                     dev_priv->chipset == 0x92 ||
 510                     dev_priv->chipset == 0xa0)
 511                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 512                 else
 513                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 514
 515                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 516                 if (!(mc & (1 << crtc)))
 517                         continue;
 518
 519                 switch ((mc & 0x00000f00) >> 8) {
 520                 case 0: type = OUTPUT_LVDS; break;
 521                 case 1: type = OUTPUT_TMDS; break;
 522                 case 2: type = OUTPUT_TMDS; break;
 523                 case 5: type = OUTPUT_TMDS; break;
 524                 case 8: type = OUTPUT_DP; break;
 525                 case 9: type = OUTPUT_DP; break;
 526                 default:
 527                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 528                         goto ack;
 529                 }
 530
 531                 or = i;
 532         }
 533
 534         /* There was no encoder to disable */
 535         if (type == OUTPUT_ANY)
 536                 goto ack;
 537
 538         /* Disable the encoder */
 539         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 540                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 541
 542                 if (dcb->type == type && (dcb->or & (1 << or))) {
 543                         nouveau_bios_run_display_table(dev, dcb, 0, -1);
 544                         dev_priv->evo_irq.dcb = dcb;
 545                         goto ack;
 546                 }
 547         }
 548
 549         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 550 ack:
 551         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 552         nv_wr32(dev, 0x610030, 0x80000000);
 553 }
 554
 555 static void
 556 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 557 {
 558         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 559         struct drm_encoder *encoder;
 560         uint32_t tmp, unk0 = 0, unk1 = 0;
 561
 562         if (dcb->type != OUTPUT_DP)
 563                 return;
 564
 565         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 566                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 567
 568                 if (nv_encoder->dcb == dcb) {
 569                         unk0 = nv_encoder->dp.unk0;
 570                         unk1 = nv_encoder->dp.unk1;
 571                         break;
 572                 }
 573         }
 574
 575         if (unk0 || unk1) {
 576                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 577                 tmp &= 0xfffffe03;
 578                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 579
 580                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 581                 tmp &= 0xfef080c0;
 582                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 583         }
 584 }
 585
 586 static void
 587 nv50_display_unk20_handler(struct drm_device *dev)
 588 {
 589         struct drm_nouveau_private *dev_priv = dev->dev_private;
 590         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
 591         struct dcb_entry *dcb;
 592         int i, crtc, or, type = OUTPUT_ANY;
 593
 594         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 595         dcb = dev_priv->evo_irq.dcb;
 596         if (dcb) {
 597                 nouveau_bios_run_display_table(dev, dcb, 0, -2);
 598                 dev_priv->evo_irq.dcb = NULL;
 599         }
 600
 601         /* CRTC clock change requested? */
 602         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 603         if (crtc >= 0) {
 604                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 605                 pclk &= 0x003fffff;
 606
 607                 nv50_crtc_set_clock(dev, crtc, pclk);
 608
 609                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 610                 tmp &= ~0x000000f;
 611                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 612         }
 613
 614         /* Nothing needs to be done for the encoder */
 615         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 616         if (crtc < 0)
 617                 goto ack;
 618         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 619
 620         /* Find which encoder is connected to the CRTC */
 621         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 622                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 623                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 624                 if (!(mc & (1 << crtc)))
 625                         continue;
 626
 627                 switch ((mc & 0x00000f00) >> 8) {
 628                 case 0: type = OUTPUT_ANALOG; break;
 629                 case 1: type = OUTPUT_TV; break;
 630                 default:
 631                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 632                         goto ack;
 633                 }
 634
 635                 or = i;
 636         }
 637
 638         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 639                 if (dev_priv->chipset  < 0x90 ||
 640                     dev_priv->chipset == 0x92 ||
 641                     dev_priv->chipset == 0xa0)
 642                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 643                 else
 644                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 645
 646                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 647                 if (!(mc & (1 << crtc)))
 648                         continue;
 649
 650                 switch ((mc & 0x00000f00) >> 8) {
 651                 case 0: type = OUTPUT_LVDS; break;
 652                 case 1: type = OUTPUT_TMDS; break;
 653                 case 2: type = OUTPUT_TMDS; break;
 654                 case 5: type = OUTPUT_TMDS; break;
 655                 case 8: type = OUTPUT_DP; break;
 656                 case 9: type = OUTPUT_DP; break;
 657                 default:
 658                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 659                         goto ack;
 660                 }
 661
 662                 or = i;
 663         }
 664
 665         if (type == OUTPUT_ANY)
 666                 goto ack;
 667
 668         /* Enable the encoder */
 669         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 670                 dcb = &dev_priv->vbios.dcb.entry[i];
 671                 if (dcb->type == type && (dcb->or & (1 << or)))
 672                         break;
 673         }
 674
 675         if (i == dev_priv->vbios.dcb.entries) {
 676                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 677                 goto ack;
 678         }
 679
 680         script = nv50_display_script_select(dev, dcb, mc, pclk);
 681         nouveau_bios_run_display_table(dev, dcb, script, pclk);
 682
 683         nv50_display_unk20_dp_hack(dev, dcb);
 684
 685         if (dcb->type != OUTPUT_ANALOG) {
 686                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 687                 tmp &= ~0x00000f0f;
 688                 if (script & 0x0100)
 689                         tmp |= 0x00000101;
 690                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 691         } else {
 692                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 693         }
 694
 695         dev_priv->evo_irq.dcb = dcb;
 696         dev_priv->evo_irq.pclk = pclk;
 697         dev_priv->evo_irq.script = script;
 698
 699 ack:
 700         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 701         nv_wr32(dev, 0x610030, 0x80000000);
 702 }
 703
 704 /* If programming a TMDS output on a SOR that can also be configured for
 705  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 706  *
 707  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 708  * the VBIOS scripts on at least one board I have only switch it off on
 709  * link 0, causing a blank display if the output has previously been
 710  * programmed for DisplayPort.
 711  */
 712 static void
 713 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 714 {
 715         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 716         struct drm_encoder *encoder;
 717         u32 tmp;
 718
 719         if (dcb->type != OUTPUT_TMDS)
 720                 return;
 721
 722         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 723                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 724
 725                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 726                     nv_encoder->dcb->or & (1 << or)) {
 727                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 728                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 729                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 730                         break;
 731                 }
 732         }
 733 }
 734
 735 static void
 736 nv50_display_unk40_handler(struct drm_device *dev)
 737 {
 738         struct drm_nouveau_private *dev_priv = dev->dev_private;
 739         struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
 740         u16 script = dev_priv->evo_irq.script;
 741         u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
 742
 743         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 744         dev_priv->evo_irq.dcb = NULL;
 745         if (!dcb)
 746                 goto ack;
 747
 748         nouveau_bios_run_display_table(dev, dcb, script, -pclk);
 749         nv50_display_unk40_dp_set_tmds(dev, dcb);
 750
 751 ack:
 752         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 753         nv_wr32(dev, 0x610030, 0x80000000);
 754         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 755 }
 756
 757 void
 758 nv50_display_irq_handler_bh(struct work_struct *work)
 759 {
 760         struct drm_nouveau_private *dev_priv =
 761                 container_of(work, struct drm_nouveau_private, irq_work);
 762         struct drm_device *dev = dev_priv->dev;
 763
 764         for (;;) {
 765                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 766                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 767
 768                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 769
 770                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 771                         nv50_display_unk10_handler(dev);
 772                 else
 773                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 774                         nv50_display_unk20_handler(dev);
 775                 else
 776                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 777                         nv50_display_unk40_handler(dev);
 778                 else
 779                         break;
 780         }
 781
 782         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 783 }
 784
 785 static void
 786 nv50_display_error_handler(struct drm_device *dev)
 787 {
 788         u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 789         u32 addr, data;
 790         int chid;
 791
 792         for (chid = 0; chid < 5; chid++) {
 793                 if (!(channels & (1 << chid)))
 794                         continue;
 795
 796                 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 797                 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 798                 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
 799                 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 800                               "(0x%04x 0x%02x)\n", chid,
 801                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 802
 803                 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 804         }
 805 }
 806
 807 static void
 808 nv50_display_isr(struct drm_device *dev)
 809 {
 810         struct drm_nouveau_private *dev_priv = dev->dev_private;
 811         uint32_t delayed = 0;
 812
 813         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 814                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 815                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 816                 uint32_t clock;
 817
 818                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 819
 820                 if (!intr0 && !(intr1 & ~delayed))
 821                         break;
 822
 823                 if (intr0 & 0x001f0000) {
 824                         nv50_display_error_handler(dev);
 825                         intr0 &= ~0x001f0000;
 826                 }
 827
 828                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 829                         nv50_display_vblank_handler(dev, intr1);
 830                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 831                 }
 832
 833                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 834                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 835                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 836                 if (clock) {
 837                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 838                         if (!work_pending(&dev_priv->irq_work))
 839                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
 840                         delayed |= clock;
 841                         intr1 &= ~clock;
 842                 }
 843
 844                 if (intr0) {
 845                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 846                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
 847                 }
 848
 849                 if (intr1) {
 850                         NV_ERROR(dev,
 851                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
 852                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
 853                 }
 854         }
 855 }