drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "drm_crtc_helper.h"
  34
  35 static void
  36 nv50_evo_channel_del(struct nouveau_channel **pchan)
  37 {
  38         struct nouveau_channel *chan = *pchan;
  39
  40         if (!chan)
  41                 return;
  42         *pchan = NULL;
  43
  44         nouveau_gpuobj_channel_takedown(chan);
  45         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  46
  47         if (chan->user)
  48                 iounmap(chan->user);
  49
  50         kfree(chan);
  51 }
  52
  53 static int
  54 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
  55                     uint32_t tile_flags, uint32_t magic_flags,
  56                     uint32_t offset, uint32_t limit)
  57 {
  58         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
  59         struct drm_device *dev = evo->dev;
  60         struct nouveau_gpuobj *obj = NULL;
  61         int ret;
  62
  63         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
  64         if (ret)
  65                 return ret;
  66         obj->engine = NVOBJ_ENGINE_DISPLAY;
  67
  68         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
  69         if (ret) {
  70                 nouveau_gpuobj_del(dev, &obj);
  71                 return ret;
  72         }
  73
  74         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
  75         nv_wo32(dev, obj, 1, limit);
  76         nv_wo32(dev, obj, 2, offset);
  77         nv_wo32(dev, obj, 3, 0x00000000);
  78         nv_wo32(dev, obj, 4, 0x00000000);
  79         nv_wo32(dev, obj, 5, 0x00010000);
  80         dev_priv->engine.instmem.flush(dev);
  81
  82         return 0;
  83 }
  84
  85 static int
  86 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
  87 {
  88         struct drm_nouveau_private *dev_priv = dev->dev_private;
  89         struct nouveau_channel *chan;
  90         int ret;
  91
  92         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
  93         if (!chan)
  94                 return -ENOMEM;
  95         *pchan = chan;
  96
  97         chan->id = -1;
  98         chan->dev = dev;
  99         chan->user_get = 4;
 100         chan->user_put = 0;
 101
 102         INIT_LIST_HEAD(&chan->ramht_refs);
 103
 104         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
 105                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 106         if (ret) {
 107                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
 108                 nv50_evo_channel_del(pchan);
 109                 return ret;
 110         }
 111
 112         ret = drm_mm_init(&chan->ramin_heap,
 113                           chan->ramin->gpuobj->im_pramin->start, 32768);
 114         if (ret) {
 115                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
 116                 nv50_evo_channel_del(pchan);
 117                 return ret;
 118         }
 119
 120         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
 121                                      0, &chan->ramht);
 122         if (ret) {
 123                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
 124                 nv50_evo_channel_del(pchan);
 125                 return ret;
 126         }
 127
 128         if (dev_priv->chipset != 0x50) {
 129                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
 130                                           0, 0xffffffff);
 131                 if (ret) {
 132                         nv50_evo_channel_del(pchan);
 133                         return ret;
 134                 }
 135
 136
 137                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
 138                                           0, 0xffffffff);
 139                 if (ret) {
 140                         nv50_evo_channel_del(pchan);
 141                         return ret;
 142                 }
 143         }
 144
 145         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
 146                                   0, dev_priv->vram_size);
 147         if (ret) {
 148                 nv50_evo_channel_del(pchan);
 149                 return ret;
 150         }
 151
 152         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
 153                              false, true, &chan->pushbuf_bo);
 154         if (ret == 0)
 155                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
 156         if (ret) {
 157                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
 158                 nv50_evo_channel_del(pchan);
 159                 return ret;
 160         }
 161
 162         ret = nouveau_bo_map(chan->pushbuf_bo);
 163         if (ret) {
 164                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
 165                 nv50_evo_channel_del(pchan);
 166                 return ret;
 167         }
 168
 169         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 170                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
 171         if (!chan->user) {
 172                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
 173                 nv50_evo_channel_del(pchan);
 174                 return -ENOMEM;
 175         }
 176
 177         return 0;
 178 }
 179
 180 int
 181 nv50_display_early_init(struct drm_device *dev)
 182 {
 183         return 0;
 184 }
 185
 186 void
 187 nv50_display_late_takedown(struct drm_device *dev)
 188 {
 189 }
 190
 191 int
 192 nv50_display_init(struct drm_device *dev)
 193 {
 194         struct drm_nouveau_private *dev_priv = dev->dev_private;
 195         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 196         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 197         struct nouveau_channel *evo = dev_priv->evo;
 198         struct drm_connector *connector;
 199         uint32_t val, ram_amount;
 200         uint64_t start;
 201         int ret, i;
 202
 203         NV_DEBUG_KMS(dev, "\n");
 204
 205         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 206         /*
 207          * I think the 0x006101XX range is some kind of main control area
 208          * that enables things.
 209          */
 210         /* CRTC? */
 211         for (i = 0; i < 2; i++) {
 212                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 213                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 214                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 215                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 216                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 217                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 218                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 219                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 220         }
 221         /* DAC */
 222         for (i = 0; i < 3; i++) {
 223                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 224                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 225         }
 226         /* SOR */
 227         for (i = 0; i < 4; i++) {
 228                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 229                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 230         }
 231         /* Something not yet in use, tv-out maybe. */
 232         for (i = 0; i < 3; i++) {
 233                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 234                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 235         }
 236
 237         for (i = 0; i < 3; i++) {
 238                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 239                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 240                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 241         }
 242
 243         /* This used to be in crtc unblank, but seems out of place there. */
 244         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
 245         /* RAM is clamped to 256 MiB. */
 246         ram_amount = dev_priv->vram_size;
 247         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
 248         if (ram_amount > 256*1024*1024)
 249                 ram_amount = 256*1024*1024;
 250         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
 251         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
 252         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
 253
 254         /* The precise purpose is unknown, i suspect it has something to do
 255          * with text mode.
 256          */
 257         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 258                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 259                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 260                 if (!nv_wait(0x006194e8, 2, 0)) {
 261                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 262                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 263                                                 nv_rd32(dev, 0x6194e8));
 264                         return -EBUSY;
 265                 }
 266         }
 267
 268         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
 269          * stuck in some unspecified state
 270          */
 271         start = ptimer->read(dev);
 272         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
 273         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
 274                 if ((val & 0x9f0000) == 0x20000)
 275                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 276                                                         val | 0x800000);
 277
 278                 if ((val & 0x3f0000) == 0x30000)
 279                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 280                                                         val | 0x200000);
 281
 282                 if (ptimer->read(dev) - start > 1000000000ULL) {
 283                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
 284                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
 285                         return -EBUSY;
 286                 }
 287         }
 288
 289         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 290         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
 291         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
 292                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
 293                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 294                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 295                 return -EBUSY;
 296         }
 297
 298         for (i = 0; i < 2; i++) {
 299                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 300                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 301                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 302                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 303                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 304                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 305                         return -EBUSY;
 306                 }
 307
 308                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 309                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 310                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 311                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 312                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 313                         NV_ERROR(dev, "timeout: "
 314                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 315                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 316                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 317                         return -EBUSY;
 318                 }
 319         }
 320
 321         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
 322
 323         /* initialise fifo */
 324         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
 325                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
 326                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
 327                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
 328         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
 329         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
 330         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
 331                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
 332                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
 333                 return -EBUSY;
 334         }
 335         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 336                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
 337                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 338         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
 339         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
 340                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 341         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
 342
 343         evo->dma.max = (4096/4) - 2;
 344         evo->dma.put = 0;
 345         evo->dma.cur = evo->dma.put;
 346         evo->dma.free = evo->dma.max - evo->dma.cur;
 347
 348         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
 349         if (ret)
 350                 return ret;
 351
 352         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 353                 OUT_RING(evo, 0);
 354
 355         ret = RING_SPACE(evo, 11);
 356         if (ret)
 357                 return ret;
 358         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 359         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 360         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 361         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 362         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 363         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 364         OUT_RING(evo, 0);
 365         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 366         OUT_RING(evo, 0);
 367         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 368         OUT_RING(evo, 0);
 369         FIRE_RING(evo);
 370         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
 371                 NV_ERROR(dev, "evo pushbuf stalled\n");
 372
 373         /* enable clock change interrupts. */
 374         nv_wr32(dev, 0x610028, 0x00010001);
 375         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
 376                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
 377                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
 378
 379         /* enable hotplug interrupts */
 380         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 381                 struct nouveau_connector *conn = nouveau_connector(connector);
 382
 383                 if (conn->dcb->gpio_tag == 0xff)
 384                         continue;
 385
 386                 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int nv50_display_disable(struct drm_device *dev)
 393 {
 394         struct drm_nouveau_private *dev_priv = dev->dev_private;
 395         struct drm_crtc *drm_crtc;
 396         int ret, i;
 397
 398         NV_DEBUG_KMS(dev, "\n");
 399
 400         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 401                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 402
 403                 nv50_crtc_blank(crtc, true);
 404         }
 405
 406         ret = RING_SPACE(dev_priv->evo, 2);
 407         if (ret == 0) {
 408                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 409                 OUT_RING(dev_priv->evo, 0);
 410         }
 411         FIRE_RING(dev_priv->evo);
 412
 413         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 414          * cleaning up?
 415          */
 416         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 417                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 418                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 419
 420                 if (!crtc->base.enabled)
 421                         continue;
 422
 423                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 424                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
 425                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 426                                       "0x%08x\n", mask, mask);
 427                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 428                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 429                 }
 430         }
 431
 432         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
 433         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
 434         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
 435                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
 436                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 437                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 438         }
 439
 440         for (i = 0; i < 3; i++) {
 441                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
 442                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 443                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 444                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 445                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 446                 }
 447         }
 448
 449         /* disable interrupts. */
 450         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
 451
 452         /* disable hotplug interrupts */
 453         nv_wr32(dev, 0xe054, 0xffffffff);
 454         nv_wr32(dev, 0xe050, 0x00000000);
 455         if (dev_priv->chipset >= 0x90) {
 456                 nv_wr32(dev, 0xe074, 0xffffffff);
 457                 nv_wr32(dev, 0xe070, 0x00000000);
 458         }
 459         return 0;
 460 }
 461
 462 int nv50_display_create(struct drm_device *dev)
 463 {
 464         struct drm_nouveau_private *dev_priv = dev->dev_private;
 465         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 466         struct drm_connector *connector, *ct;
 467         int ret, i;
 468
 469         NV_DEBUG_KMS(dev, "\n");
 470
 471         /* init basic kernel modesetting */
 472         drm_mode_config_init(dev);
 473
 474         /* Initialise some optional connector properties. */
 475         drm_mode_create_scaling_mode_property(dev);
 476         drm_mode_create_dithering_property(dev);
 477
 478         dev->mode_config.min_width = 0;
 479         dev->mode_config.min_height = 0;
 480
 481         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 482
 483         dev->mode_config.max_width = 8192;
 484         dev->mode_config.max_height = 8192;
 485
 486         dev->mode_config.fb_base = dev_priv->fb_phys;
 487
 488         /* Create EVO channel */
 489         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
 490         if (ret) {
 491                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
 492                 return ret;
 493         }
 494
 495         /* Create CRTC objects */
 496         for (i = 0; i < 2; i++)
 497                 nv50_crtc_create(dev, i);
 498
 499         /* We setup the encoders from the BIOS table */
 500         for (i = 0 ; i < dcb->entries; i++) {
 501                 struct dcb_entry *entry = &dcb->entry[i];
 502
 503                 if (entry->location != DCB_LOC_ON_CHIP) {
 504                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 505                                 entry->type, ffs(entry->or) - 1);
 506                         continue;
 507                 }
 508
 509                 connector = nouveau_connector_create(dev, entry->connector);
 510                 if (IS_ERR(connector))
 511                         continue;
 512
 513                 switch (entry->type) {
 514                 case OUTPUT_TMDS:
 515                 case OUTPUT_LVDS:
 516                 case OUTPUT_DP:
 517                         nv50_sor_create(connector, entry);
 518                         break;
 519                 case OUTPUT_ANALOG:
 520                         nv50_dac_create(connector, entry);
 521                         break;
 522                 default:
 523                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 524                         continue;
 525                 }
 526         }
 527
 528         list_for_each_entry_safe(connector, ct,
 529                                  &dev->mode_config.connector_list, head) {
 530                 if (!connector->encoder_ids[0]) {
 531                         NV_WARN(dev, "%s has no encoders, removing\n",
 532                                 drm_get_connector_name(connector));
 533                         connector->funcs->destroy(connector);
 534                 }
 535         }
 536
 537         ret = nv50_display_init(dev);
 538         if (ret) {
 539                 nv50_display_destroy(dev);
 540                 return ret;
 541         }
 542
 543         return 0;
 544 }
 545
 546 void
 547 nv50_display_destroy(struct drm_device *dev)
 548 {
 549         struct drm_nouveau_private *dev_priv = dev->dev_private;
 550
 551         NV_DEBUG_KMS(dev, "\n");
 552
 553         drm_mode_config_cleanup(dev);
 554
 555         nv50_display_disable(dev);
 556         nv50_evo_channel_del(&dev_priv->evo);
 557 }
 558
 559 static u16
 560 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 561                            u32 mc, int pxclk)
 562 {
 563         struct drm_nouveau_private *dev_priv = dev->dev_private;
 564         struct nouveau_connector *nv_connector = NULL;
 565         struct drm_encoder *encoder;
 566         struct nvbios *bios = &dev_priv->vbios;
 567         u32 script = 0, or;
 568
 569         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 570                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 571
 572                 if (nv_encoder->dcb != dcb)
 573                         continue;
 574
 575                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 576                 break;
 577         }
 578
 579         or = ffs(dcb->or) - 1;
 580         switch (dcb->type) {
 581         case OUTPUT_LVDS:
 582                 script = (mc >> 8) & 0xf;
 583                 if (bios->fp_no_ddc) {
 584                         if (bios->fp.dual_link)
 585                                 script |= 0x0100;
 586                         if (bios->fp.if_is_24bit)
 587                                 script |= 0x0200;
 588                 } else {
 589                         if (pxclk >= bios->fp.duallink_transition_clk) {
 590                                 script |= 0x0100;
 591                                 if (bios->fp.strapless_is_24bit & 2)
 592                                         script |= 0x0200;
 593                         } else
 594                         if (bios->fp.strapless_is_24bit & 1)
 595                                 script |= 0x0200;
 596
 597                         if (nv_connector && nv_connector->edid &&
 598                             (nv_connector->edid->revision >= 4) &&
 599                             (nv_connector->edid->input & 0x70) >= 0x20)
 600                                 script |= 0x0200;
 601                 }
 602
 603                 if (nouveau_uscript_lvds >= 0) {
 604                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 605                                      "for output LVDS-%d\n", script,
 606                                      nouveau_uscript_lvds, or);
 607                         script = nouveau_uscript_lvds;
 608                 }
 609                 break;
 610         case OUTPUT_TMDS:
 611                 script = (mc >> 8) & 0xf;
 612                 if (pxclk >= 165000)
 613                         script |= 0x0100;
 614
 615                 if (nouveau_uscript_tmds >= 0) {
 616                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 617                                      "for output TMDS-%d\n", script,
 618                                      nouveau_uscript_tmds, or);
 619                         script = nouveau_uscript_tmds;
 620                 }
 621                 break;
 622         case OUTPUT_DP:
 623                 script = (mc >> 8) & 0xf;
 624                 break;
 625         case OUTPUT_ANALOG:
 626                 script = 0xff;
 627                 break;
 628         default:
 629                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 630                 break;
 631         }
 632
 633         return script;
 634 }
 635
 636 static void
 637 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 638 {
 639         struct drm_nouveau_private *dev_priv = dev->dev_private;
 640         struct nouveau_channel *chan;
 641         struct list_head *entry, *tmp;
 642
 643         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
 644                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
 645
 646                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 647                                                 chan->nvsw.vblsem_rval);
 648                 list_del(&chan->nvsw.vbl_wait);
 649         }
 650 }
 651
 652 static void
 653 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 654 {
 655         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 656
 657         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 658                 nv50_display_vblank_crtc_handler(dev, 0);
 659
 660         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 661                 nv50_display_vblank_crtc_handler(dev, 1);
 662
 663         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
 664                      NV50_PDISPLAY_INTR_EN) & ~intr);
 665         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
 666 }
 667
 668 static void
 669 nv50_display_unk10_handler(struct drm_device *dev)
 670 {
 671         struct drm_nouveau_private *dev_priv = dev->dev_private;
 672         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 673         int i, crtc, or, type = OUTPUT_ANY;
 674
 675         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 676         dev_priv->evo_irq.dcb = NULL;
 677
 678         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 679
 680         /* Determine which CRTC we're dealing with, only 1 ever will be
 681          * signalled at the same time with the current nouveau code.
 682          */
 683         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 684         if (crtc < 0)
 685                 goto ack;
 686
 687         /* Nothing needs to be done for the encoder */
 688         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 689         if (crtc < 0)
 690                 goto ack;
 691
 692         /* Find which encoder was connected to the CRTC */
 693         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 694                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 695                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 696                 if (!(mc & (1 << crtc)))
 697                         continue;
 698
 699                 switch ((mc & 0x00000f00) >> 8) {
 700                 case 0: type = OUTPUT_ANALOG; break;
 701                 case 1: type = OUTPUT_TV; break;
 702                 default:
 703                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 704                         goto ack;
 705                 }
 706
 707                 or = i;
 708         }
 709
 710         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 711                 if (dev_priv->chipset  < 0x90 ||
 712                     dev_priv->chipset == 0x92 ||
 713                     dev_priv->chipset == 0xa0)
 714                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 715                 else
 716                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 717
 718                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 719                 if (!(mc & (1 << crtc)))
 720                         continue;
 721
 722                 switch ((mc & 0x00000f00) >> 8) {
 723                 case 0: type = OUTPUT_LVDS; break;
 724                 case 1: type = OUTPUT_TMDS; break;
 725                 case 2: type = OUTPUT_TMDS; break;
 726                 case 5: type = OUTPUT_TMDS; break;
 727                 case 8: type = OUTPUT_DP; break;
 728                 case 9: type = OUTPUT_DP; break;
 729                 default:
 730                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 731                         goto ack;
 732                 }
 733
 734                 or = i;
 735         }
 736
 737         /* There was no encoder to disable */
 738         if (type == OUTPUT_ANY)
 739                 goto ack;
 740
 741         /* Disable the encoder */
 742         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 743                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 744
 745                 if (dcb->type == type && (dcb->or & (1 << or))) {
 746                         nouveau_bios_run_display_table(dev, dcb, 0, -1);
 747                         dev_priv->evo_irq.dcb = dcb;
 748                         goto ack;
 749                 }
 750         }
 751
 752         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 753 ack:
 754         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 755         nv_wr32(dev, 0x610030, 0x80000000);
 756 }
 757
 758 static void
 759 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 760 {
 761         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 762         struct drm_encoder *encoder;
 763         uint32_t tmp, unk0 = 0, unk1 = 0;
 764
 765         if (dcb->type != OUTPUT_DP)
 766                 return;
 767
 768         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 769                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 770
 771                 if (nv_encoder->dcb == dcb) {
 772                         unk0 = nv_encoder->dp.unk0;
 773                         unk1 = nv_encoder->dp.unk1;
 774                         break;
 775                 }
 776         }
 777
 778         if (unk0 || unk1) {
 779                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 780                 tmp &= 0xfffffe03;
 781                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 782
 783                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 784                 tmp &= 0xfef080c0;
 785                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 786         }
 787 }
 788
 789 static void
 790 nv50_display_unk20_handler(struct drm_device *dev)
 791 {
 792         struct drm_nouveau_private *dev_priv = dev->dev_private;
 793         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
 794         struct dcb_entry *dcb;
 795         int i, crtc, or, type = OUTPUT_ANY;
 796
 797         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 798         dcb = dev_priv->evo_irq.dcb;
 799         if (dcb) {
 800                 nouveau_bios_run_display_table(dev, dcb, 0, -2);
 801                 dev_priv->evo_irq.dcb = NULL;
 802         }
 803
 804         /* CRTC clock change requested? */
 805         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 806         if (crtc >= 0) {
 807                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 808                 pclk &= 0x003fffff;
 809
 810                 nv50_crtc_set_clock(dev, crtc, pclk);
 811
 812                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 813                 tmp &= ~0x000000f;
 814                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 815         }
 816
 817         /* Nothing needs to be done for the encoder */
 818         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 819         if (crtc < 0)
 820                 goto ack;
 821         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 822
 823         /* Find which encoder is connected to the CRTC */
 824         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 825                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 826                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 827                 if (!(mc & (1 << crtc)))
 828                         continue;
 829
 830                 switch ((mc & 0x00000f00) >> 8) {
 831                 case 0: type = OUTPUT_ANALOG; break;
 832                 case 1: type = OUTPUT_TV; break;
 833                 default:
 834                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 835                         goto ack;
 836                 }
 837
 838                 or = i;
 839         }
 840
 841         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 842                 if (dev_priv->chipset  < 0x90 ||
 843                     dev_priv->chipset == 0x92 ||
 844                     dev_priv->chipset == 0xa0)
 845                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 846                 else
 847                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 848
 849                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 850                 if (!(mc & (1 << crtc)))
 851                         continue;
 852
 853                 switch ((mc & 0x00000f00) >> 8) {
 854                 case 0: type = OUTPUT_LVDS; break;
 855                 case 1: type = OUTPUT_TMDS; break;
 856                 case 2: type = OUTPUT_TMDS; break;
 857                 case 5: type = OUTPUT_TMDS; break;
 858                 case 8: type = OUTPUT_DP; break;
 859                 case 9: type = OUTPUT_DP; break;
 860                 default:
 861                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 862                         goto ack;
 863                 }
 864
 865                 or = i;
 866         }
 867
 868         if (type == OUTPUT_ANY)
 869                 goto ack;
 870
 871         /* Enable the encoder */
 872         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 873                 dcb = &dev_priv->vbios.dcb.entry[i];
 874                 if (dcb->type == type && (dcb->or & (1 << or)))
 875                         break;
 876         }
 877
 878         if (i == dev_priv->vbios.dcb.entries) {
 879                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 880                 goto ack;
 881         }
 882
 883         script = nv50_display_script_select(dev, dcb, mc, pclk);
 884         nouveau_bios_run_display_table(dev, dcb, script, pclk);
 885
 886         nv50_display_unk20_dp_hack(dev, dcb);
 887
 888         if (dcb->type != OUTPUT_ANALOG) {
 889                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 890                 tmp &= ~0x00000f0f;
 891                 if (script & 0x0100)
 892                         tmp |= 0x00000101;
 893                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 894         } else {
 895                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 896         }
 897
 898         dev_priv->evo_irq.dcb = dcb;
 899         dev_priv->evo_irq.pclk = pclk;
 900         dev_priv->evo_irq.script = script;
 901
 902 ack:
 903         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 904         nv_wr32(dev, 0x610030, 0x80000000);
 905 }
 906
 907 /* If programming a TMDS output on a SOR that can also be configured for
 908  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 909  *
 910  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 911  * the VBIOS scripts on at least one board I have only switch it off on
 912  * link 0, causing a blank display if the output has previously been
 913  * programmed for DisplayPort.
 914  */
 915 static void
 916 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 917 {
 918         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 919         struct drm_encoder *encoder;
 920         u32 tmp;
 921
 922         if (dcb->type != OUTPUT_TMDS)
 923                 return;
 924
 925         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 926                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 927
 928                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 929                     nv_encoder->dcb->or & (1 << or)) {
 930                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 931                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 932                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 933                         break;
 934                 }
 935         }
 936 }
 937
 938 static void
 939 nv50_display_unk40_handler(struct drm_device *dev)
 940 {
 941         struct drm_nouveau_private *dev_priv = dev->dev_private;
 942         struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
 943         u16 script = dev_priv->evo_irq.script;
 944         u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
 945
 946         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 947         dev_priv->evo_irq.dcb = NULL;
 948         if (!dcb)
 949                 goto ack;
 950
 951         nouveau_bios_run_display_table(dev, dcb, script, -pclk);
 952         nv50_display_unk40_dp_set_tmds(dev, dcb);
 953
 954 ack:
 955         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 956         nv_wr32(dev, 0x610030, 0x80000000);
 957         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 958 }
 959
 960 void
 961 nv50_display_irq_handler_bh(struct work_struct *work)
 962 {
 963         struct drm_nouveau_private *dev_priv =
 964                 container_of(work, struct drm_nouveau_private, irq_work);
 965         struct drm_device *dev = dev_priv->dev;
 966
 967         for (;;) {
 968                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 969                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 970
 971                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 972
 973                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 974                         nv50_display_unk10_handler(dev);
 975                 else
 976                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 977                         nv50_display_unk20_handler(dev);
 978                 else
 979                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 980                         nv50_display_unk40_handler(dev);
 981                 else
 982                         break;
 983         }
 984
 985         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 986 }
 987
 988 static void
 989 nv50_display_error_handler(struct drm_device *dev)
 990 {
 991         uint32_t addr, data;
 992
 993         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
 994         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
 995         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
 996
 997         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
 998                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 999
1000         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
1001 }
1002
1003 void
1004 nv50_display_irq_hotplug_bh(struct work_struct *work)
1005 {
1006         struct drm_nouveau_private *dev_priv =
1007                 container_of(work, struct drm_nouveau_private, hpd_work);
1008         struct drm_device *dev = dev_priv->dev;
1009         struct drm_connector *connector;
1010         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1011         uint32_t unplug_mask, plug_mask, change_mask;
1012         uint32_t hpd0, hpd1 = 0;
1013
1014         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1015         if (dev_priv->chipset >= 0x90)
1016                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1017
1018         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1019         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1020         change_mask = plug_mask | unplug_mask;
1021
1022         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1023                 struct drm_encoder_helper_funcs *helper;
1024                 struct nouveau_connector *nv_connector =
1025                         nouveau_connector(connector);
1026                 struct nouveau_encoder *nv_encoder;
1027                 struct dcb_gpio_entry *gpio;
1028                 uint32_t reg;
1029                 bool plugged;
1030
1031                 if (!nv_connector->dcb)
1032                         continue;
1033
1034                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1035                 if (!gpio || !(change_mask & (1 << gpio->line)))
1036                         continue;
1037
1038                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1039                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1040                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1041                         drm_get_connector_name(connector)) ;
1042
1043                 if (!connector->encoder || !connector->encoder->crtc ||
1044                     !connector->encoder->crtc->enabled)
1045                         continue;
1046                 nv_encoder = nouveau_encoder(connector->encoder);
1047                 helper = connector->encoder->helper_private;
1048
1049                 if (nv_encoder->dcb->type != OUTPUT_DP)
1050                         continue;
1051
1052                 if (plugged)
1053                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1054                 else
1055                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1056         }
1057
1058         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1059         if (dev_priv->chipset >= 0x90)
1060                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
1061
1062         drm_helper_hpd_irq_event(dev);
1063 }
1064
1065 void
1066 nv50_display_irq_handler(struct drm_device *dev)
1067 {
1068         struct drm_nouveau_private *dev_priv = dev->dev_private;
1069         uint32_t delayed = 0;
1070
1071         if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1072                 if (!work_pending(&dev_priv->hpd_work))
1073                         queue_work(dev_priv->wq, &dev_priv->hpd_work);
1074         }
1075
1076         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1077                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1078                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1079                 uint32_t clock;
1080
1081                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1082
1083                 if (!intr0 && !(intr1 & ~delayed))
1084                         break;
1085
1086                 if (intr0 & 0x00010000) {
1087                         nv50_display_error_handler(dev);
1088                         intr0 &= ~0x00010000;
1089                 }
1090
1091                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1092                         nv50_display_vblank_handler(dev, intr1);
1093                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1094                 }
1095
1096                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1097                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1098                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
1099                 if (clock) {
1100                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1101                         if (!work_pending(&dev_priv->irq_work))
1102                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
1103                         delayed |= clock;
1104                         intr1 &= ~clock;
1105                 }
1106
1107                 if (intr0) {
1108                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1109                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1110                 }
1111
1112                 if (intr1) {
1113                         NV_ERROR(dev,
1114                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1115                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1116                 }
1117         }
1118 }
1119