drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  28 #include "nv50_display.h"
  29 #include "nouveau_crtc.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_fb.h"
  33 #include "nouveau_fbcon.h"
  34 #include "nouveau_ramht.h"
  35 #include "drm_crtc_helper.h"
  36
  37 static void nv50_display_isr(struct drm_device *);
  38 static void nv50_display_bh(unsigned long);
  39
  40 static inline int
  41 nv50_sor_nr(struct drm_device *dev)
  42 {
  43         struct drm_nouveau_private *dev_priv = dev->dev_private;
  44
  45         if (dev_priv->chipset  < 0x90 ||
  46             dev_priv->chipset == 0x92 ||
  47             dev_priv->chipset == 0xa0)
  48                 return 2;
  49
  50         return 4;
  51 }
  52
  53 int
  54 nv50_display_early_init(struct drm_device *dev)
  55 {
  56         return 0;
  57 }
  58
  59 void
  60 nv50_display_late_takedown(struct drm_device *dev)
  61 {
  62 }
  63
  64 int
  65 nv50_display_init(struct drm_device *dev)
  66 {
  67         struct drm_nouveau_private *dev_priv = dev->dev_private;
  68         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
  69         struct drm_connector *connector;
  70         struct nouveau_channel *evo;
  71         int ret, i;
  72         u32 val;
  73
  74         NV_DEBUG_KMS(dev, "\n");
  75
  76         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
  77
  78         /*
  79          * I think the 0x006101XX range is some kind of main control area
  80          * that enables things.
  81          */
  82         /* CRTC? */
  83         for (i = 0; i < 2; i++) {
  84                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
  85                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
  86                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
  87                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
  88                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
  89                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
  90                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
  91                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
  92         }
  93
  94         /* DAC */
  95         for (i = 0; i < 3; i++) {
  96                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
  97                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
  98         }
  99
 100         /* SOR */
 101         for (i = 0; i < nv50_sor_nr(dev); i++) {
 102                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 103                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 104         }
 105
 106         /* EXT */
 107         for (i = 0; i < 3; i++) {
 108                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 109                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 110         }
 111
 112         for (i = 0; i < 3; i++) {
 113                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 114                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 115                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 116         }
 117
 118         /* The precise purpose is unknown, i suspect it has something to do
 119          * with text mode.
 120          */
 121         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 122                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 123                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 124                 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
 125                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 126                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 127                                                 nv_rd32(dev, 0x6194e8));
 128                         return -EBUSY;
 129                 }
 130         }
 131
 132         for (i = 0; i < 2; i++) {
 133                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 134                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 135                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 136                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 137                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 138                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 139                         return -EBUSY;
 140                 }
 141
 142                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 143                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 144                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 145                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 146                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 147                         NV_ERROR(dev, "timeout: "
 148                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 149                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 150                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 151                         return -EBUSY;
 152                 }
 153         }
 154
 155         nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 156         nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 157         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 158         nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 159         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
 160                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 161                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 162                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 163
 164         /* enable hotplug interrupts */
 165         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 166                 struct nouveau_connector *conn = nouveau_connector(connector);
 167
 168                 if (conn->dcb->gpio_tag == 0xff)
 169                         continue;
 170
 171                 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
 172         }
 173
 174         ret = nv50_evo_init(dev);
 175         if (ret)
 176                 return ret;
 177         evo = nv50_display(dev)->master;
 178
 179         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
 180
 181         ret = RING_SPACE(evo, 15);
 182         if (ret)
 183                 return ret;
 184         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 185         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 186         OUT_RING(evo, NvEvoSync);
 187         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 188         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 189         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 190         OUT_RING(evo, 0);
 191         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 192         OUT_RING(evo, 0);
 193         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 194         OUT_RING(evo, 0);
 195         /* required to make display sync channels not hate life */
 196         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK900), 1);
 197         OUT_RING  (evo, 0x00000311);
 198         BEGIN_RING(evo, 0, NV50_EVO_CRTC(1, UNK900), 1);
 199         OUT_RING  (evo, 0x00000311);
 200         FIRE_RING(evo);
 201         if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
 202                 NV_ERROR(dev, "evo pushbuf stalled\n");
 203
 204
 205         return 0;
 206 }
 207
 208 static int nv50_display_disable(struct drm_device *dev)
 209 {
 210         struct drm_nouveau_private *dev_priv = dev->dev_private;
 211         struct nv50_display *disp = nv50_display(dev);
 212         struct nouveau_channel *evo = disp->master;
 213         struct drm_crtc *drm_crtc;
 214         int ret, i;
 215
 216         NV_DEBUG_KMS(dev, "\n");
 217
 218         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 219                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 220
 221                 nv50_crtc_blank(crtc, true);
 222         }
 223
 224         ret = RING_SPACE(evo, 2);
 225         if (ret == 0) {
 226                 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
 227                 OUT_RING(evo, 0);
 228         }
 229         FIRE_RING(evo);
 230
 231         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 232          * cleaning up?
 233          */
 234         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 235                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 236                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 237
 238                 if (!crtc->base.enabled)
 239                         continue;
 240
 241                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 242                 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
 243                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 244                                       "0x%08x\n", mask, mask);
 245                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 246                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 247                 }
 248         }
 249
 250         nv50_evo_fini(dev);
 251
 252         for (i = 0; i < 3; i++) {
 253                 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 254                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 255                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 256                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 257                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 258                 }
 259         }
 260
 261         /* disable interrupts. */
 262         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 263
 264         /* disable hotplug interrupts */
 265         nv_wr32(dev, 0xe054, 0xffffffff);
 266         nv_wr32(dev, 0xe050, 0x00000000);
 267         if (dev_priv->chipset >= 0x90) {
 268                 nv_wr32(dev, 0xe074, 0xffffffff);
 269                 nv_wr32(dev, 0xe070, 0x00000000);
 270         }
 271         return 0;
 272 }
 273
 274 int nv50_display_create(struct drm_device *dev)
 275 {
 276         struct drm_nouveau_private *dev_priv = dev->dev_private;
 277         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 278         struct drm_connector *connector, *ct;
 279         struct nv50_display *priv;
 280         int ret, i;
 281
 282         NV_DEBUG_KMS(dev, "\n");
 283
 284         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 285         if (!priv)
 286                 return -ENOMEM;
 287         dev_priv->engine.display.priv = priv;
 288
 289         /* init basic kernel modesetting */
 290         drm_mode_config_init(dev);
 291
 292         /* Initialise some optional connector properties. */
 293         drm_mode_create_scaling_mode_property(dev);
 294         drm_mode_create_dithering_property(dev);
 295
 296         dev->mode_config.min_width = 0;
 297         dev->mode_config.min_height = 0;
 298
 299         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 300
 301         dev->mode_config.max_width = 8192;
 302         dev->mode_config.max_height = 8192;
 303
 304         dev->mode_config.fb_base = dev_priv->fb_phys;
 305
 306         /* Create CRTC objects */
 307         for (i = 0; i < 2; i++)
 308                 nv50_crtc_create(dev, i);
 309
 310         /* We setup the encoders from the BIOS table */
 311         for (i = 0 ; i < dcb->entries; i++) {
 312                 struct dcb_entry *entry = &dcb->entry[i];
 313
 314                 if (entry->location != DCB_LOC_ON_CHIP) {
 315                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 316                                 entry->type, ffs(entry->or) - 1);
 317                         continue;
 318                 }
 319
 320                 connector = nouveau_connector_create(dev, entry->connector);
 321                 if (IS_ERR(connector))
 322                         continue;
 323
 324                 switch (entry->type) {
 325                 case OUTPUT_TMDS:
 326                 case OUTPUT_LVDS:
 327                 case OUTPUT_DP:
 328                         nv50_sor_create(connector, entry);
 329                         break;
 330                 case OUTPUT_ANALOG:
 331                         nv50_dac_create(connector, entry);
 332                         break;
 333                 default:
 334                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 335                         continue;
 336                 }
 337         }
 338
 339         list_for_each_entry_safe(connector, ct,
 340                                  &dev->mode_config.connector_list, head) {
 341                 if (!connector->encoder_ids[0]) {
 342                         NV_WARN(dev, "%s has no encoders, removing\n",
 343                                 drm_get_connector_name(connector));
 344                         connector->funcs->destroy(connector);
 345                 }
 346         }
 347
 348         tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
 349         nouveau_irq_register(dev, 26, nv50_display_isr);
 350
 351         ret = nv50_display_init(dev);
 352         if (ret) {
 353                 nv50_display_destroy(dev);
 354                 return ret;
 355         }
 356
 357         return 0;
 358 }
 359
 360 void
 361 nv50_display_destroy(struct drm_device *dev)
 362 {
 363         struct nv50_display *disp = nv50_display(dev);
 364
 365         NV_DEBUG_KMS(dev, "\n");
 366
 367         drm_mode_config_cleanup(dev);
 368
 369         nv50_display_disable(dev);
 370         nouveau_irq_unregister(dev, 26);
 371         kfree(disp);
 372 }
 373
 374 void
 375 nv50_display_flip_stop(struct drm_crtc *crtc)
 376 {
 377         struct nv50_display *disp = nv50_display(crtc->dev);
 378         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 379         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 380         struct nouveau_channel *evo = dispc->sync;
 381         int ret;
 382
 383         ret = RING_SPACE(evo, 8);
 384         if (ret) {
 385                 WARN_ON(1);
 386                 return;
 387         }
 388
 389         BEGIN_RING(evo, 0, 0x0084, 1);
 390         OUT_RING  (evo, 0x00000000);
 391         BEGIN_RING(evo, 0, 0x0094, 1);
 392         OUT_RING  (evo, 0x00000000);
 393         BEGIN_RING(evo, 0, 0x00c0, 1);
 394         OUT_RING  (evo, 0x00000000);
 395         BEGIN_RING(evo, 0, 0x0080, 1);
 396         OUT_RING  (evo, 0x00000000);
 397         FIRE_RING (evo);
 398 }
 399
 400 int
 401 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 402                        struct nouveau_channel *chan)
 403 {
 404         struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
 405         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 406         struct nv50_display *disp = nv50_display(crtc->dev);
 407         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 408         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 409         struct nouveau_channel *evo = dispc->sync;
 410         int ret;
 411
 412         ret = RING_SPACE(evo, 24);
 413         if (unlikely(ret))
 414                 return ret;
 415
 416         /* synchronise with the rendering channel, if necessary */
 417         if (likely(chan)) {
 418                 u64 offset = dispc->sem.bo->vma.offset + dispc->sem.offset;
 419
 420                 ret = RING_SPACE(chan, 10);
 421                 if (ret) {
 422                         WIND_RING(evo);
 423                         return ret;
 424                 }
 425
 426                 if (dev_priv->chipset < 0xc0) {
 427                         BEGIN_RING(chan, NvSubSw, 0x0060, 2);
 428                         OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 429                         OUT_RING  (chan, dispc->sem.offset);
 430                         BEGIN_RING(chan, NvSubSw, 0x006c, 1);
 431                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 432                         BEGIN_RING(chan, NvSubSw, 0x0064, 2);
 433                         OUT_RING  (chan, dispc->sem.offset ^ 0x10);
 434                         OUT_RING  (chan, 0x74b1e000);
 435                         BEGIN_RING(chan, NvSubSw, 0x0060, 1);
 436                         if (dev_priv->chipset < 0x84)
 437                                 OUT_RING  (chan, NvSema);
 438                         else
 439                                 OUT_RING  (chan, chan->vram_handle);
 440                 } else {
 441                         BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
 442                         OUT_RING  (chan, upper_32_bits(offset));
 443                         OUT_RING  (chan, lower_32_bits(offset));
 444                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 445                         OUT_RING  (chan, 0x1002);
 446                         BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
 447                         OUT_RING  (chan, upper_32_bits(offset));
 448                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 449                         OUT_RING  (chan, 0x74b1e000);
 450                         OUT_RING  (chan, 0x1001);
 451                 }
 452                 FIRE_RING (chan);
 453         } else {
 454                 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
 455                                 0xf00d0000 | dispc->sem.value);
 456         }
 457
 458         /* queue the flip on the crtc's "display sync" channel */
 459         BEGIN_RING(evo, 0, 0x0100, 1);
 460         OUT_RING  (evo, 0xfffe0000);
 461         BEGIN_RING(evo, 0, 0x0084, 5);
 462         OUT_RING  (evo, chan ? 0x00000100 : 0x00000010);
 463         OUT_RING  (evo, dispc->sem.offset);
 464         OUT_RING  (evo, 0xf00d0000 | dispc->sem.value);
 465         OUT_RING  (evo, 0x74b1e000);
 466         OUT_RING  (evo, NvEvoSync);
 467         BEGIN_RING(evo, 0, 0x00a0, 2);
 468         OUT_RING  (evo, 0x00000000);
 469         OUT_RING  (evo, 0x00000000);
 470         BEGIN_RING(evo, 0, 0x00c0, 1);
 471         OUT_RING  (evo, nv_fb->r_dma);
 472         BEGIN_RING(evo, 0, 0x0110, 2);
 473         OUT_RING  (evo, 0x00000000);
 474         OUT_RING  (evo, 0x00000000);
 475         BEGIN_RING(evo, 0, 0x0800, 5);
 476         OUT_RING  (evo, (nv_fb->nvbo->bo.mem.start << PAGE_SHIFT) >> 8);
 477         OUT_RING  (evo, 0);
 478         OUT_RING  (evo, (fb->height << 16) | fb->width);
 479         OUT_RING  (evo, nv_fb->r_pitch);
 480         OUT_RING  (evo, nv_fb->r_format);
 481         BEGIN_RING(evo, 0, 0x0080, 1);
 482         OUT_RING  (evo, 0x00000000);
 483         FIRE_RING (evo);
 484
 485         dispc->sem.offset ^= 0x10;
 486         dispc->sem.value++;
 487         return 0;
 488 }
 489
 490 static u16
 491 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 492                            u32 mc, int pxclk)
 493 {
 494         struct drm_nouveau_private *dev_priv = dev->dev_private;
 495         struct nouveau_connector *nv_connector = NULL;
 496         struct drm_encoder *encoder;
 497         struct nvbios *bios = &dev_priv->vbios;
 498         u32 script = 0, or;
 499
 500         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 501                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 502
 503                 if (nv_encoder->dcb != dcb)
 504                         continue;
 505
 506                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 507                 break;
 508         }
 509
 510         or = ffs(dcb->or) - 1;
 511         switch (dcb->type) {
 512         case OUTPUT_LVDS:
 513                 script = (mc >> 8) & 0xf;
 514                 if (bios->fp_no_ddc) {
 515                         if (bios->fp.dual_link)
 516                                 script |= 0x0100;
 517                         if (bios->fp.if_is_24bit)
 518                                 script |= 0x0200;
 519                 } else {
 520                         if (pxclk >= bios->fp.duallink_transition_clk) {
 521                                 script |= 0x0100;
 522                                 if (bios->fp.strapless_is_24bit & 2)
 523                                         script |= 0x0200;
 524                         } else
 525                         if (bios->fp.strapless_is_24bit & 1)
 526                                 script |= 0x0200;
 527
 528                         if (nv_connector && nv_connector->edid &&
 529                             (nv_connector->edid->revision >= 4) &&
 530                             (nv_connector->edid->input & 0x70) >= 0x20)
 531                                 script |= 0x0200;
 532                 }
 533
 534                 if (nouveau_uscript_lvds >= 0) {
 535                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 536                                      "for output LVDS-%d\n", script,
 537                                      nouveau_uscript_lvds, or);
 538                         script = nouveau_uscript_lvds;
 539                 }
 540                 break;
 541         case OUTPUT_TMDS:
 542                 script = (mc >> 8) & 0xf;
 543                 if (pxclk >= 165000)
 544                         script |= 0x0100;
 545
 546                 if (nouveau_uscript_tmds >= 0) {
 547                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 548                                      "for output TMDS-%d\n", script,
 549                                      nouveau_uscript_tmds, or);
 550                         script = nouveau_uscript_tmds;
 551                 }
 552                 break;
 553         case OUTPUT_DP:
 554                 script = (mc >> 8) & 0xf;
 555                 break;
 556         case OUTPUT_ANALOG:
 557                 script = 0xff;
 558                 break;
 559         default:
 560                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 561                 break;
 562         }
 563
 564         return script;
 565 }
 566
 567 static void
 568 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 569 {
 570         struct drm_nouveau_private *dev_priv = dev->dev_private;
 571         struct nouveau_channel *chan, *tmp;
 572
 573         list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
 574                                  nvsw.vbl_wait) {
 575                 if (chan->nvsw.vblsem_head != crtc)
 576                         continue;
 577
 578                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 579                                                 chan->nvsw.vblsem_rval);
 580                 list_del(&chan->nvsw.vbl_wait);
 581                 drm_vblank_put(dev, crtc);
 582         }
 583
 584         drm_handle_vblank(dev, crtc);
 585 }
 586
 587 static void
 588 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 589 {
 590         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 591                 nv50_display_vblank_crtc_handler(dev, 0);
 592
 593         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 594                 nv50_display_vblank_crtc_handler(dev, 1);
 595
 596         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
 597 }
 598
 599 static void
 600 nv50_display_unk10_handler(struct drm_device *dev)
 601 {
 602         struct drm_nouveau_private *dev_priv = dev->dev_private;
 603         struct nv50_display *disp = nv50_display(dev);
 604         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 605         int i, crtc, or, type = OUTPUT_ANY;
 606
 607         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 608         disp->irq.dcb = NULL;
 609
 610         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 611
 612         /* Determine which CRTC we're dealing with, only 1 ever will be
 613          * signalled at the same time with the current nouveau code.
 614          */
 615         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 616         if (crtc < 0)
 617                 goto ack;
 618
 619         /* Nothing needs to be done for the encoder */
 620         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 621         if (crtc < 0)
 622                 goto ack;
 623
 624         /* Find which encoder was connected to the CRTC */
 625         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 626                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 627                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 628                 if (!(mc & (1 << crtc)))
 629                         continue;
 630
 631                 switch ((mc & 0x00000f00) >> 8) {
 632                 case 0: type = OUTPUT_ANALOG; break;
 633                 case 1: type = OUTPUT_TV; break;
 634                 default:
 635                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 636                         goto ack;
 637                 }
 638
 639                 or = i;
 640         }
 641
 642         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 643                 if (dev_priv->chipset  < 0x90 ||
 644                     dev_priv->chipset == 0x92 ||
 645                     dev_priv->chipset == 0xa0)
 646                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 647                 else
 648                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 649
 650                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 651                 if (!(mc & (1 << crtc)))
 652                         continue;
 653
 654                 switch ((mc & 0x00000f00) >> 8) {
 655                 case 0: type = OUTPUT_LVDS; break;
 656                 case 1: type = OUTPUT_TMDS; break;
 657                 case 2: type = OUTPUT_TMDS; break;
 658                 case 5: type = OUTPUT_TMDS; break;
 659                 case 8: type = OUTPUT_DP; break;
 660                 case 9: type = OUTPUT_DP; break;
 661                 default:
 662                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 663                         goto ack;
 664                 }
 665
 666                 or = i;
 667         }
 668
 669         /* There was no encoder to disable */
 670         if (type == OUTPUT_ANY)
 671                 goto ack;
 672
 673         /* Disable the encoder */
 674         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 675                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 676
 677                 if (dcb->type == type && (dcb->or & (1 << or))) {
 678                         nouveau_bios_run_display_table(dev, dcb, 0, -1);
 679                         disp->irq.dcb = dcb;
 680                         goto ack;
 681                 }
 682         }
 683
 684         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 685 ack:
 686         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 687         nv_wr32(dev, 0x610030, 0x80000000);
 688 }
 689
 690 static void
 691 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 692 {
 693         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 694         struct drm_encoder *encoder;
 695         uint32_t tmp, unk0 = 0, unk1 = 0;
 696
 697         if (dcb->type != OUTPUT_DP)
 698                 return;
 699
 700         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 701                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 702
 703                 if (nv_encoder->dcb == dcb) {
 704                         unk0 = nv_encoder->dp.unk0;
 705                         unk1 = nv_encoder->dp.unk1;
 706                         break;
 707                 }
 708         }
 709
 710         if (unk0 || unk1) {
 711                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 712                 tmp &= 0xfffffe03;
 713                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 714
 715                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 716                 tmp &= 0xfef080c0;
 717                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 718         }
 719 }
 720
 721 static void
 722 nv50_display_unk20_handler(struct drm_device *dev)
 723 {
 724         struct drm_nouveau_private *dev_priv = dev->dev_private;
 725         struct nv50_display *disp = nv50_display(dev);
 726         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
 727         struct dcb_entry *dcb;
 728         int i, crtc, or, type = OUTPUT_ANY;
 729
 730         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 731         dcb = disp->irq.dcb;
 732         if (dcb) {
 733                 nouveau_bios_run_display_table(dev, dcb, 0, -2);
 734                 disp->irq.dcb = NULL;
 735         }
 736
 737         /* CRTC clock change requested? */
 738         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 739         if (crtc >= 0) {
 740                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 741                 pclk &= 0x003fffff;
 742
 743                 nv50_crtc_set_clock(dev, crtc, pclk);
 744
 745                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 746                 tmp &= ~0x000000f;
 747                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 748         }
 749
 750         /* Nothing needs to be done for the encoder */
 751         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 752         if (crtc < 0)
 753                 goto ack;
 754         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 755
 756         /* Find which encoder is connected to the CRTC */
 757         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 758                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 759                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 760                 if (!(mc & (1 << crtc)))
 761                         continue;
 762
 763                 switch ((mc & 0x00000f00) >> 8) {
 764                 case 0: type = OUTPUT_ANALOG; break;
 765                 case 1: type = OUTPUT_TV; break;
 766                 default:
 767                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 768                         goto ack;
 769                 }
 770
 771                 or = i;
 772         }
 773
 774         for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 775                 if (dev_priv->chipset  < 0x90 ||
 776                     dev_priv->chipset == 0x92 ||
 777                     dev_priv->chipset == 0xa0)
 778                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 779                 else
 780                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 781
 782                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 783                 if (!(mc & (1 << crtc)))
 784                         continue;
 785
 786                 switch ((mc & 0x00000f00) >> 8) {
 787                 case 0: type = OUTPUT_LVDS; break;
 788                 case 1: type = OUTPUT_TMDS; break;
 789                 case 2: type = OUTPUT_TMDS; break;
 790                 case 5: type = OUTPUT_TMDS; break;
 791                 case 8: type = OUTPUT_DP; break;
 792                 case 9: type = OUTPUT_DP; break;
 793                 default:
 794                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 795                         goto ack;
 796                 }
 797
 798                 or = i;
 799         }
 800
 801         if (type == OUTPUT_ANY)
 802                 goto ack;
 803
 804         /* Enable the encoder */
 805         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 806                 dcb = &dev_priv->vbios.dcb.entry[i];
 807                 if (dcb->type == type && (dcb->or & (1 << or)))
 808                         break;
 809         }
 810
 811         if (i == dev_priv->vbios.dcb.entries) {
 812                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 813                 goto ack;
 814         }
 815
 816         script = nv50_display_script_select(dev, dcb, mc, pclk);
 817         nouveau_bios_run_display_table(dev, dcb, script, pclk);
 818
 819         nv50_display_unk20_dp_hack(dev, dcb);
 820
 821         if (dcb->type != OUTPUT_ANALOG) {
 822                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 823                 tmp &= ~0x00000f0f;
 824                 if (script & 0x0100)
 825                         tmp |= 0x00000101;
 826                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 827         } else {
 828                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 829         }
 830
 831         disp->irq.dcb = dcb;
 832         disp->irq.pclk = pclk;
 833         disp->irq.script = script;
 834
 835 ack:
 836         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 837         nv_wr32(dev, 0x610030, 0x80000000);
 838 }
 839
 840 /* If programming a TMDS output on a SOR that can also be configured for
 841  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 842  *
 843  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 844  * the VBIOS scripts on at least one board I have only switch it off on
 845  * link 0, causing a blank display if the output has previously been
 846  * programmed for DisplayPort.
 847  */
 848 static void
 849 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 850 {
 851         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 852         struct drm_encoder *encoder;
 853         u32 tmp;
 854
 855         if (dcb->type != OUTPUT_TMDS)
 856                 return;
 857
 858         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 859                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 860
 861                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 862                     nv_encoder->dcb->or & (1 << or)) {
 863                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 864                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 865                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 866                         break;
 867                 }
 868         }
 869 }
 870
 871 static void
 872 nv50_display_unk40_handler(struct drm_device *dev)
 873 {
 874         struct nv50_display *disp = nv50_display(dev);
 875         struct dcb_entry *dcb = disp->irq.dcb;
 876         u16 script = disp->irq.script;
 877         u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
 878
 879         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 880         disp->irq.dcb = NULL;
 881         if (!dcb)
 882                 goto ack;
 883
 884         nouveau_bios_run_display_table(dev, dcb, script, -pclk);
 885         nv50_display_unk40_dp_set_tmds(dev, dcb);
 886
 887 ack:
 888         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 889         nv_wr32(dev, 0x610030, 0x80000000);
 890         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 891 }
 892
 893 static void
 894 nv50_display_bh(unsigned long data)
 895 {
 896         struct drm_device *dev = (struct drm_device *)data;
 897
 898         for (;;) {
 899                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 900                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 901
 902                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 903
 904                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 905                         nv50_display_unk10_handler(dev);
 906                 else
 907                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 908                         nv50_display_unk20_handler(dev);
 909                 else
 910                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 911                         nv50_display_unk40_handler(dev);
 912                 else
 913                         break;
 914         }
 915
 916         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 917 }
 918
 919 static void
 920 nv50_display_error_handler(struct drm_device *dev)
 921 {
 922         u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 923         u32 addr, data;
 924         int chid;
 925
 926         for (chid = 0; chid < 5; chid++) {
 927                 if (!(channels & (1 << chid)))
 928                         continue;
 929
 930                 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 931                 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 932                 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
 933                 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 934                               "(0x%04x 0x%02x)\n", chid,
 935                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 936
 937                 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 938         }
 939 }
 940
 941 static void
 942 nv50_display_isr(struct drm_device *dev)
 943 {
 944         struct nv50_display *disp = nv50_display(dev);
 945         uint32_t delayed = 0;
 946
 947         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 948                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 949                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 950                 uint32_t clock;
 951
 952                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 953
 954                 if (!intr0 && !(intr1 & ~delayed))
 955                         break;
 956
 957                 if (intr0 & 0x001f0000) {
 958                         nv50_display_error_handler(dev);
 959                         intr0 &= ~0x001f0000;
 960                 }
 961
 962                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 963                         nv50_display_vblank_handler(dev, intr1);
 964                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 965                 }
 966
 967                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 968                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 969                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 970                 if (clock) {
 971                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 972                         tasklet_schedule(&disp->tasklet);
 973                         delayed |= clock;
 974                         intr1 &= ~clock;
 975                 }
 976
 977                 if (intr0) {
 978                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 979                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
 980                 }
 981
 982                 if (intr1) {
 983                         NV_ERROR(dev,
 984                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
 985                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
 986                 }
 987         }
 988 }