drivers/gpu/drm/nouveau/nv40_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_grctx.h"
  31 #include "nouveau_ramht.h"
  32
  33 struct nv40_graph_engine {
  34         struct nouveau_exec_engine base;
  35         u32 grctx_size;
  36 };
  37
  38 static struct nouveau_channel *
  39 nv40_graph_channel(struct drm_device *dev)
  40 {
  41         struct drm_nouveau_private *dev_priv = dev->dev_private;
  42         struct nouveau_gpuobj *grctx;
  43         uint32_t inst;
  44         int i;
  45
  46         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
  47         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
  48                 return NULL;
  49         inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
  50
  51         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  52                 if (!dev_priv->channels.ptr[i])
  53                         continue;
  54
  55                 grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
  56                 if (grctx && grctx->pinst == inst)
  57                         return dev_priv->channels.ptr[i];
  58         }
  59
  60         return NULL;
  61 }
  62
  63 static int
  64 nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
  65 {
  66         uint32_t old_cp, tv = 1000, tmp;
  67         int i;
  68
  69         old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
  70         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
  71
  72         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
  73         tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
  74                       NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
  75         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
  76
  77         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
  78         tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
  79         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
  80
  81         nouveau_wait_for_idle(dev);
  82
  83         for (i = 0; i < tv; i++) {
  84                 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
  85                         break;
  86         }
  87
  88         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
  89
  90         if (i == tv) {
  91                 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
  92                 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
  93                 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
  94                          ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
  95                          ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
  96                 NV_ERROR(dev, "0x40030C = 0x%08x\n",
  97                          nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
  98                 return -EBUSY;
  99         }
 100
 101         return 0;
 102 }
 103
 104 static int
 105 nv40_graph_unload_context(struct drm_device *dev)
 106 {
 107         uint32_t inst;
 108         int ret;
 109
 110         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
 111         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
 112                 return 0;
 113         inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
 114
 115         ret = nv40_graph_transfer_context(dev, inst, 1);
 116
 117         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
 118         return ret;
 119 }
 120
 121 static int
 122 nv40_graph_context_new(struct nouveau_channel *chan, int engine)
 123 {
 124         struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
 125         struct drm_device *dev = chan->dev;
 126         struct drm_nouveau_private *dev_priv = dev->dev_private;
 127         struct nouveau_gpuobj *grctx = NULL;
 128         struct nouveau_grctx ctx = {};
 129         unsigned long flags;
 130         int ret;
 131
 132         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
 133                                  NVOBJ_FLAG_ZERO_ALLOC, &grctx);
 134         if (ret)
 135                 return ret;
 136
 137         /* Initialise default context values */
 138         ctx.dev = chan->dev;
 139         ctx.mode = NOUVEAU_GRCTX_VALS;
 140         ctx.data = grctx;
 141         nv40_grctx_init(&ctx);
 142
 143         nv_wo32(grctx, 0, grctx->vinst);
 144
 145         /* init grctx pointer in ramfc, and on PFIFO if channel is
 146          * already active there
 147          */
 148         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 149         nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
 150         nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
 151         if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
 152                 nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
 153         nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
 154         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 155
 156         chan->engctx[engine] = grctx;
 157         return 0;
 158 }
 159
 160 static void
 161 nv40_graph_context_del(struct nouveau_channel *chan, int engine)
 162 {
 163         struct nouveau_gpuobj *grctx = chan->engctx[engine];
 164         struct drm_device *dev = chan->dev;
 165         struct drm_nouveau_private *dev_priv = dev->dev_private;
 166         unsigned long flags;
 167
 168         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 169         nv04_graph_fifo_access(dev, false);
 170
 171         /* Unload the context if it's the currently active one */
 172         if (nv40_graph_channel(dev) == chan)
 173                 nv40_graph_unload_context(dev);
 174
 175         nv04_graph_fifo_access(dev, true);
 176         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 177
 178         /* Free the context resources */
 179         nouveau_gpuobj_ref(NULL, &grctx);
 180         chan->engctx[engine] = NULL;
 181 }
 182
 183 int
 184 nv40_graph_object_new(struct nouveau_channel *chan, int engine,
 185                       u32 handle, u16 class)
 186 {
 187         struct drm_device *dev = chan->dev;
 188         struct nouveau_gpuobj *obj = NULL;
 189         int ret;
 190
 191         ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 192         if (ret)
 193                 return ret;
 194         obj->engine = 1;
 195         obj->class  = class;
 196
 197         nv_wo32(obj, 0x00, class);
 198         nv_wo32(obj, 0x04, 0x00000000);
 199 #ifndef __BIG_ENDIAN
 200         nv_wo32(obj, 0x08, 0x00000000);
 201 #else
 202         nv_wo32(obj, 0x08, 0x01000000);
 203 #endif
 204         nv_wo32(obj, 0x0c, 0x00000000);
 205         nv_wo32(obj, 0x10, 0x00000000);
 206
 207         ret = nouveau_ramht_insert(chan, handle, obj);
 208         nouveau_gpuobj_ref(NULL, &obj);
 209         return ret;
 210 }
 211
 212 static void
 213 nv40_graph_set_tile_region(struct drm_device *dev, int i)
 214 {
 215         struct drm_nouveau_private *dev_priv = dev->dev_private;
 216         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 217
 218         switch (dev_priv->chipset) {
 219         case 0x40:
 220         case 0x41: /* guess */
 221         case 0x42:
 222         case 0x43:
 223         case 0x45: /* guess */
 224         case 0x4e:
 225                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 226                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 227                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 228                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 229                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 230                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 231                 break;
 232         case 0x44:
 233         case 0x4a:
 234                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 235                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 236                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 237                 break;
 238         case 0x46:
 239         case 0x47:
 240         case 0x49:
 241         case 0x4b:
 242         case 0x4c:
 243         case 0x67:
 244         default:
 245                 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
 246                 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
 247                 nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
 248                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 249                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 250                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 251                 break;
 252         }
 253 }
 254
 255 /*
 256  * G70          0x47
 257  * G71          0x49
 258  * NV45         0x48
 259  * G72[M]       0x46
 260  * G73          0x4b
 261  * C51_G7X      0x4c
 262  * C51          0x4e
 263  */
 264 int
 265 nv40_graph_init(struct drm_device *dev, int engine)
 266 {
 267         struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
 268         struct drm_nouveau_private *dev_priv = dev->dev_private;
 269         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 270         struct nouveau_grctx ctx = {};
 271         uint32_t vramsz, *cp;
 272         int i, j;
 273
 274         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
 275                         ~NV_PMC_ENABLE_PGRAPH);
 276         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 277                          NV_PMC_ENABLE_PGRAPH);
 278
 279         cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
 280         if (!cp)
 281                 return -ENOMEM;
 282
 283         ctx.dev = dev;
 284         ctx.mode = NOUVEAU_GRCTX_PROG;
 285         ctx.data = cp;
 286         ctx.ctxprog_max = 256;
 287         nv40_grctx_init(&ctx);
 288         pgraph->grctx_size = ctx.ctxvals_pos * 4;
 289
 290         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 291         for (i = 0; i < ctx.ctxprog_len; i++)
 292                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 293
 294         kfree(cp);
 295
 296         /* No context present currently */
 297         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 298
 299         nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 300         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 301
 302         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 303         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
 304         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 305         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
 306         nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
 307         nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 308
 309         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 310         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 311
 312         j = nv_rd32(dev, 0x1540) & 0xff;
 313         if (j) {
 314                 for (i = 0; !(j & 1); j >>= 1, i++)
 315                         ;
 316                 nv_wr32(dev, 0x405000, i);
 317         }
 318
 319         if (dev_priv->chipset == 0x40) {
 320                 nv_wr32(dev, 0x4009b0, 0x83280fff);
 321                 nv_wr32(dev, 0x4009b4, 0x000000a0);
 322         } else {
 323                 nv_wr32(dev, 0x400820, 0x83280eff);
 324                 nv_wr32(dev, 0x400824, 0x000000a0);
 325         }
 326
 327         switch (dev_priv->chipset) {
 328         case 0x40:
 329         case 0x45:
 330                 nv_wr32(dev, 0x4009b8, 0x0078e366);
 331                 nv_wr32(dev, 0x4009bc, 0x0000014c);
 332                 break;
 333         case 0x41:
 334         case 0x42: /* pciid also 0x00Cx */
 335         /* case 0x0120: XXX (pciid) */
 336                 nv_wr32(dev, 0x400828, 0x007596ff);
 337                 nv_wr32(dev, 0x40082c, 0x00000108);
 338                 break;
 339         case 0x43:
 340                 nv_wr32(dev, 0x400828, 0x0072cb77);
 341                 nv_wr32(dev, 0x40082c, 0x00000108);
 342                 break;
 343         case 0x44:
 344         case 0x46: /* G72 */
 345         case 0x4a:
 346         case 0x4c: /* G7x-based C51 */
 347         case 0x4e:
 348                 nv_wr32(dev, 0x400860, 0);
 349                 nv_wr32(dev, 0x400864, 0);
 350                 break;
 351         case 0x47: /* G70 */
 352         case 0x49: /* G71 */
 353         case 0x4b: /* G73 */
 354                 nv_wr32(dev, 0x400828, 0x07830610);
 355                 nv_wr32(dev, 0x40082c, 0x0000016A);
 356                 break;
 357         default:
 358                 break;
 359         }
 360
 361         nv_wr32(dev, 0x400b38, 0x2ffff800);
 362         nv_wr32(dev, 0x400b3c, 0x00006000);
 363
 364         /* Tiling related stuff. */
 365         switch (dev_priv->chipset) {
 366         case 0x44:
 367         case 0x4a:
 368                 nv_wr32(dev, 0x400bc4, 0x1003d888);
 369                 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
 370                 break;
 371         case 0x46:
 372                 nv_wr32(dev, 0x400bc4, 0x0000e024);
 373                 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
 374                 break;
 375         case 0x4c:
 376         case 0x4e:
 377         case 0x67:
 378                 nv_wr32(dev, 0x400bc4, 0x1003d888);
 379                 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
 380                 break;
 381         default:
 382                 break;
 383         }
 384
 385         /* Turn all the tiling regions off. */
 386         for (i = 0; i < pfb->num_tiles; i++)
 387                 nv40_graph_set_tile_region(dev, i);
 388
 389         /* begin RAM config */
 390         vramsz = pci_resource_len(dev->pdev, 0) - 1;
 391         switch (dev_priv->chipset) {
 392         case 0x40:
 393                 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
 394                 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
 395                 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
 396                 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
 397                 nv_wr32(dev, 0x400820, 0);
 398                 nv_wr32(dev, 0x400824, 0);
 399                 nv_wr32(dev, 0x400864, vramsz);
 400                 nv_wr32(dev, 0x400868, vramsz);
 401                 break;
 402         default:
 403                 switch (dev_priv->chipset) {
 404                 case 0x41:
 405                 case 0x42:
 406                 case 0x43:
 407                 case 0x45:
 408                 case 0x4e:
 409                 case 0x44:
 410                 case 0x4a:
 411                         nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
 412                         nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
 413                         break;
 414                 default:
 415                         nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
 416                         nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
 417                         break;
 418                 }
 419                 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
 420                 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
 421                 nv_wr32(dev, 0x400840, 0);
 422                 nv_wr32(dev, 0x400844, 0);
 423                 nv_wr32(dev, 0x4008A0, vramsz);
 424                 nv_wr32(dev, 0x4008A4, vramsz);
 425                 break;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int
 432 nv40_graph_fini(struct drm_device *dev, int engine)
 433 {
 434         nv40_graph_unload_context(dev);
 435         return 0;
 436 }
 437
 438 static int
 439 nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
 440 {
 441         struct drm_nouveau_private *dev_priv = dev->dev_private;
 442         struct nouveau_gpuobj *grctx;
 443         unsigned long flags;
 444         int i;
 445
 446         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 447         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 448                 if (!dev_priv->channels.ptr[i])
 449                         continue;
 450                 grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
 451
 452                 if (grctx && grctx->pinst == inst)
 453                         break;
 454         }
 455         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 456         return i;
 457 }
 458
 459 static void
 460 nv40_graph_isr(struct drm_device *dev)
 461 {
 462         u32 stat;
 463
 464         while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
 465                 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
 466                 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
 467                 u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
 468                 u32 chid = nv40_graph_isr_chid(dev, inst);
 469                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 470                 u32 subc = (addr & 0x00070000) >> 16;
 471                 u32 mthd = (addr & 0x00001ffc);
 472                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 473                 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
 474                 u32 show = stat;
 475
 476                 if (stat & NV_PGRAPH_INTR_ERROR) {
 477                         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 478                                 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
 479                                         show &= ~NV_PGRAPH_INTR_ERROR;
 480                         } else
 481                         if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
 482                                 nv_mask(dev, 0x402000, 0, 0);
 483                         }
 484                 }
 485
 486                 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
 487                 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
 488
 489                 if (show && nouveau_ratelimit()) {
 490                         NV_INFO(dev, "PGRAPH -");
 491                         nouveau_bitfield_print(nv10_graph_intr, show);
 492                         printk(" nsource:");
 493                         nouveau_bitfield_print(nv04_graph_nsource, nsource);
 494                         printk(" nstatus:");
 495                         nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
 496                         printk("\n");
 497                         NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
 498                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
 499                                 chid, inst, subc, class, mthd, data);
 500                 }
 501         }
 502 }
 503
 504 static void
 505 nv40_graph_destroy(struct drm_device *dev, int engine)
 506 {
 507         struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
 508
 509         nouveau_irq_unregister(dev, 12);
 510
 511         NVOBJ_ENGINE_DEL(dev, GR);
 512         kfree(pgraph);
 513 }
 514
 515 int
 516 nv40_graph_create(struct drm_device *dev)
 517 {
 518         struct nv40_graph_engine *pgraph;
 519
 520         pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
 521         if (!pgraph)
 522                 return -ENOMEM;
 523
 524         pgraph->base.destroy = nv40_graph_destroy;
 525         pgraph->base.init = nv40_graph_init;
 526         pgraph->base.fini = nv40_graph_fini;
 527         pgraph->base.context_new = nv40_graph_context_new;
 528         pgraph->base.context_del = nv40_graph_context_del;
 529         pgraph->base.object_new = nv40_graph_object_new;
 530         pgraph->base.set_tile_region = nv40_graph_set_tile_region;
 531
 532         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
 533         nouveau_irq_register(dev, 12, nv40_graph_isr);
 534
 535         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
 536         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 537         NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
 538         NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
 539         NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
 540         NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
 541         NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
 542         NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
 543         NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
 544         NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
 545         NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
 546         NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
 547         NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
 548         NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
 549         NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
 550         NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
 551
 552         /* curie */
 553         if (nv44_graph_class(dev))
 554                 NVOBJ_CLASS(dev, 0x4497, GR);
 555         else
 556                 NVOBJ_CLASS(dev, 0x4097, GR);
 557
 558         /* nvsw */
 559         NVOBJ_CLASS(dev, 0x506e, SW);
 560         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
 561         return 0;
 562 }