drivers/gpu/drm/nouveau/nv40_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_grctx.h"
  31
  32 struct nouveau_channel *
  33 nv40_graph_channel(struct drm_device *dev)
  34 {
  35         struct drm_nouveau_private *dev_priv = dev->dev_private;
  36         uint32_t inst;
  37         int i;
  38
  39         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
  40         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
  41                 return NULL;
  42         inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
  43
  44         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  45                 struct nouveau_channel *chan = dev_priv->fifos[i];
  46
  47                 if (chan && chan->ramin_grctx &&
  48                     chan->ramin_grctx->instance == inst)
  49                         return chan;
  50         }
  51
  52         return NULL;
  53 }
  54
  55 int
  56 nv40_graph_create_context(struct nouveau_channel *chan)
  57 {
  58         struct drm_device *dev = chan->dev;
  59         struct drm_nouveau_private *dev_priv = dev->dev_private;
  60         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  61         int ret;
  62
  63         ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
  64                                      16, NVOBJ_FLAG_ZERO_ALLOC,
  65                                      &chan->ramin_grctx);
  66         if (ret)
  67                 return ret;
  68
  69         /* Initialise default context values */
  70         dev_priv->engine.instmem.prepare_access(dev, true);
  71         if (!pgraph->ctxprog) {
  72                 struct nouveau_grctx ctx = {};
  73
  74                 ctx.dev = chan->dev;
  75                 ctx.mode = NOUVEAU_GRCTX_VALS;
  76                 ctx.data = chan->ramin_grctx->gpuobj;
  77                 nv40_grctx_init(&ctx);
  78         } else {
  79                 nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
  80         }
  81         nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
  82                      chan->ramin_grctx->gpuobj->im_pramin->start);
  83         dev_priv->engine.instmem.finish_access(dev);
  84         return 0;
  85 }
  86
  87 void
  88 nv40_graph_destroy_context(struct nouveau_channel *chan)
  89 {
  90         nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx);
  91 }
  92
  93 static int
  94 nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
  95 {
  96         uint32_t old_cp, tv = 1000, tmp;
  97         int i;
  98
  99         old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
 100         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
 101
 102         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
 103         tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
 104                       NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
 105         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
 106
 107         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
 108         tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
 109         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
 110
 111         nouveau_wait_for_idle(dev);
 112
 113         for (i = 0; i < tv; i++) {
 114                 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
 115                         break;
 116         }
 117
 118         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
 119
 120         if (i == tv) {
 121                 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
 122                 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
 123                 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
 124                          ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
 125                          ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
 126                 NV_ERROR(dev, "0x40030C = 0x%08x\n",
 127                          nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
 128                 return -EBUSY;
 129         }
 130
 131         return 0;
 132 }
 133
 134 /* Restore the context for a specific channel into PGRAPH */
 135 int
 136 nv40_graph_load_context(struct nouveau_channel *chan)
 137 {
 138         struct drm_device *dev = chan->dev;
 139         uint32_t inst;
 140         int ret;
 141
 142         if (!chan->ramin_grctx)
 143                 return -EINVAL;
 144         inst = chan->ramin_grctx->instance >> 4;
 145
 146         ret = nv40_graph_transfer_context(dev, inst, 0);
 147         if (ret)
 148                 return ret;
 149
 150         /* 0x40032C, no idea of it's exact function.  Could simply be a
 151          * record of the currently active PGRAPH context.  It's currently
 152          * unknown as to what bit 24 does.  The nv ddx has it set, so we will
 153          * set it here too.
 154          */
 155         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
 156         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
 157                  (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
 158                   NV40_PGRAPH_CTXCTL_CUR_LOADED);
 159         /* 0x32E0 records the instance address of the active FIFO's PGRAPH
 160          * context.  If at any time this doesn't match 0x40032C, you will
 161          * recieve PGRAPH_INTR_CONTEXT_SWITCH
 162          */
 163         nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
 164         return 0;
 165 }
 166
 167 int
 168 nv40_graph_unload_context(struct drm_device *dev)
 169 {
 170         uint32_t inst;
 171         int ret;
 172
 173         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
 174         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
 175                 return 0;
 176         inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
 177
 178         ret = nv40_graph_transfer_context(dev, inst, 1);
 179
 180         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
 181         return ret;
 182 }
 183
 184 /*
 185  * G70          0x47
 186  * G71          0x49
 187  * NV45         0x48
 188  * G72[M]       0x46
 189  * G73          0x4b
 190  * C51_G7X      0x4c
 191  * C51          0x4e
 192  */
 193 int
 194 nv40_graph_init(struct drm_device *dev)
 195 {
 196         struct drm_nouveau_private *dev_priv =
 197                 (struct drm_nouveau_private *)dev->dev_private;
 198         uint32_t vramsz, tmp;
 199         int i, j;
 200
 201         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
 202                         ~NV_PMC_ENABLE_PGRAPH);
 203         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 204                          NV_PMC_ENABLE_PGRAPH);
 205
 206         if (nouveau_ctxfw) {
 207                 nouveau_grctx_prog_load(dev);
 208                 dev_priv->engine.graph.grctx_size = 175 * 1024;
 209         }
 210
 211         if (!dev_priv->engine.graph.ctxprog) {
 212                 struct nouveau_grctx ctx = {};
 213                 uint32_t cp[256];
 214
 215                 ctx.dev = dev;
 216                 ctx.mode = NOUVEAU_GRCTX_PROG;
 217                 ctx.data = cp;
 218                 ctx.ctxprog_max = 256;
 219                 nv40_grctx_init(&ctx);
 220                 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 221
 222                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 223                 for (i = 0; i < ctx.ctxprog_len; i++)
 224                         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 225         }
 226
 227         /* No context present currently */
 228         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 229
 230         nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 231         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 232
 233         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 234         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
 235         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 236         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
 237         nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
 238         nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 239
 240         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 241         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 242
 243         j = nv_rd32(dev, 0x1540) & 0xff;
 244         if (j) {
 245                 for (i = 0; !(j & 1); j >>= 1, i++)
 246                         ;
 247                 nv_wr32(dev, 0x405000, i);
 248         }
 249
 250         if (dev_priv->chipset == 0x40) {
 251                 nv_wr32(dev, 0x4009b0, 0x83280fff);
 252                 nv_wr32(dev, 0x4009b4, 0x000000a0);
 253         } else {
 254                 nv_wr32(dev, 0x400820, 0x83280eff);
 255                 nv_wr32(dev, 0x400824, 0x000000a0);
 256         }
 257
 258         switch (dev_priv->chipset) {
 259         case 0x40:
 260         case 0x45:
 261                 nv_wr32(dev, 0x4009b8, 0x0078e366);
 262                 nv_wr32(dev, 0x4009bc, 0x0000014c);
 263                 break;
 264         case 0x41:
 265         case 0x42: /* pciid also 0x00Cx */
 266         /* case 0x0120: XXX (pciid) */
 267                 nv_wr32(dev, 0x400828, 0x007596ff);
 268                 nv_wr32(dev, 0x40082c, 0x00000108);
 269                 break;
 270         case 0x43:
 271                 nv_wr32(dev, 0x400828, 0x0072cb77);
 272                 nv_wr32(dev, 0x40082c, 0x00000108);
 273                 break;
 274         case 0x44:
 275         case 0x46: /* G72 */
 276         case 0x4a:
 277         case 0x4c: /* G7x-based C51 */
 278         case 0x4e:
 279                 nv_wr32(dev, 0x400860, 0);
 280                 nv_wr32(dev, 0x400864, 0);
 281                 break;
 282         case 0x47: /* G70 */
 283         case 0x49: /* G71 */
 284         case 0x4b: /* G73 */
 285                 nv_wr32(dev, 0x400828, 0x07830610);
 286                 nv_wr32(dev, 0x40082c, 0x0000016A);
 287                 break;
 288         default:
 289                 break;
 290         }
 291
 292         nv_wr32(dev, 0x400b38, 0x2ffff800);
 293         nv_wr32(dev, 0x400b3c, 0x00006000);
 294
 295         /* copy tile info from PFB */
 296         switch (dev_priv->chipset) {
 297         case 0x40: /* vanilla NV40 */
 298                 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
 299                         tmp = nv_rd32(dev, NV10_PFB_TILE(i));
 300                         nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
 301                         nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
 302                         tmp = nv_rd32(dev, NV10_PFB_TLIMIT(i));
 303                         nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
 304                         nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
 305                         tmp = nv_rd32(dev, NV10_PFB_TSIZE(i));
 306                         nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
 307                         nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
 308                         tmp = nv_rd32(dev, NV10_PFB_TSTATUS(i));
 309                         nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
 310                         nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
 311                 }
 312                 break;
 313         case 0x44:
 314         case 0x4a:
 315         case 0x4e: /* NV44-based cores don't have 0x406900? */
 316                 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
 317                         tmp = nv_rd32(dev, NV40_PFB_TILE(i));
 318                         nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
 319                         tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
 320                         nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
 321                         tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
 322                         nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
 323                         tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
 324                         nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
 325                 }
 326                 break;
 327         case 0x46:
 328         case 0x47:
 329         case 0x49:
 330         case 0x4b: /* G7X-based cores */
 331                 for (i = 0; i < NV40_PFB_TILE__SIZE_1; i++) {
 332                         tmp = nv_rd32(dev, NV40_PFB_TILE(i));
 333                         nv_wr32(dev, NV47_PGRAPH_TILE0(i), tmp);
 334                         nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
 335                         tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
 336                         nv_wr32(dev, NV47_PGRAPH_TLIMIT0(i), tmp);
 337                         nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
 338                         tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
 339                         nv_wr32(dev, NV47_PGRAPH_TSIZE0(i), tmp);
 340                         nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
 341                         tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
 342                         nv_wr32(dev, NV47_PGRAPH_TSTATUS0(i), tmp);
 343                         nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
 344                 }
 345                 break;
 346         default: /* everything else */
 347                 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
 348                         tmp = nv_rd32(dev, NV40_PFB_TILE(i));
 349                         nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
 350                         nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
 351                         tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
 352                         nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
 353                         nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
 354                         tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
 355                         nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
 356                         nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
 357                         tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
 358                         nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
 359                         nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
 360                 }
 361                 break;
 362         }
 363
 364         /* begin RAM config */
 365         vramsz = drm_get_resource_len(dev, 0) - 1;
 366         switch (dev_priv->chipset) {
 367         case 0x40:
 368                 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
 369                 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
 370                 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
 371                 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
 372                 nv_wr32(dev, 0x400820, 0);
 373                 nv_wr32(dev, 0x400824, 0);
 374                 nv_wr32(dev, 0x400864, vramsz);
 375                 nv_wr32(dev, 0x400868, vramsz);
 376                 break;
 377         default:
 378                 switch (dev_priv->chipset) {
 379                 case 0x46:
 380                 case 0x47:
 381                 case 0x49:
 382                 case 0x4b:
 383                         nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
 384                         nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
 385                         break;
 386                 default:
 387                         nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
 388                         nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
 389                         break;
 390                 }
 391                 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
 392                 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
 393                 nv_wr32(dev, 0x400840, 0);
 394                 nv_wr32(dev, 0x400844, 0);
 395                 nv_wr32(dev, 0x4008A0, vramsz);
 396                 nv_wr32(dev, 0x4008A4, vramsz);
 397                 break;
 398         }
 399
 400         return 0;
 401 }
 402
 403 void nv40_graph_takedown(struct drm_device *dev)
 404 {
 405         nouveau_grctx_fini(dev);
 406 }
 407
 408 struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
 409         { 0x0030, false, NULL }, /* null */
 410         { 0x0039, false, NULL }, /* m2mf */
 411         { 0x004a, false, NULL }, /* gdirect */
 412         { 0x009f, false, NULL }, /* imageblit (nv12) */
 413         { 0x008a, false, NULL }, /* ifc */
 414         { 0x0089, false, NULL }, /* sifm */
 415         { 0x3089, false, NULL }, /* sifm (nv40) */
 416         { 0x0062, false, NULL }, /* surf2d */
 417         { 0x3062, false, NULL }, /* surf2d (nv40) */
 418         { 0x0043, false, NULL }, /* rop */
 419         { 0x0012, false, NULL }, /* beta1 */
 420         { 0x0072, false, NULL }, /* beta4 */
 421         { 0x0019, false, NULL }, /* cliprect */
 422         { 0x0044, false, NULL }, /* pattern */
 423         { 0x309e, false, NULL }, /* swzsurf */
 424         { 0x4097, false, NULL }, /* curie (nv40) */
 425         { 0x4497, false, NULL }, /* curie (nv44) */
 426         {}
 427 };
 428