2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_ramht.h"
32 #define NV04_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV04_RAMFC__SIZE))
33 #define NV04_RAMFC__SIZE 32
34 #define NV04_RAMFC_DMA_PUT 0x00
35 #define NV04_RAMFC_DMA_GET 0x04
36 #define NV04_RAMFC_DMA_INSTANCE 0x08
37 #define NV04_RAMFC_DMA_STATE 0x0C
38 #define NV04_RAMFC_DMA_FETCH 0x10
39 #define NV04_RAMFC_ENGINE 0x14
40 #define NV04_RAMFC_PULL1_ENGINE 0x18
42 #define RAMFC_WR(offset, val) nv_wo32(chan->ramfc, NV04_RAMFC_##offset, (val))
43 #define RAMFC_RD(offset) nv_ro32(chan->ramfc, NV04_RAMFC_##offset)
46 nv04_fifo_disable(struct drm_device *dev)
50 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH);
51 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, tmp & ~1);
52 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
53 tmp = nv_rd32(dev, NV03_PFIFO_CACHE1_PULL1);
54 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, tmp & ~1);
58 nv04_fifo_enable(struct drm_device *dev)
60 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
61 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
65 nv04_fifo_reassign(struct drm_device *dev, bool enable)
67 uint32_t reassign = nv_rd32(dev, NV03_PFIFO_CACHES);
69 nv_wr32(dev, NV03_PFIFO_CACHES, enable ? 1 : 0);
70 return (reassign == 1);
74 nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
76 int pull = nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 1, enable);
79 /* In some cases the PFIFO puller may be left in an
80 * inconsistent state if you try to stop it when it's
81 * busy translating handles. Sometimes you get a
82 * PFIFO_CACHE_ERROR, sometimes it just fails silently
83 * sending incorrect instance offsets to PGRAPH after
84 * it's started up again. To avoid the latter we
85 * invalidate the most recently calculated instance.
87 if (!nv_wait(dev, NV04_PFIFO_CACHE1_PULL0,
88 NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0))
89 NV_ERROR(dev, "Timeout idling the PFIFO puller.\n");
91 if (nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0) &
92 NV04_PFIFO_CACHE1_PULL0_HASH_FAILED)
93 nv_wr32(dev, NV03_PFIFO_INTR_0,
94 NV_PFIFO_INTR_CACHE_ERROR);
96 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
103 nv04_fifo_channel_id(struct drm_device *dev)
105 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
106 NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
110 #define DMA_FETCH_ENDIANNESS NV_PFIFO_CACHE1_BIG_ENDIAN
112 #define DMA_FETCH_ENDIANNESS 0
116 nv04_fifo_create_context(struct nouveau_channel *chan)
118 struct drm_device *dev = chan->dev;
119 struct drm_nouveau_private *dev_priv = dev->dev_private;
123 ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
125 NVOBJ_FLAG_ZERO_ALLOC |
126 NVOBJ_FLAG_ZERO_FREE,
131 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
133 /* Setup initial state */
134 RAMFC_WR(DMA_PUT, chan->pushbuf_base);
135 RAMFC_WR(DMA_GET, chan->pushbuf_base);
136 RAMFC_WR(DMA_INSTANCE, chan->pushbuf->pinst >> 4);
137 RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
138 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
139 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
140 DMA_FETCH_ENDIANNESS));
142 /* enable the fifo dma operation */
143 nv_wr32(dev, NV04_PFIFO_MODE,
144 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
146 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
151 nv04_fifo_destroy_context(struct nouveau_channel *chan)
153 struct drm_device *dev = chan->dev;
155 nv_wr32(dev, NV04_PFIFO_MODE,
156 nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
158 nouveau_gpuobj_ref(NULL, &chan->ramfc);
162 nv04_fifo_do_load_context(struct drm_device *dev, int chid)
164 struct drm_nouveau_private *dev_priv = dev->dev_private;
165 uint32_t fc = NV04_RAMFC(chid), tmp;
167 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
168 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
169 tmp = nv_ri32(dev, fc + 8);
170 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
171 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
172 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 12));
173 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 16));
174 nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 20));
175 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 24));
177 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
178 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
182 nv04_fifo_load_context(struct nouveau_channel *chan)
186 nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1,
187 NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
188 nv04_fifo_do_load_context(chan->dev, chan->id);
189 nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
191 /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
192 tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
193 nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
199 nv04_fifo_unload_context(struct drm_device *dev)
201 struct drm_nouveau_private *dev_priv = dev->dev_private;
202 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
203 struct nouveau_channel *chan = NULL;
207 chid = pfifo->channel_id(dev);
208 if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
211 chan = dev_priv->fifos[chid];
213 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
217 RAMFC_WR(DMA_PUT, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
218 RAMFC_WR(DMA_GET, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
219 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
220 tmp |= nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE);
221 RAMFC_WR(DMA_INSTANCE, tmp);
222 RAMFC_WR(DMA_STATE, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
223 RAMFC_WR(DMA_FETCH, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
224 RAMFC_WR(ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
225 RAMFC_WR(PULL1_ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
227 nv04_fifo_do_load_context(dev, pfifo->channels - 1);
228 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
233 nv04_fifo_init_reset(struct drm_device *dev)
235 nv_wr32(dev, NV03_PMC_ENABLE,
236 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
237 nv_wr32(dev, NV03_PMC_ENABLE,
238 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO);
240 nv_wr32(dev, 0x003224, 0x000f0078);
241 nv_wr32(dev, 0x002044, 0x0101ffff);
242 nv_wr32(dev, 0x002040, 0x000000ff);
243 nv_wr32(dev, 0x002500, 0x00000000);
244 nv_wr32(dev, 0x003000, 0x00000000);
245 nv_wr32(dev, 0x003050, 0x00000000);
246 nv_wr32(dev, 0x003200, 0x00000000);
247 nv_wr32(dev, 0x003250, 0x00000000);
248 nv_wr32(dev, 0x003220, 0x00000000);
250 nv_wr32(dev, 0x003250, 0x00000000);
251 nv_wr32(dev, 0x003270, 0x00000000);
252 nv_wr32(dev, 0x003210, 0x00000000);
256 nv04_fifo_init_ramxx(struct drm_device *dev)
258 struct drm_nouveau_private *dev_priv = dev->dev_private;
260 nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
261 ((dev_priv->ramht->bits - 9) << 16) |
262 (dev_priv->ramht->gpuobj->pinst >> 8));
263 nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
264 nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
268 nv04_fifo_init_intr(struct drm_device *dev)
270 nv_wr32(dev, 0x002100, 0xffffffff);
271 nv_wr32(dev, 0x002140, 0xffffffff);
275 nv04_fifo_init(struct drm_device *dev)
277 struct drm_nouveau_private *dev_priv = dev->dev_private;
278 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
281 nv04_fifo_init_reset(dev);
282 nv04_fifo_init_ramxx(dev);
284 nv04_fifo_do_load_context(dev, pfifo->channels - 1);
285 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
287 nv04_fifo_init_intr(dev);
289 pfifo->reassign(dev, true);
291 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
292 if (dev_priv->fifos[i]) {
293 uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
294 nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));