drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49         u32 pclass = dev->pdev->class >> 8;
  50
  51         switch (dev_priv->chipset & 0xf0) {
  52         case 0x00:
  53                 engine->instmem.init            = nv04_instmem_init;
  54                 engine->instmem.takedown        = nv04_instmem_takedown;
  55                 engine->instmem.suspend         = nv04_instmem_suspend;
  56                 engine->instmem.resume          = nv04_instmem_resume;
  57                 engine->instmem.get             = nv04_instmem_get;
  58                 engine->instmem.put             = nv04_instmem_put;
  59                 engine->instmem.map             = nv04_instmem_map;
  60                 engine->instmem.unmap           = nv04_instmem_unmap;
  61                 engine->instmem.flush           = nv04_instmem_flush;
  62                 engine->mc.init                 = nv04_mc_init;
  63                 engine->mc.takedown             = nv04_mc_takedown;
  64                 engine->timer.init              = nv04_timer_init;
  65                 engine->timer.read              = nv04_timer_read;
  66                 engine->timer.takedown          = nv04_timer_takedown;
  67                 engine->fb.init                 = nv04_fb_init;
  68                 engine->fb.takedown             = nv04_fb_takedown;
  69                 engine->fifo.channels           = 16;
  70                 engine->fifo.init               = nv04_fifo_init;
  71                 engine->fifo.takedown           = nv04_fifo_fini;
  72                 engine->fifo.disable            = nv04_fifo_disable;
  73                 engine->fifo.enable             = nv04_fifo_enable;
  74                 engine->fifo.reassign           = nv04_fifo_reassign;
  75                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  76                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  77                 engine->fifo.create_context     = nv04_fifo_create_context;
  78                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  79                 engine->fifo.load_context       = nv04_fifo_load_context;
  80                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  81                 engine->display.early_init      = nv04_display_early_init;
  82                 engine->display.late_takedown   = nv04_display_late_takedown;
  83                 engine->display.create          = nv04_display_create;
  84                 engine->display.init            = nv04_display_init;
  85                 engine->display.destroy         = nv04_display_destroy;
  86                 engine->gpio.init               = nouveau_stub_init;
  87                 engine->gpio.takedown           = nouveau_stub_takedown;
  88                 engine->gpio.get                = NULL;
  89                 engine->gpio.set                = NULL;
  90                 engine->gpio.irq_enable         = NULL;
  91                 engine->pm.clock_get            = nv04_pm_clock_get;
  92                 engine->pm.clock_pre            = nv04_pm_clock_pre;
  93                 engine->pm.clock_set            = nv04_pm_clock_set;
  94                 engine->vram.init               = nouveau_mem_detect;
  95                 engine->vram.takedown           = nouveau_stub_takedown;
  96                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  97                 break;
  98         case 0x10:
  99                 engine->instmem.init            = nv04_instmem_init;
 100                 engine->instmem.takedown        = nv04_instmem_takedown;
 101                 engine->instmem.suspend         = nv04_instmem_suspend;
 102                 engine->instmem.resume          = nv04_instmem_resume;
 103                 engine->instmem.get             = nv04_instmem_get;
 104                 engine->instmem.put             = nv04_instmem_put;
 105                 engine->instmem.map             = nv04_instmem_map;
 106                 engine->instmem.unmap           = nv04_instmem_unmap;
 107                 engine->instmem.flush           = nv04_instmem_flush;
 108                 engine->mc.init                 = nv04_mc_init;
 109                 engine->mc.takedown             = nv04_mc_takedown;
 110                 engine->timer.init              = nv04_timer_init;
 111                 engine->timer.read              = nv04_timer_read;
 112                 engine->timer.takedown          = nv04_timer_takedown;
 113                 engine->fb.init                 = nv10_fb_init;
 114                 engine->fb.takedown             = nv10_fb_takedown;
 115                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 116                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 117                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 118                 engine->fifo.channels           = 32;
 119                 engine->fifo.init               = nv10_fifo_init;
 120                 engine->fifo.takedown           = nv04_fifo_fini;
 121                 engine->fifo.disable            = nv04_fifo_disable;
 122                 engine->fifo.enable             = nv04_fifo_enable;
 123                 engine->fifo.reassign           = nv04_fifo_reassign;
 124                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 125                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 126                 engine->fifo.create_context     = nv10_fifo_create_context;
 127                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 128                 engine->fifo.load_context       = nv10_fifo_load_context;
 129                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 130                 engine->display.early_init      = nv04_display_early_init;
 131                 engine->display.late_takedown   = nv04_display_late_takedown;
 132                 engine->display.create          = nv04_display_create;
 133                 engine->display.init            = nv04_display_init;
 134                 engine->display.destroy         = nv04_display_destroy;
 135                 engine->gpio.init               = nouveau_stub_init;
 136                 engine->gpio.takedown           = nouveau_stub_takedown;
 137                 engine->gpio.get                = nv10_gpio_get;
 138                 engine->gpio.set                = nv10_gpio_set;
 139                 engine->gpio.irq_enable         = NULL;
 140                 engine->pm.clock_get            = nv04_pm_clock_get;
 141                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 142                 engine->pm.clock_set            = nv04_pm_clock_set;
 143                 engine->vram.init               = nouveau_mem_detect;
 144                 engine->vram.takedown           = nouveau_stub_takedown;
 145                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 146                 break;
 147         case 0x20:
 148                 engine->instmem.init            = nv04_instmem_init;
 149                 engine->instmem.takedown        = nv04_instmem_takedown;
 150                 engine->instmem.suspend         = nv04_instmem_suspend;
 151                 engine->instmem.resume          = nv04_instmem_resume;
 152                 engine->instmem.get             = nv04_instmem_get;
 153                 engine->instmem.put             = nv04_instmem_put;
 154                 engine->instmem.map             = nv04_instmem_map;
 155                 engine->instmem.unmap           = nv04_instmem_unmap;
 156                 engine->instmem.flush           = nv04_instmem_flush;
 157                 engine->mc.init                 = nv04_mc_init;
 158                 engine->mc.takedown             = nv04_mc_takedown;
 159                 engine->timer.init              = nv04_timer_init;
 160                 engine->timer.read              = nv04_timer_read;
 161                 engine->timer.takedown          = nv04_timer_takedown;
 162                 engine->fb.init                 = nv10_fb_init;
 163                 engine->fb.takedown             = nv10_fb_takedown;
 164                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 165                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 166                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 167                 engine->fifo.channels           = 32;
 168                 engine->fifo.init               = nv10_fifo_init;
 169                 engine->fifo.takedown           = nv04_fifo_fini;
 170                 engine->fifo.disable            = nv04_fifo_disable;
 171                 engine->fifo.enable             = nv04_fifo_enable;
 172                 engine->fifo.reassign           = nv04_fifo_reassign;
 173                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 174                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 175                 engine->fifo.create_context     = nv10_fifo_create_context;
 176                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 177                 engine->fifo.load_context       = nv10_fifo_load_context;
 178                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 179                 engine->display.early_init      = nv04_display_early_init;
 180                 engine->display.late_takedown   = nv04_display_late_takedown;
 181                 engine->display.create          = nv04_display_create;
 182                 engine->display.init            = nv04_display_init;
 183                 engine->display.destroy         = nv04_display_destroy;
 184                 engine->gpio.init               = nouveau_stub_init;
 185                 engine->gpio.takedown           = nouveau_stub_takedown;
 186                 engine->gpio.get                = nv10_gpio_get;
 187                 engine->gpio.set                = nv10_gpio_set;
 188                 engine->gpio.irq_enable         = NULL;
 189                 engine->pm.clock_get            = nv04_pm_clock_get;
 190                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 191                 engine->pm.clock_set            = nv04_pm_clock_set;
 192                 engine->vram.init               = nouveau_mem_detect;
 193                 engine->vram.takedown           = nouveau_stub_takedown;
 194                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 195                 break;
 196         case 0x30:
 197                 engine->instmem.init            = nv04_instmem_init;
 198                 engine->instmem.takedown        = nv04_instmem_takedown;
 199                 engine->instmem.suspend         = nv04_instmem_suspend;
 200                 engine->instmem.resume          = nv04_instmem_resume;
 201                 engine->instmem.get             = nv04_instmem_get;
 202                 engine->instmem.put             = nv04_instmem_put;
 203                 engine->instmem.map             = nv04_instmem_map;
 204                 engine->instmem.unmap           = nv04_instmem_unmap;
 205                 engine->instmem.flush           = nv04_instmem_flush;
 206                 engine->mc.init                 = nv04_mc_init;
 207                 engine->mc.takedown             = nv04_mc_takedown;
 208                 engine->timer.init              = nv04_timer_init;
 209                 engine->timer.read              = nv04_timer_read;
 210                 engine->timer.takedown          = nv04_timer_takedown;
 211                 engine->fb.init                 = nv30_fb_init;
 212                 engine->fb.takedown             = nv30_fb_takedown;
 213                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 214                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 215                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 216                 engine->fifo.channels           = 32;
 217                 engine->fifo.init               = nv10_fifo_init;
 218                 engine->fifo.takedown           = nv04_fifo_fini;
 219                 engine->fifo.disable            = nv04_fifo_disable;
 220                 engine->fifo.enable             = nv04_fifo_enable;
 221                 engine->fifo.reassign           = nv04_fifo_reassign;
 222                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 223                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 224                 engine->fifo.create_context     = nv10_fifo_create_context;
 225                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 226                 engine->fifo.load_context       = nv10_fifo_load_context;
 227                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 228                 engine->display.early_init      = nv04_display_early_init;
 229                 engine->display.late_takedown   = nv04_display_late_takedown;
 230                 engine->display.create          = nv04_display_create;
 231                 engine->display.init            = nv04_display_init;
 232                 engine->display.destroy         = nv04_display_destroy;
 233                 engine->gpio.init               = nouveau_stub_init;
 234                 engine->gpio.takedown           = nouveau_stub_takedown;
 235                 engine->gpio.get                = nv10_gpio_get;
 236                 engine->gpio.set                = nv10_gpio_set;
 237                 engine->gpio.irq_enable         = NULL;
 238                 engine->pm.clock_get            = nv04_pm_clock_get;
 239                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 240                 engine->pm.clock_set            = nv04_pm_clock_set;
 241                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 242                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 243                 engine->vram.init               = nouveau_mem_detect;
 244                 engine->vram.takedown           = nouveau_stub_takedown;
 245                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 246                 break;
 247         case 0x40:
 248         case 0x60:
 249                 engine->instmem.init            = nv04_instmem_init;
 250                 engine->instmem.takedown        = nv04_instmem_takedown;
 251                 engine->instmem.suspend         = nv04_instmem_suspend;
 252                 engine->instmem.resume          = nv04_instmem_resume;
 253                 engine->instmem.get             = nv04_instmem_get;
 254                 engine->instmem.put             = nv04_instmem_put;
 255                 engine->instmem.map             = nv04_instmem_map;
 256                 engine->instmem.unmap           = nv04_instmem_unmap;
 257                 engine->instmem.flush           = nv04_instmem_flush;
 258                 engine->mc.init                 = nv40_mc_init;
 259                 engine->mc.takedown             = nv40_mc_takedown;
 260                 engine->timer.init              = nv04_timer_init;
 261                 engine->timer.read              = nv04_timer_read;
 262                 engine->timer.takedown          = nv04_timer_takedown;
 263                 engine->fb.init                 = nv40_fb_init;
 264                 engine->fb.takedown             = nv40_fb_takedown;
 265                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 266                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 267                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 268                 engine->fifo.channels           = 32;
 269                 engine->fifo.init               = nv40_fifo_init;
 270                 engine->fifo.takedown           = nv04_fifo_fini;
 271                 engine->fifo.disable            = nv04_fifo_disable;
 272                 engine->fifo.enable             = nv04_fifo_enable;
 273                 engine->fifo.reassign           = nv04_fifo_reassign;
 274                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 275                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 276                 engine->fifo.create_context     = nv40_fifo_create_context;
 277                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 278                 engine->fifo.load_context       = nv40_fifo_load_context;
 279                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 280                 engine->display.early_init      = nv04_display_early_init;
 281                 engine->display.late_takedown   = nv04_display_late_takedown;
 282                 engine->display.create          = nv04_display_create;
 283                 engine->display.init            = nv04_display_init;
 284                 engine->display.destroy         = nv04_display_destroy;
 285                 engine->gpio.init               = nouveau_stub_init;
 286                 engine->gpio.takedown           = nouveau_stub_takedown;
 287                 engine->gpio.get                = nv10_gpio_get;
 288                 engine->gpio.set                = nv10_gpio_set;
 289                 engine->gpio.irq_enable         = NULL;
 290                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 291                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 292                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 293                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 294                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 295                 engine->pm.temp_get             = nv40_temp_get;
 296                 engine->vram.init               = nouveau_mem_detect;
 297                 engine->vram.takedown           = nouveau_stub_takedown;
 298                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 299                 break;
 300         case 0x50:
 301         case 0x80: /* gotta love NVIDIA's consistency.. */
 302         case 0x90:
 303         case 0xa0:
 304                 engine->instmem.init            = nv50_instmem_init;
 305                 engine->instmem.takedown        = nv50_instmem_takedown;
 306                 engine->instmem.suspend         = nv50_instmem_suspend;
 307                 engine->instmem.resume          = nv50_instmem_resume;
 308                 engine->instmem.get             = nv50_instmem_get;
 309                 engine->instmem.put             = nv50_instmem_put;
 310                 engine->instmem.map             = nv50_instmem_map;
 311                 engine->instmem.unmap           = nv50_instmem_unmap;
 312                 if (dev_priv->chipset == 0x50)
 313                         engine->instmem.flush   = nv50_instmem_flush;
 314                 else
 315                         engine->instmem.flush   = nv84_instmem_flush;
 316                 engine->mc.init                 = nv50_mc_init;
 317                 engine->mc.takedown             = nv50_mc_takedown;
 318                 engine->timer.init              = nv04_timer_init;
 319                 engine->timer.read              = nv04_timer_read;
 320                 engine->timer.takedown          = nv04_timer_takedown;
 321                 engine->fb.init                 = nv50_fb_init;
 322                 engine->fb.takedown             = nv50_fb_takedown;
 323                 engine->fifo.channels           = 128;
 324                 engine->fifo.init               = nv50_fifo_init;
 325                 engine->fifo.takedown           = nv50_fifo_takedown;
 326                 engine->fifo.disable            = nv04_fifo_disable;
 327                 engine->fifo.enable             = nv04_fifo_enable;
 328                 engine->fifo.reassign           = nv04_fifo_reassign;
 329                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 330                 engine->fifo.create_context     = nv50_fifo_create_context;
 331                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 332                 engine->fifo.load_context       = nv50_fifo_load_context;
 333                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 334                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 335                 engine->display.early_init      = nv50_display_early_init;
 336                 engine->display.late_takedown   = nv50_display_late_takedown;
 337                 engine->display.create          = nv50_display_create;
 338                 engine->display.init            = nv50_display_init;
 339                 engine->display.destroy         = nv50_display_destroy;
 340                 engine->gpio.init               = nv50_gpio_init;
 341                 engine->gpio.takedown           = nv50_gpio_fini;
 342                 engine->gpio.get                = nv50_gpio_get;
 343                 engine->gpio.set                = nv50_gpio_set;
 344                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 345                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 346                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 347                 switch (dev_priv->chipset) {
 348                 case 0x84:
 349                 case 0x86:
 350                 case 0x92:
 351                 case 0x94:
 352                 case 0x96:
 353                 case 0x98:
 354                 case 0xa0:
 355                 case 0xaa:
 356                 case 0xac:
 357                 case 0x50:
 358                         engine->pm.clock_get    = nv50_pm_clock_get;
 359                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 360                         engine->pm.clock_set    = nv50_pm_clock_set;
 361                         break;
 362                 default:
 363                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 364                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 365                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 366                         break;
 367                 }
 368                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 369                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 370                 if (dev_priv->chipset >= 0x84)
 371                         engine->pm.temp_get     = nv84_temp_get;
 372                 else
 373                         engine->pm.temp_get     = nv40_temp_get;
 374                 engine->vram.init               = nv50_vram_init;
 375                 engine->vram.takedown           = nv50_vram_fini;
 376                 engine->vram.get                = nv50_vram_new;
 377                 engine->vram.put                = nv50_vram_del;
 378                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 379                 break;
 380         case 0xc0:
 381                 engine->instmem.init            = nvc0_instmem_init;
 382                 engine->instmem.takedown        = nvc0_instmem_takedown;
 383                 engine->instmem.suspend         = nvc0_instmem_suspend;
 384                 engine->instmem.resume          = nvc0_instmem_resume;
 385                 engine->instmem.get             = nv50_instmem_get;
 386                 engine->instmem.put             = nv50_instmem_put;
 387                 engine->instmem.map             = nv50_instmem_map;
 388                 engine->instmem.unmap           = nv50_instmem_unmap;
 389                 engine->instmem.flush           = nv84_instmem_flush;
 390                 engine->mc.init                 = nv50_mc_init;
 391                 engine->mc.takedown             = nv50_mc_takedown;
 392                 engine->timer.init              = nv04_timer_init;
 393                 engine->timer.read              = nv04_timer_read;
 394                 engine->timer.takedown          = nv04_timer_takedown;
 395                 engine->fb.init                 = nvc0_fb_init;
 396                 engine->fb.takedown             = nvc0_fb_takedown;
 397                 engine->fifo.channels           = 128;
 398                 engine->fifo.init               = nvc0_fifo_init;
 399                 engine->fifo.takedown           = nvc0_fifo_takedown;
 400                 engine->fifo.disable            = nvc0_fifo_disable;
 401                 engine->fifo.enable             = nvc0_fifo_enable;
 402                 engine->fifo.reassign           = nvc0_fifo_reassign;
 403                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 404                 engine->fifo.create_context     = nvc0_fifo_create_context;
 405                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 406                 engine->fifo.load_context       = nvc0_fifo_load_context;
 407                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 408                 engine->display.early_init      = nv50_display_early_init;
 409                 engine->display.late_takedown   = nv50_display_late_takedown;
 410                 engine->display.create          = nv50_display_create;
 411                 engine->display.init            = nv50_display_init;
 412                 engine->display.destroy         = nv50_display_destroy;
 413                 engine->gpio.init               = nv50_gpio_init;
 414                 engine->gpio.takedown           = nouveau_stub_takedown;
 415                 engine->gpio.get                = nv50_gpio_get;
 416                 engine->gpio.set                = nv50_gpio_set;
 417                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 418                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 419                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 420                 engine->vram.init               = nvc0_vram_init;
 421                 engine->vram.takedown           = nv50_vram_fini;
 422                 engine->vram.get                = nvc0_vram_new;
 423                 engine->vram.put                = nv50_vram_del;
 424                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 425                 engine->pm.temp_get             = nv84_temp_get;
 426                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 427                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 428                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 429                 break;
 430         case 0xd0:
 431                 engine->instmem.init            = nvc0_instmem_init;
 432                 engine->instmem.takedown        = nvc0_instmem_takedown;
 433                 engine->instmem.suspend         = nvc0_instmem_suspend;
 434                 engine->instmem.resume          = nvc0_instmem_resume;
 435                 engine->instmem.get             = nv50_instmem_get;
 436                 engine->instmem.put             = nv50_instmem_put;
 437                 engine->instmem.map             = nv50_instmem_map;
 438                 engine->instmem.unmap           = nv50_instmem_unmap;
 439                 engine->instmem.flush           = nv84_instmem_flush;
 440                 engine->mc.init                 = nv50_mc_init;
 441                 engine->mc.takedown             = nv50_mc_takedown;
 442                 engine->timer.init              = nv04_timer_init;
 443                 engine->timer.read              = nv04_timer_read;
 444                 engine->timer.takedown          = nv04_timer_takedown;
 445                 engine->fb.init                 = nvc0_fb_init;
 446                 engine->fb.takedown             = nvc0_fb_takedown;
 447                 engine->fifo.channels           = 128;
 448                 engine->fifo.init               = nvc0_fifo_init;
 449                 engine->fifo.takedown           = nvc0_fifo_takedown;
 450                 engine->fifo.disable            = nvc0_fifo_disable;
 451                 engine->fifo.enable             = nvc0_fifo_enable;
 452                 engine->fifo.reassign           = nvc0_fifo_reassign;
 453                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 454                 engine->fifo.create_context     = nvc0_fifo_create_context;
 455                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 456                 engine->fifo.load_context       = nvc0_fifo_load_context;
 457                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 458                 engine->display.early_init      = nouveau_stub_init;
 459                 engine->display.late_takedown   = nouveau_stub_takedown;
 460                 engine->display.create          = nvd0_display_create;
 461                 engine->display.init            = nvd0_display_init;
 462                 engine->display.destroy         = nvd0_display_destroy;
 463                 engine->gpio.init               = nv50_gpio_init;
 464                 engine->gpio.takedown           = nouveau_stub_takedown;
 465                 engine->gpio.get                = nvd0_gpio_get;
 466                 engine->gpio.set                = nvd0_gpio_set;
 467                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 468                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 469                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 470                 engine->vram.init               = nvc0_vram_init;
 471                 engine->vram.takedown           = nv50_vram_fini;
 472                 engine->vram.get                = nvc0_vram_new;
 473                 engine->vram.put                = nv50_vram_del;
 474                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 475                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 476                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 477                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 478                 break;
 479         default:
 480                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 481                 return 1;
 482         }
 483
 484         /* headless mode */
 485         if (nouveau_modeset == 2 ||
 486             (nouveau_modeset < 0 && pclass != PCI_CLASS_DISPLAY_VGA)) {
 487                 engine->display.early_init = nouveau_stub_init;
 488                 engine->display.late_takedown = nouveau_stub_takedown;
 489                 engine->display.create = nouveau_stub_init;
 490                 engine->display.init = nouveau_stub_init;
 491                 engine->display.destroy = nouveau_stub_takedown;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static unsigned int
 498 nouveau_vga_set_decode(void *priv, bool state)
 499 {
 500         struct drm_device *dev = priv;
 501         struct drm_nouveau_private *dev_priv = dev->dev_private;
 502
 503         if (dev_priv->chipset >= 0x40)
 504                 nv_wr32(dev, 0x88054, state);
 505         else
 506                 nv_wr32(dev, 0x1854, state);
 507
 508         if (state)
 509                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 510                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 511         else
 512                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 513 }
 514
 515 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 516                                          enum vga_switcheroo_state state)
 517 {
 518         struct drm_device *dev = pci_get_drvdata(pdev);
 519         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 520         if (state == VGA_SWITCHEROO_ON) {
 521                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 522                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 523                 nouveau_pci_resume(pdev);
 524                 drm_kms_helper_poll_enable(dev);
 525                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 526         } else {
 527                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 528                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 529                 drm_kms_helper_poll_disable(dev);
 530                 nouveau_pci_suspend(pdev, pmm);
 531                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 532         }
 533 }
 534
 535 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 536 {
 537         struct drm_device *dev = pci_get_drvdata(pdev);
 538         nouveau_fbcon_output_poll_changed(dev);
 539 }
 540
 541 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 542 {
 543         struct drm_device *dev = pci_get_drvdata(pdev);
 544         bool can_switch;
 545
 546         spin_lock(&dev->count_lock);
 547         can_switch = (dev->open_count == 0);
 548         spin_unlock(&dev->count_lock);
 549         return can_switch;
 550 }
 551
 552 int
 553 nouveau_card_init(struct drm_device *dev)
 554 {
 555         struct drm_nouveau_private *dev_priv = dev->dev_private;
 556         struct nouveau_engine *engine;
 557         int ret, e = 0;
 558
 559         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 560         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 561                                        nouveau_switcheroo_reprobe,
 562                                        nouveau_switcheroo_can_switch);
 563
 564         /* Initialise internal driver API hooks */
 565         ret = nouveau_init_engine_ptrs(dev);
 566         if (ret)
 567                 goto out;
 568         engine = &dev_priv->engine;
 569         spin_lock_init(&dev_priv->channels.lock);
 570         spin_lock_init(&dev_priv->tile.lock);
 571         spin_lock_init(&dev_priv->context_switch_lock);
 572         spin_lock_init(&dev_priv->vm_lock);
 573
 574         /* Make the CRTCs and I2C buses accessible */
 575         ret = engine->display.early_init(dev);
 576         if (ret)
 577                 goto out;
 578
 579         /* Parse BIOS tables / Run init tables if card not POSTed */
 580         ret = nouveau_bios_init(dev);
 581         if (ret)
 582                 goto out_display_early;
 583
 584         /* workaround an odd issue on nvc1 by disabling the device's
 585          * nosnoop capability.  hopefully won't cause issues until a
 586          * better fix is found - assuming there is one...
 587          */
 588         if (dev_priv->chipset == 0xc1) {
 589                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 590         }
 591
 592         nouveau_pm_init(dev);
 593
 594         ret = engine->vram.init(dev);
 595         if (ret)
 596                 goto out_bios;
 597
 598         ret = nouveau_gpuobj_init(dev);
 599         if (ret)
 600                 goto out_vram;
 601
 602         ret = engine->instmem.init(dev);
 603         if (ret)
 604                 goto out_gpuobj;
 605
 606         ret = nouveau_mem_vram_init(dev);
 607         if (ret)
 608                 goto out_instmem;
 609
 610         ret = nouveau_mem_gart_init(dev);
 611         if (ret)
 612                 goto out_ttmvram;
 613
 614         /* PMC */
 615         ret = engine->mc.init(dev);
 616         if (ret)
 617                 goto out_gart;
 618
 619         /* PGPIO */
 620         ret = engine->gpio.init(dev);
 621         if (ret)
 622                 goto out_mc;
 623
 624         /* PTIMER */
 625         ret = engine->timer.init(dev);
 626         if (ret)
 627                 goto out_gpio;
 628
 629         /* PFB */
 630         ret = engine->fb.init(dev);
 631         if (ret)
 632                 goto out_timer;
 633
 634         if (!dev_priv->noaccel) {
 635                 switch (dev_priv->card_type) {
 636                 case NV_04:
 637                         nv04_graph_create(dev);
 638                         break;
 639                 case NV_10:
 640                         nv10_graph_create(dev);
 641                         break;
 642                 case NV_20:
 643                 case NV_30:
 644                         nv20_graph_create(dev);
 645                         break;
 646                 case NV_40:
 647                         nv40_graph_create(dev);
 648                         break;
 649                 case NV_50:
 650                         nv50_graph_create(dev);
 651                         break;
 652                 case NV_C0:
 653                         nvc0_graph_create(dev);
 654                         break;
 655                 default:
 656                         break;
 657                 }
 658
 659                 switch (dev_priv->chipset) {
 660                 case 0x84:
 661                 case 0x86:
 662                 case 0x92:
 663                 case 0x94:
 664                 case 0x96:
 665                 case 0xa0:
 666                         nv84_crypt_create(dev);
 667                         break;
 668                 }
 669
 670                 switch (dev_priv->card_type) {
 671                 case NV_50:
 672                         switch (dev_priv->chipset) {
 673                         case 0xa3:
 674                         case 0xa5:
 675                         case 0xa8:
 676                         case 0xaf:
 677                                 nva3_copy_create(dev);
 678                                 break;
 679                         }
 680                         break;
 681                 case NV_C0:
 682                         nvc0_copy_create(dev, 0);
 683                         nvc0_copy_create(dev, 1);
 684                         break;
 685                 default:
 686                         break;
 687                 }
 688
 689                 if (dev_priv->card_type == NV_40 ||
 690                     dev_priv->chipset == 0x31 ||
 691                     dev_priv->chipset == 0x34 ||
 692                     dev_priv->chipset == 0x36)
 693                         nv31_mpeg_create(dev);
 694                 else
 695                 if (dev_priv->card_type == NV_50 &&
 696                     (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
 697                         nv50_mpeg_create(dev);
 698
 699                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 700                         if (dev_priv->eng[e]) {
 701                                 ret = dev_priv->eng[e]->init(dev, e);
 702                                 if (ret)
 703                                         goto out_engine;
 704                         }
 705                 }
 706
 707                 /* PFIFO */
 708                 ret = engine->fifo.init(dev);
 709                 if (ret)
 710                         goto out_engine;
 711         }
 712
 713         ret = nouveau_irq_init(dev);
 714         if (ret)
 715                 goto out_fifo;
 716
 717         /* initialise general modesetting */
 718         drm_mode_config_init(dev);
 719         drm_mode_create_scaling_mode_property(dev);
 720         drm_mode_create_dithering_property(dev);
 721         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 722         dev->mode_config.fb_base = pci_resource_start(dev->pdev, 1);
 723         dev->mode_config.min_width = 0;
 724         dev->mode_config.min_height = 0;
 725         if (dev_priv->card_type < NV_10) {
 726                 dev->mode_config.max_width = 2048;
 727                 dev->mode_config.max_height = 2048;
 728         } else
 729         if (dev_priv->card_type < NV_50) {
 730                 dev->mode_config.max_width = 4096;
 731                 dev->mode_config.max_height = 4096;
 732         } else {
 733                 dev->mode_config.max_width = 8192;
 734                 dev->mode_config.max_height = 8192;
 735         }
 736
 737         ret = engine->display.create(dev);
 738         if (ret)
 739                 goto out_irq;
 740
 741         nouveau_backlight_init(dev);
 742
 743         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 744                 ret = nouveau_fence_init(dev);
 745                 if (ret)
 746                         goto out_disp;
 747
 748                 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
 749                                             NvDmaFB, NvDmaTT);
 750                 if (ret)
 751                         goto out_fence;
 752
 753                 mutex_unlock(&dev_priv->channel->mutex);
 754         }
 755
 756         if (dev->mode_config.num_crtc) {
 757                 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 758                 if (ret)
 759                         goto out_chan;
 760
 761                 nouveau_fbcon_init(dev);
 762                 drm_kms_helper_poll_init(dev);
 763         }
 764
 765         return 0;
 766
 767 out_chan:
 768         nouveau_channel_put_unlocked(&dev_priv->channel);
 769 out_fence:
 770         nouveau_fence_fini(dev);
 771 out_disp:
 772         nouveau_backlight_exit(dev);
 773         engine->display.destroy(dev);
 774 out_irq:
 775         nouveau_irq_fini(dev);
 776 out_fifo:
 777         if (!dev_priv->noaccel)
 778                 engine->fifo.takedown(dev);
 779 out_engine:
 780         if (!dev_priv->noaccel) {
 781                 for (e = e - 1; e >= 0; e--) {
 782                         if (!dev_priv->eng[e])
 783                                 continue;
 784                         dev_priv->eng[e]->fini(dev, e, false);
 785                         dev_priv->eng[e]->destroy(dev,e );
 786                 }
 787         }
 788
 789         engine->fb.takedown(dev);
 790 out_timer:
 791         engine->timer.takedown(dev);
 792 out_gpio:
 793         engine->gpio.takedown(dev);
 794 out_mc:
 795         engine->mc.takedown(dev);
 796 out_gart:
 797         nouveau_mem_gart_fini(dev);
 798 out_ttmvram:
 799         nouveau_mem_vram_fini(dev);
 800 out_instmem:
 801         engine->instmem.takedown(dev);
 802 out_gpuobj:
 803         nouveau_gpuobj_takedown(dev);
 804 out_vram:
 805         engine->vram.takedown(dev);
 806 out_bios:
 807         nouveau_pm_fini(dev);
 808         nouveau_bios_takedown(dev);
 809 out_display_early:
 810         engine->display.late_takedown(dev);
 811 out:
 812         vga_client_register(dev->pdev, NULL, NULL, NULL);
 813         return ret;
 814 }
 815
 816 static void nouveau_card_takedown(struct drm_device *dev)
 817 {
 818         struct drm_nouveau_private *dev_priv = dev->dev_private;
 819         struct nouveau_engine *engine = &dev_priv->engine;
 820         int e;
 821
 822         if (dev->mode_config.num_crtc) {
 823                 drm_kms_helper_poll_fini(dev);
 824                 nouveau_fbcon_fini(dev);
 825                 drm_vblank_cleanup(dev);
 826         }
 827
 828         if (dev_priv->channel) {
 829                 nouveau_channel_put_unlocked(&dev_priv->channel);
 830                 nouveau_fence_fini(dev);
 831         }
 832
 833         nouveau_backlight_exit(dev);
 834         engine->display.destroy(dev);
 835         drm_mode_config_cleanup(dev);
 836
 837         if (!dev_priv->noaccel) {
 838                 engine->fifo.takedown(dev);
 839                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 840                         if (dev_priv->eng[e]) {
 841                                 dev_priv->eng[e]->fini(dev, e, false);
 842                                 dev_priv->eng[e]->destroy(dev,e );
 843                         }
 844                 }
 845         }
 846         engine->fb.takedown(dev);
 847         engine->timer.takedown(dev);
 848         engine->gpio.takedown(dev);
 849         engine->mc.takedown(dev);
 850         engine->display.late_takedown(dev);
 851
 852         if (dev_priv->vga_ram) {
 853                 nouveau_bo_unpin(dev_priv->vga_ram);
 854                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 855         }
 856
 857         mutex_lock(&dev->struct_mutex);
 858         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 859         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 860         mutex_unlock(&dev->struct_mutex);
 861         nouveau_mem_gart_fini(dev);
 862         nouveau_mem_vram_fini(dev);
 863
 864         engine->instmem.takedown(dev);
 865         nouveau_gpuobj_takedown(dev);
 866         engine->vram.takedown(dev);
 867
 868         nouveau_irq_fini(dev);
 869
 870         nouveau_pm_fini(dev);
 871         nouveau_bios_takedown(dev);
 872
 873         vga_client_register(dev->pdev, NULL, NULL, NULL);
 874 }
 875
 876 int
 877 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 878 {
 879         struct drm_nouveau_private *dev_priv = dev->dev_private;
 880         struct nouveau_fpriv *fpriv;
 881         int ret;
 882
 883         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 884         if (unlikely(!fpriv))
 885                 return -ENOMEM;
 886
 887         spin_lock_init(&fpriv->lock);
 888         INIT_LIST_HEAD(&fpriv->channels);
 889
 890         if (dev_priv->card_type == NV_50) {
 891                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 892                                      &fpriv->vm);
 893                 if (ret) {
 894                         kfree(fpriv);
 895                         return ret;
 896                 }
 897         } else
 898         if (dev_priv->card_type >= NV_C0) {
 899                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 900                                      &fpriv->vm);
 901                 if (ret) {
 902                         kfree(fpriv);
 903                         return ret;
 904                 }
 905         }
 906
 907         file_priv->driver_priv = fpriv;
 908         return 0;
 909 }
 910
 911 /* here a client dies, release the stuff that was allocated for its
 912  * file_priv */
 913 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 914 {
 915         nouveau_channel_cleanup(dev, file_priv);
 916 }
 917
 918 void
 919 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
 920 {
 921         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 922         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
 923         kfree(fpriv);
 924 }
 925
 926 /* first module load, setup the mmio/fb mapping */
 927 /* KMS: we need mmio at load time, not when the first drm client opens. */
 928 int nouveau_firstopen(struct drm_device *dev)
 929 {
 930         return 0;
 931 }
 932
 933 /* if we have an OF card, copy vbios to RAMIN */
 934 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 935 {
 936 #if defined(__powerpc__)
 937         int size, i;
 938         const uint32_t *bios;
 939         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 940         if (!dn) {
 941                 NV_INFO(dev, "Unable to get the OF node\n");
 942                 return;
 943         }
 944
 945         bios = of_get_property(dn, "NVDA,BMP", &size);
 946         if (bios) {
 947                 for (i = 0; i < size; i += 4)
 948                         nv_wi32(dev, i, bios[i/4]);
 949                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 950         } else {
 951                 NV_INFO(dev, "Unable to get the OF bios\n");
 952         }
 953 #endif
 954 }
 955
 956 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 957 {
 958         struct pci_dev *pdev = dev->pdev;
 959         struct apertures_struct *aper = alloc_apertures(3);
 960         if (!aper)
 961                 return NULL;
 962
 963         aper->ranges[0].base = pci_resource_start(pdev, 1);
 964         aper->ranges[0].size = pci_resource_len(pdev, 1);
 965         aper->count = 1;
 966
 967         if (pci_resource_len(pdev, 2)) {
 968                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 969                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 970                 aper->count++;
 971         }
 972
 973         if (pci_resource_len(pdev, 3)) {
 974                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 975                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 976                 aper->count++;
 977         }
 978
 979         return aper;
 980 }
 981
 982 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 983 {
 984         struct drm_nouveau_private *dev_priv = dev->dev_private;
 985         bool primary = false;
 986         dev_priv->apertures = nouveau_get_apertures(dev);
 987         if (!dev_priv->apertures)
 988                 return -ENOMEM;
 989
 990 #ifdef CONFIG_X86
 991         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 992 #endif
 993
 994         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 995         return 0;
 996 }
 997
 998 int nouveau_load(struct drm_device *dev, unsigned long flags)
 999 {
1000         struct drm_nouveau_private *dev_priv;
1001         uint32_t reg0, strap;
1002         resource_size_t mmio_start_offs;
1003         int ret;
1004
1005         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1006         if (!dev_priv) {
1007                 ret = -ENOMEM;
1008                 goto err_out;
1009         }
1010         dev->dev_private = dev_priv;
1011         dev_priv->dev = dev;
1012
1013         dev_priv->flags = flags & NOUVEAU_FLAGS;
1014
1015         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1016                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1017
1018         /* resource 0 is mmio regs */
1019         /* resource 1 is linear FB */
1020         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
1021         /* resource 6 is bios */
1022
1023         /* map the mmio regs */
1024         mmio_start_offs = pci_resource_start(dev->pdev, 0);
1025         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
1026         if (!dev_priv->mmio) {
1027                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1028                          "Please report your setup to " DRIVER_EMAIL "\n");
1029                 ret = -EINVAL;
1030                 goto err_priv;
1031         }
1032         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
1033                                         (unsigned long long)mmio_start_offs);
1034
1035 #ifdef __BIG_ENDIAN
1036         /* Put the card in BE mode if it's not */
1037         if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1038                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1039
1040         DRM_MEMORYBARRIER();
1041 #endif
1042
1043         /* Time to determine the card architecture */
1044         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1045
1046         /* We're dealing with >=NV10 */
1047         if ((reg0 & 0x0f000000) > 0) {
1048                 /* Bit 27-20 contain the architecture in hex */
1049                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1050         /* NV04 or NV05 */
1051         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1052                 if (reg0 & 0x00f00000)
1053                         dev_priv->chipset = 0x05;
1054                 else
1055                         dev_priv->chipset = 0x04;
1056         } else
1057                 dev_priv->chipset = 0xff;
1058
1059         switch (dev_priv->chipset & 0xf0) {
1060         case 0x00:
1061         case 0x10:
1062         case 0x20:
1063         case 0x30:
1064                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1065                 break;
1066         case 0x40:
1067         case 0x60:
1068                 dev_priv->card_type = NV_40;
1069                 break;
1070         case 0x50:
1071         case 0x80:
1072         case 0x90:
1073         case 0xa0:
1074                 dev_priv->card_type = NV_50;
1075                 break;
1076         case 0xc0:
1077                 dev_priv->card_type = NV_C0;
1078                 break;
1079         case 0xd0:
1080                 dev_priv->card_type = NV_D0;
1081                 break;
1082         default:
1083                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
1084                 ret = -EINVAL;
1085                 goto err_mmio;
1086         }
1087
1088         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1089                 dev_priv->card_type, reg0);
1090
1091         /* determine frequency of timing crystal */
1092         strap = nv_rd32(dev, 0x101000);
1093         if ( dev_priv->chipset < 0x17 ||
1094             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1095                 strap &= 0x00000040;
1096         else
1097                 strap &= 0x00400040;
1098
1099         switch (strap) {
1100         case 0x00000000: dev_priv->crystal = 13500; break;
1101         case 0x00000040: dev_priv->crystal = 14318; break;
1102         case 0x00400000: dev_priv->crystal = 27000; break;
1103         case 0x00400040: dev_priv->crystal = 25000; break;
1104         }
1105
1106         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1107
1108         /* Determine whether we'll attempt acceleration or not, some
1109          * cards are disabled by default here due to them being known
1110          * non-functional, or never been tested due to lack of hw.
1111          */
1112         dev_priv->noaccel = !!nouveau_noaccel;
1113         if (nouveau_noaccel == -1) {
1114                 switch (dev_priv->chipset) {
1115 #if 0
1116                 case 0xXX: /* known broken */
1117                         NV_INFO(dev, "acceleration disabled by default, pass "
1118                                      "noaccel=0 to force enable\n");
1119                         dev_priv->noaccel = true;
1120                         break;
1121 #endif
1122                 default:
1123                         dev_priv->noaccel = false;
1124                         break;
1125                 }
1126         }
1127
1128         ret = nouveau_remove_conflicting_drivers(dev);
1129         if (ret)
1130                 goto err_mmio;
1131
1132         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1133         if (dev_priv->card_type >= NV_40) {
1134                 int ramin_bar = 2;
1135                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1136                         ramin_bar = 3;
1137
1138                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1139                 dev_priv->ramin =
1140                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1141                                 dev_priv->ramin_size);
1142                 if (!dev_priv->ramin) {
1143                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1144                         ret = -ENOMEM;
1145                         goto err_mmio;
1146                 }
1147         } else {
1148                 dev_priv->ramin_size = 1 * 1024 * 1024;
1149                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1150                                           dev_priv->ramin_size);
1151                 if (!dev_priv->ramin) {
1152                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1153                         ret = -ENOMEM;
1154                         goto err_mmio;
1155                 }
1156         }
1157
1158         nouveau_OF_copy_vbios_to_ramin(dev);
1159
1160         /* Special flags */
1161         if (dev->pci_device == 0x01a0)
1162                 dev_priv->flags |= NV_NFORCE;
1163         else if (dev->pci_device == 0x01f0)
1164                 dev_priv->flags |= NV_NFORCE2;
1165
1166         /* For kernel modesetting, init card now and bring up fbcon */
1167         ret = nouveau_card_init(dev);
1168         if (ret)
1169                 goto err_ramin;
1170
1171         return 0;
1172
1173 err_ramin:
1174         iounmap(dev_priv->ramin);
1175 err_mmio:
1176         iounmap(dev_priv->mmio);
1177 err_priv:
1178         kfree(dev_priv);
1179         dev->dev_private = NULL;
1180 err_out:
1181         return ret;
1182 }
1183
1184 void nouveau_lastclose(struct drm_device *dev)
1185 {
1186         vga_switcheroo_process_delayed_switch();
1187 }
1188
1189 int nouveau_unload(struct drm_device *dev)
1190 {
1191         struct drm_nouveau_private *dev_priv = dev->dev_private;
1192
1193         nouveau_card_takedown(dev);
1194
1195         iounmap(dev_priv->mmio);
1196         iounmap(dev_priv->ramin);
1197
1198         kfree(dev_priv);
1199         dev->dev_private = NULL;
1200         return 0;
1201 }
1202
1203 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1204                                                 struct drm_file *file_priv)
1205 {
1206         struct drm_nouveau_private *dev_priv = dev->dev_private;
1207         struct drm_nouveau_getparam *getparam = data;
1208
1209         switch (getparam->param) {
1210         case NOUVEAU_GETPARAM_CHIPSET_ID:
1211                 getparam->value = dev_priv->chipset;
1212                 break;
1213         case NOUVEAU_GETPARAM_PCI_VENDOR:
1214                 getparam->value = dev->pci_vendor;
1215                 break;
1216         case NOUVEAU_GETPARAM_PCI_DEVICE:
1217                 getparam->value = dev->pci_device;
1218                 break;
1219         case NOUVEAU_GETPARAM_BUS_TYPE:
1220                 if (drm_pci_device_is_agp(dev))
1221                         getparam->value = NV_AGP;
1222                 else if (pci_is_pcie(dev->pdev))
1223                         getparam->value = NV_PCIE;
1224                 else
1225                         getparam->value = NV_PCI;
1226                 break;
1227         case NOUVEAU_GETPARAM_FB_SIZE:
1228                 getparam->value = dev_priv->fb_available_size;
1229                 break;
1230         case NOUVEAU_GETPARAM_AGP_SIZE:
1231                 getparam->value = dev_priv->gart_info.aper_size;
1232                 break;
1233         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1234                 getparam->value = 0; /* deprecated */
1235                 break;
1236         case NOUVEAU_GETPARAM_PTIMER_TIME:
1237                 getparam->value = dev_priv->engine.timer.read(dev);
1238                 break;
1239         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1240                 getparam->value = 1;
1241                 break;
1242         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1243                 getparam->value = dev_priv->card_type < NV_D0;
1244                 break;
1245         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1246                 /* NV40 and NV50 versions are quite different, but register
1247                  * address is the same. User is supposed to know the card
1248                  * family anyway... */
1249                 if (dev_priv->chipset >= 0x40) {
1250                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1251                         break;
1252                 }
1253                 /* FALLTHRU */
1254         default:
1255                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1256                 return -EINVAL;
1257         }
1258
1259         return 0;
1260 }
1261
1262 int
1263 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1264                        struct drm_file *file_priv)
1265 {
1266         struct drm_nouveau_setparam *setparam = data;
1267
1268         switch (setparam->param) {
1269         default:
1270                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1271                 return -EINVAL;
1272         }
1273
1274         return 0;
1275 }
1276
1277 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1278 bool
1279 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1280                 uint32_t reg, uint32_t mask, uint32_t val)
1281 {
1282         struct drm_nouveau_private *dev_priv = dev->dev_private;
1283         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1284         uint64_t start = ptimer->read(dev);
1285
1286         do {
1287                 if ((nv_rd32(dev, reg) & mask) == val)
1288                         return true;
1289         } while (ptimer->read(dev) - start < timeout);
1290
1291         return false;
1292 }
1293
1294 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1295 bool
1296 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1297                 uint32_t reg, uint32_t mask, uint32_t val)
1298 {
1299         struct drm_nouveau_private *dev_priv = dev->dev_private;
1300         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1301         uint64_t start = ptimer->read(dev);
1302
1303         do {
1304                 if ((nv_rd32(dev, reg) & mask) != val)
1305                         return true;
1306         } while (ptimer->read(dev) - start < timeout);
1307
1308         return false;
1309 }
1310
1311 /* Wait until cond(data) == true, up until timeout has hit */
1312 bool
1313 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1314                 bool (*cond)(void *), void *data)
1315 {
1316         struct drm_nouveau_private *dev_priv = dev->dev_private;
1317         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1318         u64 start = ptimer->read(dev);
1319
1320         do {
1321                 if (cond(data) == true)
1322                         return true;
1323         } while (ptimer->read(dev) - start < timeout);
1324
1325         return false;
1326 }
1327
1328 /* Waits for PGRAPH to go completely idle */
1329 bool nouveau_wait_for_idle(struct drm_device *dev)
1330 {
1331         struct drm_nouveau_private *dev_priv = dev->dev_private;
1332         uint32_t mask = ~0;
1333
1334         if (dev_priv->card_type == NV_40)
1335                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1336
1337         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1338                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1339                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1340                 return false;
1341         }
1342
1343         return true;
1344 }
1345