drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36
  37 #include "nouveau_drv.h"
  38 #include "nouveau_pm.h"
  39 #include "nouveau_mm.h"
  40 #include "nouveau_vm.h"
  41
  42 /*
  43  * NV10-NV40 tiling helpers
  44  */
  45
  46 static void
  47 nv10_mem_update_tile_region(struct drm_device *dev,
  48                             struct nouveau_tile_reg *tile, uint32_t addr,
  49                             uint32_t size, uint32_t pitch, uint32_t flags)
  50 {
  51         struct drm_nouveau_private *dev_priv = dev->dev_private;
  52         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  53         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  54         int i = tile - dev_priv->tile.reg, j;
  55         unsigned long save;
  56
  57         nouveau_fence_unref(&tile->fence);
  58
  59         if (tile->pitch)
  60                 pfb->free_tile_region(dev, i);
  61
  62         if (pitch)
  63                 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
  64
  65         spin_lock_irqsave(&dev_priv->context_switch_lock, save);
  66         pfifo->reassign(dev, false);
  67         pfifo->cache_pull(dev, false);
  68
  69         nouveau_wait_for_idle(dev);
  70
  71         pfb->set_tile_region(dev, i);
  72         for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
  73                 if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
  74                         dev_priv->eng[j]->set_tile_region(dev, i);
  75         }
  76
  77         pfifo->cache_pull(dev, true);
  78         pfifo->reassign(dev, true);
  79         spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
  80 }
  81
  82 static struct nouveau_tile_reg *
  83 nv10_mem_get_tile_region(struct drm_device *dev, int i)
  84 {
  85         struct drm_nouveau_private *dev_priv = dev->dev_private;
  86         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  87
  88         spin_lock(&dev_priv->tile.lock);
  89
  90         if (!tile->used &&
  91             (!tile->fence || nouveau_fence_signalled(tile->fence)))
  92                 tile->used = true;
  93         else
  94                 tile = NULL;
  95
  96         spin_unlock(&dev_priv->tile.lock);
  97         return tile;
  98 }
  99
 100 void
 101 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
 102                          struct nouveau_fence *fence)
 103 {
 104         struct drm_nouveau_private *dev_priv = dev->dev_private;
 105
 106         if (tile) {
 107                 spin_lock(&dev_priv->tile.lock);
 108                 if (fence) {
 109                         /* Mark it as pending. */
 110                         tile->fence = fence;
 111                         nouveau_fence_ref(fence);
 112                 }
 113
 114                 tile->used = false;
 115                 spin_unlock(&dev_priv->tile.lock);
 116         }
 117 }
 118
 119 struct nouveau_tile_reg *
 120 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
 121                     uint32_t pitch, uint32_t flags)
 122 {
 123         struct drm_nouveau_private *dev_priv = dev->dev_private;
 124         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 125         struct nouveau_tile_reg *tile, *found = NULL;
 126         int i;
 127
 128         for (i = 0; i < pfb->num_tiles; i++) {
 129                 tile = nv10_mem_get_tile_region(dev, i);
 130
 131                 if (pitch && !found) {
 132                         found = tile;
 133                         continue;
 134
 135                 } else if (tile && tile->pitch) {
 136                         /* Kill an unused tile region. */
 137                         nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
 138                 }
 139
 140                 nv10_mem_put_tile_region(dev, tile, NULL);
 141         }
 142
 143         if (found)
 144                 nv10_mem_update_tile_region(dev, found, addr, size,
 145                                             pitch, flags);
 146         return found;
 147 }
 148
 149 /*
 150  * Cleanup everything
 151  */
 152 void
 153 nouveau_mem_vram_fini(struct drm_device *dev)
 154 {
 155         struct drm_nouveau_private *dev_priv = dev->dev_private;
 156
 157         ttm_bo_device_release(&dev_priv->ttm.bdev);
 158
 159         nouveau_ttm_global_release(dev_priv);
 160
 161         if (dev_priv->fb_mtrr >= 0) {
 162                 drm_mtrr_del(dev_priv->fb_mtrr,
 163                              pci_resource_start(dev->pdev, 1),
 164                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 165                 dev_priv->fb_mtrr = -1;
 166         }
 167 }
 168
 169 void
 170 nouveau_mem_gart_fini(struct drm_device *dev)
 171 {
 172         nouveau_sgdma_takedown(dev);
 173
 174         if (drm_core_has_AGP(dev) && dev->agp) {
 175                 struct drm_agp_mem *entry, *tempe;
 176
 177                 /* Remove AGP resources, but leave dev->agp
 178                    intact until drv_cleanup is called. */
 179                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 180                         if (entry->bound)
 181                                 drm_unbind_agp(entry->memory);
 182                         drm_free_agp(entry->memory, entry->pages);
 183                         kfree(entry);
 184                 }
 185                 INIT_LIST_HEAD(&dev->agp->memory);
 186
 187                 if (dev->agp->acquired)
 188                         drm_agp_release(dev);
 189
 190                 dev->agp->acquired = 0;
 191                 dev->agp->enabled = 0;
 192         }
 193 }
 194
 195 static uint32_t
 196 nouveau_mem_detect_nv04(struct drm_device *dev)
 197 {
 198         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 199
 200         if (boot0 & 0x00000100)
 201                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 202
 203         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 204         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 205                 return 32 * 1024 * 1024;
 206         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 207                 return 16 * 1024 * 1024;
 208         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 209                 return 8 * 1024 * 1024;
 210         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 211                 return 4 * 1024 * 1024;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static uint32_t
 218 nouveau_mem_detect_nforce(struct drm_device *dev)
 219 {
 220         struct drm_nouveau_private *dev_priv = dev->dev_private;
 221         struct pci_dev *bridge;
 222         uint32_t mem;
 223
 224         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 225         if (!bridge) {
 226                 NV_ERROR(dev, "no bridge device\n");
 227                 return 0;
 228         }
 229
 230         if (dev_priv->flags & NV_NFORCE) {
 231                 pci_read_config_dword(bridge, 0x7C, &mem);
 232                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 233         } else
 234         if (dev_priv->flags & NV_NFORCE2) {
 235                 pci_read_config_dword(bridge, 0x84, &mem);
 236                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 237         }
 238
 239         NV_ERROR(dev, "impossible!\n");
 240         return 0;
 241 }
 242
 243 int
 244 nouveau_mem_detect(struct drm_device *dev)
 245 {
 246         struct drm_nouveau_private *dev_priv = dev->dev_private;
 247
 248         if (dev_priv->card_type == NV_04) {
 249                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 250         } else
 251         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 252                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 253         } else
 254         if (dev_priv->card_type < NV_50) {
 255                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 256                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 257         }
 258
 259         if (dev_priv->vram_size)
 260                 return 0;
 261         return -ENOMEM;
 262 }
 263
 264 bool
 265 nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
 266 {
 267         if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
 268                 return true;
 269
 270         return false;
 271 }
 272
 273 #if __OS_HAS_AGP
 274 static unsigned long
 275 get_agp_mode(struct drm_device *dev, unsigned long mode)
 276 {
 277         struct drm_nouveau_private *dev_priv = dev->dev_private;
 278
 279         /*
 280          * FW seems to be broken on nv18, it makes the card lock up
 281          * randomly.
 282          */
 283         if (dev_priv->chipset == 0x18)
 284                 mode &= ~PCI_AGP_COMMAND_FW;
 285
 286         /*
 287          * AGP mode set in the command line.
 288          */
 289         if (nouveau_agpmode > 0) {
 290                 bool agpv3 = mode & 0x8;
 291                 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
 292
 293                 mode = (mode & ~0x7) | (rate & 0x7);
 294         }
 295
 296         return mode;
 297 }
 298 #endif
 299
 300 int
 301 nouveau_mem_reset_agp(struct drm_device *dev)
 302 {
 303 #if __OS_HAS_AGP
 304         uint32_t saved_pci_nv_1, pmc_enable;
 305         int ret;
 306
 307         /* First of all, disable fast writes, otherwise if it's
 308          * already enabled in the AGP bridge and we disable the card's
 309          * AGP controller we might be locking ourselves out of it. */
 310         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 311              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 312                 struct drm_agp_info info;
 313                 struct drm_agp_mode mode;
 314
 315                 ret = drm_agp_info(dev, &info);
 316                 if (ret)
 317                         return ret;
 318
 319                 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
 320                 ret = drm_agp_enable(dev, mode);
 321                 if (ret)
 322                         return ret;
 323         }
 324
 325         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 326
 327         /* clear busmaster bit */
 328         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 329         /* disable AGP */
 330         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 331
 332         /* power cycle pgraph, if enabled */
 333         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 334         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 335                 nv_wr32(dev, NV03_PMC_ENABLE,
 336                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 337                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 338                                 NV_PMC_ENABLE_PGRAPH);
 339         }
 340
 341         /* and restore (gives effect of resetting AGP) */
 342         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 343 #endif
 344
 345         return 0;
 346 }
 347
 348 int
 349 nouveau_mem_init_agp(struct drm_device *dev)
 350 {
 351 #if __OS_HAS_AGP
 352         struct drm_nouveau_private *dev_priv = dev->dev_private;
 353         struct drm_agp_info info;
 354         struct drm_agp_mode mode;
 355         int ret;
 356
 357         if (!dev->agp->acquired) {
 358                 ret = drm_agp_acquire(dev);
 359                 if (ret) {
 360                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 361                         return ret;
 362                 }
 363         }
 364
 365         nouveau_mem_reset_agp(dev);
 366
 367         ret = drm_agp_info(dev, &info);
 368         if (ret) {
 369                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 370                 return ret;
 371         }
 372
 373         /* see agp.h for the AGPSTAT_* modes available */
 374         mode.mode = get_agp_mode(dev, info.mode);
 375         ret = drm_agp_enable(dev, mode);
 376         if (ret) {
 377                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 378                 return ret;
 379         }
 380
 381         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 382         dev_priv->gart_info.aper_base   = info.aperture_base;
 383         dev_priv->gart_info.aper_size   = info.aperture_size;
 384 #endif
 385         return 0;
 386 }
 387
 388 int
 389 nouveau_mem_vram_init(struct drm_device *dev)
 390 {
 391         struct drm_nouveau_private *dev_priv = dev->dev_private;
 392         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 393         int ret, dma_bits;
 394
 395         dma_bits = 32;
 396         if (dev_priv->card_type >= NV_50) {
 397                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 398                         dma_bits = 40;
 399         } else
 400         if (0 && pci_is_pcie(dev->pdev) &&
 401             dev_priv->chipset  > 0x40 &&
 402             dev_priv->chipset != 0x45) {
 403                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
 404                         dma_bits = 39;
 405         }
 406
 407         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 408         if (ret)
 409                 return ret;
 410
 411         dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
 412
 413         ret = nouveau_ttm_global_init(dev_priv);
 414         if (ret)
 415                 return ret;
 416
 417         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 418                                  dev_priv->ttm.bo_global_ref.ref.object,
 419                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 420                                  dma_bits <= 32 ? true : false);
 421         if (ret) {
 422                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 423                 return ret;
 424         }
 425
 426         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 427         if (dev_priv->vram_sys_base) {
 428                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 429                         dev_priv->vram_sys_base);
 430         }
 431
 432         dev_priv->fb_available_size = dev_priv->vram_size;
 433         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 434         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 435                 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
 436         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 437
 438         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 439         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 440
 441         /* mappable vram */
 442         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 443                              dev_priv->fb_available_size >> PAGE_SHIFT);
 444         if (ret) {
 445                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 446                 return ret;
 447         }
 448
 449         if (dev_priv->card_type < NV_50) {
 450                 ret = nouveau_bo_new(dev, 256*1024, 0, TTM_PL_FLAG_VRAM,
 451                                      0, 0, &dev_priv->vga_ram);
 452                 if (ret == 0)
 453                         ret = nouveau_bo_pin(dev_priv->vga_ram,
 454                                              TTM_PL_FLAG_VRAM);
 455
 456                 if (ret) {
 457                         NV_WARN(dev, "failed to reserve VGA memory\n");
 458                         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 459                 }
 460         }
 461
 462         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 463                                          pci_resource_len(dev->pdev, 1),
 464                                          DRM_MTRR_WC);
 465         return 0;
 466 }
 467
 468 int
 469 nouveau_mem_gart_init(struct drm_device *dev)
 470 {
 471         struct drm_nouveau_private *dev_priv = dev->dev_private;
 472         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 473         int ret;
 474
 475         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 476
 477 #if !defined(__powerpc__) && !defined(__ia64__)
 478         if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
 479                 ret = nouveau_mem_init_agp(dev);
 480                 if (ret)
 481                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 482         }
 483 #endif
 484
 485         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 486                 ret = nouveau_sgdma_init(dev);
 487                 if (ret) {
 488                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 489                         return ret;
 490                 }
 491         }
 492
 493         NV_INFO(dev, "%d MiB GART (aperture)\n",
 494                 (int)(dev_priv->gart_info.aper_size >> 20));
 495         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 496
 497         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 498                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 499         if (ret) {
 500                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 501                 return ret;
 502         }
 503
 504         return 0;
 505 }
 506
 507 void
 508 nouveau_mem_timing_init(struct drm_device *dev)
 509 {
 510         /* cards < NVC0 only */
 511         struct drm_nouveau_private *dev_priv = dev->dev_private;
 512         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 513         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 514         struct nvbios *bios = &dev_priv->vbios;
 515         struct bit_entry P;
 516         u8 tUNK_0, tUNK_1, tUNK_2;
 517         u8 tRP;         /* Byte 3 */
 518         u8 tRAS;        /* Byte 5 */
 519         u8 tRFC;        /* Byte 7 */
 520         u8 tRC;         /* Byte 9 */
 521         u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
 522         u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
 523         u8 magic_number = 0; /* Yeah... sorry*/
 524         u8 *mem = NULL, *entry;
 525         int i, recordlen, entries;
 526
 527         if (bios->type == NVBIOS_BIT) {
 528                 if (bit_table(dev, 'P', &P))
 529                         return;
 530
 531                 if (P.version == 1)
 532                         mem = ROMPTR(bios, P.data[4]);
 533                 else
 534                 if (P.version == 2)
 535                         mem = ROMPTR(bios, P.data[8]);
 536                 else {
 537                         NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
 538                 }
 539         } else {
 540                 NV_DEBUG(dev, "BMP version too old for memory\n");
 541                 return;
 542         }
 543
 544         if (!mem) {
 545                 NV_DEBUG(dev, "memory timing table pointer invalid\n");
 546                 return;
 547         }
 548
 549         if (mem[0] != 0x10) {
 550                 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
 551                 return;
 552         }
 553
 554         /* validate record length */
 555         entries   = mem[2];
 556         recordlen = mem[3];
 557         if (recordlen < 15) {
 558                 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
 559                 return;
 560         }
 561
 562         /* parse vbios entries into common format */
 563         memtimings->timing =
 564                 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
 565         if (!memtimings->timing)
 566                 return;
 567
 568         /* Get "some number" from the timing reg for NV_40 and NV_50
 569          * Used in calculations later */
 570         if (dev_priv->card_type >= NV_40 && dev_priv->chipset < 0x98) {
 571                 magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24;
 572         }
 573
 574         entry = mem + mem[1];
 575         for (i = 0; i < entries; i++, entry += recordlen) {
 576                 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
 577                 if (entry[0] == 0)
 578                         continue;
 579
 580                 tUNK_18 = 1;
 581                 tUNK_19 = 1;
 582                 tUNK_20 = 0;
 583                 tUNK_21 = 0;
 584                 switch (min(recordlen, 22)) {
 585                 case 22:
 586                         tUNK_21 = entry[21];
 587                 case 21:
 588                         tUNK_20 = entry[20];
 589                 case 20:
 590                         tUNK_19 = entry[19];
 591                 case 19:
 592                         tUNK_18 = entry[18];
 593                 default:
 594                         tUNK_0  = entry[0];
 595                         tUNK_1  = entry[1];
 596                         tUNK_2  = entry[2];
 597                         tRP     = entry[3];
 598                         tRAS    = entry[5];
 599                         tRFC    = entry[7];
 600                         tRC     = entry[9];
 601                         tUNK_10 = entry[10];
 602                         tUNK_11 = entry[11];
 603                         tUNK_12 = entry[12];
 604                         tUNK_13 = entry[13];
 605                         tUNK_14 = entry[14];
 606                         break;
 607                 }
 608
 609                 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
 610
 611                 /* XXX: I don't trust the -1's and +1's... they must come
 612                  *      from somewhere! */
 613                 timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
 614                                       max(tUNK_18, (u8) 1) << 16 |
 615                                       (tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
 616                 if (dev_priv->chipset == 0xa8) {
 617                         timing->reg_100224 |= (tUNK_2 - 1);
 618                 } else {
 619                         timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
 620                 }
 621
 622                 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
 623                 if (dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa)
 624                         timing->reg_100228 |= (tUNK_19 - 1) << 24;
 625                 else
 626                         timing->reg_100228 |= magic_number << 24;
 627
 628                 if (dev_priv->card_type == NV_40) {
 629                         /* NV40: don't know what the rest of the regs are..
 630                          * And don't need to know either */
 631                         timing->reg_100228 |= 0x20200000;
 632                 } else if (dev_priv->card_type >= NV_50) {
 633                         if (dev_priv->chipset < 0x98 ||
 634                             (dev_priv->chipset == 0x98 &&
 635                              dev_priv->stepping <= 0xa1)) {
 636                                 timing->reg_10022c = (0x14 + tUNK_2) << 24 |
 637                                                      0x16 << 16 |
 638                                                      (tUNK_2 - 1) << 8 |
 639                                                      (tUNK_2 - 1);
 640                         } else {
 641                                 /* XXX: reg_10022c for recentish cards */
 642                                 timing->reg_10022c = tUNK_2 - 1;
 643                         }
 644
 645                         timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
 646                                                   tUNK_13 << 8  | tUNK_13);
 647
 648                         timing->reg_100234 = (tRAS << 24 | tRC);
 649                         timing->reg_100234 += max(tUNK_10, tUNK_11) << 16;
 650
 651                         if (dev_priv->chipset < 0x98 ||
 652                             (dev_priv->chipset == 0x98 &&
 653                              dev_priv->stepping <= 0xa1)) {
 654                                 timing->reg_100234 |= (tUNK_2 + 2) << 8;
 655                         } else {
 656                                 /* XXX: +6? */
 657                                 timing->reg_100234 |= (tUNK_19 + 6) << 8;
 658                         }
 659
 660                         /* XXX; reg_100238
 661                          * reg_100238: 0x00?????? */
 662                         timing->reg_10023c = 0x202;
 663                         if (dev_priv->chipset < 0x98 ||
 664                             (dev_priv->chipset == 0x98 &&
 665                              dev_priv->stepping <= 0xa1)) {
 666                                 timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
 667                         } else {
 668                                 /* XXX: reg_10023c
 669                                  * currently unknown
 670                                  * 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
 671                         }
 672
 673                         /* XXX: reg_100240? */
 674                 }
 675                 timing->id = i;
 676
 677                 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
 678                          timing->reg_100220, timing->reg_100224,
 679                          timing->reg_100228, timing->reg_10022c);
 680                 NV_DEBUG(dev, "         230: %08x %08x %08x %08x\n",
 681                          timing->reg_100230, timing->reg_100234,
 682                          timing->reg_100238, timing->reg_10023c);
 683                 NV_DEBUG(dev, "         240: %08x\n", timing->reg_100240);
 684         }
 685
 686         memtimings->nr_timing = entries;
 687         memtimings->supported = (dev_priv->chipset <= 0x98);
 688 }
 689
 690 void
 691 nouveau_mem_timing_fini(struct drm_device *dev)
 692 {
 693         struct drm_nouveau_private *dev_priv = dev->dev_private;
 694         struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
 695
 696         kfree(mem->timing);
 697 }
 698
 699 static int
 700 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 701 {
 702         /* nothing to do */
 703         return 0;
 704 }
 705
 706 static int
 707 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
 708 {
 709         /* nothing to do */
 710         return 0;
 711 }
 712
 713 static inline void
 714 nouveau_mem_node_cleanup(struct nouveau_mem *node)
 715 {
 716         if (node->vma[0].node) {
 717                 nouveau_vm_unmap(&node->vma[0]);
 718                 nouveau_vm_put(&node->vma[0]);
 719         }
 720
 721         if (node->vma[1].node) {
 722                 nouveau_vm_unmap(&node->vma[1]);
 723                 nouveau_vm_put(&node->vma[1]);
 724         }
 725 }
 726
 727 static void
 728 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
 729                          struct ttm_mem_reg *mem)
 730 {
 731         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 732         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 733         struct drm_device *dev = dev_priv->dev;
 734
 735         nouveau_mem_node_cleanup(mem->mm_node);
 736         vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
 737 }
 738
 739 static int
 740 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 741                          struct ttm_buffer_object *bo,
 742                          struct ttm_placement *placement,
 743                          struct ttm_mem_reg *mem)
 744 {
 745         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 746         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 747         struct drm_device *dev = dev_priv->dev;
 748         struct nouveau_bo *nvbo = nouveau_bo(bo);
 749         struct nouveau_mem *node;
 750         u32 size_nc = 0;
 751         int ret;
 752
 753         if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
 754                 size_nc = 1 << nvbo->page_shift;
 755
 756         ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
 757                         mem->page_alignment << PAGE_SHIFT, size_nc,
 758                         (nvbo->tile_flags >> 8) & 0x3ff, &node);
 759         if (ret) {
 760                 mem->mm_node = NULL;
 761                 return (ret == -ENOSPC) ? 0 : ret;
 762         }
 763
 764         node->page_shift = nvbo->page_shift;
 765
 766         mem->mm_node = node;
 767         mem->start   = node->offset >> PAGE_SHIFT;
 768         return 0;
 769 }
 770
 771 void
 772 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 773 {
 774         struct nouveau_mm *mm = man->priv;
 775         struct nouveau_mm_node *r;
 776         u32 total = 0, free = 0;
 777
 778         mutex_lock(&mm->mutex);
 779         list_for_each_entry(r, &mm->nodes, nl_entry) {
 780                 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
 781                        prefix, r->type, ((u64)r->offset << 12),
 782                        (((u64)r->offset + r->length) << 12));
 783
 784                 total += r->length;
 785                 if (!r->type)
 786                         free += r->length;
 787         }
 788         mutex_unlock(&mm->mutex);
 789
 790         printk(KERN_DEBUG "%s  total: 0x%010llx free: 0x%010llx\n",
 791                prefix, (u64)total << 12, (u64)free << 12);
 792         printk(KERN_DEBUG "%s  block: 0x%08x\n",
 793                prefix, mm->block_size << 12);
 794 }
 795
 796 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
 797         nouveau_vram_manager_init,
 798         nouveau_vram_manager_fini,
 799         nouveau_vram_manager_new,
 800         nouveau_vram_manager_del,
 801         nouveau_vram_manager_debug
 802 };
 803
 804 static int
 805 nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 806 {
 807         return 0;
 808 }
 809
 810 static int
 811 nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
 812 {
 813         return 0;
 814 }
 815
 816 static void
 817 nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
 818                          struct ttm_mem_reg *mem)
 819 {
 820         nouveau_mem_node_cleanup(mem->mm_node);
 821         kfree(mem->mm_node);
 822         mem->mm_node = NULL;
 823 }
 824
 825 static int
 826 nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
 827                          struct ttm_buffer_object *bo,
 828                          struct ttm_placement *placement,
 829                          struct ttm_mem_reg *mem)
 830 {
 831         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 832         struct nouveau_mem *node;
 833
 834         if (unlikely((mem->num_pages << PAGE_SHIFT) >=
 835                      dev_priv->gart_info.aper_size))
 836                 return -ENOMEM;
 837
 838         node = kzalloc(sizeof(*node), GFP_KERNEL);
 839         if (!node)
 840                 return -ENOMEM;
 841         node->page_shift = 12;
 842
 843         mem->mm_node = node;
 844         mem->start   = 0;
 845         return 0;
 846 }
 847
 848 void
 849 nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 850 {
 851 }
 852
 853 const struct ttm_mem_type_manager_func nouveau_gart_manager = {
 854         nouveau_gart_manager_init,
 855         nouveau_gart_manager_fini,
 856         nouveau_gart_manager_new,
 857         nouveau_gart_manager_del,
 858         nouveau_gart_manager_debug
 859 };