2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
32 nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
34 struct drm_device *dev = chan->dev;
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct nouveau_bo *pb = chan->pushbuf_bo;
37 struct nouveau_gpuobj *pushbuf = NULL;
40 if (dev_priv->card_type >= NV_50) {
41 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
42 dev_priv->vm_end, NV_DMA_ACCESS_RO,
43 NV_DMA_TARGET_AGP, &pushbuf);
44 chan->pushbuf_base = pb->bo.offset;
46 if (pb->bo.mem.mem_type == TTM_PL_TT) {
47 ret = nouveau_gpuobj_gart_dma_new(chan, 0,
48 dev_priv->gart_info.aper_size,
49 NV_DMA_ACCESS_RO, &pushbuf,
51 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
53 if (dev_priv->card_type != NV_04) {
54 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
55 dev_priv->fb_available_size,
57 NV_DMA_TARGET_VIDMEM, &pushbuf);
58 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
60 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
61 * exact reason for existing :) PCI access to cmdbuf in
64 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
65 pci_resource_start(dev->pdev,
67 dev_priv->fb_available_size,
69 NV_DMA_TARGET_PCI, &pushbuf);
70 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
73 nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);
74 nouveau_gpuobj_ref(NULL, &pushbuf);
78 static struct nouveau_bo *
79 nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
81 struct nouveau_bo *pushbuf = NULL;
84 if (nouveau_vram_pushbuf)
85 location = TTM_PL_FLAG_VRAM;
87 location = TTM_PL_FLAG_TT;
89 ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
92 NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
96 ret = nouveau_bo_pin(pushbuf, location);
98 NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
99 nouveau_bo_ref(NULL, &pushbuf);
106 /* allocates and initializes a fifo for user space consumption */
108 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
109 struct drm_file *file_priv,
110 uint32_t vram_handle, uint32_t tt_handle)
112 struct drm_nouveau_private *dev_priv = dev->dev_private;
113 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
114 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
115 struct nouveau_channel *chan;
120 * Alright, here is the full story
121 * Nvidia cards have multiple hw fifo contexts (praise them for that,
122 * no complicated crash-prone context switches)
123 * We allocate a new context for each app and let it write to it
124 * directly (woo, full userspace command submission !)
125 * When there are no more contexts, you lost
127 for (channel = 0; channel < pfifo->channels; channel++) {
128 if (dev_priv->fifos[channel] == NULL)
132 /* no more fifos. you lost. */
133 if (channel == pfifo->channels)
136 dev_priv->fifos[channel] = kzalloc(sizeof(struct nouveau_channel),
138 if (!dev_priv->fifos[channel])
140 chan = dev_priv->fifos[channel];
141 INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
142 INIT_LIST_HEAD(&chan->fence.pending);
145 chan->file_priv = file_priv;
146 chan->vram_handle = vram_handle;
147 chan->gart_handle = tt_handle;
149 NV_INFO(dev, "Allocating FIFO number %d\n", channel);
151 /* Allocate DMA push buffer */
152 chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
153 if (!chan->pushbuf_bo) {
155 NV_ERROR(dev, "pushbuf %d\n", ret);
156 nouveau_channel_free(chan);
160 nouveau_dma_pre_init(chan);
162 /* Locate channel's user control regs */
163 if (dev_priv->card_type < NV_40)
164 user = NV03_USER(channel);
166 if (dev_priv->card_type < NV_50)
167 user = NV40_USER(channel);
169 user = NV50_USER(channel);
171 chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
174 NV_ERROR(dev, "ioremap of regs failed.\n");
175 nouveau_channel_free(chan);
178 chan->user_put = 0x40;
179 chan->user_get = 0x44;
181 /* Allocate space for per-channel fixed notifier memory */
182 ret = nouveau_notifier_init_channel(chan);
184 NV_ERROR(dev, "ntfy %d\n", ret);
185 nouveau_channel_free(chan);
189 /* Setup channel's default objects */
190 ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
192 NV_ERROR(dev, "gpuobj %d\n", ret);
193 nouveau_channel_free(chan);
197 /* Create a dma object for the push buffer */
198 ret = nouveau_channel_pushbuf_ctxdma_init(chan);
200 NV_ERROR(dev, "pbctxdma %d\n", ret);
201 nouveau_channel_free(chan);
205 /* disable the fifo caches */
206 pfifo->reassign(dev, false);
208 /* Create a graphics context for new channel */
209 ret = pgraph->create_context(chan);
211 nouveau_channel_free(chan);
215 /* Construct inital RAMFC for new channel */
216 ret = pfifo->create_context(chan);
218 nouveau_channel_free(chan);
222 pfifo->reassign(dev, true);
224 ret = nouveau_dma_init(chan);
226 ret = nouveau_fence_channel_init(chan);
228 nouveau_channel_free(chan);
232 nouveau_debugfs_channel_init(chan);
234 NV_INFO(dev, "%s: initialised FIFO %d\n", __func__, channel);
241 nouveau_channel_free(struct nouveau_channel *chan)
243 struct drm_device *dev = chan->dev;
244 struct drm_nouveau_private *dev_priv = dev->dev_private;
245 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
246 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
250 NV_INFO(dev, "%s: freeing fifo %d\n", __func__, chan->id);
252 nouveau_debugfs_channel_fini(chan);
254 /* Give outstanding push buffers a chance to complete */
255 nouveau_fence_update(chan);
256 if (chan->fence.sequence != chan->fence.sequence_ack) {
257 struct nouveau_fence *fence = NULL;
259 ret = nouveau_fence_new(chan, &fence, true);
261 ret = nouveau_fence_wait(fence, NULL, false, false);
262 nouveau_fence_unref((void *)&fence);
266 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
269 /* Ensure all outstanding fences are signaled. They should be if the
270 * above attempts at idling were OK, but if we failed this'll tell TTM
271 * we're done with the buffers.
273 nouveau_fence_channel_fini(chan);
275 /* This will prevent pfifo from switching channels. */
276 pfifo->reassign(dev, false);
278 /* We want to give pgraph a chance to idle and get rid of all potential
279 * errors. We need to do this before the lock, otherwise the irq handler
280 * is unable to process them.
282 if (pgraph->channel(dev) == chan)
283 nouveau_wait_for_idle(dev);
285 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
287 pgraph->fifo_access(dev, false);
288 if (pgraph->channel(dev) == chan)
289 pgraph->unload_context(dev);
290 pgraph->destroy_context(chan);
291 pgraph->fifo_access(dev, true);
293 if (pfifo->channel_id(dev) == chan->id) {
295 pfifo->unload_context(dev);
298 pfifo->destroy_context(chan);
300 pfifo->reassign(dev, true);
302 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
304 /* Release the channel's resources */
305 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
306 if (chan->pushbuf_bo) {
307 nouveau_bo_unmap(chan->pushbuf_bo);
308 nouveau_bo_unpin(chan->pushbuf_bo);
309 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
311 nouveau_gpuobj_channel_takedown(chan);
312 nouveau_notifier_takedown_channel(chan);
316 dev_priv->fifos[chan->id] = NULL;
320 /* cleans up all the fifos from file_priv */
322 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
324 struct drm_nouveau_private *dev_priv = dev->dev_private;
325 struct nouveau_engine *engine = &dev_priv->engine;
328 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
329 for (i = 0; i < engine->fifo.channels; i++) {
330 struct nouveau_channel *chan = dev_priv->fifos[i];
332 if (chan && chan->file_priv == file_priv)
333 nouveau_channel_free(chan);
338 nouveau_channel_owner(struct drm_device *dev, struct drm_file *file_priv,
341 struct drm_nouveau_private *dev_priv = dev->dev_private;
342 struct nouveau_engine *engine = &dev_priv->engine;
344 if (channel >= engine->fifo.channels)
346 if (dev_priv->fifos[channel] == NULL)
349 return (dev_priv->fifos[channel]->file_priv == file_priv);
352 /***********************************
353 * ioctls wrapping the functions
354 ***********************************/
357 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
358 struct drm_file *file_priv)
360 struct drm_nouveau_private *dev_priv = dev->dev_private;
361 struct drm_nouveau_channel_alloc *init = data;
362 struct nouveau_channel *chan;
365 if (dev_priv->engine.graph.accel_blocked)
368 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
371 ret = nouveau_channel_alloc(dev, &chan, file_priv,
372 init->fb_ctxdma_handle,
373 init->tt_ctxdma_handle);
376 init->channel = chan->id;
378 if (chan->dma.ib_max)
379 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
380 NOUVEAU_GEM_DOMAIN_GART;
381 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
382 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
384 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
386 init->subchan[0].handle = NvM2MF;
387 if (dev_priv->card_type < NV_50)
388 init->subchan[0].grclass = 0x0039;
390 init->subchan[0].grclass = 0x5039;
391 init->subchan[1].handle = NvSw;
392 init->subchan[1].grclass = NV_SW;
393 init->nr_subchan = 2;
395 /* Named memory object area */
396 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
397 &init->notifier_handle);
399 nouveau_channel_free(chan);
407 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
408 struct drm_file *file_priv)
410 struct drm_nouveau_channel_free *cfree = data;
411 struct nouveau_channel *chan;
413 NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);
415 nouveau_channel_free(chan);
419 /***********************************
420 * finally, the ioctl table
421 ***********************************/
423 struct drm_ioctl_desc nouveau_ioctls[] = {
424 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
425 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
426 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
427 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
428 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
429 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
430 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
431 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
432 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
433 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
434 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
435 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
438 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);