drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include "drmP.h"
  31
  32 #include "nouveau_drm.h"
  33 #include "nouveau_drv.h"
  34 #include "nouveau_dma.h"
  35
  36 #include <linux/log2.h>
  37 #include <linux/slab.h>
  38
  39 static void
  40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  41 {
  42         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  43         struct drm_device *dev = dev_priv->dev;
  44         struct nouveau_bo *nvbo = nouveau_bo(bo);
  45
  46         ttm_bo_kunmap(&nvbo->kmap);
  47
  48         if (unlikely(nvbo->gem))
  49                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
  50
  51         if (nvbo->tile)
  52                 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
  53
  54         spin_lock(&dev_priv->ttm.bo_list_lock);
  55         list_del(&nvbo->head);
  56         spin_unlock(&dev_priv->ttm.bo_list_lock);
  57         kfree(nvbo);
  58 }
  59
  60 static void
  61 nouveau_bo_fixup_align(struct drm_device *dev,
  62                        uint32_t tile_mode, uint32_t tile_flags,
  63                        int *align, int *size)
  64 {
  65         struct drm_nouveau_private *dev_priv = dev->dev_private;
  66
  67         /*
  68          * Some of the tile_flags have a periodic structure of N*4096 bytes,
  69          * align to to that as well as the page size. Align the size to the
  70          * appropriate boundaries. This does imply that sizes are rounded up
  71          * 3-7 pages, so be aware of this and do not waste memory by allocating
  72          * many small buffers.
  73          */
  74         if (dev_priv->card_type == NV_50) {
  75                 uint32_t block_size = dev_priv->vram_size >> 15;
  76                 int i;
  77
  78                 switch (tile_flags) {
  79                 case 0x1800:
  80                 case 0x2800:
  81                 case 0x4800:
  82                 case 0x7a00:
  83                         if (is_power_of_2(block_size)) {
  84                                 for (i = 1; i < 10; i++) {
  85                                         *align = 12 * i * block_size;
  86                                         if (!(*align % 65536))
  87                                                 break;
  88                                 }
  89                         } else {
  90                                 for (i = 1; i < 10; i++) {
  91                                         *align = 8 * i * block_size;
  92                                         if (!(*align % 65536))
  93                                                 break;
  94                                 }
  95                         }
  96                         *size = roundup(*size, *align);
  97                         break;
  98                 default:
  99                         break;
 100                 }
 101
 102         } else {
 103                 if (tile_mode) {
 104                         if (dev_priv->chipset >= 0x40) {
 105                                 *align = 65536;
 106                                 *size = roundup(*size, 64 * tile_mode);
 107
 108                         } else if (dev_priv->chipset >= 0x30) {
 109                                 *align = 32768;
 110                                 *size = roundup(*size, 64 * tile_mode);
 111
 112                         } else if (dev_priv->chipset >= 0x20) {
 113                                 *align = 16384;
 114                                 *size = roundup(*size, 64 * tile_mode);
 115
 116                         } else if (dev_priv->chipset >= 0x10) {
 117                                 *align = 16384;
 118                                 *size = roundup(*size, 32 * tile_mode);
 119                         }
 120                 }
 121         }
 122
 123         /* ALIGN works only on powers of two. */
 124         *size = roundup(*size, PAGE_SIZE);
 125
 126         if (dev_priv->card_type == NV_50) {
 127                 *size = roundup(*size, 65536);
 128                 *align = max(65536, *align);
 129         }
 130 }
 131
 132 int
 133 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
 134                int size, int align, uint32_t flags, uint32_t tile_mode,
 135                uint32_t tile_flags, bool no_vm, bool mappable,
 136                struct nouveau_bo **pnvbo)
 137 {
 138         struct drm_nouveau_private *dev_priv = dev->dev_private;
 139         struct nouveau_bo *nvbo;
 140         int ret = 0;
 141
 142         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 143         if (!nvbo)
 144                 return -ENOMEM;
 145         INIT_LIST_HEAD(&nvbo->head);
 146         INIT_LIST_HEAD(&nvbo->entry);
 147         nvbo->mappable = mappable;
 148         nvbo->no_vm = no_vm;
 149         nvbo->tile_mode = tile_mode;
 150         nvbo->tile_flags = tile_flags;
 151
 152         nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
 153         align >>= PAGE_SHIFT;
 154
 155         nvbo->placement.fpfn = 0;
 156         nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
 157         nouveau_bo_placement_set(nvbo, flags, 0);
 158
 159         nvbo->channel = chan;
 160         ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
 161                           ttm_bo_type_device, &nvbo->placement, align, 0,
 162                           false, NULL, size, nouveau_bo_del_ttm);
 163         if (ret) {
 164                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 165                 return ret;
 166         }
 167         nvbo->channel = NULL;
 168
 169         spin_lock(&dev_priv->ttm.bo_list_lock);
 170         list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
 171         spin_unlock(&dev_priv->ttm.bo_list_lock);
 172         *pnvbo = nvbo;
 173         return 0;
 174 }
 175
 176 static void
 177 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
 178 {
 179         *n = 0;
 180
 181         if (type & TTM_PL_FLAG_VRAM)
 182                 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
 183         if (type & TTM_PL_FLAG_TT)
 184                 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
 185         if (type & TTM_PL_FLAG_SYSTEM)
 186                 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
 187 }
 188
 189 void
 190 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 191 {
 192         struct ttm_placement *pl = &nvbo->placement;
 193         uint32_t flags = TTM_PL_MASK_CACHING |
 194                 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 195
 196         pl->placement = nvbo->placements;
 197         set_placement_list(nvbo->placements, &pl->num_placement,
 198                            type, flags);
 199
 200         pl->busy_placement = nvbo->busy_placements;
 201         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 202                            type | busy, flags);
 203 }
 204
 205 int
 206 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
 207 {
 208         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 209         struct ttm_buffer_object *bo = &nvbo->bo;
 210         int ret;
 211
 212         if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
 213                 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
 214                          "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
 215                          1 << bo->mem.mem_type, memtype);
 216                 return -EINVAL;
 217         }
 218
 219         if (nvbo->pin_refcnt++)
 220                 return 0;
 221
 222         ret = ttm_bo_reserve(bo, false, false, false, 0);
 223         if (ret)
 224                 goto out;
 225
 226         nouveau_bo_placement_set(nvbo, memtype, 0);
 227
 228         ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
 229         if (ret == 0) {
 230                 switch (bo->mem.mem_type) {
 231                 case TTM_PL_VRAM:
 232                         dev_priv->fb_aper_free -= bo->mem.size;
 233                         break;
 234                 case TTM_PL_TT:
 235                         dev_priv->gart_info.aper_free -= bo->mem.size;
 236                         break;
 237                 default:
 238                         break;
 239                 }
 240         }
 241         ttm_bo_unreserve(bo);
 242 out:
 243         if (unlikely(ret))
 244                 nvbo->pin_refcnt--;
 245         return ret;
 246 }
 247
 248 int
 249 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 250 {
 251         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 252         struct ttm_buffer_object *bo = &nvbo->bo;
 253         int ret;
 254
 255         if (--nvbo->pin_refcnt)
 256                 return 0;
 257
 258         ret = ttm_bo_reserve(bo, false, false, false, 0);
 259         if (ret)
 260                 return ret;
 261
 262         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 263
 264         ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
 265         if (ret == 0) {
 266                 switch (bo->mem.mem_type) {
 267                 case TTM_PL_VRAM:
 268                         dev_priv->fb_aper_free += bo->mem.size;
 269                         break;
 270                 case TTM_PL_TT:
 271                         dev_priv->gart_info.aper_free += bo->mem.size;
 272                         break;
 273                 default:
 274                         break;
 275                 }
 276         }
 277
 278         ttm_bo_unreserve(bo);
 279         return ret;
 280 }
 281
 282 int
 283 nouveau_bo_map(struct nouveau_bo *nvbo)
 284 {
 285         int ret;
 286
 287         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
 288         if (ret)
 289                 return ret;
 290
 291         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 292         ttm_bo_unreserve(&nvbo->bo);
 293         return ret;
 294 }
 295
 296 void
 297 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 298 {
 299         ttm_bo_kunmap(&nvbo->kmap);
 300 }
 301
 302 u16
 303 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
 304 {
 305         bool is_iomem;
 306         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 307         mem = &mem[index];
 308         if (is_iomem)
 309                 return ioread16_native((void __force __iomem *)mem);
 310         else
 311                 return *mem;
 312 }
 313
 314 void
 315 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 316 {
 317         bool is_iomem;
 318         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 319         mem = &mem[index];
 320         if (is_iomem)
 321                 iowrite16_native(val, (void __force __iomem *)mem);
 322         else
 323                 *mem = val;
 324 }
 325
 326 u32
 327 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 328 {
 329         bool is_iomem;
 330         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 331         mem = &mem[index];
 332         if (is_iomem)
 333                 return ioread32_native((void __force __iomem *)mem);
 334         else
 335                 return *mem;
 336 }
 337
 338 void
 339 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 340 {
 341         bool is_iomem;
 342         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 343         mem = &mem[index];
 344         if (is_iomem)
 345                 iowrite32_native(val, (void __force __iomem *)mem);
 346         else
 347                 *mem = val;
 348 }
 349
 350 static struct ttm_backend *
 351 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
 352 {
 353         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 354         struct drm_device *dev = dev_priv->dev;
 355
 356         switch (dev_priv->gart_info.type) {
 357 #if __OS_HAS_AGP
 358         case NOUVEAU_GART_AGP:
 359                 return ttm_agp_backend_init(bdev, dev->agp->bridge);
 360 #endif
 361         case NOUVEAU_GART_SGDMA:
 362                 return nouveau_sgdma_init_ttm(dev);
 363         default:
 364                 NV_ERROR(dev, "Unknown GART type %d\n",
 365                          dev_priv->gart_info.type);
 366                 break;
 367         }
 368
 369         return NULL;
 370 }
 371
 372 static int
 373 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 374 {
 375         /* We'll do this from user space. */
 376         return 0;
 377 }
 378
 379 static int
 380 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 381                          struct ttm_mem_type_manager *man)
 382 {
 383         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 384         struct drm_device *dev = dev_priv->dev;
 385
 386         switch (type) {
 387         case TTM_PL_SYSTEM:
 388                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 389                 man->available_caching = TTM_PL_MASK_CACHING;
 390                 man->default_caching = TTM_PL_FLAG_CACHED;
 391                 break;
 392         case TTM_PL_VRAM:
 393                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 394                              TTM_MEMTYPE_FLAG_MAPPABLE;
 395                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 396                                          TTM_PL_FLAG_WC;
 397                 man->default_caching = TTM_PL_FLAG_WC;
 398                 man->gpu_offset = dev_priv->vm_vram_base;
 399                 break;
 400         case TTM_PL_TT:
 401                 switch (dev_priv->gart_info.type) {
 402                 case NOUVEAU_GART_AGP:
 403                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 404                         man->available_caching = TTM_PL_FLAG_UNCACHED;
 405                         man->default_caching = TTM_PL_FLAG_UNCACHED;
 406                         break;
 407                 case NOUVEAU_GART_SGDMA:
 408                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 409                                      TTM_MEMTYPE_FLAG_CMA;
 410                         man->available_caching = TTM_PL_MASK_CACHING;
 411                         man->default_caching = TTM_PL_FLAG_CACHED;
 412                         break;
 413                 default:
 414                         NV_ERROR(dev, "Unknown GART type: %d\n",
 415                                  dev_priv->gart_info.type);
 416                         return -EINVAL;
 417                 }
 418                 man->gpu_offset = dev_priv->vm_gart_base;
 419                 break;
 420         default:
 421                 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
 422                 return -EINVAL;
 423         }
 424         return 0;
 425 }
 426
 427 static void
 428 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 429 {
 430         struct nouveau_bo *nvbo = nouveau_bo(bo);
 431
 432         switch (bo->mem.mem_type) {
 433         case TTM_PL_VRAM:
 434                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 435                                          TTM_PL_FLAG_SYSTEM);
 436                 break;
 437         default:
 438                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 439                 break;
 440         }
 441
 442         *pl = nvbo->placement;
 443 }
 444
 445
 446 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
 447  * TTM_PL_{VRAM,TT} directly.
 448  */
 449
 450 static int
 451 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
 452                               struct nouveau_bo *nvbo, bool evict,
 453                               bool no_wait_reserve, bool no_wait_gpu,
 454                               struct ttm_mem_reg *new_mem)
 455 {
 456         struct nouveau_fence *fence = NULL;
 457         int ret;
 458
 459         ret = nouveau_fence_new(chan, &fence, true);
 460         if (ret)
 461                 return ret;
 462
 463         ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
 464                                         evict, no_wait_reserve, no_wait_gpu, new_mem);
 465         if (nvbo->channel && nvbo->channel != chan)
 466                 ret = nouveau_fence_wait(fence, NULL, false, false);
 467         nouveau_fence_unref((void *)&fence);
 468         return ret;
 469 }
 470
 471 static inline uint32_t
 472 nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
 473                       struct ttm_mem_reg *mem)
 474 {
 475         if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) {
 476                 if (mem->mem_type == TTM_PL_TT)
 477                         return NvDmaGART;
 478                 return NvDmaVRAM;
 479         }
 480
 481         if (mem->mem_type == TTM_PL_TT)
 482                 return chan->gart_handle;
 483         return chan->vram_handle;
 484 }
 485
 486 static int
 487 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 488                      bool no_wait_reserve, bool no_wait_gpu,
 489                      struct ttm_mem_reg *new_mem)
 490 {
 491         struct nouveau_bo *nvbo = nouveau_bo(bo);
 492         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 493         struct ttm_mem_reg *old_mem = &bo->mem;
 494         struct nouveau_channel *chan;
 495         uint64_t src_offset, dst_offset;
 496         uint32_t page_count;
 497         int ret;
 498
 499         chan = nvbo->channel;
 500         if (!chan || nvbo->tile_flags || nvbo->no_vm)
 501                 chan = dev_priv->channel;
 502
 503         src_offset = old_mem->mm_node->start << PAGE_SHIFT;
 504         dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
 505         if (chan != dev_priv->channel) {
 506                 if (old_mem->mem_type == TTM_PL_TT)
 507                         src_offset += dev_priv->vm_gart_base;
 508                 else
 509                         src_offset += dev_priv->vm_vram_base;
 510
 511                 if (new_mem->mem_type == TTM_PL_TT)
 512                         dst_offset += dev_priv->vm_gart_base;
 513                 else
 514                         dst_offset += dev_priv->vm_vram_base;
 515         }
 516
 517         ret = RING_SPACE(chan, 3);
 518         if (ret)
 519                 return ret;
 520         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 521         OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem));
 522         OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem));
 523
 524         if (dev_priv->card_type >= NV_50) {
 525                 ret = RING_SPACE(chan, 4);
 526                 if (ret)
 527                         return ret;
 528                 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
 529                 OUT_RING(chan, 1);
 530                 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
 531                 OUT_RING(chan, 1);
 532         }
 533
 534         page_count = new_mem->num_pages;
 535         while (page_count) {
 536                 int line_count = (page_count > 2047) ? 2047 : page_count;
 537
 538                 if (dev_priv->card_type >= NV_50) {
 539                         ret = RING_SPACE(chan, 3);
 540                         if (ret)
 541                                 return ret;
 542                         BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
 543                         OUT_RING(chan, upper_32_bits(src_offset));
 544                         OUT_RING(chan, upper_32_bits(dst_offset));
 545                 }
 546                 ret = RING_SPACE(chan, 11);
 547                 if (ret)
 548                         return ret;
 549                 BEGIN_RING(chan, NvSubM2MF,
 550                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 551                 OUT_RING(chan, lower_32_bits(src_offset));
 552                 OUT_RING(chan, lower_32_bits(dst_offset));
 553                 OUT_RING(chan, PAGE_SIZE); /* src_pitch */
 554                 OUT_RING(chan, PAGE_SIZE); /* dst_pitch */
 555                 OUT_RING(chan, PAGE_SIZE); /* line_length */
 556                 OUT_RING(chan, line_count);
 557                 OUT_RING(chan, (1<<8)|(1<<0));
 558                 OUT_RING(chan, 0);
 559                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 560                 OUT_RING(chan, 0);
 561
 562                 page_count -= line_count;
 563                 src_offset += (PAGE_SIZE * line_count);
 564                 dst_offset += (PAGE_SIZE * line_count);
 565         }
 566
 567         return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 568 }
 569
 570 static int
 571 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 572                       bool no_wait_reserve, bool no_wait_gpu,
 573                       struct ttm_mem_reg *new_mem)
 574 {
 575         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 576         struct ttm_placement placement;
 577         struct ttm_mem_reg tmp_mem;
 578         int ret;
 579
 580         placement.fpfn = placement.lpfn = 0;
 581         placement.num_placement = placement.num_busy_placement = 1;
 582         placement.placement = placement.busy_placement = &placement_memtype;
 583
 584         tmp_mem = *new_mem;
 585         tmp_mem.mm_node = NULL;
 586         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 587         if (ret)
 588                 return ret;
 589
 590         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
 591         if (ret)
 592                 goto out;
 593
 594         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
 595         if (ret)
 596                 goto out;
 597
 598         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 599 out:
 600         if (tmp_mem.mm_node) {
 601                 spin_lock(&bo->bdev->glob->lru_lock);
 602                 drm_mm_put_block(tmp_mem.mm_node);
 603                 spin_unlock(&bo->bdev->glob->lru_lock);
 604         }
 605
 606         return ret;
 607 }
 608
 609 static int
 610 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 611                       bool no_wait_reserve, bool no_wait_gpu,
 612                       struct ttm_mem_reg *new_mem)
 613 {
 614         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 615         struct ttm_placement placement;
 616         struct ttm_mem_reg tmp_mem;
 617         int ret;
 618
 619         placement.fpfn = placement.lpfn = 0;
 620         placement.num_placement = placement.num_busy_placement = 1;
 621         placement.placement = placement.busy_placement = &placement_memtype;
 622
 623         tmp_mem = *new_mem;
 624         tmp_mem.mm_node = NULL;
 625         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 626         if (ret)
 627                 return ret;
 628
 629         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
 630         if (ret)
 631                 goto out;
 632
 633         ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 634         if (ret)
 635                 goto out;
 636
 637 out:
 638         if (tmp_mem.mm_node) {
 639                 spin_lock(&bo->bdev->glob->lru_lock);
 640                 drm_mm_put_block(tmp_mem.mm_node);
 641                 spin_unlock(&bo->bdev->glob->lru_lock);
 642         }
 643
 644         return ret;
 645 }
 646
 647 static int
 648 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
 649                    struct nouveau_tile_reg **new_tile)
 650 {
 651         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 652         struct drm_device *dev = dev_priv->dev;
 653         struct nouveau_bo *nvbo = nouveau_bo(bo);
 654         uint64_t offset;
 655         int ret;
 656
 657         if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
 658                 /* Nothing to do. */
 659                 *new_tile = NULL;
 660                 return 0;
 661         }
 662
 663         offset = new_mem->mm_node->start << PAGE_SHIFT;
 664
 665         if (dev_priv->card_type == NV_50) {
 666                 ret = nv50_mem_vm_bind_linear(dev,
 667                                               offset + dev_priv->vm_vram_base,
 668                                               new_mem->size, nvbo->tile_flags,
 669                                               offset);
 670                 if (ret)
 671                         return ret;
 672
 673         } else if (dev_priv->card_type >= NV_10) {
 674                 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
 675                                                 nvbo->tile_mode);
 676         }
 677
 678         return 0;
 679 }
 680
 681 static void
 682 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
 683                       struct nouveau_tile_reg *new_tile,
 684                       struct nouveau_tile_reg **old_tile)
 685 {
 686         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 687         struct drm_device *dev = dev_priv->dev;
 688
 689         if (dev_priv->card_type >= NV_10 &&
 690             dev_priv->card_type < NV_50) {
 691                 if (*old_tile)
 692                         nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
 693
 694                 *old_tile = new_tile;
 695         }
 696 }
 697
 698 static int
 699 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
 700                 bool no_wait_reserve, bool no_wait_gpu,
 701                 struct ttm_mem_reg *new_mem)
 702 {
 703         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 704         struct nouveau_bo *nvbo = nouveau_bo(bo);
 705         struct ttm_mem_reg *old_mem = &bo->mem;
 706         struct nouveau_tile_reg *new_tile = NULL;
 707         int ret = 0;
 708
 709         ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
 710         if (ret)
 711                 return ret;
 712
 713         /* Software copy if the card isn't up and running yet. */
 714         if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
 715             !dev_priv->channel) {
 716                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 717                 goto out;
 718         }
 719
 720         /* Fake bo copy. */
 721         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
 722                 BUG_ON(bo->mem.mm_node != NULL);
 723                 bo->mem = *new_mem;
 724                 new_mem->mm_node = NULL;
 725                 goto out;
 726         }
 727
 728         /* Hardware assisted copy. */
 729         if (new_mem->mem_type == TTM_PL_SYSTEM)
 730                 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 731         else if (old_mem->mem_type == TTM_PL_SYSTEM)
 732                 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 733         else
 734                 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 735
 736         if (!ret)
 737                 goto out;
 738
 739         /* Fallback to software copy. */
 740         ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 741
 742 out:
 743         if (ret)
 744                 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
 745         else
 746                 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
 747
 748         return ret;
 749 }
 750
 751 static int
 752 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 753 {
 754         return 0;
 755 }
 756
 757 static int
 758 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 759 {
 760         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 761         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 762         struct drm_device *dev = dev_priv->dev;
 763
 764         mem->bus.addr = NULL;
 765         mem->bus.offset = 0;
 766         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 767         mem->bus.base = 0;
 768         mem->bus.is_iomem = false;
 769         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 770                 return -EINVAL;
 771         switch (mem->mem_type) {
 772         case TTM_PL_SYSTEM:
 773                 /* System memory */
 774                 return 0;
 775         case TTM_PL_TT:
 776 #if __OS_HAS_AGP
 777                 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
 778                         mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
 779                         mem->bus.base = dev_priv->gart_info.aper_base;
 780                         mem->bus.is_iomem = true;
 781                 }
 782 #endif
 783                 break;
 784         case TTM_PL_VRAM:
 785                 mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
 786                 mem->bus.base = drm_get_resource_start(dev, 1);
 787                 mem->bus.is_iomem = true;
 788                 break;
 789         default:
 790                 return -EINVAL;
 791         }
 792         return 0;
 793 }
 794
 795 static void
 796 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 797 {
 798 }
 799
 800 static int
 801 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
 802 {
 803         return 0;
 804 }
 805
 806 struct ttm_bo_driver nouveau_bo_driver = {
 807         .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
 808         .invalidate_caches = nouveau_bo_invalidate_caches,
 809         .init_mem_type = nouveau_bo_init_mem_type,
 810         .evict_flags = nouveau_bo_evict_flags,
 811         .move = nouveau_bo_move,
 812         .verify_access = nouveau_bo_verify_access,
 813         .sync_obj_signaled = nouveau_fence_signalled,
 814         .sync_obj_wait = nouveau_fence_wait,
 815         .sync_obj_flush = nouveau_fence_flush,
 816         .sync_obj_unref = nouveau_fence_unref,
 817         .sync_obj_ref = nouveau_fence_ref,
 818         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
 819         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
 820         .io_mem_free = &nouveau_ttm_io_mem_free,
 821 };
 822