2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
30 #include "nouveau_gpio.h"
32 #include <linux/io-mapping.h>
34 /* these defines are made up */
35 #define NV_CIO_CRE_44_HEADA 0x0
36 #define NV_CIO_CRE_44_HEADB 0x3
37 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
41 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42 #define LOG_OLD_VALUE(x)
49 static bool nv_cksum(const uint8_t *data, unsigned int length)
52 * There's a few checksums in the BIOS, so here's a generic checking
58 for (i = 0; i < length; i++)
68 score_vbios(struct nvbios *bios, const bool writeable)
70 if (!bios->data || bios->data[0] != 0x55 || bios->data[1] != 0xAA) {
71 NV_TRACEWARN(bios->dev, "... BIOS signature not found\n");
75 if (nv_cksum(bios->data, bios->data[2] * 512)) {
76 NV_TRACEWARN(bios->dev, "... BIOS checksum invalid\n");
77 /* if a ro image is somewhat bad, it's probably all rubbish */
78 return writeable ? 2 : 1;
81 NV_TRACE(bios->dev, "... appears to be valid\n");
86 bios_shadow_prom(struct nvbios *bios)
88 struct drm_device *dev = bios->dev;
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 /* enable access to rom */
95 if (dev_priv->card_type >= NV_50)
98 pcireg = NV_PBUS_PCI_NV_20;
99 access = nv_mask(dev, pcireg, 0x00000001, 0x00000000);
101 /* bail if no rom signature, with a workaround for a PROM reading
102 * issue on some chipsets. the first read after a period of
103 * inactivity returns the wrong result, so retry the first header
104 * byte a few times before giving up as a workaround
108 if (nv_rd08(dev, NV_PROM_OFFSET + 0) == 0x55)
112 if (!i || nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
115 /* additional check (see note below) - read PCI record header */
116 pcir = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
117 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
118 if (nv_rd08(dev, NV_PROM_OFFSET + pcir + 0) != 'P' ||
119 nv_rd08(dev, NV_PROM_OFFSET + pcir + 1) != 'C' ||
120 nv_rd08(dev, NV_PROM_OFFSET + pcir + 2) != 'I' ||
121 nv_rd08(dev, NV_PROM_OFFSET + pcir + 3) != 'R')
124 /* read entire bios image to system memory */
125 bios->length = nv_rd08(dev, NV_PROM_OFFSET + 2) * 512;
126 bios->data = kmalloc(bios->length, GFP_KERNEL);
128 for (i = 0; i < bios->length; i++)
129 bios->data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
133 /* disable access to rom */
134 nv_wr32(dev, pcireg, access);
138 bios_shadow_pramin(struct nvbios *bios)
140 struct drm_device *dev = bios->dev;
141 struct drm_nouveau_private *dev_priv = dev->dev_private;
145 if (dev_priv->card_type >= NV_50) {
146 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
148 addr = (u64)nv_rd32(dev, 0x001700) << 16;
152 bar0 = nv_mask(dev, 0x001700, 0xffffffff, addr >> 16);
155 /* bail if no rom signature */
156 if (nv_rd08(dev, NV_PRAMIN_OFFSET + 0) != 0x55 ||
157 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
160 bios->length = nv_rd08(dev, NV_PRAMIN_OFFSET + 2) * 512;
161 bios->data = kmalloc(bios->length, GFP_KERNEL);
163 for (i = 0; i < bios->length; i++)
164 bios->data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
168 if (dev_priv->card_type >= NV_50)
169 nv_wr32(dev, 0x001700, bar0);
173 bios_shadow_pci(struct nvbios *bios)
175 struct pci_dev *pdev = bios->dev->pdev;
178 if (!pci_enable_rom(pdev)) {
179 void __iomem *rom = pci_map_rom(pdev, &length);
181 bios->data = kmalloc(length, GFP_KERNEL);
183 memcpy_fromio(bios->data, rom, length);
184 bios->length = length;
188 pci_unmap_rom(pdev, rom);
190 pci_disable_rom(pdev);
195 bios_shadow_acpi(struct nvbios *bios)
197 struct pci_dev *pdev = bios->dev->pdev;
201 if (!nouveau_acpi_rom_supported(pdev))
204 ret = nouveau_acpi_get_bios_chunk(data, 0, sizeof(data));
205 if (ret != sizeof(data))
208 bios->length = min(data[2] * 512, 65536);
209 bios->data = kmalloc(bios->length, GFP_KERNEL);
216 int size = (len > ROM_BIOS_PAGE) ? ROM_BIOS_PAGE : len;
218 ret = nouveau_acpi_get_bios_chunk(bios->data, ptr, size);
232 void (*shadow)(struct nvbios *);
240 bios_shadow(struct drm_device *dev)
242 struct methods shadow_methods[] = {
243 { "PRAMIN", bios_shadow_pramin, true, 0, 0, NULL },
244 { "PROM", bios_shadow_prom, false, 0, 0, NULL },
245 { "ACPI", bios_shadow_acpi, true, 0, 0, NULL },
246 { "PCIROM", bios_shadow_pci, true, 0, 0, NULL },
249 struct drm_nouveau_private *dev_priv = dev->dev_private;
250 struct nvbios *bios = &dev_priv->vbios;
251 struct methods *mthd, *best;
254 mthd = shadow_methods;
256 if (strcasecmp(nouveau_vbios, mthd->desc))
258 NV_INFO(dev, "VBIOS source: %s\n", mthd->desc);
261 mthd->score = score_vbios(bios, mthd->rw);
264 } while ((++mthd)->shadow);
266 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
269 mthd = shadow_methods;
271 NV_TRACE(dev, "Checking %s for VBIOS\n", mthd->desc);
273 mthd->score = score_vbios(bios, mthd->rw);
274 mthd->size = bios->length;
275 mthd->data = bios->data;
277 } while (mthd->score != 3 && (++mthd)->shadow);
279 mthd = shadow_methods;
282 if (mthd->score > best->score) {
287 } while ((++mthd)->shadow);
290 NV_TRACE(dev, "Using VBIOS from %s\n", best->desc);
291 bios->length = best->size;
292 bios->data = best->data;
296 NV_ERROR(dev, "No valid VBIOS image found\n");
300 struct init_tbl_entry {
304 * > 0: success, length of opcode
305 * 0: success, but abort further parsing of table (INIT_DONE etc)
306 * < 0: failure, table parsing will be aborted
308 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
311 static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
313 #define MACRO_INDEX_SIZE 2
315 #define CONDITION_SIZE 12
316 #define IO_FLAG_CONDITION_SIZE 9
317 #define IO_CONDITION_SIZE 5
318 #define MEM_INIT_SIZE 66
320 static void still_alive(void)
329 munge_reg(struct nvbios *bios, uint32_t reg)
331 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
332 struct dcb_entry *dcbent = bios->display.output;
334 if (dev_priv->card_type < NV_50)
337 if (reg & 0x80000000) {
338 BUG_ON(bios->display.crtc < 0);
339 reg += bios->display.crtc * 0x800;
342 if (reg & 0x40000000) {
345 reg += (ffs(dcbent->or) - 1) * 0x800;
346 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
355 valid_reg(struct nvbios *bios, uint32_t reg)
357 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
358 struct drm_device *dev = bios->dev;
360 /* C51 has misaligned regs on purpose. Marvellous */
362 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
363 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
365 /* warn on C51 regs that haven't been verified accessible in tracing */
366 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
367 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
368 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
371 if (reg >= (8*1024*1024)) {
372 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
380 valid_idx_port(struct nvbios *bios, uint16_t port)
382 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
383 struct drm_device *dev = bios->dev;
386 * If adding more ports here, the read/write functions below will need
387 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
388 * used for the port in question
390 if (dev_priv->card_type < NV_50) {
391 if (port == NV_CIO_CRX__COLOR)
393 if (port == NV_VIO_SRX)
396 if (port == NV_CIO_CRX__COLOR)
400 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
407 valid_port(struct nvbios *bios, uint16_t port)
409 struct drm_device *dev = bios->dev;
412 * If adding more ports here, the read/write functions below will need
413 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
414 * used for the port in question
416 if (port == NV_VIO_VSE2)
419 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
425 bios_rd32(struct nvbios *bios, uint32_t reg)
429 reg = munge_reg(bios, reg);
430 if (!valid_reg(bios, reg))
434 * C51 sometimes uses regs with bit0 set in the address. For these
435 * cases there should exist a translation in a BIOS table to an IO
436 * port address which the BIOS uses for accessing the reg
438 * These only seem to appear for the power control regs to a flat panel,
439 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
440 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
441 * suspend-resume mmio trace from a C51 will be required to see if this
442 * is true for the power microcode in 0x14.., or whether the direct IO
443 * port access method is needed
448 data = nv_rd32(bios->dev, reg);
450 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
456 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
458 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
460 reg = munge_reg(bios, reg);
461 if (!valid_reg(bios, reg))
464 /* see note in bios_rd32 */
468 LOG_OLD_VALUE(bios_rd32(bios, reg));
469 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
471 if (dev_priv->vbios.execute) {
473 nv_wr32(bios->dev, reg, data);
478 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
480 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
481 struct drm_device *dev = bios->dev;
484 if (!valid_idx_port(bios, port))
487 if (dev_priv->card_type < NV_50) {
488 if (port == NV_VIO_SRX)
489 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
490 else /* assume NV_CIO_CRX__COLOR */
491 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
495 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
496 data = (data32 >> ((index & 3) << 3)) & 0xff;
499 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
500 "Head: 0x%02X, Data: 0x%02X\n",
501 port, index, bios->state.crtchead, data);
506 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
508 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
509 struct drm_device *dev = bios->dev;
511 if (!valid_idx_port(bios, port))
515 * The current head is maintained in the nvbios member state.crtchead.
516 * We trap changes to CR44 and update the head variable and hence the
517 * register set written.
518 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
519 * of the write, and to head1 after the write
521 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
522 data != NV_CIO_CRE_44_HEADB)
523 bios->state.crtchead = 0;
525 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
526 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
527 "Head: 0x%02X, Data: 0x%02X\n",
528 port, index, bios->state.crtchead, data);
530 if (bios->execute && dev_priv->card_type < NV_50) {
532 if (port == NV_VIO_SRX)
533 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
534 else /* assume NV_CIO_CRX__COLOR */
535 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
538 uint32_t data32, shift = (index & 3) << 3;
542 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
543 data32 &= ~(0xff << shift);
544 data32 |= (data << shift);
545 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
548 if (port == NV_CIO_CRX__COLOR &&
549 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
550 bios->state.crtchead = 1;
554 bios_port_rd(struct nvbios *bios, uint16_t port)
556 uint8_t data, head = bios->state.crtchead;
558 if (!valid_port(bios, port))
561 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
563 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
570 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
572 int head = bios->state.crtchead;
574 if (!valid_port(bios, port))
577 LOG_OLD_VALUE(bios_port_rd(bios, port));
578 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
585 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
589 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
592 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
593 * for the CRTC index; 1 byte for the mask to apply to the value
594 * retrieved from the CRTC; 1 byte for the shift right to apply to the
595 * masked CRTC value; 2 bytes for the offset to the flag array, to
596 * which the shifted value is added; 1 byte for the mask applied to the
597 * value read from the flag array; and 1 byte for the value to compare
598 * against the masked byte from the flag table.
601 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
602 uint16_t crtcport = ROM16(bios->data[condptr]);
603 uint8_t crtcindex = bios->data[condptr + 2];
604 uint8_t mask = bios->data[condptr + 3];
605 uint8_t shift = bios->data[condptr + 4];
606 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
607 uint8_t flagarraymask = bios->data[condptr + 7];
608 uint8_t cmpval = bios->data[condptr + 8];
611 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
612 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
614 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
616 data = bios_idxprt_rd(bios, crtcport, crtcindex);
618 data = bios->data[flagarray + ((data & mask) >> shift)];
619 data &= flagarraymask;
621 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
622 offset, data, cmpval);
624 return (data == cmpval);
628 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
631 * The condition table entry has 4 bytes for the address of the
632 * register to check, 4 bytes for a mask to apply to the register and
633 * 4 for a test comparison value
636 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
637 uint32_t reg = ROM32(bios->data[condptr]);
638 uint32_t mask = ROM32(bios->data[condptr + 4]);
639 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
642 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
643 offset, cond, reg, mask);
645 data = bios_rd32(bios, reg) & mask;
647 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
648 offset, data, cmpval);
650 return (data == cmpval);
654 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
657 * The IO condition entry has 2 bytes for the IO port address; 1 byte
658 * for the index to write to io_port; 1 byte for the mask to apply to
659 * the byte read from io_port+1; and 1 byte for the value to compare
660 * against the masked byte.
663 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
664 uint16_t io_port = ROM16(bios->data[condptr]);
665 uint8_t port_index = bios->data[condptr + 2];
666 uint8_t mask = bios->data[condptr + 3];
667 uint8_t cmpval = bios->data[condptr + 4];
669 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
671 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
672 offset, data, cmpval);
674 return (data == cmpval);
678 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
680 struct drm_nouveau_private *dev_priv = dev->dev_private;
681 struct nouveau_pll_vals pll;
682 struct pll_lims pll_limits;
683 u32 ctrl, mask, coef;
686 ret = get_pll_limits(dev, reg, &pll_limits);
690 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
694 coef = pll.N1 << 8 | pll.M1;
695 ctrl = pll.log2P << 16;
697 if (reg == 0x004008) {
699 ctrl |= (pll_limits.log2p_bias << 19);
700 ctrl |= (pll.log2P << 22);
703 if (!dev_priv->vbios.execute)
706 nv_mask(dev, reg + 0, mask, ctrl);
707 nv_wr32(dev, reg + 4, coef);
712 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
714 struct drm_device *dev = bios->dev;
715 struct drm_nouveau_private *dev_priv = dev->dev_private;
717 struct pll_lims pll_lim;
718 struct nouveau_pll_vals pllvals;
721 if (dev_priv->card_type >= NV_50)
722 return nv50_pll_set(dev, reg, clk);
724 /* high regs (such as in the mac g5 table) are not -= 4 */
725 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
729 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
735 nouveau_hw_setpll(dev, reg, &pllvals);
741 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
743 struct drm_nouveau_private *dev_priv = dev->dev_private;
744 struct nvbios *bios = &dev_priv->vbios;
747 * For the results of this function to be correct, CR44 must have been
748 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
749 * and the DCB table parsed, before the script calling the function is
750 * run. run_digital_op_script is example of how to do such setup
753 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
755 if (dcb_entry > bios->dcb.entries) {
756 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
757 "(%02X)\n", dcb_entry);
758 dcb_entry = 0x7f; /* unused / invalid marker */
764 static struct nouveau_i2c_chan *
765 init_i2c_device_find(struct drm_device *dev, int i2c_index)
767 if (i2c_index == 0xff) {
768 struct drm_nouveau_private *dev_priv = dev->dev_private;
769 struct dcb_table *dcb = &dev_priv->vbios.dcb;
770 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
771 int idx = dcb_entry_idx_from_crtchead(dev);
773 i2c_index = NV_I2C_DEFAULT(0);
774 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
775 i2c_index = NV_I2C_DEFAULT(1);
778 return nouveau_i2c_find(dev, i2c_index);
782 get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
785 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
786 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
787 * CR58 for CR57 = 0 to index a table of offsets to the basic
789 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
790 * CR58 for CR57 = 0 to index a table of offsets to the basic
791 * 0x6808b0 address, and then flip the offset by 8.
794 struct drm_nouveau_private *dev_priv = dev->dev_private;
795 struct nvbios *bios = &dev_priv->vbios;
796 const int pramdac_offset[13] = {
797 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
798 const uint32_t pramdac_table[4] = {
799 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
802 int dcb_entry, dacoffset;
804 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
805 dcb_entry = dcb_entry_idx_from_crtchead(dev);
806 if (dcb_entry == 0x7f)
808 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
811 return 0x6808b0 + dacoffset;
813 if (mlv >= ARRAY_SIZE(pramdac_table)) {
814 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
818 return pramdac_table[mlv];
823 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
824 struct init_exec *iexec)
827 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
829 * offset (8 bit): opcode
830 * offset + 1 (16 bit): CRTC port
831 * offset + 3 (8 bit): CRTC index
832 * offset + 4 (8 bit): mask
833 * offset + 5 (8 bit): shift
834 * offset + 6 (8 bit): count
835 * offset + 7 (32 bit): register
836 * offset + 11 (32 bit): configuration 1
839 * Starting at offset + 11 there are "count" 32 bit values.
840 * To find out which value to use read index "CRTC index" on "CRTC
841 * port", AND this value with "mask" and then bit shift right "shift"
842 * bits. Read the appropriate value using this index and write to
846 uint16_t crtcport = ROM16(bios->data[offset + 1]);
847 uint8_t crtcindex = bios->data[offset + 3];
848 uint8_t mask = bios->data[offset + 4];
849 uint8_t shift = bios->data[offset + 5];
850 uint8_t count = bios->data[offset + 6];
851 uint32_t reg = ROM32(bios->data[offset + 7]);
854 int len = 11 + count * 4;
859 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
860 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
861 offset, crtcport, crtcindex, mask, shift, count, reg);
863 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
864 if (config > count) {
866 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
867 offset, config, count);
871 configval = ROM32(bios->data[offset + 11 + config * 4]);
873 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
875 bios_wr32(bios, reg, configval);
881 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
884 * INIT_REPEAT opcode: 0x33 ('3')
886 * offset (8 bit): opcode
887 * offset + 1 (8 bit): count
889 * Execute script following this opcode up to INIT_REPEAT_END
893 uint8_t count = bios->data[offset + 1];
896 /* no iexec->execute check by design */
898 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
901 iexec->repeat = true;
904 * count - 1, as the script block will execute once when we leave this
905 * opcode -- this is compatible with bios behaviour as:
906 * a) the block is always executed at least once, even if count == 0
907 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
910 for (i = 0; i < count - 1; i++)
911 parse_init_table(bios, offset + 2, iexec);
913 iexec->repeat = false;
919 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
920 struct init_exec *iexec)
923 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
925 * offset (8 bit): opcode
926 * offset + 1 (16 bit): CRTC port
927 * offset + 3 (8 bit): CRTC index
928 * offset + 4 (8 bit): mask
929 * offset + 5 (8 bit): shift
930 * offset + 6 (8 bit): IO flag condition index
931 * offset + 7 (8 bit): count
932 * offset + 8 (32 bit): register
933 * offset + 12 (16 bit): frequency 1
936 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
937 * Set PLL register "register" to coefficients for frequency n,
938 * selected by reading index "CRTC index" of "CRTC port" ANDed with
939 * "mask" and shifted right by "shift".
941 * If "IO flag condition index" > 0, and condition met, double
942 * frequency before setting it.
945 uint16_t crtcport = ROM16(bios->data[offset + 1]);
946 uint8_t crtcindex = bios->data[offset + 3];
947 uint8_t mask = bios->data[offset + 4];
948 uint8_t shift = bios->data[offset + 5];
949 int8_t io_flag_condition_idx = bios->data[offset + 6];
950 uint8_t count = bios->data[offset + 7];
951 uint32_t reg = ROM32(bios->data[offset + 8]);
954 int len = 12 + count * 2;
959 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
960 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
961 "Count: 0x%02X, Reg: 0x%08X\n",
962 offset, crtcport, crtcindex, mask, shift,
963 io_flag_condition_idx, count, reg);
965 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
966 if (config > count) {
968 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
969 offset, config, count);
973 freq = ROM16(bios->data[offset + 12 + config * 2]);
975 if (io_flag_condition_idx > 0) {
976 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
977 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
978 "frequency doubled\n", offset);
981 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
982 "frequency unchanged\n", offset);
985 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
986 offset, reg, config, freq);
988 setPLL(bios, reg, freq * 10);
994 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
997 * INIT_END_REPEAT opcode: 0x36 ('6')
999 * offset (8 bit): opcode
1001 * Marks the end of the block for INIT_REPEAT to repeat
1004 /* no iexec->execute check by design */
1007 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1008 * we're not in repeat mode
1017 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1020 * INIT_COPY opcode: 0x37 ('7')
1022 * offset (8 bit): opcode
1023 * offset + 1 (32 bit): register
1024 * offset + 5 (8 bit): shift
1025 * offset + 6 (8 bit): srcmask
1026 * offset + 7 (16 bit): CRTC port
1027 * offset + 9 (8 bit): CRTC index
1028 * offset + 10 (8 bit): mask
1030 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1031 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1035 uint32_t reg = ROM32(bios->data[offset + 1]);
1036 uint8_t shift = bios->data[offset + 5];
1037 uint8_t srcmask = bios->data[offset + 6];
1038 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1039 uint8_t crtcindex = bios->data[offset + 9];
1040 uint8_t mask = bios->data[offset + 10];
1044 if (!iexec->execute)
1047 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1048 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1049 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1051 data = bios_rd32(bios, reg);
1056 data <<= (0x100 - shift);
1060 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1061 crtcdata |= (uint8_t)data;
1062 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1068 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1071 * INIT_NOT opcode: 0x38 ('8')
1073 * offset (8 bit): opcode
1075 * Invert the current execute / no-execute condition (i.e. "else")
1078 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1080 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1082 iexec->execute = !iexec->execute;
1087 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1088 struct init_exec *iexec)
1091 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1093 * offset (8 bit): opcode
1094 * offset + 1 (8 bit): condition number
1096 * Check condition "condition number" in the IO flag condition table.
1097 * If condition not met skip subsequent opcodes until condition is
1098 * inverted (INIT_NOT), or we hit INIT_RESUME
1101 uint8_t cond = bios->data[offset + 1];
1103 if (!iexec->execute)
1106 if (io_flag_condition_met(bios, offset, cond))
1107 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1109 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1110 iexec->execute = false;
1117 init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1120 * INIT_DP_CONDITION opcode: 0x3A ('')
1122 * offset (8 bit): opcode
1123 * offset + 1 (8 bit): "sub" opcode
1124 * offset + 2 (8 bit): unknown
1128 struct dcb_entry *dcb = bios->display.output;
1129 struct drm_device *dev = bios->dev;
1130 uint8_t cond = bios->data[offset + 1];
1131 uint8_t *table, *entry;
1133 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1135 if (!iexec->execute)
1138 table = nouveau_dp_bios_data(dev, dcb, &entry);
1144 entry = dcb_conn(dev, dcb->connector);
1145 if (!entry || entry[0] != DCB_CONNECTOR_eDP)
1146 iexec->execute = false;
1150 if ((table[0] < 0x40 && !(entry[5] & cond)) ||
1151 (table[0] == 0x40 && !(entry[4] & cond)))
1152 iexec->execute = false;
1156 struct nouveau_i2c_chan *auxch;
1159 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1161 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1165 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1167 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1172 iexec->execute = false;
1176 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1181 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1183 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1189 init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1192 * INIT_3B opcode: 0x3B ('')
1194 * offset (8 bit): opcode
1195 * offset + 1 (8 bit): crtc index
1199 uint8_t or = ffs(bios->display.output->or) - 1;
1200 uint8_t index = bios->data[offset + 1];
1203 if (!iexec->execute)
1206 data = bios_idxprt_rd(bios, 0x3d4, index);
1207 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1212 init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1215 * INIT_3C opcode: 0x3C ('')
1217 * offset (8 bit): opcode
1218 * offset + 1 (8 bit): crtc index
1222 uint8_t or = ffs(bios->display.output->or) - 1;
1223 uint8_t index = bios->data[offset + 1];
1226 if (!iexec->execute)
1229 data = bios_idxprt_rd(bios, 0x3d4, index);
1230 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1235 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1236 struct init_exec *iexec)
1239 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1241 * offset (8 bit): opcode
1242 * offset + 1 (32 bit): control register
1243 * offset + 5 (32 bit): data register
1244 * offset + 9 (32 bit): mask
1245 * offset + 13 (32 bit): data
1246 * offset + 17 (8 bit): count
1247 * offset + 18 (8 bit): address 1
1248 * offset + 19 (8 bit): data 1
1251 * For each of "count" address and data pairs, write "data n" to
1252 * "data register", read the current value of "control register",
1253 * and write it back once ANDed with "mask", ORed with "data",
1254 * and ORed with "address n"
1257 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1258 uint32_t datareg = ROM32(bios->data[offset + 5]);
1259 uint32_t mask = ROM32(bios->data[offset + 9]);
1260 uint32_t data = ROM32(bios->data[offset + 13]);
1261 uint8_t count = bios->data[offset + 17];
1262 int len = 18 + count * 2;
1266 if (!iexec->execute)
1269 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1270 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1271 offset, controlreg, datareg, mask, data, count);
1273 for (i = 0; i < count; i++) {
1274 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1275 uint8_t instdata = bios->data[offset + 19 + i * 2];
1277 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1278 offset, instaddress, instdata);
1280 bios_wr32(bios, datareg, instdata);
1281 value = bios_rd32(bios, controlreg) & mask;
1283 value |= instaddress;
1284 bios_wr32(bios, controlreg, value);
1291 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1292 struct init_exec *iexec)
1295 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1297 * offset (8 bit): opcode
1298 * offset + 1 (16 bit): CRTC port
1299 * offset + 3 (8 bit): CRTC index
1300 * offset + 4 (8 bit): mask
1301 * offset + 5 (8 bit): shift
1302 * offset + 6 (8 bit): count
1303 * offset + 7 (32 bit): register
1304 * offset + 11 (32 bit): frequency 1
1307 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1308 * Set PLL register "register" to coefficients for frequency n,
1309 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1310 * "mask" and shifted right by "shift".
1313 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1314 uint8_t crtcindex = bios->data[offset + 3];
1315 uint8_t mask = bios->data[offset + 4];
1316 uint8_t shift = bios->data[offset + 5];
1317 uint8_t count = bios->data[offset + 6];
1318 uint32_t reg = ROM32(bios->data[offset + 7]);
1319 int len = 11 + count * 4;
1323 if (!iexec->execute)
1326 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1327 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1328 offset, crtcport, crtcindex, mask, shift, count, reg);
1333 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1334 if (config > count) {
1336 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1337 offset, config, count);
1341 freq = ROM32(bios->data[offset + 11 + config * 4]);
1343 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1344 offset, reg, config, freq);
1346 setPLL(bios, reg, freq);
1352 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1355 * INIT_PLL2 opcode: 0x4B ('K')
1357 * offset (8 bit): opcode
1358 * offset + 1 (32 bit): register
1359 * offset + 5 (32 bit): freq
1361 * Set PLL register "register" to coefficients for frequency "freq"
1364 uint32_t reg = ROM32(bios->data[offset + 1]);
1365 uint32_t freq = ROM32(bios->data[offset + 5]);
1367 if (!iexec->execute)
1370 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1373 setPLL(bios, reg, freq);
1378 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1381 * INIT_I2C_BYTE opcode: 0x4C ('L')
1383 * offset (8 bit): opcode
1384 * offset + 1 (8 bit): DCB I2C table entry index
1385 * offset + 2 (8 bit): I2C slave address
1386 * offset + 3 (8 bit): count
1387 * offset + 4 (8 bit): I2C register 1
1388 * offset + 5 (8 bit): mask 1
1389 * offset + 6 (8 bit): data 1
1392 * For each of "count" registers given by "I2C register n" on the device
1393 * addressed by "I2C slave address" on the I2C bus given by
1394 * "DCB I2C table entry index", read the register, AND the result with
1395 * "mask n" and OR it with "data n" before writing it back to the device
1398 struct drm_device *dev = bios->dev;
1399 uint8_t i2c_index = bios->data[offset + 1];
1400 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1401 uint8_t count = bios->data[offset + 3];
1402 struct nouveau_i2c_chan *chan;
1403 int len = 4 + count * 3;
1406 if (!iexec->execute)
1409 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1411 offset, i2c_index, i2c_address, count);
1413 chan = init_i2c_device_find(dev, i2c_index);
1415 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1419 for (i = 0; i < count; i++) {
1420 uint8_t reg = bios->data[offset + 4 + i * 3];
1421 uint8_t mask = bios->data[offset + 5 + i * 3];
1422 uint8_t data = bios->data[offset + 6 + i * 3];
1423 union i2c_smbus_data val;
1425 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1426 I2C_SMBUS_READ, reg,
1427 I2C_SMBUS_BYTE_DATA, &val);
1429 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1433 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1434 "Mask: 0x%02X, Data: 0x%02X\n",
1435 offset, reg, val.byte, mask, data);
1442 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1443 I2C_SMBUS_WRITE, reg,
1444 I2C_SMBUS_BYTE_DATA, &val);
1446 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1455 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1458 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1460 * offset (8 bit): opcode
1461 * offset + 1 (8 bit): DCB I2C table entry index
1462 * offset + 2 (8 bit): I2C slave address
1463 * offset + 3 (8 bit): count
1464 * offset + 4 (8 bit): I2C register 1
1465 * offset + 5 (8 bit): data 1
1468 * For each of "count" registers given by "I2C register n" on the device
1469 * addressed by "I2C slave address" on the I2C bus given by
1470 * "DCB I2C table entry index", set the register to "data n"
1473 struct drm_device *dev = bios->dev;
1474 uint8_t i2c_index = bios->data[offset + 1];
1475 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1476 uint8_t count = bios->data[offset + 3];
1477 struct nouveau_i2c_chan *chan;
1478 int len = 4 + count * 2;
1481 if (!iexec->execute)
1484 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1486 offset, i2c_index, i2c_address, count);
1488 chan = init_i2c_device_find(dev, i2c_index);
1490 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1494 for (i = 0; i < count; i++) {
1495 uint8_t reg = bios->data[offset + 4 + i * 2];
1496 union i2c_smbus_data val;
1498 val.byte = bios->data[offset + 5 + i * 2];
1500 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1501 offset, reg, val.byte);
1506 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1507 I2C_SMBUS_WRITE, reg,
1508 I2C_SMBUS_BYTE_DATA, &val);
1510 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1519 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1522 * INIT_ZM_I2C opcode: 0x4E ('N')
1524 * offset (8 bit): opcode
1525 * offset + 1 (8 bit): DCB I2C table entry index
1526 * offset + 2 (8 bit): I2C slave address
1527 * offset + 3 (8 bit): count
1528 * offset + 4 (8 bit): data 1
1531 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1532 * address" on the I2C bus given by "DCB I2C table entry index"
1535 struct drm_device *dev = bios->dev;
1536 uint8_t i2c_index = bios->data[offset + 1];
1537 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1538 uint8_t count = bios->data[offset + 3];
1539 int len = 4 + count;
1540 struct nouveau_i2c_chan *chan;
1545 if (!iexec->execute)
1548 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1550 offset, i2c_index, i2c_address, count);
1552 chan = init_i2c_device_find(dev, i2c_index);
1554 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1558 for (i = 0; i < count; i++) {
1559 data[i] = bios->data[offset + 4 + i];
1561 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1564 if (bios->execute) {
1565 msg.addr = i2c_address;
1569 ret = i2c_transfer(&chan->adapter, &msg, 1);
1571 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1580 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1583 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1585 * offset (8 bit): opcode
1586 * offset + 1 (8 bit): magic lookup value
1587 * offset + 2 (8 bit): TMDS address
1588 * offset + 3 (8 bit): mask
1589 * offset + 4 (8 bit): data
1591 * Read the data reg for TMDS address "TMDS address", AND it with mask
1592 * and OR it with data, then write it back
1593 * "magic lookup value" determines which TMDS base address register is
1594 * used -- see get_tmds_index_reg()
1597 struct drm_device *dev = bios->dev;
1598 uint8_t mlv = bios->data[offset + 1];
1599 uint32_t tmdsaddr = bios->data[offset + 2];
1600 uint8_t mask = bios->data[offset + 3];
1601 uint8_t data = bios->data[offset + 4];
1602 uint32_t reg, value;
1604 if (!iexec->execute)
1607 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1608 "Mask: 0x%02X, Data: 0x%02X\n",
1609 offset, mlv, tmdsaddr, mask, data);
1611 reg = get_tmds_index_reg(bios->dev, mlv);
1613 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1617 bios_wr32(bios, reg,
1618 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1619 value = (bios_rd32(bios, reg + 4) & mask) | data;
1620 bios_wr32(bios, reg + 4, value);
1621 bios_wr32(bios, reg, tmdsaddr);
1627 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1628 struct init_exec *iexec)
1631 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1633 * offset (8 bit): opcode
1634 * offset + 1 (8 bit): magic lookup value
1635 * offset + 2 (8 bit): count
1636 * offset + 3 (8 bit): addr 1
1637 * offset + 4 (8 bit): data 1
1640 * For each of "count" TMDS address and data pairs write "data n" to
1641 * "addr n". "magic lookup value" determines which TMDS base address
1642 * register is used -- see get_tmds_index_reg()
1645 struct drm_device *dev = bios->dev;
1646 uint8_t mlv = bios->data[offset + 1];
1647 uint8_t count = bios->data[offset + 2];
1648 int len = 3 + count * 2;
1652 if (!iexec->execute)
1655 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1656 offset, mlv, count);
1658 reg = get_tmds_index_reg(bios->dev, mlv);
1660 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1664 for (i = 0; i < count; i++) {
1665 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1666 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1668 bios_wr32(bios, reg + 4, tmdsdata);
1669 bios_wr32(bios, reg, tmdsaddr);
1676 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1677 struct init_exec *iexec)
1680 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1682 * offset (8 bit): opcode
1683 * offset + 1 (8 bit): CRTC index1
1684 * offset + 2 (8 bit): CRTC index2
1685 * offset + 3 (8 bit): baseaddr
1686 * offset + 4 (8 bit): count
1687 * offset + 5 (8 bit): data 1
1690 * For each of "count" address and data pairs, write "baseaddr + n" to
1691 * "CRTC index1" and "data n" to "CRTC index2"
1692 * Once complete, restore initial value read from "CRTC index1"
1694 uint8_t crtcindex1 = bios->data[offset + 1];
1695 uint8_t crtcindex2 = bios->data[offset + 2];
1696 uint8_t baseaddr = bios->data[offset + 3];
1697 uint8_t count = bios->data[offset + 4];
1698 int len = 5 + count;
1699 uint8_t oldaddr, data;
1702 if (!iexec->execute)
1705 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1706 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1707 offset, crtcindex1, crtcindex2, baseaddr, count);
1709 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1711 for (i = 0; i < count; i++) {
1712 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1714 data = bios->data[offset + 5 + i];
1715 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1718 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1724 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1727 * INIT_CR opcode: 0x52 ('R')
1729 * offset (8 bit): opcode
1730 * offset + 1 (8 bit): CRTC index
1731 * offset + 2 (8 bit): mask
1732 * offset + 3 (8 bit): data
1734 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1735 * data back to "CRTC index"
1738 uint8_t crtcindex = bios->data[offset + 1];
1739 uint8_t mask = bios->data[offset + 2];
1740 uint8_t data = bios->data[offset + 3];
1743 if (!iexec->execute)
1746 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1747 offset, crtcindex, mask, data);
1749 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1751 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1757 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1760 * INIT_ZM_CR opcode: 0x53 ('S')
1762 * offset (8 bit): opcode
1763 * offset + 1 (8 bit): CRTC index
1764 * offset + 2 (8 bit): value
1766 * Assign "value" to CRTC register with index "CRTC index".
1769 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1770 uint8_t data = bios->data[offset + 2];
1772 if (!iexec->execute)
1775 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1781 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1784 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1786 * offset (8 bit): opcode
1787 * offset + 1 (8 bit): count
1788 * offset + 2 (8 bit): CRTC index 1
1789 * offset + 3 (8 bit): value 1
1792 * For "count", assign "value n" to CRTC register with index
1796 uint8_t count = bios->data[offset + 1];
1797 int len = 2 + count * 2;
1800 if (!iexec->execute)
1803 for (i = 0; i < count; i++)
1804 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1810 init_condition_time(struct nvbios *bios, uint16_t offset,
1811 struct init_exec *iexec)
1814 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1816 * offset (8 bit): opcode
1817 * offset + 1 (8 bit): condition number
1818 * offset + 2 (8 bit): retries / 50
1820 * Check condition "condition number" in the condition table.
1821 * Bios code then sleeps for 2ms if the condition is not met, and
1822 * repeats up to "retries" times, but on one C51 this has proved
1823 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1824 * this, and bail after "retries" times, or 2s, whichever is less.
1825 * If still not met after retries, clear execution flag for this table.
1828 uint8_t cond = bios->data[offset + 1];
1829 uint16_t retries = bios->data[offset + 2] * 50;
1832 if (!iexec->execute)
1838 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1839 offset, cond, retries);
1841 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1844 for (cnt = 0; cnt < retries; cnt++) {
1845 if (bios_condition_met(bios, offset, cond)) {
1846 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1850 BIOSLOG(bios, "0x%04X: "
1851 "Condition not met, sleeping for 20ms\n",
1857 if (!bios_condition_met(bios, offset, cond)) {
1859 "0x%04X: Condition still not met after %dms, "
1860 "skipping following opcodes\n", offset, 20 * retries);
1861 iexec->execute = false;
1868 init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1871 * INIT_LTIME opcode: 0x57 ('V')
1873 * offset (8 bit): opcode
1874 * offset + 1 (16 bit): time
1876 * Sleep for "time" milliseconds.
1879 unsigned time = ROM16(bios->data[offset + 1]);
1881 if (!iexec->execute)
1884 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1893 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1894 struct init_exec *iexec)
1897 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1899 * offset (8 bit): opcode
1900 * offset + 1 (32 bit): base register
1901 * offset + 5 (8 bit): count
1902 * offset + 6 (32 bit): value 1
1905 * Starting at offset + 6 there are "count" 32 bit values.
1906 * For "count" iterations set "base register" + 4 * current_iteration
1907 * to "value current_iteration"
1910 uint32_t basereg = ROM32(bios->data[offset + 1]);
1911 uint32_t count = bios->data[offset + 5];
1912 int len = 6 + count * 4;
1915 if (!iexec->execute)
1918 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1919 offset, basereg, count);
1921 for (i = 0; i < count; i++) {
1922 uint32_t reg = basereg + i * 4;
1923 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1925 bios_wr32(bios, reg, data);
1932 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1935 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1937 * offset (8 bit): opcode
1938 * offset + 1 (16 bit): subroutine offset (in bios)
1940 * Calls a subroutine that will execute commands until INIT_DONE
1944 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1946 if (!iexec->execute)
1949 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1950 offset, sub_offset);
1952 parse_init_table(bios, sub_offset, iexec);
1954 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1960 init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1963 * INIT_JUMP opcode: 0x5C ('\')
1965 * offset (8 bit): opcode
1966 * offset + 1 (16 bit): offset (in bios)
1968 * Continue execution of init table from 'offset'
1971 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1973 if (!iexec->execute)
1976 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1977 return jmp_offset - offset;
1981 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1984 * INIT_I2C_IF opcode: 0x5E ('^')
1986 * offset (8 bit): opcode
1987 * offset + 1 (8 bit): DCB I2C table entry index
1988 * offset + 2 (8 bit): I2C slave address
1989 * offset + 3 (8 bit): I2C register
1990 * offset + 4 (8 bit): mask
1991 * offset + 5 (8 bit): data
1993 * Read the register given by "I2C register" on the device addressed
1994 * by "I2C slave address" on the I2C bus given by "DCB I2C table
1995 * entry index". Compare the result AND "mask" to "data".
1996 * If they're not equal, skip subsequent opcodes until condition is
1997 * inverted (INIT_NOT), or we hit INIT_RESUME
2000 uint8_t i2c_index = bios->data[offset + 1];
2001 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2002 uint8_t reg = bios->data[offset + 3];
2003 uint8_t mask = bios->data[offset + 4];
2004 uint8_t data = bios->data[offset + 5];
2005 struct nouveau_i2c_chan *chan;
2006 union i2c_smbus_data val;
2009 /* no execute check by design */
2011 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2012 offset, i2c_index, i2c_address);
2014 chan = init_i2c_device_find(bios->dev, i2c_index);
2018 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2019 I2C_SMBUS_READ, reg,
2020 I2C_SMBUS_BYTE_DATA, &val);
2022 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2023 "Mask: 0x%02X, Data: 0x%02X\n",
2024 offset, reg, mask, data);
2029 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2030 "Mask: 0x%02X, Data: 0x%02X\n",
2031 offset, reg, val.byte, mask, data);
2033 iexec->execute = ((val.byte & mask) == data);
2039 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2042 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2044 * offset (8 bit): opcode
2045 * offset + 1 (32 bit): src reg
2046 * offset + 5 (8 bit): shift
2047 * offset + 6 (32 bit): src mask
2048 * offset + 10 (32 bit): xor
2049 * offset + 14 (32 bit): dst reg
2050 * offset + 18 (32 bit): dst mask
2052 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2053 * "src mask", then XOR with "xor". Write this OR'd with
2054 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2057 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2058 uint8_t shift = bios->data[offset + 5];
2059 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2060 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2061 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2062 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2063 uint32_t srcvalue, dstvalue;
2065 if (!iexec->execute)
2068 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2069 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2070 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2072 srcvalue = bios_rd32(bios, srcreg);
2077 srcvalue <<= (0x100 - shift);
2079 srcvalue = (srcvalue & srcmask) ^ xor;
2081 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2083 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2089 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2092 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2094 * offset (8 bit): opcode
2095 * offset + 1 (16 bit): CRTC port
2096 * offset + 3 (8 bit): CRTC index
2097 * offset + 4 (8 bit): data
2099 * Write "data" to index "CRTC index" of "CRTC port"
2101 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2102 uint8_t crtcindex = bios->data[offset + 3];
2103 uint8_t data = bios->data[offset + 4];
2105 if (!iexec->execute)
2108 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2114 bios_md32(struct nvbios *bios, uint32_t reg,
2115 uint32_t mask, uint32_t val)
2117 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2121 peek_fb(struct drm_device *dev, struct io_mapping *fb,
2126 if (off < pci_resource_len(dev->pdev, 1)) {
2127 uint8_t __iomem *p =
2128 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2130 val = ioread32(p + (off & ~PAGE_MASK));
2132 io_mapping_unmap_atomic(p);
2139 poke_fb(struct drm_device *dev, struct io_mapping *fb,
2140 uint32_t off, uint32_t val)
2142 if (off < pci_resource_len(dev->pdev, 1)) {
2143 uint8_t __iomem *p =
2144 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2146 iowrite32(val, p + (off & ~PAGE_MASK));
2149 io_mapping_unmap_atomic(p);
2154 read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2155 uint32_t off, uint32_t val)
2157 poke_fb(dev, fb, off, val);
2158 return val == peek_fb(dev, fb, off);
2162 nv04_init_compute_mem(struct nvbios *bios)
2164 struct drm_device *dev = bios->dev;
2165 uint32_t patt = 0xdeadbeef;
2166 struct io_mapping *fb;
2169 /* Map the framebuffer aperture */
2170 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2171 pci_resource_len(dev->pdev, 1));
2175 /* Sequencer and refresh off */
2176 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2177 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2179 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2180 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2181 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2182 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2184 for (i = 0; i < 4; i++)
2185 poke_fb(dev, fb, 4 * i, patt);
2187 poke_fb(dev, fb, 0x400000, patt + 1);
2189 if (peek_fb(dev, fb, 0) == patt + 1) {
2190 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2191 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2192 bios_md32(bios, NV04_PFB_DEBUG_0,
2193 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2195 for (i = 0; i < 4; i++)
2196 poke_fb(dev, fb, 4 * i, patt);
2198 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2199 bios_md32(bios, NV04_PFB_BOOT_0,
2200 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2201 NV04_PFB_BOOT_0_RAM_AMOUNT,
2202 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2204 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2205 (patt & 0xffff0000)) {
2206 bios_md32(bios, NV04_PFB_BOOT_0,
2207 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2208 NV04_PFB_BOOT_0_RAM_AMOUNT,
2209 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2211 } else if (peek_fb(dev, fb, 0) != patt) {
2212 if (read_back_fb(dev, fb, 0x800000, patt))
2213 bios_md32(bios, NV04_PFB_BOOT_0,
2214 NV04_PFB_BOOT_0_RAM_AMOUNT,
2215 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2217 bios_md32(bios, NV04_PFB_BOOT_0,
2218 NV04_PFB_BOOT_0_RAM_AMOUNT,
2219 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2221 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2222 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2224 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2225 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2226 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2230 /* Refresh on, sequencer on */
2231 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2232 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2234 io_mapping_free(fb);
2238 static const uint8_t *
2239 nv05_memory_config(struct nvbios *bios)
2241 /* Defaults for BIOSes lacking a memory config table */
2242 static const uint8_t default_config_tab[][2] = {
2252 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2253 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2255 if (bios->legacy.mem_init_tbl_ptr)
2256 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2258 return default_config_tab[i];
2262 nv05_init_compute_mem(struct nvbios *bios)
2264 struct drm_device *dev = bios->dev;
2265 const uint8_t *ramcfg = nv05_memory_config(bios);
2266 uint32_t patt = 0xdeadbeef;
2267 struct io_mapping *fb;
2270 /* Map the framebuffer aperture */
2271 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2272 pci_resource_len(dev->pdev, 1));
2277 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2279 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2282 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2284 /* If present load the hardcoded scrambling table */
2285 if (bios->legacy.mem_init_tbl_ptr) {
2286 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2287 bios->legacy.mem_init_tbl_ptr + 0x10];
2289 for (i = 0; i < 8; i++)
2290 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2291 ROM32(scramble_tab[i]));
2294 /* Set memory type/width/length defaults depending on the straps */
2295 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2297 if (ramcfg[1] & 0x80)
2298 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2300 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2301 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2303 /* Probe memory bus width */
2304 for (i = 0; i < 4; i++)
2305 poke_fb(dev, fb, 4 * i, patt);
2307 if (peek_fb(dev, fb, 0xc) != patt)
2308 bios_md32(bios, NV04_PFB_BOOT_0,
2309 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2311 /* Probe memory length */
2312 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2314 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2315 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2316 !read_back_fb(dev, fb, 0, ++patt)))
2317 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2318 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2320 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2321 !read_back_fb(dev, fb, 0x800000, ++patt))
2322 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2323 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2325 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2326 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2327 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2331 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2333 io_mapping_free(fb);
2338 nv10_init_compute_mem(struct nvbios *bios)
2340 struct drm_device *dev = bios->dev;
2341 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2342 const int mem_width[] = { 0x10, 0x00, 0x20 };
2343 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2344 uint32_t patt = 0xdeadbeef;
2345 struct io_mapping *fb;
2348 /* Map the framebuffer aperture */
2349 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2350 pci_resource_len(dev->pdev, 1));
2354 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2356 /* Probe memory bus width */
2357 for (i = 0; i < mem_width_count; i++) {
2358 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2360 for (j = 0; j < 4; j++) {
2361 for (k = 0; k < 4; k++)
2362 poke_fb(dev, fb, 0x1c, 0);
2364 poke_fb(dev, fb, 0x1c, patt);
2365 poke_fb(dev, fb, 0x3c, 0);
2367 if (peek_fb(dev, fb, 0x1c) == patt)
2368 goto mem_width_found;
2375 /* Probe amount of installed memory */
2376 for (i = 0; i < 4; i++) {
2377 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2379 poke_fb(dev, fb, off, patt);
2380 poke_fb(dev, fb, 0, 0);
2382 peek_fb(dev, fb, 0);
2383 peek_fb(dev, fb, 0);
2384 peek_fb(dev, fb, 0);
2385 peek_fb(dev, fb, 0);
2387 if (peek_fb(dev, fb, off) == patt)
2391 /* IC missing - disable the upper half memory space. */
2392 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2395 io_mapping_free(fb);
2400 nv20_init_compute_mem(struct nvbios *bios)
2402 struct drm_device *dev = bios->dev;
2403 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2404 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2405 uint32_t amount, off;
2406 struct io_mapping *fb;
2408 /* Map the framebuffer aperture */
2409 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2410 pci_resource_len(dev->pdev, 1));
2414 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2416 /* Allow full addressing */
2417 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2419 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2420 for (off = amount; off > 0x2000000; off -= 0x2000000)
2421 poke_fb(dev, fb, off - 4, off);
2423 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2424 if (amount != peek_fb(dev, fb, amount - 4))
2425 /* IC missing - disable the upper half memory space. */
2426 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2428 io_mapping_free(fb);
2433 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2436 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2438 * offset (8 bit): opcode
2440 * This opcode is meant to set the PFB memory config registers
2441 * appropriately so that we can correctly calculate how much VRAM it
2442 * has (on nv10 and better chipsets the amount of installed VRAM is
2443 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2445 * The implementation of this opcode in general consists of several
2448 * 1) Determination of memory type and density. Only necessary for
2449 * really old chipsets, the memory type reported by the strap bits
2450 * (0x101000) is assumed to be accurate on nv05 and newer.
2452 * 2) Determination of the memory bus width. Usually done by a cunning
2453 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2454 * seeing whether the written values are read back correctly.
2456 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2459 * 3) Determination of how many of the card's RAM pads have ICs
2460 * attached, usually done by a cunning combination of writes to an
2461 * offset slightly less than the maximum memory reported by
2462 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2464 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2465 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2466 * card show nothing being done for this opcode. Why is it still listed
2470 /* no iexec->execute check by design */
2472 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2475 if (dev_priv->chipset >= 0x40 ||
2476 dev_priv->chipset == 0x1a ||
2477 dev_priv->chipset == 0x1f)
2479 else if (dev_priv->chipset >= 0x20 &&
2480 dev_priv->chipset != 0x34)
2481 ret = nv20_init_compute_mem(bios);
2482 else if (dev_priv->chipset >= 0x10)
2483 ret = nv10_init_compute_mem(bios);
2484 else if (dev_priv->chipset >= 0x5)
2485 ret = nv05_init_compute_mem(bios);
2487 ret = nv04_init_compute_mem(bios);
2496 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2499 * INIT_RESET opcode: 0x65 ('e')
2501 * offset (8 bit): opcode
2502 * offset + 1 (32 bit): register
2503 * offset + 5 (32 bit): value1
2504 * offset + 9 (32 bit): value2
2506 * Assign "value1" to "register", then assign "value2" to "register"
2509 uint32_t reg = ROM32(bios->data[offset + 1]);
2510 uint32_t value1 = ROM32(bios->data[offset + 5]);
2511 uint32_t value2 = ROM32(bios->data[offset + 9]);
2512 uint32_t pci_nv_19, pci_nv_20;
2514 /* no iexec->execute check by design */
2516 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2517 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2519 bios_wr32(bios, reg, value1);
2523 bios_wr32(bios, reg, value2);
2524 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2526 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2527 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2528 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2534 init_configure_mem(struct nvbios *bios, uint16_t offset,
2535 struct init_exec *iexec)
2538 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2540 * offset (8 bit): opcode
2542 * Equivalent to INIT_DONE on bios version 3 or greater.
2543 * For early bios versions, sets up the memory registers, using values
2544 * taken from the memory init table
2547 /* no iexec->execute check by design */
2549 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2550 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2553 if (bios->major_version > 2)
2556 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2557 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2559 if (bios->data[meminitoffs] & 1)
2560 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2562 for (reg = ROM32(bios->data[seqtbloffs]);
2564 reg = ROM32(bios->data[seqtbloffs += 4])) {
2568 data = NV04_PFB_PRE_CMD_PRECHARGE;
2571 data = NV04_PFB_PAD_CKE_NORMAL;
2574 data = NV04_PFB_REF_CMD_REFRESH;
2577 data = ROM32(bios->data[meminitdata]);
2579 if (data == 0xffffffff)
2583 bios_wr32(bios, reg, data);
2590 init_configure_clk(struct nvbios *bios, uint16_t offset,
2591 struct init_exec *iexec)
2594 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2596 * offset (8 bit): opcode
2598 * Equivalent to INIT_DONE on bios version 3 or greater.
2599 * For early bios versions, sets up the NVClk and MClk PLLs, using
2600 * values taken from the memory init table
2603 /* no iexec->execute check by design */
2605 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2608 if (bios->major_version > 2)
2611 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2612 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2614 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2615 if (bios->data[meminitoffs] & 1) /* DDR */
2617 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2623 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2624 struct init_exec *iexec)
2627 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2629 * offset (8 bit): opcode
2631 * Equivalent to INIT_DONE on bios version 3 or greater.
2632 * For early bios versions, does early init, loading ram and crystal
2633 * configuration from straps into CR3C
2636 /* no iexec->execute check by design */
2638 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2639 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2641 if (bios->major_version > 2)
2644 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2645 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2651 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2654 * INIT_IO opcode: 0x69 ('i')
2656 * offset (8 bit): opcode
2657 * offset + 1 (16 bit): CRTC port
2658 * offset + 3 (8 bit): mask
2659 * offset + 4 (8 bit): data
2661 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2664 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2665 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2666 uint8_t mask = bios->data[offset + 3];
2667 uint8_t data = bios->data[offset + 4];
2669 if (!iexec->execute)
2672 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2673 offset, crtcport, mask, data);
2676 * I have no idea what this does, but NVIDIA do this magic sequence
2677 * in the places where this INIT_IO happens..
2679 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2682 bios_wr32(bios, 0x614100, (bios_rd32(
2683 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2685 bios_wr32(bios, 0x00e18c, bios_rd32(
2686 bios, 0x00e18c) | 0x00020000);
2688 bios_wr32(bios, 0x614900, (bios_rd32(
2689 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2691 bios_wr32(bios, 0x000200, bios_rd32(
2692 bios, 0x000200) & ~0x40000000);
2696 bios_wr32(bios, 0x00e18c, bios_rd32(
2697 bios, 0x00e18c) & ~0x00020000);
2699 bios_wr32(bios, 0x000200, bios_rd32(
2700 bios, 0x000200) | 0x40000000);
2702 bios_wr32(bios, 0x614100, 0x00800018);
2703 bios_wr32(bios, 0x614900, 0x00800018);
2707 bios_wr32(bios, 0x614100, 0x10000018);
2708 bios_wr32(bios, 0x614900, 0x10000018);
2710 for (i = 0; i < 3; i++)
2711 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2712 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2714 for (i = 0; i < 2; i++)
2715 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2716 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2718 for (i = 0; i < 3; i++)
2719 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2720 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2722 for (i = 0; i < 2; i++)
2723 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2724 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2726 for (i = 0; i < 2; i++)
2727 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2728 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2732 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2738 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2741 * INIT_SUB opcode: 0x6B ('k')
2743 * offset (8 bit): opcode
2744 * offset + 1 (8 bit): script number
2746 * Execute script number "script number", as a subroutine
2749 uint8_t sub = bios->data[offset + 1];
2751 if (!iexec->execute)
2754 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2756 parse_init_table(bios,
2757 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2760 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2766 init_ram_condition(struct nvbios *bios, uint16_t offset,
2767 struct init_exec *iexec)
2770 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2772 * offset (8 bit): opcode
2773 * offset + 1 (8 bit): mask
2774 * offset + 2 (8 bit): cmpval
2776 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2777 * If condition not met skip subsequent opcodes until condition is
2778 * inverted (INIT_NOT), or we hit INIT_RESUME
2781 uint8_t mask = bios->data[offset + 1];
2782 uint8_t cmpval = bios->data[offset + 2];
2785 if (!iexec->execute)
2788 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2790 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2791 offset, data, cmpval);
2794 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2796 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2797 iexec->execute = false;
2804 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2807 * INIT_NV_REG opcode: 0x6E ('n')
2809 * offset (8 bit): opcode
2810 * offset + 1 (32 bit): register
2811 * offset + 5 (32 bit): mask
2812 * offset + 9 (32 bit): data
2814 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2817 uint32_t reg = ROM32(bios->data[offset + 1]);
2818 uint32_t mask = ROM32(bios->data[offset + 5]);
2819 uint32_t data = ROM32(bios->data[offset + 9]);
2821 if (!iexec->execute)
2824 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2825 offset, reg, mask, data);
2827 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2833 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2836 * INIT_MACRO opcode: 0x6F ('o')
2838 * offset (8 bit): opcode
2839 * offset + 1 (8 bit): macro number
2841 * Look up macro index "macro number" in the macro index table.
2842 * The macro index table entry has 1 byte for the index in the macro
2843 * table, and 1 byte for the number of times to repeat the macro.
2844 * The macro table entry has 4 bytes for the register address and
2845 * 4 bytes for the value to write to that register
2848 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2849 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2850 uint8_t macro_tbl_idx = bios->data[tmp];
2851 uint8_t count = bios->data[tmp + 1];
2855 if (!iexec->execute)
2858 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2860 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2862 for (i = 0; i < count; i++) {
2863 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2865 reg = ROM32(bios->data[macroentryptr]);
2866 data = ROM32(bios->data[macroentryptr + 4]);
2868 bios_wr32(bios, reg, data);
2875 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2878 * INIT_DONE opcode: 0x71 ('q')
2880 * offset (8 bit): opcode
2882 * End the current script
2885 /* mild retval abuse to stop parsing this table */
2890 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2893 * INIT_RESUME opcode: 0x72 ('r')
2895 * offset (8 bit): opcode
2897 * End the current execute / no-execute condition
2903 iexec->execute = true;
2904 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2910 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2913 * INIT_TIME opcode: 0x74 ('t')
2915 * offset (8 bit): opcode
2916 * offset + 1 (16 bit): time
2918 * Sleep for "time" microseconds.
2921 unsigned time = ROM16(bios->data[offset + 1]);
2923 if (!iexec->execute)
2926 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2932 mdelay((time + 900) / 1000);
2938 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2941 * INIT_CONDITION opcode: 0x75 ('u')
2943 * offset (8 bit): opcode
2944 * offset + 1 (8 bit): condition number
2946 * Check condition "condition number" in the condition table.
2947 * If condition not met skip subsequent opcodes until condition is
2948 * inverted (INIT_NOT), or we hit INIT_RESUME
2951 uint8_t cond = bios->data[offset + 1];
2953 if (!iexec->execute)
2956 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2958 if (bios_condition_met(bios, offset, cond))
2959 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2961 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2962 iexec->execute = false;
2969 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2972 * INIT_IO_CONDITION opcode: 0x76
2974 * offset (8 bit): opcode
2975 * offset + 1 (8 bit): condition number
2977 * Check condition "condition number" in the io condition table.
2978 * If condition not met skip subsequent opcodes until condition is
2979 * inverted (INIT_NOT), or we hit INIT_RESUME
2982 uint8_t cond = bios->data[offset + 1];
2984 if (!iexec->execute)
2987 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2989 if (io_condition_met(bios, offset, cond))
2990 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2992 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2993 iexec->execute = false;
3000 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3003 * INIT_INDEX_IO opcode: 0x78 ('x')
3005 * offset (8 bit): opcode
3006 * offset + 1 (16 bit): CRTC port
3007 * offset + 3 (8 bit): CRTC index
3008 * offset + 4 (8 bit): mask
3009 * offset + 5 (8 bit): data
3011 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3012 * OR with "data", write-back
3015 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3016 uint8_t crtcindex = bios->data[offset + 3];
3017 uint8_t mask = bios->data[offset + 4];
3018 uint8_t data = bios->data[offset + 5];
3021 if (!iexec->execute)
3024 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3026 offset, crtcport, crtcindex, mask, data);
3028 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3029 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3035 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3038 * INIT_PLL opcode: 0x79 ('y')
3040 * offset (8 bit): opcode
3041 * offset + 1 (32 bit): register
3042 * offset + 5 (16 bit): freq
3044 * Set PLL register "register" to coefficients for frequency (10kHz)
3048 uint32_t reg = ROM32(bios->data[offset + 1]);
3049 uint16_t freq = ROM16(bios->data[offset + 5]);
3051 if (!iexec->execute)
3054 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3056 setPLL(bios, reg, freq * 10);
3062 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3065 * INIT_ZM_REG opcode: 0x7A ('z')
3067 * offset (8 bit): opcode
3068 * offset + 1 (32 bit): register
3069 * offset + 5 (32 bit): value
3071 * Assign "value" to "register"
3074 uint32_t reg = ROM32(bios->data[offset + 1]);
3075 uint32_t value = ROM32(bios->data[offset + 5]);
3077 if (!iexec->execute)
3080 if (reg == 0x000200)
3083 bios_wr32(bios, reg, value);
3089 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3090 struct init_exec *iexec)
3093 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3095 * offset (8 bit): opcode
3096 * offset + 1 (8 bit): PLL type
3097 * offset + 2 (32 bit): frequency 0
3099 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3100 * ram_restrict_table_ptr. The value read from there is used to select
3101 * a frequency from the table starting at 'frequency 0' to be
3102 * programmed into the PLL corresponding to 'type'.
3104 * The PLL limits table on cards using this opcode has a mapping of
3105 * 'type' to the relevant registers.
3108 struct drm_device *dev = bios->dev;
3109 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3110 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3111 uint8_t type = bios->data[offset + 1];
3112 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3113 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
3114 int len = 2 + bios->ram_restrict_group_count * 4;
3117 if (!iexec->execute)
3120 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3121 NV_ERROR(dev, "PLL limits table not version 3.x\n");
3122 return len; /* deliberate, allow default clocks to remain */
3125 entry = pll_limits + pll_limits[1];
3126 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3127 if (entry[0] == type) {
3128 uint32_t reg = ROM32(entry[3]);
3130 BIOSLOG(bios, "0x%04X: "
3131 "Type %02x Reg 0x%08x Freq %dKHz\n",
3132 offset, type, reg, freq);
3134 setPLL(bios, reg, freq);
3139 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
3144 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3147 * INIT_8C opcode: 0x8C ('')
3157 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3160 * INIT_8D opcode: 0x8D ('')
3170 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3173 * INIT_GPIO opcode: 0x8E ('')
3175 * offset (8 bit): opcode
3177 * Loop over all entries in the DCB GPIO table, and initialise
3178 * each GPIO according to various values listed in each entry
3181 if (iexec->execute && bios->execute)
3182 nouveau_gpio_reset(bios->dev);
3188 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3189 struct init_exec *iexec)
3192 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3194 * offset (8 bit): opcode
3195 * offset + 1 (32 bit): reg
3196 * offset + 5 (8 bit): regincrement
3197 * offset + 6 (8 bit): count
3198 * offset + 7 (32 bit): value 1,1
3201 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3202 * ram_restrict_table_ptr. The value read from here is 'n', and
3203 * "value 1,n" gets written to "reg". This repeats "count" times and on
3204 * each iteration 'm', "reg" increases by "regincrement" and
3205 * "value m,n" is used. The extent of n is limited by a number read
3206 * from the 'M' BIT table, herein called "blocklen"
3209 uint32_t reg = ROM32(bios->data[offset + 1]);
3210 uint8_t regincrement = bios->data[offset + 5];
3211 uint8_t count = bios->data[offset + 6];
3212 uint32_t strap_ramcfg, data;
3213 /* previously set by 'M' BIT table */
3214 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3215 int len = 7 + count * blocklen;
3219 /* critical! to know the length of the opcode */;
3222 "0x%04X: Zero block length - has the M table "
3223 "been parsed?\n", offset);
3227 if (!iexec->execute)
3230 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3231 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3233 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3234 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3235 offset, reg, regincrement, count, strap_ramcfg, index);
3237 for (i = 0; i < count; i++) {
3238 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3240 bios_wr32(bios, reg, data);
3242 reg += regincrement;
3249 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3252 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3254 * offset (8 bit): opcode
3255 * offset + 1 (32 bit): src reg
3256 * offset + 5 (32 bit): dst reg
3258 * Put contents of "src reg" into "dst reg"
3261 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3262 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3264 if (!iexec->execute)
3267 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3273 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3274 struct init_exec *iexec)
3277 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3279 * offset (8 bit): opcode
3280 * offset + 1 (32 bit): dst reg
3281 * offset + 5 (8 bit): count
3282 * offset + 6 (32 bit): data 1
3285 * For each of "count" values write "data n" to "dst reg"
3288 uint32_t reg = ROM32(bios->data[offset + 1]);
3289 uint8_t count = bios->data[offset + 5];
3290 int len = 6 + count * 4;
3293 if (!iexec->execute)
3296 for (i = 0; i < count; i++) {
3297 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3298 bios_wr32(bios, reg, data);
3305 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3308 * INIT_RESERVED opcode: 0x92 ('')
3310 * offset (8 bit): opcode
3312 * Seemingly does nothing
3319 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3322 * INIT_96 opcode: 0x96 ('')
3324 * offset (8 bit): opcode
3325 * offset + 1 (32 bit): sreg
3326 * offset + 5 (8 bit): sshift
3327 * offset + 6 (8 bit): smask
3328 * offset + 7 (8 bit): index
3329 * offset + 8 (32 bit): reg
3330 * offset + 12 (32 bit): mask
3331 * offset + 16 (8 bit): shift
3335 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3336 uint32_t reg = ROM32(bios->data[offset + 8]);
3337 uint32_t mask = ROM32(bios->data[offset + 12]);
3340 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3341 if (bios->data[offset + 5] < 0x80)
3342 val >>= bios->data[offset + 5];
3344 val <<= (0x100 - bios->data[offset + 5]);
3345 val &= bios->data[offset + 6];
3347 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3348 val <<= bios->data[offset + 16];
3350 if (!iexec->execute)
3353 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3358 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3361 * INIT_97 opcode: 0x97 ('')
3363 * offset (8 bit): opcode
3364 * offset + 1 (32 bit): register
3365 * offset + 5 (32 bit): mask
3366 * offset + 9 (32 bit): value
3368 * Adds "value" to "register" preserving the fields specified
3372 uint32_t reg = ROM32(bios->data[offset + 1]);
3373 uint32_t mask = ROM32(bios->data[offset + 5]);
3374 uint32_t add = ROM32(bios->data[offset + 9]);
3377 val = bios_rd32(bios, reg);
3378 val = (val & mask) | ((val + add) & ~mask);
3380 if (!iexec->execute)
3383 bios_wr32(bios, reg, val);
3388 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3391 * INIT_AUXCH opcode: 0x98 ('')
3393 * offset (8 bit): opcode
3394 * offset + 1 (32 bit): address
3395 * offset + 5 (8 bit): count
3396 * offset + 6 (8 bit): mask 0
3397 * offset + 7 (8 bit): data 0
3402 struct drm_device *dev = bios->dev;
3403 struct nouveau_i2c_chan *auxch;
3404 uint32_t addr = ROM32(bios->data[offset + 1]);
3405 uint8_t count = bios->data[offset + 5];
3406 int len = 6 + count * 2;
3409 if (!bios->display.output) {
3410 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3414 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3416 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3417 bios->display.output->i2c_index);
3421 if (!iexec->execute)
3425 for (i = 0; i < count; i++, offset += 2) {
3428 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3430 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3434 data &= bios->data[offset + 0];
3435 data |= bios->data[offset + 1];
3437 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3439 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3448 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3451 * INIT_ZM_AUXCH opcode: 0x99 ('')
3453 * offset (8 bit): opcode
3454 * offset + 1 (32 bit): address
3455 * offset + 5 (8 bit): count
3456 * offset + 6 (8 bit): data 0
3461 struct drm_device *dev = bios->dev;
3462 struct nouveau_i2c_chan *auxch;
3463 uint32_t addr = ROM32(bios->data[offset + 1]);
3464 uint8_t count = bios->data[offset + 5];
3465 int len = 6 + count;
3468 if (!bios->display.output) {
3469 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3473 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3475 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3476 bios->display.output->i2c_index);
3480 if (!iexec->execute)
3484 for (i = 0; i < count; i++, offset++) {
3485 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3487 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3496 init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3499 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3501 * offset (8 bit): opcode
3502 * offset + 1 (8 bit): DCB I2C table entry index
3503 * offset + 2 (8 bit): I2C slave address
3504 * offset + 3 (16 bit): I2C register
3505 * offset + 5 (8 bit): mask
3506 * offset + 6 (8 bit): data
3508 * Read the register given by "I2C register" on the device addressed
3509 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3510 * entry index". Compare the result AND "mask" to "data".
3511 * If they're not equal, skip subsequent opcodes until condition is
3512 * inverted (INIT_NOT), or we hit INIT_RESUME
3515 uint8_t i2c_index = bios->data[offset + 1];
3516 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3517 uint8_t reglo = bios->data[offset + 3];
3518 uint8_t reghi = bios->data[offset + 4];
3519 uint8_t mask = bios->data[offset + 5];
3520 uint8_t data = bios->data[offset + 6];
3521 struct nouveau_i2c_chan *chan;
3522 uint8_t buf0[2] = { reghi, reglo };
3524 struct i2c_msg msg[2] = {
3525 { i2c_address, 0, 1, buf0 },
3526 { i2c_address, I2C_M_RD, 1, buf1 },
3530 /* no execute check by design */
3532 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3533 offset, i2c_index, i2c_address);
3535 chan = init_i2c_device_find(bios->dev, i2c_index);
3540 ret = i2c_transfer(&chan->adapter, msg, 2);
3542 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3543 "Mask: 0x%02X, Data: 0x%02X\n",
3544 offset, reghi, reglo, mask, data);
3549 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3550 "Mask: 0x%02X, Data: 0x%02X\n",
3551 offset, reghi, reglo, buf1[0], mask, data);
3553 iexec->execute = ((buf1[0] & mask) == data);
3558 static struct init_tbl_entry itbl_entry[] = {
3559 /* command name , id , length , offset , mult , command handler */
3560 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3561 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3562 { "INIT_REPEAT" , 0x33, init_repeat },
3563 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3564 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3565 { "INIT_COPY" , 0x37, init_copy },
3566 { "INIT_NOT" , 0x38, init_not },
3567 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3568 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3569 { "INIT_OP_3B" , 0x3B, init_op_3b },
3570 { "INIT_OP_3C" , 0x3C, init_op_3c },
3571 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3572 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3573 { "INIT_PLL2" , 0x4B, init_pll2 },
3574 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3575 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3576 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3577 { "INIT_TMDS" , 0x4F, init_tmds },
3578 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3579 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3580 { "INIT_CR" , 0x52, init_cr },
3581 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3582 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3583 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3584 { "INIT_LTIME" , 0x57, init_ltime },
3585 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3586 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3587 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3588 { "INIT_JUMP" , 0x5C, init_jump },
3589 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3590 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3591 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3592 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3593 { "INIT_RESET" , 0x65, init_reset },
3594 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3595 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3596 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3597 { "INIT_IO" , 0x69, init_io },
3598 { "INIT_SUB" , 0x6B, init_sub },
3599 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3600 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3601 { "INIT_MACRO" , 0x6F, init_macro },
3602 { "INIT_DONE" , 0x71, init_done },
3603 { "INIT_RESUME" , 0x72, init_resume },
3604 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3605 { "INIT_TIME" , 0x74, init_time },
3606 { "INIT_CONDITION" , 0x75, init_condition },
3607 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3608 { "INIT_INDEX_IO" , 0x78, init_index_io },
3609 { "INIT_PLL" , 0x79, init_pll },
3610 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3611 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3612 { "INIT_8C" , 0x8C, init_8c },
3613 { "INIT_8D" , 0x8D, init_8d },
3614 { "INIT_GPIO" , 0x8E, init_gpio },
3615 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3616 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3617 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3618 { "INIT_RESERVED" , 0x92, init_reserved },
3619 { "INIT_96" , 0x96, init_96 },
3620 { "INIT_97" , 0x97, init_97 },
3621 { "INIT_AUXCH" , 0x98, init_auxch },
3622 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3623 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3627 #define MAX_TABLE_OPS 1000
3630 parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3633 * Parses all commands in an init table.
3635 * We start out executing all commands found in the init table. Some
3636 * opcodes may change the status of iexec->execute to SKIP, which will
3637 * cause the following opcodes to perform no operation until the value
3638 * is changed back to EXECUTE.
3641 int count = 0, i, ret;
3644 /* catch NULL script pointers */
3649 * Loop until INIT_DONE causes us to break out of the loop
3650 * (or until offset > bios length just in case... )
3651 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3653 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3654 id = bios->data[offset];
3656 /* Find matching id in itbl_entry */
3657 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3660 if (!itbl_entry[i].name) {
3662 "0x%04X: Init table command not found: "
3663 "0x%02X\n", offset, id);
3667 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3668 itbl_entry[i].id, itbl_entry[i].name);
3670 /* execute eventual command handler */
3671 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3673 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3674 "table opcode: %s %d\n", offset,
3675 itbl_entry[i].name, ret);
3682 * Add the offset of the current command including all data
3683 * of that command. The offset will then be pointing on the
3689 if (offset >= bios->length)
3691 "Offset 0x%04X greater than known bios image length. "
3692 "Corrupt image?\n", offset);
3693 if (count >= MAX_TABLE_OPS)
3695 "More than %d opcodes to a table is unlikely, "
3696 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3702 parse_init_tables(struct nvbios *bios)
3704 /* Loops and calls parse_init_table() for each present table. */
3708 struct init_exec iexec = {true, false};
3710 if (bios->old_style_init) {
3711 if (bios->init_script_tbls_ptr)
3712 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3713 if (bios->extra_init_script_tbl_ptr)
3714 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3719 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3721 "Parsing VBIOS init table %d at offset 0x%04X\n",
3723 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3725 parse_init_table(bios, table, &iexec);
3730 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3732 int compare_record_len, i = 0;
3733 uint16_t compareclk, scriptptr = 0;
3735 if (bios->major_version < 5) /* pre BIT */
3736 compare_record_len = 3;
3738 compare_record_len = 4;
3741 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3742 if (pxclk >= compareclk * 10) {
3743 if (bios->major_version < 5) {
3744 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3745 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3747 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3751 } while (compareclk);
3757 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3758 struct dcb_entry *dcbent, int head, bool dl)
3760 struct drm_nouveau_private *dev_priv = dev->dev_private;
3761 struct nvbios *bios = &dev_priv->vbios;
3762 struct init_exec iexec = {true, false};
3764 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3766 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3767 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3768 /* note: if dcb entries have been merged, index may be misleading */
3769 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3770 parse_init_table(bios, scriptptr, &iexec);
3772 nv04_dfp_bind_head(dev, dcbent, head, dl);
3775 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3777 struct drm_nouveau_private *dev_priv = dev->dev_private;
3778 struct nvbios *bios = &dev_priv->vbios;
3779 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3780 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3782 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3785 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3787 if (script == LVDS_PANEL_OFF) {
3788 /* off-on delay in ms */
3789 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3792 /* Powerbook specific quirks */
3793 if (script == LVDS_RESET &&
3794 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3795 dev->pci_device == 0x0329))
3796 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3802 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3805 * The BIT LVDS table's header has the information to setup the
3806 * necessary registers. Following the standard 4 byte header are:
3807 * A bitmask byte and a dual-link transition pxclk value for use in
3808 * selecting the init script when not using straps; 4 script pointers
3809 * for panel power, selected by output and on/off; and 8 table pointers
3810 * for panel init, the needed one determined by output, and bits in the
3811 * conf byte. These tables are similar to the TMDS tables, consisting
3812 * of a list of pxclks and script pointers.
3814 struct drm_nouveau_private *dev_priv = dev->dev_private;
3815 struct nvbios *bios = &dev_priv->vbios;
3816 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3817 uint16_t scriptptr = 0, clktable;
3820 * For now we assume version 3.0 table - g80 support will need some
3827 case LVDS_BACKLIGHT_ON:
3829 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3831 case LVDS_BACKLIGHT_OFF:
3832 case LVDS_PANEL_OFF:
3833 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3836 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3837 if (dcbent->or == 4)
3840 if (dcbent->lvdsconf.use_straps_for_mode) {
3841 if (bios->fp.dual_link)
3843 if (bios->fp.if_is_24bit)
3847 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3849 if (bios->fp.dual_link) {
3854 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3858 clktable = ROM16(bios->data[clktable]);
3860 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3863 scriptptr = clkcmptable(bios, clktable, pxclk);
3867 NV_ERROR(dev, "LVDS output init script not found\n");
3870 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3875 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3878 * LVDS operations are multiplexed in an effort to present a single API
3879 * which works with two vastly differing underlying structures.
3880 * This acts as the demux
3883 struct drm_nouveau_private *dev_priv = dev->dev_private;
3884 struct nvbios *bios = &dev_priv->vbios;
3885 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3886 uint32_t sel_clk_binding, sel_clk;
3889 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3890 (lvds_ver >= 0x30 && script == LVDS_INIT))
3893 if (!bios->fp.lvds_init_run) {
3894 bios->fp.lvds_init_run = true;
3895 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3898 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3899 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3900 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3901 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3903 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3905 /* don't let script change pll->head binding */
3906 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3908 if (lvds_ver < 0x30)
3909 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3911 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3913 bios->fp.last_script_invoc = (script << 1 | head);
3915 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3916 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3917 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3918 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3923 struct lvdstableheader {
3924 uint8_t lvds_ver, headerlen, recordlen;
3927 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3930 * BMP version (0xa) LVDS table has a simple header of version and
3931 * record length. The BIT LVDS table has the typical BIT table header:
3932 * version byte, header length byte, record length byte, and a byte for
3933 * the maximum number of records that can be held in the table.
3936 uint8_t lvds_ver, headerlen, recordlen;
3938 memset(lth, 0, sizeof(struct lvdstableheader));
3940 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3941 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3945 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3948 case 0x0a: /* pre NV40 */
3950 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3952 case 0x30: /* NV4x */
3953 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3954 if (headerlen < 0x1f) {
3955 NV_ERROR(dev, "LVDS table header not understood\n");
3958 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3960 case 0x40: /* G80/G90 */
3961 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3962 if (headerlen < 0x7) {
3963 NV_ERROR(dev, "LVDS table header not understood\n");
3966 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3970 "LVDS table revision %d.%d not currently supported\n",
3971 lvds_ver >> 4, lvds_ver & 0xf);
3975 lth->lvds_ver = lvds_ver;
3976 lth->headerlen = headerlen;
3977 lth->recordlen = recordlen;
3983 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3985 struct drm_nouveau_private *dev_priv = dev->dev_private;
3988 * The fp strap is normally dictated by the "User Strap" in
3989 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3990 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3991 * by the PCI subsystem ID during POST, but not before the previous user
3992 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3993 * read and used instead
3996 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3997 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3999 if (dev_priv->card_type >= NV_50)
4000 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4002 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4005 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4008 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4009 int ret, ofs, fpstrapping;
4010 struct lvdstableheader lth;
4012 if (bios->fp.fptablepointer == 0x0) {
4013 /* Apple cards don't have the fp table; the laptops use DDC */
4014 /* The table is also missing on some x86 IGPs */
4016 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4018 bios->digital_min_front_porch = 0x4b;
4022 fptable = &bios->data[bios->fp.fptablepointer];
4023 fptable_ver = fptable[0];
4025 switch (fptable_ver) {
4027 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4028 * version field, and miss one of the spread spectrum/PWM bytes.
4029 * This could affect early GF2Go parts (not seen any appropriate ROMs
4030 * though). Here we assume that a version of 0x05 matches this case
4031 * (combining with a BMP version check would be better), as the
4032 * common case for the panel type field is 0x0005, and that is in
4033 * fact what we are reading the first byte of.
4035 case 0x05: /* some NV10, 11, 15, 16 */
4039 case 0x10: /* some NV15/16, and NV11+ */
4043 case 0x20: /* NV40+ */
4044 headerlen = fptable[1];
4045 recordlen = fptable[2];
4046 fpentries = fptable[3];
4048 * fptable[4] is the minimum
4049 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4051 bios->digital_min_front_porch = fptable[4];
4056 "FP table revision %d.%d not currently supported\n",
4057 fptable_ver >> 4, fptable_ver & 0xf);
4061 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4064 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4068 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4069 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4071 bios->fp.xlatwidth = lth.recordlen;
4073 if (bios->fp.fpxlatetableptr == 0x0) {
4074 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4078 fpstrapping = get_fp_strap(dev, bios);
4080 fpindex = bios->data[bios->fp.fpxlatetableptr +
4081 fpstrapping * bios->fp.xlatwidth];
4083 if (fpindex > fpentries) {
4084 NV_ERROR(dev, "Bad flat panel table index\n");
4088 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4089 if (lth.lvds_ver > 0x10)
4090 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
4093 * If either the strap or xlated fpindex value are 0xf there is no
4094 * panel using a strap-derived bios mode present. this condition
4095 * includes, but is different from, the DDC panel indicator above
4097 if (fpstrapping == 0xf || fpindex == 0xf)
4100 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4101 recordlen * fpindex + ofs;
4103 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4104 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4105 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4106 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4111 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4113 struct drm_nouveau_private *dev_priv = dev->dev_private;
4114 struct nvbios *bios = &dev_priv->vbios;
4115 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4117 if (!mode) /* just checking whether we can produce a mode */
4118 return bios->fp.mode_ptr;
4120 memset(mode, 0, sizeof(struct drm_display_mode));
4122 * For version 1.0 (version in byte 0):
4123 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4124 * single/dual link, and type (TFT etc.)
4125 * bytes 3-6 are bits per colour in RGBX
4127 mode->clock = ROM16(mode_entry[7]) * 10;
4128 /* bytes 9-10 is HActive */
4129 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4131 * bytes 13-14 is HValid Start
4132 * bytes 15-16 is HValid End
4134 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4135 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4136 mode->htotal = ROM16(mode_entry[21]) + 1;
4137 /* bytes 23-24, 27-30 similarly, but vertical */
4138 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4139 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4140 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4141 mode->vtotal = ROM16(mode_entry[35]) + 1;
4142 mode->flags |= (mode_entry[37] & 0x10) ?
4143 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4144 mode->flags |= (mode_entry[37] & 0x1) ?
4145 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4147 * bytes 38-39 relate to spread spectrum settings
4148 * bytes 40-43 are something to do with PWM
4151 mode->status = MODE_OK;
4152 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4153 drm_mode_set_name(mode);
4154 return bios->fp.mode_ptr;
4157 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4160 * The LVDS table header is (mostly) described in
4161 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4162 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4163 * straps are not being used for the panel, this specifies the frequency
4164 * at which modes should be set up in the dual link style.
4166 * Following the header, the BMP (ver 0xa) table has several records,
4167 * indexed by a separate xlat table, indexed in turn by the fp strap in
4168 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4169 * numbers for use by INIT_SUB which controlled panel init and power,
4170 * and finally a dword of ms to sleep between power off and on
4173 * In the BIT versions, the table following the header serves as an
4174 * integrated config and xlat table: the records in the table are
4175 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4176 * two bytes - the first as a config byte, the second for indexing the
4177 * fp mode table pointed to by the BIT 'D' table
4179 * DDC is not used until after card init, so selecting the correct table
4180 * entry and setting the dual link flag for EDID equipped panels,
4181 * requiring tests against the native-mode pixel clock, cannot be done
4182 * until later, when this function should be called with non-zero pxclk
4184 struct drm_nouveau_private *dev_priv = dev->dev_private;
4185 struct nvbios *bios = &dev_priv->vbios;
4186 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4187 struct lvdstableheader lth;
4189 int ret, chip_version = bios->chip_version;
4191 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4195 switch (lth.lvds_ver) {
4196 case 0x0a: /* pre NV40 */
4197 lvdsmanufacturerindex = bios->data[
4198 bios->fp.fpxlatemanufacturertableptr +
4201 /* we're done if this isn't the EDID panel case */
4205 if (chip_version < 0x25) {
4208 * It seems the old style lvds script pointer is reused
4209 * to select 18/24 bit colour depth for EDID panels.
4211 lvdsmanufacturerindex =
4212 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4214 if (pxclk >= bios->fp.duallink_transition_clk)
4215 lvdsmanufacturerindex++;
4216 } else if (chip_version < 0x30) {
4217 /* nv28 behaviour (off-chip encoder)
4219 * nv28 does a complex dance of first using byte 121 of
4220 * the EDID to choose the lvdsmanufacturerindex, then
4221 * later attempting to match the EDID manufacturer and
4222 * product IDs in a table (signature 'pidt' (panel id
4223 * table?)), setting an lvdsmanufacturerindex of 0 and
4224 * an fp strap of the match index (or 0xf if none)
4226 lvdsmanufacturerindex = 0;
4228 /* nv31, nv34 behaviour */
4229 lvdsmanufacturerindex = 0;
4230 if (pxclk >= bios->fp.duallink_transition_clk)
4231 lvdsmanufacturerindex = 2;
4232 if (pxclk >= 140000)
4233 lvdsmanufacturerindex = 3;
4237 * nvidia set the high nibble of (cr57=f, cr58) to
4238 * lvdsmanufacturerindex in this case; we don't
4241 case 0x30: /* NV4x */
4242 case 0x40: /* G80/G90 */
4243 lvdsmanufacturerindex = fpstrapping;
4246 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4250 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4251 switch (lth.lvds_ver) {
4253 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4254 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4255 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4256 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4257 *if_is_24bit = bios->data[lvdsofs] & 16;
4262 * No sign of the "power off for reset" or "reset for panel
4263 * on" bits, but it's safer to assume we should
4265 bios->fp.power_off_for_reset = true;
4266 bios->fp.reset_after_pclk_change = true;
4269 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4270 * over-written, and if_is_24bit isn't used
4272 bios->fp.dual_link = bios->data[lvdsofs] & 1;
4273 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4274 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4275 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4279 /* set dual_link flag for EDID case */
4280 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4281 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4283 *dl = bios->fp.dual_link;
4288 /* BIT 'U'/'d' table encoder subtables have hashes matching them to
4289 * a particular set of encoders.
4291 * This function returns true if a particular DCB entry matches.
4294 bios_encoder_match(struct dcb_entry *dcb, u32 hash)
4296 if ((hash & 0x000000f0) != (dcb->location << 4))
4298 if ((hash & 0x0000000f) != dcb->type)
4300 if (!(hash & (dcb->or << 16)))
4303 switch (dcb->type) {
4307 if (hash & 0x00c00000) {
4308 if (!(hash & (dcb->sorconf.link << 22)))
4317 nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4318 struct dcb_entry *dcbent, int crtc)
4321 * The display script table is located by the BIT 'U' table.
4323 * It contains an array of pointers to various tables describing
4324 * a particular output type. The first 32-bits of the output
4325 * tables contains similar information to a DCB entry, and is
4326 * used to decide whether that particular table is suitable for
4327 * the output you want to access.
4329 * The "record header length" field here seems to indicate the
4330 * offset of the first configuration entry in the output tables.
4331 * This is 10 on most cards I've seen, but 12 has been witnessed
4332 * on DP cards, and there's another script pointer within the
4335 * offset + 0 ( 8 bits): version
4336 * offset + 1 ( 8 bits): header length
4337 * offset + 2 ( 8 bits): record length
4338 * offset + 3 ( 8 bits): number of records
4339 * offset + 4 ( 8 bits): record header length
4340 * offset + 5 (16 bits): pointer to first output script table
4343 struct drm_nouveau_private *dev_priv = dev->dev_private;
4344 struct nvbios *bios = &dev_priv->vbios;
4345 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4346 uint8_t *otable = NULL;
4350 if (!bios->display.script_table_ptr) {
4351 NV_ERROR(dev, "No pointer to output script table\n");
4356 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4357 * so until they are, we really don't need to care.
4359 if (table[0] < 0x20)
4362 if (table[0] != 0x20 && table[0] != 0x21) {
4363 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4369 * The output script tables describing a particular output type
4372 * offset + 0 (32 bits): output this table matches (hash of DCB)
4373 * offset + 4 ( 8 bits): unknown
4374 * offset + 5 ( 8 bits): number of configurations
4375 * offset + 6 (16 bits): pointer to some script
4376 * offset + 8 (16 bits): pointer to some script
4379 * offset + 10 : configuration 0
4382 * offset + 10 : pointer to some script
4383 * offset + 12 : configuration 0
4385 * Each config entry is as follows:
4387 * offset + 0 (16 bits): unknown, assumed to be a match value
4388 * offset + 2 (16 bits): pointer to script table (clock set?)
4389 * offset + 4 (16 bits): pointer to script table (reset?)
4391 * There doesn't appear to be a count value to say how many
4392 * entries exist in each script table, instead, a 0 value in
4393 * the first 16-bit word seems to indicate both the end of the
4394 * list and the default entry. The second 16-bit word in the
4395 * script tables is a pointer to the script to execute.
4398 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
4399 dcbent->type, dcbent->location, dcbent->or);
4400 for (i = 0; i < table[3]; i++) {
4401 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
4402 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4407 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4411 if (pclk < -2 || pclk > 0) {
4412 /* Try to find matching script table entry */
4413 for (i = 0; i < otable[5]; i++) {
4414 if (ROM16(otable[table[4] + i*6]) == type)
4418 if (i == otable[5]) {
4419 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4421 type, dcbent->type, dcbent->or);
4427 script = ROM16(otable[6]);
4429 NV_DEBUG_KMS(dev, "output script 0 not found\n");
4433 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4434 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4437 script = ROM16(otable[8]);
4439 NV_DEBUG_KMS(dev, "output script 1 not found\n");
4443 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4444 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4448 script = ROM16(otable[10]);
4452 NV_DEBUG_KMS(dev, "output script 2 not found\n");
4456 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4457 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4460 script = ROM16(otable[table[4] + i*6 + 2]);
4462 script = clkcmptable(bios, script, pclk);
4464 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4468 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4469 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4472 script = ROM16(otable[table[4] + i*6 + 4]);
4474 script = clkcmptable(bios, script, -pclk);
4476 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
4480 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4481 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4488 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4491 * the pxclk parameter is in kHz
4493 * This runs the TMDS regs setting code found on BIT bios cards
4495 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4496 * ffs(or) == 3, use the second.
4499 struct drm_nouveau_private *dev_priv = dev->dev_private;
4500 struct nvbios *bios = &dev_priv->vbios;
4501 int cv = bios->chip_version;
4502 uint16_t clktable = 0, scriptptr;
4503 uint32_t sel_clk_binding, sel_clk;
4505 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4506 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4507 dcbent->location != DCB_LOC_ON_CHIP)
4510 switch (ffs(dcbent->or)) {
4512 clktable = bios->tmds.output0_script_ptr;
4516 clktable = bios->tmds.output1_script_ptr;
4521 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4525 scriptptr = clkcmptable(bios, clktable, pxclk);
4528 NV_ERROR(dev, "TMDS output init script not found\n");
4532 /* don't let script change pll->head binding */
4533 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4534 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4535 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4536 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4541 struct pll_mapping {
4546 static struct pll_mapping nv04_pll_mapping[] = {
4547 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4548 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4549 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4550 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4554 static struct pll_mapping nv40_pll_mapping[] = {
4555 { PLL_CORE , 0x004000 },
4556 { PLL_MEMORY, 0x004020 },
4557 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4558 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4562 static struct pll_mapping nv50_pll_mapping[] = {
4563 { PLL_CORE , 0x004028 },
4564 { PLL_SHADER, 0x004020 },
4565 { PLL_UNK03 , 0x004000 },
4566 { PLL_MEMORY, 0x004008 },
4567 { PLL_UNK40 , 0x00e810 },
4568 { PLL_UNK41 , 0x00e818 },
4569 { PLL_UNK42 , 0x00e824 },
4570 { PLL_VPLL0 , 0x614100 },
4571 { PLL_VPLL1 , 0x614900 },
4575 static struct pll_mapping nv84_pll_mapping[] = {
4576 { PLL_CORE , 0x004028 },
4577 { PLL_SHADER, 0x004020 },
4578 { PLL_MEMORY, 0x004008 },
4579 { PLL_VDEC , 0x004030 },
4580 { PLL_UNK41 , 0x00e818 },
4581 { PLL_VPLL0 , 0x614100 },
4582 { PLL_VPLL1 , 0x614900 },
4587 get_pll_register(struct drm_device *dev, enum pll_types type)
4589 struct drm_nouveau_private *dev_priv = dev->dev_private;
4590 struct nvbios *bios = &dev_priv->vbios;
4591 struct pll_mapping *map;
4594 if (dev_priv->card_type < NV_40)
4595 map = nv04_pll_mapping;
4597 if (dev_priv->card_type < NV_50)
4598 map = nv40_pll_mapping;
4600 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4602 if (plim[0] >= 0x30) {
4603 u8 *entry = plim + plim[1];
4604 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4605 if (entry[0] == type)
4606 return ROM32(entry[3]);
4612 if (dev_priv->chipset == 0x50)
4613 map = nv50_pll_mapping;
4615 map = nv84_pll_mapping;
4619 if (map->type == type)
4627 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4632 * Version 0x10: NV30, NV31
4633 * One byte header (version), one record of 24 bytes
4634 * Version 0x11: NV36 - Not implemented
4635 * Seems to have same record style as 0x10, but 3 records rather than 1
4636 * Version 0x20: Found on Geforce 6 cards
4637 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4638 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4639 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4640 * length in general, some (integrated) have an extra configuration byte
4641 * Version 0x30: Found on Geforce 8, separates the register mapping
4642 * from the limits tables.
4645 struct drm_nouveau_private *dev_priv = dev->dev_private;
4646 struct nvbios *bios = &dev_priv->vbios;
4647 int cv = bios->chip_version, pllindex = 0;
4648 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4649 uint32_t crystal_strap_mask, crystal_straps;
4651 if (!bios->pll_limit_tbl_ptr) {
4652 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4654 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4658 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4660 crystal_strap_mask = 1 << 6;
4661 /* open coded dev->twoHeads test */
4662 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4663 crystal_strap_mask |= 1 << 22;
4664 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4667 switch (pll_lim_ver) {
4669 * We use version 0 to indicate a pre limit table bios (single stage
4670 * pll) and load the hard coded limits instead.
4677 * Strictly v0x11 has 3 entries, but the last two don't seem
4689 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4690 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4691 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4694 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4695 "supported\n", pll_lim_ver);
4699 /* initialize all members to zero */
4700 memset(pll_lim, 0, sizeof(struct pll_lims));
4702 /* if we were passed a type rather than a register, figure
4703 * out the register and store it
4705 if (limit_match > PLL_MAX)
4706 pll_lim->reg = limit_match;
4708 pll_lim->reg = get_pll_register(dev, limit_match);
4713 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4714 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4716 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4717 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4718 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4719 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4720 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4721 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4722 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4724 /* these values taken from nv30/31/36 */
4725 pll_lim->vco1.min_n = 0x1;
4727 pll_lim->vco1.min_n = 0x5;
4728 pll_lim->vco1.max_n = 0xff;
4729 pll_lim->vco1.min_m = 0x1;
4730 pll_lim->vco1.max_m = 0xd;
4731 pll_lim->vco2.min_n = 0x4;
4733 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4734 * table version (apart from nv35)), N2 is compared to
4735 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4738 pll_lim->vco2.max_n = 0x28;
4739 if (cv == 0x30 || cv == 0x35)
4740 /* only 5 bits available for N2 on nv30/35 */
4741 pll_lim->vco2.max_n = 0x1f;
4742 pll_lim->vco2.min_m = 0x1;
4743 pll_lim->vco2.max_m = 0x4;
4744 pll_lim->max_log2p = 0x7;
4745 pll_lim->max_usable_log2p = 0x6;
4746 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4747 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4752 * First entry is default match, if nothing better. warn if
4755 if (ROM32(bios->data[plloffs]))
4756 NV_WARN(dev, "Default PLL limit entry has non-zero "
4757 "register field\n");
4759 for (i = 1; i < entries; i++)
4760 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
4765 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4766 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4767 "limits table", pll_lim->reg);
4771 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4773 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4774 pllindex ? pll_lim->reg : 0);
4777 * Frequencies are stored in tables in MHz, kHz are more
4778 * useful, so we convert.
4781 /* What output frequencies can each VCO generate? */
4782 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4783 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4784 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4785 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4787 /* What input frequencies they accept (past the m-divider)? */
4788 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4789 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4790 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4791 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4793 /* What values are accepted as multiplier and divider? */
4794 pll_lim->vco1.min_n = pll_rec[20];
4795 pll_lim->vco1.max_n = pll_rec[21];
4796 pll_lim->vco1.min_m = pll_rec[22];
4797 pll_lim->vco1.max_m = pll_rec[23];
4798 pll_lim->vco2.min_n = pll_rec[24];
4799 pll_lim->vco2.max_n = pll_rec[25];
4800 pll_lim->vco2.min_m = pll_rec[26];
4801 pll_lim->vco2.max_m = pll_rec[27];
4803 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4804 if (pll_lim->max_log2p > 0x7)
4805 /* pll decoding in nv_hw.c assumes never > 7 */
4806 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4807 pll_lim->max_log2p);
4809 pll_lim->max_usable_log2p = 0x6;
4810 pll_lim->log2p_bias = pll_rec[30];
4812 if (recordlen > 0x22)
4813 pll_lim->refclk = ROM32(pll_rec[31]);
4815 if (recordlen > 0x23 && pll_rec[35])
4817 "Bits set in PLL configuration byte (%x)\n",
4820 /* C51 special not seen elsewhere */
4821 if (cv == 0x51 && !pll_lim->refclk) {
4822 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4824 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4825 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
4826 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4827 pll_lim->refclk = 200000;
4829 pll_lim->refclk = 25000;
4832 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4833 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4834 uint8_t *record = NULL;
4837 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4840 for (i = 0; i < entries; i++, entry += recordlen) {
4841 if (ROM32(entry[3]) == pll_lim->reg) {
4842 record = &bios->data[ROM16(entry[1])];
4848 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4849 "limits table", pll_lim->reg);
4853 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4854 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4855 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4856 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4857 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4858 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4859 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4860 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4861 pll_lim->vco1.min_n = record[16];
4862 pll_lim->vco1.max_n = record[17];
4863 pll_lim->vco1.min_m = record[18];
4864 pll_lim->vco1.max_m = record[19];
4865 pll_lim->vco2.min_n = record[20];
4866 pll_lim->vco2.max_n = record[21];
4867 pll_lim->vco2.min_m = record[22];
4868 pll_lim->vco2.max_m = record[23];
4869 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4870 pll_lim->log2p_bias = record[27];
4871 pll_lim->refclk = ROM32(record[28]);
4872 } else if (pll_lim_ver) { /* ver 0x40 */
4873 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4874 uint8_t *record = NULL;
4877 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4880 for (i = 0; i < entries; i++, entry += recordlen) {
4881 if (ROM32(entry[3]) == pll_lim->reg) {
4882 record = &bios->data[ROM16(entry[1])];
4888 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4889 "limits table", pll_lim->reg);
4893 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4894 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4895 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4896 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4897 pll_lim->vco1.min_m = record[8];
4898 pll_lim->vco1.max_m = record[9];
4899 pll_lim->vco1.min_n = record[10];
4900 pll_lim->vco1.max_n = record[11];
4901 pll_lim->min_p = record[12];
4902 pll_lim->max_p = record[13];
4903 pll_lim->refclk = ROM16(entry[9]) * 1000;
4907 * By now any valid limit table ought to have set a max frequency for
4908 * vco1, so if it's zero it's either a pre limit table bios, or one
4909 * with an empty limit table (seen on nv18)
4911 if (!pll_lim->vco1.maxfreq) {
4912 pll_lim->vco1.minfreq = bios->fminvco;
4913 pll_lim->vco1.maxfreq = bios->fmaxvco;
4914 pll_lim->vco1.min_inputfreq = 0;
4915 pll_lim->vco1.max_inputfreq = INT_MAX;
4916 pll_lim->vco1.min_n = 0x1;
4917 pll_lim->vco1.max_n = 0xff;
4918 pll_lim->vco1.min_m = 0x1;
4919 if (crystal_straps == 0) {
4920 /* nv05 does this, nv11 doesn't, nv10 unknown */
4922 pll_lim->vco1.min_m = 0x7;
4923 pll_lim->vco1.max_m = 0xd;
4926 pll_lim->vco1.min_m = 0x8;
4927 pll_lim->vco1.max_m = 0xe;
4929 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4930 pll_lim->max_log2p = 4;
4932 pll_lim->max_log2p = 5;
4933 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4936 if (!pll_lim->refclk)
4937 switch (crystal_straps) {
4939 pll_lim->refclk = 13500;
4942 pll_lim->refclk = 14318;
4945 pll_lim->refclk = 27000;
4947 case (1 << 22 | 1 << 6):
4948 pll_lim->refclk = 25000;
4952 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4953 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4954 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4955 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4956 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4957 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4958 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4959 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4960 if (pll_lim->vco2.maxfreq) {
4961 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4962 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4963 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4964 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4965 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4966 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4967 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4968 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4970 if (!pll_lim->max_p) {
4971 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4972 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4974 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4975 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4977 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
4982 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4985 * offset + 0 (8 bits): Micro version
4986 * offset + 1 (8 bits): Minor version
4987 * offset + 2 (8 bits): Chip version
4988 * offset + 3 (8 bits): Major version
4991 bios->major_version = bios->data[offset + 3];
4992 bios->chip_version = bios->data[offset + 2];
4993 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4994 bios->data[offset + 3], bios->data[offset + 2],
4995 bios->data[offset + 1], bios->data[offset]);
4998 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5001 * Parses the init table segment for pointers used in script execution.
5003 * offset + 0 (16 bits): init script tables pointer
5004 * offset + 2 (16 bits): macro index table pointer
5005 * offset + 4 (16 bits): macro table pointer
5006 * offset + 6 (16 bits): condition table pointer
5007 * offset + 8 (16 bits): io condition table pointer
5008 * offset + 10 (16 bits): io flag condition table pointer
5009 * offset + 12 (16 bits): init function table pointer
5012 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5013 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5014 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5015 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5016 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5017 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5018 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5021 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5024 * Parses the load detect values for g80 cards.
5026 * offset + 0 (16 bits): loadval table pointer
5029 uint16_t load_table_ptr;
5030 uint8_t version, headerlen, entrylen, num_entries;
5032 if (bitentry->length != 3) {
5033 NV_ERROR(dev, "Do not understand BIT A table\n");
5037 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5039 if (load_table_ptr == 0x0) {
5040 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
5044 version = bios->data[load_table_ptr];
5046 if (version != 0x10) {
5047 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5048 version >> 4, version & 0xF);
5052 headerlen = bios->data[load_table_ptr + 1];
5053 entrylen = bios->data[load_table_ptr + 2];
5054 num_entries = bios->data[load_table_ptr + 3];
5056 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5057 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5061 /* First entry is normal dac, 2nd tv-out perhaps? */
5062 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
5067 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5070 * offset + 8 (16 bits): PLL limits table pointer
5072 * There's more in here, but that's unknown.
5075 if (bitentry->length < 10) {
5076 NV_ERROR(dev, "Do not understand BIT C table\n");
5080 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5085 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5088 * Parses the flat panel table segment that the bit entry points to.
5089 * Starting at bitentry->offset:
5091 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5092 * records beginning with a freq.
5093 * offset + 2 (16 bits): mode table pointer
5096 if (bitentry->length != 4) {
5097 NV_ERROR(dev, "Do not understand BIT display table\n");
5101 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5106 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5109 * Parses the init table segment that the bit entry points to.
5111 * See parse_script_table_pointers for layout
5114 if (bitentry->length < 14) {
5115 NV_ERROR(dev, "Do not understand init table\n");
5119 parse_script_table_pointers(bios, bitentry->offset);
5121 if (bitentry->length >= 16)
5122 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5123 if (bitentry->length >= 18)
5124 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5129 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5132 * BIT 'i' (info?) table
5134 * offset + 0 (32 bits): BIOS version dword (as in B table)
5135 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5136 * offset + 13 (16 bits): pointer to table containing DAC load
5137 * detection comparison values
5139 * There's other things in the table, purpose unknown
5142 uint16_t daccmpoffset;
5143 uint8_t dacver, dacheaderlen;
5145 if (bitentry->length < 6) {
5146 NV_ERROR(dev, "BIT i table too short for needed information\n");
5150 parse_bios_version(dev, bios, bitentry->offset);
5153 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5154 * Quadro identity crisis), other bits possibly as for BMP feature byte
5156 bios->feature_byte = bios->data[bitentry->offset + 5];
5157 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5159 if (bitentry->length < 15) {
5160 NV_WARN(dev, "BIT i table not long enough for DAC load "
5161 "detection comparison table\n");
5165 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5167 /* doesn't exist on g80 */
5172 * The first value in the table, following the header, is the
5173 * comparison value, the second entry is a comparison value for
5174 * TV load detection.
5177 dacver = bios->data[daccmpoffset];
5178 dacheaderlen = bios->data[daccmpoffset + 1];
5180 if (dacver != 0x00 && dacver != 0x10) {
5181 NV_WARN(dev, "DAC load detection comparison table version "
5182 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5186 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5187 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
5192 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5195 * Parses the LVDS table segment that the bit entry points to.
5196 * Starting at bitentry->offset:
5198 * offset + 0 (16 bits): LVDS strap xlate table pointer
5201 if (bitentry->length != 2) {
5202 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5207 * No idea if it's still called the LVDS manufacturer table, but
5208 * the concept's close enough.
5210 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5216 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5217 struct bit_entry *bitentry)
5220 * offset + 2 (8 bits): number of options in an
5221 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5222 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5223 * restrict option selection
5225 * There's a bunch of bits in this table other than the RAM restrict
5226 * stuff that we don't use - their use currently unknown
5230 * Older bios versions don't have a sufficiently long table for
5233 if (bitentry->length < 0x5)
5236 if (bitentry->version < 2) {
5237 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5238 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
5240 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5241 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
5247 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5250 * Parses the pointer to the TMDS table
5252 * Starting at bitentry->offset:
5254 * offset + 0 (16 bits): TMDS table pointer
5256 * The TMDS table is typically found just before the DCB table, with a
5257 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5260 * At offset +7 is a pointer to a script, which I don't know how to
5262 * At offset +9 is a pointer to another script, likewise
5263 * Offset +11 has a pointer to a table where the first word is a pxclk
5264 * frequency and the second word a pointer to a script, which should be
5265 * run if the comparison pxclk frequency is less than the pxclk desired.
5266 * This repeats for decreasing comparison frequencies
5267 * Offset +13 has a pointer to a similar table
5268 * The selection of table (and possibly +7/+9 script) is dictated by
5269 * "or" from the DCB.
5272 uint16_t tmdstableptr, script1, script2;
5274 if (bitentry->length != 2) {
5275 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5279 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5280 if (!tmdstableptr) {
5281 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5285 NV_INFO(dev, "TMDS table version %d.%d\n",
5286 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5288 /* nv50+ has v2.0, but we don't parse it atm */
5289 if (bios->data[tmdstableptr] != 0x11)
5293 * These two scripts are odd: they don't seem to get run even when
5294 * they are not stubbed.
5296 script1 = ROM16(bios->data[tmdstableptr + 7]);
5297 script2 = ROM16(bios->data[tmdstableptr + 9]);
5298 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5299 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5301 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5302 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5308 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5309 struct bit_entry *bitentry)
5312 * Parses the pointer to the G80 output script tables
5314 * Starting at bitentry->offset:
5316 * offset + 0 (16 bits): output script table pointer
5319 uint16_t outputscripttableptr;
5321 if (bitentry->length != 3) {
5322 NV_ERROR(dev, "Do not understand BIT U table\n");
5326 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5327 bios->display.script_table_ptr = outputscripttableptr;
5333 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5336 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5339 bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5341 struct drm_nouveau_private *dev_priv = dev->dev_private;
5342 struct nvbios *bios = &dev_priv->vbios;
5345 if (bios->type != NVBIOS_BIT)
5348 entries = bios->data[bios->offset + 10];
5349 entry = &bios->data[bios->offset + 12];
5351 if (entry[0] == id) {
5353 bit->version = entry[1];
5354 bit->length = ROM16(entry[2]);
5355 bit->offset = ROM16(entry[4]);
5356 bit->data = ROMPTR(dev, entry[4]);
5360 entry += bios->data[bios->offset + 9];
5367 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5368 struct bit_table *table)
5370 struct drm_device *dev = bios->dev;
5371 struct bit_entry bitentry;
5373 if (bit_table(dev, table->id, &bitentry) == 0)
5374 return table->parse_fn(dev, bios, &bitentry);
5376 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5381 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5386 * The only restriction on parsing order currently is having 'i' first
5387 * for use of bios->*_version or bios->feature_byte while parsing;
5388 * functions shouldn't be actually *doing* anything apart from pulling
5389 * data from the image into the bios struct, thus no interdependencies
5391 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5392 if (ret) /* info? */
5394 if (bios->major_version >= 0x60) /* g80+ */
5395 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5396 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5399 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5400 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5403 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5404 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5405 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5406 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5411 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5414 * Parses the BMP structure for useful things, but does not act on them
5416 * offset + 5: BMP major version
5417 * offset + 6: BMP minor version
5418 * offset + 9: BMP feature byte
5419 * offset + 10: BCD encoded BIOS version
5421 * offset + 18: init script table pointer (for bios versions < 5.10h)
5422 * offset + 20: extra init script table pointer (for bios
5425 * offset + 24: memory init table pointer (used on early bios versions)
5426 * offset + 26: SDR memory sequencing setup data table
5427 * offset + 28: DDR memory sequencing setup data table
5429 * offset + 54: index of I2C CRTC pair to use for CRT output
5430 * offset + 55: index of I2C CRTC pair to use for TV output
5431 * offset + 56: index of I2C CRTC pair to use for flat panel output
5432 * offset + 58: write CRTC index for I2C pair 0
5433 * offset + 59: read CRTC index for I2C pair 0
5434 * offset + 60: write CRTC index for I2C pair 1
5435 * offset + 61: read CRTC index for I2C pair 1
5437 * offset + 67: maximum internal PLL frequency (single stage PLL)
5438 * offset + 71: minimum internal PLL frequency (single stage PLL)
5440 * offset + 75: script table pointers, as described in
5441 * parse_script_table_pointers
5443 * offset + 89: TMDS single link output A table pointer
5444 * offset + 91: TMDS single link output B table pointer
5445 * offset + 95: LVDS single link output A table pointer
5446 * offset + 105: flat panel timings table pointer
5447 * offset + 107: flat panel strapping translation table pointer
5448 * offset + 117: LVDS manufacturer panel config table pointer
5449 * offset + 119: LVDS manufacturer strapping translation table pointer
5451 * offset + 142: PLL limits table pointer
5453 * offset + 156: minimum pixel clock for LVDS dual link
5456 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5458 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5460 /* load needed defaults in case we can't parse this info */
5461 bios->digital_min_front_porch = 0x4b;
5462 bios->fmaxvco = 256000;
5463 bios->fminvco = 128000;
5464 bios->fp.duallink_transition_clk = 90000;
5466 bmp_version_major = bmp[5];
5467 bmp_version_minor = bmp[6];
5469 NV_TRACE(dev, "BMP version %d.%d\n",
5470 bmp_version_major, bmp_version_minor);
5473 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5474 * pointer on early versions
5476 if (bmp_version_major < 5)
5477 *(uint16_t *)&bios->data[0x36] = 0;
5480 * Seems that the minor version was 1 for all major versions prior
5481 * to 5. Version 6 could theoretically exist, but I suspect BIT
5484 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5485 NV_ERROR(dev, "You have an unsupported BMP version. "
5486 "Please send in your bios\n");
5490 if (bmp_version_major == 0)
5491 /* nothing that's currently useful in this version */
5493 else if (bmp_version_major == 1)
5494 bmplength = 44; /* exact for 1.01 */
5495 else if (bmp_version_major == 2)
5496 bmplength = 48; /* exact for 2.01 */
5497 else if (bmp_version_major == 3)
5499 /* guessed - mem init tables added in this version */
5500 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5501 /* don't know if 5.0 exists... */
5503 /* guessed - BMP I2C indices added in version 4*/
5504 else if (bmp_version_minor < 0x6)
5505 bmplength = 67; /* exact for 5.01 */
5506 else if (bmp_version_minor < 0x10)
5507 bmplength = 75; /* exact for 5.06 */
5508 else if (bmp_version_minor == 0x10)
5509 bmplength = 89; /* exact for 5.10h */
5510 else if (bmp_version_minor < 0x14)
5511 bmplength = 118; /* exact for 5.11h */
5512 else if (bmp_version_minor < 0x24)
5514 * Not sure of version where pll limits came in;
5515 * certainly exist by 0x24 though.
5517 /* length not exact: this is long enough to get lvds members */
5519 else if (bmp_version_minor < 0x27)
5521 * Length not exact: this is long enough to get pll limit
5527 * Length not exact: this is long enough to get dual link
5533 if (nv_cksum(bmp, 8)) {
5534 NV_ERROR(dev, "Bad BMP checksum\n");
5539 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5540 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5541 * (not nv10gl), bit 5 that the flat panel tables are present, and
5544 bios->feature_byte = bmp[9];
5546 parse_bios_version(dev, bios, offset + 10);
5548 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5549 bios->old_style_init = true;
5550 legacy_scripts_offset = 18;
5551 if (bmp_version_major < 2)
5552 legacy_scripts_offset -= 4;
5553 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5554 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5556 if (bmp_version_major > 2) { /* appears in BMP 3 */
5557 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5558 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5559 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5562 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5564 legacy_i2c_offset = offset + 54;
5565 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5566 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5567 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
5569 if (bmplength > 74) {
5570 bios->fmaxvco = ROM32(bmp[67]);
5571 bios->fminvco = ROM32(bmp[71]);
5574 parse_script_table_pointers(bios, offset + 75);
5575 if (bmplength > 94) {
5576 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5577 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5579 * Never observed in use with lvds scripts, but is reused for
5580 * 18/24 bit panel interface default for EDID equipped panels
5581 * (if_is_24bit not set directly to avoid any oscillation).
5583 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5585 if (bmplength > 108) {
5586 bios->fp.fptablepointer = ROM16(bmp[105]);
5587 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5588 bios->fp.xlatwidth = 1;
5590 if (bmplength > 120) {
5591 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5592 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5594 if (bmplength > 143)
5595 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5597 if (bmplength > 157)
5598 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5603 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5607 for (i = 0; i <= (n - len); i++) {
5608 for (j = 0; j < len; j++)
5609 if (data[i + j] != str[j])
5619 dcb_table(struct drm_device *dev)
5621 struct drm_nouveau_private *dev_priv = dev->dev_private;
5624 if (dev_priv->card_type > NV_04)
5625 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]);
5627 NV_WARNONCE(dev, "No DCB data found in VBIOS\n");
5631 if (dcb[0] >= 0x41) {
5632 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]);
5635 if (dcb[0] >= 0x30) {
5636 if (ROM32(dcb[6]) == 0x4edcbdcb)
5639 if (dcb[0] >= 0x20) {
5640 if (ROM32(dcb[4]) == 0x4edcbdcb)
5643 if (dcb[0] >= 0x15) {
5644 if (!memcmp(&dcb[-7], "DEV_REC", 7))
5648 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
5649 * always has the same single (crt) entry, even when tv-out
5650 * present, so the conclusion is this version cannot really
5653 * v1.2 tables (some NV6/10, and NV15+) normally have the
5654 * same 5 entries, which are not specific to the card and so
5657 * v1.2 does have an I2C table that read_dcb_i2c_table can
5658 * handle, but cards exist (nv11 in #14821) with a bad i2c
5659 * table pointer, so use the indices parsed in
5660 * parse_bmp_structure.
5662 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5664 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n");
5668 NV_WARNONCE(dev, "DCB header validation failed\n");
5673 dcb_outp(struct drm_device *dev, u8 idx)
5675 u8 *dcb = dcb_table(dev);
5676 if (dcb && dcb[0] >= 0x30) {
5678 return dcb + dcb[1] + (idx * dcb[3]);
5680 if (dcb && dcb[0] >= 0x20) {
5681 u8 *i2c = ROMPTR(dev, dcb[2]);
5682 u8 *ent = dcb + 8 + (idx * 8);
5683 if (i2c && ent < i2c)
5686 if (dcb && dcb[0] >= 0x15) {
5687 u8 *i2c = ROMPTR(dev, dcb[2]);
5688 u8 *ent = dcb + 4 + (idx * 10);
5689 if (i2c && ent < i2c)
5697 dcb_outp_foreach(struct drm_device *dev, void *data,
5698 int (*exec)(struct drm_device *, void *, int idx, u8 *outp))
5702 while ((outp = dcb_outp(dev, ++idx))) {
5703 if (ROM32(outp[0]) == 0x00000000)
5704 break; /* seen on an NV11 with DCB v1.5 */
5705 if (ROM32(outp[0]) == 0xffffffff)
5706 break; /* seen on an NV17 with DCB v2.0 */
5708 if ((outp[0] & 0x0f) == OUTPUT_UNUSED)
5710 if ((outp[0] & 0x0f) == OUTPUT_EOL)
5713 ret = exec(dev, data, idx, outp);
5722 dcb_conntab(struct drm_device *dev)
5724 u8 *dcb = dcb_table(dev);
5725 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) {
5726 u8 *conntab = ROMPTR(dev, dcb[0x14]);
5727 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40)
5734 dcb_conn(struct drm_device *dev, u8 idx)
5736 u8 *conntab = dcb_conntab(dev);
5737 if (conntab && idx < conntab[2])
5738 return conntab + conntab[1] + (idx * conntab[3]);
5742 static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
5744 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5746 memset(entry, 0, sizeof(struct dcb_entry));
5747 entry->index = dcb->entries++;
5752 static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
5755 struct dcb_entry *entry = new_dcb_entry(dcb);
5758 entry->i2c_index = i2c;
5759 entry->heads = heads;
5760 if (type != OUTPUT_ANALOG)
5761 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5766 parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5767 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5769 entry->type = conn & 0xf;
5770 entry->i2c_index = (conn >> 4) & 0xf;
5771 entry->heads = (conn >> 8) & 0xf;
5772 entry->connector = (conn >> 12) & 0xf;
5773 entry->bus = (conn >> 16) & 0xf;
5774 entry->location = (conn >> 20) & 0x3;
5775 entry->or = (conn >> 24) & 0xf;
5777 switch (entry->type) {
5780 * Although the rest of a CRT conf dword is usually
5781 * zeros, mac biosen have stuff there so we must mask
5783 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
5784 (conf & 0xffff) * 10 :
5785 (conf & 0xff) * 10000;
5791 entry->lvdsconf.use_straps_for_mode = true;
5792 if (dcb->version < 0x22) {
5795 * The laptop in bug 14567 lies and claims to not use
5796 * straps when it does, so assume all DCB 2.0 laptops
5797 * use straps, until a broken EDID using one is produced
5799 entry->lvdsconf.use_straps_for_mode = true;
5801 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5802 * mean the same thing (probably wrong, but might work)
5804 if (conf & 0x4 || conf & 0x8)
5805 entry->lvdsconf.use_power_scripts = true;
5809 entry->lvdsconf.use_acpi_for_edid = true;
5811 entry->lvdsconf.use_power_scripts = true;
5812 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
5816 * Until we even try to use these on G8x, it's
5817 * useless reporting unknown bits. They all are.
5819 if (dcb->version >= 0x40)
5822 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5829 if (dcb->version >= 0x30)
5830 entry->tvconf.has_component_output = conf & (0x8 << 4);
5832 entry->tvconf.has_component_output = false;
5837 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5838 switch ((conf & 0x00e00000) >> 21) {
5840 entry->dpconf.link_bw = 162000;
5843 entry->dpconf.link_bw = 270000;
5846 switch ((conf & 0x0f000000) >> 24) {
5848 entry->dpconf.link_nr = 4;
5851 entry->dpconf.link_nr = 2;
5854 entry->dpconf.link_nr = 1;
5859 if (dcb->version >= 0x40)
5860 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5861 else if (dcb->version >= 0x30)
5862 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
5863 else if (dcb->version >= 0x22)
5864 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
5868 /* weird g80 mobile type that "nv" treats as a terminator */
5875 if (dcb->version < 0x40) {
5876 /* Normal entries consist of a single bit, but dual link has
5877 * the next most significant bit set too
5879 entry->duallink_possible =
5880 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5882 entry->duallink_possible = (entry->sorconf.link == 3);
5885 /* unsure what DCB version introduces this, 3.0? */
5886 if (conf & 0x100000)
5887 entry->i2c_upper_default = true;
5893 parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
5894 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5896 switch (conn & 0x0000000f) {
5898 entry->type = OUTPUT_ANALOG;
5901 entry->type = OUTPUT_TV;
5906 entry->type = OUTPUT_LVDS;
5908 entry->type = OUTPUT_TMDS;
5911 entry->type = OUTPUT_LVDS;
5914 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5918 entry->i2c_index = (conn & 0x0003c000) >> 14;
5919 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5920 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5921 entry->location = (conn & 0x01e00000) >> 21;
5922 entry->bus = (conn & 0x0e000000) >> 25;
5923 entry->duallink_possible = false;
5925 switch (entry->type) {
5927 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5930 entry->tvconf.has_component_output = false;
5933 if ((conn & 0x00003f00) >> 8 != 0x10)
5934 entry->lvdsconf.use_straps_for_mode = true;
5935 entry->lvdsconf.use_power_scripts = true;
5945 void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
5948 * DCB v2.0 lists each output combination separately.
5949 * Here we merge compatible entries to have fewer outputs, with
5953 int i, newentries = 0;
5955 for (i = 0; i < dcb->entries; i++) {
5956 struct dcb_entry *ient = &dcb->entry[i];
5959 for (j = i + 1; j < dcb->entries; j++) {
5960 struct dcb_entry *jent = &dcb->entry[j];
5962 if (jent->type == 100) /* already merged entry */
5965 /* merge heads field when all other fields the same */
5966 if (jent->i2c_index == ient->i2c_index &&
5967 jent->type == ient->type &&
5968 jent->location == ient->location &&
5969 jent->or == ient->or) {
5970 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5972 ient->heads |= jent->heads;
5973 jent->type = 100; /* dummy value */
5978 /* Compact entries merged into others out of dcb */
5979 for (i = 0; i < dcb->entries; i++) {
5980 if (dcb->entry[i].type == 100)
5983 if (newentries != i) {
5984 dcb->entry[newentries] = dcb->entry[i];
5985 dcb->entry[newentries].index = newentries;
5990 dcb->entries = newentries;
5994 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
5996 struct drm_nouveau_private *dev_priv = dev->dev_private;
5997 struct dcb_table *dcb = &dev_priv->vbios.dcb;
5999 /* Dell Precision M6300
6000 * DCB entry 2: 02025312 00000010
6001 * DCB entry 3: 02026312 00000020
6003 * Identical, except apparently a different connector on a
6004 * different SOR link. Not a clue how we're supposed to know
6005 * which one is in use if it even shares an i2c line...
6007 * Ignore the connector on the second SOR link to prevent
6008 * nasty problems until this is sorted (assuming it's not a
6011 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
6012 if (*conn == 0x02026312 && *conf == 0x00000020)
6018 * DCB reports an LVDS output that should be TMDS:
6019 * DCB entry 1: f2005014 ffffffff
6021 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6022 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6023 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6030 * So many things wrong here, replace the entire encoder table..
6032 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6034 *conn = 0x02001300; /* VGA, connector 1 */
6038 *conn = 0x01010312; /* DVI, connector 0 */
6042 *conn = 0x01010310; /* VGA, connector 0 */
6046 *conn = 0x02022362; /* HDMI, connector 2 */
6049 *conn = 0x0000000e; /* EOL */
6054 /* Some other twisted XFX board (rhbz#694914)
6056 * The DVI/VGA encoder combo that's supposed to represent the
6057 * DVI-I connector actually point at two different ones, and
6058 * the HDMI connector ends up paired with the VGA instead.
6060 * Connector table is missing anything for VGA at all, pointing it
6061 * an invalid conntab entry 2 so we figure it out ourself.
6063 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6065 *conn = 0x02002300; /* VGA, connector 2 */
6069 *conn = 0x01010312; /* DVI, connector 0 */
6073 *conn = 0x04020310; /* VGA, connector 0 */
6077 *conn = 0x02021322; /* HDMI, connector 1 */
6080 *conn = 0x0000000e; /* EOL */
6089 fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6091 struct dcb_table *dcb = &bios->dcb;
6092 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6095 /* Apple iMac G4 NV17 */
6096 if (of_machine_is_compatible("PowerMac4,5")) {
6097 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6098 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6103 /* Make up some sane defaults */
6104 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
6105 bios->legacy.i2c_indices.crt, 1, 1);
6107 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6108 fabricate_dcb_output(dcb, OUTPUT_TV,
6109 bios->legacy.i2c_indices.tv,
6112 else if (bios->tmds.output0_script_ptr ||
6113 bios->tmds.output1_script_ptr)
6114 fabricate_dcb_output(dcb, OUTPUT_TMDS,
6115 bios->legacy.i2c_indices.panel,
6120 parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
6122 struct drm_nouveau_private *dev_priv = dev->dev_private;
6123 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6124 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
6125 u32 conn = ROM32(outp[0]);
6128 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
6129 struct dcb_entry *entry = new_dcb_entry(dcb);
6131 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
6133 if (dcb->version >= 0x20)
6134 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6136 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6138 return 1; /* stop parsing */
6140 /* Ignore the I2C index for on-chip TV-out, as there
6141 * are cards with bogus values (nv31m in bug 23212),
6142 * and it's otherwise useless.
6144 if (entry->type == OUTPUT_TV &&
6145 entry->location == DCB_LOC_ON_CHIP)
6146 entry->i2c_index = 0x0f;
6153 dcb_fake_connectors(struct nvbios *bios)
6155 struct dcb_table *dcbt = &bios->dcb;
6159 /* heuristic: if we ever get a non-zero connector field, assume
6160 * that all the indices are valid and we don't need fake them.
6162 for (i = 0; i < dcbt->entries; i++) {
6163 if (dcbt->entry[i].connector)
6167 /* no useful connector info available, we need to make it up
6168 * ourselves. the rule here is: anything on the same i2c bus
6169 * is considered to be on the same connector. any output
6170 * without an associated i2c bus is assigned its own unique
6173 for (i = 0; i < dcbt->entries; i++) {
6174 u8 i2c = dcbt->entry[i].i2c_index;
6176 dcbt->entry[i].connector = idx++;
6180 dcbt->entry[i].connector = map[i2c] - 1;
6184 /* if we created more than one connector, destroy the connector
6185 * table - just in case it has random, rather than stub, entries.
6188 u8 *conntab = dcb_conntab(bios->dev);
6195 parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6197 struct dcb_table *dcb = &bios->dcb;
6201 dcbt = dcb_table(dev);
6203 /* handle pre-DCB boards */
6204 if (bios->type == NVBIOS_BMP) {
6205 fabricate_dcb_encoder_table(dev, bios);
6212 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
6214 dcb->version = dcbt[0];
6215 dcb_outp_foreach(dev, NULL, parse_dcb_entry);
6218 * apart for v2.1+ not being known for requiring merging, this
6219 * guarantees dcbent->index is the index of the entry in the rom image
6221 if (dcb->version < 0x21)
6222 merge_like_dcb_entries(dev, dcb);
6227 /* dump connector table entries to log, if any exist */
6229 while ((conn = dcb_conn(dev, ++idx))) {
6230 if (conn[0] != 0xff) {
6231 NV_TRACE(dev, "DCB conn %02d: ", idx);
6232 if (dcb_conntab(dev)[3] < 4)
6233 printk("%04x\n", ROM16(conn[0]));
6235 printk("%08x\n", ROM32(conn[0]));
6238 dcb_fake_connectors(bios);
6242 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6245 * The header following the "HWSQ" signature has the number of entries,
6246 * and the entry size
6248 * An entry consists of a dword to write to the sequencer control reg
6249 * (0x00001304), followed by the ucode bytes, written sequentially,
6250 * starting at reg 0x00001400
6253 uint8_t bytes_to_write;
6254 uint16_t hwsq_entry_offset;
6257 if (bios->data[hwsq_offset] <= entry) {
6258 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6259 "requested entry\n");
6263 bytes_to_write = bios->data[hwsq_offset + 1];
6265 if (bytes_to_write != 36) {
6266 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6270 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6272 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6274 /* set sequencer control */
6275 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6276 bytes_to_write -= 4;
6279 for (i = 0; i < bytes_to_write; i += 4)
6280 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6282 /* twiddle NV_PBUS_DEBUG_4 */
6283 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6288 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6289 struct nvbios *bios)
6292 * BMP based cards, from NV17, need a microcode loading to correctly
6293 * control the GPIO etc for LVDS panels
6295 * BIT based cards seem to do this directly in the init scripts
6297 * The microcode entries are found by the "HWSQ" signature.
6300 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6301 const int sz = sizeof(hwsq_signature);
6304 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6308 /* always use entry 0? */
6309 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6312 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6314 struct drm_nouveau_private *dev_priv = dev->dev_private;
6315 struct nvbios *bios = &dev_priv->vbios;
6316 const uint8_t edid_sig[] = {
6317 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6318 uint16_t offset = 0;
6320 int searchlen = NV_PROM_SIZE;
6323 return bios->fp.edid;
6326 newoffset = findstr(&bios->data[offset], searchlen,
6330 offset += newoffset;
6331 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6334 searchlen -= offset;
6338 NV_TRACE(dev, "Found EDID in BIOS\n");
6340 return bios->fp.edid = &bios->data[offset];
6344 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6345 struct dcb_entry *dcbent, int crtc)
6347 struct drm_nouveau_private *dev_priv = dev->dev_private;
6348 struct nvbios *bios = &dev_priv->vbios;
6349 struct init_exec iexec = { true, false };
6351 spin_lock_bh(&bios->lock);
6352 bios->display.output = dcbent;
6353 bios->display.crtc = crtc;
6354 parse_init_table(bios, table, &iexec);
6355 bios->display.output = NULL;
6356 spin_unlock_bh(&bios->lock);
6360 nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6362 struct drm_nouveau_private *dev_priv = dev->dev_private;
6363 struct nvbios *bios = &dev_priv->vbios;
6364 struct init_exec iexec = { true, false };
6366 parse_init_table(bios, table, &iexec);
6369 static bool NVInitVBIOS(struct drm_device *dev)
6371 struct drm_nouveau_private *dev_priv = dev->dev_private;
6372 struct nvbios *bios = &dev_priv->vbios;
6374 memset(bios, 0, sizeof(struct nvbios));
6375 spin_lock_init(&bios->lock);
6378 return bios_shadow(dev);
6381 static int nouveau_parse_vbios_struct(struct drm_device *dev)
6383 struct drm_nouveau_private *dev_priv = dev->dev_private;
6384 struct nvbios *bios = &dev_priv->vbios;
6385 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6386 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6389 offset = findstr(bios->data, bios->length,
6390 bit_signature, sizeof(bit_signature));
6392 NV_TRACE(dev, "BIT BIOS found\n");
6393 bios->type = NVBIOS_BIT;
6394 bios->offset = offset;
6395 return parse_bit_structure(bios, offset + 6);
6398 offset = findstr(bios->data, bios->length,
6399 bmp_signature, sizeof(bmp_signature));
6401 NV_TRACE(dev, "BMP BIOS found\n");
6402 bios->type = NVBIOS_BMP;
6403 bios->offset = offset;
6404 return parse_bmp_structure(dev, bios, offset);
6407 NV_ERROR(dev, "No known BIOS signature found\n");
6412 nouveau_run_vbios_init(struct drm_device *dev)
6414 struct drm_nouveau_private *dev_priv = dev->dev_private;
6415 struct nvbios *bios = &dev_priv->vbios;
6418 /* Reset the BIOS head to 0. */
6419 bios->state.crtchead = 0;
6421 if (bios->major_version < 5) /* BMP only */
6422 load_nv17_hw_sequencer_ucode(dev, bios);
6424 if (bios->execute) {
6425 bios->fp.last_script_invoc = 0;
6426 bios->fp.lvds_init_run = false;
6429 parse_init_tables(bios);
6432 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6433 * parser will run this right after the init tables, the binary
6434 * driver appears to run it at some point later.
6436 if (bios->some_script_ptr) {
6437 struct init_exec iexec = {true, false};
6439 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6440 bios->some_script_ptr);
6441 parse_init_table(bios, bios->some_script_ptr, &iexec);
6444 if (dev_priv->card_type >= NV_50) {
6445 for (i = 0; i < bios->dcb.entries; i++) {
6446 nouveau_bios_run_display_table(dev, 0, 0,
6447 &bios->dcb.entry[i], -1);
6455 nouveau_bios_posted(struct drm_device *dev)
6457 struct drm_nouveau_private *dev_priv = dev->dev_private;
6460 if (dev_priv->card_type >= NV_50) {
6461 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6462 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6467 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6468 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6469 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6470 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6471 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6473 return (htotal != 0);
6477 nouveau_bios_init(struct drm_device *dev)
6479 struct drm_nouveau_private *dev_priv = dev->dev_private;
6480 struct nvbios *bios = &dev_priv->vbios;
6483 if (!NVInitVBIOS(dev))
6486 ret = nouveau_parse_vbios_struct(dev);
6490 ret = nouveau_i2c_init(dev);
6494 ret = nouveau_mxm_init(dev);
6498 ret = parse_dcb_table(dev, bios);
6502 if (!bios->major_version) /* we don't run version 0 bios */
6505 /* init script execution disabled */
6506 bios->execute = false;
6508 /* ... unless card isn't POSTed already */
6509 if (!nouveau_bios_posted(dev)) {
6510 NV_INFO(dev, "Adaptor not initialised, "
6511 "running VBIOS init tables.\n");
6512 bios->execute = true;
6514 if (nouveau_force_post)
6515 bios->execute = true;
6517 ret = nouveau_run_vbios_init(dev);
6521 /* feature_byte on BMP is poor, but init always sets CR4B */
6522 if (bios->major_version < 5)
6523 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6525 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6526 if (bios->is_mobile || bios->major_version >= 5)
6527 ret = parse_fp_mode_table(dev, bios);
6529 /* allow subsequent scripts to execute */
6530 bios->execute = true;
6536 nouveau_bios_takedown(struct drm_device *dev)
6538 struct drm_nouveau_private *dev_priv = dev->dev_private;
6540 nouveau_mxm_fini(dev);
6541 nouveau_i2c_fini(dev);
6543 kfree(dev_priv->vbios.data);