drivers/gpu/drm/i915/intel_sdvo.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2007 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  */
  28 #include <linux/i2c.h>
  29 #include <linux/delay.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "intel_sdvo_regs.h"
  37
  38 #undef SDVO_DEBUG
  39
  40 struct intel_sdvo_priv {
  41         struct intel_i2c_chan *i2c_bus;
  42         int slaveaddr;
  43
  44         /* Register for the SDVO device: SDVOB or SDVOC */
  45         int output_device;
  46
  47         /* Active outputs controlled by this SDVO output */
  48         uint16_t controlled_output;
  49
  50         /*
  51          * Capabilities of the SDVO device returned by
  52          * i830_sdvo_get_capabilities()
  53          */
  54         struct intel_sdvo_caps caps;
  55
  56         /* Pixel clock limitations reported by the SDVO device, in kHz */
  57         int pixel_clock_min, pixel_clock_max;
  58
  59         /**
  60          * This is set if we're going to treat the device as TV-out.
  61          *
  62          * While we have these nice friendly flags for output types that ought
  63          * to decide this for us, the S-Video output on our HDMI+S-Video card
  64          * shows up as RGB1 (VGA).
  65          */
  66         bool is_tv;
  67
  68         /**
  69          * This is set if we treat the device as HDMI, instead of DVI.
  70          */
  71         bool is_hdmi;
  72
  73         /**
  74          * Returned SDTV resolutions allowed for the current format, if the
  75          * device reported it.
  76          */
  77         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  78
  79         /**
  80          * Current selected TV format.
  81          *
  82          * This is stored in the same structure that's passed to the device, for
  83          * convenience.
  84          */
  85         struct intel_sdvo_tv_format tv_format;
  86
  87         /*
  88          * supported encoding mode, used to determine whether HDMI is
  89          * supported
  90          */
  91         struct intel_sdvo_encode encode;
  92
  93         /* DDC bus used by this SDVO output */
  94         uint8_t ddc_bus;
  95
  96         int save_sdvo_mult;
  97         u16 save_active_outputs;
  98         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
  99         struct intel_sdvo_dtd save_output_dtd[16];
 100         u32 save_SDVOX;
 101 };
 102
 103 /**
 104  * Writes the SDVOB or SDVOC with the given value, but always writes both
 105  * SDVOB and SDVOC to work around apparent hardware issues (according to
 106  * comments in the BIOS).
 107  */
 108 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
 109 {
 110         struct drm_device *dev = intel_output->base.dev;
 111         struct drm_i915_private *dev_priv = dev->dev_private;
 112         struct intel_sdvo_priv   *sdvo_priv = intel_output->dev_priv;
 113         u32 bval = val, cval = val;
 114         int i;
 115
 116         if (sdvo_priv->output_device == SDVOB) {
 117                 cval = I915_READ(SDVOC);
 118         } else {
 119                 bval = I915_READ(SDVOB);
 120         }
 121         /*
 122          * Write the registers twice for luck. Sometimes,
 123          * writing them only once doesn't appear to 'stick'.
 124          * The BIOS does this too. Yay, magic
 125          */
 126         for (i = 0; i < 2; i++)
 127         {
 128                 I915_WRITE(SDVOB, bval);
 129                 I915_READ(SDVOB);
 130                 I915_WRITE(SDVOC, cval);
 131                 I915_READ(SDVOC);
 132         }
 133 }
 134
 135 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
 136                                  u8 *ch)
 137 {
 138         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 139         u8 out_buf[2];
 140         u8 buf[2];
 141         int ret;
 142
 143         struct i2c_msg msgs[] = {
 144                 {
 145                         .addr = sdvo_priv->i2c_bus->slave_addr,
 146                         .flags = 0,
 147                         .len = 1,
 148                         .buf = out_buf,
 149                 },
 150                 {
 151                         .addr = sdvo_priv->i2c_bus->slave_addr,
 152                         .flags = I2C_M_RD,
 153                         .len = 1,
 154                         .buf = buf,
 155                 }
 156         };
 157
 158         out_buf[0] = addr;
 159         out_buf[1] = 0;
 160
 161         if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
 162         {
 163                 *ch = buf[0];
 164                 return true;
 165         }
 166
 167         DRM_DEBUG("i2c transfer returned %d\n", ret);
 168         return false;
 169 }
 170
 171 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
 172                                   u8 ch)
 173 {
 174         u8 out_buf[2];
 175         struct i2c_msg msgs[] = {
 176                 {
 177                         .addr = intel_output->i2c_bus->slave_addr,
 178                         .flags = 0,
 179                         .len = 2,
 180                         .buf = out_buf,
 181                 }
 182         };
 183
 184         out_buf[0] = addr;
 185         out_buf[1] = ch;
 186
 187         if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
 188         {
 189                 return true;
 190         }
 191         return false;
 192 }
 193
 194 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
 195 /** Mapping of command numbers to names, for debug output */
 196 static const struct _sdvo_cmd_name {
 197         u8 cmd;
 198         char *name;
 199 } sdvo_cmd_names[] = {
 200     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
 201     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
 202     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
 203     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
 204     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
 205     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
 206     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
 207     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
 208     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
 209     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
 210     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
 211     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
 212     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
 213     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
 214     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
 215     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
 216     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
 217     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 218     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
 219     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
 220     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
 221     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
 222     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
 223     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
 224     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
 225     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
 226     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
 227     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
 228     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
 229     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
 230     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
 231     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
 232     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
 233     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
 234     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
 235     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
 236     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
 237     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
 238     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
 239     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
 240     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
 241     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 242     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
 243     /* HDMI op code */
 244     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
 245     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
 246     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
 247     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
 248     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
 249     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
 250     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
 251     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
 252     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
 253     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
 254     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
 255     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
 256     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
 257     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
 258     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
 259     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
 260     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
 261     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
 262     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
 263     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
 264 };
 265
 266 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
 267 #define SDVO_PRIV(output)   ((struct intel_sdvo_priv *) (output)->dev_priv)
 268
 269 #ifdef SDVO_DEBUG
 270 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
 271                                    void *args, int args_len)
 272 {
 273         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 274         int i;
 275
 276         printk(KERN_DEBUG "%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
 277         for (i = 0; i < args_len; i++)
 278                 printk(KERN_DEBUG "%02X ", ((u8 *)args)[i]);
 279         for (; i < 8; i++)
 280                 printk(KERN_DEBUG "   ");
 281         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
 282                 if (cmd == sdvo_cmd_names[i].cmd) {
 283                         printk(KERN_DEBUG "(%s)", sdvo_cmd_names[i].name);
 284                         break;
 285                 }
 286         }
 287         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
 288                 printk(KERN_DEBUG "(%02X)", cmd);
 289         printk(KERN_DEBUG "\n");
 290 }
 291 #else
 292 #define intel_sdvo_debug_write(o, c, a, l)
 293 #endif
 294
 295 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
 296                                  void *args, int args_len)
 297 {
 298         int i;
 299
 300         intel_sdvo_debug_write(intel_output, cmd, args, args_len);
 301
 302         for (i = 0; i < args_len; i++) {
 303                 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
 304                                       ((u8*)args)[i]);
 305         }
 306
 307         intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
 308 }
 309
 310 #ifdef SDVO_DEBUG
 311 static const char *cmd_status_names[] = {
 312         "Power on",
 313         "Success",
 314         "Not supported",
 315         "Invalid arg",
 316         "Pending",
 317         "Target not specified",
 318         "Scaling not supported"
 319 };
 320
 321 static void intel_sdvo_debug_response(struct intel_output *intel_output,
 322                                       void *response, int response_len,
 323                                       u8 status)
 324 {
 325         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 326         int i;
 327
 328         printk(KERN_DEBUG "%s: R: ", SDVO_NAME(sdvo_priv));
 329         for (i = 0; i < response_len; i++)
 330                 printk(KERN_DEBUG "%02X ", ((u8 *)response)[i]);
 331         for (; i < 8; i++)
 332                 printk(KERN_DEBUG "   ");
 333         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
 334                 printk(KERN_DEBUG "(%s)", cmd_status_names[status]);
 335         else
 336                 printk(KERN_DEBUG "(??? %d)", status);
 337         printk(KERN_DEBUG "\n");
 338 }
 339 #else
 340 #define intel_sdvo_debug_response(o, r, l, s)
 341 #endif
 342
 343 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
 344                                    void *response, int response_len)
 345 {
 346         int i;
 347         u8 status;
 348         u8 retry = 50;
 349
 350         while (retry--) {
 351                 /* Read the command response */
 352                 for (i = 0; i < response_len; i++) {
 353                         intel_sdvo_read_byte(intel_output,
 354                                              SDVO_I2C_RETURN_0 + i,
 355                                              &((u8 *)response)[i]);
 356                 }
 357
 358                 /* read the return status */
 359                 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
 360                                      &status);
 361
 362                 intel_sdvo_debug_response(intel_output, response, response_len,
 363                                           status);
 364                 if (status != SDVO_CMD_STATUS_PENDING)
 365                         return status;
 366
 367                 mdelay(50);
 368         }
 369
 370         return status;
 371 }
 372
 373 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
 374 {
 375         if (mode->clock >= 100000)
 376                 return 1;
 377         else if (mode->clock >= 50000)
 378                 return 2;
 379         else
 380                 return 4;
 381 }
 382
 383 /**
 384  * Don't check status code from this as it switches the bus back to the
 385  * SDVO chips which defeats the purpose of doing a bus switch in the first
 386  * place.
 387  */
 388 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
 389                                               u8 target)
 390 {
 391         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
 392 }
 393
 394 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
 395 {
 396         struct intel_sdvo_set_target_input_args targets = {0};
 397         u8 status;
 398
 399         if (target_0 && target_1)
 400                 return SDVO_CMD_STATUS_NOTSUPP;
 401
 402         if (target_1)
 403                 targets.target_1 = 1;
 404
 405         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
 406                              sizeof(targets));
 407
 408         status = intel_sdvo_read_response(intel_output, NULL, 0);
 409
 410         return (status == SDVO_CMD_STATUS_SUCCESS);
 411 }
 412
 413 /**
 414  * Return whether each input is trained.
 415  *
 416  * This function is making an assumption about the layout of the response,
 417  * which should be checked against the docs.
 418  */
 419 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
 420 {
 421         struct intel_sdvo_get_trained_inputs_response response;
 422         u8 status;
 423
 424         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
 425         status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
 426         if (status != SDVO_CMD_STATUS_SUCCESS)
 427                 return false;
 428
 429         *input_1 = response.input0_trained;
 430         *input_2 = response.input1_trained;
 431         return true;
 432 }
 433
 434 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
 435                                           u16 *outputs)
 436 {
 437         u8 status;
 438
 439         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
 440         status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
 441
 442         return (status == SDVO_CMD_STATUS_SUCCESS);
 443 }
 444
 445 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
 446                                           u16 outputs)
 447 {
 448         u8 status;
 449
 450         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
 451                              sizeof(outputs));
 452         status = intel_sdvo_read_response(intel_output, NULL, 0);
 453         return (status == SDVO_CMD_STATUS_SUCCESS);
 454 }
 455
 456 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
 457                                                int mode)
 458 {
 459         u8 status, state = SDVO_ENCODER_STATE_ON;
 460
 461         switch (mode) {
 462         case DRM_MODE_DPMS_ON:
 463                 state = SDVO_ENCODER_STATE_ON;
 464                 break;
 465         case DRM_MODE_DPMS_STANDBY:
 466                 state = SDVO_ENCODER_STATE_STANDBY;
 467                 break;
 468         case DRM_MODE_DPMS_SUSPEND:
 469                 state = SDVO_ENCODER_STATE_SUSPEND;
 470                 break;
 471         case DRM_MODE_DPMS_OFF:
 472                 state = SDVO_ENCODER_STATE_OFF;
 473                 break;
 474         }
 475
 476         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
 477                              sizeof(state));
 478         status = intel_sdvo_read_response(intel_output, NULL, 0);
 479
 480         return (status == SDVO_CMD_STATUS_SUCCESS);
 481 }
 482
 483 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
 484                                                    int *clock_min,
 485                                                    int *clock_max)
 486 {
 487         struct intel_sdvo_pixel_clock_range clocks;
 488         u8 status;
 489
 490         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
 491                              NULL, 0);
 492
 493         status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
 494
 495         if (status != SDVO_CMD_STATUS_SUCCESS)
 496                 return false;
 497
 498         /* Convert the values from units of 10 kHz to kHz. */
 499         *clock_min = clocks.min * 10;
 500         *clock_max = clocks.max * 10;
 501
 502         return true;
 503 }
 504
 505 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
 506                                          u16 outputs)
 507 {
 508         u8 status;
 509
 510         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
 511                              sizeof(outputs));
 512
 513         status = intel_sdvo_read_response(intel_output, NULL, 0);
 514         return (status == SDVO_CMD_STATUS_SUCCESS);
 515 }
 516
 517 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
 518                                   struct intel_sdvo_dtd *dtd)
 519 {
 520         u8 status;
 521
 522         intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
 523         status = intel_sdvo_read_response(intel_output, &dtd->part1,
 524                                           sizeof(dtd->part1));
 525         if (status != SDVO_CMD_STATUS_SUCCESS)
 526                 return false;
 527
 528         intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
 529         status = intel_sdvo_read_response(intel_output, &dtd->part2,
 530                                           sizeof(dtd->part2));
 531         if (status != SDVO_CMD_STATUS_SUCCESS)
 532                 return false;
 533
 534         return true;
 535 }
 536
 537 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
 538                                          struct intel_sdvo_dtd *dtd)
 539 {
 540         return intel_sdvo_get_timing(intel_output,
 541                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 542 }
 543
 544 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
 545                                          struct intel_sdvo_dtd *dtd)
 546 {
 547         return intel_sdvo_get_timing(intel_output,
 548                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
 549 }
 550
 551 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
 552                                   struct intel_sdvo_dtd *dtd)
 553 {
 554         u8 status;
 555
 556         intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
 557         status = intel_sdvo_read_response(intel_output, NULL, 0);
 558         if (status != SDVO_CMD_STATUS_SUCCESS)
 559                 return false;
 560
 561         intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 562         status = intel_sdvo_read_response(intel_output, NULL, 0);
 563         if (status != SDVO_CMD_STATUS_SUCCESS)
 564                 return false;
 565
 566         return true;
 567 }
 568
 569 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
 570                                          struct intel_sdvo_dtd *dtd)
 571 {
 572         return intel_sdvo_set_timing(intel_output,
 573                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
 574 }
 575
 576 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
 577                                          struct intel_sdvo_dtd *dtd)
 578 {
 579         return intel_sdvo_set_timing(intel_output,
 580                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
 581 }
 582
 583 static bool
 584 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
 585                                          uint16_t clock,
 586                                          uint16_t width,
 587                                          uint16_t height)
 588 {
 589         struct intel_sdvo_preferred_input_timing_args args;
 590         uint8_t status;
 591
 592         memset(&args, 0, sizeof(args));
 593         args.clock = clock;
 594         args.width = width;
 595         args.height = height;
 596         args.interlace = 0;
 597         args.scaled = 0;
 598         intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
 599                              &args, sizeof(args));
 600         status = intel_sdvo_read_response(output, NULL, 0);
 601         if (status != SDVO_CMD_STATUS_SUCCESS)
 602                 return false;
 603
 604         return true;
 605 }
 606
 607 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
 608                                                   struct intel_sdvo_dtd *dtd)
 609 {
 610         bool status;
 611
 612         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
 613                              NULL, 0);
 614
 615         status = intel_sdvo_read_response(output, &dtd->part1,
 616                                           sizeof(dtd->part1));
 617         if (status != SDVO_CMD_STATUS_SUCCESS)
 618                 return false;
 619
 620         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
 621                              NULL, 0);
 622
 623         status = intel_sdvo_read_response(output, &dtd->part2,
 624                                           sizeof(dtd->part2));
 625         if (status != SDVO_CMD_STATUS_SUCCESS)
 626                 return false;
 627
 628         return false;
 629 }
 630
 631 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
 632 {
 633         u8 response, status;
 634
 635         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
 636         status = intel_sdvo_read_response(intel_output, &response, 1);
 637
 638         if (status != SDVO_CMD_STATUS_SUCCESS) {
 639                 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
 640                 return SDVO_CLOCK_RATE_MULT_1X;
 641         } else {
 642                 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
 643         }
 644
 645         return response;
 646 }
 647
 648 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
 649 {
 650         u8 status;
 651
 652         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
 653         status = intel_sdvo_read_response(intel_output, NULL, 0);
 654         if (status != SDVO_CMD_STATUS_SUCCESS)
 655                 return false;
 656
 657         return true;
 658 }
 659
 660 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
 661                                          struct drm_display_mode *mode)
 662 {
 663         uint16_t width, height;
 664         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
 665         uint16_t h_sync_offset, v_sync_offset;
 666
 667         width = mode->crtc_hdisplay;
 668         height = mode->crtc_vdisplay;
 669
 670         /* do some mode translations */
 671         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
 672         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 673
 674         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
 675         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 676
 677         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
 678         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 679
 680         dtd->part1.clock = mode->clock / 10;
 681         dtd->part1.h_active = width & 0xff;
 682         dtd->part1.h_blank = h_blank_len & 0xff;
 683         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
 684                 ((h_blank_len >> 8) & 0xf);
 685         dtd->part1.v_active = height & 0xff;
 686         dtd->part1.v_blank = v_blank_len & 0xff;
 687         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
 688                 ((v_blank_len >> 8) & 0xf);
 689
 690         dtd->part2.h_sync_off = h_sync_offset & 0xff;
 691         dtd->part2.h_sync_width = h_sync_len & 0xff;
 692         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
 693                 (v_sync_len & 0xf);
 694         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
 695                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
 696                 ((v_sync_len & 0x30) >> 4);
 697
 698         dtd->part2.dtd_flags = 0x18;
 699         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 700                 dtd->part2.dtd_flags |= 0x2;
 701         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 702                 dtd->part2.dtd_flags |= 0x4;
 703
 704         dtd->part2.sdvo_flags = 0;
 705         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
 706         dtd->part2.reserved = 0;
 707 }
 708
 709 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
 710                                          struct intel_sdvo_dtd *dtd)
 711 {
 712         mode->hdisplay = dtd->part1.h_active;
 713         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
 714         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
 715         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
 716         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
 717         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
 718         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
 719         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
 720
 721         mode->vdisplay = dtd->part1.v_active;
 722         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
 723         mode->vsync_start = mode->vdisplay;
 724         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
 725         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
 726         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
 727         mode->vsync_end = mode->vsync_start +
 728                 (dtd->part2.v_sync_off_width & 0xf);
 729         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
 730         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
 731         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
 732
 733         mode->clock = dtd->part1.clock * 10;
 734
 735         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 736         if (dtd->part2.dtd_flags & 0x2)
 737                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
 738         if (dtd->part2.dtd_flags & 0x4)
 739                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
 740 }
 741
 742 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
 743                                        struct intel_sdvo_encode *encode)
 744 {
 745         uint8_t status;
 746
 747         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
 748         status = intel_sdvo_read_response(output, encode, sizeof(*encode));
 749         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
 750                 memset(encode, 0, sizeof(*encode));
 751                 return false;
 752         }
 753
 754         return true;
 755 }
 756
 757 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
 758 {
 759         uint8_t status;
 760
 761         intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
 762         status = intel_sdvo_read_response(output, NULL, 0);
 763
 764         return (status == SDVO_CMD_STATUS_SUCCESS);
 765 }
 766
 767 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
 768                                        uint8_t mode)
 769 {
 770         uint8_t status;
 771
 772         intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
 773         status = intel_sdvo_read_response(output, NULL, 0);
 774
 775         return (status == SDVO_CMD_STATUS_SUCCESS);
 776 }
 777
 778 #if 0
 779 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
 780 {
 781         int i, j;
 782         uint8_t set_buf_index[2];
 783         uint8_t av_split;
 784         uint8_t buf_size;
 785         uint8_t buf[48];
 786         uint8_t *pos;
 787
 788         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
 789         intel_sdvo_read_response(output, &av_split, 1);
 790
 791         for (i = 0; i <= av_split; i++) {
 792                 set_buf_index[0] = i; set_buf_index[1] = 0;
 793                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
 794                                      set_buf_index, 2);
 795                 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
 796                 intel_sdvo_read_response(output, &buf_size, 1);
 797
 798                 pos = buf;
 799                 for (j = 0; j <= buf_size; j += 8) {
 800                         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
 801                                              NULL, 0);
 802                         intel_sdvo_read_response(output, pos, 8);
 803                         pos += 8;
 804                 }
 805         }
 806 }
 807 #endif
 808
 809 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
 810                                 uint8_t *data, int8_t size, uint8_t tx_rate)
 811 {
 812     uint8_t set_buf_index[2];
 813
 814     set_buf_index[0] = index;
 815     set_buf_index[1] = 0;
 816
 817     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
 818
 819     for (; size > 0; size -= 8) {
 820         intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
 821         data += 8;
 822     }
 823
 824     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
 825 }
 826
 827 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
 828 {
 829         uint8_t csum = 0;
 830         int i;
 831
 832         for (i = 0; i < size; i++)
 833                 csum += data[i];
 834
 835         return 0x100 - csum;
 836 }
 837
 838 #define DIP_TYPE_AVI    0x82
 839 #define DIP_VERSION_AVI 0x2
 840 #define DIP_LEN_AVI     13
 841
 842 struct dip_infoframe {
 843         uint8_t type;
 844         uint8_t version;
 845         uint8_t len;
 846         uint8_t checksum;
 847         union {
 848                 struct {
 849                         /* Packet Byte #1 */
 850                         uint8_t S:2;
 851                         uint8_t B:2;
 852                         uint8_t A:1;
 853                         uint8_t Y:2;
 854                         uint8_t rsvd1:1;
 855                         /* Packet Byte #2 */
 856                         uint8_t R:4;
 857                         uint8_t M:2;
 858                         uint8_t C:2;
 859                         /* Packet Byte #3 */
 860                         uint8_t SC:2;
 861                         uint8_t Q:2;
 862                         uint8_t EC:3;
 863                         uint8_t ITC:1;
 864                         /* Packet Byte #4 */
 865                         uint8_t VIC:7;
 866                         uint8_t rsvd2:1;
 867                         /* Packet Byte #5 */
 868                         uint8_t PR:4;
 869                         uint8_t rsvd3:4;
 870                         /* Packet Byte #6~13 */
 871                         uint16_t top_bar_end;
 872                         uint16_t bottom_bar_start;
 873                         uint16_t left_bar_end;
 874                         uint16_t right_bar_start;
 875                 } avi;
 876                 struct {
 877                         /* Packet Byte #1 */
 878                         uint8_t channel_count:3;
 879                         uint8_t rsvd1:1;
 880                         uint8_t coding_type:4;
 881                         /* Packet Byte #2 */
 882                         uint8_t sample_size:2; /* SS0, SS1 */
 883                         uint8_t sample_frequency:3;
 884                         uint8_t rsvd2:3;
 885                         /* Packet Byte #3 */
 886                         uint8_t coding_type_private:5;
 887                         uint8_t rsvd3:3;
 888                         /* Packet Byte #4 */
 889                         uint8_t channel_allocation;
 890                         /* Packet Byte #5 */
 891                         uint8_t rsvd4:3;
 892                         uint8_t level_shift:4;
 893                         uint8_t downmix_inhibit:1;
 894                 } audio;
 895                 uint8_t payload[28];
 896         } __attribute__ ((packed)) u;
 897 } __attribute__((packed));
 898
 899 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
 900                                          struct drm_display_mode * mode)
 901 {
 902         struct dip_infoframe avi_if = {
 903                 .type = DIP_TYPE_AVI,
 904                 .version = DIP_VERSION_AVI,
 905                 .len = DIP_LEN_AVI,
 906         };
 907
 908         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
 909                                                     4 + avi_if.len);
 910         intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
 911                                 SDVO_HBUF_TX_VSYNC);
 912 }
 913
 914 static void intel_sdvo_set_tv_format(struct intel_output *output)
 915 {
 916         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 917         struct intel_sdvo_tv_format *format, unset;
 918         u8 status;
 919
 920         format = &sdvo_priv->tv_format;
 921         memset(&unset, 0, sizeof(unset));
 922         if (memcmp(format, &unset, sizeof(*format))) {
 923                 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
 924                                 SDVO_NAME(sdvo_priv));
 925                 format->ntsc_m = 1;
 926                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
 927                                 sizeof(*format));
 928                 status = intel_sdvo_read_response(output, NULL, 0);
 929                 if (status != SDVO_CMD_STATUS_SUCCESS)
 930                         DRM_DEBUG("%s: Failed to set TV format\n",
 931                                         SDVO_NAME(sdvo_priv));
 932         }
 933 }
 934
 935 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
 936                                   struct drm_display_mode *mode,
 937                                   struct drm_display_mode *adjusted_mode)
 938 {
 939         struct intel_output *output = enc_to_intel_output(encoder);
 940         struct intel_sdvo_priv *dev_priv = output->dev_priv;
 941
 942         if (!dev_priv->is_tv) {
 943                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
 944                  * SDVO device will be told of the multiplier during mode_set.
 945                  */
 946                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
 947         } else {
 948                 struct intel_sdvo_dtd output_dtd;
 949                 bool success;
 950
 951                 /* We need to construct preferred input timings based on our
 952                  * output timings.  To do that, we have to set the output
 953                  * timings, even though this isn't really the right place in
 954                  * the sequence to do it. Oh well.
 955                  */
 956
 957
 958                 /* Set output timings */
 959                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
 960                 intel_sdvo_set_target_output(output,
 961                                              dev_priv->controlled_output);
 962                 intel_sdvo_set_output_timing(output, &output_dtd);
 963
 964                 /* Set the input timing to the screen. Assume always input 0. */
 965                 intel_sdvo_set_target_input(output, true, false);
 966
 967
 968                 success = intel_sdvo_create_preferred_input_timing(output,
 969                                                                    mode->clock / 10,
 970                                                                    mode->hdisplay,
 971                                                                    mode->vdisplay);
 972                 if (success) {
 973                         struct intel_sdvo_dtd input_dtd;
 974
 975                         intel_sdvo_get_preferred_input_timing(output,
 976                                                              &input_dtd);
 977                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
 978
 979                         drm_mode_set_crtcinfo(adjusted_mode, 0);
 980
 981                         mode->clock = adjusted_mode->clock;
 982
 983                         adjusted_mode->clock *=
 984                                 intel_sdvo_get_pixel_multiplier(mode);
 985                 } else {
 986                         return false;
 987                 }
 988         }
 989         return true;
 990 }
 991
 992 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
 993                                 struct drm_display_mode *mode,
 994                                 struct drm_display_mode *adjusted_mode)
 995 {
 996         struct drm_device *dev = encoder->dev;
 997         struct drm_i915_private *dev_priv = dev->dev_private;
 998         struct drm_crtc *crtc = encoder->crtc;
 999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1000         struct intel_output *output = enc_to_intel_output(encoder);
1001         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1002         u32 sdvox = 0;
1003         int sdvo_pixel_multiply;
1004         struct intel_sdvo_in_out_map in_out;
1005         struct intel_sdvo_dtd input_dtd;
1006         u8 status;
1007
1008         if (!mode)
1009                 return;
1010
1011         /* First, set the input mapping for the first input to our controlled
1012          * output. This is only correct if we're a single-input device, in
1013          * which case the first input is the output from the appropriate SDVO
1014          * channel on the motherboard.  In a two-input device, the first input
1015          * will be SDVOB and the second SDVOC.
1016          */
1017         in_out.in0 = sdvo_priv->controlled_output;
1018         in_out.in1 = 0;
1019
1020         intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1021                              &in_out, sizeof(in_out));
1022         status = intel_sdvo_read_response(output, NULL, 0);
1023
1024         if (sdvo_priv->is_hdmi) {
1025                 intel_sdvo_set_avi_infoframe(output, mode);
1026                 sdvox |= SDVO_AUDIO_ENABLE;
1027         }
1028
1029         /* We have tried to get input timing in mode_fixup, and filled into
1030            adjusted_mode */
1031         if (sdvo_priv->is_tv)
1032                 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1033         else
1034                 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1035
1036         /* If it's a TV, we already set the output timing in mode_fixup.
1037          * Otherwise, the output timing is equal to the input timing.
1038          */
1039         if (!sdvo_priv->is_tv) {
1040                 /* Set the output timing to the screen */
1041                 intel_sdvo_set_target_output(output,
1042                                              sdvo_priv->controlled_output);
1043                 intel_sdvo_set_output_timing(output, &input_dtd);
1044         }
1045
1046         /* Set the input timing to the screen. Assume always input 0. */
1047         intel_sdvo_set_target_input(output, true, false);
1048
1049         if (sdvo_priv->is_tv)
1050                 intel_sdvo_set_tv_format(output);
1051
1052         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1053          * provide the device with a timing it can support, if it supports that
1054          * feature.  However, presumably we would need to adjust the CRTC to
1055          * output the preferred timing, and we don't support that currently.
1056          */
1057 #if 0
1058         success = intel_sdvo_create_preferred_input_timing(output, clock,
1059                                                            width, height);
1060         if (success) {
1061                 struct intel_sdvo_dtd *input_dtd;
1062
1063                 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1064                 intel_sdvo_set_input_timing(output, &input_dtd);
1065         }
1066 #else
1067         intel_sdvo_set_input_timing(output, &input_dtd);
1068 #endif
1069
1070         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1071         case 1:
1072                 intel_sdvo_set_clock_rate_mult(output,
1073                                                SDVO_CLOCK_RATE_MULT_1X);
1074                 break;
1075         case 2:
1076                 intel_sdvo_set_clock_rate_mult(output,
1077                                                SDVO_CLOCK_RATE_MULT_2X);
1078                 break;
1079         case 4:
1080                 intel_sdvo_set_clock_rate_mult(output,
1081                                                SDVO_CLOCK_RATE_MULT_4X);
1082                 break;
1083         }
1084
1085         /* Set the SDVO control regs. */
1086         if (IS_I965G(dev)) {
1087                 sdvox |= SDVO_BORDER_ENABLE |
1088                         SDVO_VSYNC_ACTIVE_HIGH |
1089                         SDVO_HSYNC_ACTIVE_HIGH;
1090         } else {
1091                 sdvox |= I915_READ(sdvo_priv->output_device);
1092                 switch (sdvo_priv->output_device) {
1093                 case SDVOB:
1094                         sdvox &= SDVOB_PRESERVE_MASK;
1095                         break;
1096                 case SDVOC:
1097                         sdvox &= SDVOC_PRESERVE_MASK;
1098                         break;
1099                 }
1100                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1101         }
1102         if (intel_crtc->pipe == 1)
1103                 sdvox |= SDVO_PIPE_B_SELECT;
1104
1105         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1106         if (IS_I965G(dev)) {
1107                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1108         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1109                 /* done in crtc_mode_set as it lives inside the dpll register */
1110         } else {
1111                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1112         }
1113
1114         intel_sdvo_write_sdvox(output, sdvox);
1115 }
1116
1117 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1118 {
1119         struct drm_device *dev = encoder->dev;
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         struct intel_output *intel_output = enc_to_intel_output(encoder);
1122         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1123         u32 temp;
1124
1125         if (mode != DRM_MODE_DPMS_ON) {
1126                 intel_sdvo_set_active_outputs(intel_output, 0);
1127                 if (0)
1128                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1129
1130                 if (mode == DRM_MODE_DPMS_OFF) {
1131                         temp = I915_READ(sdvo_priv->output_device);
1132                         if ((temp & SDVO_ENABLE) != 0) {
1133                                 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1134                         }
1135                 }
1136         } else {
1137                 bool input1, input2;
1138                 int i;
1139                 u8 status;
1140
1141                 temp = I915_READ(sdvo_priv->output_device);
1142                 if ((temp & SDVO_ENABLE) == 0)
1143                         intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1144                 for (i = 0; i < 2; i++)
1145                   intel_wait_for_vblank(dev);
1146
1147                 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1148                                                        &input2);
1149
1150
1151                 /* Warn if the device reported failure to sync.
1152                  * A lot of SDVO devices fail to notify of sync, but it's
1153                  * a given it the status is a success, we succeeded.
1154                  */
1155                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1156                         DRM_DEBUG("First %s output reported failure to sync\n",
1157                                    SDVO_NAME(sdvo_priv));
1158                 }
1159
1160                 if (0)
1161                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1162                 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1163         }
1164         return;
1165 }
1166
1167 static void intel_sdvo_save(struct drm_connector *connector)
1168 {
1169         struct drm_device *dev = connector->dev;
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171         struct intel_output *intel_output = to_intel_output(connector);
1172         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1173         int o;
1174
1175         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1176         intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1177
1178         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1179                 intel_sdvo_set_target_input(intel_output, true, false);
1180                 intel_sdvo_get_input_timing(intel_output,
1181                                             &sdvo_priv->save_input_dtd_1);
1182         }
1183
1184         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1185                 intel_sdvo_set_target_input(intel_output, false, true);
1186                 intel_sdvo_get_input_timing(intel_output,
1187                                             &sdvo_priv->save_input_dtd_2);
1188         }
1189
1190         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1191         {
1192                 u16  this_output = (1 << o);
1193                 if (sdvo_priv->caps.output_flags & this_output)
1194                 {
1195                         intel_sdvo_set_target_output(intel_output, this_output);
1196                         intel_sdvo_get_output_timing(intel_output,
1197                                                      &sdvo_priv->save_output_dtd[o]);
1198                 }
1199         }
1200         if (sdvo_priv->is_tv) {
1201                 /* XXX: Save TV format/enhancements. */
1202         }
1203
1204         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1205 }
1206
1207 static void intel_sdvo_restore(struct drm_connector *connector)
1208 {
1209         struct drm_device *dev = connector->dev;
1210         struct intel_output *intel_output = to_intel_output(connector);
1211         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1212         int o;
1213         int i;
1214         bool input1, input2;
1215         u8 status;
1216
1217         intel_sdvo_set_active_outputs(intel_output, 0);
1218
1219         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1220         {
1221                 u16  this_output = (1 << o);
1222                 if (sdvo_priv->caps.output_flags & this_output) {
1223                         intel_sdvo_set_target_output(intel_output, this_output);
1224                         intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1225                 }
1226         }
1227
1228         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1229                 intel_sdvo_set_target_input(intel_output, true, false);
1230                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1231         }
1232
1233         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1234                 intel_sdvo_set_target_input(intel_output, false, true);
1235                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1236         }
1237
1238         intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1239
1240         if (sdvo_priv->is_tv) {
1241                 /* XXX: Restore TV format/enhancements. */
1242         }
1243
1244         intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1245
1246         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1247         {
1248                 for (i = 0; i < 2; i++)
1249                         intel_wait_for_vblank(dev);
1250                 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1251                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1252                         DRM_DEBUG("First %s output reported failure to sync\n",
1253                                    SDVO_NAME(sdvo_priv));
1254         }
1255
1256         intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1257 }
1258
1259 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1260                                  struct drm_display_mode *mode)
1261 {
1262         struct intel_output *intel_output = to_intel_output(connector);
1263         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1264
1265         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1266                 return MODE_NO_DBLESCAN;
1267
1268         if (sdvo_priv->pixel_clock_min > mode->clock)
1269                 return MODE_CLOCK_LOW;
1270
1271         if (sdvo_priv->pixel_clock_max < mode->clock)
1272                 return MODE_CLOCK_HIGH;
1273
1274         return MODE_OK;
1275 }
1276
1277 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1278 {
1279         u8 status;
1280
1281         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1282         status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1283         if (status != SDVO_CMD_STATUS_SUCCESS)
1284                 return false;
1285
1286         return true;
1287 }
1288
1289 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1290 {
1291         struct drm_connector *connector = NULL;
1292         struct intel_output *iout = NULL;
1293         struct intel_sdvo_priv *sdvo;
1294
1295         /* find the sdvo connector */
1296         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1297                 iout = to_intel_output(connector);
1298
1299                 if (iout->type != INTEL_OUTPUT_SDVO)
1300                         continue;
1301
1302                 sdvo = iout->dev_priv;
1303
1304                 if (sdvo->output_device == SDVOB && sdvoB)
1305                         return connector;
1306
1307                 if (sdvo->output_device == SDVOC && !sdvoB)
1308                         return connector;
1309
1310         }
1311
1312         return NULL;
1313 }
1314
1315 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1316 {
1317         u8 response[2];
1318         u8 status;
1319         struct intel_output *intel_output;
1320         DRM_DEBUG("\n");
1321
1322         if (!connector)
1323                 return 0;
1324
1325         intel_output = to_intel_output(connector);
1326
1327         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1328         status = intel_sdvo_read_response(intel_output, &response, 2);
1329
1330         if (response[0] !=0)
1331                 return 1;
1332
1333         return 0;
1334 }
1335
1336 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1337 {
1338         u8 response[2];
1339         u8 status;
1340         struct intel_output *intel_output = to_intel_output(connector);
1341
1342         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1343         intel_sdvo_read_response(intel_output, &response, 2);
1344
1345         if (on) {
1346                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1347                 status = intel_sdvo_read_response(intel_output, &response, 2);
1348
1349                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1350         } else {
1351                 response[0] = 0;
1352                 response[1] = 0;
1353                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1354         }
1355
1356         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1357         intel_sdvo_read_response(intel_output, &response, 2);
1358 }
1359
1360 static void
1361 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1362 {
1363         struct intel_output *intel_output = to_intel_output(connector);
1364         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1365         struct edid *edid = NULL;
1366
1367         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1368         edid = drm_get_edid(&intel_output->base,
1369                             &intel_output->ddc_bus->adapter);
1370         if (edid != NULL) {
1371                 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1372                 kfree(edid);
1373                 intel_output->base.display_info.raw_edid = NULL;
1374         }
1375 }
1376
1377 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1378 {
1379         u8 response[2];
1380         u8 status;
1381         struct intel_output *intel_output = to_intel_output(connector);
1382
1383         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1384         status = intel_sdvo_read_response(intel_output, &response, 2);
1385
1386         DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
1387
1388         if (status != SDVO_CMD_STATUS_SUCCESS)
1389                 return connector_status_unknown;
1390
1391         if ((response[0] != 0) || (response[1] != 0)) {
1392                 intel_sdvo_hdmi_sink_detect(connector);
1393                 return connector_status_connected;
1394         } else
1395                 return connector_status_disconnected;
1396 }
1397
1398 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1399 {
1400         struct intel_output *intel_output = to_intel_output(connector);
1401         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1402
1403         /* set the bus switch and get the modes */
1404         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1405         intel_ddc_get_modes(intel_output);
1406
1407 #if 0
1408         struct drm_device *dev = encoder->dev;
1409         struct drm_i915_private *dev_priv = dev->dev_private;
1410         /* Mac mini hack.  On this device, I get DDC through the analog, which
1411          * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
1412          * but it does load-detect as connected.  So, just steal the DDC bits
1413          * from analog when we fail at finding it the right way.
1414          */
1415         crt = xf86_config->output[0];
1416         intel_output = crt->driver_private;
1417         if (intel_output->type == I830_OUTPUT_ANALOG &&
1418             crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1419                 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1420                 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1421                 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1422         }
1423         if (edid_mon) {
1424                 xf86OutputSetEDID(output, edid_mon);
1425                 modes = xf86OutputGetEDIDModes(output);
1426         }
1427 #endif
1428 }
1429
1430 /**
1431  * This function checks the current TV format, and chooses a default if
1432  * it hasn't been set.
1433  */
1434 static void
1435 intel_sdvo_check_tv_format(struct intel_output *output)
1436 {
1437         struct intel_sdvo_priv *dev_priv = output->dev_priv;
1438         struct intel_sdvo_tv_format format;
1439         uint8_t status;
1440
1441         intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1442         status = intel_sdvo_read_response(output, &format, sizeof(format));
1443         if (status != SDVO_CMD_STATUS_SUCCESS)
1444                 return;
1445
1446         memcpy(&dev_priv->tv_format, &format, sizeof(format));
1447 }
1448
1449 /*
1450  * Set of SDVO TV modes.
1451  * Note!  This is in reply order (see loop in get_tv_modes).
1452  * XXX: all 60Hz refresh?
1453  */
1454 struct drm_display_mode sdvo_tv_modes[] = {
1455         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1456                    416, 0, 200, 201, 232, 233, 0,
1457                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1458         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1459                    416, 0, 240, 241, 272, 273, 0,
1460                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1461         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1462                    496, 0, 300, 301, 332, 333, 0,
1463                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1464         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1465                    736, 0, 350, 351, 382, 383, 0,
1466                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1467         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1468                    736, 0, 400, 401, 432, 433, 0,
1469                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1470         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1471                    736, 0, 480, 481, 512, 513, 0,
1472                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1473         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1474                    800, 0, 480, 481, 512, 513, 0,
1475                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1476         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1477                    800, 0, 576, 577, 608, 609, 0,
1478                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1479         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1480                    816, 0, 350, 351, 382, 383, 0,
1481                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1482         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1483                    816, 0, 400, 401, 432, 433, 0,
1484                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1485         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1486                    816, 0, 480, 481, 512, 513, 0,
1487                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1488         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1489                    816, 0, 540, 541, 572, 573, 0,
1490                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1491         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1492                    816, 0, 576, 577, 608, 609, 0,
1493                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1494         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1495                    864, 0, 576, 577, 608, 609, 0,
1496                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1497         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1498                    896, 0, 600, 601, 632, 633, 0,
1499                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1500         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1501                    928, 0, 624, 625, 656, 657, 0,
1502                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1503         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1504                    1016, 0, 766, 767, 798, 799, 0,
1505                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1506         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1507                    1120, 0, 768, 769, 800, 801, 0,
1508                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1509         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1510                    1376, 0, 1024, 1025, 1056, 1057, 0,
1511                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1512 };
1513
1514 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1515 {
1516         struct intel_output *output = to_intel_output(connector);
1517         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1518         struct intel_sdvo_sdtv_resolution_request tv_res;
1519         uint32_t reply = 0;
1520         uint8_t status;
1521         int i = 0;
1522
1523         intel_sdvo_check_tv_format(output);
1524
1525         /* Read the list of supported input resolutions for the selected TV
1526          * format.
1527          */
1528         memset(&tv_res, 0, sizeof(tv_res));
1529         memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
1530         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1531                              &tv_res, sizeof(tv_res));
1532         status = intel_sdvo_read_response(output, &reply, 3);
1533         if (status != SDVO_CMD_STATUS_SUCCESS)
1534                 return;
1535
1536         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1537                 if (reply & (1 << i)) {
1538                         struct drm_display_mode *nmode;
1539                         nmode = drm_mode_duplicate(connector->dev,
1540                                         &sdvo_tv_modes[i]);
1541                         if (nmode)
1542                                 drm_mode_probed_add(connector, nmode);
1543                 }
1544 }
1545
1546 static int intel_sdvo_get_modes(struct drm_connector *connector)
1547 {
1548         struct intel_output *output = to_intel_output(connector);
1549         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1550
1551         if (sdvo_priv->is_tv)
1552                 intel_sdvo_get_tv_modes(connector);
1553         else
1554                 intel_sdvo_get_ddc_modes(connector);
1555
1556         if (list_empty(&connector->probed_modes))
1557                 return 0;
1558         return 1;
1559 }
1560
1561 static void intel_sdvo_destroy(struct drm_connector *connector)
1562 {
1563         struct intel_output *intel_output = to_intel_output(connector);
1564
1565         if (intel_output->i2c_bus)
1566                 intel_i2c_destroy(intel_output->i2c_bus);
1567         drm_sysfs_connector_remove(connector);
1568         drm_connector_cleanup(connector);
1569         kfree(intel_output);
1570 }
1571
1572 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1573         .dpms = intel_sdvo_dpms,
1574         .mode_fixup = intel_sdvo_mode_fixup,
1575         .prepare = intel_encoder_prepare,
1576         .mode_set = intel_sdvo_mode_set,
1577         .commit = intel_encoder_commit,
1578 };
1579
1580 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1581         .save = intel_sdvo_save,
1582         .restore = intel_sdvo_restore,
1583         .detect = intel_sdvo_detect,
1584         .fill_modes = drm_helper_probe_single_connector_modes,
1585         .destroy = intel_sdvo_destroy,
1586 };
1587
1588 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1589         .get_modes = intel_sdvo_get_modes,
1590         .mode_valid = intel_sdvo_mode_valid,
1591         .best_encoder = intel_best_encoder,
1592 };
1593
1594 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1595 {
1596         drm_encoder_cleanup(encoder);
1597 }
1598
1599 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1600         .destroy = intel_sdvo_enc_destroy,
1601 };
1602
1603
1604 /**
1605  * Choose the appropriate DDC bus for control bus switch command for this
1606  * SDVO output based on the controlled output.
1607  *
1608  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1609  * outputs, then LVDS outputs.
1610  */
1611 static void
1612 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1613 {
1614         uint16_t mask = 0;
1615         unsigned int num_bits;
1616
1617         /* Make a mask of outputs less than or equal to our own priority in the
1618          * list.
1619          */
1620         switch (dev_priv->controlled_output) {
1621         case SDVO_OUTPUT_LVDS1:
1622                 mask |= SDVO_OUTPUT_LVDS1;
1623         case SDVO_OUTPUT_LVDS0:
1624                 mask |= SDVO_OUTPUT_LVDS0;
1625         case SDVO_OUTPUT_TMDS1:
1626                 mask |= SDVO_OUTPUT_TMDS1;
1627         case SDVO_OUTPUT_TMDS0:
1628                 mask |= SDVO_OUTPUT_TMDS0;
1629         case SDVO_OUTPUT_RGB1:
1630                 mask |= SDVO_OUTPUT_RGB1;
1631         case SDVO_OUTPUT_RGB0:
1632                 mask |= SDVO_OUTPUT_RGB0;
1633                 break;
1634         }
1635
1636         /* Count bits to find what number we are in the priority list. */
1637         mask &= dev_priv->caps.output_flags;
1638         num_bits = hweight16(mask);
1639         if (num_bits > 3) {
1640                 /* if more than 3 outputs, default to DDC bus 3 for now */
1641                 num_bits = 3;
1642         }
1643
1644         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1645         dev_priv->ddc_bus = 1 << num_bits;
1646 }
1647
1648 static bool
1649 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1650 {
1651         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1652         uint8_t status;
1653
1654         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1655
1656         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1657         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1658         if (status != SDVO_CMD_STATUS_SUCCESS)
1659                 return false;
1660         return true;
1661 }
1662
1663 bool intel_sdvo_init(struct drm_device *dev, int output_device)
1664 {
1665         struct drm_connector *connector;
1666         struct intel_output *intel_output;
1667         struct intel_sdvo_priv *sdvo_priv;
1668         struct intel_i2c_chan *i2cbus = NULL;
1669         int connector_type;
1670         u8 ch[0x40];
1671         int i;
1672         int encoder_type, output_id;
1673
1674         intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1675         if (!intel_output) {
1676                 return false;
1677         }
1678
1679         connector = &intel_output->base;
1680
1681         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1682                            DRM_MODE_CONNECTOR_Unknown);
1683         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1684         sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1685         intel_output->type = INTEL_OUTPUT_SDVO;
1686
1687         connector->interlace_allowed = 0;
1688         connector->doublescan_allowed = 0;
1689
1690         /* setup the DDC bus. */
1691         if (output_device == SDVOB)
1692                 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1693         else
1694                 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1695
1696         if (!i2cbus)
1697                 goto err_connector;
1698
1699         sdvo_priv->i2c_bus = i2cbus;
1700
1701         if (output_device == SDVOB) {
1702                 output_id = 1;
1703                 sdvo_priv->i2c_bus->slave_addr = 0x38;
1704         } else {
1705                 output_id = 2;
1706                 sdvo_priv->i2c_bus->slave_addr = 0x39;
1707         }
1708
1709         sdvo_priv->output_device = output_device;
1710         intel_output->i2c_bus = i2cbus;
1711         intel_output->dev_priv = sdvo_priv;
1712
1713
1714         /* Read the regs to test if we can talk to the device */
1715         for (i = 0; i < 0x40; i++) {
1716                 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1717                         DRM_DEBUG("No SDVO device found on SDVO%c\n",
1718                                   output_device == SDVOB ? 'B' : 'C');
1719                         goto err_i2c;
1720                 }
1721         }
1722
1723         intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1724
1725         if (sdvo_priv->caps.output_flags &
1726             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1727                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1728                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1729                 else
1730                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1731
1732                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1733                 encoder_type = DRM_MODE_ENCODER_TMDS;
1734                 connector_type = DRM_MODE_CONNECTOR_DVID;
1735
1736                 if (intel_sdvo_get_supp_encode(intel_output,
1737                                                &sdvo_priv->encode) &&
1738                     intel_sdvo_get_digital_encoding_mode(intel_output) &&
1739                     sdvo_priv->is_hdmi) {
1740                         /* enable hdmi encoding mode if supported */
1741                         intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1742                         intel_sdvo_set_colorimetry(intel_output,
1743                                                    SDVO_COLORIMETRY_RGB256);
1744                         connector_type = DRM_MODE_CONNECTOR_HDMIA;
1745                 }
1746         }
1747         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
1748         {
1749                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1750                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1751                 encoder_type = DRM_MODE_ENCODER_TVDAC;
1752                 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1753                 sdvo_priv->is_tv = true;
1754                 intel_output->needs_tv_clock = true;
1755         }
1756         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1757         {
1758                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1759                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1760                 encoder_type = DRM_MODE_ENCODER_DAC;
1761                 connector_type = DRM_MODE_CONNECTOR_VGA;
1762         }
1763         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1764         {
1765                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1766                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1767                 encoder_type = DRM_MODE_ENCODER_DAC;
1768                 connector_type = DRM_MODE_CONNECTOR_VGA;
1769         }
1770         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
1771         {
1772                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1773                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1774                 encoder_type = DRM_MODE_ENCODER_LVDS;
1775                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1776         }
1777         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
1778         {
1779                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1780                 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1781                 encoder_type = DRM_MODE_ENCODER_LVDS;
1782                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1783         }
1784         else
1785         {
1786                 unsigned char bytes[2];
1787
1788                 sdvo_priv->controlled_output = 0;
1789                 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1790                 DRM_DEBUG("%s: Unknown SDVO output type (0x%02x%02x)\n",
1791                           SDVO_NAME(sdvo_priv),
1792                           bytes[0], bytes[1]);
1793                 encoder_type = DRM_MODE_ENCODER_NONE;
1794                 connector_type = DRM_MODE_CONNECTOR_Unknown;
1795                 goto err_i2c;
1796         }
1797
1798         drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1799         drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1800         connector->connector_type = connector_type;
1801
1802         drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1803         drm_sysfs_connector_add(connector);
1804
1805         intel_sdvo_select_ddc_bus(sdvo_priv);
1806
1807         /* Set the input timing to the screen. Assume always input 0. */
1808         intel_sdvo_set_target_input(intel_output, true, false);
1809
1810         intel_sdvo_get_input_pixel_clock_range(intel_output,
1811                                                &sdvo_priv->pixel_clock_min,
1812                                                &sdvo_priv->pixel_clock_max);
1813
1814
1815         DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1816                   "clock range %dMHz - %dMHz, "
1817                   "input 1: %c, input 2: %c, "
1818                   "output 1: %c, output 2: %c\n",
1819                   SDVO_NAME(sdvo_priv),
1820                   sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1821                   sdvo_priv->caps.device_rev_id,
1822                   sdvo_priv->pixel_clock_min / 1000,
1823                   sdvo_priv->pixel_clock_max / 1000,
1824                   (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1825                   (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1826                   /* check currently supported outputs */
1827                   sdvo_priv->caps.output_flags &
1828                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1829                   sdvo_priv->caps.output_flags &
1830                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1831
1832         intel_output->ddc_bus = i2cbus;
1833
1834         return true;
1835
1836 err_i2c:
1837         intel_i2c_destroy(intel_output->i2c_bus);
1838 err_connector:
1839         drm_connector_cleanup(connector);
1840         kfree(intel_output);
1841
1842         return false;
1843 }