Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt...
[pandora-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2007 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *      Eric Anholt <eric@anholt.net>
27  */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "intel_drv.h"
35 #include "drm_edid.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "intel_sdvo_regs.h"
39 #include <linux/dmi.h>
40
41 static char *tv_format_names[] = {
42         "NTSC_M"   , "NTSC_J"  , "NTSC_443",
43         "PAL_B"    , "PAL_D"   , "PAL_G"   ,
44         "PAL_H"    , "PAL_I"   , "PAL_M"   ,
45         "PAL_N"    , "PAL_NC"  , "PAL_60"  ,
46         "SECAM_B"  , "SECAM_D" , "SECAM_G" ,
47         "SECAM_K"  , "SECAM_K1", "SECAM_L" ,
48         "SECAM_60"
49 };
50
51 #define TV_FORMAT_NUM  (sizeof(tv_format_names) / sizeof(*tv_format_names))
52
53 struct intel_sdvo_priv {
54         u8 slave_addr;
55
56         /* Register for the SDVO device: SDVOB or SDVOC */
57         int sdvo_reg;
58
59         /* Active outputs controlled by this SDVO output */
60         uint16_t controlled_output;
61
62         /*
63          * Capabilities of the SDVO device returned by
64          * i830_sdvo_get_capabilities()
65          */
66         struct intel_sdvo_caps caps;
67
68         /* Pixel clock limitations reported by the SDVO device, in kHz */
69         int pixel_clock_min, pixel_clock_max;
70
71         /*
72         * For multiple function SDVO device,
73         * this is for current attached outputs.
74         */
75         uint16_t attached_output;
76
77         /**
78          * This is set if we're going to treat the device as TV-out.
79          *
80          * While we have these nice friendly flags for output types that ought
81          * to decide this for us, the S-Video output on our HDMI+S-Video card
82          * shows up as RGB1 (VGA).
83          */
84         bool is_tv;
85
86         /* This is for current tv format name */
87         char *tv_format_name;
88
89         /* This contains all current supported TV format */
90         char *tv_format_supported[TV_FORMAT_NUM];
91         int   format_supported_num;
92         struct drm_property *tv_format_property;
93         struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
94
95         /**
96          * This is set if we treat the device as HDMI, instead of DVI.
97          */
98         bool is_hdmi;
99
100         /**
101          * This is set if we detect output of sdvo device as LVDS.
102          */
103         bool is_lvds;
104
105         /**
106          * This is sdvo flags for input timing.
107          */
108         uint8_t sdvo_flags;
109
110         /**
111          * This is sdvo fixed pannel mode pointer
112          */
113         struct drm_display_mode *sdvo_lvds_fixed_mode;
114
115         /**
116          * Returned SDTV resolutions allowed for the current format, if the
117          * device reported it.
118          */
119         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
120
121         /*
122          * supported encoding mode, used to determine whether HDMI is
123          * supported
124          */
125         struct intel_sdvo_encode encode;
126
127         /* DDC bus used by this SDVO encoder */
128         uint8_t ddc_bus;
129
130         /* Mac mini hack -- use the same DDC as the analog connector */
131         struct i2c_adapter *analog_ddc_bus;
132
133         int save_sdvo_mult;
134         u16 save_active_outputs;
135         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
136         struct intel_sdvo_dtd save_output_dtd[16];
137         u32 save_SDVOX;
138         /* add the property for the SDVO-TV */
139         struct drm_property *left_property;
140         struct drm_property *right_property;
141         struct drm_property *top_property;
142         struct drm_property *bottom_property;
143         struct drm_property *hpos_property;
144         struct drm_property *vpos_property;
145
146         /* add the property for the SDVO-TV/LVDS */
147         struct drm_property *brightness_property;
148         struct drm_property *contrast_property;
149         struct drm_property *saturation_property;
150         struct drm_property *hue_property;
151
152         /* Add variable to record current setting for the above property */
153         u32     left_margin, right_margin, top_margin, bottom_margin;
154         /* this is to get the range of margin.*/
155         u32     max_hscan,  max_vscan;
156         u32     max_hpos, cur_hpos;
157         u32     max_vpos, cur_vpos;
158         u32     cur_brightness, max_brightness;
159         u32     cur_contrast,   max_contrast;
160         u32     cur_saturation, max_saturation;
161         u32     cur_hue,        max_hue;
162 };
163
164 static bool
165 intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags);
166
167 /**
168  * Writes the SDVOB or SDVOC with the given value, but always writes both
169  * SDVOB and SDVOC to work around apparent hardware issues (according to
170  * comments in the BIOS).
171  */
172 static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
173 {
174         struct drm_device *dev = intel_encoder->base.dev;
175         struct drm_i915_private *dev_priv = dev->dev_private;
176         struct intel_sdvo_priv   *sdvo_priv = intel_encoder->dev_priv;
177         u32 bval = val, cval = val;
178         int i;
179
180         if (sdvo_priv->sdvo_reg == SDVOB) {
181                 cval = I915_READ(SDVOC);
182         } else {
183                 bval = I915_READ(SDVOB);
184         }
185         /*
186          * Write the registers twice for luck. Sometimes,
187          * writing them only once doesn't appear to 'stick'.
188          * The BIOS does this too. Yay, magic
189          */
190         for (i = 0; i < 2; i++)
191         {
192                 I915_WRITE(SDVOB, bval);
193                 I915_READ(SDVOB);
194                 I915_WRITE(SDVOC, cval);
195                 I915_READ(SDVOC);
196         }
197 }
198
199 static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
200                                  u8 *ch)
201 {
202         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
203         u8 out_buf[2];
204         u8 buf[2];
205         int ret;
206
207         struct i2c_msg msgs[] = {
208                 {
209                         .addr = sdvo_priv->slave_addr >> 1,
210                         .flags = 0,
211                         .len = 1,
212                         .buf = out_buf,
213                 },
214                 {
215                         .addr = sdvo_priv->slave_addr >> 1,
216                         .flags = I2C_M_RD,
217                         .len = 1,
218                         .buf = buf,
219                 }
220         };
221
222         out_buf[0] = addr;
223         out_buf[1] = 0;
224
225         if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
226         {
227                 *ch = buf[0];
228                 return true;
229         }
230
231         DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
232         return false;
233 }
234
235 static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
236                                   u8 ch)
237 {
238         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
239         u8 out_buf[2];
240         struct i2c_msg msgs[] = {
241                 {
242                         .addr = sdvo_priv->slave_addr >> 1,
243                         .flags = 0,
244                         .len = 2,
245                         .buf = out_buf,
246                 }
247         };
248
249         out_buf[0] = addr;
250         out_buf[1] = ch;
251
252         if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
253         {
254                 return true;
255         }
256         return false;
257 }
258
259 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
260 /** Mapping of command numbers to names, for debug output */
261 static const struct _sdvo_cmd_name {
262         u8 cmd;
263         char *name;
264 } sdvo_cmd_names[] = {
265     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
266     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
267     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
268     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
269     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
270     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
271     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
272     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
273     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
274     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
275     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
276     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
277     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
278     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
279     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
280     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
281     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
282     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
283     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
284     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
285     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
286     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
287     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
288     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
289     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
290     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
291     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
292     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
293     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
294     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
295     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
296     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
297     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
298     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
299     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
300     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
301     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
302     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
303     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
304     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
305     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
306     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
307     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
308     /* Add the op code for SDVO enhancements */
309     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
310     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
311     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
312     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
313     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
314     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
315     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
316     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
317     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
318     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
319     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
320     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
321     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
322     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
323     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
324     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
325     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
326     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
327     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
328     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
329     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
330     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
331     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
332     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
333     /* HDMI op code */
334     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
335     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
336     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
337     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
338     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
339     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
340     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
341     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
342     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
343     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
344     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
345     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
346     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
347     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
348     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
349     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
350     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
351     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
352     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
353     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
354 };
355
356 #define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC")
357 #define SDVO_PRIV(encoder)   ((struct intel_sdvo_priv *) (encoder)->dev_priv)
358
359 static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
360                                    void *args, int args_len)
361 {
362         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
363         int i;
364
365         DRM_DEBUG_KMS("%s: W: %02X ",
366                                 SDVO_NAME(sdvo_priv), cmd);
367         for (i = 0; i < args_len; i++)
368                 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
369         for (; i < 8; i++)
370                 DRM_LOG_KMS("   ");
371         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
372                 if (cmd == sdvo_cmd_names[i].cmd) {
373                         DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
374                         break;
375                 }
376         }
377         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
378                 DRM_LOG_KMS("(%02X)", cmd);
379         DRM_LOG_KMS("\n");
380 }
381
382 static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
383                                  void *args, int args_len)
384 {
385         int i;
386
387         intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
388
389         for (i = 0; i < args_len; i++) {
390                 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
391                                       ((u8*)args)[i]);
392         }
393
394         intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
395 }
396
397 static const char *cmd_status_names[] = {
398         "Power on",
399         "Success",
400         "Not supported",
401         "Invalid arg",
402         "Pending",
403         "Target not specified",
404         "Scaling not supported"
405 };
406
407 static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
408                                       void *response, int response_len,
409                                       u8 status)
410 {
411         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
412         int i;
413
414         DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
415         for (i = 0; i < response_len; i++)
416                 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
417         for (; i < 8; i++)
418                 DRM_LOG_KMS("   ");
419         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
420                 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
421         else
422                 DRM_LOG_KMS("(??? %d)", status);
423         DRM_LOG_KMS("\n");
424 }
425
426 static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
427                                    void *response, int response_len)
428 {
429         int i;
430         u8 status;
431         u8 retry = 50;
432
433         while (retry--) {
434                 /* Read the command response */
435                 for (i = 0; i < response_len; i++) {
436                         intel_sdvo_read_byte(intel_encoder,
437                                              SDVO_I2C_RETURN_0 + i,
438                                              &((u8 *)response)[i]);
439                 }
440
441                 /* read the return status */
442                 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
443                                      &status);
444
445                 intel_sdvo_debug_response(intel_encoder, response, response_len,
446                                           status);
447                 if (status != SDVO_CMD_STATUS_PENDING)
448                         return status;
449
450                 mdelay(50);
451         }
452
453         return status;
454 }
455
456 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
457 {
458         if (mode->clock >= 100000)
459                 return 1;
460         else if (mode->clock >= 50000)
461                 return 2;
462         else
463                 return 4;
464 }
465
466 /**
467  * Try to read the response after issuie the DDC switch command. But it
468  * is noted that we must do the action of reading response and issuing DDC
469  * switch command in one I2C transaction. Otherwise when we try to start
470  * another I2C transaction after issuing the DDC bus switch, it will be
471  * switched to the internal SDVO register.
472  */
473 static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
474                                               u8 target)
475 {
476         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
477         u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
478         struct i2c_msg msgs[] = {
479                 {
480                         .addr = sdvo_priv->slave_addr >> 1,
481                         .flags = 0,
482                         .len = 2,
483                         .buf = out_buf,
484                 },
485                 /* the following two are to read the response */
486                 {
487                         .addr = sdvo_priv->slave_addr >> 1,
488                         .flags = 0,
489                         .len = 1,
490                         .buf = cmd_buf,
491                 },
492                 {
493                         .addr = sdvo_priv->slave_addr >> 1,
494                         .flags = I2C_M_RD,
495                         .len = 1,
496                         .buf = ret_value,
497                 },
498         };
499
500         intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
501                                         &target, 1);
502         /* write the DDC switch command argument */
503         intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
504
505         out_buf[0] = SDVO_I2C_OPCODE;
506         out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
507         cmd_buf[0] = SDVO_I2C_CMD_STATUS;
508         cmd_buf[1] = 0;
509         ret_value[0] = 0;
510         ret_value[1] = 0;
511
512         ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
513         if (ret != 3) {
514                 /* failure in I2C transfer */
515                 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
516                 return;
517         }
518         if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
519                 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
520                                         ret_value[0]);
521                 return;
522         }
523         return;
524 }
525
526 static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
527 {
528         struct intel_sdvo_set_target_input_args targets = {0};
529         u8 status;
530
531         if (target_0 && target_1)
532                 return SDVO_CMD_STATUS_NOTSUPP;
533
534         if (target_1)
535                 targets.target_1 = 1;
536
537         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
538                              sizeof(targets));
539
540         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
541
542         return (status == SDVO_CMD_STATUS_SUCCESS);
543 }
544
545 /**
546  * Return whether each input is trained.
547  *
548  * This function is making an assumption about the layout of the response,
549  * which should be checked against the docs.
550  */
551 static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
552 {
553         struct intel_sdvo_get_trained_inputs_response response;
554         u8 status;
555
556         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
557         status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
558         if (status != SDVO_CMD_STATUS_SUCCESS)
559                 return false;
560
561         *input_1 = response.input0_trained;
562         *input_2 = response.input1_trained;
563         return true;
564 }
565
566 static bool intel_sdvo_get_active_outputs(struct intel_encoder *intel_encoder,
567                                           u16 *outputs)
568 {
569         u8 status;
570
571         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
572         status = intel_sdvo_read_response(intel_encoder, outputs, sizeof(*outputs));
573
574         return (status == SDVO_CMD_STATUS_SUCCESS);
575 }
576
577 static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
578                                           u16 outputs)
579 {
580         u8 status;
581
582         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
583                              sizeof(outputs));
584         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
585         return (status == SDVO_CMD_STATUS_SUCCESS);
586 }
587
588 static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
589                                                int mode)
590 {
591         u8 status, state = SDVO_ENCODER_STATE_ON;
592
593         switch (mode) {
594         case DRM_MODE_DPMS_ON:
595                 state = SDVO_ENCODER_STATE_ON;
596                 break;
597         case DRM_MODE_DPMS_STANDBY:
598                 state = SDVO_ENCODER_STATE_STANDBY;
599                 break;
600         case DRM_MODE_DPMS_SUSPEND:
601                 state = SDVO_ENCODER_STATE_SUSPEND;
602                 break;
603         case DRM_MODE_DPMS_OFF:
604                 state = SDVO_ENCODER_STATE_OFF;
605                 break;
606         }
607
608         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
609                              sizeof(state));
610         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
611
612         return (status == SDVO_CMD_STATUS_SUCCESS);
613 }
614
615 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
616                                                    int *clock_min,
617                                                    int *clock_max)
618 {
619         struct intel_sdvo_pixel_clock_range clocks;
620         u8 status;
621
622         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
623                              NULL, 0);
624
625         status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
626
627         if (status != SDVO_CMD_STATUS_SUCCESS)
628                 return false;
629
630         /* Convert the values from units of 10 kHz to kHz. */
631         *clock_min = clocks.min * 10;
632         *clock_max = clocks.max * 10;
633
634         return true;
635 }
636
637 static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
638                                          u16 outputs)
639 {
640         u8 status;
641
642         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
643                              sizeof(outputs));
644
645         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
646         return (status == SDVO_CMD_STATUS_SUCCESS);
647 }
648
649 static bool intel_sdvo_get_timing(struct intel_encoder *intel_encoder, u8 cmd,
650                                   struct intel_sdvo_dtd *dtd)
651 {
652         u8 status;
653
654         intel_sdvo_write_cmd(intel_encoder, cmd, NULL, 0);
655         status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
656                                           sizeof(dtd->part1));
657         if (status != SDVO_CMD_STATUS_SUCCESS)
658                 return false;
659
660         intel_sdvo_write_cmd(intel_encoder, cmd + 1, NULL, 0);
661         status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
662                                           sizeof(dtd->part2));
663         if (status != SDVO_CMD_STATUS_SUCCESS)
664                 return false;
665
666         return true;
667 }
668
669 static bool intel_sdvo_get_input_timing(struct intel_encoder *intel_encoder,
670                                          struct intel_sdvo_dtd *dtd)
671 {
672         return intel_sdvo_get_timing(intel_encoder,
673                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
674 }
675
676 static bool intel_sdvo_get_output_timing(struct intel_encoder *intel_encoder,
677                                          struct intel_sdvo_dtd *dtd)
678 {
679         return intel_sdvo_get_timing(intel_encoder,
680                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
681 }
682
683 static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
684                                   struct intel_sdvo_dtd *dtd)
685 {
686         u8 status;
687
688         intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
689         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
690         if (status != SDVO_CMD_STATUS_SUCCESS)
691                 return false;
692
693         intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
694         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
695         if (status != SDVO_CMD_STATUS_SUCCESS)
696                 return false;
697
698         return true;
699 }
700
701 static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
702                                          struct intel_sdvo_dtd *dtd)
703 {
704         return intel_sdvo_set_timing(intel_encoder,
705                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
706 }
707
708 static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
709                                          struct intel_sdvo_dtd *dtd)
710 {
711         return intel_sdvo_set_timing(intel_encoder,
712                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
713 }
714
715 static bool
716 intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
717                                          uint16_t clock,
718                                          uint16_t width,
719                                          uint16_t height)
720 {
721         struct intel_sdvo_preferred_input_timing_args args;
722         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
723         uint8_t status;
724
725         memset(&args, 0, sizeof(args));
726         args.clock = clock;
727         args.width = width;
728         args.height = height;
729         args.interlace = 0;
730
731         if (sdvo_priv->is_lvds &&
732            (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
733             sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
734                 args.scaled = 1;
735
736         intel_sdvo_write_cmd(intel_encoder,
737                              SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
738                              &args, sizeof(args));
739         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
740         if (status != SDVO_CMD_STATUS_SUCCESS)
741                 return false;
742
743         return true;
744 }
745
746 static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
747                                                   struct intel_sdvo_dtd *dtd)
748 {
749         bool status;
750
751         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
752                              NULL, 0);
753
754         status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
755                                           sizeof(dtd->part1));
756         if (status != SDVO_CMD_STATUS_SUCCESS)
757                 return false;
758
759         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
760                              NULL, 0);
761
762         status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
763                                           sizeof(dtd->part2));
764         if (status != SDVO_CMD_STATUS_SUCCESS)
765                 return false;
766
767         return false;
768 }
769
770 static int intel_sdvo_get_clock_rate_mult(struct intel_encoder *intel_encoder)
771 {
772         u8 response, status;
773
774         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
775         status = intel_sdvo_read_response(intel_encoder, &response, 1);
776
777         if (status != SDVO_CMD_STATUS_SUCCESS) {
778                 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
779                 return SDVO_CLOCK_RATE_MULT_1X;
780         } else {
781                 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
782         }
783
784         return response;
785 }
786
787 static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
788 {
789         u8 status;
790
791         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
792         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
793         if (status != SDVO_CMD_STATUS_SUCCESS)
794                 return false;
795
796         return true;
797 }
798
799 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
800                                          struct drm_display_mode *mode)
801 {
802         uint16_t width, height;
803         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
804         uint16_t h_sync_offset, v_sync_offset;
805
806         width = mode->crtc_hdisplay;
807         height = mode->crtc_vdisplay;
808
809         /* do some mode translations */
810         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
811         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
812
813         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
814         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
815
816         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
817         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
818
819         dtd->part1.clock = mode->clock / 10;
820         dtd->part1.h_active = width & 0xff;
821         dtd->part1.h_blank = h_blank_len & 0xff;
822         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
823                 ((h_blank_len >> 8) & 0xf);
824         dtd->part1.v_active = height & 0xff;
825         dtd->part1.v_blank = v_blank_len & 0xff;
826         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
827                 ((v_blank_len >> 8) & 0xf);
828
829         dtd->part2.h_sync_off = h_sync_offset & 0xff;
830         dtd->part2.h_sync_width = h_sync_len & 0xff;
831         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
832                 (v_sync_len & 0xf);
833         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
834                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
835                 ((v_sync_len & 0x30) >> 4);
836
837         dtd->part2.dtd_flags = 0x18;
838         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
839                 dtd->part2.dtd_flags |= 0x2;
840         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
841                 dtd->part2.dtd_flags |= 0x4;
842
843         dtd->part2.sdvo_flags = 0;
844         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
845         dtd->part2.reserved = 0;
846 }
847
848 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
849                                          struct intel_sdvo_dtd *dtd)
850 {
851         mode->hdisplay = dtd->part1.h_active;
852         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
853         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
854         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
855         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
856         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
857         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
858         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
859
860         mode->vdisplay = dtd->part1.v_active;
861         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
862         mode->vsync_start = mode->vdisplay;
863         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
864         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
865         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
866         mode->vsync_end = mode->vsync_start +
867                 (dtd->part2.v_sync_off_width & 0xf);
868         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
869         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
870         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
871
872         mode->clock = dtd->part1.clock * 10;
873
874         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
875         if (dtd->part2.dtd_flags & 0x2)
876                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
877         if (dtd->part2.dtd_flags & 0x4)
878                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
879 }
880
881 static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
882                                        struct intel_sdvo_encode *encode)
883 {
884         uint8_t status;
885
886         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
887         status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
888         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
889                 memset(encode, 0, sizeof(*encode));
890                 return false;
891         }
892
893         return true;
894 }
895
896 static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
897                                   uint8_t mode)
898 {
899         uint8_t status;
900
901         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
902         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
903
904         return (status == SDVO_CMD_STATUS_SUCCESS);
905 }
906
907 static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
908                                        uint8_t mode)
909 {
910         uint8_t status;
911
912         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
913         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
914
915         return (status == SDVO_CMD_STATUS_SUCCESS);
916 }
917
918 #if 0
919 static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
920 {
921         int i, j;
922         uint8_t set_buf_index[2];
923         uint8_t av_split;
924         uint8_t buf_size;
925         uint8_t buf[48];
926         uint8_t *pos;
927
928         intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
929         intel_sdvo_read_response(encoder, &av_split, 1);
930
931         for (i = 0; i <= av_split; i++) {
932                 set_buf_index[0] = i; set_buf_index[1] = 0;
933                 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
934                                      set_buf_index, 2);
935                 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
936                 intel_sdvo_read_response(encoder, &buf_size, 1);
937
938                 pos = buf;
939                 for (j = 0; j <= buf_size; j += 8) {
940                         intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
941                                              NULL, 0);
942                         intel_sdvo_read_response(encoder, pos, 8);
943                         pos += 8;
944                 }
945         }
946 }
947 #endif
948
949 static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
950                                     int index,
951                                     uint8_t *data, int8_t size, uint8_t tx_rate)
952 {
953     uint8_t set_buf_index[2];
954
955     set_buf_index[0] = index;
956     set_buf_index[1] = 0;
957
958     intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
959                          set_buf_index, 2);
960
961     for (; size > 0; size -= 8) {
962         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
963         data += 8;
964     }
965
966     intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
967 }
968
969 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
970 {
971         uint8_t csum = 0;
972         int i;
973
974         for (i = 0; i < size; i++)
975                 csum += data[i];
976
977         return 0x100 - csum;
978 }
979
980 #define DIP_TYPE_AVI    0x82
981 #define DIP_VERSION_AVI 0x2
982 #define DIP_LEN_AVI     13
983
984 struct dip_infoframe {
985         uint8_t type;
986         uint8_t version;
987         uint8_t len;
988         uint8_t checksum;
989         union {
990                 struct {
991                         /* Packet Byte #1 */
992                         uint8_t S:2;
993                         uint8_t B:2;
994                         uint8_t A:1;
995                         uint8_t Y:2;
996                         uint8_t rsvd1:1;
997                         /* Packet Byte #2 */
998                         uint8_t R:4;
999                         uint8_t M:2;
1000                         uint8_t C:2;
1001                         /* Packet Byte #3 */
1002                         uint8_t SC:2;
1003                         uint8_t Q:2;
1004                         uint8_t EC:3;
1005                         uint8_t ITC:1;
1006                         /* Packet Byte #4 */
1007                         uint8_t VIC:7;
1008                         uint8_t rsvd2:1;
1009                         /* Packet Byte #5 */
1010                         uint8_t PR:4;
1011                         uint8_t rsvd3:4;
1012                         /* Packet Byte #6~13 */
1013                         uint16_t top_bar_end;
1014                         uint16_t bottom_bar_start;
1015                         uint16_t left_bar_end;
1016                         uint16_t right_bar_start;
1017                 } avi;
1018                 struct {
1019                         /* Packet Byte #1 */
1020                         uint8_t channel_count:3;
1021                         uint8_t rsvd1:1;
1022                         uint8_t coding_type:4;
1023                         /* Packet Byte #2 */
1024                         uint8_t sample_size:2; /* SS0, SS1 */
1025                         uint8_t sample_frequency:3;
1026                         uint8_t rsvd2:3;
1027                         /* Packet Byte #3 */
1028                         uint8_t coding_type_private:5;
1029                         uint8_t rsvd3:3;
1030                         /* Packet Byte #4 */
1031                         uint8_t channel_allocation;
1032                         /* Packet Byte #5 */
1033                         uint8_t rsvd4:3;
1034                         uint8_t level_shift:4;
1035                         uint8_t downmix_inhibit:1;
1036                 } audio;
1037                 uint8_t payload[28];
1038         } __attribute__ ((packed)) u;
1039 } __attribute__((packed));
1040
1041 static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
1042                                          struct drm_display_mode * mode)
1043 {
1044         struct dip_infoframe avi_if = {
1045                 .type = DIP_TYPE_AVI,
1046                 .version = DIP_VERSION_AVI,
1047                 .len = DIP_LEN_AVI,
1048         };
1049
1050         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1051                                                     4 + avi_if.len);
1052         intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
1053                                 4 + avi_if.len,
1054                                 SDVO_HBUF_TX_VSYNC);
1055 }
1056
1057 static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
1058 {
1059
1060         struct intel_sdvo_tv_format format;
1061         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1062         uint32_t format_map, i;
1063         uint8_t status;
1064
1065         for (i = 0; i < TV_FORMAT_NUM; i++)
1066                 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1067                         break;
1068
1069         format_map = 1 << i;
1070         memset(&format, 0, sizeof(format));
1071         memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1072                         sizeof(format) : sizeof(format_map));
1073
1074         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map,
1075                              sizeof(format));
1076
1077         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1078         if (status != SDVO_CMD_STATUS_SUCCESS)
1079                 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1080                           SDVO_NAME(sdvo_priv));
1081 }
1082
1083 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1084                                   struct drm_display_mode *mode,
1085                                   struct drm_display_mode *adjusted_mode)
1086 {
1087         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1088         struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
1089
1090         if (dev_priv->is_tv) {
1091                 struct intel_sdvo_dtd output_dtd;
1092                 bool success;
1093
1094                 /* We need to construct preferred input timings based on our
1095                  * output timings.  To do that, we have to set the output
1096                  * timings, even though this isn't really the right place in
1097                  * the sequence to do it. Oh well.
1098                  */
1099
1100
1101                 /* Set output timings */
1102                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1103                 intel_sdvo_set_target_output(intel_encoder,
1104                                              dev_priv->controlled_output);
1105                 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1106
1107                 /* Set the input timing to the screen. Assume always input 0. */
1108                 intel_sdvo_set_target_input(intel_encoder, true, false);
1109
1110
1111                 success = intel_sdvo_create_preferred_input_timing(intel_encoder,
1112                                                                    mode->clock / 10,
1113                                                                    mode->hdisplay,
1114                                                                    mode->vdisplay);
1115                 if (success) {
1116                         struct intel_sdvo_dtd input_dtd;
1117
1118                         intel_sdvo_get_preferred_input_timing(intel_encoder,
1119                                                              &input_dtd);
1120                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1121                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1122
1123                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1124
1125                         mode->clock = adjusted_mode->clock;
1126
1127                         adjusted_mode->clock *=
1128                                 intel_sdvo_get_pixel_multiplier(mode);
1129                 } else {
1130                         return false;
1131                 }
1132         } else if (dev_priv->is_lvds) {
1133                 struct intel_sdvo_dtd output_dtd;
1134                 bool success;
1135
1136                 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1137                 /* Set output timings */
1138                 intel_sdvo_get_dtd_from_mode(&output_dtd,
1139                                 dev_priv->sdvo_lvds_fixed_mode);
1140
1141                 intel_sdvo_set_target_output(intel_encoder,
1142                                              dev_priv->controlled_output);
1143                 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1144
1145                 /* Set the input timing to the screen. Assume always input 0. */
1146                 intel_sdvo_set_target_input(intel_encoder, true, false);
1147
1148
1149                 success = intel_sdvo_create_preferred_input_timing(
1150                                 intel_encoder,
1151                                 mode->clock / 10,
1152                                 mode->hdisplay,
1153                                 mode->vdisplay);
1154
1155                 if (success) {
1156                         struct intel_sdvo_dtd input_dtd;
1157
1158                         intel_sdvo_get_preferred_input_timing(intel_encoder,
1159                                                              &input_dtd);
1160                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1161                         dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1162
1163                         drm_mode_set_crtcinfo(adjusted_mode, 0);
1164
1165                         mode->clock = adjusted_mode->clock;
1166
1167                         adjusted_mode->clock *=
1168                                 intel_sdvo_get_pixel_multiplier(mode);
1169                 } else {
1170                         return false;
1171                 }
1172
1173         } else {
1174                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
1175                  * SDVO device will be told of the multiplier during mode_set.
1176                  */
1177                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1178         }
1179         return true;
1180 }
1181
1182 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1183                                 struct drm_display_mode *mode,
1184                                 struct drm_display_mode *adjusted_mode)
1185 {
1186         struct drm_device *dev = encoder->dev;
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188         struct drm_crtc *crtc = encoder->crtc;
1189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1190         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1191         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1192         u32 sdvox = 0;
1193         int sdvo_pixel_multiply;
1194         struct intel_sdvo_in_out_map in_out;
1195         struct intel_sdvo_dtd input_dtd;
1196         u8 status;
1197
1198         if (!mode)
1199                 return;
1200
1201         /* First, set the input mapping for the first input to our controlled
1202          * output. This is only correct if we're a single-input device, in
1203          * which case the first input is the output from the appropriate SDVO
1204          * channel on the motherboard.  In a two-input device, the first input
1205          * will be SDVOB and the second SDVOC.
1206          */
1207         in_out.in0 = sdvo_priv->controlled_output;
1208         in_out.in1 = 0;
1209
1210         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
1211                              &in_out, sizeof(in_out));
1212         status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1213
1214         if (sdvo_priv->is_hdmi) {
1215                 intel_sdvo_set_avi_infoframe(intel_encoder, mode);
1216                 sdvox |= SDVO_AUDIO_ENABLE;
1217         }
1218
1219         /* We have tried to get input timing in mode_fixup, and filled into
1220            adjusted_mode */
1221         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1222                 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1223                 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1224         } else
1225                 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1226
1227         /* If it's a TV, we already set the output timing in mode_fixup.
1228          * Otherwise, the output timing is equal to the input timing.
1229          */
1230         if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1231                 /* Set the output timing to the screen */
1232                 intel_sdvo_set_target_output(intel_encoder,
1233                                              sdvo_priv->controlled_output);
1234                 intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
1235         }
1236
1237         /* Set the input timing to the screen. Assume always input 0. */
1238         intel_sdvo_set_target_input(intel_encoder, true, false);
1239
1240         if (sdvo_priv->is_tv)
1241                 intel_sdvo_set_tv_format(intel_encoder);
1242
1243         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1244          * provide the device with a timing it can support, if it supports that
1245          * feature.  However, presumably we would need to adjust the CRTC to
1246          * output the preferred timing, and we don't support that currently.
1247          */
1248 #if 0
1249         success = intel_sdvo_create_preferred_input_timing(encoder, clock,
1250                                                            width, height);
1251         if (success) {
1252                 struct intel_sdvo_dtd *input_dtd;
1253
1254                 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1255                 intel_sdvo_set_input_timing(encoder, &input_dtd);
1256         }
1257 #else
1258         intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
1259 #endif
1260
1261         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1262         case 1:
1263                 intel_sdvo_set_clock_rate_mult(intel_encoder,
1264                                                SDVO_CLOCK_RATE_MULT_1X);
1265                 break;
1266         case 2:
1267                 intel_sdvo_set_clock_rate_mult(intel_encoder,
1268                                                SDVO_CLOCK_RATE_MULT_2X);
1269                 break;
1270         case 4:
1271                 intel_sdvo_set_clock_rate_mult(intel_encoder,
1272                                                SDVO_CLOCK_RATE_MULT_4X);
1273                 break;
1274         }
1275
1276         /* Set the SDVO control regs. */
1277         if (IS_I965G(dev)) {
1278                 sdvox |= SDVO_BORDER_ENABLE |
1279                         SDVO_VSYNC_ACTIVE_HIGH |
1280                         SDVO_HSYNC_ACTIVE_HIGH;
1281         } else {
1282                 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
1283                 switch (sdvo_priv->sdvo_reg) {
1284                 case SDVOB:
1285                         sdvox &= SDVOB_PRESERVE_MASK;
1286                         break;
1287                 case SDVOC:
1288                         sdvox &= SDVOC_PRESERVE_MASK;
1289                         break;
1290                 }
1291                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1292         }
1293         if (intel_crtc->pipe == 1)
1294                 sdvox |= SDVO_PIPE_B_SELECT;
1295
1296         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1297         if (IS_I965G(dev)) {
1298                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1299         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1300                 /* done in crtc_mode_set as it lives inside the dpll register */
1301         } else {
1302                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1303         }
1304
1305         if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1306                 sdvox |= SDVO_STALL_SELECT;
1307         intel_sdvo_write_sdvox(intel_encoder, sdvox);
1308 }
1309
1310 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1311 {
1312         struct drm_device *dev = encoder->dev;
1313         struct drm_i915_private *dev_priv = dev->dev_private;
1314         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1315         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1316         u32 temp;
1317
1318         if (mode != DRM_MODE_DPMS_ON) {
1319                 intel_sdvo_set_active_outputs(intel_encoder, 0);
1320                 if (0)
1321                         intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1322
1323                 if (mode == DRM_MODE_DPMS_OFF) {
1324                         temp = I915_READ(sdvo_priv->sdvo_reg);
1325                         if ((temp & SDVO_ENABLE) != 0) {
1326                                 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
1327                         }
1328                 }
1329         } else {
1330                 bool input1, input2;
1331                 int i;
1332                 u8 status;
1333
1334                 temp = I915_READ(sdvo_priv->sdvo_reg);
1335                 if ((temp & SDVO_ENABLE) == 0)
1336                         intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
1337                 for (i = 0; i < 2; i++)
1338                   intel_wait_for_vblank(dev);
1339
1340                 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
1341                                                        &input2);
1342
1343
1344                 /* Warn if the device reported failure to sync.
1345                  * A lot of SDVO devices fail to notify of sync, but it's
1346                  * a given it the status is a success, we succeeded.
1347                  */
1348                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1349                         DRM_DEBUG_KMS("First %s output reported failure to "
1350                                         "sync\n", SDVO_NAME(sdvo_priv));
1351                 }
1352
1353                 if (0)
1354                         intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1355                 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->controlled_output);
1356         }
1357         return;
1358 }
1359
1360 static void intel_sdvo_save(struct drm_connector *connector)
1361 {
1362         struct drm_device *dev = connector->dev;
1363         struct drm_i915_private *dev_priv = dev->dev_private;
1364         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1365         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1366         int o;
1367
1368         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_encoder);
1369         intel_sdvo_get_active_outputs(intel_encoder, &sdvo_priv->save_active_outputs);
1370
1371         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1372                 intel_sdvo_set_target_input(intel_encoder, true, false);
1373                 intel_sdvo_get_input_timing(intel_encoder,
1374                                             &sdvo_priv->save_input_dtd_1);
1375         }
1376
1377         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1378                 intel_sdvo_set_target_input(intel_encoder, false, true);
1379                 intel_sdvo_get_input_timing(intel_encoder,
1380                                             &sdvo_priv->save_input_dtd_2);
1381         }
1382
1383         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1384         {
1385                 u16  this_output = (1 << o);
1386                 if (sdvo_priv->caps.output_flags & this_output)
1387                 {
1388                         intel_sdvo_set_target_output(intel_encoder, this_output);
1389                         intel_sdvo_get_output_timing(intel_encoder,
1390                                                      &sdvo_priv->save_output_dtd[o]);
1391                 }
1392         }
1393         if (sdvo_priv->is_tv) {
1394                 /* XXX: Save TV format/enhancements. */
1395         }
1396
1397         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->sdvo_reg);
1398 }
1399
1400 static void intel_sdvo_restore(struct drm_connector *connector)
1401 {
1402         struct drm_device *dev = connector->dev;
1403         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1404         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1405         int o;
1406         int i;
1407         bool input1, input2;
1408         u8 status;
1409
1410         intel_sdvo_set_active_outputs(intel_encoder, 0);
1411
1412         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1413         {
1414                 u16  this_output = (1 << o);
1415                 if (sdvo_priv->caps.output_flags & this_output) {
1416                         intel_sdvo_set_target_output(intel_encoder, this_output);
1417                         intel_sdvo_set_output_timing(intel_encoder, &sdvo_priv->save_output_dtd[o]);
1418                 }
1419         }
1420
1421         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1422                 intel_sdvo_set_target_input(intel_encoder, true, false);
1423                 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_1);
1424         }
1425
1426         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1427                 intel_sdvo_set_target_input(intel_encoder, false, true);
1428                 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_2);
1429         }
1430
1431         intel_sdvo_set_clock_rate_mult(intel_encoder, sdvo_priv->save_sdvo_mult);
1432
1433         if (sdvo_priv->is_tv) {
1434                 /* XXX: Restore TV format/enhancements. */
1435         }
1436
1437         intel_sdvo_write_sdvox(intel_encoder, sdvo_priv->save_SDVOX);
1438
1439         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1440         {
1441                 for (i = 0; i < 2; i++)
1442                         intel_wait_for_vblank(dev);
1443                 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1, &input2);
1444                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1445                         DRM_DEBUG_KMS("First %s output reported failure to "
1446                                         "sync\n", SDVO_NAME(sdvo_priv));
1447         }
1448
1449         intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->save_active_outputs);
1450 }
1451
1452 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1453                                  struct drm_display_mode *mode)
1454 {
1455         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1456         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1457
1458         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1459                 return MODE_NO_DBLESCAN;
1460
1461         if (sdvo_priv->pixel_clock_min > mode->clock)
1462                 return MODE_CLOCK_LOW;
1463
1464         if (sdvo_priv->pixel_clock_max < mode->clock)
1465                 return MODE_CLOCK_HIGH;
1466
1467         if (sdvo_priv->is_lvds == true) {
1468                 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1469                         return MODE_PANEL;
1470
1471                 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1472                         return MODE_PANEL;
1473
1474                 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1475                         return MODE_PANEL;
1476         }
1477
1478         return MODE_OK;
1479 }
1480
1481 static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
1482 {
1483         u8 status;
1484
1485         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1486         status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
1487         if (status != SDVO_CMD_STATUS_SUCCESS)
1488                 return false;
1489
1490         return true;
1491 }
1492
1493 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1494 {
1495         struct drm_connector *connector = NULL;
1496         struct intel_encoder *iout = NULL;
1497         struct intel_sdvo_priv *sdvo;
1498
1499         /* find the sdvo connector */
1500         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1501                 iout = to_intel_encoder(connector);
1502
1503                 if (iout->type != INTEL_OUTPUT_SDVO)
1504                         continue;
1505
1506                 sdvo = iout->dev_priv;
1507
1508                 if (sdvo->sdvo_reg == SDVOB && sdvoB)
1509                         return connector;
1510
1511                 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
1512                         return connector;
1513
1514         }
1515
1516         return NULL;
1517 }
1518
1519 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1520 {
1521         u8 response[2];
1522         u8 status;
1523         struct intel_encoder *intel_encoder;
1524         DRM_DEBUG_KMS("\n");
1525
1526         if (!connector)
1527                 return 0;
1528
1529         intel_encoder = to_intel_encoder(connector);
1530
1531         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1532         status = intel_sdvo_read_response(intel_encoder, &response, 2);
1533
1534         if (response[0] !=0)
1535                 return 1;
1536
1537         return 0;
1538 }
1539
1540 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1541 {
1542         u8 response[2];
1543         u8 status;
1544         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1545
1546         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1547         intel_sdvo_read_response(intel_encoder, &response, 2);
1548
1549         if (on) {
1550                 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1551                 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1552
1553                 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1554         } else {
1555                 response[0] = 0;
1556                 response[1] = 0;
1557                 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1558         }
1559
1560         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1561         intel_sdvo_read_response(intel_encoder, &response, 2);
1562 }
1563
1564 static bool
1565 intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
1566 {
1567         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1568         int caps = 0;
1569
1570         if (sdvo_priv->caps.output_flags &
1571                 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1572                 caps++;
1573         if (sdvo_priv->caps.output_flags &
1574                 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1575                 caps++;
1576         if (sdvo_priv->caps.output_flags &
1577                 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1578                 caps++;
1579         if (sdvo_priv->caps.output_flags &
1580                 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1581                 caps++;
1582         if (sdvo_priv->caps.output_flags &
1583                 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1584                 caps++;
1585
1586         if (sdvo_priv->caps.output_flags &
1587                 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1588                 caps++;
1589
1590         if (sdvo_priv->caps.output_flags &
1591                 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1592                 caps++;
1593
1594         return (caps > 1);
1595 }
1596
1597 static struct drm_connector *
1598 intel_find_analog_connector(struct drm_device *dev)
1599 {
1600         struct drm_connector *connector;
1601         struct intel_encoder *intel_encoder;
1602
1603         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1604                 intel_encoder = to_intel_encoder(connector);
1605                 if (intel_encoder->type == INTEL_OUTPUT_ANALOG)
1606                         return connector;
1607         }
1608         return NULL;
1609 }
1610
1611 static int
1612 intel_analog_is_connected(struct drm_device *dev)
1613 {
1614         struct drm_connector *analog_connector;
1615         analog_connector = intel_find_analog_connector(dev);
1616
1617         if (!analog_connector)
1618                 return false;
1619
1620         if (analog_connector->funcs->detect(analog_connector) ==
1621                         connector_status_disconnected)
1622                 return false;
1623
1624         return true;
1625 }
1626
1627 enum drm_connector_status
1628 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1629 {
1630         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1631         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1632         enum drm_connector_status status = connector_status_connected;
1633         struct edid *edid = NULL;
1634
1635         edid = drm_get_edid(&intel_encoder->base,
1636                             intel_encoder->ddc_bus);
1637
1638         /* This is only applied to SDVO cards with multiple outputs */
1639         if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
1640                 uint8_t saved_ddc, temp_ddc;
1641                 saved_ddc = sdvo_priv->ddc_bus;
1642                 temp_ddc = sdvo_priv->ddc_bus >> 1;
1643                 /*
1644                  * Don't use the 1 as the argument of DDC bus switch to get
1645                  * the EDID. It is used for SDVO SPD ROM.
1646                  */
1647                 while(temp_ddc > 1) {
1648                         sdvo_priv->ddc_bus = temp_ddc;
1649                         edid = drm_get_edid(&intel_encoder->base,
1650                                 intel_encoder->ddc_bus);
1651                         if (edid) {
1652                                 /*
1653                                  * When we can get the EDID, maybe it is the
1654                                  * correct DDC bus. Update it.
1655                                  */
1656                                 sdvo_priv->ddc_bus = temp_ddc;
1657                                 break;
1658                         }
1659                         temp_ddc >>= 1;
1660                 }
1661                 if (edid == NULL)
1662                         sdvo_priv->ddc_bus = saved_ddc;
1663         }
1664         /* when there is no edid and no monitor is connected with VGA
1665          * port, try to use the CRT ddc to read the EDID for DVI-connector
1666          */
1667         if (edid == NULL &&
1668             sdvo_priv->analog_ddc_bus &&
1669             !intel_analog_is_connected(intel_encoder->base.dev))
1670                 edid = drm_get_edid(&intel_encoder->base,
1671                                     sdvo_priv->analog_ddc_bus);
1672         if (edid != NULL) {
1673                 /* Don't report the output as connected if it's a DVI-I
1674                  * connector with a non-digital EDID coming out.
1675                  */
1676                 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1677                         if (edid->input & DRM_EDID_INPUT_DIGITAL)
1678                                 sdvo_priv->is_hdmi =
1679                                         drm_detect_hdmi_monitor(edid);
1680                         else
1681                                 status = connector_status_disconnected;
1682                 }
1683
1684                 kfree(edid);
1685                 intel_encoder->base.display_info.raw_edid = NULL;
1686
1687         } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1688                 status = connector_status_disconnected;
1689
1690         return status;
1691 }
1692
1693 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1694 {
1695         uint16_t response;
1696         u8 status;
1697         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1698         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1699
1700         intel_sdvo_write_cmd(intel_encoder,
1701                              SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1702         if (sdvo_priv->is_tv) {
1703                 /* add 30ms delay when the output type is SDVO-TV */
1704                 mdelay(30);
1705         }
1706         status = intel_sdvo_read_response(intel_encoder, &response, 2);
1707
1708         DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1709
1710         if (status != SDVO_CMD_STATUS_SUCCESS)
1711                 return connector_status_unknown;
1712
1713         if (response == 0)
1714                 return connector_status_disconnected;
1715
1716         if (intel_sdvo_multifunc_encoder(intel_encoder) &&
1717                 sdvo_priv->attached_output != response) {
1718                 if (sdvo_priv->controlled_output != response &&
1719                         intel_sdvo_output_setup(intel_encoder, response) != true)
1720                         return connector_status_unknown;
1721                 sdvo_priv->attached_output = response;
1722         }
1723         return intel_sdvo_hdmi_sink_detect(connector, response);
1724 }
1725
1726 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1727 {
1728         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1729         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1730         int num_modes;
1731
1732         /* set the bus switch and get the modes */
1733         num_modes = intel_ddc_get_modes(intel_encoder);
1734
1735         /*
1736          * Mac mini hack.  On this device, the DVI-I connector shares one DDC
1737          * link between analog and digital outputs. So, if the regular SDVO
1738          * DDC fails, check to see if the analog output is disconnected, in
1739          * which case we'll look there for the digital DDC data.
1740          */
1741         if (num_modes == 0 &&
1742             sdvo_priv->analog_ddc_bus &&
1743             !intel_analog_is_connected(intel_encoder->base.dev)) {
1744                 struct i2c_adapter *digital_ddc_bus;
1745
1746                 /* Switch to the analog ddc bus and try that
1747                  */
1748                 digital_ddc_bus = intel_encoder->ddc_bus;
1749                 intel_encoder->ddc_bus = sdvo_priv->analog_ddc_bus;
1750
1751                 (void) intel_ddc_get_modes(intel_encoder);
1752
1753                 intel_encoder->ddc_bus = digital_ddc_bus;
1754         }
1755 }
1756
1757 /*
1758  * Set of SDVO TV modes.
1759  * Note!  This is in reply order (see loop in get_tv_modes).
1760  * XXX: all 60Hz refresh?
1761  */
1762 struct drm_display_mode sdvo_tv_modes[] = {
1763         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1764                    416, 0, 200, 201, 232, 233, 0,
1765                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1766         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1767                    416, 0, 240, 241, 272, 273, 0,
1768                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1769         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1770                    496, 0, 300, 301, 332, 333, 0,
1771                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1772         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1773                    736, 0, 350, 351, 382, 383, 0,
1774                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1775         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1776                    736, 0, 400, 401, 432, 433, 0,
1777                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1778         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1779                    736, 0, 480, 481, 512, 513, 0,
1780                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1781         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1782                    800, 0, 480, 481, 512, 513, 0,
1783                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1784         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1785                    800, 0, 576, 577, 608, 609, 0,
1786                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1787         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1788                    816, 0, 350, 351, 382, 383, 0,
1789                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1790         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1791                    816, 0, 400, 401, 432, 433, 0,
1792                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1793         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1794                    816, 0, 480, 481, 512, 513, 0,
1795                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1796         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1797                    816, 0, 540, 541, 572, 573, 0,
1798                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1799         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1800                    816, 0, 576, 577, 608, 609, 0,
1801                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1802         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1803                    864, 0, 576, 577, 608, 609, 0,
1804                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1805         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1806                    896, 0, 600, 601, 632, 633, 0,
1807                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1808         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1809                    928, 0, 624, 625, 656, 657, 0,
1810                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1811         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1812                    1016, 0, 766, 767, 798, 799, 0,
1813                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1814         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1815                    1120, 0, 768, 769, 800, 801, 0,
1816                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1817         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1818                    1376, 0, 1024, 1025, 1056, 1057, 0,
1819                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1820 };
1821
1822 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1823 {
1824         struct intel_encoder *output = to_intel_encoder(connector);
1825         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1826         struct intel_sdvo_sdtv_resolution_request tv_res;
1827         uint32_t reply = 0, format_map = 0;
1828         int i;
1829         uint8_t status;
1830
1831
1832         /* Read the list of supported input resolutions for the selected TV
1833          * format.
1834          */
1835         for (i = 0; i < TV_FORMAT_NUM; i++)
1836                 if (tv_format_names[i] ==  sdvo_priv->tv_format_name)
1837                         break;
1838
1839         format_map = (1 << i);
1840         memcpy(&tv_res, &format_map,
1841                sizeof(struct intel_sdvo_sdtv_resolution_request) >
1842                sizeof(format_map) ? sizeof(format_map) :
1843                sizeof(struct intel_sdvo_sdtv_resolution_request));
1844
1845         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1846
1847         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1848                              &tv_res, sizeof(tv_res));
1849         status = intel_sdvo_read_response(output, &reply, 3);
1850         if (status != SDVO_CMD_STATUS_SUCCESS)
1851                 return;
1852
1853         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1854                 if (reply & (1 << i)) {
1855                         struct drm_display_mode *nmode;
1856                         nmode = drm_mode_duplicate(connector->dev,
1857                                         &sdvo_tv_modes[i]);
1858                         if (nmode)
1859                                 drm_mode_probed_add(connector, nmode);
1860                 }
1861
1862 }
1863
1864 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1865 {
1866         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1867         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1868         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1869         struct drm_display_mode *newmode;
1870
1871         /*
1872          * Attempt to get the mode list from DDC.
1873          * Assume that the preferred modes are
1874          * arranged in priority order.
1875          */
1876         intel_ddc_get_modes(intel_encoder);
1877         if (list_empty(&connector->probed_modes) == false)
1878                 goto end;
1879
1880         /* Fetch modes from VBT */
1881         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1882                 newmode = drm_mode_duplicate(connector->dev,
1883                                              dev_priv->sdvo_lvds_vbt_mode);
1884                 if (newmode != NULL) {
1885                         /* Guarantee the mode is preferred */
1886                         newmode->type = (DRM_MODE_TYPE_PREFERRED |
1887                                          DRM_MODE_TYPE_DRIVER);
1888                         drm_mode_probed_add(connector, newmode);
1889                 }
1890         }
1891
1892 end:
1893         list_for_each_entry(newmode, &connector->probed_modes, head) {
1894                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1895                         sdvo_priv->sdvo_lvds_fixed_mode =
1896                                 drm_mode_duplicate(connector->dev, newmode);
1897                         break;
1898                 }
1899         }
1900
1901 }
1902
1903 static int intel_sdvo_get_modes(struct drm_connector *connector)
1904 {
1905         struct intel_encoder *output = to_intel_encoder(connector);
1906         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1907
1908         if (sdvo_priv->is_tv)
1909                 intel_sdvo_get_tv_modes(connector);
1910         else if (sdvo_priv->is_lvds == true)
1911                 intel_sdvo_get_lvds_modes(connector);
1912         else
1913                 intel_sdvo_get_ddc_modes(connector);
1914
1915         if (list_empty(&connector->probed_modes))
1916                 return 0;
1917         return 1;
1918 }
1919
1920 static
1921 void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1922 {
1923         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1924         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1925         struct drm_device *dev = connector->dev;
1926
1927         if (sdvo_priv->is_tv) {
1928                 if (sdvo_priv->left_property)
1929                         drm_property_destroy(dev, sdvo_priv->left_property);
1930                 if (sdvo_priv->right_property)
1931                         drm_property_destroy(dev, sdvo_priv->right_property);
1932                 if (sdvo_priv->top_property)
1933                         drm_property_destroy(dev, sdvo_priv->top_property);
1934                 if (sdvo_priv->bottom_property)
1935                         drm_property_destroy(dev, sdvo_priv->bottom_property);
1936                 if (sdvo_priv->hpos_property)
1937                         drm_property_destroy(dev, sdvo_priv->hpos_property);
1938                 if (sdvo_priv->vpos_property)
1939                         drm_property_destroy(dev, sdvo_priv->vpos_property);
1940         }
1941         if (sdvo_priv->is_tv) {
1942                 if (sdvo_priv->saturation_property)
1943                         drm_property_destroy(dev,
1944                                         sdvo_priv->saturation_property);
1945                 if (sdvo_priv->contrast_property)
1946                         drm_property_destroy(dev,
1947                                         sdvo_priv->contrast_property);
1948                 if (sdvo_priv->hue_property)
1949                         drm_property_destroy(dev, sdvo_priv->hue_property);
1950         }
1951         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1952                 if (sdvo_priv->brightness_property)
1953                         drm_property_destroy(dev,
1954                                         sdvo_priv->brightness_property);
1955         }
1956         return;
1957 }
1958
1959 static void intel_sdvo_destroy(struct drm_connector *connector)
1960 {
1961         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1962         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1963
1964         if (intel_encoder->i2c_bus)
1965                 intel_i2c_destroy(intel_encoder->i2c_bus);
1966         if (intel_encoder->ddc_bus)
1967                 intel_i2c_destroy(intel_encoder->ddc_bus);
1968         if (sdvo_priv->analog_ddc_bus)
1969                 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1970
1971         if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1972                 drm_mode_destroy(connector->dev,
1973                                  sdvo_priv->sdvo_lvds_fixed_mode);
1974
1975         if (sdvo_priv->tv_format_property)
1976                 drm_property_destroy(connector->dev,
1977                                      sdvo_priv->tv_format_property);
1978
1979         if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
1980                 intel_sdvo_destroy_enhance_property(connector);
1981
1982         drm_sysfs_connector_remove(connector);
1983         drm_connector_cleanup(connector);
1984
1985         kfree(intel_encoder);
1986 }
1987
1988 static int
1989 intel_sdvo_set_property(struct drm_connector *connector,
1990                         struct drm_property *property,
1991                         uint64_t val)
1992 {
1993         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1994         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1995         struct drm_encoder *encoder = &intel_encoder->enc;
1996         struct drm_crtc *crtc = encoder->crtc;
1997         int ret = 0;
1998         bool changed = false;
1999         uint8_t cmd, status;
2000         uint16_t temp_value;
2001
2002         ret = drm_connector_property_set_value(connector, property, val);
2003         if (ret < 0)
2004                 goto out;
2005
2006         if (property == sdvo_priv->tv_format_property) {
2007                 if (val >= TV_FORMAT_NUM) {
2008                         ret = -EINVAL;
2009                         goto out;
2010                 }
2011                 if (sdvo_priv->tv_format_name ==
2012                     sdvo_priv->tv_format_supported[val])
2013                         goto out;
2014
2015                 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
2016                 changed = true;
2017         }
2018
2019         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2020                 cmd = 0;
2021                 temp_value = val;
2022                 if (sdvo_priv->left_property == property) {
2023                         drm_connector_property_set_value(connector,
2024                                 sdvo_priv->right_property, val);
2025                         if (sdvo_priv->left_margin == temp_value)
2026                                 goto out;
2027
2028                         sdvo_priv->left_margin = temp_value;
2029                         sdvo_priv->right_margin = temp_value;
2030                         temp_value = sdvo_priv->max_hscan -
2031                                         sdvo_priv->left_margin;
2032                         cmd = SDVO_CMD_SET_OVERSCAN_H;
2033                 } else if (sdvo_priv->right_property == property) {
2034                         drm_connector_property_set_value(connector,
2035                                 sdvo_priv->left_property, val);
2036                         if (sdvo_priv->right_margin == temp_value)
2037                                 goto out;
2038
2039                         sdvo_priv->left_margin = temp_value;
2040                         sdvo_priv->right_margin = temp_value;
2041                         temp_value = sdvo_priv->max_hscan -
2042                                 sdvo_priv->left_margin;
2043                         cmd = SDVO_CMD_SET_OVERSCAN_H;
2044                 } else if (sdvo_priv->top_property == property) {
2045                         drm_connector_property_set_value(connector,
2046                                 sdvo_priv->bottom_property, val);
2047                         if (sdvo_priv->top_margin == temp_value)
2048                                 goto out;
2049
2050                         sdvo_priv->top_margin = temp_value;
2051                         sdvo_priv->bottom_margin = temp_value;
2052                         temp_value = sdvo_priv->max_vscan -
2053                                         sdvo_priv->top_margin;
2054                         cmd = SDVO_CMD_SET_OVERSCAN_V;
2055                 } else if (sdvo_priv->bottom_property == property) {
2056                         drm_connector_property_set_value(connector,
2057                                 sdvo_priv->top_property, val);
2058                         if (sdvo_priv->bottom_margin == temp_value)
2059                                 goto out;
2060                         sdvo_priv->top_margin = temp_value;
2061                         sdvo_priv->bottom_margin = temp_value;
2062                         temp_value = sdvo_priv->max_vscan -
2063                                         sdvo_priv->top_margin;
2064                         cmd = SDVO_CMD_SET_OVERSCAN_V;
2065                 } else if (sdvo_priv->hpos_property == property) {
2066                         if (sdvo_priv->cur_hpos == temp_value)
2067                                 goto out;
2068
2069                         cmd = SDVO_CMD_SET_POSITION_H;
2070                         sdvo_priv->cur_hpos = temp_value;
2071                 } else if (sdvo_priv->vpos_property == property) {
2072                         if (sdvo_priv->cur_vpos == temp_value)
2073                                 goto out;
2074
2075                         cmd = SDVO_CMD_SET_POSITION_V;
2076                         sdvo_priv->cur_vpos = temp_value;
2077                 } else if (sdvo_priv->saturation_property == property) {
2078                         if (sdvo_priv->cur_saturation == temp_value)
2079                                 goto out;
2080
2081                         cmd = SDVO_CMD_SET_SATURATION;
2082                         sdvo_priv->cur_saturation = temp_value;
2083                 } else if (sdvo_priv->contrast_property == property) {
2084                         if (sdvo_priv->cur_contrast == temp_value)
2085                                 goto out;
2086
2087                         cmd = SDVO_CMD_SET_CONTRAST;
2088                         sdvo_priv->cur_contrast = temp_value;
2089                 } else if (sdvo_priv->hue_property == property) {
2090                         if (sdvo_priv->cur_hue == temp_value)
2091                                 goto out;
2092
2093                         cmd = SDVO_CMD_SET_HUE;
2094                         sdvo_priv->cur_hue = temp_value;
2095                 } else if (sdvo_priv->brightness_property == property) {
2096                         if (sdvo_priv->cur_brightness == temp_value)
2097                                 goto out;
2098
2099                         cmd = SDVO_CMD_SET_BRIGHTNESS;
2100                         sdvo_priv->cur_brightness = temp_value;
2101                 }
2102                 if (cmd) {
2103                         intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
2104                         status = intel_sdvo_read_response(intel_encoder,
2105                                                                 NULL, 0);
2106                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2107                                 DRM_DEBUG_KMS("Incorrect SDVO command \n");
2108                                 return -EINVAL;
2109                         }
2110                         changed = true;
2111                 }
2112         }
2113         if (changed && crtc)
2114                 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2115                                 crtc->y, crtc->fb);
2116 out:
2117         return ret;
2118 }
2119
2120 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2121         .dpms = intel_sdvo_dpms,
2122         .mode_fixup = intel_sdvo_mode_fixup,
2123         .prepare = intel_encoder_prepare,
2124         .mode_set = intel_sdvo_mode_set,
2125         .commit = intel_encoder_commit,
2126 };
2127
2128 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2129         .dpms = drm_helper_connector_dpms,
2130         .save = intel_sdvo_save,
2131         .restore = intel_sdvo_restore,
2132         .detect = intel_sdvo_detect,
2133         .fill_modes = drm_helper_probe_single_connector_modes,
2134         .set_property = intel_sdvo_set_property,
2135         .destroy = intel_sdvo_destroy,
2136 };
2137
2138 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2139         .get_modes = intel_sdvo_get_modes,
2140         .mode_valid = intel_sdvo_mode_valid,
2141         .best_encoder = intel_best_encoder,
2142 };
2143
2144 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2145 {
2146         drm_encoder_cleanup(encoder);
2147 }
2148
2149 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2150         .destroy = intel_sdvo_enc_destroy,
2151 };
2152
2153
2154 /**
2155  * Choose the appropriate DDC bus for control bus switch command for this
2156  * SDVO output based on the controlled output.
2157  *
2158  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2159  * outputs, then LVDS outputs.
2160  */
2161 static void
2162 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2163 {
2164         uint16_t mask = 0;
2165         unsigned int num_bits;
2166
2167         /* Make a mask of outputs less than or equal to our own priority in the
2168          * list.
2169          */
2170         switch (dev_priv->controlled_output) {
2171         case SDVO_OUTPUT_LVDS1:
2172                 mask |= SDVO_OUTPUT_LVDS1;
2173         case SDVO_OUTPUT_LVDS0:
2174                 mask |= SDVO_OUTPUT_LVDS0;
2175         case SDVO_OUTPUT_TMDS1:
2176                 mask |= SDVO_OUTPUT_TMDS1;
2177         case SDVO_OUTPUT_TMDS0:
2178                 mask |= SDVO_OUTPUT_TMDS0;
2179         case SDVO_OUTPUT_RGB1:
2180                 mask |= SDVO_OUTPUT_RGB1;
2181         case SDVO_OUTPUT_RGB0:
2182                 mask |= SDVO_OUTPUT_RGB0;
2183                 break;
2184         }
2185
2186         /* Count bits to find what number we are in the priority list. */
2187         mask &= dev_priv->caps.output_flags;
2188         num_bits = hweight16(mask);
2189         if (num_bits > 3) {
2190                 /* if more than 3 outputs, default to DDC bus 3 for now */
2191                 num_bits = 3;
2192         }
2193
2194         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2195         dev_priv->ddc_bus = 1 << num_bits;
2196 }
2197
2198 static bool
2199 intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output)
2200 {
2201         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2202         uint8_t status;
2203
2204         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2205
2206         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2207         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2208         if (status != SDVO_CMD_STATUS_SUCCESS)
2209                 return false;
2210         return true;
2211 }
2212
2213 static struct intel_encoder *
2214 intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
2215 {
2216         struct drm_device *dev = chan->drm_dev;
2217         struct drm_connector *connector;
2218         struct intel_encoder *intel_encoder = NULL;
2219
2220         list_for_each_entry(connector,
2221                         &dev->mode_config.connector_list, head) {
2222                 if (to_intel_encoder(connector)->ddc_bus == &chan->adapter) {
2223                         intel_encoder = to_intel_encoder(connector);
2224                         break;
2225                 }
2226         }
2227         return intel_encoder;
2228 }
2229
2230 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2231                                   struct i2c_msg msgs[], int num)
2232 {
2233         struct intel_encoder *intel_encoder;
2234         struct intel_sdvo_priv *sdvo_priv;
2235         struct i2c_algo_bit_data *algo_data;
2236         const struct i2c_algorithm *algo;
2237
2238         algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2239         intel_encoder =
2240                 intel_sdvo_chan_to_intel_encoder(
2241                                 (struct intel_i2c_chan *)(algo_data->data));
2242         if (intel_encoder == NULL)
2243                 return -EINVAL;
2244
2245         sdvo_priv = intel_encoder->dev_priv;
2246         algo = intel_encoder->i2c_bus->algo;
2247
2248         intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
2249         return algo->master_xfer(i2c_adap, msgs, num);
2250 }
2251
2252 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2253         .master_xfer    = intel_sdvo_master_xfer,
2254 };
2255
2256 static u8
2257 intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
2258 {
2259         struct drm_i915_private *dev_priv = dev->dev_private;
2260         struct sdvo_device_mapping *my_mapping, *other_mapping;
2261
2262         if (sdvo_reg == SDVOB) {
2263                 my_mapping = &dev_priv->sdvo_mappings[0];
2264                 other_mapping = &dev_priv->sdvo_mappings[1];
2265         } else {
2266                 my_mapping = &dev_priv->sdvo_mappings[1];
2267                 other_mapping = &dev_priv->sdvo_mappings[0];
2268         }
2269
2270         /* If the BIOS described our SDVO device, take advantage of it. */
2271         if (my_mapping->slave_addr)
2272                 return my_mapping->slave_addr;
2273
2274         /* If the BIOS only described a different SDVO device, use the
2275          * address that it isn't using.
2276          */
2277         if (other_mapping->slave_addr) {
2278                 if (other_mapping->slave_addr == 0x70)
2279                         return 0x72;
2280                 else
2281                         return 0x70;
2282         }
2283
2284         /* No SDVO device info is found for another DVO port,
2285          * so use mapping assumption we had before BIOS parsing.
2286          */
2287         if (sdvo_reg == SDVOB)
2288                 return 0x70;
2289         else
2290                 return 0x72;
2291 }
2292
2293 static int intel_sdvo_bad_tv_callback(const struct dmi_system_id *id)
2294 {
2295         DRM_DEBUG_KMS("Ignoring bad SDVO TV connector for %s\n", id->ident);
2296         return 1;
2297 }
2298
2299 static struct dmi_system_id intel_sdvo_bad_tv[] = {
2300         {
2301                 .callback = intel_sdvo_bad_tv_callback,
2302                 .ident = "IntelG45/ICH10R/DME1737",
2303                 .matches = {
2304                         DMI_MATCH(DMI_SYS_VENDOR, "IBM CORPORATION"),
2305                         DMI_MATCH(DMI_PRODUCT_NAME, "4800784"),
2306                 },
2307         },
2308
2309         { }     /* terminating entry */
2310 };
2311
2312 static bool
2313 intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
2314 {
2315         struct drm_connector *connector = &intel_encoder->base;
2316         struct drm_encoder *encoder = &intel_encoder->enc;
2317         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2318         bool ret = true, registered = false;
2319
2320         sdvo_priv->is_tv = false;
2321         intel_encoder->needs_tv_clock = false;
2322         sdvo_priv->is_lvds = false;
2323
2324         if (device_is_registered(&connector->kdev)) {
2325                 drm_sysfs_connector_remove(connector);
2326                 registered = true;
2327         }
2328
2329         if (flags &
2330             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2331                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2332                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2333                 else
2334                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2335
2336                 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2337                 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2338
2339                 if (intel_sdvo_get_supp_encode(intel_encoder,
2340                                                &sdvo_priv->encode) &&
2341                     intel_sdvo_get_digital_encoding_mode(intel_encoder) &&
2342                     sdvo_priv->is_hdmi) {
2343                         /* enable hdmi encoding mode if supported */
2344                         intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
2345                         intel_sdvo_set_colorimetry(intel_encoder,
2346                                                    SDVO_COLORIMETRY_RGB256);
2347                         connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2348                         intel_encoder->clone_mask =
2349                                         (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2350                                         (1 << INTEL_ANALOG_CLONE_BIT);
2351                 }
2352         } else if ((flags & SDVO_OUTPUT_SVID0) &&
2353                    !dmi_check_system(intel_sdvo_bad_tv)) {
2354
2355                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2356                 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2357                 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2358                 sdvo_priv->is_tv = true;
2359                 intel_encoder->needs_tv_clock = true;
2360                 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2361         } else if (flags & SDVO_OUTPUT_RGB0) {
2362
2363                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2364                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2365                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2366                 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2367                                         (1 << INTEL_ANALOG_CLONE_BIT);
2368         } else if (flags & SDVO_OUTPUT_RGB1) {
2369
2370                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2371                 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2372                 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2373                 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2374                                         (1 << INTEL_ANALOG_CLONE_BIT);
2375         } else if (flags & SDVO_OUTPUT_CVBS0) {
2376
2377                 sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0;
2378                 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2379                 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2380                 sdvo_priv->is_tv = true;
2381                 intel_encoder->needs_tv_clock = true;
2382                 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2383         } else if (flags & SDVO_OUTPUT_LVDS0) {
2384
2385                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2386                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2387                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2388                 sdvo_priv->is_lvds = true;
2389                 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2390                                         (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2391         } else if (flags & SDVO_OUTPUT_LVDS1) {
2392
2393                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2394                 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2395                 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2396                 sdvo_priv->is_lvds = true;
2397                 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2398                                         (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2399         } else {
2400
2401                 unsigned char bytes[2];
2402
2403                 sdvo_priv->controlled_output = 0;
2404                 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2405                 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2406                               SDVO_NAME(sdvo_priv),
2407                               bytes[0], bytes[1]);
2408                 ret = false;
2409         }
2410         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2411
2412         if (ret && registered)
2413                 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2414
2415
2416         return ret;
2417
2418 }
2419
2420 static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2421 {
2422       struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2423         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2424         struct intel_sdvo_tv_format format;
2425         uint32_t format_map, i;
2426         uint8_t status;
2427
2428         intel_sdvo_set_target_output(intel_encoder,
2429                                      sdvo_priv->controlled_output);
2430
2431         intel_sdvo_write_cmd(intel_encoder,
2432                              SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2433         status = intel_sdvo_read_response(intel_encoder,
2434                                           &format, sizeof(format));
2435         if (status != SDVO_CMD_STATUS_SUCCESS)
2436                 return;
2437
2438         memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2439                sizeof(format_map) : sizeof(format));
2440
2441         if (format_map == 0)
2442                 return;
2443
2444         sdvo_priv->format_supported_num = 0;
2445         for (i = 0 ; i < TV_FORMAT_NUM; i++)
2446                 if (format_map & (1 << i)) {
2447                         sdvo_priv->tv_format_supported
2448                         [sdvo_priv->format_supported_num++] =
2449                         tv_format_names[i];
2450                 }
2451
2452
2453         sdvo_priv->tv_format_property =
2454                         drm_property_create(
2455                                 connector->dev, DRM_MODE_PROP_ENUM,
2456                                 "mode", sdvo_priv->format_supported_num);
2457
2458         for (i = 0; i < sdvo_priv->format_supported_num; i++)
2459                 drm_property_add_enum(
2460                                 sdvo_priv->tv_format_property, i,
2461                                 i, sdvo_priv->tv_format_supported[i]);
2462
2463         sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2464         drm_connector_attach_property(
2465                         connector, sdvo_priv->tv_format_property, 0);
2466
2467 }
2468
2469 static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2470 {
2471         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2472         struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2473         struct intel_sdvo_enhancements_reply sdvo_data;
2474         struct drm_device *dev = connector->dev;
2475         uint8_t status;
2476         uint16_t response, data_value[2];
2477
2478         intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2479                                                 NULL, 0);
2480         status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
2481                                         sizeof(sdvo_data));
2482         if (status != SDVO_CMD_STATUS_SUCCESS) {
2483                 DRM_DEBUG_KMS(" incorrect response is returned\n");
2484                 return;
2485         }
2486         response = *((uint16_t *)&sdvo_data);
2487         if (!response) {
2488                 DRM_DEBUG_KMS("No enhancement is supported\n");
2489                 return;
2490         }
2491         if (sdvo_priv->is_tv) {
2492                 /* when horizontal overscan is supported, Add the left/right
2493                  * property
2494                  */
2495                 if (sdvo_data.overscan_h) {
2496                         intel_sdvo_write_cmd(intel_encoder,
2497                                 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2498                         status = intel_sdvo_read_response(intel_encoder,
2499                                 &data_value, 4);
2500                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2501                                 DRM_DEBUG_KMS("Incorrect SDVO max "
2502                                                 "h_overscan\n");
2503                                 return;
2504                         }
2505                         intel_sdvo_write_cmd(intel_encoder,
2506                                 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2507                         status = intel_sdvo_read_response(intel_encoder,
2508                                 &response, 2);
2509                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2510                                 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2511                                 return;
2512                         }
2513                         sdvo_priv->max_hscan = data_value[0];
2514                         sdvo_priv->left_margin = data_value[0] - response;
2515                         sdvo_priv->right_margin = sdvo_priv->left_margin;
2516                         sdvo_priv->left_property =
2517                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2518                                                 "left_margin", 2);
2519                         sdvo_priv->left_property->values[0] = 0;
2520                         sdvo_priv->left_property->values[1] = data_value[0];
2521                         drm_connector_attach_property(connector,
2522                                                 sdvo_priv->left_property,
2523                                                 sdvo_priv->left_margin);
2524                         sdvo_priv->right_property =
2525                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2526                                                 "right_margin", 2);
2527                         sdvo_priv->right_property->values[0] = 0;
2528                         sdvo_priv->right_property->values[1] = data_value[0];
2529                         drm_connector_attach_property(connector,
2530                                                 sdvo_priv->right_property,
2531                                                 sdvo_priv->right_margin);
2532                         DRM_DEBUG_KMS("h_overscan: max %d, "
2533                                         "default %d, current %d\n",
2534                                         data_value[0], data_value[1], response);
2535                 }
2536                 if (sdvo_data.overscan_v) {
2537                         intel_sdvo_write_cmd(intel_encoder,
2538                                 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2539                         status = intel_sdvo_read_response(intel_encoder,
2540                                 &data_value, 4);
2541                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2542                                 DRM_DEBUG_KMS("Incorrect SDVO max "
2543                                                 "v_overscan\n");
2544                                 return;
2545                         }
2546                         intel_sdvo_write_cmd(intel_encoder,
2547                                 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2548                         status = intel_sdvo_read_response(intel_encoder,
2549                                 &response, 2);
2550                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2551                                 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2552                                 return;
2553                         }
2554                         sdvo_priv->max_vscan = data_value[0];
2555                         sdvo_priv->top_margin = data_value[0] - response;
2556                         sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2557                         sdvo_priv->top_property =
2558                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2559                                                 "top_margin", 2);
2560                         sdvo_priv->top_property->values[0] = 0;
2561                         sdvo_priv->top_property->values[1] = data_value[0];
2562                         drm_connector_attach_property(connector,
2563                                                 sdvo_priv->top_property,
2564                                                 sdvo_priv->top_margin);
2565                         sdvo_priv->bottom_property =
2566                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2567                                                 "bottom_margin", 2);
2568                         sdvo_priv->bottom_property->values[0] = 0;
2569                         sdvo_priv->bottom_property->values[1] = data_value[0];
2570                         drm_connector_attach_property(connector,
2571                                                 sdvo_priv->bottom_property,
2572                                                 sdvo_priv->bottom_margin);
2573                         DRM_DEBUG_KMS("v_overscan: max %d, "
2574                                         "default %d, current %d\n",
2575                                         data_value[0], data_value[1], response);
2576                 }
2577                 if (sdvo_data.position_h) {
2578                         intel_sdvo_write_cmd(intel_encoder,
2579                                 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2580                         status = intel_sdvo_read_response(intel_encoder,
2581                                 &data_value, 4);
2582                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2583                                 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2584                                 return;
2585                         }
2586                         intel_sdvo_write_cmd(intel_encoder,
2587                                 SDVO_CMD_GET_POSITION_H, NULL, 0);
2588                         status = intel_sdvo_read_response(intel_encoder,
2589                                 &response, 2);
2590                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2591                                 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2592                                 return;
2593                         }
2594                         sdvo_priv->max_hpos = data_value[0];
2595                         sdvo_priv->cur_hpos = response;
2596                         sdvo_priv->hpos_property =
2597                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2598                                                 "hpos", 2);
2599                         sdvo_priv->hpos_property->values[0] = 0;
2600                         sdvo_priv->hpos_property->values[1] = data_value[0];
2601                         drm_connector_attach_property(connector,
2602                                                 sdvo_priv->hpos_property,
2603                                                 sdvo_priv->cur_hpos);
2604                         DRM_DEBUG_KMS("h_position: max %d, "
2605                                         "default %d, current %d\n",
2606                                         data_value[0], data_value[1], response);
2607                 }
2608                 if (sdvo_data.position_v) {
2609                         intel_sdvo_write_cmd(intel_encoder,
2610                                 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2611                         status = intel_sdvo_read_response(intel_encoder,
2612                                 &data_value, 4);
2613                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2614                                 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2615                                 return;
2616                         }
2617                         intel_sdvo_write_cmd(intel_encoder,
2618                                 SDVO_CMD_GET_POSITION_V, NULL, 0);
2619                         status = intel_sdvo_read_response(intel_encoder,
2620                                 &response, 2);
2621                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2622                                 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2623                                 return;
2624                         }
2625                         sdvo_priv->max_vpos = data_value[0];
2626                         sdvo_priv->cur_vpos = response;
2627                         sdvo_priv->vpos_property =
2628                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2629                                                 "vpos", 2);
2630                         sdvo_priv->vpos_property->values[0] = 0;
2631                         sdvo_priv->vpos_property->values[1] = data_value[0];
2632                         drm_connector_attach_property(connector,
2633                                                 sdvo_priv->vpos_property,
2634                                                 sdvo_priv->cur_vpos);
2635                         DRM_DEBUG_KMS("v_position: max %d, "
2636                                         "default %d, current %d\n",
2637                                         data_value[0], data_value[1], response);
2638                 }
2639         }
2640         if (sdvo_priv->is_tv) {
2641                 if (sdvo_data.saturation) {
2642                         intel_sdvo_write_cmd(intel_encoder,
2643                                 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2644                         status = intel_sdvo_read_response(intel_encoder,
2645                                 &data_value, 4);
2646                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2647                                 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2648                                 return;
2649                         }
2650                         intel_sdvo_write_cmd(intel_encoder,
2651                                 SDVO_CMD_GET_SATURATION, NULL, 0);
2652                         status = intel_sdvo_read_response(intel_encoder,
2653                                 &response, 2);
2654                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2655                                 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2656                                 return;
2657                         }
2658                         sdvo_priv->max_saturation = data_value[0];
2659                         sdvo_priv->cur_saturation = response;
2660                         sdvo_priv->saturation_property =
2661                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2662                                                 "saturation", 2);
2663                         sdvo_priv->saturation_property->values[0] = 0;
2664                         sdvo_priv->saturation_property->values[1] =
2665                                                         data_value[0];
2666                         drm_connector_attach_property(connector,
2667                                                 sdvo_priv->saturation_property,
2668                                                 sdvo_priv->cur_saturation);
2669                         DRM_DEBUG_KMS("saturation: max %d, "
2670                                         "default %d, current %d\n",
2671                                         data_value[0], data_value[1], response);
2672                 }
2673                 if (sdvo_data.contrast) {
2674                         intel_sdvo_write_cmd(intel_encoder,
2675                                 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2676                         status = intel_sdvo_read_response(intel_encoder,
2677                                 &data_value, 4);
2678                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2679                                 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2680                                 return;
2681                         }
2682                         intel_sdvo_write_cmd(intel_encoder,
2683                                 SDVO_CMD_GET_CONTRAST, NULL, 0);
2684                         status = intel_sdvo_read_response(intel_encoder,
2685                                 &response, 2);
2686                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2687                                 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2688                                 return;
2689                         }
2690                         sdvo_priv->max_contrast = data_value[0];
2691                         sdvo_priv->cur_contrast = response;
2692                         sdvo_priv->contrast_property =
2693                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2694                                                 "contrast", 2);
2695                         sdvo_priv->contrast_property->values[0] = 0;
2696                         sdvo_priv->contrast_property->values[1] = data_value[0];
2697                         drm_connector_attach_property(connector,
2698                                                 sdvo_priv->contrast_property,
2699                                                 sdvo_priv->cur_contrast);
2700                         DRM_DEBUG_KMS("contrast: max %d, "
2701                                         "default %d, current %d\n",
2702                                         data_value[0], data_value[1], response);
2703                 }
2704                 if (sdvo_data.hue) {
2705                         intel_sdvo_write_cmd(intel_encoder,
2706                                 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2707                         status = intel_sdvo_read_response(intel_encoder,
2708                                 &data_value, 4);
2709                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2710                                 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2711                                 return;
2712                         }
2713                         intel_sdvo_write_cmd(intel_encoder,
2714                                 SDVO_CMD_GET_HUE, NULL, 0);
2715                         status = intel_sdvo_read_response(intel_encoder,
2716                                 &response, 2);
2717                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2718                                 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2719                                 return;
2720                         }
2721                         sdvo_priv->max_hue = data_value[0];
2722                         sdvo_priv->cur_hue = response;
2723                         sdvo_priv->hue_property =
2724                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2725                                                 "hue", 2);
2726                         sdvo_priv->hue_property->values[0] = 0;
2727                         sdvo_priv->hue_property->values[1] =
2728                                                         data_value[0];
2729                         drm_connector_attach_property(connector,
2730                                                 sdvo_priv->hue_property,
2731                                                 sdvo_priv->cur_hue);
2732                         DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2733                                         data_value[0], data_value[1], response);
2734                 }
2735         }
2736         if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2737                 if (sdvo_data.brightness) {
2738                         intel_sdvo_write_cmd(intel_encoder,
2739                                 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2740                         status = intel_sdvo_read_response(intel_encoder,
2741                                 &data_value, 4);
2742                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2743                                 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2744                                 return;
2745                         }
2746                         intel_sdvo_write_cmd(intel_encoder,
2747                                 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2748                         status = intel_sdvo_read_response(intel_encoder,
2749                                 &response, 2);
2750                         if (status != SDVO_CMD_STATUS_SUCCESS) {
2751                                 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2752                                 return;
2753                         }
2754                         sdvo_priv->max_brightness = data_value[0];
2755                         sdvo_priv->cur_brightness = response;
2756                         sdvo_priv->brightness_property =
2757                                 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2758                                                 "brightness", 2);
2759                         sdvo_priv->brightness_property->values[0] = 0;
2760                         sdvo_priv->brightness_property->values[1] =
2761                                                         data_value[0];
2762                         drm_connector_attach_property(connector,
2763                                                 sdvo_priv->brightness_property,
2764                                                 sdvo_priv->cur_brightness);
2765                         DRM_DEBUG_KMS("brightness: max %d, "
2766                                         "default %d, current %d\n",
2767                                         data_value[0], data_value[1], response);
2768                 }
2769         }
2770         return;
2771 }
2772
2773 bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2774 {
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct drm_connector *connector;
2777         struct intel_encoder *intel_encoder;
2778         struct intel_sdvo_priv *sdvo_priv;
2779
2780         u8 ch[0x40];
2781         int i;
2782
2783         intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2784         if (!intel_encoder) {
2785                 return false;
2786         }
2787
2788         sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
2789         sdvo_priv->sdvo_reg = sdvo_reg;
2790
2791         intel_encoder->dev_priv = sdvo_priv;
2792         intel_encoder->type = INTEL_OUTPUT_SDVO;
2793
2794         /* setup the DDC bus. */
2795         if (sdvo_reg == SDVOB)
2796                 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2797         else
2798                 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2799
2800         if (!intel_encoder->i2c_bus)
2801                 goto err_inteloutput;
2802
2803         sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
2804
2805         /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2806         intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
2807
2808         /* Read the regs to test if we can talk to the device */
2809         for (i = 0; i < 0x40; i++) {
2810                 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
2811                         DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2812                                         sdvo_reg == SDVOB ? 'B' : 'C');
2813                         goto err_i2c;
2814                 }
2815         }
2816
2817         /* setup the DDC bus. */
2818         if (sdvo_reg == SDVOB) {
2819                 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2820                 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2821                                                 "SDVOB/VGA DDC BUS");
2822                 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2823         } else {
2824                 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2825                 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2826                                                 "SDVOC/VGA DDC BUS");
2827                 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2828         }
2829
2830         if (intel_encoder->ddc_bus == NULL)
2831                 goto err_i2c;
2832
2833         /* Wrap with our custom algo which switches to DDC mode */
2834         intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2835
2836         /* In default case sdvo lvds is false */
2837         intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
2838
2839         if (intel_sdvo_output_setup(intel_encoder,
2840                                     sdvo_priv->caps.output_flags) != true) {
2841                 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2842                           sdvo_reg == SDVOB ? 'B' : 'C');
2843                 goto err_i2c;
2844         }
2845
2846
2847         connector = &intel_encoder->base;
2848         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2849                            connector->connector_type);
2850
2851         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2852         connector->interlace_allowed = 0;
2853         connector->doublescan_allowed = 0;
2854         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2855
2856         drm_encoder_init(dev, &intel_encoder->enc,
2857                         &intel_sdvo_enc_funcs, intel_encoder->enc.encoder_type);
2858
2859         drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2860
2861         drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc);
2862         if (sdvo_priv->is_tv)
2863                 intel_sdvo_tv_create_property(connector);
2864
2865         if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
2866                 intel_sdvo_create_enhance_property(connector);
2867
2868         drm_sysfs_connector_add(connector);
2869
2870         intel_sdvo_select_ddc_bus(sdvo_priv);
2871
2872         /* Set the input timing to the screen. Assume always input 0. */
2873         intel_sdvo_set_target_input(intel_encoder, true, false);
2874
2875         intel_sdvo_get_input_pixel_clock_range(intel_encoder,
2876                                                &sdvo_priv->pixel_clock_min,
2877                                                &sdvo_priv->pixel_clock_max);
2878
2879
2880         DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2881                         "clock range %dMHz - %dMHz, "
2882                         "input 1: %c, input 2: %c, "
2883                         "output 1: %c, output 2: %c\n",
2884                         SDVO_NAME(sdvo_priv),
2885                         sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2886                         sdvo_priv->caps.device_rev_id,
2887                         sdvo_priv->pixel_clock_min / 1000,
2888                         sdvo_priv->pixel_clock_max / 1000,
2889                         (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2890                         (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2891                         /* check currently supported outputs */
2892                         sdvo_priv->caps.output_flags &
2893                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2894                         sdvo_priv->caps.output_flags &
2895                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2896
2897         return true;
2898
2899 err_i2c:
2900         if (sdvo_priv->analog_ddc_bus != NULL)
2901                 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2902         if (intel_encoder->ddc_bus != NULL)
2903                 intel_i2c_destroy(intel_encoder->ddc_bus);
2904         if (intel_encoder->i2c_bus != NULL)
2905                 intel_i2c_destroy(intel_encoder->i2c_bus);
2906 err_inteloutput:
2907         kfree(intel_encoder);
2908