drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35
  36 static u32 i915_gem_get_seqno(struct drm_device *dev)
  37 {
  38         drm_i915_private_t *dev_priv = dev->dev_private;
  39         u32 seqno;
  40
  41         seqno = dev_priv->next_seqno;
  42
  43         /* reserve 0 for non-seqno */
  44         if (++dev_priv->next_seqno == 0)
  45                 dev_priv->next_seqno = 1;
  46
  47         return seqno;
  48 }
  49
  50 static void
  51 render_ring_flush(struct drm_device *dev,
  52                 struct intel_ring_buffer *ring,
  53                 u32     invalidate_domains,
  54                 u32     flush_domains)
  55 {
  56         drm_i915_private_t *dev_priv = dev->dev_private;
  57         u32 cmd;
  58
  59 #if WATCH_EXEC
  60         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
  61                   invalidate_domains, flush_domains);
  62 #endif
  63
  64         trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
  65                                      invalidate_domains, flush_domains);
  66
  67         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
  68                 /*
  69                  * read/write caches:
  70                  *
  71                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  72                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  73                  * also flushed at 2d versus 3d pipeline switches.
  74                  *
  75                  * read-only caches:
  76                  *
  77                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  78                  * MI_READ_FLUSH is set, and is always flushed on 965.
  79                  *
  80                  * I915_GEM_DOMAIN_COMMAND may not exist?
  81                  *
  82                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  83                  * invalidated when MI_EXE_FLUSH is set.
  84                  *
  85                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  86                  * invalidated with every MI_FLUSH.
  87                  *
  88                  * TLBs:
  89                  *
  90                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  91                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  92                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  93                  * are flushed at any MI_FLUSH.
  94                  */
  95
  96                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  97                 if ((invalidate_domains|flush_domains) &
  98                     I915_GEM_DOMAIN_RENDER)
  99                         cmd &= ~MI_NO_WRITE_FLUSH;
 100                 if (INTEL_INFO(dev)->gen < 4) {
 101                         /*
 102                          * On the 965, the sampler cache always gets flushed
 103                          * and this bit is reserved.
 104                          */
 105                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                                 cmd |= MI_READ_FLUSH;
 107                 }
 108                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 109                         cmd |= MI_EXE_FLUSH;
 110
 111 #if WATCH_EXEC
 112                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 113 #endif
 114                 intel_ring_begin(dev, ring, 2);
 115                 intel_ring_emit(dev, ring, cmd);
 116                 intel_ring_emit(dev, ring, MI_NOOP);
 117                 intel_ring_advance(dev, ring);
 118         }
 119 }
 120
 121 static unsigned int render_ring_get_head(struct drm_device *dev,
 122                 struct intel_ring_buffer *ring)
 123 {
 124         drm_i915_private_t *dev_priv = dev->dev_private;
 125         return I915_READ(PRB0_HEAD) & HEAD_ADDR;
 126 }
 127
 128 static unsigned int render_ring_get_tail(struct drm_device *dev,
 129                 struct intel_ring_buffer *ring)
 130 {
 131         drm_i915_private_t *dev_priv = dev->dev_private;
 132         return I915_READ(PRB0_TAIL) & TAIL_ADDR;
 133 }
 134
 135 static inline void render_ring_set_tail(struct drm_device *dev, u32 value)
 136 {
 137         drm_i915_private_t *dev_priv = dev->dev_private;
 138         I915_WRITE(PRB0_TAIL, value);
 139 }
 140
 141 static unsigned int render_ring_get_active_head(struct drm_device *dev,
 142                 struct intel_ring_buffer *ring)
 143 {
 144         drm_i915_private_t *dev_priv = dev->dev_private;
 145         u32 acthd_reg = INTEL_INFO(dev)->gen ? ACTHD_I965 : ACTHD;
 146
 147         return I915_READ(acthd_reg);
 148 }
 149
 150 static int init_ring_common(struct drm_device *dev,
 151                 struct intel_ring_buffer *ring)
 152 {
 153         u32 head;
 154         drm_i915_private_t *dev_priv = dev->dev_private;
 155         struct drm_i915_gem_object *obj_priv;
 156         obj_priv = to_intel_bo(ring->gem_object);
 157
 158         /* Stop the ring if it's running. */
 159         I915_WRITE(ring->regs.ctl, 0);
 160         I915_WRITE(ring->regs.head, 0);
 161         ring->set_tail(dev, 0);
 162
 163         /* Initialize the ring. */
 164         I915_WRITE(ring->regs.start, obj_priv->gtt_offset);
 165         head = ring->get_head(dev, ring);
 166
 167         /* G45 ring initialization fails to reset head to zero */
 168         if (head != 0) {
 169                 DRM_ERROR("%s head not reset to zero "
 170                                 "ctl %08x head %08x tail %08x start %08x\n",
 171                                 ring->name,
 172                                 I915_READ(ring->regs.ctl),
 173                                 I915_READ(ring->regs.head),
 174                                 I915_READ(ring->regs.tail),
 175                                 I915_READ(ring->regs.start));
 176
 177                 I915_WRITE(ring->regs.head, 0);
 178
 179                 DRM_ERROR("%s head forced to zero "
 180                                 "ctl %08x head %08x tail %08x start %08x\n",
 181                                 ring->name,
 182                                 I915_READ(ring->regs.ctl),
 183                                 I915_READ(ring->regs.head),
 184                                 I915_READ(ring->regs.tail),
 185                                 I915_READ(ring->regs.start));
 186         }
 187
 188         I915_WRITE(ring->regs.ctl,
 189                         ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
 190                         | RING_NO_REPORT | RING_VALID);
 191
 192         head = I915_READ(ring->regs.head) & HEAD_ADDR;
 193         /* If the head is still not zero, the ring is dead */
 194         if (head != 0) {
 195                 DRM_ERROR("%s initialization failed "
 196                                 "ctl %08x head %08x tail %08x start %08x\n",
 197                                 ring->name,
 198                                 I915_READ(ring->regs.ctl),
 199                                 I915_READ(ring->regs.head),
 200                                 I915_READ(ring->regs.tail),
 201                                 I915_READ(ring->regs.start));
 202                 return -EIO;
 203         }
 204
 205         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 206                 i915_kernel_lost_context(dev);
 207         else {
 208                 ring->head = ring->get_head(dev, ring);
 209                 ring->tail = ring->get_tail(dev, ring);
 210                 ring->space = ring->head - (ring->tail + 8);
 211                 if (ring->space < 0)
 212                         ring->space += ring->size;
 213         }
 214         return 0;
 215 }
 216
 217 static int init_render_ring(struct drm_device *dev,
 218                 struct intel_ring_buffer *ring)
 219 {
 220         drm_i915_private_t *dev_priv = dev->dev_private;
 221         int ret = init_ring_common(dev, ring);
 222         int mode;
 223
 224         if (INTEL_INFO(dev)->gen > 3) {
 225                 mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 226                 if (IS_GEN6(dev))
 227                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 228                 I915_WRITE(MI_MODE, mode);
 229         }
 230         return ret;
 231 }
 232
 233 #define PIPE_CONTROL_FLUSH(addr)                                        \
 234 do {                                                                    \
 235         OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |          \
 236                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
 237         OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT);                       \
 238         OUT_RING(0);                                                    \
 239         OUT_RING(0);                                                    \
 240 } while (0)
 241
 242 /**
 243  * Creates a new sequence number, emitting a write of it to the status page
 244  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 245  *
 246  * Must be called with struct_lock held.
 247  *
 248  * Returned sequence numbers are nonzero on success.
 249  */
 250 static u32
 251 render_ring_add_request(struct drm_device *dev,
 252                 struct intel_ring_buffer *ring,
 253                 struct drm_file *file_priv,
 254                 u32 flush_domains)
 255 {
 256         drm_i915_private_t *dev_priv = dev->dev_private;
 257         u32 seqno;
 258
 259         seqno = i915_gem_get_seqno(dev);
 260
 261         if (IS_GEN6(dev)) {
 262                 BEGIN_LP_RING(6);
 263                 OUT_RING(GFX_OP_PIPE_CONTROL | 3);
 264                 OUT_RING(PIPE_CONTROL_QW_WRITE |
 265                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
 266                          PIPE_CONTROL_NOTIFY);
 267                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 268                 OUT_RING(seqno);
 269                 OUT_RING(0);
 270                 OUT_RING(0);
 271                 ADVANCE_LP_RING();
 272         } else if (HAS_PIPE_CONTROL(dev)) {
 273                 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
 274
 275                 /*
 276                  * Workaround qword write incoherence by flushing the
 277                  * PIPE_NOTIFY buffers out to memory before requesting
 278                  * an interrupt.
 279                  */
 280                 BEGIN_LP_RING(32);
 281                 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 282                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
 283                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 284                 OUT_RING(seqno);
 285                 OUT_RING(0);
 286                 PIPE_CONTROL_FLUSH(scratch_addr);
 287                 scratch_addr += 128; /* write to separate cachelines */
 288                 PIPE_CONTROL_FLUSH(scratch_addr);
 289                 scratch_addr += 128;
 290                 PIPE_CONTROL_FLUSH(scratch_addr);
 291                 scratch_addr += 128;
 292                 PIPE_CONTROL_FLUSH(scratch_addr);
 293                 scratch_addr += 128;
 294                 PIPE_CONTROL_FLUSH(scratch_addr);
 295                 scratch_addr += 128;
 296                 PIPE_CONTROL_FLUSH(scratch_addr);
 297                 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 298                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 299                          PIPE_CONTROL_NOTIFY);
 300                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 301                 OUT_RING(seqno);
 302                 OUT_RING(0);
 303                 ADVANCE_LP_RING();
 304         } else {
 305                 BEGIN_LP_RING(4);
 306                 OUT_RING(MI_STORE_DWORD_INDEX);
 307                 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 308                 OUT_RING(seqno);
 309
 310                 OUT_RING(MI_USER_INTERRUPT);
 311                 ADVANCE_LP_RING();
 312         }
 313         return seqno;
 314 }
 315
 316 static u32
 317 render_ring_get_gem_seqno(struct drm_device *dev,
 318                 struct intel_ring_buffer *ring)
 319 {
 320         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 321         if (HAS_PIPE_CONTROL(dev))
 322                 return ((volatile u32 *)(dev_priv->seqno_page))[0];
 323         else
 324                 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 325 }
 326
 327 static void
 328 render_ring_get_user_irq(struct drm_device *dev,
 329                 struct intel_ring_buffer *ring)
 330 {
 331         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 332         unsigned long irqflags;
 333
 334         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 335         if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
 336                 if (HAS_PCH_SPLIT(dev))
 337                         ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 338                 else
 339                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 340         }
 341         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 342 }
 343
 344 static void
 345 render_ring_put_user_irq(struct drm_device *dev,
 346                 struct intel_ring_buffer *ring)
 347 {
 348         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 349         unsigned long irqflags;
 350
 351         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 352         BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
 353         if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
 354                 if (HAS_PCH_SPLIT(dev))
 355                         ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 356                 else
 357                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 358         }
 359         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 360 }
 361
 362 static void render_setup_status_page(struct drm_device *dev,
 363         struct  intel_ring_buffer *ring)
 364 {
 365         drm_i915_private_t *dev_priv = dev->dev_private;
 366         if (IS_GEN6(dev)) {
 367                 I915_WRITE(HWS_PGA_GEN6, ring->status_page.gfx_addr);
 368                 I915_READ(HWS_PGA_GEN6); /* posting read */
 369         } else {
 370                 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 371                 I915_READ(HWS_PGA); /* posting read */
 372         }
 373
 374 }
 375
 376 void
 377 bsd_ring_flush(struct drm_device *dev,
 378                 struct intel_ring_buffer *ring,
 379                 u32     invalidate_domains,
 380                 u32     flush_domains)
 381 {
 382         intel_ring_begin(dev, ring, 2);
 383         intel_ring_emit(dev, ring, MI_FLUSH);
 384         intel_ring_emit(dev, ring, MI_NOOP);
 385         intel_ring_advance(dev, ring);
 386 }
 387
 388 static inline unsigned int bsd_ring_get_head(struct drm_device *dev,
 389                 struct intel_ring_buffer *ring)
 390 {
 391         drm_i915_private_t *dev_priv = dev->dev_private;
 392         return I915_READ(BSD_RING_HEAD) & HEAD_ADDR;
 393 }
 394
 395 static inline unsigned int bsd_ring_get_tail(struct drm_device *dev,
 396                 struct intel_ring_buffer *ring)
 397 {
 398         drm_i915_private_t *dev_priv = dev->dev_private;
 399         return I915_READ(BSD_RING_TAIL) & TAIL_ADDR;
 400 }
 401
 402 static inline void bsd_ring_set_tail(struct drm_device *dev, u32 value)
 403 {
 404         drm_i915_private_t *dev_priv = dev->dev_private;
 405         I915_WRITE(BSD_RING_TAIL, value);
 406 }
 407
 408 static inline unsigned int bsd_ring_get_active_head(struct drm_device *dev,
 409                 struct intel_ring_buffer *ring)
 410 {
 411         drm_i915_private_t *dev_priv = dev->dev_private;
 412         return I915_READ(BSD_RING_ACTHD);
 413 }
 414
 415 static int init_bsd_ring(struct drm_device *dev,
 416                 struct intel_ring_buffer *ring)
 417 {
 418         return init_ring_common(dev, ring);
 419 }
 420
 421 static u32
 422 bsd_ring_add_request(struct drm_device *dev,
 423                 struct intel_ring_buffer *ring,
 424                 struct drm_file *file_priv,
 425                 u32 flush_domains)
 426 {
 427         u32 seqno;
 428
 429         seqno = i915_gem_get_seqno(dev);
 430
 431         intel_ring_begin(dev, ring, 4);
 432         intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
 433         intel_ring_emit(dev, ring,
 434                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 435         intel_ring_emit(dev, ring, seqno);
 436         intel_ring_emit(dev, ring, MI_USER_INTERRUPT);
 437         intel_ring_advance(dev, ring);
 438
 439         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
 440
 441         return seqno;
 442 }
 443
 444 static void bsd_setup_status_page(struct drm_device *dev,
 445                 struct  intel_ring_buffer *ring)
 446 {
 447         drm_i915_private_t *dev_priv = dev->dev_private;
 448         I915_WRITE(BSD_HWS_PGA, ring->status_page.gfx_addr);
 449         I915_READ(BSD_HWS_PGA);
 450 }
 451
 452 static void
 453 bsd_ring_get_user_irq(struct drm_device *dev,
 454                 struct intel_ring_buffer *ring)
 455 {
 456         /* do nothing */
 457 }
 458 static void
 459 bsd_ring_put_user_irq(struct drm_device *dev,
 460                 struct intel_ring_buffer *ring)
 461 {
 462         /* do nothing */
 463 }
 464
 465 static u32
 466 bsd_ring_get_gem_seqno(struct drm_device *dev,
 467                 struct intel_ring_buffer *ring)
 468 {
 469         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 470 }
 471
 472 static int
 473 bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
 474                 struct intel_ring_buffer *ring,
 475                 struct drm_i915_gem_execbuffer2 *exec,
 476                 struct drm_clip_rect *cliprects,
 477                 uint64_t exec_offset)
 478 {
 479         uint32_t exec_start;
 480         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
 481         intel_ring_begin(dev, ring, 2);
 482         intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
 483                         (2 << 6) | MI_BATCH_NON_SECURE_I965);
 484         intel_ring_emit(dev, ring, exec_start);
 485         intel_ring_advance(dev, ring);
 486         return 0;
 487 }
 488
 489
 490 static int
 491 render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
 492                 struct intel_ring_buffer *ring,
 493                 struct drm_i915_gem_execbuffer2 *exec,
 494                 struct drm_clip_rect *cliprects,
 495                 uint64_t exec_offset)
 496 {
 497         drm_i915_private_t *dev_priv = dev->dev_private;
 498         int nbox = exec->num_cliprects;
 499         int i = 0, count;
 500         uint32_t exec_start, exec_len;
 501         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
 502         exec_len = (uint32_t) exec->batch_len;
 503
 504         trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
 505
 506         count = nbox ? nbox : 1;
 507
 508         for (i = 0; i < count; i++) {
 509                 if (i < nbox) {
 510                         int ret = i915_emit_box(dev, cliprects, i,
 511                                                 exec->DR1, exec->DR4);
 512                         if (ret)
 513                                 return ret;
 514                 }
 515
 516                 if (IS_I830(dev) || IS_845G(dev)) {
 517                         intel_ring_begin(dev, ring, 4);
 518                         intel_ring_emit(dev, ring, MI_BATCH_BUFFER);
 519                         intel_ring_emit(dev, ring,
 520                                         exec_start | MI_BATCH_NON_SECURE);
 521                         intel_ring_emit(dev, ring, exec_start + exec_len - 4);
 522                         intel_ring_emit(dev, ring, 0);
 523                 } else {
 524                         intel_ring_begin(dev, ring, 4);
 525                         if (INTEL_INFO(dev)->gen >= 4) {
 526                                 intel_ring_emit(dev, ring,
 527                                                 MI_BATCH_BUFFER_START | (2 << 6)
 528                                                 | MI_BATCH_NON_SECURE_I965);
 529                                 intel_ring_emit(dev, ring, exec_start);
 530                         } else {
 531                                 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START
 532                                                 | (2 << 6));
 533                                 intel_ring_emit(dev, ring, exec_start |
 534                                                 MI_BATCH_NON_SECURE);
 535                         }
 536                 }
 537                 intel_ring_advance(dev, ring);
 538         }
 539
 540         if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
 541                 intel_ring_begin(dev, ring, 2);
 542                 intel_ring_emit(dev, ring, MI_FLUSH |
 543                                 MI_NO_WRITE_FLUSH |
 544                                 MI_INVALIDATE_ISP );
 545                 intel_ring_emit(dev, ring, MI_NOOP);
 546                 intel_ring_advance(dev, ring);
 547         }
 548         /* XXX breadcrumb */
 549
 550         return 0;
 551 }
 552
 553 static void cleanup_status_page(struct drm_device *dev,
 554                 struct intel_ring_buffer *ring)
 555 {
 556         drm_i915_private_t *dev_priv = dev->dev_private;
 557         struct drm_gem_object *obj;
 558         struct drm_i915_gem_object *obj_priv;
 559
 560         obj = ring->status_page.obj;
 561         if (obj == NULL)
 562                 return;
 563         obj_priv = to_intel_bo(obj);
 564
 565         kunmap(obj_priv->pages[0]);
 566         i915_gem_object_unpin(obj);
 567         drm_gem_object_unreference(obj);
 568         ring->status_page.obj = NULL;
 569
 570         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 571 }
 572
 573 static int init_status_page(struct drm_device *dev,
 574                 struct intel_ring_buffer *ring)
 575 {
 576         drm_i915_private_t *dev_priv = dev->dev_private;
 577         struct drm_gem_object *obj;
 578         struct drm_i915_gem_object *obj_priv;
 579         int ret;
 580
 581         obj = i915_gem_alloc_object(dev, 4096);
 582         if (obj == NULL) {
 583                 DRM_ERROR("Failed to allocate status page\n");
 584                 ret = -ENOMEM;
 585                 goto err;
 586         }
 587         obj_priv = to_intel_bo(obj);
 588         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
 589
 590         ret = i915_gem_object_pin(obj, 4096);
 591         if (ret != 0) {
 592                 goto err_unref;
 593         }
 594
 595         ring->status_page.gfx_addr = obj_priv->gtt_offset;
 596         ring->status_page.page_addr = kmap(obj_priv->pages[0]);
 597         if (ring->status_page.page_addr == NULL) {
 598                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 599                 goto err_unpin;
 600         }
 601         ring->status_page.obj = obj;
 602         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 603
 604         ring->setup_status_page(dev, ring);
 605         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 606                         ring->name, ring->status_page.gfx_addr);
 607
 608         return 0;
 609
 610 err_unpin:
 611         i915_gem_object_unpin(obj);
 612 err_unref:
 613         drm_gem_object_unreference(obj);
 614 err:
 615         return ret;
 616 }
 617
 618
 619 int intel_init_ring_buffer(struct drm_device *dev,
 620                 struct intel_ring_buffer *ring)
 621 {
 622         struct drm_i915_gem_object *obj_priv;
 623         struct drm_gem_object *obj;
 624         int ret;
 625
 626         ring->dev = dev;
 627
 628         if (I915_NEED_GFX_HWS(dev)) {
 629                 ret = init_status_page(dev, ring);
 630                 if (ret)
 631                         return ret;
 632         }
 633
 634         obj = i915_gem_alloc_object(dev, ring->size);
 635         if (obj == NULL) {
 636                 DRM_ERROR("Failed to allocate ringbuffer\n");
 637                 ret = -ENOMEM;
 638                 goto err_hws;
 639         }
 640
 641         ring->gem_object = obj;
 642
 643         ret = i915_gem_object_pin(obj, ring->alignment);
 644         if (ret)
 645                 goto err_unref;
 646
 647         obj_priv = to_intel_bo(obj);
 648         ring->map.size = ring->size;
 649         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
 650         ring->map.type = 0;
 651         ring->map.flags = 0;
 652         ring->map.mtrr = 0;
 653
 654         drm_core_ioremap_wc(&ring->map, dev);
 655         if (ring->map.handle == NULL) {
 656                 DRM_ERROR("Failed to map ringbuffer.\n");
 657                 ret = -EINVAL;
 658                 goto err_unpin;
 659         }
 660
 661         ring->virtual_start = ring->map.handle;
 662         ret = ring->init(dev, ring);
 663         if (ret)
 664                 goto err_unmap;
 665
 666         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 667                 i915_kernel_lost_context(dev);
 668         else {
 669                 ring->head = ring->get_head(dev, ring);
 670                 ring->tail = ring->get_tail(dev, ring);
 671                 ring->space = ring->head - (ring->tail + 8);
 672                 if (ring->space < 0)
 673                         ring->space += ring->size;
 674         }
 675         INIT_LIST_HEAD(&ring->active_list);
 676         INIT_LIST_HEAD(&ring->request_list);
 677         return ret;
 678
 679 err_unmap:
 680         drm_core_ioremapfree(&ring->map, dev);
 681 err_unpin:
 682         i915_gem_object_unpin(obj);
 683 err_unref:
 684         drm_gem_object_unreference(obj);
 685         ring->gem_object = NULL;
 686 err_hws:
 687         cleanup_status_page(dev, ring);
 688         return ret;
 689 }
 690
 691 void intel_cleanup_ring_buffer(struct drm_device *dev,
 692                 struct intel_ring_buffer *ring)
 693 {
 694         if (ring->gem_object == NULL)
 695                 return;
 696
 697         drm_core_ioremapfree(&ring->map, dev);
 698
 699         i915_gem_object_unpin(ring->gem_object);
 700         drm_gem_object_unreference(ring->gem_object);
 701         ring->gem_object = NULL;
 702         cleanup_status_page(dev, ring);
 703 }
 704
 705 int intel_wrap_ring_buffer(struct drm_device *dev,
 706                 struct intel_ring_buffer *ring)
 707 {
 708         unsigned int *virt;
 709         int rem;
 710         rem = ring->size - ring->tail;
 711
 712         if (ring->space < rem) {
 713                 int ret = intel_wait_ring_buffer(dev, ring, rem);
 714                 if (ret)
 715                         return ret;
 716         }
 717
 718         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 719         rem /= 8;
 720         while (rem--) {
 721                 *virt++ = MI_NOOP;
 722                 *virt++ = MI_NOOP;
 723         }
 724
 725         ring->tail = 0;
 726         ring->space = ring->head - 8;
 727
 728         return 0;
 729 }
 730
 731 int intel_wait_ring_buffer(struct drm_device *dev,
 732                 struct intel_ring_buffer *ring, int n)
 733 {
 734         unsigned long end;
 735
 736         trace_i915_ring_wait_begin (dev);
 737         end = jiffies + 3 * HZ;
 738         do {
 739                 ring->head = ring->get_head(dev, ring);
 740                 ring->space = ring->head - (ring->tail + 8);
 741                 if (ring->space < 0)
 742                         ring->space += ring->size;
 743                 if (ring->space >= n) {
 744                         trace_i915_ring_wait_end (dev);
 745                         return 0;
 746                 }
 747
 748                 if (dev->primary->master) {
 749                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 750                         if (master_priv->sarea_priv)
 751                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 752                 }
 753
 754                 yield();
 755         } while (!time_after(jiffies, end));
 756         trace_i915_ring_wait_end (dev);
 757         return -EBUSY;
 758 }
 759
 760 void intel_ring_begin(struct drm_device *dev,
 761                 struct intel_ring_buffer *ring, int num_dwords)
 762 {
 763         int n = 4*num_dwords;
 764         if (unlikely(ring->tail + n > ring->size))
 765                 intel_wrap_ring_buffer(dev, ring);
 766         if (unlikely(ring->space < n))
 767                 intel_wait_ring_buffer(dev, ring, n);
 768
 769         ring->space -= n;
 770 }
 771
 772 void intel_ring_advance(struct drm_device *dev,
 773                 struct intel_ring_buffer *ring)
 774 {
 775         ring->tail &= ring->size - 1;
 776         ring->set_tail(dev, ring->tail);
 777 }
 778
 779 void intel_fill_struct(struct drm_device *dev,
 780                 struct intel_ring_buffer *ring,
 781                 void *data,
 782                 unsigned int len)
 783 {
 784         unsigned int *virt = ring->virtual_start + ring->tail;
 785         BUG_ON((len&~(4-1)) != 0);
 786         intel_ring_begin(dev, ring, len/4);
 787         memcpy(virt, data, len);
 788         ring->tail += len;
 789         ring->tail &= ring->size - 1;
 790         ring->space -= len;
 791         intel_ring_advance(dev, ring);
 792 }
 793
 794 static struct intel_ring_buffer render_ring = {
 795         .name                   = "render ring",
 796         .id                     = RING_RENDER,
 797         .regs                   = {
 798                 .ctl = PRB0_CTL,
 799                 .head = PRB0_HEAD,
 800                 .tail = PRB0_TAIL,
 801                 .start = PRB0_START
 802         },
 803         .size                   = 32 * PAGE_SIZE,
 804         .alignment              = PAGE_SIZE,
 805         .virtual_start          = NULL,
 806         .dev                    = NULL,
 807         .gem_object             = NULL,
 808         .head                   = 0,
 809         .tail                   = 0,
 810         .space                  = 0,
 811         .user_irq_refcount      = 0,
 812         .irq_gem_seqno          = 0,
 813         .waiting_gem_seqno      = 0,
 814         .setup_status_page      = render_setup_status_page,
 815         .init                   = init_render_ring,
 816         .get_head               = render_ring_get_head,
 817         .get_tail               = render_ring_get_tail,
 818         .set_tail               = render_ring_set_tail,
 819         .get_active_head        = render_ring_get_active_head,
 820         .flush                  = render_ring_flush,
 821         .add_request            = render_ring_add_request,
 822         .get_gem_seqno          = render_ring_get_gem_seqno,
 823         .user_irq_get           = render_ring_get_user_irq,
 824         .user_irq_put           = render_ring_put_user_irq,
 825         .dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer,
 826         .status_page            = {NULL, 0, NULL},
 827         .map                    = {0,}
 828 };
 829
 830 /* ring buffer for bit-stream decoder */
 831
 832 static struct intel_ring_buffer bsd_ring = {
 833         .name                   = "bsd ring",
 834         .id                     = RING_BSD,
 835         .regs                   = {
 836                 .ctl = BSD_RING_CTL,
 837                 .head = BSD_RING_HEAD,
 838                 .tail = BSD_RING_TAIL,
 839                 .start = BSD_RING_START
 840         },
 841         .size                   = 32 * PAGE_SIZE,
 842         .alignment              = PAGE_SIZE,
 843         .virtual_start          = NULL,
 844         .dev                    = NULL,
 845         .gem_object             = NULL,
 846         .head                   = 0,
 847         .tail                   = 0,
 848         .space                  = 0,
 849         .user_irq_refcount      = 0,
 850         .irq_gem_seqno          = 0,
 851         .waiting_gem_seqno      = 0,
 852         .setup_status_page      = bsd_setup_status_page,
 853         .init                   = init_bsd_ring,
 854         .get_head               = bsd_ring_get_head,
 855         .get_tail               = bsd_ring_get_tail,
 856         .set_tail               = bsd_ring_set_tail,
 857         .get_active_head        = bsd_ring_get_active_head,
 858         .flush                  = bsd_ring_flush,
 859         .add_request            = bsd_ring_add_request,
 860         .get_gem_seqno          = bsd_ring_get_gem_seqno,
 861         .user_irq_get           = bsd_ring_get_user_irq,
 862         .user_irq_put           = bsd_ring_put_user_irq,
 863         .dispatch_gem_execbuffer = bsd_ring_dispatch_gem_execbuffer,
 864         .status_page            = {NULL, 0, NULL},
 865         .map                    = {0,}
 866 };
 867
 868 int intel_init_render_ring_buffer(struct drm_device *dev)
 869 {
 870         drm_i915_private_t *dev_priv = dev->dev_private;
 871
 872         dev_priv->render_ring = render_ring;
 873
 874         if (!I915_NEED_GFX_HWS(dev)) {
 875                 dev_priv->render_ring.status_page.page_addr
 876                         = dev_priv->status_page_dmah->vaddr;
 877                 memset(dev_priv->render_ring.status_page.page_addr,
 878                                 0, PAGE_SIZE);
 879         }
 880
 881         return intel_init_ring_buffer(dev, &dev_priv->render_ring);
 882 }
 883
 884 int intel_init_bsd_ring_buffer(struct drm_device *dev)
 885 {
 886         drm_i915_private_t *dev_priv = dev->dev_private;
 887
 888         dev_priv->bsd_ring = bsd_ring;
 889
 890         return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
 891 }