drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 static inline int ring_space(struct intel_ring_buffer *ring)
  38 {
  39         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  40         if (space < 0)
  41                 space += ring->size;
  42         return space;
  43 }
  44
  45 static u32 i915_gem_get_seqno(struct drm_device *dev)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         u32 seqno;
  49
  50         seqno = dev_priv->next_seqno;
  51
  52         /* reserve 0 for non-seqno */
  53         if (++dev_priv->next_seqno == 0)
  54                 dev_priv->next_seqno = 1;
  55
  56         return seqno;
  57 }
  58
  59 static int
  60 render_ring_flush(struct intel_ring_buffer *ring,
  61                   u32   invalidate_domains,
  62                   u32   flush_domains)
  63 {
  64         struct drm_device *dev = ring->dev;
  65         u32 cmd;
  66         int ret;
  67
  68         /*
  69          * read/write caches:
  70          *
  71          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  72          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  73          * also flushed at 2d versus 3d pipeline switches.
  74          *
  75          * read-only caches:
  76          *
  77          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  78          * MI_READ_FLUSH is set, and is always flushed on 965.
  79          *
  80          * I915_GEM_DOMAIN_COMMAND may not exist?
  81          *
  82          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  83          * invalidated when MI_EXE_FLUSH is set.
  84          *
  85          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  86          * invalidated with every MI_FLUSH.
  87          *
  88          * TLBs:
  89          *
  90          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  91          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  92          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  93          * are flushed at any MI_FLUSH.
  94          */
  95
  96         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  97         if ((invalidate_domains|flush_domains) &
  98             I915_GEM_DOMAIN_RENDER)
  99                 cmd &= ~MI_NO_WRITE_FLUSH;
 100         if (INTEL_INFO(dev)->gen < 4) {
 101                 /*
 102                  * On the 965, the sampler cache always gets flushed
 103                  * and this bit is reserved.
 104                  */
 105                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                         cmd |= MI_READ_FLUSH;
 107         }
 108         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 109                 cmd |= MI_EXE_FLUSH;
 110
 111         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 112             (IS_G4X(dev) || IS_GEN5(dev)))
 113                 cmd |= MI_INVALIDATE_ISP;
 114
 115         ret = intel_ring_begin(ring, 2);
 116         if (ret)
 117                 return ret;
 118
 119         intel_ring_emit(ring, cmd);
 120         intel_ring_emit(ring, MI_NOOP);
 121         intel_ring_advance(ring);
 122
 123         return 0;
 124 }
 125
 126 static void ring_write_tail(struct intel_ring_buffer *ring,
 127                             u32 value)
 128 {
 129         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 130         I915_WRITE_TAIL(ring, value);
 131 }
 132
 133 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 134 {
 135         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 136         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 137                         RING_ACTHD(ring->mmio_base) : ACTHD;
 138
 139         return I915_READ(acthd_reg);
 140 }
 141
 142 static int init_ring_common(struct intel_ring_buffer *ring)
 143 {
 144         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 145         struct drm_i915_gem_object *obj = ring->obj;
 146         u32 head;
 147
 148         /* Stop the ring if it's running. */
 149         I915_WRITE_CTL(ring, 0);
 150         I915_WRITE_HEAD(ring, 0);
 151         ring->write_tail(ring, 0);
 152
 153         /* Initialize the ring. */
 154         I915_WRITE_START(ring, obj->gtt_offset);
 155         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 156
 157         /* G45 ring initialization fails to reset head to zero */
 158         if (head != 0) {
 159                 DRM_DEBUG_KMS("%s head not reset to zero "
 160                               "ctl %08x head %08x tail %08x start %08x\n",
 161                               ring->name,
 162                               I915_READ_CTL(ring),
 163                               I915_READ_HEAD(ring),
 164                               I915_READ_TAIL(ring),
 165                               I915_READ_START(ring));
 166
 167                 I915_WRITE_HEAD(ring, 0);
 168
 169                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 170                         DRM_ERROR("failed to set %s head to zero "
 171                                   "ctl %08x head %08x tail %08x start %08x\n",
 172                                   ring->name,
 173                                   I915_READ_CTL(ring),
 174                                   I915_READ_HEAD(ring),
 175                                   I915_READ_TAIL(ring),
 176                                   I915_READ_START(ring));
 177                 }
 178         }
 179
 180         I915_WRITE_CTL(ring,
 181                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 182                         | RING_REPORT_64K | RING_VALID);
 183
 184         /* If the head is still not zero, the ring is dead */
 185         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 186             I915_READ_START(ring) != obj->gtt_offset ||
 187             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 188                 DRM_ERROR("%s initialization failed "
 189                                 "ctl %08x head %08x tail %08x start %08x\n",
 190                                 ring->name,
 191                                 I915_READ_CTL(ring),
 192                                 I915_READ_HEAD(ring),
 193                                 I915_READ_TAIL(ring),
 194                                 I915_READ_START(ring));
 195                 return -EIO;
 196         }
 197
 198         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 199                 i915_kernel_lost_context(ring->dev);
 200         else {
 201                 ring->head = I915_READ_HEAD(ring);
 202                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 203                 ring->space = ring_space(ring);
 204         }
 205
 206         return 0;
 207 }
 208
 209 /*
 210  * 965+ support PIPE_CONTROL commands, which provide finer grained control
 211  * over cache flushing.
 212  */
 213 struct pipe_control {
 214         struct drm_i915_gem_object *obj;
 215         volatile u32 *cpu_page;
 216         u32 gtt_offset;
 217 };
 218
 219 static int
 220 init_pipe_control(struct intel_ring_buffer *ring)
 221 {
 222         struct pipe_control *pc;
 223         struct drm_i915_gem_object *obj;
 224         int ret;
 225
 226         if (ring->private)
 227                 return 0;
 228
 229         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 230         if (!pc)
 231                 return -ENOMEM;
 232
 233         obj = i915_gem_alloc_object(ring->dev, 4096);
 234         if (obj == NULL) {
 235                 DRM_ERROR("Failed to allocate seqno page\n");
 236                 ret = -ENOMEM;
 237                 goto err;
 238         }
 239         obj->cache_level = I915_CACHE_LLC;
 240
 241         ret = i915_gem_object_pin(obj, 4096, true);
 242         if (ret)
 243                 goto err_unref;
 244
 245         pc->gtt_offset = obj->gtt_offset;
 246         pc->cpu_page =  kmap(obj->pages[0]);
 247         if (pc->cpu_page == NULL)
 248                 goto err_unpin;
 249
 250         pc->obj = obj;
 251         ring->private = pc;
 252         return 0;
 253
 254 err_unpin:
 255         i915_gem_object_unpin(obj);
 256 err_unref:
 257         drm_gem_object_unreference(&obj->base);
 258 err:
 259         kfree(pc);
 260         return ret;
 261 }
 262
 263 static void
 264 cleanup_pipe_control(struct intel_ring_buffer *ring)
 265 {
 266         struct pipe_control *pc = ring->private;
 267         struct drm_i915_gem_object *obj;
 268
 269         if (!ring->private)
 270                 return;
 271
 272         obj = pc->obj;
 273         kunmap(obj->pages[0]);
 274         i915_gem_object_unpin(obj);
 275         drm_gem_object_unreference(&obj->base);
 276
 277         kfree(pc);
 278         ring->private = NULL;
 279 }
 280
 281 static int init_render_ring(struct intel_ring_buffer *ring)
 282 {
 283         struct drm_device *dev = ring->dev;
 284         struct drm_i915_private *dev_priv = dev->dev_private;
 285         int ret = init_ring_common(ring);
 286
 287         if (INTEL_INFO(dev)->gen > 3) {
 288                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 289                 if (IS_GEN6(dev) || IS_GEN7(dev))
 290                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 291                 I915_WRITE(MI_MODE, mode);
 292         }
 293
 294         if (INTEL_INFO(dev)->gen >= 6) {
 295         } else if (IS_GEN5(dev)) {
 296                 ret = init_pipe_control(ring);
 297                 if (ret)
 298                         return ret;
 299         }
 300
 301         return ret;
 302 }
 303
 304 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 305 {
 306         if (!ring->private)
 307                 return;
 308
 309         cleanup_pipe_control(ring);
 310 }
 311
 312 static void
 313 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
 314 {
 315         struct drm_device *dev = ring->dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317         int id;
 318
 319         /*
 320          * cs -> 1 = vcs, 0 = bcs
 321          * vcs -> 1 = bcs, 0 = cs,
 322          * bcs -> 1 = cs, 0 = vcs.
 323          */
 324         id = ring - dev_priv->ring;
 325         id += 2 - i;
 326         id %= 3;
 327
 328         intel_ring_emit(ring,
 329                         MI_SEMAPHORE_MBOX |
 330                         MI_SEMAPHORE_REGISTER |
 331                         MI_SEMAPHORE_UPDATE);
 332         intel_ring_emit(ring, seqno);
 333         intel_ring_emit(ring,
 334                         RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
 335 }
 336
 337 static int
 338 gen6_add_request(struct intel_ring_buffer *ring,
 339                  u32 *result)
 340 {
 341         u32 seqno;
 342         int ret;
 343
 344         ret = intel_ring_begin(ring, 10);
 345         if (ret)
 346                 return ret;
 347
 348         seqno = i915_gem_get_seqno(ring->dev);
 349         update_semaphore(ring, 0, seqno);
 350         update_semaphore(ring, 1, seqno);
 351
 352         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 353         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 354         intel_ring_emit(ring, seqno);
 355         intel_ring_emit(ring, MI_USER_INTERRUPT);
 356         intel_ring_advance(ring);
 357
 358         *result = seqno;
 359         return 0;
 360 }
 361
 362 int
 363 intel_ring_sync(struct intel_ring_buffer *ring,
 364                 struct intel_ring_buffer *to,
 365                 u32 seqno)
 366 {
 367         int ret;
 368
 369         ret = intel_ring_begin(ring, 4);
 370         if (ret)
 371                 return ret;
 372
 373         intel_ring_emit(ring,
 374                         MI_SEMAPHORE_MBOX |
 375                         MI_SEMAPHORE_REGISTER |
 376                         intel_ring_sync_index(ring, to) << 17 |
 377                         MI_SEMAPHORE_COMPARE);
 378         intel_ring_emit(ring, seqno);
 379         intel_ring_emit(ring, 0);
 380         intel_ring_emit(ring, MI_NOOP);
 381         intel_ring_advance(ring);
 382
 383         return 0;
 384 }
 385
 386 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 387 do {                                                                    \
 388         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |           \
 389                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
 390         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 391         intel_ring_emit(ring__, 0);                                                     \
 392         intel_ring_emit(ring__, 0);                                                     \
 393 } while (0)
 394
 395 static int
 396 pc_render_add_request(struct intel_ring_buffer *ring,
 397                       u32 *result)
 398 {
 399         struct drm_device *dev = ring->dev;
 400         u32 seqno = i915_gem_get_seqno(dev);
 401         struct pipe_control *pc = ring->private;
 402         u32 scratch_addr = pc->gtt_offset + 128;
 403         int ret;
 404
 405         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 406          * incoherent with writes to memory, i.e. completely fubar,
 407          * so we need to use PIPE_NOTIFY instead.
 408          *
 409          * However, we also need to workaround the qword write
 410          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 411          * memory before requesting an interrupt.
 412          */
 413         ret = intel_ring_begin(ring, 32);
 414         if (ret)
 415                 return ret;
 416
 417         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 418                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
 419         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 420         intel_ring_emit(ring, seqno);
 421         intel_ring_emit(ring, 0);
 422         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 423         scratch_addr += 128; /* write to separate cachelines */
 424         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 425         scratch_addr += 128;
 426         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 427         scratch_addr += 128;
 428         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 429         scratch_addr += 128;
 430         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 431         scratch_addr += 128;
 432         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 433         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 434                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 435                         PIPE_CONTROL_NOTIFY);
 436         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 437         intel_ring_emit(ring, seqno);
 438         intel_ring_emit(ring, 0);
 439         intel_ring_advance(ring);
 440
 441         *result = seqno;
 442         return 0;
 443 }
 444
 445 static int
 446 render_ring_add_request(struct intel_ring_buffer *ring,
 447                         u32 *result)
 448 {
 449         struct drm_device *dev = ring->dev;
 450         u32 seqno = i915_gem_get_seqno(dev);
 451         int ret;
 452
 453         ret = intel_ring_begin(ring, 4);
 454         if (ret)
 455                 return ret;
 456
 457         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 458         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 459         intel_ring_emit(ring, seqno);
 460         intel_ring_emit(ring, MI_USER_INTERRUPT);
 461         intel_ring_advance(ring);
 462
 463         *result = seqno;
 464         return 0;
 465 }
 466
 467 static u32
 468 ring_get_seqno(struct intel_ring_buffer *ring)
 469 {
 470         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 471 }
 472
 473 static u32
 474 pc_render_get_seqno(struct intel_ring_buffer *ring)
 475 {
 476         struct pipe_control *pc = ring->private;
 477         return pc->cpu_page[0];
 478 }
 479
 480 static void
 481 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 482 {
 483         dev_priv->gt_irq_mask &= ~mask;
 484         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 485         POSTING_READ(GTIMR);
 486 }
 487
 488 static void
 489 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 490 {
 491         dev_priv->gt_irq_mask |= mask;
 492         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 493         POSTING_READ(GTIMR);
 494 }
 495
 496 static void
 497 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 498 {
 499         dev_priv->irq_mask &= ~mask;
 500         I915_WRITE(IMR, dev_priv->irq_mask);
 501         POSTING_READ(IMR);
 502 }
 503
 504 static void
 505 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 506 {
 507         dev_priv->irq_mask |= mask;
 508         I915_WRITE(IMR, dev_priv->irq_mask);
 509         POSTING_READ(IMR);
 510 }
 511
 512 static bool
 513 render_ring_get_irq(struct intel_ring_buffer *ring)
 514 {
 515         struct drm_device *dev = ring->dev;
 516         drm_i915_private_t *dev_priv = dev->dev_private;
 517
 518         if (!dev->irq_enabled)
 519                 return false;
 520
 521         spin_lock(&ring->irq_lock);
 522         if (ring->irq_refcount++ == 0) {
 523                 if (HAS_PCH_SPLIT(dev))
 524                         ironlake_enable_irq(dev_priv,
 525                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 526                 else
 527                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 528         }
 529         spin_unlock(&ring->irq_lock);
 530
 531         return true;
 532 }
 533
 534 static void
 535 render_ring_put_irq(struct intel_ring_buffer *ring)
 536 {
 537         struct drm_device *dev = ring->dev;
 538         drm_i915_private_t *dev_priv = dev->dev_private;
 539
 540         spin_lock(&ring->irq_lock);
 541         if (--ring->irq_refcount == 0) {
 542                 if (HAS_PCH_SPLIT(dev))
 543                         ironlake_disable_irq(dev_priv,
 544                                              GT_USER_INTERRUPT |
 545                                              GT_PIPE_NOTIFY);
 546                 else
 547                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 548         }
 549         spin_unlock(&ring->irq_lock);
 550 }
 551
 552 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 553 {
 554         struct drm_device *dev = ring->dev;
 555         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 556         u32 mmio = 0;
 557
 558         /* The ring status page addresses are no longer next to the rest of
 559          * the ring registers as of gen7.
 560          */
 561         if (IS_GEN7(dev)) {
 562                 switch (ring->id) {
 563                 case RING_RENDER:
 564                         mmio = RENDER_HWS_PGA_GEN7;
 565                         break;
 566                 case RING_BLT:
 567                         mmio = BLT_HWS_PGA_GEN7;
 568                         break;
 569                 case RING_BSD:
 570                         mmio = BSD_HWS_PGA_GEN7;
 571                         break;
 572                 }
 573         } else if (IS_GEN6(ring->dev)) {
 574                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 575         } else {
 576                 mmio = RING_HWS_PGA(ring->mmio_base);
 577         }
 578
 579         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 580         POSTING_READ(mmio);
 581 }
 582
 583 static int
 584 bsd_ring_flush(struct intel_ring_buffer *ring,
 585                u32     invalidate_domains,
 586                u32     flush_domains)
 587 {
 588         int ret;
 589
 590         ret = intel_ring_begin(ring, 2);
 591         if (ret)
 592                 return ret;
 593
 594         intel_ring_emit(ring, MI_FLUSH);
 595         intel_ring_emit(ring, MI_NOOP);
 596         intel_ring_advance(ring);
 597         return 0;
 598 }
 599
 600 static int
 601 ring_add_request(struct intel_ring_buffer *ring,
 602                  u32 *result)
 603 {
 604         u32 seqno;
 605         int ret;
 606
 607         ret = intel_ring_begin(ring, 4);
 608         if (ret)
 609                 return ret;
 610
 611         seqno = i915_gem_get_seqno(ring->dev);
 612
 613         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 614         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 615         intel_ring_emit(ring, seqno);
 616         intel_ring_emit(ring, MI_USER_INTERRUPT);
 617         intel_ring_advance(ring);
 618
 619         *result = seqno;
 620         return 0;
 621 }
 622
 623 static bool
 624 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
 625 {
 626         struct drm_device *dev = ring->dev;
 627         drm_i915_private_t *dev_priv = dev->dev_private;
 628
 629         if (!dev->irq_enabled)
 630                return false;
 631
 632         spin_lock(&ring->irq_lock);
 633         if (ring->irq_refcount++ == 0)
 634                 ironlake_enable_irq(dev_priv, flag);
 635         spin_unlock(&ring->irq_lock);
 636
 637         return true;
 638 }
 639
 640 static void
 641 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
 642 {
 643         struct drm_device *dev = ring->dev;
 644         drm_i915_private_t *dev_priv = dev->dev_private;
 645
 646         spin_lock(&ring->irq_lock);
 647         if (--ring->irq_refcount == 0)
 648                 ironlake_disable_irq(dev_priv, flag);
 649         spin_unlock(&ring->irq_lock);
 650 }
 651
 652 static bool
 653 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 654 {
 655         struct drm_device *dev = ring->dev;
 656         drm_i915_private_t *dev_priv = dev->dev_private;
 657
 658         if (!dev->irq_enabled)
 659                return false;
 660
 661         spin_lock(&ring->irq_lock);
 662         if (ring->irq_refcount++ == 0) {
 663                 ring->irq_mask &= ~rflag;
 664                 I915_WRITE_IMR(ring, ring->irq_mask);
 665                 ironlake_enable_irq(dev_priv, gflag);
 666         }
 667         spin_unlock(&ring->irq_lock);
 668
 669         return true;
 670 }
 671
 672 static void
 673 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 674 {
 675         struct drm_device *dev = ring->dev;
 676         drm_i915_private_t *dev_priv = dev->dev_private;
 677
 678         spin_lock(&ring->irq_lock);
 679         if (--ring->irq_refcount == 0) {
 680                 ring->irq_mask |= rflag;
 681                 I915_WRITE_IMR(ring, ring->irq_mask);
 682                 ironlake_disable_irq(dev_priv, gflag);
 683         }
 684         spin_unlock(&ring->irq_lock);
 685 }
 686
 687 static bool
 688 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 689 {
 690         return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
 691 }
 692 static void
 693 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 694 {
 695         ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
 696 }
 697
 698 static int
 699 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 700 {
 701         int ret;
 702
 703         ret = intel_ring_begin(ring, 2);
 704         if (ret)
 705                 return ret;
 706
 707         intel_ring_emit(ring,
 708                         MI_BATCH_BUFFER_START | (2 << 6) |
 709                         MI_BATCH_NON_SECURE_I965);
 710         intel_ring_emit(ring, offset);
 711         intel_ring_advance(ring);
 712
 713         return 0;
 714 }
 715
 716 static int
 717 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 718                                 u32 offset, u32 len)
 719 {
 720         struct drm_device *dev = ring->dev;
 721         int ret;
 722
 723         if (IS_I830(dev) || IS_845G(dev)) {
 724                 ret = intel_ring_begin(ring, 4);
 725                 if (ret)
 726                         return ret;
 727
 728                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 729                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 730                 intel_ring_emit(ring, offset + len - 8);
 731                 intel_ring_emit(ring, 0);
 732         } else {
 733                 ret = intel_ring_begin(ring, 2);
 734                 if (ret)
 735                         return ret;
 736
 737                 if (INTEL_INFO(dev)->gen >= 4) {
 738                         intel_ring_emit(ring,
 739                                         MI_BATCH_BUFFER_START | (2 << 6) |
 740                                         MI_BATCH_NON_SECURE_I965);
 741                         intel_ring_emit(ring, offset);
 742                 } else {
 743                         intel_ring_emit(ring,
 744                                         MI_BATCH_BUFFER_START | (2 << 6));
 745                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 746                 }
 747         }
 748         intel_ring_advance(ring);
 749
 750         return 0;
 751 }
 752
 753 static void cleanup_status_page(struct intel_ring_buffer *ring)
 754 {
 755         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 756         struct drm_i915_gem_object *obj;
 757
 758         obj = ring->status_page.obj;
 759         if (obj == NULL)
 760                 return;
 761
 762         kunmap(obj->pages[0]);
 763         i915_gem_object_unpin(obj);
 764         drm_gem_object_unreference(&obj->base);
 765         ring->status_page.obj = NULL;
 766
 767         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 768 }
 769
 770 static int init_status_page(struct intel_ring_buffer *ring)
 771 {
 772         struct drm_device *dev = ring->dev;
 773         drm_i915_private_t *dev_priv = dev->dev_private;
 774         struct drm_i915_gem_object *obj;
 775         int ret;
 776
 777         obj = i915_gem_alloc_object(dev, 4096);
 778         if (obj == NULL) {
 779                 DRM_ERROR("Failed to allocate status page\n");
 780                 ret = -ENOMEM;
 781                 goto err;
 782         }
 783         obj->cache_level = I915_CACHE_LLC;
 784
 785         ret = i915_gem_object_pin(obj, 4096, true);
 786         if (ret != 0) {
 787                 goto err_unref;
 788         }
 789
 790         ring->status_page.gfx_addr = obj->gtt_offset;
 791         ring->status_page.page_addr = kmap(obj->pages[0]);
 792         if (ring->status_page.page_addr == NULL) {
 793                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 794                 goto err_unpin;
 795         }
 796         ring->status_page.obj = obj;
 797         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 798
 799         intel_ring_setup_status_page(ring);
 800         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 801                         ring->name, ring->status_page.gfx_addr);
 802
 803         return 0;
 804
 805 err_unpin:
 806         i915_gem_object_unpin(obj);
 807 err_unref:
 808         drm_gem_object_unreference(&obj->base);
 809 err:
 810         return ret;
 811 }
 812
 813 int intel_init_ring_buffer(struct drm_device *dev,
 814                            struct intel_ring_buffer *ring)
 815 {
 816         struct drm_i915_gem_object *obj;
 817         int ret;
 818
 819         ring->dev = dev;
 820         INIT_LIST_HEAD(&ring->active_list);
 821         INIT_LIST_HEAD(&ring->request_list);
 822         INIT_LIST_HEAD(&ring->gpu_write_list);
 823
 824         init_waitqueue_head(&ring->irq_queue);
 825         spin_lock_init(&ring->irq_lock);
 826         ring->irq_mask = ~0;
 827
 828         if (I915_NEED_GFX_HWS(dev)) {
 829                 ret = init_status_page(ring);
 830                 if (ret)
 831                         return ret;
 832         }
 833
 834         obj = i915_gem_alloc_object(dev, ring->size);
 835         if (obj == NULL) {
 836                 DRM_ERROR("Failed to allocate ringbuffer\n");
 837                 ret = -ENOMEM;
 838                 goto err_hws;
 839         }
 840
 841         ring->obj = obj;
 842
 843         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
 844         if (ret)
 845                 goto err_unref;
 846
 847         ring->map.size = ring->size;
 848         ring->map.offset = dev->agp->base + obj->gtt_offset;
 849         ring->map.type = 0;
 850         ring->map.flags = 0;
 851         ring->map.mtrr = 0;
 852
 853         drm_core_ioremap_wc(&ring->map, dev);
 854         if (ring->map.handle == NULL) {
 855                 DRM_ERROR("Failed to map ringbuffer.\n");
 856                 ret = -EINVAL;
 857                 goto err_unpin;
 858         }
 859
 860         ring->virtual_start = ring->map.handle;
 861         ret = ring->init(ring);
 862         if (ret)
 863                 goto err_unmap;
 864
 865         /* Workaround an erratum on the i830 which causes a hang if
 866          * the TAIL pointer points to within the last 2 cachelines
 867          * of the buffer.
 868          */
 869         ring->effective_size = ring->size;
 870         if (IS_I830(ring->dev))
 871                 ring->effective_size -= 128;
 872
 873         return 0;
 874
 875 err_unmap:
 876         drm_core_ioremapfree(&ring->map, dev);
 877 err_unpin:
 878         i915_gem_object_unpin(obj);
 879 err_unref:
 880         drm_gem_object_unreference(&obj->base);
 881         ring->obj = NULL;
 882 err_hws:
 883         cleanup_status_page(ring);
 884         return ret;
 885 }
 886
 887 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
 888 {
 889         struct drm_i915_private *dev_priv;
 890         int ret;
 891
 892         if (ring->obj == NULL)
 893                 return;
 894
 895         /* Disable the ring buffer. The ring must be idle at this point */
 896         dev_priv = ring->dev->dev_private;
 897         ret = intel_wait_ring_idle(ring);
 898         if (ret)
 899                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 900                           ring->name, ret);
 901
 902         I915_WRITE_CTL(ring, 0);
 903
 904         drm_core_ioremapfree(&ring->map, ring->dev);
 905
 906         i915_gem_object_unpin(ring->obj);
 907         drm_gem_object_unreference(&ring->obj->base);
 908         ring->obj = NULL;
 909
 910         if (ring->cleanup)
 911                 ring->cleanup(ring);
 912
 913         cleanup_status_page(ring);
 914 }
 915
 916 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
 917 {
 918         unsigned int *virt;
 919         int rem = ring->size - ring->tail;
 920
 921         if (ring->space < rem) {
 922                 int ret = intel_wait_ring_buffer(ring, rem);
 923                 if (ret)
 924                         return ret;
 925         }
 926
 927         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 928         rem /= 8;
 929         while (rem--) {
 930                 *virt++ = MI_NOOP;
 931                 *virt++ = MI_NOOP;
 932         }
 933
 934         ring->tail = 0;
 935         ring->space = ring_space(ring);
 936
 937         return 0;
 938 }
 939
 940 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
 941 {
 942         struct drm_device *dev = ring->dev;
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944         unsigned long end;
 945         u32 head;
 946
 947         /* If the reported head position has wrapped or hasn't advanced,
 948          * fallback to the slow and accurate path.
 949          */
 950         head = intel_read_status_page(ring, 4);
 951         if (head > ring->head) {
 952                 ring->head = head;
 953                 ring->space = ring_space(ring);
 954                 if (ring->space >= n)
 955                         return 0;
 956         }
 957
 958         trace_i915_ring_wait_begin(ring);
 959         end = jiffies + 3 * HZ;
 960         do {
 961                 ring->head = I915_READ_HEAD(ring);
 962                 ring->space = ring_space(ring);
 963                 if (ring->space >= n) {
 964                         trace_i915_ring_wait_end(ring);
 965                         return 0;
 966                 }
 967
 968                 if (dev->primary->master) {
 969                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 970                         if (master_priv->sarea_priv)
 971                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 972                 }
 973
 974                 msleep(1);
 975                 if (atomic_read(&dev_priv->mm.wedged))
 976                         return -EAGAIN;
 977         } while (!time_after(jiffies, end));
 978         trace_i915_ring_wait_end(ring);
 979         return -EBUSY;
 980 }
 981
 982 int intel_ring_begin(struct intel_ring_buffer *ring,
 983                      int num_dwords)
 984 {
 985         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 986         int n = 4*num_dwords;
 987         int ret;
 988
 989         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
 990                 return -EIO;
 991
 992         if (unlikely(ring->tail + n > ring->effective_size)) {
 993                 ret = intel_wrap_ring_buffer(ring);
 994                 if (unlikely(ret))
 995                         return ret;
 996         }
 997
 998         if (unlikely(ring->space < n)) {
 999                 ret = intel_wait_ring_buffer(ring, n);
1000                 if (unlikely(ret))
1001                         return ret;
1002         }
1003
1004         ring->space -= n;
1005         return 0;
1006 }
1007
1008 void intel_ring_advance(struct intel_ring_buffer *ring)
1009 {
1010         ring->tail &= ring->size - 1;
1011         ring->write_tail(ring, ring->tail);
1012 }
1013
1014 static const struct intel_ring_buffer render_ring = {
1015         .name                   = "render ring",
1016         .id                     = RING_RENDER,
1017         .mmio_base              = RENDER_RING_BASE,
1018         .size                   = 32 * PAGE_SIZE,
1019         .init                   = init_render_ring,
1020         .write_tail             = ring_write_tail,
1021         .flush                  = render_ring_flush,
1022         .add_request            = render_ring_add_request,
1023         .get_seqno              = ring_get_seqno,
1024         .irq_get                = render_ring_get_irq,
1025         .irq_put                = render_ring_put_irq,
1026         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1027        .cleanup                 = render_ring_cleanup,
1028 };
1029
1030 /* ring buffer for bit-stream decoder */
1031
1032 static const struct intel_ring_buffer bsd_ring = {
1033         .name                   = "bsd ring",
1034         .id                     = RING_BSD,
1035         .mmio_base              = BSD_RING_BASE,
1036         .size                   = 32 * PAGE_SIZE,
1037         .init                   = init_ring_common,
1038         .write_tail             = ring_write_tail,
1039         .flush                  = bsd_ring_flush,
1040         .add_request            = ring_add_request,
1041         .get_seqno              = ring_get_seqno,
1042         .irq_get                = bsd_ring_get_irq,
1043         .irq_put                = bsd_ring_put_irq,
1044         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1045 };
1046
1047
1048 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1049                                      u32 value)
1050 {
1051        drm_i915_private_t *dev_priv = ring->dev->dev_private;
1052
1053        /* Every tail move must follow the sequence below */
1054        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1055                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1056                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1057        I915_WRITE(GEN6_BSD_RNCID, 0x0);
1058
1059        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1060                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1061                        50))
1062                DRM_ERROR("timed out waiting for IDLE Indicator\n");
1063
1064        I915_WRITE_TAIL(ring, value);
1065        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1066                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1067                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1068 }
1069
1070 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1071                            u32 invalidate, u32 flush)
1072 {
1073         uint32_t cmd;
1074         int ret;
1075
1076         ret = intel_ring_begin(ring, 4);
1077         if (ret)
1078                 return ret;
1079
1080         cmd = MI_FLUSH_DW;
1081         if (invalidate & I915_GEM_GPU_DOMAINS)
1082                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1083         intel_ring_emit(ring, cmd);
1084         intel_ring_emit(ring, 0);
1085         intel_ring_emit(ring, 0);
1086         intel_ring_emit(ring, MI_NOOP);
1087         intel_ring_advance(ring);
1088         return 0;
1089 }
1090
1091 static int
1092 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1093                               u32 offset, u32 len)
1094 {
1095        int ret;
1096
1097        ret = intel_ring_begin(ring, 2);
1098        if (ret)
1099                return ret;
1100
1101        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1102        /* bit0-7 is the length on GEN6+ */
1103        intel_ring_emit(ring, offset);
1104        intel_ring_advance(ring);
1105
1106        return 0;
1107 }
1108
1109 static bool
1110 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1111 {
1112         return gen6_ring_get_irq(ring,
1113                                  GT_USER_INTERRUPT,
1114                                  GEN6_RENDER_USER_INTERRUPT);
1115 }
1116
1117 static void
1118 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1119 {
1120         return gen6_ring_put_irq(ring,
1121                                  GT_USER_INTERRUPT,
1122                                  GEN6_RENDER_USER_INTERRUPT);
1123 }
1124
1125 static bool
1126 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1127 {
1128         return gen6_ring_get_irq(ring,
1129                                  GT_GEN6_BSD_USER_INTERRUPT,
1130                                  GEN6_BSD_USER_INTERRUPT);
1131 }
1132
1133 static void
1134 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1135 {
1136         return gen6_ring_put_irq(ring,
1137                                  GT_GEN6_BSD_USER_INTERRUPT,
1138                                  GEN6_BSD_USER_INTERRUPT);
1139 }
1140
1141 /* ring buffer for Video Codec for Gen6+ */
1142 static const struct intel_ring_buffer gen6_bsd_ring = {
1143         .name                   = "gen6 bsd ring",
1144         .id                     = RING_BSD,
1145         .mmio_base              = GEN6_BSD_RING_BASE,
1146         .size                   = 32 * PAGE_SIZE,
1147         .init                   = init_ring_common,
1148         .write_tail             = gen6_bsd_ring_write_tail,
1149         .flush                  = gen6_ring_flush,
1150         .add_request            = gen6_add_request,
1151         .get_seqno              = ring_get_seqno,
1152         .irq_get                = gen6_bsd_ring_get_irq,
1153         .irq_put                = gen6_bsd_ring_put_irq,
1154         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1155 };
1156
1157 /* Blitter support (SandyBridge+) */
1158
1159 static bool
1160 blt_ring_get_irq(struct intel_ring_buffer *ring)
1161 {
1162         return gen6_ring_get_irq(ring,
1163                                  GT_BLT_USER_INTERRUPT,
1164                                  GEN6_BLITTER_USER_INTERRUPT);
1165 }
1166
1167 static void
1168 blt_ring_put_irq(struct intel_ring_buffer *ring)
1169 {
1170         gen6_ring_put_irq(ring,
1171                           GT_BLT_USER_INTERRUPT,
1172                           GEN6_BLITTER_USER_INTERRUPT);
1173 }
1174
1175
1176 /* Workaround for some stepping of SNB,
1177  * each time when BLT engine ring tail moved,
1178  * the first command in the ring to be parsed
1179  * should be MI_BATCH_BUFFER_START
1180  */
1181 #define NEED_BLT_WORKAROUND(dev) \
1182         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1183
1184 static inline struct drm_i915_gem_object *
1185 to_blt_workaround(struct intel_ring_buffer *ring)
1186 {
1187         return ring->private;
1188 }
1189
1190 static int blt_ring_init(struct intel_ring_buffer *ring)
1191 {
1192         if (NEED_BLT_WORKAROUND(ring->dev)) {
1193                 struct drm_i915_gem_object *obj;
1194                 u32 *ptr;
1195                 int ret;
1196
1197                 obj = i915_gem_alloc_object(ring->dev, 4096);
1198                 if (obj == NULL)
1199                         return -ENOMEM;
1200
1201                 ret = i915_gem_object_pin(obj, 4096, true);
1202                 if (ret) {
1203                         drm_gem_object_unreference(&obj->base);
1204                         return ret;
1205                 }
1206
1207                 ptr = kmap(obj->pages[0]);
1208                 *ptr++ = MI_BATCH_BUFFER_END;
1209                 *ptr++ = MI_NOOP;
1210                 kunmap(obj->pages[0]);
1211
1212                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1213                 if (ret) {
1214                         i915_gem_object_unpin(obj);
1215                         drm_gem_object_unreference(&obj->base);
1216                         return ret;
1217                 }
1218
1219                 ring->private = obj;
1220         }
1221
1222         return init_ring_common(ring);
1223 }
1224
1225 static int blt_ring_begin(struct intel_ring_buffer *ring,
1226                           int num_dwords)
1227 {
1228         if (ring->private) {
1229                 int ret = intel_ring_begin(ring, num_dwords+2);
1230                 if (ret)
1231                         return ret;
1232
1233                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1234                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1235
1236                 return 0;
1237         } else
1238                 return intel_ring_begin(ring, 4);
1239 }
1240
1241 static int blt_ring_flush(struct intel_ring_buffer *ring,
1242                           u32 invalidate, u32 flush)
1243 {
1244         uint32_t cmd;
1245         int ret;
1246
1247         ret = blt_ring_begin(ring, 4);
1248         if (ret)
1249                 return ret;
1250
1251         cmd = MI_FLUSH_DW;
1252         if (invalidate & I915_GEM_DOMAIN_RENDER)
1253                 cmd |= MI_INVALIDATE_TLB;
1254         intel_ring_emit(ring, cmd);
1255         intel_ring_emit(ring, 0);
1256         intel_ring_emit(ring, 0);
1257         intel_ring_emit(ring, MI_NOOP);
1258         intel_ring_advance(ring);
1259         return 0;
1260 }
1261
1262 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1263 {
1264         if (!ring->private)
1265                 return;
1266
1267         i915_gem_object_unpin(ring->private);
1268         drm_gem_object_unreference(ring->private);
1269         ring->private = NULL;
1270 }
1271
1272 static const struct intel_ring_buffer gen6_blt_ring = {
1273        .name                    = "blt ring",
1274        .id                      = RING_BLT,
1275        .mmio_base               = BLT_RING_BASE,
1276        .size                    = 32 * PAGE_SIZE,
1277        .init                    = blt_ring_init,
1278        .write_tail              = ring_write_tail,
1279        .flush                   = blt_ring_flush,
1280        .add_request             = gen6_add_request,
1281        .get_seqno               = ring_get_seqno,
1282        .irq_get                 = blt_ring_get_irq,
1283        .irq_put                 = blt_ring_put_irq,
1284        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
1285        .cleanup                 = blt_ring_cleanup,
1286 };
1287
1288 int intel_init_render_ring_buffer(struct drm_device *dev)
1289 {
1290         drm_i915_private_t *dev_priv = dev->dev_private;
1291         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1292
1293         *ring = render_ring;
1294         if (INTEL_INFO(dev)->gen >= 6) {
1295                 ring->add_request = gen6_add_request;
1296                 ring->irq_get = gen6_render_ring_get_irq;
1297                 ring->irq_put = gen6_render_ring_put_irq;
1298         } else if (IS_GEN5(dev)) {
1299                 ring->add_request = pc_render_add_request;
1300                 ring->get_seqno = pc_render_get_seqno;
1301         }
1302
1303         if (!I915_NEED_GFX_HWS(dev)) {
1304                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1305                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1306         }
1307
1308         return intel_init_ring_buffer(dev, ring);
1309 }
1310
1311 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1312 {
1313         drm_i915_private_t *dev_priv = dev->dev_private;
1314         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1315
1316         *ring = render_ring;
1317         if (INTEL_INFO(dev)->gen >= 6) {
1318                 ring->add_request = gen6_add_request;
1319                 ring->irq_get = gen6_render_ring_get_irq;
1320                 ring->irq_put = gen6_render_ring_put_irq;
1321         } else if (IS_GEN5(dev)) {
1322                 ring->add_request = pc_render_add_request;
1323                 ring->get_seqno = pc_render_get_seqno;
1324         }
1325
1326         ring->dev = dev;
1327         INIT_LIST_HEAD(&ring->active_list);
1328         INIT_LIST_HEAD(&ring->request_list);
1329         INIT_LIST_HEAD(&ring->gpu_write_list);
1330
1331         ring->size = size;
1332         ring->effective_size = ring->size;
1333         if (IS_I830(ring->dev))
1334                 ring->effective_size -= 128;
1335
1336         ring->map.offset = start;
1337         ring->map.size = size;
1338         ring->map.type = 0;
1339         ring->map.flags = 0;
1340         ring->map.mtrr = 0;
1341
1342         drm_core_ioremap_wc(&ring->map, dev);
1343         if (ring->map.handle == NULL) {
1344                 DRM_ERROR("can not ioremap virtual address for"
1345                           " ring buffer\n");
1346                 return -ENOMEM;
1347         }
1348
1349         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1350         return 0;
1351 }
1352
1353 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1354 {
1355         drm_i915_private_t *dev_priv = dev->dev_private;
1356         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1357
1358         if (IS_GEN6(dev) || IS_GEN7(dev))
1359                 *ring = gen6_bsd_ring;
1360         else
1361                 *ring = bsd_ring;
1362
1363         return intel_init_ring_buffer(dev, ring);
1364 }
1365
1366 int intel_init_blt_ring_buffer(struct drm_device *dev)
1367 {
1368         drm_i915_private_t *dev_priv = dev->dev_private;
1369         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1370
1371         *ring = gen6_blt_ring;
1372
1373         return intel_init_ring_buffer(dev, ring);
1374 }