drivers/gpu/drm/i915/intel_panel.c

   1 /*
   2  * Copyright © 2006-2010 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  *      Chris Wilson <chris@chris-wilson.co.uk>
  29  */
  30
  31 #include "intel_drv.h"
  32
  33 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  34
  35 void
  36 intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
  37                        struct drm_display_mode *adjusted_mode)
  38 {
  39         adjusted_mode->hdisplay = fixed_mode->hdisplay;
  40         adjusted_mode->hsync_start = fixed_mode->hsync_start;
  41         adjusted_mode->hsync_end = fixed_mode->hsync_end;
  42         adjusted_mode->htotal = fixed_mode->htotal;
  43
  44         adjusted_mode->vdisplay = fixed_mode->vdisplay;
  45         adjusted_mode->vsync_start = fixed_mode->vsync_start;
  46         adjusted_mode->vsync_end = fixed_mode->vsync_end;
  47         adjusted_mode->vtotal = fixed_mode->vtotal;
  48
  49         adjusted_mode->clock = fixed_mode->clock;
  50
  51         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  52 }
  53
  54 /* adjusted_mode has been preset to be the panel's fixed mode */
  55 void
  56 intel_pch_panel_fitting(struct drm_device *dev,
  57                         int fitting_mode,
  58                         struct drm_display_mode *mode,
  59                         struct drm_display_mode *adjusted_mode)
  60 {
  61         struct drm_i915_private *dev_priv = dev->dev_private;
  62         int x, y, width, height;
  63
  64         x = y = width = height = 0;
  65
  66         /* Native modes don't need fitting */
  67         if (adjusted_mode->hdisplay == mode->hdisplay &&
  68             adjusted_mode->vdisplay == mode->vdisplay)
  69                 goto done;
  70
  71         switch (fitting_mode) {
  72         case DRM_MODE_SCALE_CENTER:
  73                 width = mode->hdisplay;
  74                 height = mode->vdisplay;
  75                 x = (adjusted_mode->hdisplay - width + 1)/2;
  76                 y = (adjusted_mode->vdisplay - height + 1)/2;
  77                 break;
  78
  79         case DRM_MODE_SCALE_ASPECT:
  80                 /* Scale but preserve the aspect ratio */
  81                 {
  82                         u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
  83                         u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
  84                         if (scaled_width > scaled_height) { /* pillar */
  85                                 width = scaled_height / mode->vdisplay;
  86                                 x = (adjusted_mode->hdisplay - width + 1) / 2;
  87                                 y = 0;
  88                                 height = adjusted_mode->vdisplay;
  89                         } else if (scaled_width < scaled_height) { /* letter */
  90                                 height = scaled_width / mode->hdisplay;
  91                                 y = (adjusted_mode->vdisplay - height + 1) / 2;
  92                                 x = 0;
  93                                 width = adjusted_mode->hdisplay;
  94                         } else {
  95                                 x = y = 0;
  96                                 width = adjusted_mode->hdisplay;
  97                                 height = adjusted_mode->vdisplay;
  98                         }
  99                 }
 100                 break;
 101
 102         default:
 103         case DRM_MODE_SCALE_FULLSCREEN:
 104                 x = y = 0;
 105                 width = adjusted_mode->hdisplay;
 106                 height = adjusted_mode->vdisplay;
 107                 break;
 108         }
 109
 110 done:
 111         dev_priv->pch_pf_pos = (x << 16) | y;
 112         dev_priv->pch_pf_size = (width << 16) | height;
 113 }
 114
 115 static int is_backlight_combination_mode(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118
 119         if (INTEL_INFO(dev)->gen >= 4)
 120                 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
 121
 122         if (IS_GEN2(dev))
 123                 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
 124
 125         return 0;
 126 }
 127
 128 u32 intel_panel_get_max_backlight(struct drm_device *dev)
 129 {
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         u32 max;
 132
 133         if (HAS_PCH_SPLIT(dev)) {
 134                 max = I915_READ(BLC_PWM_PCH_CTL2) >> 16;
 135         } else {
 136                 max = I915_READ(BLC_PWM_CTL);
 137                 if (IS_PINEVIEW(dev)) {
 138                         max >>= 17;
 139                 } else {
 140                         max >>= 16;
 141                         if (INTEL_INFO(dev)->gen < 4)
 142                                 max &= ~1;
 143                 }
 144
 145                 if (is_backlight_combination_mode(dev))
 146                         max *= 0xff;
 147         }
 148
 149         if (max == 0) {
 150                 /* XXX add code here to query mode clock or hardware clock
 151                  * and program max PWM appropriately.
 152                  */
 153                 DRM_ERROR("fixme: max PWM is zero.\n");
 154                 max = 1;
 155         }
 156
 157         DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
 158         return max;
 159 }
 160
 161 u32 intel_panel_get_backlight(struct drm_device *dev)
 162 {
 163         struct drm_i915_private *dev_priv = dev->dev_private;
 164         u32 val;
 165
 166         if (HAS_PCH_SPLIT(dev)) {
 167                 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 168         } else {
 169                 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 170                 if (IS_PINEVIEW(dev))
 171                         val >>= 1;
 172
 173                 if (is_backlight_combination_mode(dev)){
 174                         u8 lbpc;
 175
 176                         val &= ~1;
 177                         pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
 178                         val *= lbpc;
 179                         val >>= 1;
 180                 }
 181         }
 182
 183         DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
 184         return val;
 185 }
 186
 187 static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
 188 {
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190         u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 191         I915_WRITE(BLC_PWM_CPU_CTL, val | level);
 192 }
 193
 194 void intel_panel_set_backlight(struct drm_device *dev, u32 level)
 195 {
 196         struct drm_i915_private *dev_priv = dev->dev_private;
 197         u32 tmp;
 198
 199         DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
 200
 201         if (HAS_PCH_SPLIT(dev))
 202                 return intel_pch_panel_set_backlight(dev, level);
 203
 204         if (is_backlight_combination_mode(dev)){
 205                 u32 max = intel_panel_get_max_backlight(dev);
 206                 u8 lpbc;
 207
 208                 lpbc = level * 0xfe / max + 1;
 209                 level /= lpbc;
 210                 pci_write_config_byte(dev->pdev, PCI_LBPC, lpbc);
 211         }
 212
 213         tmp = I915_READ(BLC_PWM_CTL);
 214         if (IS_PINEVIEW(dev)) {
 215                 tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
 216                 level <<= 1;
 217         } else
 218                 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
 219         I915_WRITE(BLC_PWM_CTL, tmp | level);
 220 }