drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "i915_reg.h"
  35 #include "intel_drv.h"
  36
  37 /* Limits for overlay size. According to intel doc, the real limits are:
  38  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  39  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  40  * the mininum of both.  */
  41 #define IMAGE_MAX_WIDTH         2048
  42 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  43 /* on 830 and 845 these large limits result in the card hanging */
  44 #define IMAGE_MAX_WIDTH_LEGACY  1024
  45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  46
  47 /* overlay register definitions */
  48 /* OCMD register */
  49 #define OCMD_TILED_SURFACE      (0x1<<19)
  50 #define OCMD_MIRROR_MASK        (0x3<<17)
  51 #define OCMD_MIRROR_MODE        (0x3<<17)
  52 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  53 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  54 #define OCMD_MIRROR_BOTH        (0x3<<17)
  55 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  56 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  57 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  58 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  60 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  61 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  62 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_422_PACKED     (0x8<<10)
  64 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  65 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  66 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  67 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  68 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  69 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  70 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  71 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  72 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  73 #define OCMD_TEST_MODE          (0x1<<4)
  74 #define OCMD_BUFFER_SELECT      (0x3<<2)
  75 #define OCMD_BUFFER0            (0x0<<2)
  76 #define OCMD_BUFFER1            (0x1<<2)
  77 #define OCMD_FIELD_SELECT       (0x1<<2)
  78 #define OCMD_FIELD0             (0x0<<1)
  79 #define OCMD_FIELD1             (0x1<<1)
  80 #define OCMD_ENABLE             (0x1<<0)
  81
  82 /* OCONFIG register */
  83 #define OCONF_PIPE_MASK         (0x1<<18)
  84 #define OCONF_PIPE_A            (0x0<<18)
  85 #define OCONF_PIPE_B            (0x1<<18)
  86 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  87 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  88 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  89 #define OCONF_CSC_BYPASS        (0x1<<4)
  90 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  91 #define OCONF_TEST_MODE         (0x1<<2)
  92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  93 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  94
  95 /* DCLRKM (dst-key) register */
  96 #define DST_KEY_ENABLE          (0x1<<31)
  97 #define CLK_RGB24_MASK          0x0
  98 #define CLK_RGB16_MASK          0x070307
  99 #define CLK_RGB15_MASK          0x070707
 100 #define CLK_RGB8I_MASK          0xffffff
 101
 102 #define RGB16_TO_COLORKEY(c) \
 103         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 104 #define RGB15_TO_COLORKEY(c) \
 105         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 106
 107 /* overlay flip addr flag */
 108 #define OFC_UPDATE              0x1
 109
 110 /* polyphase filter coefficients */
 111 #define N_HORIZ_Y_TAPS          5
 112 #define N_VERT_Y_TAPS           3
 113 #define N_HORIZ_UV_TAPS         3
 114 #define N_VERT_UV_TAPS          3
 115 #define N_PHASES                17
 116 #define MAX_TAPS                5
 117
 118 /* memory bufferd overlay registers */
 119 struct overlay_registers {
 120     u32 OBUF_0Y;
 121     u32 OBUF_1Y;
 122     u32 OBUF_0U;
 123     u32 OBUF_0V;
 124     u32 OBUF_1U;
 125     u32 OBUF_1V;
 126     u32 OSTRIDE;
 127     u32 YRGB_VPH;
 128     u32 UV_VPH;
 129     u32 HORZ_PH;
 130     u32 INIT_PHS;
 131     u32 DWINPOS;
 132     u32 DWINSZ;
 133     u32 SWIDTH;
 134     u32 SWIDTHSW;
 135     u32 SHEIGHT;
 136     u32 YRGBSCALE;
 137     u32 UVSCALE;
 138     u32 OCLRC0;
 139     u32 OCLRC1;
 140     u32 DCLRKV;
 141     u32 DCLRKM;
 142     u32 SCLRKVH;
 143     u32 SCLRKVL;
 144     u32 SCLRKEN;
 145     u32 OCONFIG;
 146     u32 OCMD;
 147     u32 RESERVED1; /* 0x6C */
 148     u32 OSTART_0Y;
 149     u32 OSTART_1Y;
 150     u32 OSTART_0U;
 151     u32 OSTART_0V;
 152     u32 OSTART_1U;
 153     u32 OSTART_1V;
 154     u32 OTILEOFF_0Y;
 155     u32 OTILEOFF_1Y;
 156     u32 OTILEOFF_0U;
 157     u32 OTILEOFF_0V;
 158     u32 OTILEOFF_1U;
 159     u32 OTILEOFF_1V;
 160     u32 FASTHSCALE; /* 0xA0 */
 161     u32 UVSCALEV; /* 0xA4 */
 162     u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 163     u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 164     u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 165     u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 166     u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 167     u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 168     u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 169     u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 170     u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 171 };
 172
 173 struct intel_overlay {
 174         struct drm_device *dev;
 175         struct intel_crtc *crtc;
 176         struct drm_i915_gem_object *vid_bo;
 177         struct drm_i915_gem_object *old_vid_bo;
 178         int active;
 179         int pfit_active;
 180         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 181         u32 color_key;
 182         u32 brightness, contrast, saturation;
 183         u32 old_xscale, old_yscale;
 184         /* register access */
 185         u32 flip_addr;
 186         struct drm_i915_gem_object *reg_bo;
 187         /* flip handling */
 188         uint32_t last_flip_req;
 189         void (*flip_tail)(struct intel_overlay *);
 190 };
 191
 192 static struct overlay_registers *
 193 intel_overlay_map_regs(struct intel_overlay *overlay)
 194 {
 195         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
 196         struct overlay_registers *regs;
 197
 198         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 199                 regs = overlay->reg_bo->phys_obj->handle->vaddr;
 200         else
 201                 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
 202                                          overlay->reg_bo->gtt_offset);
 203
 204         return regs;
 205 }
 206
 207 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 208                                      struct overlay_registers *regs)
 209 {
 210         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 211                 io_mapping_unmap(regs);
 212 }
 213
 214 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 215                                          struct drm_i915_gem_request *request,
 216                                          bool interruptible,
 217                                          void (*tail)(struct intel_overlay *))
 218 {
 219         struct drm_device *dev = overlay->dev;
 220         drm_i915_private_t *dev_priv = dev->dev_private;
 221         int ret;
 222
 223         BUG_ON(overlay->last_flip_req);
 224         overlay->last_flip_req =
 225                 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
 226         if (overlay->last_flip_req == 0)
 227                 return -ENOMEM;
 228
 229         overlay->flip_tail = tail;
 230         ret = i915_do_wait_request(dev,
 231                                    overlay->last_flip_req, true,
 232                                    &dev_priv->render_ring);
 233         if (ret)
 234                 return ret;
 235
 236         overlay->last_flip_req = 0;
 237         return 0;
 238 }
 239
 240 /* Workaround for i830 bug where pipe a must be enable to change control regs */
 241 static int
 242 i830_activate_pipe_a(struct drm_device *dev)
 243 {
 244         drm_i915_private_t *dev_priv = dev->dev_private;
 245         struct intel_crtc *crtc;
 246         struct drm_crtc_helper_funcs *crtc_funcs;
 247         struct drm_display_mode vesa_640x480 = {
 248                 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 249                          752, 800, 0, 480, 489, 492, 525, 0,
 250                          DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
 251         }, *mode;
 252
 253         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
 254         if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
 255                 return 0;
 256
 257         /* most i8xx have pipe a forced on, so don't trust dpms mode */
 258         if (I915_READ(PIPEACONF) & PIPECONF_ENABLE)
 259                 return 0;
 260
 261         crtc_funcs = crtc->base.helper_private;
 262         if (crtc_funcs->dpms == NULL)
 263                 return 0;
 264
 265         DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
 266
 267         mode = drm_mode_duplicate(dev, &vesa_640x480);
 268         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
 269         if(!drm_crtc_helper_set_mode(&crtc->base, mode,
 270                                        crtc->base.x, crtc->base.y,
 271                                        crtc->base.fb))
 272                 return 0;
 273
 274         crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
 275         return 1;
 276 }
 277
 278 static void
 279 i830_deactivate_pipe_a(struct drm_device *dev)
 280 {
 281         drm_i915_private_t *dev_priv = dev->dev_private;
 282         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
 283         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 284
 285         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 286 }
 287
 288 /* overlay needs to be disable in OCMD reg */
 289 static int intel_overlay_on(struct intel_overlay *overlay)
 290 {
 291         struct drm_device *dev = overlay->dev;
 292         struct drm_i915_gem_request *request;
 293         int pipe_a_quirk = 0;
 294         int ret;
 295
 296         BUG_ON(overlay->active);
 297         overlay->active = 1;
 298
 299         if (IS_I830(dev)) {
 300                 pipe_a_quirk = i830_activate_pipe_a(dev);
 301                 if (pipe_a_quirk < 0)
 302                         return pipe_a_quirk;
 303         }
 304
 305         request = kzalloc(sizeof(*request), GFP_KERNEL);
 306         if (request == NULL) {
 307                 ret = -ENOMEM;
 308                 goto out;
 309         }
 310
 311         BEGIN_LP_RING(4);
 312         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 313         OUT_RING(overlay->flip_addr | OFC_UPDATE);
 314         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 315         OUT_RING(MI_NOOP);
 316         ADVANCE_LP_RING();
 317
 318         ret = intel_overlay_do_wait_request(overlay, request, true, NULL);
 319 out:
 320         if (pipe_a_quirk)
 321                 i830_deactivate_pipe_a(dev);
 322
 323         return ret;
 324 }
 325
 326 /* overlay needs to be enabled in OCMD reg */
 327 static int intel_overlay_continue(struct intel_overlay *overlay,
 328                                   bool load_polyphase_filter)
 329 {
 330         struct drm_device *dev = overlay->dev;
 331         drm_i915_private_t *dev_priv = dev->dev_private;
 332         struct drm_i915_gem_request *request;
 333         u32 flip_addr = overlay->flip_addr;
 334         u32 tmp;
 335
 336         BUG_ON(!overlay->active);
 337
 338         request = kzalloc(sizeof(*request), GFP_KERNEL);
 339         if (request == NULL)
 340                 return -ENOMEM;
 341
 342         if (load_polyphase_filter)
 343                 flip_addr |= OFC_UPDATE;
 344
 345         /* check for underruns */
 346         tmp = I915_READ(DOVSTA);
 347         if (tmp & (1 << 17))
 348                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 349
 350         BEGIN_LP_RING(2);
 351         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 352         OUT_RING(flip_addr);
 353         ADVANCE_LP_RING();
 354
 355         overlay->last_flip_req =
 356                 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
 357         return 0;
 358 }
 359
 360 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
 361 {
 362         struct drm_gem_object *obj = &overlay->old_vid_bo->base;
 363
 364         i915_gem_object_unpin(obj);
 365         drm_gem_object_unreference(obj);
 366
 367         overlay->old_vid_bo = NULL;
 368 }
 369
 370 static void intel_overlay_off_tail(struct intel_overlay *overlay)
 371 {
 372         struct drm_gem_object *obj;
 373
 374         /* never have the overlay hw on without showing a frame */
 375         BUG_ON(!overlay->vid_bo);
 376         obj = &overlay->vid_bo->base;
 377
 378         i915_gem_object_unpin(obj);
 379         drm_gem_object_unreference(obj);
 380         overlay->vid_bo = NULL;
 381
 382         overlay->crtc->overlay = NULL;
 383         overlay->crtc = NULL;
 384         overlay->active = 0;
 385 }
 386
 387 /* overlay needs to be disabled in OCMD reg */
 388 static int intel_overlay_off(struct intel_overlay *overlay,
 389                              bool interruptible)
 390 {
 391         struct drm_device *dev = overlay->dev;
 392         u32 flip_addr = overlay->flip_addr;
 393         struct drm_i915_gem_request *request;
 394
 395         BUG_ON(!overlay->active);
 396
 397         request = kzalloc(sizeof(*request), GFP_KERNEL);
 398         if (request == NULL)
 399                 return -ENOMEM;
 400
 401         /* According to intel docs the overlay hw may hang (when switching
 402          * off) without loading the filter coeffs. It is however unclear whether
 403          * this applies to the disabling of the overlay or to the switching off
 404          * of the hw. Do it in both cases */
 405         flip_addr |= OFC_UPDATE;
 406
 407         BEGIN_LP_RING(6);
 408         /* wait for overlay to go idle */
 409         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 410         OUT_RING(flip_addr);
 411         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 412         /* turn overlay off */
 413         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 414         OUT_RING(flip_addr);
 415         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 416         ADVANCE_LP_RING();
 417
 418         return intel_overlay_do_wait_request(overlay, request, interruptible,
 419                                              intel_overlay_off_tail);
 420 }
 421
 422 /* recover from an interruption due to a signal
 423  * We have to be careful not to repeat work forever an make forward progess. */
 424 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
 425                                                 bool interruptible)
 426 {
 427         struct drm_device *dev = overlay->dev;
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         int ret;
 430
 431         if (overlay->last_flip_req == 0)
 432                 return 0;
 433
 434         ret = i915_do_wait_request(dev, overlay->last_flip_req,
 435                                    interruptible, &dev_priv->render_ring);
 436         if (ret)
 437                 return ret;
 438
 439         if (overlay->flip_tail)
 440                 overlay->flip_tail(overlay);
 441
 442         overlay->last_flip_req = 0;
 443         return 0;
 444 }
 445
 446 /* Wait for pending overlay flip and release old frame.
 447  * Needs to be called before the overlay register are changed
 448  * via intel_overlay_(un)map_regs
 449  */
 450 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 451 {
 452         struct drm_device *dev = overlay->dev;
 453         drm_i915_private_t *dev_priv = dev->dev_private;
 454         int ret;
 455
 456         /* Only wait if there is actually an old frame to release to
 457          * guarantee forward progress.
 458          */
 459         if (!overlay->old_vid_bo)
 460                 return 0;
 461
 462         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 463                 struct drm_i915_gem_request *request;
 464
 465                 /* synchronous slowpath */
 466                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 467                 if (request == NULL)
 468                         return -ENOMEM;
 469
 470                 BEGIN_LP_RING(2);
 471                 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 472                 OUT_RING(MI_NOOP);
 473                 ADVANCE_LP_RING();
 474
 475                 ret = intel_overlay_do_wait_request(overlay, request, true,
 476                                                     intel_overlay_release_old_vid_tail);
 477                 if (ret)
 478                         return ret;
 479         }
 480
 481         intel_overlay_release_old_vid_tail(overlay);
 482         return 0;
 483 }
 484
 485 struct put_image_params {
 486         int format;
 487         short dst_x;
 488         short dst_y;
 489         short dst_w;
 490         short dst_h;
 491         short src_w;
 492         short src_scan_h;
 493         short src_scan_w;
 494         short src_h;
 495         short stride_Y;
 496         short stride_UV;
 497         int offset_Y;
 498         int offset_U;
 499         int offset_V;
 500 };
 501
 502 static int packed_depth_bytes(u32 format)
 503 {
 504         switch (format & I915_OVERLAY_DEPTH_MASK) {
 505         case I915_OVERLAY_YUV422:
 506                 return 4;
 507         case I915_OVERLAY_YUV411:
 508                 /* return 6; not implemented */
 509         default:
 510                 return -EINVAL;
 511         }
 512 }
 513
 514 static int packed_width_bytes(u32 format, short width)
 515 {
 516         switch (format & I915_OVERLAY_DEPTH_MASK) {
 517         case I915_OVERLAY_YUV422:
 518                 return width << 1;
 519         default:
 520                 return -EINVAL;
 521         }
 522 }
 523
 524 static int uv_hsubsampling(u32 format)
 525 {
 526         switch (format & I915_OVERLAY_DEPTH_MASK) {
 527         case I915_OVERLAY_YUV422:
 528         case I915_OVERLAY_YUV420:
 529                 return 2;
 530         case I915_OVERLAY_YUV411:
 531         case I915_OVERLAY_YUV410:
 532                 return 4;
 533         default:
 534                 return -EINVAL;
 535         }
 536 }
 537
 538 static int uv_vsubsampling(u32 format)
 539 {
 540         switch (format & I915_OVERLAY_DEPTH_MASK) {
 541         case I915_OVERLAY_YUV420:
 542         case I915_OVERLAY_YUV410:
 543                 return 2;
 544         case I915_OVERLAY_YUV422:
 545         case I915_OVERLAY_YUV411:
 546                 return 1;
 547         default:
 548                 return -EINVAL;
 549         }
 550 }
 551
 552 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
 553 {
 554         u32 mask, shift, ret;
 555         if (IS_I9XX(dev)) {
 556                 mask = 0x3f;
 557                 shift = 6;
 558         } else {
 559                 mask = 0x1f;
 560                 shift = 5;
 561         }
 562         ret = ((offset + width + mask) >> shift) - (offset >> shift);
 563         if (IS_I9XX(dev))
 564                 ret <<= 1;
 565         ret -=1;
 566         return ret << 2;
 567 }
 568
 569 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
 570         0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
 571         0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
 572         0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
 573         0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
 574         0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
 575         0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
 576         0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
 577         0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
 578         0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
 579         0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
 580         0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
 581         0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
 582         0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
 583         0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
 584         0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
 585         0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
 586         0xb000, 0x3000, 0x0800, 0x3000, 0xb000
 587 };
 588
 589 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
 590         0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
 591         0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
 592         0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
 593         0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
 594         0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
 595         0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
 596         0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
 597         0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
 598         0x3000, 0x0800, 0x3000
 599 };
 600
 601 static void update_polyphase_filter(struct overlay_registers *regs)
 602 {
 603         memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 604         memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
 605 }
 606
 607 static bool update_scaling_factors(struct intel_overlay *overlay,
 608                                    struct overlay_registers *regs,
 609                                    struct put_image_params *params)
 610 {
 611         /* fixed point with a 12 bit shift */
 612         u32 xscale, yscale, xscale_UV, yscale_UV;
 613 #define FP_SHIFT 12
 614 #define FRACT_MASK 0xfff
 615         bool scale_changed = false;
 616         int uv_hscale = uv_hsubsampling(params->format);
 617         int uv_vscale = uv_vsubsampling(params->format);
 618
 619         if (params->dst_w > 1)
 620                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 621                         /(params->dst_w);
 622         else
 623                 xscale = 1 << FP_SHIFT;
 624
 625         if (params->dst_h > 1)
 626                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 627                         /(params->dst_h);
 628         else
 629                 yscale = 1 << FP_SHIFT;
 630
 631         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 632         xscale_UV = xscale/uv_hscale;
 633         yscale_UV = yscale/uv_vscale;
 634         /* make the Y scale to UV scale ratio an exact multiply */
 635         xscale = xscale_UV * uv_hscale;
 636         yscale = yscale_UV * uv_vscale;
 637         /*} else {
 638           xscale_UV = 0;
 639           yscale_UV = 0;
 640           }*/
 641
 642         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 643                 scale_changed = true;
 644         overlay->old_xscale = xscale;
 645         overlay->old_yscale = yscale;
 646
 647         regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
 648                            ((xscale >> FP_SHIFT)  << 16) |
 649                            ((xscale & FRACT_MASK) << 3));
 650
 651         regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
 652                          ((xscale_UV >> FP_SHIFT)  << 16) |
 653                          ((xscale_UV & FRACT_MASK) << 3));
 654
 655         regs->UVSCALEV = ((((yscale    >> FP_SHIFT) << 16) |
 656                            ((yscale_UV >> FP_SHIFT) << 0)));
 657
 658         if (scale_changed)
 659                 update_polyphase_filter(regs);
 660
 661         return scale_changed;
 662 }
 663
 664 static void update_colorkey(struct intel_overlay *overlay,
 665                             struct overlay_registers *regs)
 666 {
 667         u32 key = overlay->color_key;
 668
 669         switch (overlay->crtc->base.fb->bits_per_pixel) {
 670         case 8:
 671                 regs->DCLRKV = 0;
 672                 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
 673                 break;
 674
 675         case 16:
 676                 if (overlay->crtc->base.fb->depth == 15) {
 677                         regs->DCLRKV = RGB15_TO_COLORKEY(key);
 678                         regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
 679                 } else {
 680                         regs->DCLRKV = RGB16_TO_COLORKEY(key);
 681                         regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
 682                 }
 683                 break;
 684
 685         case 24:
 686         case 32:
 687                 regs->DCLRKV = key;
 688                 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
 689                 break;
 690         }
 691 }
 692
 693 static u32 overlay_cmd_reg(struct put_image_params *params)
 694 {
 695         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 696
 697         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 698                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 699                 case I915_OVERLAY_YUV422:
 700                         cmd |= OCMD_YUV_422_PLANAR;
 701                         break;
 702                 case I915_OVERLAY_YUV420:
 703                         cmd |= OCMD_YUV_420_PLANAR;
 704                         break;
 705                 case I915_OVERLAY_YUV411:
 706                 case I915_OVERLAY_YUV410:
 707                         cmd |= OCMD_YUV_410_PLANAR;
 708                         break;
 709                 }
 710         } else { /* YUV packed */
 711                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 712                 case I915_OVERLAY_YUV422:
 713                         cmd |= OCMD_YUV_422_PACKED;
 714                         break;
 715                 case I915_OVERLAY_YUV411:
 716                         cmd |= OCMD_YUV_411_PACKED;
 717                         break;
 718                 }
 719
 720                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 721                 case I915_OVERLAY_NO_SWAP:
 722                         break;
 723                 case I915_OVERLAY_UV_SWAP:
 724                         cmd |= OCMD_UV_SWAP;
 725                         break;
 726                 case I915_OVERLAY_Y_SWAP:
 727                         cmd |= OCMD_Y_SWAP;
 728                         break;
 729                 case I915_OVERLAY_Y_AND_UV_SWAP:
 730                         cmd |= OCMD_Y_AND_UV_SWAP;
 731                         break;
 732                 }
 733         }
 734
 735         return cmd;
 736 }
 737
 738 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 739                                       struct drm_gem_object *new_bo,
 740                                       struct put_image_params *params)
 741 {
 742         int ret, tmp_width;
 743         struct overlay_registers *regs;
 744         bool scale_changed = false;
 745         struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
 746         struct drm_device *dev = overlay->dev;
 747
 748         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 749         BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
 750         BUG_ON(!overlay);
 751
 752         ret = intel_overlay_release_old_vid(overlay);
 753         if (ret != 0)
 754                 return ret;
 755
 756         ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
 757         if (ret != 0)
 758                 return ret;
 759
 760         ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
 761         if (ret != 0)
 762                 goto out_unpin;
 763
 764         if (!overlay->active) {
 765                 regs = intel_overlay_map_regs(overlay);
 766                 if (!regs) {
 767                         ret = -ENOMEM;
 768                         goto out_unpin;
 769                 }
 770                 regs->OCONFIG = OCONF_CC_OUT_8BIT;
 771                 if (IS_I965GM(overlay->dev))
 772                         regs->OCONFIG |= OCONF_CSC_MODE_BT709;
 773                 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
 774                         OCONF_PIPE_A : OCONF_PIPE_B;
 775                 intel_overlay_unmap_regs(overlay, regs);
 776
 777                 ret = intel_overlay_on(overlay);
 778                 if (ret != 0)
 779                         goto out_unpin;
 780         }
 781
 782         regs = intel_overlay_map_regs(overlay);
 783         if (!regs) {
 784                 ret = -ENOMEM;
 785                 goto out_unpin;
 786         }
 787
 788         regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
 789         regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
 790
 791         if (params->format & I915_OVERLAY_YUV_PACKED)
 792                 tmp_width = packed_width_bytes(params->format, params->src_w);
 793         else
 794                 tmp_width = params->src_w;
 795
 796         regs->SWIDTH = params->src_w;
 797         regs->SWIDTHSW = calc_swidthsw(overlay->dev,
 798                                        params->offset_Y, tmp_width);
 799         regs->SHEIGHT = params->src_h;
 800         regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
 801         regs->OSTRIDE = params->stride_Y;
 802
 803         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 804                 int uv_hscale = uv_hsubsampling(params->format);
 805                 int uv_vscale = uv_vsubsampling(params->format);
 806                 u32 tmp_U, tmp_V;
 807                 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
 808                 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
 809                                       params->src_w/uv_hscale);
 810                 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
 811                                       params->src_w/uv_hscale);
 812                 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
 813                 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
 814                 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
 815                 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
 816                 regs->OSTRIDE |= params->stride_UV << 16;
 817         }
 818
 819         scale_changed = update_scaling_factors(overlay, regs, params);
 820
 821         update_colorkey(overlay, regs);
 822
 823         regs->OCMD = overlay_cmd_reg(params);
 824
 825         intel_overlay_unmap_regs(overlay, regs);
 826
 827         ret = intel_overlay_continue(overlay, scale_changed);
 828         if (ret)
 829                 goto out_unpin;
 830
 831         overlay->old_vid_bo = overlay->vid_bo;
 832         overlay->vid_bo = to_intel_bo(new_bo);
 833
 834         return 0;
 835
 836 out_unpin:
 837         i915_gem_object_unpin(new_bo);
 838         return ret;
 839 }
 840
 841 int intel_overlay_switch_off(struct intel_overlay *overlay,
 842                              bool interruptible)
 843 {
 844         struct overlay_registers *regs;
 845         struct drm_device *dev = overlay->dev;
 846         int ret;
 847
 848         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 849         BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
 850
 851         ret = intel_overlay_recover_from_interrupt(overlay, interruptible);
 852         if (ret != 0)
 853                 return ret;
 854
 855         if (!overlay->active)
 856                 return 0;
 857
 858         ret = intel_overlay_release_old_vid(overlay);
 859         if (ret != 0)
 860                 return ret;
 861
 862         regs = intel_overlay_map_regs(overlay);
 863         regs->OCMD = 0;
 864         intel_overlay_unmap_regs(overlay, regs);
 865
 866         ret = intel_overlay_off(overlay, interruptible);
 867         if (ret != 0)
 868                 return ret;
 869
 870         intel_overlay_off_tail(overlay);
 871         return 0;
 872 }
 873
 874 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 875                                           struct intel_crtc *crtc)
 876 {
 877         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
 878
 879         if (!crtc->active)
 880                 return -EINVAL;
 881
 882         /* can't use the overlay with double wide pipe */
 883         if (!IS_I965G(overlay->dev) &&
 884             (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
 885                 return -EINVAL;
 886
 887         return 0;
 888 }
 889
 890 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 891 {
 892         struct drm_device *dev = overlay->dev;
 893         drm_i915_private_t *dev_priv = dev->dev_private;
 894         u32 pfit_control = I915_READ(PFIT_CONTROL);
 895         u32 ratio;
 896
 897         /* XXX: This is not the same logic as in the xorg driver, but more in
 898          * line with the intel documentation for the i965
 899          */
 900         if (!IS_I965G(dev)) {
 901                 if (pfit_control & VERT_AUTO_SCALE)
 902                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 903                 else
 904                         ratio = I915_READ(PFIT_PGM_RATIOS);
 905                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 906         } else { /* on i965 use the PGM reg to read out the autoscaler values */
 907                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 908         }
 909
 910         overlay->pfit_vscale_ratio = ratio;
 911 }
 912
 913 static int check_overlay_dst(struct intel_overlay *overlay,
 914                              struct drm_intel_overlay_put_image *rec)
 915 {
 916         struct drm_display_mode *mode = &overlay->crtc->base.mode;
 917
 918         if (rec->dst_x < mode->crtc_hdisplay &&
 919             rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
 920             rec->dst_y < mode->crtc_vdisplay &&
 921             rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
 922                 return 0;
 923         else
 924                 return -EINVAL;
 925 }
 926
 927 static int check_overlay_scaling(struct put_image_params *rec)
 928 {
 929         u32 tmp;
 930
 931         /* downscaling limit is 8.0 */
 932         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 933         if (tmp > 7)
 934                 return -EINVAL;
 935         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 936         if (tmp > 7)
 937                 return -EINVAL;
 938
 939         return 0;
 940 }
 941
 942 static int check_overlay_src(struct drm_device *dev,
 943                              struct drm_intel_overlay_put_image *rec,
 944                              struct drm_gem_object *new_bo)
 945 {
 946         int uv_hscale = uv_hsubsampling(rec->flags);
 947         int uv_vscale = uv_vsubsampling(rec->flags);
 948         u32 stride_mask, depth, tmp;
 949
 950         /* check src dimensions */
 951         if (IS_845G(dev) || IS_I830(dev)) {
 952                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 953                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 954                         return -EINVAL;
 955         } else {
 956                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 957                     rec->src_width  > IMAGE_MAX_WIDTH)
 958                         return -EINVAL;
 959         }
 960
 961         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 962         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 963             rec->src_width  < N_HORIZ_Y_TAPS*4)
 964                 return -EINVAL;
 965
 966         /* check alignment constraints */
 967         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 968         case I915_OVERLAY_RGB:
 969                 /* not implemented */
 970                 return -EINVAL;
 971
 972         case I915_OVERLAY_YUV_PACKED:
 973                 if (uv_vscale != 1)
 974                         return -EINVAL;
 975
 976                 depth = packed_depth_bytes(rec->flags);
 977                 if (depth < 0)
 978                         return depth;
 979
 980                 /* ignore UV planes */
 981                 rec->stride_UV = 0;
 982                 rec->offset_U = 0;
 983                 rec->offset_V = 0;
 984                 /* check pixel alignment */
 985                 if (rec->offset_Y % depth)
 986                         return -EINVAL;
 987                 break;
 988
 989         case I915_OVERLAY_YUV_PLANAR:
 990                 if (uv_vscale < 0 || uv_hscale < 0)
 991                         return -EINVAL;
 992                 /* no offset restrictions for planar formats */
 993                 break;
 994
 995         default:
 996                 return -EINVAL;
 997         }
 998
 999         if (rec->src_width % uv_hscale)
1000                 return -EINVAL;
1001
1002         /* stride checking */
1003         if (IS_I830(dev) || IS_845G(dev))
1004                 stride_mask = 255;
1005         else
1006                 stride_mask = 63;
1007
1008         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1009                 return -EINVAL;
1010         if (IS_I965G(dev) && rec->stride_Y < 512)
1011                 return -EINVAL;
1012
1013         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1014                 4096 : 8192;
1015         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1016                 return -EINVAL;
1017
1018         /* check buffer dimensions */
1019         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1020         case I915_OVERLAY_RGB:
1021         case I915_OVERLAY_YUV_PACKED:
1022                 /* always 4 Y values per depth pixels */
1023                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1024                         return -EINVAL;
1025
1026                 tmp = rec->stride_Y*rec->src_height;
1027                 if (rec->offset_Y + tmp > new_bo->size)
1028                         return -EINVAL;
1029                 break;
1030
1031         case I915_OVERLAY_YUV_PLANAR:
1032                 if (rec->src_width > rec->stride_Y)
1033                         return -EINVAL;
1034                 if (rec->src_width/uv_hscale > rec->stride_UV)
1035                         return -EINVAL;
1036
1037                 tmp = rec->stride_Y * rec->src_height;
1038                 if (rec->offset_Y + tmp > new_bo->size)
1039                         return -EINVAL;
1040
1041                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1042                 if (rec->offset_U + tmp > new_bo->size ||
1043                     rec->offset_V + tmp > new_bo->size)
1044                         return -EINVAL;
1045                 break;
1046         }
1047
1048         return 0;
1049 }
1050
1051 /**
1052  * Return the pipe currently connected to the panel fitter,
1053  * or -1 if the panel fitter is not present or not in use
1054  */
1055 static int intel_panel_fitter_pipe(struct drm_device *dev)
1056 {
1057         struct drm_i915_private *dev_priv = dev->dev_private;
1058         u32  pfit_control;
1059
1060         /* i830 doesn't have a panel fitter */
1061         if (IS_I830(dev))
1062                 return -1;
1063
1064         pfit_control = I915_READ(PFIT_CONTROL);
1065
1066         /* See if the panel fitter is in use */
1067         if ((pfit_control & PFIT_ENABLE) == 0)
1068                 return -1;
1069
1070         /* 965 can place panel fitter on either pipe */
1071         if (IS_I965G(dev))
1072                 return (pfit_control >> 29) & 0x3;
1073
1074         /* older chips can only use pipe 1 */
1075         return 1;
1076 }
1077
1078 int intel_overlay_put_image(struct drm_device *dev, void *data,
1079                             struct drm_file *file_priv)
1080 {
1081         struct drm_intel_overlay_put_image *put_image_rec = data;
1082         drm_i915_private_t *dev_priv = dev->dev_private;
1083         struct intel_overlay *overlay;
1084         struct drm_mode_object *drmmode_obj;
1085         struct intel_crtc *crtc;
1086         struct drm_gem_object *new_bo;
1087         struct put_image_params *params;
1088         int ret;
1089
1090         if (!dev_priv) {
1091                 DRM_ERROR("called with no initialization\n");
1092                 return -EINVAL;
1093         }
1094
1095         overlay = dev_priv->overlay;
1096         if (!overlay) {
1097                 DRM_DEBUG("userspace bug: no overlay\n");
1098                 return -ENODEV;
1099         }
1100
1101         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1102                 mutex_lock(&dev->mode_config.mutex);
1103                 mutex_lock(&dev->struct_mutex);
1104
1105                 ret = intel_overlay_switch_off(overlay, true);
1106
1107                 mutex_unlock(&dev->struct_mutex);
1108                 mutex_unlock(&dev->mode_config.mutex);
1109
1110                 return ret;
1111         }
1112
1113         params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1114         if (!params)
1115                 return -ENOMEM;
1116
1117         drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1118                                            DRM_MODE_OBJECT_CRTC);
1119         if (!drmmode_obj) {
1120                 ret = -ENOENT;
1121                 goto out_free;
1122         }
1123         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1124
1125         new_bo = drm_gem_object_lookup(dev, file_priv,
1126                                        put_image_rec->bo_handle);
1127         if (!new_bo) {
1128                 ret = -ENOENT;
1129                 goto out_free;
1130         }
1131
1132         mutex_lock(&dev->mode_config.mutex);
1133         mutex_lock(&dev->struct_mutex);
1134
1135         ret = intel_overlay_recover_from_interrupt(overlay, true);
1136         if (ret != 0)
1137                 goto out_unlock;
1138
1139         if (overlay->crtc != crtc) {
1140                 struct drm_display_mode *mode = &crtc->base.mode;
1141                 ret = intel_overlay_switch_off(overlay, true);
1142                 if (ret != 0)
1143                         goto out_unlock;
1144
1145                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1146                 if (ret != 0)
1147                         goto out_unlock;
1148
1149                 overlay->crtc = crtc;
1150                 crtc->overlay = overlay;
1151
1152                 /* line too wide, i.e. one-line-mode */
1153                 if (mode->hdisplay > 1024 &&
1154                     intel_panel_fitter_pipe(dev) == crtc->pipe) {
1155                         overlay->pfit_active = 1;
1156                         update_pfit_vscale_ratio(overlay);
1157                 } else
1158                         overlay->pfit_active = 0;
1159         }
1160
1161         ret = check_overlay_dst(overlay, put_image_rec);
1162         if (ret != 0)
1163                 goto out_unlock;
1164
1165         if (overlay->pfit_active) {
1166                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1167                                  overlay->pfit_vscale_ratio);
1168                 /* shifting right rounds downwards, so add 1 */
1169                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1170                                  overlay->pfit_vscale_ratio) + 1;
1171         } else {
1172                 params->dst_y = put_image_rec->dst_y;
1173                 params->dst_h = put_image_rec->dst_height;
1174         }
1175         params->dst_x = put_image_rec->dst_x;
1176         params->dst_w = put_image_rec->dst_width;
1177
1178         params->src_w = put_image_rec->src_width;
1179         params->src_h = put_image_rec->src_height;
1180         params->src_scan_w = put_image_rec->src_scan_width;
1181         params->src_scan_h = put_image_rec->src_scan_height;
1182         if (params->src_scan_h > params->src_h ||
1183             params->src_scan_w > params->src_w) {
1184                 ret = -EINVAL;
1185                 goto out_unlock;
1186         }
1187
1188         ret = check_overlay_src(dev, put_image_rec, new_bo);
1189         if (ret != 0)
1190                 goto out_unlock;
1191         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1192         params->stride_Y = put_image_rec->stride_Y;
1193         params->stride_UV = put_image_rec->stride_UV;
1194         params->offset_Y = put_image_rec->offset_Y;
1195         params->offset_U = put_image_rec->offset_U;
1196         params->offset_V = put_image_rec->offset_V;
1197
1198         /* Check scaling after src size to prevent a divide-by-zero. */
1199         ret = check_overlay_scaling(params);
1200         if (ret != 0)
1201                 goto out_unlock;
1202
1203         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1204         if (ret != 0)
1205                 goto out_unlock;
1206
1207         mutex_unlock(&dev->struct_mutex);
1208         mutex_unlock(&dev->mode_config.mutex);
1209
1210         kfree(params);
1211
1212         return 0;
1213
1214 out_unlock:
1215         mutex_unlock(&dev->struct_mutex);
1216         mutex_unlock(&dev->mode_config.mutex);
1217         drm_gem_object_unreference_unlocked(new_bo);
1218 out_free:
1219         kfree(params);
1220
1221         return ret;
1222 }
1223
1224 static void update_reg_attrs(struct intel_overlay *overlay,
1225                              struct overlay_registers *regs)
1226 {
1227         regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1228         regs->OCLRC1 = overlay->saturation;
1229 }
1230
1231 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1232 {
1233         int i;
1234
1235         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1236                 return false;
1237
1238         for (i = 0; i < 3; i++) {
1239                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1240                         return false;
1241         }
1242
1243         return true;
1244 }
1245
1246 static bool check_gamma5_errata(u32 gamma5)
1247 {
1248         int i;
1249
1250         for (i = 0; i < 3; i++) {
1251                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1252                         return false;
1253         }
1254
1255         return true;
1256 }
1257
1258 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1259 {
1260         if (!check_gamma_bounds(0, attrs->gamma0) ||
1261             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1262             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1263             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1264             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1265             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1266             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1267                 return -EINVAL;
1268
1269         if (!check_gamma5_errata(attrs->gamma5))
1270                 return -EINVAL;
1271
1272         return 0;
1273 }
1274
1275 int intel_overlay_attrs(struct drm_device *dev, void *data,
1276                         struct drm_file *file_priv)
1277 {
1278         struct drm_intel_overlay_attrs *attrs = data;
1279         drm_i915_private_t *dev_priv = dev->dev_private;
1280         struct intel_overlay *overlay;
1281         struct overlay_registers *regs;
1282         int ret;
1283
1284         if (!dev_priv) {
1285                 DRM_ERROR("called with no initialization\n");
1286                 return -EINVAL;
1287         }
1288
1289         overlay = dev_priv->overlay;
1290         if (!overlay) {
1291                 DRM_DEBUG("userspace bug: no overlay\n");
1292                 return -ENODEV;
1293         }
1294
1295         mutex_lock(&dev->mode_config.mutex);
1296         mutex_lock(&dev->struct_mutex);
1297
1298         ret = -EINVAL;
1299         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1300                 attrs->color_key  = overlay->color_key;
1301                 attrs->brightness = overlay->brightness;
1302                 attrs->contrast   = overlay->contrast;
1303                 attrs->saturation = overlay->saturation;
1304
1305                 if (IS_I9XX(dev)) {
1306                         attrs->gamma0 = I915_READ(OGAMC0);
1307                         attrs->gamma1 = I915_READ(OGAMC1);
1308                         attrs->gamma2 = I915_READ(OGAMC2);
1309                         attrs->gamma3 = I915_READ(OGAMC3);
1310                         attrs->gamma4 = I915_READ(OGAMC4);
1311                         attrs->gamma5 = I915_READ(OGAMC5);
1312                 }
1313         } else {
1314                 if (attrs->brightness < -128 || attrs->brightness > 127)
1315                         goto out_unlock;
1316                 if (attrs->contrast > 255)
1317                         goto out_unlock;
1318                 if (attrs->saturation > 1023)
1319                         goto out_unlock;
1320
1321                 overlay->color_key  = attrs->color_key;
1322                 overlay->brightness = attrs->brightness;
1323                 overlay->contrast   = attrs->contrast;
1324                 overlay->saturation = attrs->saturation;
1325
1326                 regs = intel_overlay_map_regs(overlay);
1327                 if (!regs) {
1328                         ret = -ENOMEM;
1329                         goto out_unlock;
1330                 }
1331
1332                 update_reg_attrs(overlay, regs);
1333
1334                 intel_overlay_unmap_regs(overlay, regs);
1335
1336                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1337                         if (!IS_I9XX(dev))
1338                                 goto out_unlock;
1339
1340                         if (overlay->active) {
1341                                 ret = -EBUSY;
1342                                 goto out_unlock;
1343                         }
1344
1345                         ret = check_gamma(attrs);
1346                         if (ret)
1347                                 goto out_unlock;
1348
1349                         I915_WRITE(OGAMC0, attrs->gamma0);
1350                         I915_WRITE(OGAMC1, attrs->gamma1);
1351                         I915_WRITE(OGAMC2, attrs->gamma2);
1352                         I915_WRITE(OGAMC3, attrs->gamma3);
1353                         I915_WRITE(OGAMC4, attrs->gamma4);
1354                         I915_WRITE(OGAMC5, attrs->gamma5);
1355                 }
1356         }
1357
1358         ret = 0;
1359 out_unlock:
1360         mutex_unlock(&dev->struct_mutex);
1361         mutex_unlock(&dev->mode_config.mutex);
1362
1363         return ret;
1364 }
1365
1366 void intel_setup_overlay(struct drm_device *dev)
1367 {
1368         drm_i915_private_t *dev_priv = dev->dev_private;
1369         struct intel_overlay *overlay;
1370         struct drm_gem_object *reg_bo;
1371         struct overlay_registers *regs;
1372         int ret;
1373
1374         if (!HAS_OVERLAY(dev))
1375                 return;
1376
1377         overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1378         if (!overlay)
1379                 return;
1380         overlay->dev = dev;
1381
1382         reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1383         if (!reg_bo)
1384                 goto out_free;
1385         overlay->reg_bo = to_intel_bo(reg_bo);
1386
1387         if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1388                 ret = i915_gem_attach_phys_object(dev, reg_bo,
1389                                                   I915_GEM_PHYS_OVERLAY_REGS,
1390                                                   PAGE_SIZE);
1391                 if (ret) {
1392                         DRM_ERROR("failed to attach phys overlay regs\n");
1393                         goto out_free_bo;
1394                 }
1395                 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1396         } else {
1397                 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1398                 if (ret) {
1399                         DRM_ERROR("failed to pin overlay register bo\n");
1400                         goto out_free_bo;
1401                 }
1402                 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1403
1404                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1405                 if (ret) {
1406                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1407                         goto out_unpin_bo;
1408                 }
1409         }
1410
1411         /* init all values */
1412         overlay->color_key = 0x0101fe;
1413         overlay->brightness = -19;
1414         overlay->contrast = 75;
1415         overlay->saturation = 146;
1416
1417         regs = intel_overlay_map_regs(overlay);
1418         if (!regs)
1419                 goto out_free_bo;
1420
1421         memset(regs, 0, sizeof(struct overlay_registers));
1422         update_polyphase_filter(regs);
1423         update_reg_attrs(overlay, regs);
1424
1425         intel_overlay_unmap_regs(overlay, regs);
1426
1427         dev_priv->overlay = overlay;
1428         DRM_INFO("initialized overlay support\n");
1429         return;
1430
1431 out_unpin_bo:
1432         i915_gem_object_unpin(reg_bo);
1433 out_free_bo:
1434         drm_gem_object_unreference(reg_bo);
1435 out_free:
1436         kfree(overlay);
1437         return;
1438 }
1439
1440 void intel_cleanup_overlay(struct drm_device *dev)
1441 {
1442         drm_i915_private_t *dev_priv = dev->dev_private;
1443
1444         if (!dev_priv->overlay)
1445                 return;
1446
1447         /* The bo's should be free'd by the generic code already.
1448          * Furthermore modesetting teardown happens beforehand so the
1449          * hardware should be off already */
1450         BUG_ON(dev_priv->overlay->active);
1451
1452         drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1453         kfree(dev_priv->overlay);
1454 }
1455
1456 #ifdef CONFIG_DEBUG_FS
1457 #include <linux/seq_file.h>
1458
1459 struct intel_overlay_error_state {
1460         struct overlay_registers regs;
1461         unsigned long base;
1462         u32 dovsta;
1463         u32 isr;
1464 };
1465
1466 static struct overlay_registers *
1467 intel_overlay_map_regs_atomic(struct intel_overlay *overlay,
1468                               int slot)
1469 {
1470         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1471         struct overlay_registers *regs;
1472
1473         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1474                 regs = overlay->reg_bo->phys_obj->handle->vaddr;
1475         else
1476                 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1477                                                 overlay->reg_bo->gtt_offset,
1478                                                 slot);
1479
1480         return regs;
1481 }
1482
1483 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1484                                             int slot,
1485                                             struct overlay_registers *regs)
1486 {
1487         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1488                 io_mapping_unmap_atomic(regs, slot);
1489 }
1490
1491
1492 struct intel_overlay_error_state *
1493 intel_overlay_capture_error_state(struct drm_device *dev)
1494 {
1495         drm_i915_private_t *dev_priv = dev->dev_private;
1496         struct intel_overlay *overlay = dev_priv->overlay;
1497         struct intel_overlay_error_state *error;
1498         struct overlay_registers __iomem *regs;
1499
1500         if (!overlay || !overlay->active)
1501                 return NULL;
1502
1503         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1504         if (error == NULL)
1505                 return NULL;
1506
1507         error->dovsta = I915_READ(DOVSTA);
1508         error->isr = I915_READ(ISR);
1509         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1510                 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1511         else
1512                 error->base = (long) overlay->reg_bo->gtt_offset;
1513
1514         regs = intel_overlay_map_regs_atomic(overlay, KM_IRQ0);
1515         if (!regs)
1516                 goto err;
1517
1518         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1519         intel_overlay_unmap_regs_atomic(overlay, KM_IRQ0, regs);
1520
1521         return error;
1522
1523 err:
1524         kfree(error);
1525         return NULL;
1526 }
1527
1528 void
1529 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1530 {
1531         seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1532                    error->dovsta, error->isr);
1533         seq_printf(m, "  Register file at 0x%08lx:\n",
1534                    error->base);
1535
1536 #define P(x) seq_printf(m, "    " #x ": 0x%08x\n", error->regs.x)
1537         P(OBUF_0Y);
1538         P(OBUF_1Y);
1539         P(OBUF_0U);
1540         P(OBUF_0V);
1541         P(OBUF_1U);
1542         P(OBUF_1V);
1543         P(OSTRIDE);
1544         P(YRGB_VPH);
1545         P(UV_VPH);
1546         P(HORZ_PH);
1547         P(INIT_PHS);
1548         P(DWINPOS);
1549         P(DWINSZ);
1550         P(SWIDTH);
1551         P(SWIDTHSW);
1552         P(SHEIGHT);
1553         P(YRGBSCALE);
1554         P(UVSCALE);
1555         P(OCLRC0);
1556         P(OCLRC1);
1557         P(DCLRKV);
1558         P(DCLRKM);
1559         P(SCLRKVH);
1560         P(SCLRKVL);
1561         P(SCLRKEN);
1562         P(OCONFIG);
1563         P(OCMD);
1564         P(OSTART_0Y);
1565         P(OSTART_1Y);
1566         P(OSTART_0U);
1567         P(OSTART_0V);
1568         P(OSTART_1U);
1569         P(OSTART_1V);
1570         P(OTILEOFF_0Y);
1571         P(OTILEOFF_1Y);
1572         P(OTILEOFF_0U);
1573         P(OTILEOFF_0V);
1574         P(OTILEOFF_1U);
1575         P(OTILEOFF_1V);
1576         P(FASTHSCALE);
1577         P(UVSCALEV);
1578 #undef P
1579 }
1580 #endif