2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
33 #include "intel_drv.h"
37 /* Intel GPIO access functions */
39 #define I2C_RISEFALL_TIME 20
42 struct i2c_adapter adapter;
43 struct i2c_algo_bit_data algo;
44 struct drm_i915_private *dev_priv;
49 intel_i2c_reset(struct drm_device *dev)
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 if (HAS_PCH_SPLIT(dev))
53 I915_WRITE(PCH_GMBUS0, 0);
55 I915_WRITE(GMBUS0, 0);
58 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
62 /* When using bit bashing for I2C, this bit needs to be set to 1 */
63 if (!IS_PINEVIEW(dev_priv->dev))
66 val = I915_READ(DSPCLK_GATE_D);
68 val |= DPCUNIT_CLOCK_GATE_DISABLE;
70 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
71 I915_WRITE(DSPCLK_GATE_D, val);
74 static int get_clock(void *data)
76 struct intel_gpio *gpio = data;
77 struct drm_i915_private *dev_priv = gpio->dev_priv;
78 return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
81 static int get_data(void *data)
83 struct intel_gpio *gpio = data;
84 struct drm_i915_private *dev_priv = gpio->dev_priv;
85 return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
88 static void set_clock(void *data, int state_high)
90 struct intel_gpio *gpio = data;
91 struct drm_i915_private *dev_priv = gpio->dev_priv;
92 struct drm_device *dev = dev_priv->dev;
93 u32 reserved = 0, clock_bits;
95 /* On most chips, these bits must be preserved in software. */
96 if (!IS_I830(dev) && !IS_845G(dev))
97 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
98 GPIO_CLOCK_PULLUP_DISABLE);
101 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
103 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
106 I915_WRITE(gpio->reg, reserved | clock_bits);
107 POSTING_READ(gpio->reg);
110 static void set_data(void *data, int state_high)
112 struct intel_gpio *gpio = data;
113 struct drm_i915_private *dev_priv = gpio->dev_priv;
114 struct drm_device *dev = dev_priv->dev;
115 u32 reserved = 0, data_bits;
117 /* On most chips, these bits must be preserved in software. */
118 if (!IS_I830(dev) && !IS_845G(dev))
119 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
120 GPIO_CLOCK_PULLUP_DISABLE);
123 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
125 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
128 I915_WRITE(gpio->reg, reserved | data_bits);
129 POSTING_READ(gpio->reg);
132 static struct i2c_adapter *
133 intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
135 static const int map_pin_to_reg[] = {
144 struct intel_gpio *gpio;
146 if (pin < 1 || pin > 7)
149 gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
153 gpio->reg = map_pin_to_reg[pin];
154 if (HAS_PCH_SPLIT(dev_priv->dev))
155 gpio->reg += PCH_GPIOA - GPIOA;
156 gpio->dev_priv = dev_priv;
158 snprintf(gpio->adapter.name, I2C_NAME_SIZE, "GPIO %d", pin);
159 gpio->adapter.owner = THIS_MODULE;
160 gpio->adapter.algo_data = &gpio->algo;
161 gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
162 gpio->algo.setsda = set_data;
163 gpio->algo.setscl = set_clock;
164 gpio->algo.getsda = get_data;
165 gpio->algo.getscl = get_clock;
166 gpio->algo.udelay = I2C_RISEFALL_TIME;
167 gpio->algo.timeout = usecs_to_jiffies(2200);
168 gpio->algo.data = gpio;
170 if (i2c_bit_add_bus(&gpio->adapter))
173 intel_i2c_reset(dev_priv->dev);
175 /* JJJ: raise SCL and SDA? */
176 intel_i2c_quirk_set(dev_priv, true);
178 udelay(I2C_RISEFALL_TIME);
180 udelay(I2C_RISEFALL_TIME);
181 intel_i2c_quirk_set(dev_priv, false);
183 return &gpio->adapter;
191 quirk_i2c_transfer(struct drm_i915_private *dev_priv,
192 struct i2c_adapter *adapter,
193 struct i2c_msg *msgs,
198 intel_i2c_reset(dev_priv->dev);
200 intel_i2c_quirk_set(dev_priv, true);
201 ret = i2c_transfer(adapter, msgs, num);
202 intel_i2c_quirk_set(dev_priv, false);
208 gmbus_xfer(struct i2c_adapter *adapter,
209 struct i2c_msg *msgs,
212 struct intel_gmbus *bus = container_of(adapter,
215 struct drm_i915_private *dev_priv = adapter->algo_data;
216 int i, speed, reg_offset;
218 if (bus->force_bitbanging)
219 return quirk_i2c_transfer(dev_priv, bus->force_bitbanging, msgs, num);
221 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
223 speed = GMBUS_RATE_100KHZ;
224 if (INTEL_INFO(dev_priv->dev)->gen > 4 || IS_G4X(dev_priv->dev)) {
225 if (bus->pin == GMBUS_PORT_DPB) /* SDVO only? */
226 speed = GMBUS_RATE_1MHZ;
228 speed = GMBUS_RATE_400KHZ;
230 I915_WRITE(GMBUS0 + reg_offset, speed | bus->pin);
232 for (i = 0; i < num; i++) {
233 u16 len = msgs[i].len;
234 u8 *buf = msgs[i].buf;
236 if (msgs[i].flags & I2C_M_RD) {
237 I915_WRITE(GMBUS1 + reg_offset,
238 GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
239 (len << GMBUS_BYTE_COUNT_SHIFT) |
240 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
241 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
245 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
247 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
250 val = I915_READ(GMBUS3 + reg_offset);
254 } while (--len && ++loop < 4);
257 u32 val = 0, loop = 0;
259 BUG_ON(msgs[i].len > 4);
262 val |= *buf++ << (loop*8);
263 } while (--len && +loop < 4);
265 I915_WRITE(GMBUS3 + reg_offset, val);
266 I915_WRITE(GMBUS1 + reg_offset,
267 (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT ) |
268 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
269 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
270 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
273 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
275 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
282 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d\n", bus->pin);
283 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
284 bus->force_bitbanging = intel_gpio_create(dev_priv, bus->pin);
285 if (!bus->force_bitbanging)
288 return quirk_i2c_transfer(dev_priv, bus->force_bitbanging, msgs, num);
291 static u32 gmbus_func(struct i2c_adapter *adapter)
293 return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
294 /* I2C_FUNC_10BIT_ADDR | */
295 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
296 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
299 static const struct i2c_algorithm gmbus_algorithm = {
300 .master_xfer = gmbus_xfer,
301 .functionality = gmbus_func
305 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
308 int intel_setup_gmbus(struct drm_device *dev)
310 static const char *names[] = {
320 struct drm_i915_private *dev_priv = dev->dev_private;
323 dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
325 if (dev_priv->gmbus == NULL)
328 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
329 struct intel_gmbus *bus = &dev_priv->gmbus[i];
331 bus->adapter.owner = THIS_MODULE;
332 bus->adapter.class = I2C_CLASS_DDC;
333 snprintf(bus->adapter.name,
338 bus->adapter.dev.parent = &dev->pdev->dev;
339 bus->adapter.algo_data = dev_priv;
341 bus->adapter.algo = &gmbus_algorithm;
342 ret = i2c_add_adapter(&bus->adapter);
349 intel_i2c_reset(dev_priv->dev);
355 struct intel_gmbus *bus = &dev_priv->gmbus[i];
356 i2c_del_adapter(&bus->adapter);
358 kfree(dev_priv->gmbus);
359 dev_priv->gmbus = NULL;
363 void intel_teardown_gmbus(struct drm_device *dev)
365 struct drm_i915_private *dev_priv = dev->dev_private;
368 if (dev_priv->gmbus == NULL)
371 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
372 struct intel_gmbus *bus = &dev_priv->gmbus[i];
373 if (bus->force_bitbanging) {
374 i2c_del_adapter(bus->force_bitbanging);
375 kfree(bus->force_bitbanging);
377 i2c_del_adapter(&bus->adapter);
380 kfree(dev_priv->gmbus);
381 dev_priv->gmbus = NULL;