drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         uint8_t link_bw;
  54         uint8_t lane_count;
  55         uint8_t dpcd[4];
  56         struct i2c_adapter adapter;
  57         struct i2c_algo_dp_aux_data algo;
  58         bool is_pch_edp;
  59         uint8_t train_set[4];
  60         uint8_t link_status[DP_LINK_STATUS_SIZE];
  61 };
  62
  63 /**
  64  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  65  * @intel_dp: DP struct
  66  *
  67  * If a CPU or PCH DP output is attached to an eDP panel, this function
  68  * will return true, and false otherwise.
  69  */
  70 static bool is_edp(struct intel_dp *intel_dp)
  71 {
  72         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  73 }
  74
  75 /**
  76  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  77  * @intel_dp: DP struct
  78  *
  79  * Returns true if the given DP struct corresponds to a PCH DP port attached
  80  * to an eDP panel, false otherwise.  Helpful for determining whether we
  81  * may need FDI resources for a given DP output or not.
  82  */
  83 static bool is_pch_edp(struct intel_dp *intel_dp)
  84 {
  85         return intel_dp->is_pch_edp;
  86 }
  87
  88 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  89 {
  90         return container_of(encoder, struct intel_dp, base.base);
  91 }
  92
  93 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  94 {
  95         return container_of(intel_attached_encoder(connector),
  96                             struct intel_dp, base);
  97 }
  98
  99 /**
 100  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 101  * @encoder: DRM encoder
 102  *
 103  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 104  * by intel_display.c.
 105  */
 106 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 107 {
 108         struct intel_dp *intel_dp;
 109
 110         if (!encoder)
 111                 return false;
 112
 113         intel_dp = enc_to_intel_dp(encoder);
 114
 115         return is_pch_edp(intel_dp);
 116 }
 117
 118 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 119 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 120 static void intel_dp_link_down(struct intel_dp *intel_dp);
 121
 122 void
 123 intel_edp_link_config (struct intel_encoder *intel_encoder,
 124                        int *lane_num, int *link_bw)
 125 {
 126         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 127
 128         *lane_num = intel_dp->lane_count;
 129         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 130                 *link_bw = 162000;
 131         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 132                 *link_bw = 270000;
 133 }
 134
 135 static int
 136 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 137 {
 138         int max_lane_count = 4;
 139
 140         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 141                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 142                 switch (max_lane_count) {
 143                 case 1: case 2: case 4:
 144                         break;
 145                 default:
 146                         max_lane_count = 4;
 147                 }
 148         }
 149         return max_lane_count;
 150 }
 151
 152 static int
 153 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 154 {
 155         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 156
 157         switch (max_link_bw) {
 158         case DP_LINK_BW_1_62:
 159         case DP_LINK_BW_2_7:
 160                 break;
 161         default:
 162                 max_link_bw = DP_LINK_BW_1_62;
 163                 break;
 164         }
 165         return max_link_bw;
 166 }
 167
 168 static int
 169 intel_dp_link_clock(uint8_t link_bw)
 170 {
 171         if (link_bw == DP_LINK_BW_2_7)
 172                 return 270000;
 173         else
 174                 return 162000;
 175 }
 176
 177 /* I think this is a fiction */
 178 static int
 179 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 180 {
 181         struct drm_i915_private *dev_priv = dev->dev_private;
 182
 183         if (is_edp(intel_dp))
 184                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
 185         else
 186                 return pixel_clock * 3;
 187 }
 188
 189 static int
 190 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 191 {
 192         return (max_link_clock * max_lanes * 8) / 10;
 193 }
 194
 195 static int
 196 intel_dp_mode_valid(struct drm_connector *connector,
 197                     struct drm_display_mode *mode)
 198 {
 199         struct intel_dp *intel_dp = intel_attached_dp(connector);
 200         struct drm_device *dev = connector->dev;
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 203         int max_lanes = intel_dp_max_lane_count(intel_dp);
 204
 205         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 206                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 207                         return MODE_PANEL;
 208
 209                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 210                         return MODE_PANEL;
 211         }
 212
 213         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 214            which are outside spec tolerances but somehow work by magic */
 215         if (!is_edp(intel_dp) &&
 216             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 217              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 218                 return MODE_CLOCK_HIGH;
 219
 220         if (mode->clock < 10000)
 221                 return MODE_CLOCK_LOW;
 222
 223         return MODE_OK;
 224 }
 225
 226 static uint32_t
 227 pack_aux(uint8_t *src, int src_bytes)
 228 {
 229         int     i;
 230         uint32_t v = 0;
 231
 232         if (src_bytes > 4)
 233                 src_bytes = 4;
 234         for (i = 0; i < src_bytes; i++)
 235                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 236         return v;
 237 }
 238
 239 static void
 240 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 241 {
 242         int i;
 243         if (dst_bytes > 4)
 244                 dst_bytes = 4;
 245         for (i = 0; i < dst_bytes; i++)
 246                 dst[i] = src >> ((3-i) * 8);
 247 }
 248
 249 /* hrawclock is 1/4 the FSB frequency */
 250 static int
 251 intel_hrawclk(struct drm_device *dev)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         uint32_t clkcfg;
 255
 256         clkcfg = I915_READ(CLKCFG);
 257         switch (clkcfg & CLKCFG_FSB_MASK) {
 258         case CLKCFG_FSB_400:
 259                 return 100;
 260         case CLKCFG_FSB_533:
 261                 return 133;
 262         case CLKCFG_FSB_667:
 263                 return 166;
 264         case CLKCFG_FSB_800:
 265                 return 200;
 266         case CLKCFG_FSB_1067:
 267                 return 266;
 268         case CLKCFG_FSB_1333:
 269                 return 333;
 270         /* these two are just a guess; one of them might be right */
 271         case CLKCFG_FSB_1600:
 272         case CLKCFG_FSB_1600_ALT:
 273                 return 400;
 274         default:
 275                 return 133;
 276         }
 277 }
 278
 279 static int
 280 intel_dp_aux_ch(struct intel_dp *intel_dp,
 281                 uint8_t *send, int send_bytes,
 282                 uint8_t *recv, int recv_size)
 283 {
 284         uint32_t output_reg = intel_dp->output_reg;
 285         struct drm_device *dev = intel_dp->base.base.dev;
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         uint32_t ch_ctl = output_reg + 0x10;
 288         uint32_t ch_data = ch_ctl + 4;
 289         int i;
 290         int recv_bytes;
 291         uint32_t status;
 292         uint32_t aux_clock_divider;
 293         int try, precharge;
 294
 295         /* The clock divider is based off the hrawclk,
 296          * and would like to run at 2MHz. So, take the
 297          * hrawclk value and divide by 2 and use that
 298          *
 299          * Note that PCH attached eDP panels should use a 125MHz input
 300          * clock divider.
 301          */
 302         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 303                 if (IS_GEN6(dev))
 304                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 305                 else
 306                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 307         } else if (HAS_PCH_SPLIT(dev))
 308                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 309         else
 310                 aux_clock_divider = intel_hrawclk(dev) / 2;
 311
 312         if (IS_GEN6(dev))
 313                 precharge = 3;
 314         else
 315                 precharge = 5;
 316
 317         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 318                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 319                           I915_READ(ch_ctl));
 320                 return -EBUSY;
 321         }
 322
 323         /* Must try at least 3 times according to DP spec */
 324         for (try = 0; try < 5; try++) {
 325                 /* Load the send data into the aux channel data registers */
 326                 for (i = 0; i < send_bytes; i += 4)
 327                         I915_WRITE(ch_data + i,
 328                                    pack_aux(send + i, send_bytes - i));
 329
 330                 /* Send the command and wait for it to complete */
 331                 I915_WRITE(ch_ctl,
 332                            DP_AUX_CH_CTL_SEND_BUSY |
 333                            DP_AUX_CH_CTL_TIME_OUT_400us |
 334                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 335                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 336                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 337                            DP_AUX_CH_CTL_DONE |
 338                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 339                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 340                 for (;;) {
 341                         status = I915_READ(ch_ctl);
 342                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 343                                 break;
 344                         udelay(100);
 345                 }
 346
 347                 /* Clear done status and any errors */
 348                 I915_WRITE(ch_ctl,
 349                            status |
 350                            DP_AUX_CH_CTL_DONE |
 351                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 352                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 353                 if (status & DP_AUX_CH_CTL_DONE)
 354                         break;
 355         }
 356
 357         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 358                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 359                 return -EBUSY;
 360         }
 361
 362         /* Check for timeout or receive error.
 363          * Timeouts occur when the sink is not connected
 364          */
 365         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 366                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 367                 return -EIO;
 368         }
 369
 370         /* Timeouts occur when the device isn't connected, so they're
 371          * "normal" -- don't fill the kernel log with these */
 372         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 373                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 374                 return -ETIMEDOUT;
 375         }
 376
 377         /* Unload any bytes sent back from the other side */
 378         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 379                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 380         if (recv_bytes > recv_size)
 381                 recv_bytes = recv_size;
 382
 383         for (i = 0; i < recv_bytes; i += 4)
 384                 unpack_aux(I915_READ(ch_data + i),
 385                            recv + i, recv_bytes - i);
 386
 387         return recv_bytes;
 388 }
 389
 390 /* Write data to the aux channel in native mode */
 391 static int
 392 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 393                           uint16_t address, uint8_t *send, int send_bytes)
 394 {
 395         int ret;
 396         uint8_t msg[20];
 397         int msg_bytes;
 398         uint8_t ack;
 399
 400         if (send_bytes > 16)
 401                 return -1;
 402         msg[0] = AUX_NATIVE_WRITE << 4;
 403         msg[1] = address >> 8;
 404         msg[2] = address & 0xff;
 405         msg[3] = send_bytes - 1;
 406         memcpy(&msg[4], send, send_bytes);
 407         msg_bytes = send_bytes + 4;
 408         for (;;) {
 409                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 410                 if (ret < 0)
 411                         return ret;
 412                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 413                         break;
 414                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 415                         udelay(100);
 416                 else
 417                         return -EIO;
 418         }
 419         return send_bytes;
 420 }
 421
 422 /* Write a single byte to the aux channel in native mode */
 423 static int
 424 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 425                             uint16_t address, uint8_t byte)
 426 {
 427         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 428 }
 429
 430 /* read bytes from a native aux channel */
 431 static int
 432 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 433                          uint16_t address, uint8_t *recv, int recv_bytes)
 434 {
 435         uint8_t msg[4];
 436         int msg_bytes;
 437         uint8_t reply[20];
 438         int reply_bytes;
 439         uint8_t ack;
 440         int ret;
 441
 442         msg[0] = AUX_NATIVE_READ << 4;
 443         msg[1] = address >> 8;
 444         msg[2] = address & 0xff;
 445         msg[3] = recv_bytes - 1;
 446
 447         msg_bytes = 4;
 448         reply_bytes = recv_bytes + 1;
 449
 450         for (;;) {
 451                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 452                                       reply, reply_bytes);
 453                 if (ret == 0)
 454                         return -EPROTO;
 455                 if (ret < 0)
 456                         return ret;
 457                 ack = reply[0];
 458                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 459                         memcpy(recv, reply + 1, ret - 1);
 460                         return ret - 1;
 461                 }
 462                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 463                         udelay(100);
 464                 else
 465                         return -EIO;
 466         }
 467 }
 468
 469 static int
 470 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 471                     uint8_t write_byte, uint8_t *read_byte)
 472 {
 473         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 474         struct intel_dp *intel_dp = container_of(adapter,
 475                                                 struct intel_dp,
 476                                                 adapter);
 477         uint16_t address = algo_data->address;
 478         uint8_t msg[5];
 479         uint8_t reply[2];
 480         unsigned retry;
 481         int msg_bytes;
 482         int reply_bytes;
 483         int ret;
 484
 485         /* Set up the command byte */
 486         if (mode & MODE_I2C_READ)
 487                 msg[0] = AUX_I2C_READ << 4;
 488         else
 489                 msg[0] = AUX_I2C_WRITE << 4;
 490
 491         if (!(mode & MODE_I2C_STOP))
 492                 msg[0] |= AUX_I2C_MOT << 4;
 493
 494         msg[1] = address >> 8;
 495         msg[2] = address;
 496
 497         switch (mode) {
 498         case MODE_I2C_WRITE:
 499                 msg[3] = 0;
 500                 msg[4] = write_byte;
 501                 msg_bytes = 5;
 502                 reply_bytes = 1;
 503                 break;
 504         case MODE_I2C_READ:
 505                 msg[3] = 0;
 506                 msg_bytes = 4;
 507                 reply_bytes = 2;
 508                 break;
 509         default:
 510                 msg_bytes = 3;
 511                 reply_bytes = 1;
 512                 break;
 513         }
 514
 515         for (retry = 0; retry < 5; retry++) {
 516                 ret = intel_dp_aux_ch(intel_dp,
 517                                       msg, msg_bytes,
 518                                       reply, reply_bytes);
 519                 if (ret < 0) {
 520                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 521                         return ret;
 522                 }
 523
 524                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 525                 case AUX_NATIVE_REPLY_ACK:
 526                         /* I2C-over-AUX Reply field is only valid
 527                          * when paired with AUX ACK.
 528                          */
 529                         break;
 530                 case AUX_NATIVE_REPLY_NACK:
 531                         DRM_DEBUG_KMS("aux_ch native nack\n");
 532                         return -EREMOTEIO;
 533                 case AUX_NATIVE_REPLY_DEFER:
 534                         udelay(100);
 535                         continue;
 536                 default:
 537                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 538                                   reply[0]);
 539                         return -EREMOTEIO;
 540                 }
 541
 542                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 543                 case AUX_I2C_REPLY_ACK:
 544                         if (mode == MODE_I2C_READ) {
 545                                 *read_byte = reply[1];
 546                         }
 547                         return reply_bytes - 1;
 548                 case AUX_I2C_REPLY_NACK:
 549                         DRM_DEBUG_KMS("aux_i2c nack\n");
 550                         return -EREMOTEIO;
 551                 case AUX_I2C_REPLY_DEFER:
 552                         DRM_DEBUG_KMS("aux_i2c defer\n");
 553                         udelay(100);
 554                         break;
 555                 default:
 556                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 557                         return -EREMOTEIO;
 558                 }
 559         }
 560
 561         DRM_ERROR("too many retries, giving up\n");
 562         return -EREMOTEIO;
 563 }
 564
 565 static int
 566 intel_dp_i2c_init(struct intel_dp *intel_dp,
 567                   struct intel_connector *intel_connector, const char *name)
 568 {
 569         DRM_DEBUG_KMS("i2c_init %s\n", name);
 570         intel_dp->algo.running = false;
 571         intel_dp->algo.address = 0;
 572         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 573
 574         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 575         intel_dp->adapter.owner = THIS_MODULE;
 576         intel_dp->adapter.class = I2C_CLASS_DDC;
 577         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 578         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 579         intel_dp->adapter.algo_data = &intel_dp->algo;
 580         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 581
 582         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 583 }
 584
 585 static bool
 586 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 587                     struct drm_display_mode *adjusted_mode)
 588 {
 589         struct drm_device *dev = encoder->dev;
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 592         int lane_count, clock;
 593         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 594         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 595         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 596
 597         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 598                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 599                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 600                                         mode, adjusted_mode);
 601                 /*
 602                  * the mode->clock is used to calculate the Data&Link M/N
 603                  * of the pipe. For the eDP the fixed clock should be used.
 604                  */
 605                 mode->clock = dev_priv->panel_fixed_mode->clock;
 606         }
 607
 608         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 609                 for (clock = 0; clock <= max_clock; clock++) {
 610                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 611
 612                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 613                                         <= link_avail) {
 614                                 intel_dp->link_bw = bws[clock];
 615                                 intel_dp->lane_count = lane_count;
 616                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 617                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 618                                                 "count %d clock %d\n",
 619                                        intel_dp->link_bw, intel_dp->lane_count,
 620                                        adjusted_mode->clock);
 621                                 return true;
 622                         }
 623                 }
 624         }
 625
 626         if (is_edp(intel_dp)) {
 627                 /* okay we failed just pick the highest */
 628                 intel_dp->lane_count = max_lane_count;
 629                 intel_dp->link_bw = bws[max_clock];
 630                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 631                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 632                               "count %d clock %d\n",
 633                               intel_dp->link_bw, intel_dp->lane_count,
 634                               adjusted_mode->clock);
 635
 636                 return true;
 637         }
 638
 639         return false;
 640 }
 641
 642 struct intel_dp_m_n {
 643         uint32_t        tu;
 644         uint32_t        gmch_m;
 645         uint32_t        gmch_n;
 646         uint32_t        link_m;
 647         uint32_t        link_n;
 648 };
 649
 650 static void
 651 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 652 {
 653         while (*num > 0xffffff || *den > 0xffffff) {
 654                 *num >>= 1;
 655                 *den >>= 1;
 656         }
 657 }
 658
 659 static void
 660 intel_dp_compute_m_n(int bpp,
 661                      int nlanes,
 662                      int pixel_clock,
 663                      int link_clock,
 664                      struct intel_dp_m_n *m_n)
 665 {
 666         m_n->tu = 64;
 667         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 668         m_n->gmch_n = link_clock * nlanes;
 669         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 670         m_n->link_m = pixel_clock;
 671         m_n->link_n = link_clock;
 672         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 673 }
 674
 675 void
 676 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 677                  struct drm_display_mode *adjusted_mode)
 678 {
 679         struct drm_device *dev = crtc->dev;
 680         struct drm_mode_config *mode_config = &dev->mode_config;
 681         struct drm_encoder *encoder;
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 684         int lane_count = 4, bpp = 24;
 685         struct intel_dp_m_n m_n;
 686         int pipe = intel_crtc->pipe;
 687
 688         /*
 689          * Find the lane count in the intel_encoder private
 690          */
 691         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 692                 struct intel_dp *intel_dp;
 693
 694                 if (encoder->crtc != crtc)
 695                         continue;
 696
 697                 intel_dp = enc_to_intel_dp(encoder);
 698                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 699                         lane_count = intel_dp->lane_count;
 700                         break;
 701                 } else if (is_edp(intel_dp)) {
 702                         lane_count = dev_priv->edp.lanes;
 703                         bpp = dev_priv->edp.bpp;
 704                         break;
 705                 }
 706         }
 707
 708         /*
 709          * Compute the GMCH and Link ratios. The '3' here is
 710          * the number of bytes_per_pixel post-LUT, which we always
 711          * set up for 8-bits of R/G/B, or 3 bytes total.
 712          */
 713         intel_dp_compute_m_n(bpp, lane_count,
 714                              mode->clock, adjusted_mode->clock, &m_n);
 715
 716         if (HAS_PCH_SPLIT(dev)) {
 717                 I915_WRITE(TRANSDATA_M1(pipe),
 718                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 719                            m_n.gmch_m);
 720                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 721                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 722                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 723         } else {
 724                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 725                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 726                            m_n.gmch_m);
 727                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 728                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 729                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 730         }
 731 }
 732
 733 static void
 734 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 735                   struct drm_display_mode *adjusted_mode)
 736 {
 737         struct drm_device *dev = encoder->dev;
 738         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 739         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 741
 742         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 743         intel_dp->DP |= intel_dp->color_range;
 744
 745         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 746                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 747         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 748                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 749
 750         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 751                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 752         else
 753                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 754
 755         switch (intel_dp->lane_count) {
 756         case 1:
 757                 intel_dp->DP |= DP_PORT_WIDTH_1;
 758                 break;
 759         case 2:
 760                 intel_dp->DP |= DP_PORT_WIDTH_2;
 761                 break;
 762         case 4:
 763                 intel_dp->DP |= DP_PORT_WIDTH_4;
 764                 break;
 765         }
 766         if (intel_dp->has_audio)
 767                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 768
 769         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 770         intel_dp->link_configuration[0] = intel_dp->link_bw;
 771         intel_dp->link_configuration[1] = intel_dp->lane_count;
 772
 773         /*
 774          * Check for DPCD version > 1.1 and enhanced framing support
 775          */
 776         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 777             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 778                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 779                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 780         }
 781
 782         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 783         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 784                 intel_dp->DP |= DP_PIPEB_SELECT;
 785
 786         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 787                 /* don't miss out required setting for eDP */
 788                 intel_dp->DP |= DP_PLL_ENABLE;
 789                 if (adjusted_mode->clock < 200000)
 790                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 791                 else
 792                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 793         }
 794 }
 795
 796 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 797 {
 798         struct drm_device *dev = intel_dp->base.base.dev;
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         u32 pp;
 801
 802         /*
 803          * If the panel wasn't on, make sure there's not a currently
 804          * active PP sequence before enabling AUX VDD.
 805          */
 806         if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
 807                 msleep(dev_priv->panel_t3);
 808
 809         pp = I915_READ(PCH_PP_CONTROL);
 810         pp |= EDP_FORCE_VDD;
 811         I915_WRITE(PCH_PP_CONTROL, pp);
 812         POSTING_READ(PCH_PP_CONTROL);
 813 }
 814
 815 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 816 {
 817         struct drm_device *dev = intel_dp->base.base.dev;
 818         struct drm_i915_private *dev_priv = dev->dev_private;
 819         u32 pp;
 820
 821         pp = I915_READ(PCH_PP_CONTROL);
 822         pp &= ~EDP_FORCE_VDD;
 823         I915_WRITE(PCH_PP_CONTROL, pp);
 824         POSTING_READ(PCH_PP_CONTROL);
 825
 826         /* Make sure sequencer is idle before allowing subsequent activity */
 827         msleep(dev_priv->panel_t12);
 828 }
 829
 830 /* Returns true if the panel was already on when called */
 831 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 832 {
 833         struct drm_device *dev = intel_dp->base.base.dev;
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 836
 837         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 838                 return true;
 839
 840         pp = I915_READ(PCH_PP_CONTROL);
 841
 842         /* ILK workaround: disable reset around power sequence */
 843         pp &= ~PANEL_POWER_RESET;
 844         I915_WRITE(PCH_PP_CONTROL, pp);
 845         POSTING_READ(PCH_PP_CONTROL);
 846
 847         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 848         I915_WRITE(PCH_PP_CONTROL, pp);
 849         POSTING_READ(PCH_PP_CONTROL);
 850
 851         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 852                      5000))
 853                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 854                           I915_READ(PCH_PP_STATUS));
 855
 856         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 857         I915_WRITE(PCH_PP_CONTROL, pp);
 858         POSTING_READ(PCH_PP_CONTROL);
 859
 860         return false;
 861 }
 862
 863 static void ironlake_edp_panel_off (struct drm_device *dev)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 867                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 868
 869         pp = I915_READ(PCH_PP_CONTROL);
 870
 871         /* ILK workaround: disable reset around power sequence */
 872         pp &= ~PANEL_POWER_RESET;
 873         I915_WRITE(PCH_PP_CONTROL, pp);
 874         POSTING_READ(PCH_PP_CONTROL);
 875
 876         pp &= ~POWER_TARGET_ON;
 877         I915_WRITE(PCH_PP_CONTROL, pp);
 878         POSTING_READ(PCH_PP_CONTROL);
 879
 880         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 881                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 882                           I915_READ(PCH_PP_STATUS));
 883
 884         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 885         I915_WRITE(PCH_PP_CONTROL, pp);
 886         POSTING_READ(PCH_PP_CONTROL);
 887 }
 888
 889 static void ironlake_edp_backlight_on (struct drm_device *dev)
 890 {
 891         struct drm_i915_private *dev_priv = dev->dev_private;
 892         u32 pp;
 893
 894         DRM_DEBUG_KMS("\n");
 895         /*
 896          * If we enable the backlight right away following a panel power
 897          * on, we may see slight flicker as the panel syncs with the eDP
 898          * link.  So delay a bit to make sure the image is solid before
 899          * allowing it to appear.
 900          */
 901         msleep(300);
 902         pp = I915_READ(PCH_PP_CONTROL);
 903         pp |= EDP_BLC_ENABLE;
 904         I915_WRITE(PCH_PP_CONTROL, pp);
 905 }
 906
 907 static void ironlake_edp_backlight_off (struct drm_device *dev)
 908 {
 909         struct drm_i915_private *dev_priv = dev->dev_private;
 910         u32 pp;
 911
 912         DRM_DEBUG_KMS("\n");
 913         pp = I915_READ(PCH_PP_CONTROL);
 914         pp &= ~EDP_BLC_ENABLE;
 915         I915_WRITE(PCH_PP_CONTROL, pp);
 916 }
 917
 918 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 919 {
 920         struct drm_device *dev = encoder->dev;
 921         struct drm_i915_private *dev_priv = dev->dev_private;
 922         u32 dpa_ctl;
 923
 924         DRM_DEBUG_KMS("\n");
 925         dpa_ctl = I915_READ(DP_A);
 926         dpa_ctl |= DP_PLL_ENABLE;
 927         I915_WRITE(DP_A, dpa_ctl);
 928         POSTING_READ(DP_A);
 929         udelay(200);
 930 }
 931
 932 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 933 {
 934         struct drm_device *dev = encoder->dev;
 935         struct drm_i915_private *dev_priv = dev->dev_private;
 936         u32 dpa_ctl;
 937
 938         dpa_ctl = I915_READ(DP_A);
 939         dpa_ctl &= ~DP_PLL_ENABLE;
 940         I915_WRITE(DP_A, dpa_ctl);
 941         POSTING_READ(DP_A);
 942         udelay(200);
 943 }
 944
 945 static void intel_dp_prepare(struct drm_encoder *encoder)
 946 {
 947         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 948         struct drm_device *dev = encoder->dev;
 949
 950         if (is_edp(intel_dp)) {
 951                 ironlake_edp_backlight_off(dev);
 952                 ironlake_edp_panel_off(dev);
 953                 if (!is_pch_edp(intel_dp))
 954                         ironlake_edp_pll_on(encoder);
 955                 else
 956                         ironlake_edp_pll_off(encoder);
 957         }
 958         intel_dp_link_down(intel_dp);
 959 }
 960
 961 static void intel_dp_commit(struct drm_encoder *encoder)
 962 {
 963         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 964         struct drm_device *dev = encoder->dev;
 965
 966         if (is_edp(intel_dp))
 967                 ironlake_edp_panel_vdd_on(intel_dp);
 968
 969         intel_dp_start_link_train(intel_dp);
 970
 971         if (is_edp(intel_dp)) {
 972                 ironlake_edp_panel_on(intel_dp);
 973                 ironlake_edp_panel_vdd_off(intel_dp);
 974         }
 975
 976         intel_dp_complete_link_train(intel_dp);
 977
 978         if (is_edp(intel_dp))
 979                 ironlake_edp_backlight_on(dev);
 980 }
 981
 982 static void
 983 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 984 {
 985         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 986         struct drm_device *dev = encoder->dev;
 987         struct drm_i915_private *dev_priv = dev->dev_private;
 988         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 989
 990         if (mode != DRM_MODE_DPMS_ON) {
 991                 if (is_edp(intel_dp))
 992                         ironlake_edp_backlight_off(dev);
 993                 intel_dp_link_down(intel_dp);
 994                 if (is_edp(intel_dp))
 995                         ironlake_edp_panel_off(dev);
 996                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
 997                         ironlake_edp_pll_off(encoder);
 998         } else {
 999                 if (is_edp(intel_dp))
1000                         ironlake_edp_panel_vdd_on(intel_dp);
1001                 if (!(dp_reg & DP_PORT_EN)) {
1002                         intel_dp_start_link_train(intel_dp);
1003                         if (is_edp(intel_dp)) {
1004                                 ironlake_edp_panel_on(intel_dp);
1005                                 ironlake_edp_panel_vdd_off(intel_dp);
1006                         }
1007                         intel_dp_complete_link_train(intel_dp);
1008                 }
1009                 if (is_edp(intel_dp))
1010                         ironlake_edp_backlight_on(dev);
1011         }
1012 }
1013
1014 /*
1015  * Fetch AUX CH registers 0x202 - 0x207 which contain
1016  * link status information
1017  */
1018 static bool
1019 intel_dp_get_link_status(struct intel_dp *intel_dp)
1020 {
1021         int ret, i;
1022
1023         /* Must try AUX reads for this at least 3 times */
1024         for (i = 0; i < 3; i++) {
1025                 ret = intel_dp_aux_native_read(intel_dp,
1026                                                DP_LANE0_1_STATUS,
1027                                                intel_dp->link_status,
1028                                                DP_LINK_STATUS_SIZE);
1029                 if (ret == DP_LINK_STATUS_SIZE)
1030                         return true;
1031                 msleep(1);
1032         }
1033
1034         return false;
1035 }
1036
1037 static uint8_t
1038 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1039                      int r)
1040 {
1041         return link_status[r - DP_LANE0_1_STATUS];
1042 }
1043
1044 static uint8_t
1045 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1046                                  int lane)
1047 {
1048         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1049         int         s = ((lane & 1) ?
1050                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1051                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1052         uint8_t l = intel_dp_link_status(link_status, i);
1053
1054         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1055 }
1056
1057 static uint8_t
1058 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1059                                       int lane)
1060 {
1061         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1062         int         s = ((lane & 1) ?
1063                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1064                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1065         uint8_t l = intel_dp_link_status(link_status, i);
1066
1067         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1068 }
1069
1070
1071 #if 0
1072 static char     *voltage_names[] = {
1073         "0.4V", "0.6V", "0.8V", "1.2V"
1074 };
1075 static char     *pre_emph_names[] = {
1076         "0dB", "3.5dB", "6dB", "9.5dB"
1077 };
1078 static char     *link_train_names[] = {
1079         "pattern 1", "pattern 2", "idle", "off"
1080 };
1081 #endif
1082
1083 /*
1084  * These are source-specific values; current Intel hardware supports
1085  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1086  */
1087 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1088
1089 static uint8_t
1090 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1091 {
1092         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1093         case DP_TRAIN_VOLTAGE_SWING_400:
1094                 return DP_TRAIN_PRE_EMPHASIS_6;
1095         case DP_TRAIN_VOLTAGE_SWING_600:
1096                 return DP_TRAIN_PRE_EMPHASIS_6;
1097         case DP_TRAIN_VOLTAGE_SWING_800:
1098                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1099         case DP_TRAIN_VOLTAGE_SWING_1200:
1100         default:
1101                 return DP_TRAIN_PRE_EMPHASIS_0;
1102         }
1103 }
1104
1105 static void
1106 intel_get_adjust_train(struct intel_dp *intel_dp)
1107 {
1108         uint8_t v = 0;
1109         uint8_t p = 0;
1110         int lane;
1111
1112         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1113                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1114                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1115
1116                 if (this_v > v)
1117                         v = this_v;
1118                 if (this_p > p)
1119                         p = this_p;
1120         }
1121
1122         if (v >= I830_DP_VOLTAGE_MAX)
1123                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1124
1125         if (p >= intel_dp_pre_emphasis_max(v))
1126                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1127
1128         for (lane = 0; lane < 4; lane++)
1129                 intel_dp->train_set[lane] = v | p;
1130 }
1131
1132 static uint32_t
1133 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1134 {
1135         uint32_t        signal_levels = 0;
1136
1137         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1138         case DP_TRAIN_VOLTAGE_SWING_400:
1139         default:
1140                 signal_levels |= DP_VOLTAGE_0_4;
1141                 break;
1142         case DP_TRAIN_VOLTAGE_SWING_600:
1143                 signal_levels |= DP_VOLTAGE_0_6;
1144                 break;
1145         case DP_TRAIN_VOLTAGE_SWING_800:
1146                 signal_levels |= DP_VOLTAGE_0_8;
1147                 break;
1148         case DP_TRAIN_VOLTAGE_SWING_1200:
1149                 signal_levels |= DP_VOLTAGE_1_2;
1150                 break;
1151         }
1152         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1153         case DP_TRAIN_PRE_EMPHASIS_0:
1154         default:
1155                 signal_levels |= DP_PRE_EMPHASIS_0;
1156                 break;
1157         case DP_TRAIN_PRE_EMPHASIS_3_5:
1158                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1159                 break;
1160         case DP_TRAIN_PRE_EMPHASIS_6:
1161                 signal_levels |= DP_PRE_EMPHASIS_6;
1162                 break;
1163         case DP_TRAIN_PRE_EMPHASIS_9_5:
1164                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1165                 break;
1166         }
1167         return signal_levels;
1168 }
1169
1170 /* Gen6's DP voltage swing and pre-emphasis control */
1171 static uint32_t
1172 intel_gen6_edp_signal_levels(uint8_t train_set)
1173 {
1174         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1175                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1176         switch (signal_levels) {
1177         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1178         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1179                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1180         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1181                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1182         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1183         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1184                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1185         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1186         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1187                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1188         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1189         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1190                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1191         default:
1192                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1193                               "0x%x\n", signal_levels);
1194                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1195         }
1196 }
1197
1198 static uint8_t
1199 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1200                       int lane)
1201 {
1202         int i = DP_LANE0_1_STATUS + (lane >> 1);
1203         int s = (lane & 1) * 4;
1204         uint8_t l = intel_dp_link_status(link_status, i);
1205
1206         return (l >> s) & 0xf;
1207 }
1208
1209 /* Check for clock recovery is done on all channels */
1210 static bool
1211 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1212 {
1213         int lane;
1214         uint8_t lane_status;
1215
1216         for (lane = 0; lane < lane_count; lane++) {
1217                 lane_status = intel_get_lane_status(link_status, lane);
1218                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1219                         return false;
1220         }
1221         return true;
1222 }
1223
1224 /* Check to see if channel eq is done on all channels */
1225 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1226                          DP_LANE_CHANNEL_EQ_DONE|\
1227                          DP_LANE_SYMBOL_LOCKED)
1228 static bool
1229 intel_channel_eq_ok(struct intel_dp *intel_dp)
1230 {
1231         uint8_t lane_align;
1232         uint8_t lane_status;
1233         int lane;
1234
1235         lane_align = intel_dp_link_status(intel_dp->link_status,
1236                                           DP_LANE_ALIGN_STATUS_UPDATED);
1237         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1238                 return false;
1239         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1240                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1241                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1242                         return false;
1243         }
1244         return true;
1245 }
1246
1247 static bool
1248 intel_dp_set_link_train(struct intel_dp *intel_dp,
1249                         uint32_t dp_reg_value,
1250                         uint8_t dp_train_pat)
1251 {
1252         struct drm_device *dev = intel_dp->base.base.dev;
1253         struct drm_i915_private *dev_priv = dev->dev_private;
1254         int ret;
1255
1256         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1257         POSTING_READ(intel_dp->output_reg);
1258
1259         intel_dp_aux_native_write_1(intel_dp,
1260                                     DP_TRAINING_PATTERN_SET,
1261                                     dp_train_pat);
1262
1263         ret = intel_dp_aux_native_write(intel_dp,
1264                                         DP_TRAINING_LANE0_SET,
1265                                         intel_dp->train_set, 4);
1266         if (ret != 4)
1267                 return false;
1268
1269         return true;
1270 }
1271
1272 /* Enable corresponding port and start training pattern 1 */
1273 static void
1274 intel_dp_start_link_train(struct intel_dp *intel_dp)
1275 {
1276         struct drm_device *dev = intel_dp->base.base.dev;
1277         struct drm_i915_private *dev_priv = dev->dev_private;
1278         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1279         int i;
1280         uint8_t voltage;
1281         bool clock_recovery = false;
1282         int tries;
1283         u32 reg;
1284         uint32_t DP = intel_dp->DP;
1285
1286         /* Enable output, wait for it to become active */
1287         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1288         POSTING_READ(intel_dp->output_reg);
1289         intel_wait_for_vblank(dev, intel_crtc->pipe);
1290
1291         /* Write the link configuration data */
1292         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1293                                   intel_dp->link_configuration,
1294                                   DP_LINK_CONFIGURATION_SIZE);
1295
1296         DP |= DP_PORT_EN;
1297         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1298                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1299         else
1300                 DP &= ~DP_LINK_TRAIN_MASK;
1301         memset(intel_dp->train_set, 0, 4);
1302         voltage = 0xff;
1303         tries = 0;
1304         clock_recovery = false;
1305         for (;;) {
1306                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1307                 uint32_t    signal_levels;
1308                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1309                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1310                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1311                 } else {
1312                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1313                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1314                 }
1315
1316                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1317                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1318                 else
1319                         reg = DP | DP_LINK_TRAIN_PAT_1;
1320
1321                 if (!intel_dp_set_link_train(intel_dp, reg,
1322                                              DP_TRAINING_PATTERN_1))
1323                         break;
1324                 /* Set training pattern 1 */
1325
1326                 udelay(100);
1327                 if (!intel_dp_get_link_status(intel_dp))
1328                         break;
1329
1330                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1331                         clock_recovery = true;
1332                         break;
1333                 }
1334
1335                 /* Check to see if we've tried the max voltage */
1336                 for (i = 0; i < intel_dp->lane_count; i++)
1337                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1338                                 break;
1339                 if (i == intel_dp->lane_count)
1340                         break;
1341
1342                 /* Check to see if we've tried the same voltage 5 times */
1343                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1344                         ++tries;
1345                         if (tries == 5)
1346                                 break;
1347                 } else
1348                         tries = 0;
1349                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1350
1351                 /* Compute new intel_dp->train_set as requested by target */
1352                 intel_get_adjust_train(intel_dp);
1353         }
1354
1355         intel_dp->DP = DP;
1356 }
1357
1358 static void
1359 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1360 {
1361         struct drm_device *dev = intel_dp->base.base.dev;
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         bool channel_eq = false;
1364         int tries, cr_tries;
1365         u32 reg;
1366         uint32_t DP = intel_dp->DP;
1367
1368         /* channel equalization */
1369         tries = 0;
1370         cr_tries = 0;
1371         channel_eq = false;
1372         for (;;) {
1373                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1374                 uint32_t    signal_levels;
1375
1376                 if (cr_tries > 5) {
1377                         DRM_ERROR("failed to train DP, aborting\n");
1378                         intel_dp_link_down(intel_dp);
1379                         break;
1380                 }
1381
1382                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1383                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1384                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1385                 } else {
1386                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1387                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1388                 }
1389
1390                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1391                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1392                 else
1393                         reg = DP | DP_LINK_TRAIN_PAT_2;
1394
1395                 /* channel eq pattern */
1396                 if (!intel_dp_set_link_train(intel_dp, reg,
1397                                              DP_TRAINING_PATTERN_2))
1398                         break;
1399
1400                 udelay(400);
1401                 if (!intel_dp_get_link_status(intel_dp))
1402                         break;
1403
1404                 /* Make sure clock is still ok */
1405                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1406                         intel_dp_start_link_train(intel_dp);
1407                         cr_tries++;
1408                         continue;
1409                 }
1410
1411                 if (intel_channel_eq_ok(intel_dp)) {
1412                         channel_eq = true;
1413                         break;
1414                 }
1415
1416                 /* Try 5 times, then try clock recovery if that fails */
1417                 if (tries > 5) {
1418                         intel_dp_link_down(intel_dp);
1419                         intel_dp_start_link_train(intel_dp);
1420                         tries = 0;
1421                         cr_tries++;
1422                         continue;
1423                 }
1424
1425                 /* Compute new intel_dp->train_set as requested by target */
1426                 intel_get_adjust_train(intel_dp);
1427                 ++tries;
1428         }
1429
1430         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1431                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1432         else
1433                 reg = DP | DP_LINK_TRAIN_OFF;
1434
1435         I915_WRITE(intel_dp->output_reg, reg);
1436         POSTING_READ(intel_dp->output_reg);
1437         intel_dp_aux_native_write_1(intel_dp,
1438                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1439 }
1440
1441 static void
1442 intel_dp_link_down(struct intel_dp *intel_dp)
1443 {
1444         struct drm_device *dev = intel_dp->base.base.dev;
1445         struct drm_i915_private *dev_priv = dev->dev_private;
1446         uint32_t DP = intel_dp->DP;
1447
1448         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1449                 return;
1450
1451         DRM_DEBUG_KMS("\n");
1452
1453         if (is_edp(intel_dp)) {
1454                 DP &= ~DP_PLL_ENABLE;
1455                 I915_WRITE(intel_dp->output_reg, DP);
1456                 POSTING_READ(intel_dp->output_reg);
1457                 udelay(100);
1458         }
1459
1460         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1461                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1462                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1463         } else {
1464                 DP &= ~DP_LINK_TRAIN_MASK;
1465                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1466         }
1467         POSTING_READ(intel_dp->output_reg);
1468
1469         msleep(17);
1470
1471         if (is_edp(intel_dp))
1472                 DP |= DP_LINK_TRAIN_OFF;
1473
1474         if (!HAS_PCH_CPT(dev) &&
1475             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1476                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1477
1478                 /* Hardware workaround: leaving our transcoder select
1479                  * set to transcoder B while it's off will prevent the
1480                  * corresponding HDMI output on transcoder A.
1481                  *
1482                  * Combine this with another hardware workaround:
1483                  * transcoder select bit can only be cleared while the
1484                  * port is enabled.
1485                  */
1486                 DP &= ~DP_PIPEB_SELECT;
1487                 I915_WRITE(intel_dp->output_reg, DP);
1488
1489                 /* Changes to enable or select take place the vblank
1490                  * after being written.
1491                  */
1492                 if (crtc == NULL) {
1493                         /* We can arrive here never having been attached
1494                          * to a CRTC, for instance, due to inheriting
1495                          * random state from the BIOS.
1496                          *
1497                          * If the pipe is not running, play safe and
1498                          * wait for the clocks to stabilise before
1499                          * continuing.
1500                          */
1501                         POSTING_READ(intel_dp->output_reg);
1502                         msleep(50);
1503                 } else
1504                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1505         }
1506
1507         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1508         POSTING_READ(intel_dp->output_reg);
1509 }
1510
1511 /*
1512  * According to DP spec
1513  * 5.1.2:
1514  *  1. Read DPCD
1515  *  2. Configure link according to Receiver Capabilities
1516  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1517  *  4. Check link status on receipt of hot-plug interrupt
1518  */
1519
1520 static void
1521 intel_dp_check_link_status(struct intel_dp *intel_dp)
1522 {
1523         int ret;
1524
1525         if (!intel_dp->base.base.crtc)
1526                 return;
1527
1528         if (!intel_dp_get_link_status(intel_dp)) {
1529                 intel_dp_link_down(intel_dp);
1530                 return;
1531         }
1532
1533         /* Try to read receiver status if the link appears to be up */
1534         ret = intel_dp_aux_native_read(intel_dp,
1535                                        0x000, intel_dp->dpcd,
1536                                        sizeof (intel_dp->dpcd));
1537         if (ret != sizeof(intel_dp->dpcd)) {
1538                 intel_dp_link_down(intel_dp);
1539                 return;
1540         }
1541
1542         if (!intel_channel_eq_ok(intel_dp)) {
1543                 intel_dp_start_link_train(intel_dp);
1544                 intel_dp_complete_link_train(intel_dp);
1545         }
1546 }
1547
1548 static enum drm_connector_status
1549 ironlake_dp_detect(struct intel_dp *intel_dp)
1550 {
1551         enum drm_connector_status status;
1552         int ret, i;
1553
1554         /* Can't disconnect eDP, but you can close the lid... */
1555         if (is_edp(intel_dp)) {
1556                 status = intel_panel_detect(intel_dp->base.base.dev);
1557                 if (status == connector_status_unknown)
1558                         status = connector_status_connected;
1559                 return status;
1560         }
1561
1562         status = connector_status_disconnected;
1563         for (i = 0; i < 3; i++) {
1564                 ret = intel_dp_aux_native_read(intel_dp,
1565                                                0x000, intel_dp->dpcd,
1566                                                sizeof (intel_dp->dpcd));
1567                 if (ret == sizeof(intel_dp->dpcd) &&
1568                     intel_dp->dpcd[DP_DPCD_REV] != 0) {
1569                         status = connector_status_connected;
1570                         break;
1571                 }
1572                 msleep(1);
1573         }
1574         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1575                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1576         return status;
1577 }
1578
1579 static enum drm_connector_status
1580 g4x_dp_detect(struct intel_dp *intel_dp)
1581 {
1582         struct drm_device *dev = intel_dp->base.base.dev;
1583         struct drm_i915_private *dev_priv = dev->dev_private;
1584         enum drm_connector_status status;
1585         uint32_t temp, bit;
1586
1587         switch (intel_dp->output_reg) {
1588         case DP_B:
1589                 bit = DPB_HOTPLUG_INT_STATUS;
1590                 break;
1591         case DP_C:
1592                 bit = DPC_HOTPLUG_INT_STATUS;
1593                 break;
1594         case DP_D:
1595                 bit = DPD_HOTPLUG_INT_STATUS;
1596                 break;
1597         default:
1598                 return connector_status_unknown;
1599         }
1600
1601         temp = I915_READ(PORT_HOTPLUG_STAT);
1602
1603         if ((temp & bit) == 0)
1604                 return connector_status_disconnected;
1605
1606         status = connector_status_disconnected;
1607         if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1608                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1609         {
1610                 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1611                         status = connector_status_connected;
1612         }
1613
1614         return status;
1615 }
1616
1617 /**
1618  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1619  *
1620  * \return true if DP port is connected.
1621  * \return false if DP port is disconnected.
1622  */
1623 static enum drm_connector_status
1624 intel_dp_detect(struct drm_connector *connector, bool force)
1625 {
1626         struct intel_dp *intel_dp = intel_attached_dp(connector);
1627         struct drm_device *dev = intel_dp->base.base.dev;
1628         enum drm_connector_status status;
1629         struct edid *edid = NULL;
1630
1631         intel_dp->has_audio = false;
1632
1633         if (HAS_PCH_SPLIT(dev))
1634                 status = ironlake_dp_detect(intel_dp);
1635         else
1636                 status = g4x_dp_detect(intel_dp);
1637         if (status != connector_status_connected)
1638                 return status;
1639
1640         if (intel_dp->force_audio) {
1641                 intel_dp->has_audio = intel_dp->force_audio > 0;
1642         } else {
1643                 edid = drm_get_edid(connector, &intel_dp->adapter);
1644                 if (edid) {
1645                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1646                         connector->display_info.raw_edid = NULL;
1647                         kfree(edid);
1648                 }
1649         }
1650
1651         return connector_status_connected;
1652 }
1653
1654 static int intel_dp_get_modes(struct drm_connector *connector)
1655 {
1656         struct intel_dp *intel_dp = intel_attached_dp(connector);
1657         struct drm_device *dev = intel_dp->base.base.dev;
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659         int ret;
1660
1661         /* We should parse the EDID data and find out if it has an audio sink
1662          */
1663
1664         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1665         if (ret) {
1666                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1667                         struct drm_display_mode *newmode;
1668                         list_for_each_entry(newmode, &connector->probed_modes,
1669                                             head) {
1670                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1671                                         dev_priv->panel_fixed_mode =
1672                                                 drm_mode_duplicate(dev, newmode);
1673                                         break;
1674                                 }
1675                         }
1676                 }
1677
1678                 return ret;
1679         }
1680
1681         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1682         if (is_edp(intel_dp)) {
1683                 if (dev_priv->panel_fixed_mode != NULL) {
1684                         struct drm_display_mode *mode;
1685                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1686                         drm_mode_probed_add(connector, mode);
1687                         return 1;
1688                 }
1689         }
1690         return 0;
1691 }
1692
1693 static bool
1694 intel_dp_detect_audio(struct drm_connector *connector)
1695 {
1696         struct intel_dp *intel_dp = intel_attached_dp(connector);
1697         struct edid *edid;
1698         bool has_audio = false;
1699
1700         edid = drm_get_edid(connector, &intel_dp->adapter);
1701         if (edid) {
1702                 has_audio = drm_detect_monitor_audio(edid);
1703
1704                 connector->display_info.raw_edid = NULL;
1705                 kfree(edid);
1706         }
1707
1708         return has_audio;
1709 }
1710
1711 static int
1712 intel_dp_set_property(struct drm_connector *connector,
1713                       struct drm_property *property,
1714                       uint64_t val)
1715 {
1716         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1717         struct intel_dp *intel_dp = intel_attached_dp(connector);
1718         int ret;
1719
1720         ret = drm_connector_property_set_value(connector, property, val);
1721         if (ret)
1722                 return ret;
1723
1724         if (property == dev_priv->force_audio_property) {
1725                 int i = val;
1726                 bool has_audio;
1727
1728                 if (i == intel_dp->force_audio)
1729                         return 0;
1730
1731                 intel_dp->force_audio = i;
1732
1733                 if (i == 0)
1734                         has_audio = intel_dp_detect_audio(connector);
1735                 else
1736                         has_audio = i > 0;
1737
1738                 if (has_audio == intel_dp->has_audio)
1739                         return 0;
1740
1741                 intel_dp->has_audio = has_audio;
1742                 goto done;
1743         }
1744
1745         if (property == dev_priv->broadcast_rgb_property) {
1746                 if (val == !!intel_dp->color_range)
1747                         return 0;
1748
1749                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1750                 goto done;
1751         }
1752
1753         return -EINVAL;
1754
1755 done:
1756         if (intel_dp->base.base.crtc) {
1757                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1758                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1759                                          crtc->x, crtc->y,
1760                                          crtc->fb);
1761         }
1762
1763         return 0;
1764 }
1765
1766 static void
1767 intel_dp_destroy (struct drm_connector *connector)
1768 {
1769         drm_sysfs_connector_remove(connector);
1770         drm_connector_cleanup(connector);
1771         kfree(connector);
1772 }
1773
1774 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1775 {
1776         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1777
1778         i2c_del_adapter(&intel_dp->adapter);
1779         drm_encoder_cleanup(encoder);
1780         kfree(intel_dp);
1781 }
1782
1783 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1784         .dpms = intel_dp_dpms,
1785         .mode_fixup = intel_dp_mode_fixup,
1786         .prepare = intel_dp_prepare,
1787         .mode_set = intel_dp_mode_set,
1788         .commit = intel_dp_commit,
1789 };
1790
1791 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1792         .dpms = drm_helper_connector_dpms,
1793         .detect = intel_dp_detect,
1794         .fill_modes = drm_helper_probe_single_connector_modes,
1795         .set_property = intel_dp_set_property,
1796         .destroy = intel_dp_destroy,
1797 };
1798
1799 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1800         .get_modes = intel_dp_get_modes,
1801         .mode_valid = intel_dp_mode_valid,
1802         .best_encoder = intel_best_encoder,
1803 };
1804
1805 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1806         .destroy = intel_dp_encoder_destroy,
1807 };
1808
1809 static void
1810 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1811 {
1812         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1813
1814         intel_dp_check_link_status(intel_dp);
1815 }
1816
1817 /* Return which DP Port should be selected for Transcoder DP control */
1818 int
1819 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1820 {
1821         struct drm_device *dev = crtc->dev;
1822         struct drm_mode_config *mode_config = &dev->mode_config;
1823         struct drm_encoder *encoder;
1824
1825         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1826                 struct intel_dp *intel_dp;
1827
1828                 if (encoder->crtc != crtc)
1829                         continue;
1830
1831                 intel_dp = enc_to_intel_dp(encoder);
1832                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1833                         return intel_dp->output_reg;
1834         }
1835
1836         return -1;
1837 }
1838
1839 /* check the VBT to see whether the eDP is on DP-D port */
1840 bool intel_dpd_is_edp(struct drm_device *dev)
1841 {
1842         struct drm_i915_private *dev_priv = dev->dev_private;
1843         struct child_device_config *p_child;
1844         int i;
1845
1846         if (!dev_priv->child_dev_num)
1847                 return false;
1848
1849         for (i = 0; i < dev_priv->child_dev_num; i++) {
1850                 p_child = dev_priv->child_dev + i;
1851
1852                 if (p_child->dvo_port == PORT_IDPD &&
1853                     p_child->device_type == DEVICE_TYPE_eDP)
1854                         return true;
1855         }
1856         return false;
1857 }
1858
1859 static void
1860 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1861 {
1862         intel_attach_force_audio_property(connector);
1863         intel_attach_broadcast_rgb_property(connector);
1864 }
1865
1866 void
1867 intel_dp_init(struct drm_device *dev, int output_reg)
1868 {
1869         struct drm_i915_private *dev_priv = dev->dev_private;
1870         struct drm_connector *connector;
1871         struct intel_dp *intel_dp;
1872         struct intel_encoder *intel_encoder;
1873         struct intel_connector *intel_connector;
1874         const char *name = NULL;
1875         int type;
1876
1877         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1878         if (!intel_dp)
1879                 return;
1880
1881         intel_dp->output_reg = output_reg;
1882
1883         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1884         if (!intel_connector) {
1885                 kfree(intel_dp);
1886                 return;
1887         }
1888         intel_encoder = &intel_dp->base;
1889
1890         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1891                 if (intel_dpd_is_edp(dev))
1892                         intel_dp->is_pch_edp = true;
1893
1894         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1895                 type = DRM_MODE_CONNECTOR_eDP;
1896                 intel_encoder->type = INTEL_OUTPUT_EDP;
1897         } else {
1898                 type = DRM_MODE_CONNECTOR_DisplayPort;
1899                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1900         }
1901
1902         connector = &intel_connector->base;
1903         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1904         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1905
1906         connector->polled = DRM_CONNECTOR_POLL_HPD;
1907
1908         if (output_reg == DP_B || output_reg == PCH_DP_B)
1909                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1910         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1911                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1912         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1913                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1914
1915         if (is_edp(intel_dp))
1916                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1917
1918         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1919         connector->interlace_allowed = true;
1920         connector->doublescan_allowed = 0;
1921
1922         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1923                          DRM_MODE_ENCODER_TMDS);
1924         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1925
1926         intel_connector_attach_encoder(intel_connector, intel_encoder);
1927         drm_sysfs_connector_add(connector);
1928
1929         /* Set up the DDC bus. */
1930         switch (output_reg) {
1931                 case DP_A:
1932                         name = "DPDDC-A";
1933                         break;
1934                 case DP_B:
1935                 case PCH_DP_B:
1936                         dev_priv->hotplug_supported_mask |=
1937                                 HDMIB_HOTPLUG_INT_STATUS;
1938                         name = "DPDDC-B";
1939                         break;
1940                 case DP_C:
1941                 case PCH_DP_C:
1942                         dev_priv->hotplug_supported_mask |=
1943                                 HDMIC_HOTPLUG_INT_STATUS;
1944                         name = "DPDDC-C";
1945                         break;
1946                 case DP_D:
1947                 case PCH_DP_D:
1948                         dev_priv->hotplug_supported_mask |=
1949                                 HDMID_HOTPLUG_INT_STATUS;
1950                         name = "DPDDC-D";
1951                         break;
1952         }
1953
1954         intel_dp_i2c_init(intel_dp, intel_connector, name);
1955
1956         /* Cache some DPCD data in the eDP case */
1957         if (is_edp(intel_dp)) {
1958                 int ret;
1959                 u32 pp_on, pp_div;
1960
1961                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
1962                 pp_div = I915_READ(PCH_PP_DIVISOR);
1963
1964                 /* Get T3 & T12 values (note: VESA not bspec terminology) */
1965                 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
1966                 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
1967                 dev_priv->panel_t12 = pp_div & 0xf;
1968                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
1969
1970                 ironlake_edp_panel_vdd_on(intel_dp);
1971                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1972                                                intel_dp->dpcd,
1973                                                sizeof(intel_dp->dpcd));
1974                 ironlake_edp_panel_vdd_off(intel_dp);
1975                 if (ret == sizeof(intel_dp->dpcd)) {
1976                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
1977                                 dev_priv->no_aux_handshake =
1978                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
1979                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1980                 } else {
1981                         /* if this fails, presume the device is a ghost */
1982                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
1983                         intel_dp_encoder_destroy(&intel_dp->base.base);
1984                         intel_dp_destroy(&intel_connector->base);
1985                         return;
1986                 }
1987         }
1988
1989         intel_encoder->hot_plug = intel_dp_hot_plug;
1990
1991         if (is_edp(intel_dp)) {
1992                 /* initialize panel mode from VBT if available for eDP */
1993                 if (dev_priv->lfp_lvds_vbt_mode) {
1994                         dev_priv->panel_fixed_mode =
1995                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1996                         if (dev_priv->panel_fixed_mode) {
1997                                 dev_priv->panel_fixed_mode->type |=
1998                                         DRM_MODE_TYPE_PREFERRED;
1999                         }
2000                 }
2001         }
2002
2003         intel_dp_add_properties(intel_dp, connector);
2004
2005         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2006          * 0xd.  Failure to do so will result in spurious interrupts being
2007          * generated on the port when a cable is not attached.
2008          */
2009         if (IS_G4X(dev) && !IS_GM45(dev)) {
2010                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2011                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2012         }
2013 }