drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[4];
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59         bool is_pch_edp;
  60         uint8_t train_set[4];
  61         uint8_t link_status[DP_LINK_STATUS_SIZE];
  62 };
  63
  64 /**
  65  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  66  * @intel_dp: DP struct
  67  *
  68  * If a CPU or PCH DP output is attached to an eDP panel, this function
  69  * will return true, and false otherwise.
  70  */
  71 static bool is_edp(struct intel_dp *intel_dp)
  72 {
  73         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  74 }
  75
  76 /**
  77  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  78  * @intel_dp: DP struct
  79  *
  80  * Returns true if the given DP struct corresponds to a PCH DP port attached
  81  * to an eDP panel, false otherwise.  Helpful for determining whether we
  82  * may need FDI resources for a given DP output or not.
  83  */
  84 static bool is_pch_edp(struct intel_dp *intel_dp)
  85 {
  86         return intel_dp->is_pch_edp;
  87 }
  88
  89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  90 {
  91         return container_of(encoder, struct intel_dp, base.base);
  92 }
  93
  94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  95 {
  96         return container_of(intel_attached_encoder(connector),
  97                             struct intel_dp, base);
  98 }
  99
 100 /**
 101  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 102  * @encoder: DRM encoder
 103  *
 104  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 105  * by intel_display.c.
 106  */
 107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 108 {
 109         struct intel_dp *intel_dp;
 110
 111         if (!encoder)
 112                 return false;
 113
 114         intel_dp = enc_to_intel_dp(encoder);
 115
 116         return is_pch_edp(intel_dp);
 117 }
 118
 119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 121 static void intel_dp_link_down(struct intel_dp *intel_dp);
 122
 123 void
 124 intel_edp_link_config (struct intel_encoder *intel_encoder,
 125                        int *lane_num, int *link_bw)
 126 {
 127         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 128
 129         *lane_num = intel_dp->lane_count;
 130         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 131                 *link_bw = 162000;
 132         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 133                 *link_bw = 270000;
 134 }
 135
 136 static int
 137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 138 {
 139         int max_lane_count = 4;
 140
 141         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 142                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 143                 switch (max_lane_count) {
 144                 case 1: case 2: case 4:
 145                         break;
 146                 default:
 147                         max_lane_count = 4;
 148                 }
 149         }
 150         return max_lane_count;
 151 }
 152
 153 static int
 154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 155 {
 156         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 157
 158         switch (max_link_bw) {
 159         case DP_LINK_BW_1_62:
 160         case DP_LINK_BW_2_7:
 161                 break;
 162         default:
 163                 max_link_bw = DP_LINK_BW_1_62;
 164                 break;
 165         }
 166         return max_link_bw;
 167 }
 168
 169 static int
 170 intel_dp_link_clock(uint8_t link_bw)
 171 {
 172         if (link_bw == DP_LINK_BW_2_7)
 173                 return 270000;
 174         else
 175                 return 162000;
 176 }
 177
 178 /* I think this is a fiction */
 179 static int
 180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 181 {
 182         struct drm_i915_private *dev_priv = dev->dev_private;
 183
 184         if (is_edp(intel_dp))
 185                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
 186         else
 187                 return pixel_clock * 3;
 188 }
 189
 190 static int
 191 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 192 {
 193         return (max_link_clock * max_lanes * 8) / 10;
 194 }
 195
 196 static int
 197 intel_dp_mode_valid(struct drm_connector *connector,
 198                     struct drm_display_mode *mode)
 199 {
 200         struct intel_dp *intel_dp = intel_attached_dp(connector);
 201         struct drm_device *dev = connector->dev;
 202         struct drm_i915_private *dev_priv = dev->dev_private;
 203         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 204         int max_lanes = intel_dp_max_lane_count(intel_dp);
 205
 206         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 207                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 208                         return MODE_PANEL;
 209
 210                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 211                         return MODE_PANEL;
 212         }
 213
 214         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 215            which are outside spec tolerances but somehow work by magic */
 216         if (!is_edp(intel_dp) &&
 217             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 218              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 219                 return MODE_CLOCK_HIGH;
 220
 221         if (mode->clock < 10000)
 222                 return MODE_CLOCK_LOW;
 223
 224         return MODE_OK;
 225 }
 226
 227 static uint32_t
 228 pack_aux(uint8_t *src, int src_bytes)
 229 {
 230         int     i;
 231         uint32_t v = 0;
 232
 233         if (src_bytes > 4)
 234                 src_bytes = 4;
 235         for (i = 0; i < src_bytes; i++)
 236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 237         return v;
 238 }
 239
 240 static void
 241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 242 {
 243         int i;
 244         if (dst_bytes > 4)
 245                 dst_bytes = 4;
 246         for (i = 0; i < dst_bytes; i++)
 247                 dst[i] = src >> ((3-i) * 8);
 248 }
 249
 250 /* hrawclock is 1/4 the FSB frequency */
 251 static int
 252 intel_hrawclk(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         uint32_t clkcfg;
 256
 257         clkcfg = I915_READ(CLKCFG);
 258         switch (clkcfg & CLKCFG_FSB_MASK) {
 259         case CLKCFG_FSB_400:
 260                 return 100;
 261         case CLKCFG_FSB_533:
 262                 return 133;
 263         case CLKCFG_FSB_667:
 264                 return 166;
 265         case CLKCFG_FSB_800:
 266                 return 200;
 267         case CLKCFG_FSB_1067:
 268                 return 266;
 269         case CLKCFG_FSB_1333:
 270                 return 333;
 271         /* these two are just a guess; one of them might be right */
 272         case CLKCFG_FSB_1600:
 273         case CLKCFG_FSB_1600_ALT:
 274                 return 400;
 275         default:
 276                 return 133;
 277         }
 278 }
 279
 280 static int
 281 intel_dp_aux_ch(struct intel_dp *intel_dp,
 282                 uint8_t *send, int send_bytes,
 283                 uint8_t *recv, int recv_size)
 284 {
 285         uint32_t output_reg = intel_dp->output_reg;
 286         struct drm_device *dev = intel_dp->base.base.dev;
 287         struct drm_i915_private *dev_priv = dev->dev_private;
 288         uint32_t ch_ctl = output_reg + 0x10;
 289         uint32_t ch_data = ch_ctl + 4;
 290         int i;
 291         int recv_bytes;
 292         uint32_t status;
 293         uint32_t aux_clock_divider;
 294         int try, precharge;
 295
 296         /* The clock divider is based off the hrawclk,
 297          * and would like to run at 2MHz. So, take the
 298          * hrawclk value and divide by 2 and use that
 299          *
 300          * Note that PCH attached eDP panels should use a 125MHz input
 301          * clock divider.
 302          */
 303         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 304                 if (IS_GEN6(dev))
 305                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 306                 else
 307                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 308         } else if (HAS_PCH_SPLIT(dev))
 309                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 310         else
 311                 aux_clock_divider = intel_hrawclk(dev) / 2;
 312
 313         if (IS_GEN6(dev))
 314                 precharge = 3;
 315         else
 316                 precharge = 5;
 317
 318         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 319                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 320                           I915_READ(ch_ctl));
 321                 return -EBUSY;
 322         }
 323
 324         /* Must try at least 3 times according to DP spec */
 325         for (try = 0; try < 5; try++) {
 326                 /* Load the send data into the aux channel data registers */
 327                 for (i = 0; i < send_bytes; i += 4)
 328                         I915_WRITE(ch_data + i,
 329                                    pack_aux(send + i, send_bytes - i));
 330
 331                 /* Send the command and wait for it to complete */
 332                 I915_WRITE(ch_ctl,
 333                            DP_AUX_CH_CTL_SEND_BUSY |
 334                            DP_AUX_CH_CTL_TIME_OUT_400us |
 335                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 336                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 337                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 338                            DP_AUX_CH_CTL_DONE |
 339                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 340                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 341                 for (;;) {
 342                         status = I915_READ(ch_ctl);
 343                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 344                                 break;
 345                         udelay(100);
 346                 }
 347
 348                 /* Clear done status and any errors */
 349                 I915_WRITE(ch_ctl,
 350                            status |
 351                            DP_AUX_CH_CTL_DONE |
 352                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 353                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 354                 if (status & DP_AUX_CH_CTL_DONE)
 355                         break;
 356         }
 357
 358         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 359                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 360                 return -EBUSY;
 361         }
 362
 363         /* Check for timeout or receive error.
 364          * Timeouts occur when the sink is not connected
 365          */
 366         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 367                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 368                 return -EIO;
 369         }
 370
 371         /* Timeouts occur when the device isn't connected, so they're
 372          * "normal" -- don't fill the kernel log with these */
 373         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 374                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 375                 return -ETIMEDOUT;
 376         }
 377
 378         /* Unload any bytes sent back from the other side */
 379         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 380                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 381         if (recv_bytes > recv_size)
 382                 recv_bytes = recv_size;
 383
 384         for (i = 0; i < recv_bytes; i += 4)
 385                 unpack_aux(I915_READ(ch_data + i),
 386                            recv + i, recv_bytes - i);
 387
 388         return recv_bytes;
 389 }
 390
 391 /* Write data to the aux channel in native mode */
 392 static int
 393 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 394                           uint16_t address, uint8_t *send, int send_bytes)
 395 {
 396         int ret;
 397         uint8_t msg[20];
 398         int msg_bytes;
 399         uint8_t ack;
 400
 401         if (send_bytes > 16)
 402                 return -1;
 403         msg[0] = AUX_NATIVE_WRITE << 4;
 404         msg[1] = address >> 8;
 405         msg[2] = address & 0xff;
 406         msg[3] = send_bytes - 1;
 407         memcpy(&msg[4], send, send_bytes);
 408         msg_bytes = send_bytes + 4;
 409         for (;;) {
 410                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 411                 if (ret < 0)
 412                         return ret;
 413                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 414                         break;
 415                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 416                         udelay(100);
 417                 else
 418                         return -EIO;
 419         }
 420         return send_bytes;
 421 }
 422
 423 /* Write a single byte to the aux channel in native mode */
 424 static int
 425 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 426                             uint16_t address, uint8_t byte)
 427 {
 428         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 429 }
 430
 431 /* read bytes from a native aux channel */
 432 static int
 433 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 434                          uint16_t address, uint8_t *recv, int recv_bytes)
 435 {
 436         uint8_t msg[4];
 437         int msg_bytes;
 438         uint8_t reply[20];
 439         int reply_bytes;
 440         uint8_t ack;
 441         int ret;
 442
 443         msg[0] = AUX_NATIVE_READ << 4;
 444         msg[1] = address >> 8;
 445         msg[2] = address & 0xff;
 446         msg[3] = recv_bytes - 1;
 447
 448         msg_bytes = 4;
 449         reply_bytes = recv_bytes + 1;
 450
 451         for (;;) {
 452                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 453                                       reply, reply_bytes);
 454                 if (ret == 0)
 455                         return -EPROTO;
 456                 if (ret < 0)
 457                         return ret;
 458                 ack = reply[0];
 459                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 460                         memcpy(recv, reply + 1, ret - 1);
 461                         return ret - 1;
 462                 }
 463                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 464                         udelay(100);
 465                 else
 466                         return -EIO;
 467         }
 468 }
 469
 470 static int
 471 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 472                     uint8_t write_byte, uint8_t *read_byte)
 473 {
 474         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 475         struct intel_dp *intel_dp = container_of(adapter,
 476                                                 struct intel_dp,
 477                                                 adapter);
 478         uint16_t address = algo_data->address;
 479         uint8_t msg[5];
 480         uint8_t reply[2];
 481         unsigned retry;
 482         int msg_bytes;
 483         int reply_bytes;
 484         int ret;
 485
 486         /* Set up the command byte */
 487         if (mode & MODE_I2C_READ)
 488                 msg[0] = AUX_I2C_READ << 4;
 489         else
 490                 msg[0] = AUX_I2C_WRITE << 4;
 491
 492         if (!(mode & MODE_I2C_STOP))
 493                 msg[0] |= AUX_I2C_MOT << 4;
 494
 495         msg[1] = address >> 8;
 496         msg[2] = address;
 497
 498         switch (mode) {
 499         case MODE_I2C_WRITE:
 500                 msg[3] = 0;
 501                 msg[4] = write_byte;
 502                 msg_bytes = 5;
 503                 reply_bytes = 1;
 504                 break;
 505         case MODE_I2C_READ:
 506                 msg[3] = 0;
 507                 msg_bytes = 4;
 508                 reply_bytes = 2;
 509                 break;
 510         default:
 511                 msg_bytes = 3;
 512                 reply_bytes = 1;
 513                 break;
 514         }
 515
 516         for (retry = 0; retry < 5; retry++) {
 517                 ret = intel_dp_aux_ch(intel_dp,
 518                                       msg, msg_bytes,
 519                                       reply, reply_bytes);
 520                 if (ret < 0) {
 521                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 522                         return ret;
 523                 }
 524
 525                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 526                 case AUX_NATIVE_REPLY_ACK:
 527                         /* I2C-over-AUX Reply field is only valid
 528                          * when paired with AUX ACK.
 529                          */
 530                         break;
 531                 case AUX_NATIVE_REPLY_NACK:
 532                         DRM_DEBUG_KMS("aux_ch native nack\n");
 533                         return -EREMOTEIO;
 534                 case AUX_NATIVE_REPLY_DEFER:
 535                         udelay(100);
 536                         continue;
 537                 default:
 538                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 539                                   reply[0]);
 540                         return -EREMOTEIO;
 541                 }
 542
 543                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 544                 case AUX_I2C_REPLY_ACK:
 545                         if (mode == MODE_I2C_READ) {
 546                                 *read_byte = reply[1];
 547                         }
 548                         return reply_bytes - 1;
 549                 case AUX_I2C_REPLY_NACK:
 550                         DRM_DEBUG_KMS("aux_i2c nack\n");
 551                         return -EREMOTEIO;
 552                 case AUX_I2C_REPLY_DEFER:
 553                         DRM_DEBUG_KMS("aux_i2c defer\n");
 554                         udelay(100);
 555                         break;
 556                 default:
 557                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 558                         return -EREMOTEIO;
 559                 }
 560         }
 561
 562         DRM_ERROR("too many retries, giving up\n");
 563         return -EREMOTEIO;
 564 }
 565
 566 static int
 567 intel_dp_i2c_init(struct intel_dp *intel_dp,
 568                   struct intel_connector *intel_connector, const char *name)
 569 {
 570         DRM_DEBUG_KMS("i2c_init %s\n", name);
 571         intel_dp->algo.running = false;
 572         intel_dp->algo.address = 0;
 573         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 574
 575         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 576         intel_dp->adapter.owner = THIS_MODULE;
 577         intel_dp->adapter.class = I2C_CLASS_DDC;
 578         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 579         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 580         intel_dp->adapter.algo_data = &intel_dp->algo;
 581         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 582
 583         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 584 }
 585
 586 static bool
 587 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 588                     struct drm_display_mode *adjusted_mode)
 589 {
 590         struct drm_device *dev = encoder->dev;
 591         struct drm_i915_private *dev_priv = dev->dev_private;
 592         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 593         int lane_count, clock;
 594         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 595         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 596         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 597
 598         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 599                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 600                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 601                                         mode, adjusted_mode);
 602                 /*
 603                  * the mode->clock is used to calculate the Data&Link M/N
 604                  * of the pipe. For the eDP the fixed clock should be used.
 605                  */
 606                 mode->clock = dev_priv->panel_fixed_mode->clock;
 607         }
 608
 609         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 610                 for (clock = 0; clock <= max_clock; clock++) {
 611                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 612
 613                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 614                                         <= link_avail) {
 615                                 intel_dp->link_bw = bws[clock];
 616                                 intel_dp->lane_count = lane_count;
 617                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 618                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 619                                                 "count %d clock %d\n",
 620                                        intel_dp->link_bw, intel_dp->lane_count,
 621                                        adjusted_mode->clock);
 622                                 return true;
 623                         }
 624                 }
 625         }
 626
 627         if (is_edp(intel_dp)) {
 628                 /* okay we failed just pick the highest */
 629                 intel_dp->lane_count = max_lane_count;
 630                 intel_dp->link_bw = bws[max_clock];
 631                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 632                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 633                               "count %d clock %d\n",
 634                               intel_dp->link_bw, intel_dp->lane_count,
 635                               adjusted_mode->clock);
 636
 637                 return true;
 638         }
 639
 640         return false;
 641 }
 642
 643 struct intel_dp_m_n {
 644         uint32_t        tu;
 645         uint32_t        gmch_m;
 646         uint32_t        gmch_n;
 647         uint32_t        link_m;
 648         uint32_t        link_n;
 649 };
 650
 651 static void
 652 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 653 {
 654         while (*num > 0xffffff || *den > 0xffffff) {
 655                 *num >>= 1;
 656                 *den >>= 1;
 657         }
 658 }
 659
 660 static void
 661 intel_dp_compute_m_n(int bpp,
 662                      int nlanes,
 663                      int pixel_clock,
 664                      int link_clock,
 665                      struct intel_dp_m_n *m_n)
 666 {
 667         m_n->tu = 64;
 668         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 669         m_n->gmch_n = link_clock * nlanes;
 670         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 671         m_n->link_m = pixel_clock;
 672         m_n->link_n = link_clock;
 673         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 674 }
 675
 676 void
 677 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 678                  struct drm_display_mode *adjusted_mode)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_mode_config *mode_config = &dev->mode_config;
 682         struct drm_encoder *encoder;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 685         int lane_count = 4, bpp = 24;
 686         struct intel_dp_m_n m_n;
 687         int pipe = intel_crtc->pipe;
 688
 689         /*
 690          * Find the lane count in the intel_encoder private
 691          */
 692         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 693                 struct intel_dp *intel_dp;
 694
 695                 if (encoder->crtc != crtc)
 696                         continue;
 697
 698                 intel_dp = enc_to_intel_dp(encoder);
 699                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 700                         lane_count = intel_dp->lane_count;
 701                         break;
 702                 } else if (is_edp(intel_dp)) {
 703                         lane_count = dev_priv->edp.lanes;
 704                         bpp = dev_priv->edp.bpp;
 705                         break;
 706                 }
 707         }
 708
 709         /*
 710          * Compute the GMCH and Link ratios. The '3' here is
 711          * the number of bytes_per_pixel post-LUT, which we always
 712          * set up for 8-bits of R/G/B, or 3 bytes total.
 713          */
 714         intel_dp_compute_m_n(bpp, lane_count,
 715                              mode->clock, adjusted_mode->clock, &m_n);
 716
 717         if (HAS_PCH_SPLIT(dev)) {
 718                 I915_WRITE(TRANSDATA_M1(pipe),
 719                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 720                            m_n.gmch_m);
 721                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 722                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 723                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 724         } else {
 725                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 726                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 727                            m_n.gmch_m);
 728                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 729                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 730                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 731         }
 732 }
 733
 734 static void
 735 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 736                   struct drm_display_mode *adjusted_mode)
 737 {
 738         struct drm_device *dev = encoder->dev;
 739         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 740         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 742
 743         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 744         intel_dp->DP |= intel_dp->color_range;
 745
 746         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 747                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 748         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 749                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 750
 751         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 752                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 753         else
 754                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 755
 756         switch (intel_dp->lane_count) {
 757         case 1:
 758                 intel_dp->DP |= DP_PORT_WIDTH_1;
 759                 break;
 760         case 2:
 761                 intel_dp->DP |= DP_PORT_WIDTH_2;
 762                 break;
 763         case 4:
 764                 intel_dp->DP |= DP_PORT_WIDTH_4;
 765                 break;
 766         }
 767         if (intel_dp->has_audio)
 768                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 769
 770         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 771         intel_dp->link_configuration[0] = intel_dp->link_bw;
 772         intel_dp->link_configuration[1] = intel_dp->lane_count;
 773
 774         /*
 775          * Check for DPCD version > 1.1 and enhanced framing support
 776          */
 777         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 778             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 779                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 780                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 781         }
 782
 783         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 784         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 785                 intel_dp->DP |= DP_PIPEB_SELECT;
 786
 787         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 788                 /* don't miss out required setting for eDP */
 789                 intel_dp->DP |= DP_PLL_ENABLE;
 790                 if (adjusted_mode->clock < 200000)
 791                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 792                 else
 793                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 794         }
 795 }
 796
 797 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 798 {
 799         struct drm_device *dev = intel_dp->base.base.dev;
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         u32 pp;
 802
 803         /*
 804          * If the panel wasn't on, make sure there's not a currently
 805          * active PP sequence before enabling AUX VDD.
 806          */
 807         if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
 808                 msleep(dev_priv->panel_t3);
 809
 810         pp = I915_READ(PCH_PP_CONTROL);
 811         pp |= EDP_FORCE_VDD;
 812         I915_WRITE(PCH_PP_CONTROL, pp);
 813         POSTING_READ(PCH_PP_CONTROL);
 814 }
 815
 816 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 817 {
 818         struct drm_device *dev = intel_dp->base.base.dev;
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         u32 pp;
 821
 822         pp = I915_READ(PCH_PP_CONTROL);
 823         pp &= ~EDP_FORCE_VDD;
 824         I915_WRITE(PCH_PP_CONTROL, pp);
 825         POSTING_READ(PCH_PP_CONTROL);
 826
 827         /* Make sure sequencer is idle before allowing subsequent activity */
 828         msleep(dev_priv->panel_t12);
 829 }
 830
 831 /* Returns true if the panel was already on when called */
 832 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 833 {
 834         struct drm_device *dev = intel_dp->base.base.dev;
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 837
 838         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 839                 return true;
 840
 841         pp = I915_READ(PCH_PP_CONTROL);
 842
 843         /* ILK workaround: disable reset around power sequence */
 844         pp &= ~PANEL_POWER_RESET;
 845         I915_WRITE(PCH_PP_CONTROL, pp);
 846         POSTING_READ(PCH_PP_CONTROL);
 847
 848         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 849         I915_WRITE(PCH_PP_CONTROL, pp);
 850         POSTING_READ(PCH_PP_CONTROL);
 851
 852         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 853                      5000))
 854                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 855                           I915_READ(PCH_PP_STATUS));
 856
 857         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 858         I915_WRITE(PCH_PP_CONTROL, pp);
 859         POSTING_READ(PCH_PP_CONTROL);
 860
 861         return false;
 862 }
 863
 864 static void ironlake_edp_panel_off (struct drm_device *dev)
 865 {
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 868                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 869
 870         pp = I915_READ(PCH_PP_CONTROL);
 871
 872         /* ILK workaround: disable reset around power sequence */
 873         pp &= ~PANEL_POWER_RESET;
 874         I915_WRITE(PCH_PP_CONTROL, pp);
 875         POSTING_READ(PCH_PP_CONTROL);
 876
 877         pp &= ~POWER_TARGET_ON;
 878         I915_WRITE(PCH_PP_CONTROL, pp);
 879         POSTING_READ(PCH_PP_CONTROL);
 880
 881         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 882                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 883                           I915_READ(PCH_PP_STATUS));
 884
 885         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 886         I915_WRITE(PCH_PP_CONTROL, pp);
 887         POSTING_READ(PCH_PP_CONTROL);
 888 }
 889
 890 static void ironlake_edp_backlight_on (struct drm_device *dev)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 pp;
 894
 895         DRM_DEBUG_KMS("\n");
 896         /*
 897          * If we enable the backlight right away following a panel power
 898          * on, we may see slight flicker as the panel syncs with the eDP
 899          * link.  So delay a bit to make sure the image is solid before
 900          * allowing it to appear.
 901          */
 902         msleep(300);
 903         pp = I915_READ(PCH_PP_CONTROL);
 904         pp |= EDP_BLC_ENABLE;
 905         I915_WRITE(PCH_PP_CONTROL, pp);
 906 }
 907
 908 static void ironlake_edp_backlight_off (struct drm_device *dev)
 909 {
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         u32 pp;
 912
 913         DRM_DEBUG_KMS("\n");
 914         pp = I915_READ(PCH_PP_CONTROL);
 915         pp &= ~EDP_BLC_ENABLE;
 916         I915_WRITE(PCH_PP_CONTROL, pp);
 917 }
 918
 919 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 920 {
 921         struct drm_device *dev = encoder->dev;
 922         struct drm_i915_private *dev_priv = dev->dev_private;
 923         u32 dpa_ctl;
 924
 925         DRM_DEBUG_KMS("\n");
 926         dpa_ctl = I915_READ(DP_A);
 927         dpa_ctl |= DP_PLL_ENABLE;
 928         I915_WRITE(DP_A, dpa_ctl);
 929         POSTING_READ(DP_A);
 930         udelay(200);
 931 }
 932
 933 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 934 {
 935         struct drm_device *dev = encoder->dev;
 936         struct drm_i915_private *dev_priv = dev->dev_private;
 937         u32 dpa_ctl;
 938
 939         dpa_ctl = I915_READ(DP_A);
 940         dpa_ctl &= ~DP_PLL_ENABLE;
 941         I915_WRITE(DP_A, dpa_ctl);
 942         POSTING_READ(DP_A);
 943         udelay(200);
 944 }
 945
 946 static void intel_dp_prepare(struct drm_encoder *encoder)
 947 {
 948         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 949         struct drm_device *dev = encoder->dev;
 950
 951         if (is_edp(intel_dp)) {
 952                 ironlake_edp_backlight_off(dev);
 953                 ironlake_edp_panel_off(dev);
 954                 if (!is_pch_edp(intel_dp))
 955                         ironlake_edp_pll_on(encoder);
 956                 else
 957                         ironlake_edp_pll_off(encoder);
 958         }
 959         intel_dp_link_down(intel_dp);
 960 }
 961
 962 static void intel_dp_commit(struct drm_encoder *encoder)
 963 {
 964         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 965         struct drm_device *dev = encoder->dev;
 966
 967         if (is_edp(intel_dp))
 968                 ironlake_edp_panel_vdd_on(intel_dp);
 969
 970         intel_dp_start_link_train(intel_dp);
 971
 972         if (is_edp(intel_dp)) {
 973                 ironlake_edp_panel_on(intel_dp);
 974                 ironlake_edp_panel_vdd_off(intel_dp);
 975         }
 976
 977         intel_dp_complete_link_train(intel_dp);
 978
 979         if (is_edp(intel_dp))
 980                 ironlake_edp_backlight_on(dev);
 981 }
 982
 983 static void
 984 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 985 {
 986         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 987         struct drm_device *dev = encoder->dev;
 988         struct drm_i915_private *dev_priv = dev->dev_private;
 989         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 990
 991         if (mode != DRM_MODE_DPMS_ON) {
 992                 if (is_edp(intel_dp))
 993                         ironlake_edp_backlight_off(dev);
 994                 intel_dp_link_down(intel_dp);
 995                 if (is_edp(intel_dp))
 996                         ironlake_edp_panel_off(dev);
 997                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
 998                         ironlake_edp_pll_off(encoder);
 999         } else {
1000                 if (is_edp(intel_dp))
1001                         ironlake_edp_panel_vdd_on(intel_dp);
1002                 if (!(dp_reg & DP_PORT_EN)) {
1003                         intel_dp_start_link_train(intel_dp);
1004                         if (is_edp(intel_dp)) {
1005                                 ironlake_edp_panel_on(intel_dp);
1006                                 ironlake_edp_panel_vdd_off(intel_dp);
1007                         }
1008                         intel_dp_complete_link_train(intel_dp);
1009                 }
1010                 if (is_edp(intel_dp))
1011                         ironlake_edp_backlight_on(dev);
1012         }
1013         intel_dp->dpms_mode = mode;
1014 }
1015
1016 /*
1017  * Fetch AUX CH registers 0x202 - 0x207 which contain
1018  * link status information
1019  */
1020 static bool
1021 intel_dp_get_link_status(struct intel_dp *intel_dp)
1022 {
1023         int ret, i;
1024
1025         /* Must try AUX reads for this at least 3 times */
1026         for (i = 0; i < 3; i++) {
1027                 ret = intel_dp_aux_native_read(intel_dp,
1028                                                DP_LANE0_1_STATUS,
1029                                                intel_dp->link_status,
1030                                                DP_LINK_STATUS_SIZE);
1031                 if (ret == DP_LINK_STATUS_SIZE)
1032                         return true;
1033                 msleep(1);
1034         }
1035
1036         return false;
1037 }
1038
1039 static uint8_t
1040 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1041                      int r)
1042 {
1043         return link_status[r - DP_LANE0_1_STATUS];
1044 }
1045
1046 static uint8_t
1047 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1048                                  int lane)
1049 {
1050         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1051         int         s = ((lane & 1) ?
1052                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1053                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1054         uint8_t l = intel_dp_link_status(link_status, i);
1055
1056         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1057 }
1058
1059 static uint8_t
1060 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1061                                       int lane)
1062 {
1063         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1064         int         s = ((lane & 1) ?
1065                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1066                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1067         uint8_t l = intel_dp_link_status(link_status, i);
1068
1069         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1070 }
1071
1072
1073 #if 0
1074 static char     *voltage_names[] = {
1075         "0.4V", "0.6V", "0.8V", "1.2V"
1076 };
1077 static char     *pre_emph_names[] = {
1078         "0dB", "3.5dB", "6dB", "9.5dB"
1079 };
1080 static char     *link_train_names[] = {
1081         "pattern 1", "pattern 2", "idle", "off"
1082 };
1083 #endif
1084
1085 /*
1086  * These are source-specific values; current Intel hardware supports
1087  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1088  */
1089 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1090
1091 static uint8_t
1092 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1093 {
1094         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1095         case DP_TRAIN_VOLTAGE_SWING_400:
1096                 return DP_TRAIN_PRE_EMPHASIS_6;
1097         case DP_TRAIN_VOLTAGE_SWING_600:
1098                 return DP_TRAIN_PRE_EMPHASIS_6;
1099         case DP_TRAIN_VOLTAGE_SWING_800:
1100                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1101         case DP_TRAIN_VOLTAGE_SWING_1200:
1102         default:
1103                 return DP_TRAIN_PRE_EMPHASIS_0;
1104         }
1105 }
1106
1107 static void
1108 intel_get_adjust_train(struct intel_dp *intel_dp)
1109 {
1110         uint8_t v = 0;
1111         uint8_t p = 0;
1112         int lane;
1113
1114         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1115                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1116                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1117
1118                 if (this_v > v)
1119                         v = this_v;
1120                 if (this_p > p)
1121                         p = this_p;
1122         }
1123
1124         if (v >= I830_DP_VOLTAGE_MAX)
1125                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1126
1127         if (p >= intel_dp_pre_emphasis_max(v))
1128                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1129
1130         for (lane = 0; lane < 4; lane++)
1131                 intel_dp->train_set[lane] = v | p;
1132 }
1133
1134 static uint32_t
1135 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1136 {
1137         uint32_t        signal_levels = 0;
1138
1139         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1140         case DP_TRAIN_VOLTAGE_SWING_400:
1141         default:
1142                 signal_levels |= DP_VOLTAGE_0_4;
1143                 break;
1144         case DP_TRAIN_VOLTAGE_SWING_600:
1145                 signal_levels |= DP_VOLTAGE_0_6;
1146                 break;
1147         case DP_TRAIN_VOLTAGE_SWING_800:
1148                 signal_levels |= DP_VOLTAGE_0_8;
1149                 break;
1150         case DP_TRAIN_VOLTAGE_SWING_1200:
1151                 signal_levels |= DP_VOLTAGE_1_2;
1152                 break;
1153         }
1154         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1155         case DP_TRAIN_PRE_EMPHASIS_0:
1156         default:
1157                 signal_levels |= DP_PRE_EMPHASIS_0;
1158                 break;
1159         case DP_TRAIN_PRE_EMPHASIS_3_5:
1160                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1161                 break;
1162         case DP_TRAIN_PRE_EMPHASIS_6:
1163                 signal_levels |= DP_PRE_EMPHASIS_6;
1164                 break;
1165         case DP_TRAIN_PRE_EMPHASIS_9_5:
1166                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1167                 break;
1168         }
1169         return signal_levels;
1170 }
1171
1172 /* Gen6's DP voltage swing and pre-emphasis control */
1173 static uint32_t
1174 intel_gen6_edp_signal_levels(uint8_t train_set)
1175 {
1176         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1177                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1178         switch (signal_levels) {
1179         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1180         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1181                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1182         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1183                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1184         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1185         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1186                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1187         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1188         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1189                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1190         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1191         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1192                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1193         default:
1194                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1195                               "0x%x\n", signal_levels);
1196                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1197         }
1198 }
1199
1200 static uint8_t
1201 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1202                       int lane)
1203 {
1204         int i = DP_LANE0_1_STATUS + (lane >> 1);
1205         int s = (lane & 1) * 4;
1206         uint8_t l = intel_dp_link_status(link_status, i);
1207
1208         return (l >> s) & 0xf;
1209 }
1210
1211 /* Check for clock recovery is done on all channels */
1212 static bool
1213 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1214 {
1215         int lane;
1216         uint8_t lane_status;
1217
1218         for (lane = 0; lane < lane_count; lane++) {
1219                 lane_status = intel_get_lane_status(link_status, lane);
1220                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1221                         return false;
1222         }
1223         return true;
1224 }
1225
1226 /* Check to see if channel eq is done on all channels */
1227 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1228                          DP_LANE_CHANNEL_EQ_DONE|\
1229                          DP_LANE_SYMBOL_LOCKED)
1230 static bool
1231 intel_channel_eq_ok(struct intel_dp *intel_dp)
1232 {
1233         uint8_t lane_align;
1234         uint8_t lane_status;
1235         int lane;
1236
1237         lane_align = intel_dp_link_status(intel_dp->link_status,
1238                                           DP_LANE_ALIGN_STATUS_UPDATED);
1239         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1240                 return false;
1241         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1242                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1243                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1244                         return false;
1245         }
1246         return true;
1247 }
1248
1249 static bool
1250 intel_dp_set_link_train(struct intel_dp *intel_dp,
1251                         uint32_t dp_reg_value,
1252                         uint8_t dp_train_pat)
1253 {
1254         struct drm_device *dev = intel_dp->base.base.dev;
1255         struct drm_i915_private *dev_priv = dev->dev_private;
1256         int ret;
1257
1258         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1259         POSTING_READ(intel_dp->output_reg);
1260
1261         intel_dp_aux_native_write_1(intel_dp,
1262                                     DP_TRAINING_PATTERN_SET,
1263                                     dp_train_pat);
1264
1265         ret = intel_dp_aux_native_write(intel_dp,
1266                                         DP_TRAINING_LANE0_SET,
1267                                         intel_dp->train_set, 4);
1268         if (ret != 4)
1269                 return false;
1270
1271         return true;
1272 }
1273
1274 /* Enable corresponding port and start training pattern 1 */
1275 static void
1276 intel_dp_start_link_train(struct intel_dp *intel_dp)
1277 {
1278         struct drm_device *dev = intel_dp->base.base.dev;
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1281         int i;
1282         uint8_t voltage;
1283         bool clock_recovery = false;
1284         int tries;
1285         u32 reg;
1286         uint32_t DP = intel_dp->DP;
1287
1288         /* Enable output, wait for it to become active */
1289         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1290         POSTING_READ(intel_dp->output_reg);
1291         intel_wait_for_vblank(dev, intel_crtc->pipe);
1292
1293         /* Write the link configuration data */
1294         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1295                                   intel_dp->link_configuration,
1296                                   DP_LINK_CONFIGURATION_SIZE);
1297
1298         DP |= DP_PORT_EN;
1299         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1300                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1301         else
1302                 DP &= ~DP_LINK_TRAIN_MASK;
1303         memset(intel_dp->train_set, 0, 4);
1304         voltage = 0xff;
1305         tries = 0;
1306         clock_recovery = false;
1307         for (;;) {
1308                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1309                 uint32_t    signal_levels;
1310                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1311                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1312                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1313                 } else {
1314                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1315                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1316                 }
1317
1318                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1319                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1320                 else
1321                         reg = DP | DP_LINK_TRAIN_PAT_1;
1322
1323                 if (!intel_dp_set_link_train(intel_dp, reg,
1324                                              DP_TRAINING_PATTERN_1))
1325                         break;
1326                 /* Set training pattern 1 */
1327
1328                 udelay(100);
1329                 if (!intel_dp_get_link_status(intel_dp))
1330                         break;
1331
1332                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1333                         clock_recovery = true;
1334                         break;
1335                 }
1336
1337                 /* Check to see if we've tried the max voltage */
1338                 for (i = 0; i < intel_dp->lane_count; i++)
1339                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1340                                 break;
1341                 if (i == intel_dp->lane_count)
1342                         break;
1343
1344                 /* Check to see if we've tried the same voltage 5 times */
1345                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1346                         ++tries;
1347                         if (tries == 5)
1348                                 break;
1349                 } else
1350                         tries = 0;
1351                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1352
1353                 /* Compute new intel_dp->train_set as requested by target */
1354                 intel_get_adjust_train(intel_dp);
1355         }
1356
1357         intel_dp->DP = DP;
1358 }
1359
1360 static void
1361 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1362 {
1363         struct drm_device *dev = intel_dp->base.base.dev;
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         bool channel_eq = false;
1366         int tries, cr_tries;
1367         u32 reg;
1368         uint32_t DP = intel_dp->DP;
1369
1370         /* channel equalization */
1371         tries = 0;
1372         cr_tries = 0;
1373         channel_eq = false;
1374         for (;;) {
1375                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1376                 uint32_t    signal_levels;
1377
1378                 if (cr_tries > 5) {
1379                         DRM_ERROR("failed to train DP, aborting\n");
1380                         intel_dp_link_down(intel_dp);
1381                         break;
1382                 }
1383
1384                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1385                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1386                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1387                 } else {
1388                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1389                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1390                 }
1391
1392                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1393                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1394                 else
1395                         reg = DP | DP_LINK_TRAIN_PAT_2;
1396
1397                 /* channel eq pattern */
1398                 if (!intel_dp_set_link_train(intel_dp, reg,
1399                                              DP_TRAINING_PATTERN_2))
1400                         break;
1401
1402                 udelay(400);
1403                 if (!intel_dp_get_link_status(intel_dp))
1404                         break;
1405
1406                 /* Make sure clock is still ok */
1407                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1408                         intel_dp_start_link_train(intel_dp);
1409                         cr_tries++;
1410                         continue;
1411                 }
1412
1413                 if (intel_channel_eq_ok(intel_dp)) {
1414                         channel_eq = true;
1415                         break;
1416                 }
1417
1418                 /* Try 5 times, then try clock recovery if that fails */
1419                 if (tries > 5) {
1420                         intel_dp_link_down(intel_dp);
1421                         intel_dp_start_link_train(intel_dp);
1422                         tries = 0;
1423                         cr_tries++;
1424                         continue;
1425                 }
1426
1427                 /* Compute new intel_dp->train_set as requested by target */
1428                 intel_get_adjust_train(intel_dp);
1429                 ++tries;
1430         }
1431
1432         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1433                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1434         else
1435                 reg = DP | DP_LINK_TRAIN_OFF;
1436
1437         I915_WRITE(intel_dp->output_reg, reg);
1438         POSTING_READ(intel_dp->output_reg);
1439         intel_dp_aux_native_write_1(intel_dp,
1440                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1441 }
1442
1443 static void
1444 intel_dp_link_down(struct intel_dp *intel_dp)
1445 {
1446         struct drm_device *dev = intel_dp->base.base.dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         uint32_t DP = intel_dp->DP;
1449
1450         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1451                 return;
1452
1453         DRM_DEBUG_KMS("\n");
1454
1455         if (is_edp(intel_dp)) {
1456                 DP &= ~DP_PLL_ENABLE;
1457                 I915_WRITE(intel_dp->output_reg, DP);
1458                 POSTING_READ(intel_dp->output_reg);
1459                 udelay(100);
1460         }
1461
1462         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1463                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1464                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1465         } else {
1466                 DP &= ~DP_LINK_TRAIN_MASK;
1467                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1468         }
1469         POSTING_READ(intel_dp->output_reg);
1470
1471         msleep(17);
1472
1473         if (is_edp(intel_dp))
1474                 DP |= DP_LINK_TRAIN_OFF;
1475
1476         if (!HAS_PCH_CPT(dev) &&
1477             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1478                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1479
1480                 /* Hardware workaround: leaving our transcoder select
1481                  * set to transcoder B while it's off will prevent the
1482                  * corresponding HDMI output on transcoder A.
1483                  *
1484                  * Combine this with another hardware workaround:
1485                  * transcoder select bit can only be cleared while the
1486                  * port is enabled.
1487                  */
1488                 DP &= ~DP_PIPEB_SELECT;
1489                 I915_WRITE(intel_dp->output_reg, DP);
1490
1491                 /* Changes to enable or select take place the vblank
1492                  * after being written.
1493                  */
1494                 if (crtc == NULL) {
1495                         /* We can arrive here never having been attached
1496                          * to a CRTC, for instance, due to inheriting
1497                          * random state from the BIOS.
1498                          *
1499                          * If the pipe is not running, play safe and
1500                          * wait for the clocks to stabilise before
1501                          * continuing.
1502                          */
1503                         POSTING_READ(intel_dp->output_reg);
1504                         msleep(50);
1505                 } else
1506                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1507         }
1508
1509         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1510         POSTING_READ(intel_dp->output_reg);
1511 }
1512
1513 /*
1514  * According to DP spec
1515  * 5.1.2:
1516  *  1. Read DPCD
1517  *  2. Configure link according to Receiver Capabilities
1518  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1519  *  4. Check link status on receipt of hot-plug interrupt
1520  */
1521
1522 static void
1523 intel_dp_check_link_status(struct intel_dp *intel_dp)
1524 {
1525         int ret;
1526
1527         if (!intel_dp->base.base.crtc)
1528                 return;
1529
1530         if (!intel_dp_get_link_status(intel_dp)) {
1531                 intel_dp_link_down(intel_dp);
1532                 return;
1533         }
1534
1535         /* Try to read receiver status if the link appears to be up */
1536         ret = intel_dp_aux_native_read(intel_dp,
1537                                        0x000, intel_dp->dpcd,
1538                                        sizeof (intel_dp->dpcd));
1539         if (ret != sizeof(intel_dp->dpcd)) {
1540                 intel_dp_link_down(intel_dp);
1541                 return;
1542         }
1543
1544         if (!intel_channel_eq_ok(intel_dp)) {
1545                 intel_dp_start_link_train(intel_dp);
1546                 intel_dp_complete_link_train(intel_dp);
1547         }
1548 }
1549
1550 static enum drm_connector_status
1551 ironlake_dp_detect(struct intel_dp *intel_dp)
1552 {
1553         enum drm_connector_status status;
1554
1555         /* Can't disconnect eDP, but you can close the lid... */
1556         if (is_edp(intel_dp)) {
1557                 status = intel_panel_detect(intel_dp->base.base.dev);
1558                 if (status == connector_status_unknown)
1559                         status = connector_status_connected;
1560                 return status;
1561         }
1562
1563         status = connector_status_disconnected;
1564         if (intel_dp_aux_native_read(intel_dp,
1565                                      0x000, intel_dp->dpcd,
1566                                      sizeof (intel_dp->dpcd))
1567             == sizeof(intel_dp->dpcd)) {
1568                 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1569                         status = connector_status_connected;
1570         }
1571         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1572                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1573         return status;
1574 }
1575
1576 static enum drm_connector_status
1577 g4x_dp_detect(struct intel_dp *intel_dp)
1578 {
1579         struct drm_device *dev = intel_dp->base.base.dev;
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         enum drm_connector_status status;
1582         uint32_t temp, bit;
1583
1584         switch (intel_dp->output_reg) {
1585         case DP_B:
1586                 bit = DPB_HOTPLUG_INT_STATUS;
1587                 break;
1588         case DP_C:
1589                 bit = DPC_HOTPLUG_INT_STATUS;
1590                 break;
1591         case DP_D:
1592                 bit = DPD_HOTPLUG_INT_STATUS;
1593                 break;
1594         default:
1595                 return connector_status_unknown;
1596         }
1597
1598         temp = I915_READ(PORT_HOTPLUG_STAT);
1599
1600         if ((temp & bit) == 0)
1601                 return connector_status_disconnected;
1602
1603         status = connector_status_disconnected;
1604         if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1605                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1606         {
1607                 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1608                         status = connector_status_connected;
1609         }
1610
1611         return status;
1612 }
1613
1614 /**
1615  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1616  *
1617  * \return true if DP port is connected.
1618  * \return false if DP port is disconnected.
1619  */
1620 static enum drm_connector_status
1621 intel_dp_detect(struct drm_connector *connector, bool force)
1622 {
1623         struct intel_dp *intel_dp = intel_attached_dp(connector);
1624         struct drm_device *dev = intel_dp->base.base.dev;
1625         enum drm_connector_status status;
1626         struct edid *edid = NULL;
1627
1628         intel_dp->has_audio = false;
1629
1630         if (HAS_PCH_SPLIT(dev))
1631                 status = ironlake_dp_detect(intel_dp);
1632         else
1633                 status = g4x_dp_detect(intel_dp);
1634         if (status != connector_status_connected)
1635                 return status;
1636
1637         if (intel_dp->force_audio) {
1638                 intel_dp->has_audio = intel_dp->force_audio > 0;
1639         } else {
1640                 edid = drm_get_edid(connector, &intel_dp->adapter);
1641                 if (edid) {
1642                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1643                         connector->display_info.raw_edid = NULL;
1644                         kfree(edid);
1645                 }
1646         }
1647
1648         return connector_status_connected;
1649 }
1650
1651 static int intel_dp_get_modes(struct drm_connector *connector)
1652 {
1653         struct intel_dp *intel_dp = intel_attached_dp(connector);
1654         struct drm_device *dev = intel_dp->base.base.dev;
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656         int ret;
1657
1658         /* We should parse the EDID data and find out if it has an audio sink
1659          */
1660
1661         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1662         if (ret) {
1663                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1664                         struct drm_display_mode *newmode;
1665                         list_for_each_entry(newmode, &connector->probed_modes,
1666                                             head) {
1667                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1668                                         dev_priv->panel_fixed_mode =
1669                                                 drm_mode_duplicate(dev, newmode);
1670                                         break;
1671                                 }
1672                         }
1673                 }
1674
1675                 return ret;
1676         }
1677
1678         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1679         if (is_edp(intel_dp)) {
1680                 if (dev_priv->panel_fixed_mode != NULL) {
1681                         struct drm_display_mode *mode;
1682                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1683                         drm_mode_probed_add(connector, mode);
1684                         return 1;
1685                 }
1686         }
1687         return 0;
1688 }
1689
1690 static bool
1691 intel_dp_detect_audio(struct drm_connector *connector)
1692 {
1693         struct intel_dp *intel_dp = intel_attached_dp(connector);
1694         struct edid *edid;
1695         bool has_audio = false;
1696
1697         edid = drm_get_edid(connector, &intel_dp->adapter);
1698         if (edid) {
1699                 has_audio = drm_detect_monitor_audio(edid);
1700
1701                 connector->display_info.raw_edid = NULL;
1702                 kfree(edid);
1703         }
1704
1705         return has_audio;
1706 }
1707
1708 static int
1709 intel_dp_set_property(struct drm_connector *connector,
1710                       struct drm_property *property,
1711                       uint64_t val)
1712 {
1713         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1714         struct intel_dp *intel_dp = intel_attached_dp(connector);
1715         int ret;
1716
1717         ret = drm_connector_property_set_value(connector, property, val);
1718         if (ret)
1719                 return ret;
1720
1721         if (property == dev_priv->force_audio_property) {
1722                 int i = val;
1723                 bool has_audio;
1724
1725                 if (i == intel_dp->force_audio)
1726                         return 0;
1727
1728                 intel_dp->force_audio = i;
1729
1730                 if (i == 0)
1731                         has_audio = intel_dp_detect_audio(connector);
1732                 else
1733                         has_audio = i > 0;
1734
1735                 if (has_audio == intel_dp->has_audio)
1736                         return 0;
1737
1738                 intel_dp->has_audio = has_audio;
1739                 goto done;
1740         }
1741
1742         if (property == dev_priv->broadcast_rgb_property) {
1743                 if (val == !!intel_dp->color_range)
1744                         return 0;
1745
1746                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1747                 goto done;
1748         }
1749
1750         return -EINVAL;
1751
1752 done:
1753         if (intel_dp->base.base.crtc) {
1754                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1755                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1756                                          crtc->x, crtc->y,
1757                                          crtc->fb);
1758         }
1759
1760         return 0;
1761 }
1762
1763 static void
1764 intel_dp_destroy (struct drm_connector *connector)
1765 {
1766         drm_sysfs_connector_remove(connector);
1767         drm_connector_cleanup(connector);
1768         kfree(connector);
1769 }
1770
1771 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1772 {
1773         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1774
1775         i2c_del_adapter(&intel_dp->adapter);
1776         drm_encoder_cleanup(encoder);
1777         kfree(intel_dp);
1778 }
1779
1780 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1781         .dpms = intel_dp_dpms,
1782         .mode_fixup = intel_dp_mode_fixup,
1783         .prepare = intel_dp_prepare,
1784         .mode_set = intel_dp_mode_set,
1785         .commit = intel_dp_commit,
1786 };
1787
1788 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1789         .dpms = drm_helper_connector_dpms,
1790         .detect = intel_dp_detect,
1791         .fill_modes = drm_helper_probe_single_connector_modes,
1792         .set_property = intel_dp_set_property,
1793         .destroy = intel_dp_destroy,
1794 };
1795
1796 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1797         .get_modes = intel_dp_get_modes,
1798         .mode_valid = intel_dp_mode_valid,
1799         .best_encoder = intel_best_encoder,
1800 };
1801
1802 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1803         .destroy = intel_dp_encoder_destroy,
1804 };
1805
1806 static void
1807 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1808 {
1809         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1810
1811         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1812                 intel_dp_check_link_status(intel_dp);
1813 }
1814
1815 /* Return which DP Port should be selected for Transcoder DP control */
1816 int
1817 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1818 {
1819         struct drm_device *dev = crtc->dev;
1820         struct drm_mode_config *mode_config = &dev->mode_config;
1821         struct drm_encoder *encoder;
1822
1823         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1824                 struct intel_dp *intel_dp;
1825
1826                 if (encoder->crtc != crtc)
1827                         continue;
1828
1829                 intel_dp = enc_to_intel_dp(encoder);
1830                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1831                         return intel_dp->output_reg;
1832         }
1833
1834         return -1;
1835 }
1836
1837 /* check the VBT to see whether the eDP is on DP-D port */
1838 bool intel_dpd_is_edp(struct drm_device *dev)
1839 {
1840         struct drm_i915_private *dev_priv = dev->dev_private;
1841         struct child_device_config *p_child;
1842         int i;
1843
1844         if (!dev_priv->child_dev_num)
1845                 return false;
1846
1847         for (i = 0; i < dev_priv->child_dev_num; i++) {
1848                 p_child = dev_priv->child_dev + i;
1849
1850                 if (p_child->dvo_port == PORT_IDPD &&
1851                     p_child->device_type == DEVICE_TYPE_eDP)
1852                         return true;
1853         }
1854         return false;
1855 }
1856
1857 static void
1858 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1859 {
1860         intel_attach_force_audio_property(connector);
1861         intel_attach_broadcast_rgb_property(connector);
1862 }
1863
1864 void
1865 intel_dp_init(struct drm_device *dev, int output_reg)
1866 {
1867         struct drm_i915_private *dev_priv = dev->dev_private;
1868         struct drm_connector *connector;
1869         struct intel_dp *intel_dp;
1870         struct intel_encoder *intel_encoder;
1871         struct intel_connector *intel_connector;
1872         const char *name = NULL;
1873         int type;
1874
1875         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1876         if (!intel_dp)
1877                 return;
1878
1879         intel_dp->output_reg = output_reg;
1880         intel_dp->dpms_mode = -1;
1881
1882         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1883         if (!intel_connector) {
1884                 kfree(intel_dp);
1885                 return;
1886         }
1887         intel_encoder = &intel_dp->base;
1888
1889         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1890                 if (intel_dpd_is_edp(dev))
1891                         intel_dp->is_pch_edp = true;
1892
1893         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1894                 type = DRM_MODE_CONNECTOR_eDP;
1895                 intel_encoder->type = INTEL_OUTPUT_EDP;
1896         } else {
1897                 type = DRM_MODE_CONNECTOR_DisplayPort;
1898                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1899         }
1900
1901         connector = &intel_connector->base;
1902         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1903         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1904
1905         connector->polled = DRM_CONNECTOR_POLL_HPD;
1906
1907         if (output_reg == DP_B || output_reg == PCH_DP_B)
1908                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1909         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1910                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1911         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1912                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1913
1914         if (is_edp(intel_dp))
1915                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1916
1917         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1918         connector->interlace_allowed = true;
1919         connector->doublescan_allowed = 0;
1920
1921         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1922                          DRM_MODE_ENCODER_TMDS);
1923         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1924
1925         intel_connector_attach_encoder(intel_connector, intel_encoder);
1926         drm_sysfs_connector_add(connector);
1927
1928         /* Set up the DDC bus. */
1929         switch (output_reg) {
1930                 case DP_A:
1931                         name = "DPDDC-A";
1932                         break;
1933                 case DP_B:
1934                 case PCH_DP_B:
1935                         dev_priv->hotplug_supported_mask |=
1936                                 HDMIB_HOTPLUG_INT_STATUS;
1937                         name = "DPDDC-B";
1938                         break;
1939                 case DP_C:
1940                 case PCH_DP_C:
1941                         dev_priv->hotplug_supported_mask |=
1942                                 HDMIC_HOTPLUG_INT_STATUS;
1943                         name = "DPDDC-C";
1944                         break;
1945                 case DP_D:
1946                 case PCH_DP_D:
1947                         dev_priv->hotplug_supported_mask |=
1948                                 HDMID_HOTPLUG_INT_STATUS;
1949                         name = "DPDDC-D";
1950                         break;
1951         }
1952
1953         intel_dp_i2c_init(intel_dp, intel_connector, name);
1954
1955         /* Cache some DPCD data in the eDP case */
1956         if (is_edp(intel_dp)) {
1957                 int ret;
1958                 u32 pp_on, pp_div;
1959
1960                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
1961                 pp_div = I915_READ(PCH_PP_DIVISOR);
1962
1963                 /* Get T3 & T12 values (note: VESA not bspec terminology) */
1964                 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
1965                 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
1966                 dev_priv->panel_t12 = pp_div & 0xf;
1967                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
1968
1969                 ironlake_edp_panel_vdd_on(intel_dp);
1970                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1971                                                intel_dp->dpcd,
1972                                                sizeof(intel_dp->dpcd));
1973                 ironlake_edp_panel_vdd_off(intel_dp);
1974                 if (ret == sizeof(intel_dp->dpcd)) {
1975                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
1976                                 dev_priv->no_aux_handshake =
1977                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
1978                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1979                 } else {
1980                         /* if this fails, presume the device is a ghost */
1981                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
1982                         intel_dp_encoder_destroy(&intel_dp->base.base);
1983                         intel_dp_destroy(&intel_connector->base);
1984                         return;
1985                 }
1986         }
1987
1988         intel_encoder->hot_plug = intel_dp_hot_plug;
1989
1990         if (is_edp(intel_dp)) {
1991                 /* initialize panel mode from VBT if available for eDP */
1992                 if (dev_priv->lfp_lvds_vbt_mode) {
1993                         dev_priv->panel_fixed_mode =
1994                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1995                         if (dev_priv->panel_fixed_mode) {
1996                                 dev_priv->panel_fixed_mode->type |=
1997                                         DRM_MODE_TYPE_PREFERRED;
1998                         }
1999                 }
2000         }
2001
2002         intel_dp_add_properties(intel_dp, connector);
2003
2004         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2005          * 0xd.  Failure to do so will result in spurious interrupts being
2006          * generated on the port when a cable is not attached.
2007          */
2008         if (IS_G4X(dev) && !IS_GM45(dev)) {
2009                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2010                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2011         }
2012 }