2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
32 #include "drm_crtc_helper.h"
33 #include "intel_drv.h"
38 #define DP_LINK_STATUS_SIZE 6
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41 #define DP_LINK_CONFIGURATION_SIZE 9
43 struct intel_dp_priv {
46 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
48 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
54 struct intel_output *intel_output;
55 struct i2c_adapter adapter;
56 struct i2c_algo_dp_aux_data algo;
60 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
61 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
64 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
67 intel_dp_max_lane_count(struct intel_output *intel_output)
69 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
70 int max_lane_count = 4;
72 if (dp_priv->dpcd[0] >= 0x11) {
73 max_lane_count = dp_priv->dpcd[2] & 0x1f;
74 switch (max_lane_count) {
75 case 1: case 2: case 4:
81 return max_lane_count;
85 intel_dp_max_link_bw(struct intel_output *intel_output)
87 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
88 int max_link_bw = dp_priv->dpcd[1];
90 switch (max_link_bw) {
95 max_link_bw = DP_LINK_BW_1_62;
102 intel_dp_link_clock(uint8_t link_bw)
104 if (link_bw == DP_LINK_BW_2_7)
110 /* I think this is a fiction */
112 intel_dp_link_required(int pixel_clock)
114 return pixel_clock * 3;
118 intel_dp_mode_valid(struct drm_connector *connector,
119 struct drm_display_mode *mode)
121 struct intel_output *intel_output = to_intel_output(connector);
122 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
123 int max_lanes = intel_dp_max_lane_count(intel_output);
125 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
126 return MODE_CLOCK_HIGH;
128 if (mode->clock < 10000)
129 return MODE_CLOCK_LOW;
135 pack_aux(uint8_t *src, int src_bytes)
142 for (i = 0; i < src_bytes; i++)
143 v |= ((uint32_t) src[i]) << ((3-i) * 8);
148 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
153 for (i = 0; i < dst_bytes; i++)
154 dst[i] = src >> ((3-i) * 8);
157 /* hrawclock is 1/4 the FSB frequency */
159 intel_hrawclk(struct drm_device *dev)
161 struct drm_i915_private *dev_priv = dev->dev_private;
164 clkcfg = I915_READ(CLKCFG);
165 switch (clkcfg & CLKCFG_FSB_MASK) {
174 case CLKCFG_FSB_1067:
176 case CLKCFG_FSB_1333:
178 /* these two are just a guess; one of them might be right */
179 case CLKCFG_FSB_1600:
180 case CLKCFG_FSB_1600_ALT:
188 intel_dp_aux_ch(struct intel_output *intel_output,
189 uint8_t *send, int send_bytes,
190 uint8_t *recv, int recv_size)
192 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
193 uint32_t output_reg = dp_priv->output_reg;
194 struct drm_device *dev = intel_output->base.dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 uint32_t ch_ctl = output_reg + 0x10;
197 uint32_t ch_data = ch_ctl + 4;
202 uint32_t aux_clock_divider;
205 /* The clock divider is based off the hrawclk,
206 * and would like to run at 2MHz. So, take the
207 * hrawclk value and divide by 2 and use that
209 aux_clock_divider = intel_hrawclk(dev) / 2;
210 /* Must try at least 3 times according to DP spec */
211 for (try = 0; try < 5; try++) {
212 /* Load the send data into the aux channel data registers */
213 for (i = 0; i < send_bytes; i += 4) {
214 uint32_t d = pack_aux(send + i, send_bytes - i);;
216 I915_WRITE(ch_data + i, d);
219 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
220 DP_AUX_CH_CTL_TIME_OUT_400us |
221 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
222 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
223 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
225 DP_AUX_CH_CTL_TIME_OUT_ERROR |
226 DP_AUX_CH_CTL_RECEIVE_ERROR);
228 /* Send the command and wait for it to complete */
229 I915_WRITE(ch_ctl, ctl);
230 (void) I915_READ(ch_ctl);
233 status = I915_READ(ch_ctl);
234 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
238 /* Clear done status and any errors */
239 I915_WRITE(ch_ctl, (ctl |
241 DP_AUX_CH_CTL_TIME_OUT_ERROR |
242 DP_AUX_CH_CTL_RECEIVE_ERROR));
243 (void) I915_READ(ch_ctl);
244 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
248 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
249 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
253 /* Check for timeout or receive error.
254 * Timeouts occur when the sink is not connected
256 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
257 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
261 /* Timeouts occur when the device isn't connected, so they're
262 * "normal" -- don't fill the kernel log with these */
263 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
264 DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status);
268 /* Unload any bytes sent back from the other side */
269 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
270 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
272 if (recv_bytes > recv_size)
273 recv_bytes = recv_size;
275 for (i = 0; i < recv_bytes; i += 4) {
276 uint32_t d = I915_READ(ch_data + i);
278 unpack_aux(d, recv + i, recv_bytes - i);
284 /* Write data to the aux channel in native mode */
286 intel_dp_aux_native_write(struct intel_output *intel_output,
287 uint16_t address, uint8_t *send, int send_bytes)
296 msg[0] = AUX_NATIVE_WRITE << 4;
297 msg[1] = address >> 8;
299 msg[3] = send_bytes - 1;
300 memcpy(&msg[4], send, send_bytes);
301 msg_bytes = send_bytes + 4;
303 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
306 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
308 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
316 /* Write a single byte to the aux channel in native mode */
318 intel_dp_aux_native_write_1(struct intel_output *intel_output,
319 uint16_t address, uint8_t byte)
321 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
324 /* read bytes from a native aux channel */
326 intel_dp_aux_native_read(struct intel_output *intel_output,
327 uint16_t address, uint8_t *recv, int recv_bytes)
336 msg[0] = AUX_NATIVE_READ << 4;
337 msg[1] = address >> 8;
338 msg[2] = address & 0xff;
339 msg[3] = recv_bytes - 1;
342 reply_bytes = recv_bytes + 1;
345 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
352 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
353 memcpy(recv, reply + 1, ret - 1);
356 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
364 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
365 uint8_t *send, int send_bytes,
366 uint8_t *recv, int recv_bytes)
368 struct intel_dp_priv *dp_priv = container_of(adapter,
369 struct intel_dp_priv,
371 struct intel_output *intel_output = dp_priv->intel_output;
373 return intel_dp_aux_ch(intel_output,
374 send, send_bytes, recv, recv_bytes);
378 intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
380 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
382 DRM_ERROR("i2c_init %s\n", name);
383 dp_priv->algo.running = false;
384 dp_priv->algo.address = 0;
385 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
387 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
388 dp_priv->adapter.owner = THIS_MODULE;
389 dp_priv->adapter.class = I2C_CLASS_DDC;
390 strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
391 dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
392 dp_priv->adapter.algo_data = &dp_priv->algo;
393 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
395 return i2c_dp_aux_add_bus(&dp_priv->adapter);
399 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
400 struct drm_display_mode *adjusted_mode)
402 struct intel_output *intel_output = enc_to_intel_output(encoder);
403 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
404 int lane_count, clock;
405 int max_lane_count = intel_dp_max_lane_count(intel_output);
406 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
407 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
409 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
410 for (clock = 0; clock <= max_clock; clock++) {
411 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
413 if (intel_dp_link_required(mode->clock) <= link_avail) {
414 dp_priv->link_bw = bws[clock];
415 dp_priv->lane_count = lane_count;
416 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
417 DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n",
418 dp_priv->link_bw, dp_priv->lane_count,
419 adjusted_mode->clock);
427 struct intel_dp_m_n {
436 intel_reduce_ratio(uint32_t *num, uint32_t *den)
438 while (*num > 0xffffff || *den > 0xffffff) {
445 intel_dp_compute_m_n(int bytes_per_pixel,
449 struct intel_dp_m_n *m_n)
452 m_n->gmch_m = pixel_clock * bytes_per_pixel;
453 m_n->gmch_n = link_clock * nlanes;
454 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
455 m_n->link_m = pixel_clock;
456 m_n->link_n = link_clock;
457 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
461 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
462 struct drm_display_mode *adjusted_mode)
464 struct drm_device *dev = crtc->dev;
465 struct drm_mode_config *mode_config = &dev->mode_config;
466 struct drm_connector *connector;
467 struct drm_i915_private *dev_priv = dev->dev_private;
468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
470 struct intel_dp_m_n m_n;
473 * Find the lane count in the intel_output private
475 list_for_each_entry(connector, &mode_config->connector_list, head) {
476 struct intel_output *intel_output = to_intel_output(connector);
477 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
479 if (!connector->encoder || connector->encoder->crtc != crtc)
482 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
483 lane_count = dp_priv->lane_count;
489 * Compute the GMCH and Link ratios. The '3' here is
490 * the number of bytes_per_pixel post-LUT, which we always
491 * set up for 8-bits of R/G/B, or 3 bytes total.
493 intel_dp_compute_m_n(3, lane_count,
494 mode->clock, adjusted_mode->clock, &m_n);
496 if (intel_crtc->pipe == 0) {
497 I915_WRITE(PIPEA_GMCH_DATA_M,
498 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
500 I915_WRITE(PIPEA_GMCH_DATA_N,
502 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
503 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
505 I915_WRITE(PIPEB_GMCH_DATA_M,
506 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
508 I915_WRITE(PIPEB_GMCH_DATA_N,
510 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
511 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
516 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
517 struct drm_display_mode *adjusted_mode)
519 struct intel_output *intel_output = enc_to_intel_output(encoder);
520 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
521 struct drm_crtc *crtc = intel_output->enc.crtc;
522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
524 dp_priv->DP = (DP_LINK_TRAIN_OFF |
530 switch (dp_priv->lane_count) {
532 dp_priv->DP |= DP_PORT_WIDTH_1;
535 dp_priv->DP |= DP_PORT_WIDTH_2;
538 dp_priv->DP |= DP_PORT_WIDTH_4;
541 if (dp_priv->has_audio)
542 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
544 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
545 dp_priv->link_configuration[0] = dp_priv->link_bw;
546 dp_priv->link_configuration[1] = dp_priv->lane_count;
549 * Check for DPCD version > 1.1,
550 * enable enahanced frame stuff in that case
552 if (dp_priv->dpcd[0] >= 0x11) {
553 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
554 dp_priv->DP |= DP_ENHANCED_FRAMING;
557 if (intel_crtc->pipe == 1)
558 dp_priv->DP |= DP_PIPEB_SELECT;
563 intel_dp_dpms(struct drm_encoder *encoder, int mode)
565 struct intel_output *intel_output = enc_to_intel_output(encoder);
566 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
567 struct drm_device *dev = intel_output->base.dev;
568 struct drm_i915_private *dev_priv = dev->dev_private;
569 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
571 if (mode != DRM_MODE_DPMS_ON) {
572 if (dp_reg & DP_PORT_EN)
573 intel_dp_link_down(intel_output, dp_priv->DP);
575 if (!(dp_reg & DP_PORT_EN))
576 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
578 dp_priv->dpms_mode = mode;
582 * Fetch AUX CH registers 0x202 - 0x207 which contain
583 * link status information
586 intel_dp_get_link_status(struct intel_output *intel_output,
587 uint8_t link_status[DP_LINK_STATUS_SIZE])
591 ret = intel_dp_aux_native_read(intel_output,
593 link_status, DP_LINK_STATUS_SIZE);
594 if (ret != DP_LINK_STATUS_SIZE)
600 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
603 return link_status[r - DP_LANE0_1_STATUS];
607 intel_dp_save(struct drm_connector *connector)
609 struct intel_output *intel_output = to_intel_output(connector);
610 struct drm_device *dev = intel_output->base.dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
614 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
615 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
616 dp_priv->save_link_configuration,
617 sizeof (dp_priv->save_link_configuration));
621 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
624 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
625 int s = ((lane & 1) ?
626 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
627 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
628 uint8_t l = intel_dp_link_status(link_status, i);
630 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
634 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
637 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
638 int s = ((lane & 1) ?
639 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
640 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
641 uint8_t l = intel_dp_link_status(link_status, i);
643 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
648 static char *voltage_names[] = {
649 "0.4V", "0.6V", "0.8V", "1.2V"
651 static char *pre_emph_names[] = {
652 "0dB", "3.5dB", "6dB", "9.5dB"
654 static char *link_train_names[] = {
655 "pattern 1", "pattern 2", "idle", "off"
660 * These are source-specific values; current Intel hardware supports
661 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
663 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
666 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
668 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
669 case DP_TRAIN_VOLTAGE_SWING_400:
670 return DP_TRAIN_PRE_EMPHASIS_6;
671 case DP_TRAIN_VOLTAGE_SWING_600:
672 return DP_TRAIN_PRE_EMPHASIS_6;
673 case DP_TRAIN_VOLTAGE_SWING_800:
674 return DP_TRAIN_PRE_EMPHASIS_3_5;
675 case DP_TRAIN_VOLTAGE_SWING_1200:
677 return DP_TRAIN_PRE_EMPHASIS_0;
682 intel_get_adjust_train(struct intel_output *intel_output,
683 uint8_t link_status[DP_LINK_STATUS_SIZE],
685 uint8_t train_set[4])
691 for (lane = 0; lane < lane_count; lane++) {
692 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
693 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
701 if (v >= I830_DP_VOLTAGE_MAX)
702 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
704 if (p >= intel_dp_pre_emphasis_max(v))
705 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
707 for (lane = 0; lane < 4; lane++)
708 train_set[lane] = v | p;
712 intel_dp_signal_levels(uint8_t train_set, int lane_count)
714 uint32_t signal_levels = 0;
716 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
717 case DP_TRAIN_VOLTAGE_SWING_400:
719 signal_levels |= DP_VOLTAGE_0_4;
721 case DP_TRAIN_VOLTAGE_SWING_600:
722 signal_levels |= DP_VOLTAGE_0_6;
724 case DP_TRAIN_VOLTAGE_SWING_800:
725 signal_levels |= DP_VOLTAGE_0_8;
727 case DP_TRAIN_VOLTAGE_SWING_1200:
728 signal_levels |= DP_VOLTAGE_1_2;
731 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
732 case DP_TRAIN_PRE_EMPHASIS_0:
734 signal_levels |= DP_PRE_EMPHASIS_0;
736 case DP_TRAIN_PRE_EMPHASIS_3_5:
737 signal_levels |= DP_PRE_EMPHASIS_3_5;
739 case DP_TRAIN_PRE_EMPHASIS_6:
740 signal_levels |= DP_PRE_EMPHASIS_6;
742 case DP_TRAIN_PRE_EMPHASIS_9_5:
743 signal_levels |= DP_PRE_EMPHASIS_9_5;
746 return signal_levels;
750 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
753 int i = DP_LANE0_1_STATUS + (lane >> 1);
754 int s = (lane & 1) * 4;
755 uint8_t l = intel_dp_link_status(link_status, i);
757 return (l >> s) & 0xf;
760 /* Check for clock recovery is done on all channels */
762 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
767 for (lane = 0; lane < lane_count; lane++) {
768 lane_status = intel_get_lane_status(link_status, lane);
769 if ((lane_status & DP_LANE_CR_DONE) == 0)
775 /* Check to see if channel eq is done on all channels */
776 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
777 DP_LANE_CHANNEL_EQ_DONE|\
778 DP_LANE_SYMBOL_LOCKED)
780 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
786 lane_align = intel_dp_link_status(link_status,
787 DP_LANE_ALIGN_STATUS_UPDATED);
788 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
790 for (lane = 0; lane < lane_count; lane++) {
791 lane_status = intel_get_lane_status(link_status, lane);
792 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
799 intel_dp_set_link_train(struct intel_output *intel_output,
800 uint32_t dp_reg_value,
801 uint8_t dp_train_pat,
802 uint8_t train_set[4],
805 struct drm_device *dev = intel_output->base.dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
810 I915_WRITE(dp_priv->output_reg, dp_reg_value);
811 POSTING_READ(dp_priv->output_reg);
813 intel_wait_for_vblank(dev);
815 intel_dp_aux_native_write_1(intel_output,
816 DP_TRAINING_PATTERN_SET,
819 ret = intel_dp_aux_native_write(intel_output,
820 DP_TRAINING_LANE0_SET, train_set, 4);
828 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
829 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
831 struct drm_device *dev = intel_output->base.dev;
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
834 uint8_t train_set[4];
835 uint8_t link_status[DP_LINK_STATUS_SIZE];
838 bool clock_recovery = false;
839 bool channel_eq = false;
843 /* Write the link configuration data */
844 intel_dp_aux_native_write(intel_output, 0x100,
845 link_configuration, DP_LINK_CONFIGURATION_SIZE);
848 DP &= ~DP_LINK_TRAIN_MASK;
849 memset(train_set, 0, 4);
852 clock_recovery = false;
854 /* Use train_set[0] to set the voltage and pre emphasis values */
855 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
856 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
858 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
859 DP_TRAINING_PATTERN_1, train_set, first))
862 /* Set training pattern 1 */
865 if (!intel_dp_get_link_status(intel_output, link_status))
868 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
869 clock_recovery = true;
873 /* Check to see if we've tried the max voltage */
874 for (i = 0; i < dp_priv->lane_count; i++)
875 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
877 if (i == dp_priv->lane_count)
880 /* Check to see if we've tried the same voltage 5 times */
881 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
887 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
889 /* Compute new train_set as requested by target */
890 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
893 /* channel equalization */
897 /* Use train_set[0] to set the voltage and pre emphasis values */
898 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
899 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
901 /* channel eq pattern */
902 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
903 DP_TRAINING_PATTERN_2, train_set,
908 if (!intel_dp_get_link_status(intel_output, link_status))
911 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
920 /* Compute new train_set as requested by target */
921 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
925 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
926 POSTING_READ(dp_priv->output_reg);
927 intel_dp_aux_native_write_1(intel_output,
928 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
932 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
934 struct drm_device *dev = intel_output->base.dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
936 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
938 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
939 POSTING_READ(dp_priv->output_reg);
943 intel_dp_restore(struct drm_connector *connector)
945 struct intel_output *intel_output = to_intel_output(connector);
946 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
948 if (dp_priv->save_DP & DP_PORT_EN)
949 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
951 intel_dp_link_down(intel_output, dp_priv->save_DP);
955 * According to DP spec
958 * 2. Configure link according to Receiver Capabilities
959 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
960 * 4. Check link status on receipt of hot-plug interrupt
964 intel_dp_check_link_status(struct intel_output *intel_output)
966 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
967 uint8_t link_status[DP_LINK_STATUS_SIZE];
969 if (!intel_output->enc.crtc)
972 if (!intel_dp_get_link_status(intel_output, link_status)) {
973 intel_dp_link_down(intel_output, dp_priv->DP);
977 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
978 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
982 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
984 * \return true if DP port is connected.
985 * \return false if DP port is disconnected.
987 static enum drm_connector_status
988 intel_dp_detect(struct drm_connector *connector)
990 struct intel_output *intel_output = to_intel_output(connector);
991 struct drm_device *dev = intel_output->base.dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
995 enum drm_connector_status status;
997 dp_priv->has_audio = false;
999 temp = I915_READ(PORT_HOTPLUG_EN);
1001 I915_WRITE(PORT_HOTPLUG_EN,
1003 DPB_HOTPLUG_INT_EN |
1004 DPC_HOTPLUG_INT_EN |
1005 DPD_HOTPLUG_INT_EN);
1007 POSTING_READ(PORT_HOTPLUG_EN);
1009 switch (dp_priv->output_reg) {
1011 bit = DPB_HOTPLUG_INT_STATUS;
1014 bit = DPC_HOTPLUG_INT_STATUS;
1017 bit = DPD_HOTPLUG_INT_STATUS;
1020 return connector_status_unknown;
1023 temp = I915_READ(PORT_HOTPLUG_STAT);
1025 if ((temp & bit) == 0)
1026 return connector_status_disconnected;
1028 status = connector_status_disconnected;
1029 if (intel_dp_aux_native_read(intel_output,
1030 0x000, dp_priv->dpcd,
1031 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1033 if (dp_priv->dpcd[0] != 0)
1034 status = connector_status_connected;
1039 static int intel_dp_get_modes(struct drm_connector *connector)
1041 struct intel_output *intel_output = to_intel_output(connector);
1043 /* We should parse the EDID data and find out if it has an audio sink
1046 return intel_ddc_get_modes(intel_output);
1050 intel_dp_destroy (struct drm_connector *connector)
1052 struct intel_output *intel_output = to_intel_output(connector);
1054 if (intel_output->i2c_bus)
1055 intel_i2c_destroy(intel_output->i2c_bus);
1056 drm_sysfs_connector_remove(connector);
1057 drm_connector_cleanup(connector);
1058 kfree(intel_output);
1061 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1062 .dpms = intel_dp_dpms,
1063 .mode_fixup = intel_dp_mode_fixup,
1064 .prepare = intel_encoder_prepare,
1065 .mode_set = intel_dp_mode_set,
1066 .commit = intel_encoder_commit,
1069 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1070 .dpms = drm_helper_connector_dpms,
1071 .save = intel_dp_save,
1072 .restore = intel_dp_restore,
1073 .detect = intel_dp_detect,
1074 .fill_modes = drm_helper_probe_single_connector_modes,
1075 .destroy = intel_dp_destroy,
1078 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1079 .get_modes = intel_dp_get_modes,
1080 .mode_valid = intel_dp_mode_valid,
1081 .best_encoder = intel_best_encoder,
1084 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1086 drm_encoder_cleanup(encoder);
1089 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1090 .destroy = intel_dp_enc_destroy,
1094 intel_dp_hot_plug(struct intel_output *intel_output)
1096 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1098 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1099 intel_dp_check_link_status(intel_output);
1103 intel_dp_init(struct drm_device *dev, int output_reg)
1105 struct drm_i915_private *dev_priv = dev->dev_private;
1106 struct drm_connector *connector;
1107 struct intel_output *intel_output;
1108 struct intel_dp_priv *dp_priv;
1110 intel_output = kcalloc(sizeof(struct intel_output) +
1111 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1115 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1117 connector = &intel_output->base;
1118 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1119 DRM_MODE_CONNECTOR_DisplayPort);
1120 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1122 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1124 connector->interlace_allowed = true;
1125 connector->doublescan_allowed = 0;
1127 dp_priv->intel_output = intel_output;
1128 dp_priv->output_reg = output_reg;
1129 dp_priv->has_audio = false;
1130 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1131 intel_output->dev_priv = dp_priv;
1133 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1134 DRM_MODE_ENCODER_TMDS);
1135 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1137 drm_mode_connector_attach_encoder(&intel_output->base,
1138 &intel_output->enc);
1139 drm_sysfs_connector_add(connector);
1141 /* Set up the DDC bus. */
1142 intel_dp_i2c_init(intel_output,
1143 (output_reg == DP_B) ? "DPDDC-B" :
1144 (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
1145 intel_output->ddc_bus = &dp_priv->adapter;
1146 intel_output->hot_plug = intel_dp_hot_plug;
1148 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1149 * 0xd. Failure to do so will result in spurious interrupts being
1150 * generated on the port when a cable is not attached.
1152 if (IS_G4X(dev) && !IS_GM45(dev)) {
1153 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1154 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);