drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         uint8_t link_bw;
  54         uint8_t lane_count;
  55         uint8_t dpcd[4];
  56         struct i2c_adapter adapter;
  57         struct i2c_algo_dp_aux_data algo;
  58         bool is_pch_edp;
  59         uint8_t train_set[4];
  60         uint8_t link_status[DP_LINK_STATUS_SIZE];
  61 };
  62
  63 /**
  64  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  65  * @intel_dp: DP struct
  66  *
  67  * If a CPU or PCH DP output is attached to an eDP panel, this function
  68  * will return true, and false otherwise.
  69  */
  70 static bool is_edp(struct intel_dp *intel_dp)
  71 {
  72         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  73 }
  74
  75 /**
  76  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  77  * @intel_dp: DP struct
  78  *
  79  * Returns true if the given DP struct corresponds to a PCH DP port attached
  80  * to an eDP panel, false otherwise.  Helpful for determining whether we
  81  * may need FDI resources for a given DP output or not.
  82  */
  83 static bool is_pch_edp(struct intel_dp *intel_dp)
  84 {
  85         return intel_dp->is_pch_edp;
  86 }
  87
  88 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  89 {
  90         return container_of(encoder, struct intel_dp, base.base);
  91 }
  92
  93 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  94 {
  95         return container_of(intel_attached_encoder(connector),
  96                             struct intel_dp, base);
  97 }
  98
  99 /**
 100  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 101  * @encoder: DRM encoder
 102  *
 103  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 104  * by intel_display.c.
 105  */
 106 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 107 {
 108         struct intel_dp *intel_dp;
 109
 110         if (!encoder)
 111                 return false;
 112
 113         intel_dp = enc_to_intel_dp(encoder);
 114
 115         return is_pch_edp(intel_dp);
 116 }
 117
 118 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 119 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 120 static void intel_dp_link_down(struct intel_dp *intel_dp);
 121
 122 void
 123 intel_edp_link_config (struct intel_encoder *intel_encoder,
 124                        int *lane_num, int *link_bw)
 125 {
 126         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 127
 128         *lane_num = intel_dp->lane_count;
 129         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 130                 *link_bw = 162000;
 131         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 132                 *link_bw = 270000;
 133 }
 134
 135 static int
 136 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 137 {
 138         int max_lane_count = 4;
 139
 140         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 141                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 142                 switch (max_lane_count) {
 143                 case 1: case 2: case 4:
 144                         break;
 145                 default:
 146                         max_lane_count = 4;
 147                 }
 148         }
 149         return max_lane_count;
 150 }
 151
 152 static int
 153 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 154 {
 155         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 156
 157         switch (max_link_bw) {
 158         case DP_LINK_BW_1_62:
 159         case DP_LINK_BW_2_7:
 160                 break;
 161         default:
 162                 max_link_bw = DP_LINK_BW_1_62;
 163                 break;
 164         }
 165         return max_link_bw;
 166 }
 167
 168 static int
 169 intel_dp_link_clock(uint8_t link_bw)
 170 {
 171         if (link_bw == DP_LINK_BW_2_7)
 172                 return 270000;
 173         else
 174                 return 162000;
 175 }
 176
 177 /* I think this is a fiction */
 178 static int
 179 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 180 {
 181         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 183         int bpp = 24;
 184
 185         if (intel_crtc)
 186                 bpp = intel_crtc->bpp;
 187
 188         return (pixel_clock * bpp + 7) / 8;
 189 }
 190
 191 static int
 192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 193 {
 194         return (max_link_clock * max_lanes * 8) / 10;
 195 }
 196
 197 static int
 198 intel_dp_mode_valid(struct drm_connector *connector,
 199                     struct drm_display_mode *mode)
 200 {
 201         struct intel_dp *intel_dp = intel_attached_dp(connector);
 202         struct drm_device *dev = connector->dev;
 203         struct drm_i915_private *dev_priv = dev->dev_private;
 204         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 205         int max_lanes = intel_dp_max_lane_count(intel_dp);
 206
 207         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 208                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 209                         return MODE_PANEL;
 210
 211                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 212                         return MODE_PANEL;
 213         }
 214
 215         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 216            which are outside spec tolerances but somehow work by magic */
 217         if (!is_edp(intel_dp) &&
 218             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 219              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 220                 return MODE_CLOCK_HIGH;
 221
 222         if (mode->clock < 10000)
 223                 return MODE_CLOCK_LOW;
 224
 225         return MODE_OK;
 226 }
 227
 228 static uint32_t
 229 pack_aux(uint8_t *src, int src_bytes)
 230 {
 231         int     i;
 232         uint32_t v = 0;
 233
 234         if (src_bytes > 4)
 235                 src_bytes = 4;
 236         for (i = 0; i < src_bytes; i++)
 237                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 238         return v;
 239 }
 240
 241 static void
 242 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 243 {
 244         int i;
 245         if (dst_bytes > 4)
 246                 dst_bytes = 4;
 247         for (i = 0; i < dst_bytes; i++)
 248                 dst[i] = src >> ((3-i) * 8);
 249 }
 250
 251 /* hrawclock is 1/4 the FSB frequency */
 252 static int
 253 intel_hrawclk(struct drm_device *dev)
 254 {
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         uint32_t clkcfg;
 257
 258         clkcfg = I915_READ(CLKCFG);
 259         switch (clkcfg & CLKCFG_FSB_MASK) {
 260         case CLKCFG_FSB_400:
 261                 return 100;
 262         case CLKCFG_FSB_533:
 263                 return 133;
 264         case CLKCFG_FSB_667:
 265                 return 166;
 266         case CLKCFG_FSB_800:
 267                 return 200;
 268         case CLKCFG_FSB_1067:
 269                 return 266;
 270         case CLKCFG_FSB_1333:
 271                 return 333;
 272         /* these two are just a guess; one of them might be right */
 273         case CLKCFG_FSB_1600:
 274         case CLKCFG_FSB_1600_ALT:
 275                 return 400;
 276         default:
 277                 return 133;
 278         }
 279 }
 280
 281 static int
 282 intel_dp_aux_ch(struct intel_dp *intel_dp,
 283                 uint8_t *send, int send_bytes,
 284                 uint8_t *recv, int recv_size)
 285 {
 286         uint32_t output_reg = intel_dp->output_reg;
 287         struct drm_device *dev = intel_dp->base.base.dev;
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         uint32_t ch_ctl = output_reg + 0x10;
 290         uint32_t ch_data = ch_ctl + 4;
 291         int i;
 292         int recv_bytes;
 293         uint32_t status;
 294         uint32_t aux_clock_divider;
 295         int try, precharge;
 296
 297         /* The clock divider is based off the hrawclk,
 298          * and would like to run at 2MHz. So, take the
 299          * hrawclk value and divide by 2 and use that
 300          *
 301          * Note that PCH attached eDP panels should use a 125MHz input
 302          * clock divider.
 303          */
 304         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 305                 if (IS_GEN6(dev))
 306                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 307                 else
 308                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 309         } else if (HAS_PCH_SPLIT(dev))
 310                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 311         else
 312                 aux_clock_divider = intel_hrawclk(dev) / 2;
 313
 314         if (IS_GEN6(dev))
 315                 precharge = 3;
 316         else
 317                 precharge = 5;
 318
 319         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 320                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 321                           I915_READ(ch_ctl));
 322                 return -EBUSY;
 323         }
 324
 325         /* Must try at least 3 times according to DP spec */
 326         for (try = 0; try < 5; try++) {
 327                 /* Load the send data into the aux channel data registers */
 328                 for (i = 0; i < send_bytes; i += 4)
 329                         I915_WRITE(ch_data + i,
 330                                    pack_aux(send + i, send_bytes - i));
 331
 332                 /* Send the command and wait for it to complete */
 333                 I915_WRITE(ch_ctl,
 334                            DP_AUX_CH_CTL_SEND_BUSY |
 335                            DP_AUX_CH_CTL_TIME_OUT_400us |
 336                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 337                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 338                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 339                            DP_AUX_CH_CTL_DONE |
 340                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 341                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 342                 for (;;) {
 343                         status = I915_READ(ch_ctl);
 344                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 345                                 break;
 346                         udelay(100);
 347                 }
 348
 349                 /* Clear done status and any errors */
 350                 I915_WRITE(ch_ctl,
 351                            status |
 352                            DP_AUX_CH_CTL_DONE |
 353                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 354                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 355                 if (status & DP_AUX_CH_CTL_DONE)
 356                         break;
 357         }
 358
 359         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 360                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 361                 return -EBUSY;
 362         }
 363
 364         /* Check for timeout or receive error.
 365          * Timeouts occur when the sink is not connected
 366          */
 367         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 368                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 369                 return -EIO;
 370         }
 371
 372         /* Timeouts occur when the device isn't connected, so they're
 373          * "normal" -- don't fill the kernel log with these */
 374         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 375                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 376                 return -ETIMEDOUT;
 377         }
 378
 379         /* Unload any bytes sent back from the other side */
 380         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 381                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 382         if (recv_bytes > recv_size)
 383                 recv_bytes = recv_size;
 384
 385         for (i = 0; i < recv_bytes; i += 4)
 386                 unpack_aux(I915_READ(ch_data + i),
 387                            recv + i, recv_bytes - i);
 388
 389         return recv_bytes;
 390 }
 391
 392 /* Write data to the aux channel in native mode */
 393 static int
 394 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 395                           uint16_t address, uint8_t *send, int send_bytes)
 396 {
 397         int ret;
 398         uint8_t msg[20];
 399         int msg_bytes;
 400         uint8_t ack;
 401
 402         if (send_bytes > 16)
 403                 return -1;
 404         msg[0] = AUX_NATIVE_WRITE << 4;
 405         msg[1] = address >> 8;
 406         msg[2] = address & 0xff;
 407         msg[3] = send_bytes - 1;
 408         memcpy(&msg[4], send, send_bytes);
 409         msg_bytes = send_bytes + 4;
 410         for (;;) {
 411                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 412                 if (ret < 0)
 413                         return ret;
 414                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 415                         break;
 416                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 417                         udelay(100);
 418                 else
 419                         return -EIO;
 420         }
 421         return send_bytes;
 422 }
 423
 424 /* Write a single byte to the aux channel in native mode */
 425 static int
 426 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 427                             uint16_t address, uint8_t byte)
 428 {
 429         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 430 }
 431
 432 /* read bytes from a native aux channel */
 433 static int
 434 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 435                          uint16_t address, uint8_t *recv, int recv_bytes)
 436 {
 437         uint8_t msg[4];
 438         int msg_bytes;
 439         uint8_t reply[20];
 440         int reply_bytes;
 441         uint8_t ack;
 442         int ret;
 443
 444         msg[0] = AUX_NATIVE_READ << 4;
 445         msg[1] = address >> 8;
 446         msg[2] = address & 0xff;
 447         msg[3] = recv_bytes - 1;
 448
 449         msg_bytes = 4;
 450         reply_bytes = recv_bytes + 1;
 451
 452         for (;;) {
 453                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 454                                       reply, reply_bytes);
 455                 if (ret == 0)
 456                         return -EPROTO;
 457                 if (ret < 0)
 458                         return ret;
 459                 ack = reply[0];
 460                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 461                         memcpy(recv, reply + 1, ret - 1);
 462                         return ret - 1;
 463                 }
 464                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 465                         udelay(100);
 466                 else
 467                         return -EIO;
 468         }
 469 }
 470
 471 static int
 472 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 473                     uint8_t write_byte, uint8_t *read_byte)
 474 {
 475         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 476         struct intel_dp *intel_dp = container_of(adapter,
 477                                                 struct intel_dp,
 478                                                 adapter);
 479         uint16_t address = algo_data->address;
 480         uint8_t msg[5];
 481         uint8_t reply[2];
 482         unsigned retry;
 483         int msg_bytes;
 484         int reply_bytes;
 485         int ret;
 486
 487         /* Set up the command byte */
 488         if (mode & MODE_I2C_READ)
 489                 msg[0] = AUX_I2C_READ << 4;
 490         else
 491                 msg[0] = AUX_I2C_WRITE << 4;
 492
 493         if (!(mode & MODE_I2C_STOP))
 494                 msg[0] |= AUX_I2C_MOT << 4;
 495
 496         msg[1] = address >> 8;
 497         msg[2] = address;
 498
 499         switch (mode) {
 500         case MODE_I2C_WRITE:
 501                 msg[3] = 0;
 502                 msg[4] = write_byte;
 503                 msg_bytes = 5;
 504                 reply_bytes = 1;
 505                 break;
 506         case MODE_I2C_READ:
 507                 msg[3] = 0;
 508                 msg_bytes = 4;
 509                 reply_bytes = 2;
 510                 break;
 511         default:
 512                 msg_bytes = 3;
 513                 reply_bytes = 1;
 514                 break;
 515         }
 516
 517         for (retry = 0; retry < 5; retry++) {
 518                 ret = intel_dp_aux_ch(intel_dp,
 519                                       msg, msg_bytes,
 520                                       reply, reply_bytes);
 521                 if (ret < 0) {
 522                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 523                         return ret;
 524                 }
 525
 526                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 527                 case AUX_NATIVE_REPLY_ACK:
 528                         /* I2C-over-AUX Reply field is only valid
 529                          * when paired with AUX ACK.
 530                          */
 531                         break;
 532                 case AUX_NATIVE_REPLY_NACK:
 533                         DRM_DEBUG_KMS("aux_ch native nack\n");
 534                         return -EREMOTEIO;
 535                 case AUX_NATIVE_REPLY_DEFER:
 536                         udelay(100);
 537                         continue;
 538                 default:
 539                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 540                                   reply[0]);
 541                         return -EREMOTEIO;
 542                 }
 543
 544                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 545                 case AUX_I2C_REPLY_ACK:
 546                         if (mode == MODE_I2C_READ) {
 547                                 *read_byte = reply[1];
 548                         }
 549                         return reply_bytes - 1;
 550                 case AUX_I2C_REPLY_NACK:
 551                         DRM_DEBUG_KMS("aux_i2c nack\n");
 552                         return -EREMOTEIO;
 553                 case AUX_I2C_REPLY_DEFER:
 554                         DRM_DEBUG_KMS("aux_i2c defer\n");
 555                         udelay(100);
 556                         break;
 557                 default:
 558                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 559                         return -EREMOTEIO;
 560                 }
 561         }
 562
 563         DRM_ERROR("too many retries, giving up\n");
 564         return -EREMOTEIO;
 565 }
 566
 567 static int
 568 intel_dp_i2c_init(struct intel_dp *intel_dp,
 569                   struct intel_connector *intel_connector, const char *name)
 570 {
 571         DRM_DEBUG_KMS("i2c_init %s\n", name);
 572         intel_dp->algo.running = false;
 573         intel_dp->algo.address = 0;
 574         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 575
 576         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 577         intel_dp->adapter.owner = THIS_MODULE;
 578         intel_dp->adapter.class = I2C_CLASS_DDC;
 579         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 580         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 581         intel_dp->adapter.algo_data = &intel_dp->algo;
 582         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 583
 584         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 585 }
 586
 587 static bool
 588 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 589                     struct drm_display_mode *adjusted_mode)
 590 {
 591         struct drm_device *dev = encoder->dev;
 592         struct drm_i915_private *dev_priv = dev->dev_private;
 593         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 594         int lane_count, clock;
 595         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 596         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 597         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 598
 599         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 600                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 601                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 602                                         mode, adjusted_mode);
 603                 /*
 604                  * the mode->clock is used to calculate the Data&Link M/N
 605                  * of the pipe. For the eDP the fixed clock should be used.
 606                  */
 607                 mode->clock = dev_priv->panel_fixed_mode->clock;
 608         }
 609
 610         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 611                 for (clock = 0; clock <= max_clock; clock++) {
 612                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 613
 614                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 615                                         <= link_avail) {
 616                                 intel_dp->link_bw = bws[clock];
 617                                 intel_dp->lane_count = lane_count;
 618                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 619                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 620                                                 "count %d clock %d\n",
 621                                        intel_dp->link_bw, intel_dp->lane_count,
 622                                        adjusted_mode->clock);
 623                                 return true;
 624                         }
 625                 }
 626         }
 627
 628         if (is_edp(intel_dp)) {
 629                 /* okay we failed just pick the highest */
 630                 intel_dp->lane_count = max_lane_count;
 631                 intel_dp->link_bw = bws[max_clock];
 632                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 633                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 634                               "count %d clock %d\n",
 635                               intel_dp->link_bw, intel_dp->lane_count,
 636                               adjusted_mode->clock);
 637
 638                 return true;
 639         }
 640
 641         return false;
 642 }
 643
 644 struct intel_dp_m_n {
 645         uint32_t        tu;
 646         uint32_t        gmch_m;
 647         uint32_t        gmch_n;
 648         uint32_t        link_m;
 649         uint32_t        link_n;
 650 };
 651
 652 static void
 653 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 654 {
 655         while (*num > 0xffffff || *den > 0xffffff) {
 656                 *num >>= 1;
 657                 *den >>= 1;
 658         }
 659 }
 660
 661 static void
 662 intel_dp_compute_m_n(int bpp,
 663                      int nlanes,
 664                      int pixel_clock,
 665                      int link_clock,
 666                      struct intel_dp_m_n *m_n)
 667 {
 668         m_n->tu = 64;
 669         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 670         m_n->gmch_n = link_clock * nlanes;
 671         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 672         m_n->link_m = pixel_clock;
 673         m_n->link_n = link_clock;
 674         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 675 }
 676
 677 void
 678 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 679                  struct drm_display_mode *adjusted_mode)
 680 {
 681         struct drm_device *dev = crtc->dev;
 682         struct drm_mode_config *mode_config = &dev->mode_config;
 683         struct drm_encoder *encoder;
 684         struct drm_i915_private *dev_priv = dev->dev_private;
 685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 686         int lane_count = 4;
 687         struct intel_dp_m_n m_n;
 688         int pipe = intel_crtc->pipe;
 689
 690         /*
 691          * Find the lane count in the intel_encoder private
 692          */
 693         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 694                 struct intel_dp *intel_dp;
 695
 696                 if (encoder->crtc != crtc)
 697                         continue;
 698
 699                 intel_dp = enc_to_intel_dp(encoder);
 700                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 701                         lane_count = intel_dp->lane_count;
 702                         break;
 703                 } else if (is_edp(intel_dp)) {
 704                         lane_count = dev_priv->edp.lanes;
 705                         break;
 706                 }
 707         }
 708
 709         /*
 710          * Compute the GMCH and Link ratios. The '3' here is
 711          * the number of bytes_per_pixel post-LUT, which we always
 712          * set up for 8-bits of R/G/B, or 3 bytes total.
 713          */
 714         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 715                              mode->clock, adjusted_mode->clock, &m_n);
 716
 717         if (HAS_PCH_SPLIT(dev)) {
 718                 I915_WRITE(TRANSDATA_M1(pipe),
 719                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 720                            m_n.gmch_m);
 721                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 722                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 723                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 724         } else {
 725                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 726                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 727                            m_n.gmch_m);
 728                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 729                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 730                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 731         }
 732 }
 733
 734 static void
 735 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 736                   struct drm_display_mode *adjusted_mode)
 737 {
 738         struct drm_device *dev = encoder->dev;
 739         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 740         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 742
 743         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 744         intel_dp->DP |= intel_dp->color_range;
 745
 746         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 747                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 748         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 749                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 750
 751         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 752                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 753         else
 754                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 755
 756         switch (intel_dp->lane_count) {
 757         case 1:
 758                 intel_dp->DP |= DP_PORT_WIDTH_1;
 759                 break;
 760         case 2:
 761                 intel_dp->DP |= DP_PORT_WIDTH_2;
 762                 break;
 763         case 4:
 764                 intel_dp->DP |= DP_PORT_WIDTH_4;
 765                 break;
 766         }
 767         if (intel_dp->has_audio)
 768                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 769
 770         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 771         intel_dp->link_configuration[0] = intel_dp->link_bw;
 772         intel_dp->link_configuration[1] = intel_dp->lane_count;
 773
 774         /*
 775          * Check for DPCD version > 1.1 and enhanced framing support
 776          */
 777         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 778             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 779                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 780                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 781         }
 782
 783         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 784         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 785                 intel_dp->DP |= DP_PIPEB_SELECT;
 786
 787         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 788                 /* don't miss out required setting for eDP */
 789                 intel_dp->DP |= DP_PLL_ENABLE;
 790                 if (adjusted_mode->clock < 200000)
 791                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 792                 else
 793                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 794         }
 795 }
 796
 797 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 798 {
 799         struct drm_device *dev = intel_dp->base.base.dev;
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         u32 pp;
 802
 803         /*
 804          * If the panel wasn't on, make sure there's not a currently
 805          * active PP sequence before enabling AUX VDD.
 806          */
 807         if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
 808                 msleep(dev_priv->panel_t3);
 809
 810         pp = I915_READ(PCH_PP_CONTROL);
 811         pp |= EDP_FORCE_VDD;
 812         I915_WRITE(PCH_PP_CONTROL, pp);
 813         POSTING_READ(PCH_PP_CONTROL);
 814 }
 815
 816 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 817 {
 818         struct drm_device *dev = intel_dp->base.base.dev;
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         u32 pp;
 821
 822         pp = I915_READ(PCH_PP_CONTROL);
 823         pp &= ~EDP_FORCE_VDD;
 824         I915_WRITE(PCH_PP_CONTROL, pp);
 825         POSTING_READ(PCH_PP_CONTROL);
 826
 827         /* Make sure sequencer is idle before allowing subsequent activity */
 828         msleep(dev_priv->panel_t12);
 829 }
 830
 831 /* Returns true if the panel was already on when called */
 832 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 833 {
 834         struct drm_device *dev = intel_dp->base.base.dev;
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 837
 838         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 839                 return true;
 840
 841         pp = I915_READ(PCH_PP_CONTROL);
 842
 843         /* ILK workaround: disable reset around power sequence */
 844         pp &= ~PANEL_POWER_RESET;
 845         I915_WRITE(PCH_PP_CONTROL, pp);
 846         POSTING_READ(PCH_PP_CONTROL);
 847
 848         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 849         I915_WRITE(PCH_PP_CONTROL, pp);
 850         POSTING_READ(PCH_PP_CONTROL);
 851
 852         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 853                      5000))
 854                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 855                           I915_READ(PCH_PP_STATUS));
 856
 857         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 858         I915_WRITE(PCH_PP_CONTROL, pp);
 859         POSTING_READ(PCH_PP_CONTROL);
 860
 861         return false;
 862 }
 863
 864 static void ironlake_edp_panel_off (struct drm_device *dev)
 865 {
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 868                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 869
 870         pp = I915_READ(PCH_PP_CONTROL);
 871
 872         /* ILK workaround: disable reset around power sequence */
 873         pp &= ~PANEL_POWER_RESET;
 874         I915_WRITE(PCH_PP_CONTROL, pp);
 875         POSTING_READ(PCH_PP_CONTROL);
 876
 877         pp &= ~POWER_TARGET_ON;
 878         I915_WRITE(PCH_PP_CONTROL, pp);
 879         POSTING_READ(PCH_PP_CONTROL);
 880
 881         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 882                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 883                           I915_READ(PCH_PP_STATUS));
 884
 885         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 886         I915_WRITE(PCH_PP_CONTROL, pp);
 887         POSTING_READ(PCH_PP_CONTROL);
 888 }
 889
 890 static void ironlake_edp_backlight_on (struct drm_device *dev)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 pp;
 894
 895         DRM_DEBUG_KMS("\n");
 896         /*
 897          * If we enable the backlight right away following a panel power
 898          * on, we may see slight flicker as the panel syncs with the eDP
 899          * link.  So delay a bit to make sure the image is solid before
 900          * allowing it to appear.
 901          */
 902         msleep(300);
 903         pp = I915_READ(PCH_PP_CONTROL);
 904         pp |= EDP_BLC_ENABLE;
 905         I915_WRITE(PCH_PP_CONTROL, pp);
 906 }
 907
 908 static void ironlake_edp_backlight_off (struct drm_device *dev)
 909 {
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         u32 pp;
 912
 913         DRM_DEBUG_KMS("\n");
 914         pp = I915_READ(PCH_PP_CONTROL);
 915         pp &= ~EDP_BLC_ENABLE;
 916         I915_WRITE(PCH_PP_CONTROL, pp);
 917 }
 918
 919 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 920 {
 921         struct drm_device *dev = encoder->dev;
 922         struct drm_i915_private *dev_priv = dev->dev_private;
 923         u32 dpa_ctl;
 924
 925         DRM_DEBUG_KMS("\n");
 926         dpa_ctl = I915_READ(DP_A);
 927         dpa_ctl |= DP_PLL_ENABLE;
 928         I915_WRITE(DP_A, dpa_ctl);
 929         POSTING_READ(DP_A);
 930         udelay(200);
 931 }
 932
 933 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 934 {
 935         struct drm_device *dev = encoder->dev;
 936         struct drm_i915_private *dev_priv = dev->dev_private;
 937         u32 dpa_ctl;
 938
 939         dpa_ctl = I915_READ(DP_A);
 940         dpa_ctl &= ~DP_PLL_ENABLE;
 941         I915_WRITE(DP_A, dpa_ctl);
 942         POSTING_READ(DP_A);
 943         udelay(200);
 944 }
 945
 946 /* If the sink supports it, try to set the power state appropriately */
 947 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 948 {
 949         int ret, i;
 950
 951         /* Should have a valid DPCD by this point */
 952         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
 953                 return;
 954
 955         if (mode != DRM_MODE_DPMS_ON) {
 956                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
 957                                                   DP_SET_POWER_D3);
 958                 if (ret != 1)
 959                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
 960         } else {
 961                 /*
 962                  * When turning on, we need to retry for 1ms to give the sink
 963                  * time to wake up.
 964                  */
 965                 for (i = 0; i < 3; i++) {
 966                         ret = intel_dp_aux_native_write_1(intel_dp,
 967                                                           DP_SET_POWER,
 968                                                           DP_SET_POWER_D0);
 969                         if (ret == 1)
 970                                 break;
 971                         msleep(1);
 972                 }
 973         }
 974 }
 975
 976 static void intel_dp_prepare(struct drm_encoder *encoder)
 977 {
 978         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 979         struct drm_device *dev = encoder->dev;
 980
 981         /* Wake up the sink first */
 982         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 983
 984         if (is_edp(intel_dp)) {
 985                 ironlake_edp_backlight_off(dev);
 986                 ironlake_edp_panel_off(dev);
 987                 if (!is_pch_edp(intel_dp))
 988                         ironlake_edp_pll_on(encoder);
 989                 else
 990                         ironlake_edp_pll_off(encoder);
 991         }
 992         intel_dp_link_down(intel_dp);
 993 }
 994
 995 static void intel_dp_commit(struct drm_encoder *encoder)
 996 {
 997         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 998         struct drm_device *dev = encoder->dev;
 999
1000         if (is_edp(intel_dp))
1001                 ironlake_edp_panel_vdd_on(intel_dp);
1002
1003         intel_dp_start_link_train(intel_dp);
1004
1005         if (is_edp(intel_dp)) {
1006                 ironlake_edp_panel_on(intel_dp);
1007                 ironlake_edp_panel_vdd_off(intel_dp);
1008         }
1009
1010         intel_dp_complete_link_train(intel_dp);
1011
1012         if (is_edp(intel_dp))
1013                 ironlake_edp_backlight_on(dev);
1014 }
1015
1016 static void
1017 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1018 {
1019         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1020         struct drm_device *dev = encoder->dev;
1021         struct drm_i915_private *dev_priv = dev->dev_private;
1022         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1023
1024         if (mode != DRM_MODE_DPMS_ON) {
1025                 if (is_edp(intel_dp))
1026                         ironlake_edp_backlight_off(dev);
1027                 intel_dp_sink_dpms(intel_dp, mode);
1028                 intel_dp_link_down(intel_dp);
1029                 if (is_edp(intel_dp))
1030                         ironlake_edp_panel_off(dev);
1031                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1032                         ironlake_edp_pll_off(encoder);
1033         } else {
1034                 if (is_edp(intel_dp))
1035                         ironlake_edp_panel_vdd_on(intel_dp);
1036                 intel_dp_sink_dpms(intel_dp, mode);
1037                 if (!(dp_reg & DP_PORT_EN)) {
1038                         intel_dp_start_link_train(intel_dp);
1039                         if (is_edp(intel_dp)) {
1040                                 ironlake_edp_panel_on(intel_dp);
1041                                 ironlake_edp_panel_vdd_off(intel_dp);
1042                         }
1043                         intel_dp_complete_link_train(intel_dp);
1044                 }
1045                 if (is_edp(intel_dp))
1046                         ironlake_edp_backlight_on(dev);
1047         }
1048 }
1049
1050 /*
1051  * Native read with retry for link status and receiver capability reads for
1052  * cases where the sink may still be asleep.
1053  */
1054 static bool
1055 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1056                                uint8_t *recv, int recv_bytes)
1057 {
1058         int ret, i;
1059
1060         /*
1061          * Sinks are *supposed* to come up within 1ms from an off state,
1062          * but we're also supposed to retry 3 times per the spec.
1063          */
1064         for (i = 0; i < 3; i++) {
1065                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1066                                                recv_bytes);
1067                 if (ret == recv_bytes)
1068                         return true;
1069                 msleep(1);
1070         }
1071
1072         return false;
1073 }
1074
1075 /*
1076  * Fetch AUX CH registers 0x202 - 0x207 which contain
1077  * link status information
1078  */
1079 static bool
1080 intel_dp_get_link_status(struct intel_dp *intel_dp)
1081 {
1082         return intel_dp_aux_native_read_retry(intel_dp,
1083                                               DP_LANE0_1_STATUS,
1084                                               intel_dp->link_status,
1085                                               DP_LINK_STATUS_SIZE);
1086 }
1087
1088 static uint8_t
1089 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1090                      int r)
1091 {
1092         return link_status[r - DP_LANE0_1_STATUS];
1093 }
1094
1095 static uint8_t
1096 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1097                                  int lane)
1098 {
1099         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1100         int         s = ((lane & 1) ?
1101                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1102                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1103         uint8_t l = intel_dp_link_status(link_status, i);
1104
1105         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1106 }
1107
1108 static uint8_t
1109 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1110                                       int lane)
1111 {
1112         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1113         int         s = ((lane & 1) ?
1114                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1115                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1116         uint8_t l = intel_dp_link_status(link_status, i);
1117
1118         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1119 }
1120
1121
1122 #if 0
1123 static char     *voltage_names[] = {
1124         "0.4V", "0.6V", "0.8V", "1.2V"
1125 };
1126 static char     *pre_emph_names[] = {
1127         "0dB", "3.5dB", "6dB", "9.5dB"
1128 };
1129 static char     *link_train_names[] = {
1130         "pattern 1", "pattern 2", "idle", "off"
1131 };
1132 #endif
1133
1134 /*
1135  * These are source-specific values; current Intel hardware supports
1136  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1137  */
1138 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1139
1140 static uint8_t
1141 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1142 {
1143         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1144         case DP_TRAIN_VOLTAGE_SWING_400:
1145                 return DP_TRAIN_PRE_EMPHASIS_6;
1146         case DP_TRAIN_VOLTAGE_SWING_600:
1147                 return DP_TRAIN_PRE_EMPHASIS_6;
1148         case DP_TRAIN_VOLTAGE_SWING_800:
1149                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1150         case DP_TRAIN_VOLTAGE_SWING_1200:
1151         default:
1152                 return DP_TRAIN_PRE_EMPHASIS_0;
1153         }
1154 }
1155
1156 static void
1157 intel_get_adjust_train(struct intel_dp *intel_dp)
1158 {
1159         uint8_t v = 0;
1160         uint8_t p = 0;
1161         int lane;
1162
1163         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1164                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1165                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1166
1167                 if (this_v > v)
1168                         v = this_v;
1169                 if (this_p > p)
1170                         p = this_p;
1171         }
1172
1173         if (v >= I830_DP_VOLTAGE_MAX)
1174                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1175
1176         if (p >= intel_dp_pre_emphasis_max(v))
1177                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1178
1179         for (lane = 0; lane < 4; lane++)
1180                 intel_dp->train_set[lane] = v | p;
1181 }
1182
1183 static uint32_t
1184 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1185 {
1186         uint32_t        signal_levels = 0;
1187
1188         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1189         case DP_TRAIN_VOLTAGE_SWING_400:
1190         default:
1191                 signal_levels |= DP_VOLTAGE_0_4;
1192                 break;
1193         case DP_TRAIN_VOLTAGE_SWING_600:
1194                 signal_levels |= DP_VOLTAGE_0_6;
1195                 break;
1196         case DP_TRAIN_VOLTAGE_SWING_800:
1197                 signal_levels |= DP_VOLTAGE_0_8;
1198                 break;
1199         case DP_TRAIN_VOLTAGE_SWING_1200:
1200                 signal_levels |= DP_VOLTAGE_1_2;
1201                 break;
1202         }
1203         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1204         case DP_TRAIN_PRE_EMPHASIS_0:
1205         default:
1206                 signal_levels |= DP_PRE_EMPHASIS_0;
1207                 break;
1208         case DP_TRAIN_PRE_EMPHASIS_3_5:
1209                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1210                 break;
1211         case DP_TRAIN_PRE_EMPHASIS_6:
1212                 signal_levels |= DP_PRE_EMPHASIS_6;
1213                 break;
1214         case DP_TRAIN_PRE_EMPHASIS_9_5:
1215                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1216                 break;
1217         }
1218         return signal_levels;
1219 }
1220
1221 /* Gen6's DP voltage swing and pre-emphasis control */
1222 static uint32_t
1223 intel_gen6_edp_signal_levels(uint8_t train_set)
1224 {
1225         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1226                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1227         switch (signal_levels) {
1228         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1229         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1230                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1231         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1232                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1233         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1234         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1235                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1236         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1237         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1238                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1239         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1240         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1241                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1242         default:
1243                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1244                               "0x%x\n", signal_levels);
1245                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1246         }
1247 }
1248
1249 static uint8_t
1250 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1251                       int lane)
1252 {
1253         int i = DP_LANE0_1_STATUS + (lane >> 1);
1254         int s = (lane & 1) * 4;
1255         uint8_t l = intel_dp_link_status(link_status, i);
1256
1257         return (l >> s) & 0xf;
1258 }
1259
1260 /* Check for clock recovery is done on all channels */
1261 static bool
1262 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1263 {
1264         int lane;
1265         uint8_t lane_status;
1266
1267         for (lane = 0; lane < lane_count; lane++) {
1268                 lane_status = intel_get_lane_status(link_status, lane);
1269                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1270                         return false;
1271         }
1272         return true;
1273 }
1274
1275 /* Check to see if channel eq is done on all channels */
1276 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1277                          DP_LANE_CHANNEL_EQ_DONE|\
1278                          DP_LANE_SYMBOL_LOCKED)
1279 static bool
1280 intel_channel_eq_ok(struct intel_dp *intel_dp)
1281 {
1282         uint8_t lane_align;
1283         uint8_t lane_status;
1284         int lane;
1285
1286         lane_align = intel_dp_link_status(intel_dp->link_status,
1287                                           DP_LANE_ALIGN_STATUS_UPDATED);
1288         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1289                 return false;
1290         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1291                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1292                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1293                         return false;
1294         }
1295         return true;
1296 }
1297
1298 static bool
1299 intel_dp_set_link_train(struct intel_dp *intel_dp,
1300                         uint32_t dp_reg_value,
1301                         uint8_t dp_train_pat)
1302 {
1303         struct drm_device *dev = intel_dp->base.base.dev;
1304         struct drm_i915_private *dev_priv = dev->dev_private;
1305         int ret;
1306
1307         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1308         POSTING_READ(intel_dp->output_reg);
1309
1310         intel_dp_aux_native_write_1(intel_dp,
1311                                     DP_TRAINING_PATTERN_SET,
1312                                     dp_train_pat);
1313
1314         ret = intel_dp_aux_native_write(intel_dp,
1315                                         DP_TRAINING_LANE0_SET,
1316                                         intel_dp->train_set, 4);
1317         if (ret != 4)
1318                 return false;
1319
1320         return true;
1321 }
1322
1323 /* Enable corresponding port and start training pattern 1 */
1324 static void
1325 intel_dp_start_link_train(struct intel_dp *intel_dp)
1326 {
1327         struct drm_device *dev = intel_dp->base.base.dev;
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1330         int i;
1331         uint8_t voltage;
1332         bool clock_recovery = false;
1333         int tries;
1334         u32 reg;
1335         uint32_t DP = intel_dp->DP;
1336
1337         /* Enable output, wait for it to become active */
1338         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1339         POSTING_READ(intel_dp->output_reg);
1340         intel_wait_for_vblank(dev, intel_crtc->pipe);
1341
1342         /* Write the link configuration data */
1343         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1344                                   intel_dp->link_configuration,
1345                                   DP_LINK_CONFIGURATION_SIZE);
1346
1347         DP |= DP_PORT_EN;
1348         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1349                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1350         else
1351                 DP &= ~DP_LINK_TRAIN_MASK;
1352         memset(intel_dp->train_set, 0, 4);
1353         voltage = 0xff;
1354         tries = 0;
1355         clock_recovery = false;
1356         for (;;) {
1357                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1358                 uint32_t    signal_levels;
1359                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1360                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1361                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1362                 } else {
1363                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1364                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1365                 }
1366
1367                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1368                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1369                 else
1370                         reg = DP | DP_LINK_TRAIN_PAT_1;
1371
1372                 if (!intel_dp_set_link_train(intel_dp, reg,
1373                                              DP_TRAINING_PATTERN_1))
1374                         break;
1375                 /* Set training pattern 1 */
1376
1377                 udelay(100);
1378                 if (!intel_dp_get_link_status(intel_dp))
1379                         break;
1380
1381                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1382                         clock_recovery = true;
1383                         break;
1384                 }
1385
1386                 /* Check to see if we've tried the max voltage */
1387                 for (i = 0; i < intel_dp->lane_count; i++)
1388                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1389                                 break;
1390                 if (i == intel_dp->lane_count)
1391                         break;
1392
1393                 /* Check to see if we've tried the same voltage 5 times */
1394                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1395                         ++tries;
1396                         if (tries == 5)
1397                                 break;
1398                 } else
1399                         tries = 0;
1400                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1401
1402                 /* Compute new intel_dp->train_set as requested by target */
1403                 intel_get_adjust_train(intel_dp);
1404         }
1405
1406         intel_dp->DP = DP;
1407 }
1408
1409 static void
1410 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1411 {
1412         struct drm_device *dev = intel_dp->base.base.dev;
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         bool channel_eq = false;
1415         int tries, cr_tries;
1416         u32 reg;
1417         uint32_t DP = intel_dp->DP;
1418
1419         /* channel equalization */
1420         tries = 0;
1421         cr_tries = 0;
1422         channel_eq = false;
1423         for (;;) {
1424                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1425                 uint32_t    signal_levels;
1426
1427                 if (cr_tries > 5) {
1428                         DRM_ERROR("failed to train DP, aborting\n");
1429                         intel_dp_link_down(intel_dp);
1430                         break;
1431                 }
1432
1433                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1434                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1435                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1436                 } else {
1437                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1438                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1439                 }
1440
1441                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1442                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1443                 else
1444                         reg = DP | DP_LINK_TRAIN_PAT_2;
1445
1446                 /* channel eq pattern */
1447                 if (!intel_dp_set_link_train(intel_dp, reg,
1448                                              DP_TRAINING_PATTERN_2))
1449                         break;
1450
1451                 udelay(400);
1452                 if (!intel_dp_get_link_status(intel_dp))
1453                         break;
1454
1455                 /* Make sure clock is still ok */
1456                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1457                         intel_dp_start_link_train(intel_dp);
1458                         cr_tries++;
1459                         continue;
1460                 }
1461
1462                 if (intel_channel_eq_ok(intel_dp)) {
1463                         channel_eq = true;
1464                         break;
1465                 }
1466
1467                 /* Try 5 times, then try clock recovery if that fails */
1468                 if (tries > 5) {
1469                         intel_dp_link_down(intel_dp);
1470                         intel_dp_start_link_train(intel_dp);
1471                         tries = 0;
1472                         cr_tries++;
1473                         continue;
1474                 }
1475
1476                 /* Compute new intel_dp->train_set as requested by target */
1477                 intel_get_adjust_train(intel_dp);
1478                 ++tries;
1479         }
1480
1481         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1482                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1483         else
1484                 reg = DP | DP_LINK_TRAIN_OFF;
1485
1486         I915_WRITE(intel_dp->output_reg, reg);
1487         POSTING_READ(intel_dp->output_reg);
1488         intel_dp_aux_native_write_1(intel_dp,
1489                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1490 }
1491
1492 static void
1493 intel_dp_link_down(struct intel_dp *intel_dp)
1494 {
1495         struct drm_device *dev = intel_dp->base.base.dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         uint32_t DP = intel_dp->DP;
1498
1499         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1500                 return;
1501
1502         DRM_DEBUG_KMS("\n");
1503
1504         if (is_edp(intel_dp)) {
1505                 DP &= ~DP_PLL_ENABLE;
1506                 I915_WRITE(intel_dp->output_reg, DP);
1507                 POSTING_READ(intel_dp->output_reg);
1508                 udelay(100);
1509         }
1510
1511         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1512                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1513                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1514         } else {
1515                 DP &= ~DP_LINK_TRAIN_MASK;
1516                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1517         }
1518         POSTING_READ(intel_dp->output_reg);
1519
1520         msleep(17);
1521
1522         if (is_edp(intel_dp))
1523                 DP |= DP_LINK_TRAIN_OFF;
1524
1525         if (!HAS_PCH_CPT(dev) &&
1526             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1527                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1528
1529                 /* Hardware workaround: leaving our transcoder select
1530                  * set to transcoder B while it's off will prevent the
1531                  * corresponding HDMI output on transcoder A.
1532                  *
1533                  * Combine this with another hardware workaround:
1534                  * transcoder select bit can only be cleared while the
1535                  * port is enabled.
1536                  */
1537                 DP &= ~DP_PIPEB_SELECT;
1538                 I915_WRITE(intel_dp->output_reg, DP);
1539
1540                 /* Changes to enable or select take place the vblank
1541                  * after being written.
1542                  */
1543                 if (crtc == NULL) {
1544                         /* We can arrive here never having been attached
1545                          * to a CRTC, for instance, due to inheriting
1546                          * random state from the BIOS.
1547                          *
1548                          * If the pipe is not running, play safe and
1549                          * wait for the clocks to stabilise before
1550                          * continuing.
1551                          */
1552                         POSTING_READ(intel_dp->output_reg);
1553                         msleep(50);
1554                 } else
1555                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1556         }
1557
1558         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1559         POSTING_READ(intel_dp->output_reg);
1560 }
1561
1562 /*
1563  * According to DP spec
1564  * 5.1.2:
1565  *  1. Read DPCD
1566  *  2. Configure link according to Receiver Capabilities
1567  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1568  *  4. Check link status on receipt of hot-plug interrupt
1569  */
1570
1571 static void
1572 intel_dp_check_link_status(struct intel_dp *intel_dp)
1573 {
1574         int ret;
1575
1576         if (!intel_dp->base.base.crtc)
1577                 return;
1578
1579         if (!intel_dp_get_link_status(intel_dp)) {
1580                 intel_dp_link_down(intel_dp);
1581                 return;
1582         }
1583
1584         /* Try to read receiver status if the link appears to be up */
1585         ret = intel_dp_aux_native_read(intel_dp,
1586                                        0x000, intel_dp->dpcd,
1587                                        sizeof (intel_dp->dpcd));
1588         if (ret != sizeof(intel_dp->dpcd)) {
1589                 intel_dp_link_down(intel_dp);
1590                 return;
1591         }
1592
1593         if (!intel_channel_eq_ok(intel_dp)) {
1594                 intel_dp_start_link_train(intel_dp);
1595                 intel_dp_complete_link_train(intel_dp);
1596         }
1597 }
1598
1599 static enum drm_connector_status
1600 ironlake_dp_detect(struct intel_dp *intel_dp)
1601 {
1602         enum drm_connector_status status;
1603         bool ret;
1604
1605         /* Can't disconnect eDP, but you can close the lid... */
1606         if (is_edp(intel_dp)) {
1607                 status = intel_panel_detect(intel_dp->base.base.dev);
1608                 if (status == connector_status_unknown)
1609                         status = connector_status_connected;
1610                 return status;
1611         }
1612
1613         status = connector_status_disconnected;
1614         ret = intel_dp_aux_native_read_retry(intel_dp,
1615                                              0x000, intel_dp->dpcd,
1616                                              sizeof (intel_dp->dpcd));
1617         if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
1618                 status = connector_status_connected;
1619         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1620                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1621         return status;
1622 }
1623
1624 static enum drm_connector_status
1625 g4x_dp_detect(struct intel_dp *intel_dp)
1626 {
1627         struct drm_device *dev = intel_dp->base.base.dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629         enum drm_connector_status status;
1630         uint32_t temp, bit;
1631
1632         switch (intel_dp->output_reg) {
1633         case DP_B:
1634                 bit = DPB_HOTPLUG_INT_STATUS;
1635                 break;
1636         case DP_C:
1637                 bit = DPC_HOTPLUG_INT_STATUS;
1638                 break;
1639         case DP_D:
1640                 bit = DPD_HOTPLUG_INT_STATUS;
1641                 break;
1642         default:
1643                 return connector_status_unknown;
1644         }
1645
1646         temp = I915_READ(PORT_HOTPLUG_STAT);
1647
1648         if ((temp & bit) == 0)
1649                 return connector_status_disconnected;
1650
1651         status = connector_status_disconnected;
1652         if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1653                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1654         {
1655                 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1656                         status = connector_status_connected;
1657         }
1658
1659         return status;
1660 }
1661
1662 /**
1663  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1664  *
1665  * \return true if DP port is connected.
1666  * \return false if DP port is disconnected.
1667  */
1668 static enum drm_connector_status
1669 intel_dp_detect(struct drm_connector *connector, bool force)
1670 {
1671         struct intel_dp *intel_dp = intel_attached_dp(connector);
1672         struct drm_device *dev = intel_dp->base.base.dev;
1673         enum drm_connector_status status;
1674         struct edid *edid = NULL;
1675
1676         intel_dp->has_audio = false;
1677
1678         if (HAS_PCH_SPLIT(dev))
1679                 status = ironlake_dp_detect(intel_dp);
1680         else
1681                 status = g4x_dp_detect(intel_dp);
1682         if (status != connector_status_connected)
1683                 return status;
1684
1685         if (intel_dp->force_audio) {
1686                 intel_dp->has_audio = intel_dp->force_audio > 0;
1687         } else {
1688                 edid = drm_get_edid(connector, &intel_dp->adapter);
1689                 if (edid) {
1690                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1691                         connector->display_info.raw_edid = NULL;
1692                         kfree(edid);
1693                 }
1694         }
1695
1696         return connector_status_connected;
1697 }
1698
1699 static int intel_dp_get_modes(struct drm_connector *connector)
1700 {
1701         struct intel_dp *intel_dp = intel_attached_dp(connector);
1702         struct drm_device *dev = intel_dp->base.base.dev;
1703         struct drm_i915_private *dev_priv = dev->dev_private;
1704         int ret;
1705
1706         /* We should parse the EDID data and find out if it has an audio sink
1707          */
1708
1709         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1710         if (ret) {
1711                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1712                         struct drm_display_mode *newmode;
1713                         list_for_each_entry(newmode, &connector->probed_modes,
1714                                             head) {
1715                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1716                                         dev_priv->panel_fixed_mode =
1717                                                 drm_mode_duplicate(dev, newmode);
1718                                         break;
1719                                 }
1720                         }
1721                 }
1722
1723                 return ret;
1724         }
1725
1726         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1727         if (is_edp(intel_dp)) {
1728                 if (dev_priv->panel_fixed_mode != NULL) {
1729                         struct drm_display_mode *mode;
1730                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1731                         drm_mode_probed_add(connector, mode);
1732                         return 1;
1733                 }
1734         }
1735         return 0;
1736 }
1737
1738 static bool
1739 intel_dp_detect_audio(struct drm_connector *connector)
1740 {
1741         struct intel_dp *intel_dp = intel_attached_dp(connector);
1742         struct edid *edid;
1743         bool has_audio = false;
1744
1745         edid = drm_get_edid(connector, &intel_dp->adapter);
1746         if (edid) {
1747                 has_audio = drm_detect_monitor_audio(edid);
1748
1749                 connector->display_info.raw_edid = NULL;
1750                 kfree(edid);
1751         }
1752
1753         return has_audio;
1754 }
1755
1756 static int
1757 intel_dp_set_property(struct drm_connector *connector,
1758                       struct drm_property *property,
1759                       uint64_t val)
1760 {
1761         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1762         struct intel_dp *intel_dp = intel_attached_dp(connector);
1763         int ret;
1764
1765         ret = drm_connector_property_set_value(connector, property, val);
1766         if (ret)
1767                 return ret;
1768
1769         if (property == dev_priv->force_audio_property) {
1770                 int i = val;
1771                 bool has_audio;
1772
1773                 if (i == intel_dp->force_audio)
1774                         return 0;
1775
1776                 intel_dp->force_audio = i;
1777
1778                 if (i == 0)
1779                         has_audio = intel_dp_detect_audio(connector);
1780                 else
1781                         has_audio = i > 0;
1782
1783                 if (has_audio == intel_dp->has_audio)
1784                         return 0;
1785
1786                 intel_dp->has_audio = has_audio;
1787                 goto done;
1788         }
1789
1790         if (property == dev_priv->broadcast_rgb_property) {
1791                 if (val == !!intel_dp->color_range)
1792                         return 0;
1793
1794                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1795                 goto done;
1796         }
1797
1798         return -EINVAL;
1799
1800 done:
1801         if (intel_dp->base.base.crtc) {
1802                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1803                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1804                                          crtc->x, crtc->y,
1805                                          crtc->fb);
1806         }
1807
1808         return 0;
1809 }
1810
1811 static void
1812 intel_dp_destroy (struct drm_connector *connector)
1813 {
1814         drm_sysfs_connector_remove(connector);
1815         drm_connector_cleanup(connector);
1816         kfree(connector);
1817 }
1818
1819 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1820 {
1821         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1822
1823         i2c_del_adapter(&intel_dp->adapter);
1824         drm_encoder_cleanup(encoder);
1825         kfree(intel_dp);
1826 }
1827
1828 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1829         .dpms = intel_dp_dpms,
1830         .mode_fixup = intel_dp_mode_fixup,
1831         .prepare = intel_dp_prepare,
1832         .mode_set = intel_dp_mode_set,
1833         .commit = intel_dp_commit,
1834 };
1835
1836 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1837         .dpms = drm_helper_connector_dpms,
1838         .detect = intel_dp_detect,
1839         .fill_modes = drm_helper_probe_single_connector_modes,
1840         .set_property = intel_dp_set_property,
1841         .destroy = intel_dp_destroy,
1842 };
1843
1844 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1845         .get_modes = intel_dp_get_modes,
1846         .mode_valid = intel_dp_mode_valid,
1847         .best_encoder = intel_best_encoder,
1848 };
1849
1850 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1851         .destroy = intel_dp_encoder_destroy,
1852 };
1853
1854 static void
1855 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1856 {
1857         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1858
1859         intel_dp_check_link_status(intel_dp);
1860 }
1861
1862 /* Return which DP Port should be selected for Transcoder DP control */
1863 int
1864 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1865 {
1866         struct drm_device *dev = crtc->dev;
1867         struct drm_mode_config *mode_config = &dev->mode_config;
1868         struct drm_encoder *encoder;
1869
1870         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1871                 struct intel_dp *intel_dp;
1872
1873                 if (encoder->crtc != crtc)
1874                         continue;
1875
1876                 intel_dp = enc_to_intel_dp(encoder);
1877                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1878                         return intel_dp->output_reg;
1879         }
1880
1881         return -1;
1882 }
1883
1884 /* check the VBT to see whether the eDP is on DP-D port */
1885 bool intel_dpd_is_edp(struct drm_device *dev)
1886 {
1887         struct drm_i915_private *dev_priv = dev->dev_private;
1888         struct child_device_config *p_child;
1889         int i;
1890
1891         if (!dev_priv->child_dev_num)
1892                 return false;
1893
1894         for (i = 0; i < dev_priv->child_dev_num; i++) {
1895                 p_child = dev_priv->child_dev + i;
1896
1897                 if (p_child->dvo_port == PORT_IDPD &&
1898                     p_child->device_type == DEVICE_TYPE_eDP)
1899                         return true;
1900         }
1901         return false;
1902 }
1903
1904 static void
1905 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1906 {
1907         intel_attach_force_audio_property(connector);
1908         intel_attach_broadcast_rgb_property(connector);
1909 }
1910
1911 void
1912 intel_dp_init(struct drm_device *dev, int output_reg)
1913 {
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915         struct drm_connector *connector;
1916         struct intel_dp *intel_dp;
1917         struct intel_encoder *intel_encoder;
1918         struct intel_connector *intel_connector;
1919         const char *name = NULL;
1920         int type;
1921
1922         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1923         if (!intel_dp)
1924                 return;
1925
1926         intel_dp->output_reg = output_reg;
1927
1928         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1929         if (!intel_connector) {
1930                 kfree(intel_dp);
1931                 return;
1932         }
1933         intel_encoder = &intel_dp->base;
1934
1935         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1936                 if (intel_dpd_is_edp(dev))
1937                         intel_dp->is_pch_edp = true;
1938
1939         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1940                 type = DRM_MODE_CONNECTOR_eDP;
1941                 intel_encoder->type = INTEL_OUTPUT_EDP;
1942         } else {
1943                 type = DRM_MODE_CONNECTOR_DisplayPort;
1944                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1945         }
1946
1947         connector = &intel_connector->base;
1948         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1949         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1950
1951         connector->polled = DRM_CONNECTOR_POLL_HPD;
1952
1953         if (output_reg == DP_B || output_reg == PCH_DP_B)
1954                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1955         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1956                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1957         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1958                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1959
1960         if (is_edp(intel_dp))
1961                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1962
1963         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1964         connector->interlace_allowed = true;
1965         connector->doublescan_allowed = 0;
1966
1967         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1968                          DRM_MODE_ENCODER_TMDS);
1969         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1970
1971         intel_connector_attach_encoder(intel_connector, intel_encoder);
1972         drm_sysfs_connector_add(connector);
1973
1974         /* Set up the DDC bus. */
1975         switch (output_reg) {
1976                 case DP_A:
1977                         name = "DPDDC-A";
1978                         break;
1979                 case DP_B:
1980                 case PCH_DP_B:
1981                         dev_priv->hotplug_supported_mask |=
1982                                 HDMIB_HOTPLUG_INT_STATUS;
1983                         name = "DPDDC-B";
1984                         break;
1985                 case DP_C:
1986                 case PCH_DP_C:
1987                         dev_priv->hotplug_supported_mask |=
1988                                 HDMIC_HOTPLUG_INT_STATUS;
1989                         name = "DPDDC-C";
1990                         break;
1991                 case DP_D:
1992                 case PCH_DP_D:
1993                         dev_priv->hotplug_supported_mask |=
1994                                 HDMID_HOTPLUG_INT_STATUS;
1995                         name = "DPDDC-D";
1996                         break;
1997         }
1998
1999         intel_dp_i2c_init(intel_dp, intel_connector, name);
2000
2001         /* Cache some DPCD data in the eDP case */
2002         if (is_edp(intel_dp)) {
2003                 int ret;
2004                 u32 pp_on, pp_div;
2005
2006                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2007                 pp_div = I915_READ(PCH_PP_DIVISOR);
2008
2009                 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2010                 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2011                 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2012                 dev_priv->panel_t12 = pp_div & 0xf;
2013                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2014
2015                 ironlake_edp_panel_vdd_on(intel_dp);
2016                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
2017                                                intel_dp->dpcd,
2018                                                sizeof(intel_dp->dpcd));
2019                 ironlake_edp_panel_vdd_off(intel_dp);
2020                 if (ret == sizeof(intel_dp->dpcd)) {
2021                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2022                                 dev_priv->no_aux_handshake =
2023                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2024                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2025                 } else {
2026                         /* if this fails, presume the device is a ghost */
2027                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2028                         intel_dp_encoder_destroy(&intel_dp->base.base);
2029                         intel_dp_destroy(&intel_connector->base);
2030                         return;
2031                 }
2032         }
2033
2034         intel_encoder->hot_plug = intel_dp_hot_plug;
2035
2036         if (is_edp(intel_dp)) {
2037                 /* initialize panel mode from VBT if available for eDP */
2038                 if (dev_priv->lfp_lvds_vbt_mode) {
2039                         dev_priv->panel_fixed_mode =
2040                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2041                         if (dev_priv->panel_fixed_mode) {
2042                                 dev_priv->panel_fixed_mode->type |=
2043                                         DRM_MODE_TYPE_PREFERRED;
2044                         }
2045                 }
2046         }
2047
2048         intel_dp_add_properties(intel_dp, connector);
2049
2050         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2051          * 0xd.  Failure to do so will result in spurious interrupts being
2052          * generated on the port when a cable is not attached.
2053          */
2054         if (IS_G4X(dev) && !IS_GM45(dev)) {
2055                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2056                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2057         }
2058 }