drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int dpms_mode;
  52         uint8_t link_bw;
  53         uint8_t lane_count;
  54         uint8_t dpcd[4];
  55         struct i2c_adapter adapter;
  56         struct i2c_algo_dp_aux_data algo;
  57         bool is_pch_edp;
  58         uint8_t train_set[4];
  59         uint8_t link_status[DP_LINK_STATUS_SIZE];
  60 };
  61
  62 /**
  63  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  64  * @intel_dp: DP struct
  65  *
  66  * If a CPU or PCH DP output is attached to an eDP panel, this function
  67  * will return true, and false otherwise.
  68  */
  69 static bool is_edp(struct intel_dp *intel_dp)
  70 {
  71         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  72 }
  73
  74 /**
  75  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  76  * @intel_dp: DP struct
  77  *
  78  * Returns true if the given DP struct corresponds to a PCH DP port attached
  79  * to an eDP panel, false otherwise.  Helpful for determining whether we
  80  * may need FDI resources for a given DP output or not.
  81  */
  82 static bool is_pch_edp(struct intel_dp *intel_dp)
  83 {
  84         return intel_dp->is_pch_edp;
  85 }
  86
  87 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  88 {
  89         return container_of(encoder, struct intel_dp, base.base);
  90 }
  91
  92 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  93 {
  94         return container_of(intel_attached_encoder(connector),
  95                             struct intel_dp, base);
  96 }
  97
  98 /**
  99  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 100  * @encoder: DRM encoder
 101  *
 102  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 103  * by intel_display.c.
 104  */
 105 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 106 {
 107         struct intel_dp *intel_dp;
 108
 109         if (!encoder)
 110                 return false;
 111
 112         intel_dp = enc_to_intel_dp(encoder);
 113
 114         return is_pch_edp(intel_dp);
 115 }
 116
 117 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 118 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 119 static void intel_dp_link_down(struct intel_dp *intel_dp);
 120
 121 void
 122 intel_edp_link_config (struct intel_encoder *intel_encoder,
 123                        int *lane_num, int *link_bw)
 124 {
 125         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 126
 127         *lane_num = intel_dp->lane_count;
 128         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 129                 *link_bw = 162000;
 130         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 131                 *link_bw = 270000;
 132 }
 133
 134 static int
 135 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 136 {
 137         int max_lane_count = 4;
 138
 139         if (intel_dp->dpcd[0] >= 0x11) {
 140                 max_lane_count = intel_dp->dpcd[2] & 0x1f;
 141                 switch (max_lane_count) {
 142                 case 1: case 2: case 4:
 143                         break;
 144                 default:
 145                         max_lane_count = 4;
 146                 }
 147         }
 148         return max_lane_count;
 149 }
 150
 151 static int
 152 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 153 {
 154         int max_link_bw = intel_dp->dpcd[1];
 155
 156         switch (max_link_bw) {
 157         case DP_LINK_BW_1_62:
 158         case DP_LINK_BW_2_7:
 159                 break;
 160         default:
 161                 max_link_bw = DP_LINK_BW_1_62;
 162                 break;
 163         }
 164         return max_link_bw;
 165 }
 166
 167 static int
 168 intel_dp_link_clock(uint8_t link_bw)
 169 {
 170         if (link_bw == DP_LINK_BW_2_7)
 171                 return 270000;
 172         else
 173                 return 162000;
 174 }
 175
 176 /* I think this is a fiction */
 177 static int
 178 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 179 {
 180         struct drm_i915_private *dev_priv = dev->dev_private;
 181
 182         if (is_edp(intel_dp))
 183                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
 184         else
 185                 return pixel_clock * 3;
 186 }
 187
 188 static int
 189 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 190 {
 191         return (max_link_clock * max_lanes * 8) / 10;
 192 }
 193
 194 static int
 195 intel_dp_mode_valid(struct drm_connector *connector,
 196                     struct drm_display_mode *mode)
 197 {
 198         struct intel_dp *intel_dp = intel_attached_dp(connector);
 199         struct drm_device *dev = connector->dev;
 200         struct drm_i915_private *dev_priv = dev->dev_private;
 201         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 202         int max_lanes = intel_dp_max_lane_count(intel_dp);
 203
 204         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 205                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 206                         return MODE_PANEL;
 207
 208                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 209                         return MODE_PANEL;
 210         }
 211
 212         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 213            which are outside spec tolerances but somehow work by magic */
 214         if (!is_edp(intel_dp) &&
 215             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 216              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 217                 return MODE_CLOCK_HIGH;
 218
 219         if (mode->clock < 10000)
 220                 return MODE_CLOCK_LOW;
 221
 222         return MODE_OK;
 223 }
 224
 225 static uint32_t
 226 pack_aux(uint8_t *src, int src_bytes)
 227 {
 228         int     i;
 229         uint32_t v = 0;
 230
 231         if (src_bytes > 4)
 232                 src_bytes = 4;
 233         for (i = 0; i < src_bytes; i++)
 234                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 235         return v;
 236 }
 237
 238 static void
 239 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 240 {
 241         int i;
 242         if (dst_bytes > 4)
 243                 dst_bytes = 4;
 244         for (i = 0; i < dst_bytes; i++)
 245                 dst[i] = src >> ((3-i) * 8);
 246 }
 247
 248 /* hrawclock is 1/4 the FSB frequency */
 249 static int
 250 intel_hrawclk(struct drm_device *dev)
 251 {
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         uint32_t clkcfg;
 254
 255         clkcfg = I915_READ(CLKCFG);
 256         switch (clkcfg & CLKCFG_FSB_MASK) {
 257         case CLKCFG_FSB_400:
 258                 return 100;
 259         case CLKCFG_FSB_533:
 260                 return 133;
 261         case CLKCFG_FSB_667:
 262                 return 166;
 263         case CLKCFG_FSB_800:
 264                 return 200;
 265         case CLKCFG_FSB_1067:
 266                 return 266;
 267         case CLKCFG_FSB_1333:
 268                 return 333;
 269         /* these two are just a guess; one of them might be right */
 270         case CLKCFG_FSB_1600:
 271         case CLKCFG_FSB_1600_ALT:
 272                 return 400;
 273         default:
 274                 return 133;
 275         }
 276 }
 277
 278 static int
 279 intel_dp_aux_ch(struct intel_dp *intel_dp,
 280                 uint8_t *send, int send_bytes,
 281                 uint8_t *recv, int recv_size)
 282 {
 283         uint32_t output_reg = intel_dp->output_reg;
 284         struct drm_device *dev = intel_dp->base.base.dev;
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286         uint32_t ch_ctl = output_reg + 0x10;
 287         uint32_t ch_data = ch_ctl + 4;
 288         int i;
 289         int recv_bytes;
 290         uint32_t status;
 291         uint32_t aux_clock_divider;
 292         int try, precharge;
 293
 294         /* The clock divider is based off the hrawclk,
 295          * and would like to run at 2MHz. So, take the
 296          * hrawclk value and divide by 2 and use that
 297          *
 298          * Note that PCH attached eDP panels should use a 125MHz input
 299          * clock divider.
 300          */
 301         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 302                 if (IS_GEN6(dev))
 303                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 304                 else
 305                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 306         } else if (HAS_PCH_SPLIT(dev))
 307                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 308         else
 309                 aux_clock_divider = intel_hrawclk(dev) / 2;
 310
 311         if (IS_GEN6(dev))
 312                 precharge = 3;
 313         else
 314                 precharge = 5;
 315
 316         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 317                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 318                           I915_READ(ch_ctl));
 319                 return -EBUSY;
 320         }
 321
 322         /* Must try at least 3 times according to DP spec */
 323         for (try = 0; try < 5; try++) {
 324                 /* Load the send data into the aux channel data registers */
 325                 for (i = 0; i < send_bytes; i += 4)
 326                         I915_WRITE(ch_data + i,
 327                                    pack_aux(send + i, send_bytes - i));
 328
 329                 /* Send the command and wait for it to complete */
 330                 I915_WRITE(ch_ctl,
 331                            DP_AUX_CH_CTL_SEND_BUSY |
 332                            DP_AUX_CH_CTL_TIME_OUT_400us |
 333                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 334                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 335                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 336                            DP_AUX_CH_CTL_DONE |
 337                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 338                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 339                 for (;;) {
 340                         status = I915_READ(ch_ctl);
 341                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 342                                 break;
 343                         udelay(100);
 344                 }
 345
 346                 /* Clear done status and any errors */
 347                 I915_WRITE(ch_ctl,
 348                            status |
 349                            DP_AUX_CH_CTL_DONE |
 350                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 351                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 352                 if (status & DP_AUX_CH_CTL_DONE)
 353                         break;
 354         }
 355
 356         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 357                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 358                 return -EBUSY;
 359         }
 360
 361         /* Check for timeout or receive error.
 362          * Timeouts occur when the sink is not connected
 363          */
 364         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 365                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 366                 return -EIO;
 367         }
 368
 369         /* Timeouts occur when the device isn't connected, so they're
 370          * "normal" -- don't fill the kernel log with these */
 371         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 372                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 373                 return -ETIMEDOUT;
 374         }
 375
 376         /* Unload any bytes sent back from the other side */
 377         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 378                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 379         if (recv_bytes > recv_size)
 380                 recv_bytes = recv_size;
 381
 382         for (i = 0; i < recv_bytes; i += 4)
 383                 unpack_aux(I915_READ(ch_data + i),
 384                            recv + i, recv_bytes - i);
 385
 386         return recv_bytes;
 387 }
 388
 389 /* Write data to the aux channel in native mode */
 390 static int
 391 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 392                           uint16_t address, uint8_t *send, int send_bytes)
 393 {
 394         int ret;
 395         uint8_t msg[20];
 396         int msg_bytes;
 397         uint8_t ack;
 398
 399         if (send_bytes > 16)
 400                 return -1;
 401         msg[0] = AUX_NATIVE_WRITE << 4;
 402         msg[1] = address >> 8;
 403         msg[2] = address & 0xff;
 404         msg[3] = send_bytes - 1;
 405         memcpy(&msg[4], send, send_bytes);
 406         msg_bytes = send_bytes + 4;
 407         for (;;) {
 408                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 409                 if (ret < 0)
 410                         return ret;
 411                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 412                         break;
 413                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 414                         udelay(100);
 415                 else
 416                         return -EIO;
 417         }
 418         return send_bytes;
 419 }
 420
 421 /* Write a single byte to the aux channel in native mode */
 422 static int
 423 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 424                             uint16_t address, uint8_t byte)
 425 {
 426         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 427 }
 428
 429 /* read bytes from a native aux channel */
 430 static int
 431 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 432                          uint16_t address, uint8_t *recv, int recv_bytes)
 433 {
 434         uint8_t msg[4];
 435         int msg_bytes;
 436         uint8_t reply[20];
 437         int reply_bytes;
 438         uint8_t ack;
 439         int ret;
 440
 441         msg[0] = AUX_NATIVE_READ << 4;
 442         msg[1] = address >> 8;
 443         msg[2] = address & 0xff;
 444         msg[3] = recv_bytes - 1;
 445
 446         msg_bytes = 4;
 447         reply_bytes = recv_bytes + 1;
 448
 449         for (;;) {
 450                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 451                                       reply, reply_bytes);
 452                 if (ret == 0)
 453                         return -EPROTO;
 454                 if (ret < 0)
 455                         return ret;
 456                 ack = reply[0];
 457                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 458                         memcpy(recv, reply + 1, ret - 1);
 459                         return ret - 1;
 460                 }
 461                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 462                         udelay(100);
 463                 else
 464                         return -EIO;
 465         }
 466 }
 467
 468 static int
 469 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 470                     uint8_t write_byte, uint8_t *read_byte)
 471 {
 472         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 473         struct intel_dp *intel_dp = container_of(adapter,
 474                                                 struct intel_dp,
 475                                                 adapter);
 476         uint16_t address = algo_data->address;
 477         uint8_t msg[5];
 478         uint8_t reply[2];
 479         int msg_bytes;
 480         int reply_bytes;
 481         int ret;
 482
 483         /* Set up the command byte */
 484         if (mode & MODE_I2C_READ)
 485                 msg[0] = AUX_I2C_READ << 4;
 486         else
 487                 msg[0] = AUX_I2C_WRITE << 4;
 488
 489         if (!(mode & MODE_I2C_STOP))
 490                 msg[0] |= AUX_I2C_MOT << 4;
 491
 492         msg[1] = address >> 8;
 493         msg[2] = address;
 494
 495         switch (mode) {
 496         case MODE_I2C_WRITE:
 497                 msg[3] = 0;
 498                 msg[4] = write_byte;
 499                 msg_bytes = 5;
 500                 reply_bytes = 1;
 501                 break;
 502         case MODE_I2C_READ:
 503                 msg[3] = 0;
 504                 msg_bytes = 4;
 505                 reply_bytes = 2;
 506                 break;
 507         default:
 508                 msg_bytes = 3;
 509                 reply_bytes = 1;
 510                 break;
 511         }
 512
 513         for (;;) {
 514           ret = intel_dp_aux_ch(intel_dp,
 515                                 msg, msg_bytes,
 516                                 reply, reply_bytes);
 517                 if (ret < 0) {
 518                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 519                         return ret;
 520                 }
 521                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 522                 case AUX_I2C_REPLY_ACK:
 523                         if (mode == MODE_I2C_READ) {
 524                                 *read_byte = reply[1];
 525                         }
 526                         return reply_bytes - 1;
 527                 case AUX_I2C_REPLY_NACK:
 528                         DRM_DEBUG_KMS("aux_ch nack\n");
 529                         return -EREMOTEIO;
 530                 case AUX_I2C_REPLY_DEFER:
 531                         DRM_DEBUG_KMS("aux_ch defer\n");
 532                         udelay(100);
 533                         break;
 534                 default:
 535                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 536                         return -EREMOTEIO;
 537                 }
 538         }
 539 }
 540
 541 static int
 542 intel_dp_i2c_init(struct intel_dp *intel_dp,
 543                   struct intel_connector *intel_connector, const char *name)
 544 {
 545         DRM_DEBUG_KMS("i2c_init %s\n", name);
 546         intel_dp->algo.running = false;
 547         intel_dp->algo.address = 0;
 548         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 549
 550         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 551         intel_dp->adapter.owner = THIS_MODULE;
 552         intel_dp->adapter.class = I2C_CLASS_DDC;
 553         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 554         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 555         intel_dp->adapter.algo_data = &intel_dp->algo;
 556         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 557
 558         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 559 }
 560
 561 static bool
 562 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 563                     struct drm_display_mode *adjusted_mode)
 564 {
 565         struct drm_device *dev = encoder->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 568         int lane_count, clock;
 569         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 570         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 571         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 572
 573         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 574                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 575                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 576                                         mode, adjusted_mode);
 577                 /*
 578                  * the mode->clock is used to calculate the Data&Link M/N
 579                  * of the pipe. For the eDP the fixed clock should be used.
 580                  */
 581                 mode->clock = dev_priv->panel_fixed_mode->clock;
 582         }
 583
 584         /* Just use VBT values for eDP */
 585         if (is_edp(intel_dp)) {
 586                 intel_dp->lane_count = dev_priv->edp.lanes;
 587                 intel_dp->link_bw = dev_priv->edp.rate;
 588                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 589                 DRM_DEBUG_KMS("eDP link bw %02x lane count %d clock %d\n",
 590                               intel_dp->link_bw, intel_dp->lane_count,
 591                               adjusted_mode->clock);
 592                 return true;
 593         }
 594
 595         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 596                 for (clock = 0; clock <= max_clock; clock++) {
 597                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 598
 599                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 600                                         <= link_avail) {
 601                                 intel_dp->link_bw = bws[clock];
 602                                 intel_dp->lane_count = lane_count;
 603                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 604                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 605                                                 "count %d clock %d\n",
 606                                        intel_dp->link_bw, intel_dp->lane_count,
 607                                        adjusted_mode->clock);
 608                                 return true;
 609                         }
 610                 }
 611         }
 612
 613         return false;
 614 }
 615
 616 struct intel_dp_m_n {
 617         uint32_t        tu;
 618         uint32_t        gmch_m;
 619         uint32_t        gmch_n;
 620         uint32_t        link_m;
 621         uint32_t        link_n;
 622 };
 623
 624 static void
 625 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 626 {
 627         while (*num > 0xffffff || *den > 0xffffff) {
 628                 *num >>= 1;
 629                 *den >>= 1;
 630         }
 631 }
 632
 633 static void
 634 intel_dp_compute_m_n(int bpp,
 635                      int nlanes,
 636                      int pixel_clock,
 637                      int link_clock,
 638                      struct intel_dp_m_n *m_n)
 639 {
 640         m_n->tu = 64;
 641         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 642         m_n->gmch_n = link_clock * nlanes;
 643         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 644         m_n->link_m = pixel_clock;
 645         m_n->link_n = link_clock;
 646         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 647 }
 648
 649 void
 650 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 651                  struct drm_display_mode *adjusted_mode)
 652 {
 653         struct drm_device *dev = crtc->dev;
 654         struct drm_mode_config *mode_config = &dev->mode_config;
 655         struct drm_encoder *encoder;
 656         struct drm_i915_private *dev_priv = dev->dev_private;
 657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 658         int lane_count = 4, bpp = 24;
 659         struct intel_dp_m_n m_n;
 660
 661         /*
 662          * Find the lane count in the intel_encoder private
 663          */
 664         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 665                 struct intel_dp *intel_dp;
 666
 667                 if (encoder->crtc != crtc)
 668                         continue;
 669
 670                 intel_dp = enc_to_intel_dp(encoder);
 671                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 672                         lane_count = intel_dp->lane_count;
 673                         break;
 674                 } else if (is_edp(intel_dp)) {
 675                         lane_count = dev_priv->edp.lanes;
 676                         bpp = dev_priv->edp.bpp;
 677                         break;
 678                 }
 679         }
 680
 681         /*
 682          * Compute the GMCH and Link ratios. The '3' here is
 683          * the number of bytes_per_pixel post-LUT, which we always
 684          * set up for 8-bits of R/G/B, or 3 bytes total.
 685          */
 686         intel_dp_compute_m_n(bpp, lane_count,
 687                              mode->clock, adjusted_mode->clock, &m_n);
 688
 689         if (HAS_PCH_SPLIT(dev)) {
 690                 if (intel_crtc->pipe == 0) {
 691                         I915_WRITE(TRANSA_DATA_M1,
 692                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 693                                    m_n.gmch_m);
 694                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 695                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 696                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 697                 } else {
 698                         I915_WRITE(TRANSB_DATA_M1,
 699                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 700                                    m_n.gmch_m);
 701                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 702                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 703                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 704                 }
 705         } else {
 706                 if (intel_crtc->pipe == 0) {
 707                         I915_WRITE(PIPEA_GMCH_DATA_M,
 708                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 709                                    m_n.gmch_m);
 710                         I915_WRITE(PIPEA_GMCH_DATA_N,
 711                                    m_n.gmch_n);
 712                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 713                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 714                 } else {
 715                         I915_WRITE(PIPEB_GMCH_DATA_M,
 716                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 717                                    m_n.gmch_m);
 718                         I915_WRITE(PIPEB_GMCH_DATA_N,
 719                                         m_n.gmch_n);
 720                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 721                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 722                 }
 723         }
 724 }
 725
 726 static void
 727 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 728                   struct drm_display_mode *adjusted_mode)
 729 {
 730         struct drm_device *dev = encoder->dev;
 731         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 732         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         intel_dp->DP = (DP_VOLTAGE_0_4 |
 736                        DP_PRE_EMPHASIS_0);
 737
 738         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 739                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 740         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 741                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 742
 743         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 744                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 745         else
 746                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 747
 748         switch (intel_dp->lane_count) {
 749         case 1:
 750                 intel_dp->DP |= DP_PORT_WIDTH_1;
 751                 break;
 752         case 2:
 753                 intel_dp->DP |= DP_PORT_WIDTH_2;
 754                 break;
 755         case 4:
 756                 intel_dp->DP |= DP_PORT_WIDTH_4;
 757                 break;
 758         }
 759         if (intel_dp->has_audio)
 760                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 761
 762         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 763         intel_dp->link_configuration[0] = intel_dp->link_bw;
 764         intel_dp->link_configuration[1] = intel_dp->lane_count;
 765
 766         /*
 767          * Check for DPCD version > 1.1 and enhanced framing support
 768          */
 769         if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 770                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 771                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 772         }
 773
 774         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 775         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 776                 intel_dp->DP |= DP_PIPEB_SELECT;
 777
 778         if (is_edp(intel_dp)) {
 779                 /* don't miss out required setting for eDP */
 780                 intel_dp->DP |= DP_PLL_ENABLE;
 781                 if (adjusted_mode->clock < 200000)
 782                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 783                 else
 784                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 785         }
 786 }
 787
 788 /* Returns true if the panel was already on when called */
 789 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 790 {
 791         struct drm_device *dev = intel_dp->base.base.dev;
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 794
 795         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 796                 return true;
 797
 798         pp = I915_READ(PCH_PP_CONTROL);
 799
 800         /* ILK workaround: disable reset around power sequence */
 801         pp &= ~PANEL_POWER_RESET;
 802         I915_WRITE(PCH_PP_CONTROL, pp);
 803         POSTING_READ(PCH_PP_CONTROL);
 804
 805         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 806         I915_WRITE(PCH_PP_CONTROL, pp);
 807         POSTING_READ(PCH_PP_CONTROL);
 808
 809         /* Ouch. We need to wait here for some panels, like Dell e6510
 810          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
 811          */
 812         msleep(300);
 813
 814         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 815                      5000))
 816                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 817                           I915_READ(PCH_PP_STATUS));
 818
 819         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 820         I915_WRITE(PCH_PP_CONTROL, pp);
 821         POSTING_READ(PCH_PP_CONTROL);
 822
 823         return false;
 824 }
 825
 826 static void ironlake_edp_panel_off (struct drm_device *dev)
 827 {
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 830                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 831
 832         pp = I915_READ(PCH_PP_CONTROL);
 833
 834         /* ILK workaround: disable reset around power sequence */
 835         pp &= ~PANEL_POWER_RESET;
 836         I915_WRITE(PCH_PP_CONTROL, pp);
 837         POSTING_READ(PCH_PP_CONTROL);
 838
 839         pp &= ~POWER_TARGET_ON;
 840         I915_WRITE(PCH_PP_CONTROL, pp);
 841         POSTING_READ(PCH_PP_CONTROL);
 842
 843         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 844                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 845                           I915_READ(PCH_PP_STATUS));
 846
 847         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 848         I915_WRITE(PCH_PP_CONTROL, pp);
 849         POSTING_READ(PCH_PP_CONTROL);
 850
 851         /* Ouch. We need to wait here for some panels, like Dell e6510
 852          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
 853          */
 854         msleep(300);
 855 }
 856
 857 static void ironlake_edp_backlight_on (struct drm_device *dev)
 858 {
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860         u32 pp;
 861
 862         DRM_DEBUG_KMS("\n");
 863         /*
 864          * If we enable the backlight right away following a panel power
 865          * on, we may see slight flicker as the panel syncs with the eDP
 866          * link.  So delay a bit to make sure the image is solid before
 867          * allowing it to appear.
 868          */
 869         msleep(300);
 870         pp = I915_READ(PCH_PP_CONTROL);
 871         pp |= EDP_BLC_ENABLE;
 872         I915_WRITE(PCH_PP_CONTROL, pp);
 873 }
 874
 875 static void ironlake_edp_backlight_off (struct drm_device *dev)
 876 {
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878         u32 pp;
 879
 880         DRM_DEBUG_KMS("\n");
 881         pp = I915_READ(PCH_PP_CONTROL);
 882         pp &= ~EDP_BLC_ENABLE;
 883         I915_WRITE(PCH_PP_CONTROL, pp);
 884 }
 885
 886 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 887 {
 888         struct drm_device *dev = encoder->dev;
 889         struct drm_i915_private *dev_priv = dev->dev_private;
 890         u32 dpa_ctl;
 891
 892         DRM_DEBUG_KMS("\n");
 893         dpa_ctl = I915_READ(DP_A);
 894         dpa_ctl &= ~DP_PLL_ENABLE;
 895         I915_WRITE(DP_A, dpa_ctl);
 896 }
 897
 898 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 899 {
 900         struct drm_device *dev = encoder->dev;
 901         struct drm_i915_private *dev_priv = dev->dev_private;
 902         u32 dpa_ctl;
 903
 904         dpa_ctl = I915_READ(DP_A);
 905         dpa_ctl |= DP_PLL_ENABLE;
 906         I915_WRITE(DP_A, dpa_ctl);
 907         POSTING_READ(DP_A);
 908         udelay(200);
 909 }
 910
 911 static void intel_dp_prepare(struct drm_encoder *encoder)
 912 {
 913         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 914         struct drm_device *dev = encoder->dev;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 917
 918         if (is_edp(intel_dp)) {
 919                 ironlake_edp_backlight_off(dev);
 920                 ironlake_edp_panel_on(intel_dp);
 921                 if (!is_pch_edp(intel_dp))
 922                         ironlake_edp_pll_on(encoder);
 923                 else
 924                         ironlake_edp_pll_off(encoder);
 925         }
 926         if (dp_reg & DP_PORT_EN)
 927                 intel_dp_link_down(intel_dp);
 928 }
 929
 930 static void intel_dp_commit(struct drm_encoder *encoder)
 931 {
 932         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 933         struct drm_device *dev = encoder->dev;
 934
 935         intel_dp_start_link_train(intel_dp);
 936
 937         if (is_edp(intel_dp))
 938                 ironlake_edp_panel_on(intel_dp);
 939
 940         intel_dp_complete_link_train(intel_dp);
 941
 942         if (is_edp(intel_dp))
 943                 ironlake_edp_backlight_on(dev);
 944 }
 945
 946 static void
 947 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 948 {
 949         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 950         struct drm_device *dev = encoder->dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 953
 954         if (mode != DRM_MODE_DPMS_ON) {
 955                 if (is_edp(intel_dp))
 956                         ironlake_edp_backlight_off(dev);
 957                 if (dp_reg & DP_PORT_EN)
 958                         intel_dp_link_down(intel_dp);
 959                 if (is_edp(intel_dp))
 960                         ironlake_edp_panel_off(dev);
 961                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
 962                         ironlake_edp_pll_off(encoder);
 963         } else {
 964                 if (!(dp_reg & DP_PORT_EN)) {
 965                         if (is_edp(intel_dp))
 966                                 ironlake_edp_panel_on(intel_dp);
 967                         intel_dp_start_link_train(intel_dp);
 968                         intel_dp_complete_link_train(intel_dp);
 969                         if (is_edp(intel_dp))
 970                                 ironlake_edp_backlight_on(dev);
 971                 }
 972         }
 973         intel_dp->dpms_mode = mode;
 974 }
 975
 976 /*
 977  * Fetch AUX CH registers 0x202 - 0x207 which contain
 978  * link status information
 979  */
 980 static bool
 981 intel_dp_get_link_status(struct intel_dp *intel_dp)
 982 {
 983         int ret;
 984
 985         ret = intel_dp_aux_native_read(intel_dp,
 986                                        DP_LANE0_1_STATUS,
 987                                        intel_dp->link_status, DP_LINK_STATUS_SIZE);
 988         if (ret != DP_LINK_STATUS_SIZE)
 989                 return false;
 990         return true;
 991 }
 992
 993 static uint8_t
 994 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 995                      int r)
 996 {
 997         return link_status[r - DP_LANE0_1_STATUS];
 998 }
 999
1000 static uint8_t
1001 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1002                                  int lane)
1003 {
1004         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1005         int         s = ((lane & 1) ?
1006                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1007                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1008         uint8_t l = intel_dp_link_status(link_status, i);
1009
1010         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1011 }
1012
1013 static uint8_t
1014 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1015                                       int lane)
1016 {
1017         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1018         int         s = ((lane & 1) ?
1019                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1020                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1021         uint8_t l = intel_dp_link_status(link_status, i);
1022
1023         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1024 }
1025
1026
1027 #if 0
1028 static char     *voltage_names[] = {
1029         "0.4V", "0.6V", "0.8V", "1.2V"
1030 };
1031 static char     *pre_emph_names[] = {
1032         "0dB", "3.5dB", "6dB", "9.5dB"
1033 };
1034 static char     *link_train_names[] = {
1035         "pattern 1", "pattern 2", "idle", "off"
1036 };
1037 #endif
1038
1039 /*
1040  * These are source-specific values; current Intel hardware supports
1041  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1042  */
1043 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1044
1045 static uint8_t
1046 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1047 {
1048         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1049         case DP_TRAIN_VOLTAGE_SWING_400:
1050                 return DP_TRAIN_PRE_EMPHASIS_6;
1051         case DP_TRAIN_VOLTAGE_SWING_600:
1052                 return DP_TRAIN_PRE_EMPHASIS_6;
1053         case DP_TRAIN_VOLTAGE_SWING_800:
1054                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1055         case DP_TRAIN_VOLTAGE_SWING_1200:
1056         default:
1057                 return DP_TRAIN_PRE_EMPHASIS_0;
1058         }
1059 }
1060
1061 static void
1062 intel_get_adjust_train(struct intel_dp *intel_dp)
1063 {
1064         uint8_t v = 0;
1065         uint8_t p = 0;
1066         int lane;
1067
1068         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1069                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1070                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1071
1072                 if (this_v > v)
1073                         v = this_v;
1074                 if (this_p > p)
1075                         p = this_p;
1076         }
1077
1078         if (v >= I830_DP_VOLTAGE_MAX)
1079                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1080
1081         if (p >= intel_dp_pre_emphasis_max(v))
1082                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1083
1084         for (lane = 0; lane < 4; lane++)
1085                 intel_dp->train_set[lane] = v | p;
1086 }
1087
1088 static uint32_t
1089 intel_dp_signal_levels(struct intel_dp *intel_dp)
1090 {
1091         struct drm_device *dev = intel_dp->base.base.dev;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         uint32_t signal_levels = 0;
1094         u8 train_set = intel_dp->train_set[0];
1095         u32 vswing = train_set & DP_TRAIN_VOLTAGE_SWING_MASK;
1096         u32 preemphasis = train_set & DP_TRAIN_PRE_EMPHASIS_MASK;
1097
1098         if (is_edp(intel_dp)) {
1099                 vswing = dev_priv->edp.vswing;
1100                 preemphasis = dev_priv->edp.preemphasis;
1101         }
1102
1103         switch (vswing) {
1104         case DP_TRAIN_VOLTAGE_SWING_400:
1105         default:
1106                 signal_levels |= DP_VOLTAGE_0_4;
1107                 break;
1108         case DP_TRAIN_VOLTAGE_SWING_600:
1109                 signal_levels |= DP_VOLTAGE_0_6;
1110                 break;
1111         case DP_TRAIN_VOLTAGE_SWING_800:
1112                 signal_levels |= DP_VOLTAGE_0_8;
1113                 break;
1114         case DP_TRAIN_VOLTAGE_SWING_1200:
1115                 signal_levels |= DP_VOLTAGE_1_2;
1116                 break;
1117         }
1118         switch (preemphasis) {
1119         case DP_TRAIN_PRE_EMPHASIS_0:
1120         default:
1121                 signal_levels |= DP_PRE_EMPHASIS_0;
1122                 break;
1123         case DP_TRAIN_PRE_EMPHASIS_3_5:
1124                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1125                 break;
1126         case DP_TRAIN_PRE_EMPHASIS_6:
1127                 signal_levels |= DP_PRE_EMPHASIS_6;
1128                 break;
1129         case DP_TRAIN_PRE_EMPHASIS_9_5:
1130                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1131                 break;
1132         }
1133         return signal_levels;
1134 }
1135
1136 /* Gen6's DP voltage swing and pre-emphasis control */
1137 static uint32_t
1138 intel_gen6_edp_signal_levels(uint8_t train_set)
1139 {
1140         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1141         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1142                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1143         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1144                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1145         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1146                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1147         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1148                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1149         default:
1150                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1151                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1152         }
1153 }
1154
1155 static uint8_t
1156 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1157                       int lane)
1158 {
1159         int i = DP_LANE0_1_STATUS + (lane >> 1);
1160         int s = (lane & 1) * 4;
1161         uint8_t l = intel_dp_link_status(link_status, i);
1162
1163         return (l >> s) & 0xf;
1164 }
1165
1166 /* Check for clock recovery is done on all channels */
1167 static bool
1168 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1169 {
1170         int lane;
1171         uint8_t lane_status;
1172
1173         for (lane = 0; lane < lane_count; lane++) {
1174                 lane_status = intel_get_lane_status(link_status, lane);
1175                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1176                         return false;
1177         }
1178         return true;
1179 }
1180
1181 /* Check to see if channel eq is done on all channels */
1182 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1183                          DP_LANE_CHANNEL_EQ_DONE|\
1184                          DP_LANE_SYMBOL_LOCKED)
1185 static bool
1186 intel_channel_eq_ok(struct intel_dp *intel_dp)
1187 {
1188         uint8_t lane_align;
1189         uint8_t lane_status;
1190         int lane;
1191
1192         lane_align = intel_dp_link_status(intel_dp->link_status,
1193                                           DP_LANE_ALIGN_STATUS_UPDATED);
1194         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1195                 return false;
1196         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1197                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1198                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1199                         return false;
1200         }
1201         return true;
1202 }
1203
1204 static bool
1205 intel_dp_aux_handshake_required(struct intel_dp *intel_dp)
1206 {
1207         struct drm_device *dev = intel_dp->base.base.dev;
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209
1210         if (is_edp(intel_dp) && dev_priv->no_aux_handshake)
1211                 return false;
1212
1213         return true;
1214 }
1215
1216 static bool
1217 intel_dp_set_link_train(struct intel_dp *intel_dp,
1218                         uint32_t dp_reg_value,
1219                         uint8_t dp_train_pat)
1220 {
1221         struct drm_device *dev = intel_dp->base.base.dev;
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223         int ret;
1224
1225         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1226         POSTING_READ(intel_dp->output_reg);
1227
1228         if (!intel_dp_aux_handshake_required(intel_dp))
1229                 return true;
1230
1231         intel_dp_aux_native_write_1(intel_dp,
1232                                     DP_TRAINING_PATTERN_SET,
1233                                     dp_train_pat);
1234
1235         ret = intel_dp_aux_native_write(intel_dp,
1236                                         DP_TRAINING_LANE0_SET,
1237                                         intel_dp->train_set, 4);
1238         if (ret != 4)
1239                 return false;
1240
1241         return true;
1242 }
1243
1244 /* Enable corresponding port and start training pattern 1 */
1245 static void
1246 intel_dp_start_link_train(struct intel_dp *intel_dp)
1247 {
1248         struct drm_device *dev = intel_dp->base.base.dev;
1249         struct drm_i915_private *dev_priv = dev->dev_private;
1250         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1251         int i;
1252         uint8_t voltage;
1253         bool clock_recovery = false;
1254         int tries;
1255         u32 reg;
1256         uint32_t DP = intel_dp->DP;
1257
1258         /* Enable output, wait for it to become active */
1259         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1260         POSTING_READ(intel_dp->output_reg);
1261         intel_wait_for_vblank(dev, intel_crtc->pipe);
1262
1263         if (intel_dp_aux_handshake_required(intel_dp))
1264                 /* Write the link configuration data */
1265                 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1266                                           intel_dp->link_configuration,
1267                                           DP_LINK_CONFIGURATION_SIZE);
1268
1269         DP |= DP_PORT_EN;
1270         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1271                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1272         else
1273                 DP &= ~DP_LINK_TRAIN_MASK;
1274         memset(intel_dp->train_set, 0, 4);
1275         voltage = 0xff;
1276         tries = 0;
1277         clock_recovery = false;
1278         for (;;) {
1279                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1280                 uint32_t    signal_levels;
1281                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1282                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1283                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1284                 } else {
1285                         signal_levels = intel_dp_signal_levels(intel_dp);
1286                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1287                 }
1288
1289                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1290                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1291                 else
1292                         reg = DP | DP_LINK_TRAIN_PAT_1;
1293
1294                 if (!intel_dp_set_link_train(intel_dp, reg,
1295                                              DP_TRAINING_PATTERN_1))
1296                         break;
1297                 /* Set training pattern 1 */
1298
1299                 udelay(500);
1300                 if (intel_dp_aux_handshake_required(intel_dp)) {
1301                         break;
1302                 } else {
1303                         if (!intel_dp_get_link_status(intel_dp))
1304                                 break;
1305
1306                         if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1307                                 clock_recovery = true;
1308                                 break;
1309                         }
1310
1311                         /* Check to see if we've tried the max voltage */
1312                         for (i = 0; i < intel_dp->lane_count; i++)
1313                                 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1314                                         break;
1315                         if (i == intel_dp->lane_count)
1316                                 break;
1317
1318                         /* Check to see if we've tried the same voltage 5 times */
1319                         if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1320                                 ++tries;
1321                                 if (tries == 5)
1322                                         break;
1323                         } else
1324                                 tries = 0;
1325                         voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1326
1327                         /* Compute new intel_dp->train_set as requested by target */
1328                         intel_get_adjust_train(intel_dp);
1329                 }
1330         }
1331
1332         intel_dp->DP = DP;
1333 }
1334
1335 static void
1336 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1337 {
1338         struct drm_device *dev = intel_dp->base.base.dev;
1339         struct drm_i915_private *dev_priv = dev->dev_private;
1340         bool channel_eq = false;
1341         int tries;
1342         u32 reg;
1343         uint32_t DP = intel_dp->DP;
1344
1345         /* channel equalization */
1346         tries = 0;
1347         channel_eq = false;
1348         for (;;) {
1349                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1350                 uint32_t    signal_levels;
1351
1352                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1353                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1354                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1355                 } else {
1356                         signal_levels = intel_dp_signal_levels(intel_dp);
1357                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1358                 }
1359
1360                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1361                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1362                 else
1363                         reg = DP | DP_LINK_TRAIN_PAT_2;
1364
1365                 /* channel eq pattern */
1366                 if (!intel_dp_set_link_train(intel_dp, reg,
1367                                              DP_TRAINING_PATTERN_2))
1368                         break;
1369
1370                 udelay(500);
1371
1372                 if (!intel_dp_aux_handshake_required(intel_dp)) {
1373                         break;
1374                 } else {
1375                         if (!intel_dp_get_link_status(intel_dp))
1376                                 break;
1377
1378                         if (intel_channel_eq_ok(intel_dp)) {
1379                                 channel_eq = true;
1380                                 break;
1381                         }
1382
1383                         /* Try 5 times */
1384                         if (tries > 5)
1385                                 break;
1386
1387                         /* Compute new intel_dp->train_set as requested by target */
1388                         intel_get_adjust_train(intel_dp);
1389                         ++tries;
1390                 }
1391         }
1392         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1393                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1394         else
1395                 reg = DP | DP_LINK_TRAIN_OFF;
1396
1397         I915_WRITE(intel_dp->output_reg, reg);
1398         POSTING_READ(intel_dp->output_reg);
1399         intel_dp_aux_native_write_1(intel_dp,
1400                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1401 }
1402
1403 static void
1404 intel_dp_link_down(struct intel_dp *intel_dp)
1405 {
1406         struct drm_device *dev = intel_dp->base.base.dev;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         uint32_t DP = intel_dp->DP;
1409
1410         DRM_DEBUG_KMS("\n");
1411
1412         if (is_edp(intel_dp)) {
1413                 DP &= ~DP_PLL_ENABLE;
1414                 I915_WRITE(intel_dp->output_reg, DP);
1415                 POSTING_READ(intel_dp->output_reg);
1416                 udelay(100);
1417         }
1418
1419         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1420                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1421                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1422         } else {
1423                 DP &= ~DP_LINK_TRAIN_MASK;
1424                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1425         }
1426         POSTING_READ(intel_dp->output_reg);
1427
1428         msleep(17);
1429
1430         if (is_edp(intel_dp))
1431                 DP |= DP_LINK_TRAIN_OFF;
1432         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1433         POSTING_READ(intel_dp->output_reg);
1434 }
1435
1436 /*
1437  * According to DP spec
1438  * 5.1.2:
1439  *  1. Read DPCD
1440  *  2. Configure link according to Receiver Capabilities
1441  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1442  *  4. Check link status on receipt of hot-plug interrupt
1443  */
1444
1445 static void
1446 intel_dp_check_link_status(struct intel_dp *intel_dp)
1447 {
1448         if (!intel_dp->base.base.crtc)
1449                 return;
1450
1451         if (!intel_dp_get_link_status(intel_dp)) {
1452                 intel_dp_link_down(intel_dp);
1453                 return;
1454         }
1455
1456         if (!intel_channel_eq_ok(intel_dp)) {
1457                 intel_dp_start_link_train(intel_dp);
1458                 intel_dp_complete_link_train(intel_dp);
1459         }
1460 }
1461
1462 static enum drm_connector_status
1463 ironlake_dp_detect(struct drm_connector *connector)
1464 {
1465         struct intel_dp *intel_dp = intel_attached_dp(connector);
1466         enum drm_connector_status status;
1467
1468         /* Can't disconnect eDP */
1469         if (is_edp(intel_dp))
1470                 return connector_status_connected;
1471
1472         status = connector_status_disconnected;
1473         if (intel_dp_aux_native_read(intel_dp,
1474                                      0x000, intel_dp->dpcd,
1475                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1476         {
1477                 if (intel_dp->dpcd[0] != 0)
1478                         status = connector_status_connected;
1479         }
1480         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1481                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1482         return status;
1483 }
1484
1485 /**
1486  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1487  *
1488  * \return true if DP port is connected.
1489  * \return false if DP port is disconnected.
1490  */
1491 static enum drm_connector_status
1492 intel_dp_detect(struct drm_connector *connector, bool force)
1493 {
1494         struct intel_dp *intel_dp = intel_attached_dp(connector);
1495         struct drm_device *dev = intel_dp->base.base.dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         uint32_t temp, bit;
1498         enum drm_connector_status status;
1499
1500         intel_dp->has_audio = false;
1501
1502         if (HAS_PCH_SPLIT(dev))
1503                 return ironlake_dp_detect(connector);
1504
1505         switch (intel_dp->output_reg) {
1506         case DP_B:
1507                 bit = DPB_HOTPLUG_INT_STATUS;
1508                 break;
1509         case DP_C:
1510                 bit = DPC_HOTPLUG_INT_STATUS;
1511                 break;
1512         case DP_D:
1513                 bit = DPD_HOTPLUG_INT_STATUS;
1514                 break;
1515         default:
1516                 return connector_status_unknown;
1517         }
1518
1519         temp = I915_READ(PORT_HOTPLUG_STAT);
1520
1521         if ((temp & bit) == 0)
1522                 return connector_status_disconnected;
1523
1524         status = connector_status_disconnected;
1525         if (intel_dp_aux_native_read(intel_dp,
1526                                      0x000, intel_dp->dpcd,
1527                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1528         {
1529                 if (intel_dp->dpcd[0] != 0)
1530                         status = connector_status_connected;
1531         }
1532         return status;
1533 }
1534
1535 static int intel_dp_get_modes(struct drm_connector *connector)
1536 {
1537         struct intel_dp *intel_dp = intel_attached_dp(connector);
1538         struct drm_device *dev = intel_dp->base.base.dev;
1539         struct drm_i915_private *dev_priv = dev->dev_private;
1540         int ret;
1541
1542         /* We should parse the EDID data and find out if it has an audio sink
1543          */
1544
1545         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1546         if (ret) {
1547                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1548                         struct drm_display_mode *newmode;
1549                         list_for_each_entry(newmode, &connector->probed_modes,
1550                                             head) {
1551                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1552                                         dev_priv->panel_fixed_mode =
1553                                                 drm_mode_duplicate(dev, newmode);
1554                                         break;
1555                                 }
1556                         }
1557                 }
1558
1559                 return ret;
1560         }
1561
1562         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1563         if (is_edp(intel_dp)) {
1564                 if (dev_priv->panel_fixed_mode != NULL) {
1565                         struct drm_display_mode *mode;
1566                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1567                         drm_mode_probed_add(connector, mode);
1568                         return 1;
1569                 }
1570         }
1571         return 0;
1572 }
1573
1574 static void
1575 intel_dp_destroy (struct drm_connector *connector)
1576 {
1577         drm_sysfs_connector_remove(connector);
1578         drm_connector_cleanup(connector);
1579         kfree(connector);
1580 }
1581
1582 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1583 {
1584         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1585
1586         i2c_del_adapter(&intel_dp->adapter);
1587         drm_encoder_cleanup(encoder);
1588         kfree(intel_dp);
1589 }
1590
1591 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1592         .dpms = intel_dp_dpms,
1593         .mode_fixup = intel_dp_mode_fixup,
1594         .prepare = intel_dp_prepare,
1595         .mode_set = intel_dp_mode_set,
1596         .commit = intel_dp_commit,
1597 };
1598
1599 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1600         .dpms = drm_helper_connector_dpms,
1601         .detect = intel_dp_detect,
1602         .fill_modes = drm_helper_probe_single_connector_modes,
1603         .destroy = intel_dp_destroy,
1604 };
1605
1606 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1607         .get_modes = intel_dp_get_modes,
1608         .mode_valid = intel_dp_mode_valid,
1609         .best_encoder = intel_best_encoder,
1610 };
1611
1612 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1613         .destroy = intel_dp_encoder_destroy,
1614 };
1615
1616 static void
1617 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1618 {
1619         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1620
1621         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1622                 intel_dp_check_link_status(intel_dp);
1623 }
1624
1625 /* Return which DP Port should be selected for Transcoder DP control */
1626 int
1627 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1628 {
1629         struct drm_device *dev = crtc->dev;
1630         struct drm_mode_config *mode_config = &dev->mode_config;
1631         struct drm_encoder *encoder;
1632
1633         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1634                 struct intel_dp *intel_dp;
1635
1636                 if (encoder->crtc != crtc)
1637                         continue;
1638
1639                 intel_dp = enc_to_intel_dp(encoder);
1640                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1641                         return intel_dp->output_reg;
1642         }
1643
1644         return -1;
1645 }
1646
1647 /* check the VBT to see whether the eDP is on DP-D port */
1648 bool intel_dpd_is_edp(struct drm_device *dev)
1649 {
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651         struct child_device_config *p_child;
1652         int i;
1653
1654         if (!dev_priv->child_dev_num)
1655                 return false;
1656
1657         for (i = 0; i < dev_priv->child_dev_num; i++) {
1658                 p_child = dev_priv->child_dev + i;
1659
1660                 if (p_child->dvo_port == PORT_IDPD &&
1661                     p_child->device_type == DEVICE_TYPE_eDP)
1662                         return true;
1663         }
1664         return false;
1665 }
1666
1667 void
1668 intel_dp_init(struct drm_device *dev, int output_reg)
1669 {
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         struct drm_connector *connector;
1672         struct intel_dp *intel_dp;
1673         struct intel_encoder *intel_encoder;
1674         struct intel_connector *intel_connector;
1675         const char *name = NULL;
1676         int type;
1677
1678         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1679         if (!intel_dp)
1680                 return;
1681
1682         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1683         if (!intel_connector) {
1684                 kfree(intel_dp);
1685                 return;
1686         }
1687         intel_encoder = &intel_dp->base;
1688
1689         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1690                 if (intel_dpd_is_edp(dev))
1691                         intel_dp->is_pch_edp = true;
1692
1693         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1694                 type = DRM_MODE_CONNECTOR_eDP;
1695                 intel_encoder->type = INTEL_OUTPUT_EDP;
1696         } else {
1697                 type = DRM_MODE_CONNECTOR_DisplayPort;
1698                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1699         }
1700
1701         connector = &intel_connector->base;
1702         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1703         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1704
1705         connector->polled = DRM_CONNECTOR_POLL_HPD;
1706
1707         if (output_reg == DP_B || output_reg == PCH_DP_B)
1708                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1709         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1710                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1711         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1712                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1713
1714         if (is_edp(intel_dp))
1715                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1716
1717         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1718         connector->interlace_allowed = true;
1719         connector->doublescan_allowed = 0;
1720
1721         intel_dp->output_reg = output_reg;
1722         intel_dp->has_audio = false;
1723         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1724
1725         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1726                          DRM_MODE_ENCODER_TMDS);
1727         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1728
1729         intel_connector_attach_encoder(intel_connector, intel_encoder);
1730         drm_sysfs_connector_add(connector);
1731
1732         /* Set up the DDC bus. */
1733         switch (output_reg) {
1734                 case DP_A:
1735                         name = "DPDDC-A";
1736                         break;
1737                 case DP_B:
1738                 case PCH_DP_B:
1739                         dev_priv->hotplug_supported_mask |=
1740                                 HDMIB_HOTPLUG_INT_STATUS;
1741                         name = "DPDDC-B";
1742                         break;
1743                 case DP_C:
1744                 case PCH_DP_C:
1745                         dev_priv->hotplug_supported_mask |=
1746                                 HDMIC_HOTPLUG_INT_STATUS;
1747                         name = "DPDDC-C";
1748                         break;
1749                 case DP_D:
1750                 case PCH_DP_D:
1751                         dev_priv->hotplug_supported_mask |=
1752                                 HDMID_HOTPLUG_INT_STATUS;
1753                         name = "DPDDC-D";
1754                         break;
1755         }
1756
1757         intel_dp_i2c_init(intel_dp, intel_connector, name);
1758
1759         /* Cache some DPCD data in the eDP case */
1760         if (is_edp(intel_dp)) {
1761                 int ret;
1762                 bool was_on;
1763
1764                 was_on = ironlake_edp_panel_on(intel_dp);
1765                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1766                                                intel_dp->dpcd,
1767                                                sizeof(intel_dp->dpcd));
1768                 if (ret == sizeof(intel_dp->dpcd)) {
1769                         if (intel_dp->dpcd[0] >= 0x11)
1770                                 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1771                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1772                 } else {
1773                         DRM_ERROR("failed to retrieve link info\n");
1774                 }
1775                 if (!was_on)
1776                         ironlake_edp_panel_off(dev);
1777         }
1778
1779         intel_encoder->hot_plug = intel_dp_hot_plug;
1780
1781         if (is_edp(intel_dp)) {
1782                 /* initialize panel mode from VBT if available for eDP */
1783                 if (dev_priv->lfp_lvds_vbt_mode) {
1784                         dev_priv->panel_fixed_mode =
1785                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1786                         if (dev_priv->panel_fixed_mode) {
1787                                 dev_priv->panel_fixed_mode->type |=
1788                                         DRM_MODE_TYPE_PREFERRED;
1789                         }
1790                 }
1791         }
1792
1793         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1794          * 0xd.  Failure to do so will result in spurious interrupts being
1795          * generated on the port when a cable is not attached.
1796          */
1797         if (IS_G4X(dev) && !IS_GM45(dev)) {
1798                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1799                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1800         }
1801 }