drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39 #define DP_RECEIVER_CAP_SIZE    0xf
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59         bool is_pch_edp;
  60         uint8_t train_set[4];
  61         int panel_power_up_delay;
  62         int panel_power_down_delay;
  63         int panel_power_cycle_delay;
  64         int backlight_on_delay;
  65         int backlight_off_delay;
  66         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  67         struct delayed_work panel_vdd_work;
  68         bool want_panel_vdd;
  69         unsigned long panel_off_jiffies;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = 4;
 159
 160         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 161                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 162                 switch (max_lane_count) {
 163                 case 1: case 2: case 4:
 164                         break;
 165                 default:
 166                         max_lane_count = 4;
 167                 }
 168         }
 169         return max_lane_count;
 170 }
 171
 172 static int
 173 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 174 {
 175         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 176
 177         switch (max_link_bw) {
 178         case DP_LINK_BW_1_62:
 179         case DP_LINK_BW_2_7:
 180                 break;
 181         default:
 182                 max_link_bw = DP_LINK_BW_1_62;
 183                 break;
 184         }
 185         return max_link_bw;
 186 }
 187
 188 static int
 189 intel_dp_link_clock(uint8_t link_bw)
 190 {
 191         if (link_bw == DP_LINK_BW_2_7)
 192                 return 270000;
 193         else
 194                 return 162000;
 195 }
 196
 197 /*
 198  * The units on the numbers in the next two are... bizarre.  Examples will
 199  * make it clearer; this one parallels an example in the eDP spec.
 200  *
 201  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 202  *
 203  *     270000 * 1 * 8 / 10 == 216000
 204  *
 205  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 206  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 207  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 208  * 119000.  At 18bpp that's 2142000 kilobits per second.
 209  *
 210  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 211  * get the result in decakilobits instead of kilobits.
 212  */
 213
 214 static int
 215 intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
 216 {
 217         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 219         int bpp = 24;
 220
 221         if (intel_crtc)
 222                 bpp = intel_crtc->bpp;
 223
 224         return (pixel_clock * bpp + 9) / 10;
 225 }
 226
 227 static int
 228 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 229 {
 230         return (max_link_clock * max_lanes * 8) / 10;
 231 }
 232
 233 static int
 234 intel_dp_mode_valid(struct drm_connector *connector,
 235                     struct drm_display_mode *mode)
 236 {
 237         struct intel_dp *intel_dp = intel_attached_dp(connector);
 238         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 239         int max_lanes = intel_dp_max_lane_count(intel_dp);
 240
 241         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 242                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 243                         return MODE_PANEL;
 244
 245                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 246                         return MODE_PANEL;
 247         }
 248
 249         if (intel_dp_link_required(intel_dp, mode->clock)
 250             > intel_dp_max_data_rate(max_link_clock, max_lanes))
 251                 return MODE_CLOCK_HIGH;
 252
 253         if (mode->clock < 10000)
 254                 return MODE_CLOCK_LOW;
 255
 256         return MODE_OK;
 257 }
 258
 259 static uint32_t
 260 pack_aux(uint8_t *src, int src_bytes)
 261 {
 262         int     i;
 263         uint32_t v = 0;
 264
 265         if (src_bytes > 4)
 266                 src_bytes = 4;
 267         for (i = 0; i < src_bytes; i++)
 268                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 269         return v;
 270 }
 271
 272 static void
 273 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 274 {
 275         int i;
 276         if (dst_bytes > 4)
 277                 dst_bytes = 4;
 278         for (i = 0; i < dst_bytes; i++)
 279                 dst[i] = src >> ((3-i) * 8);
 280 }
 281
 282 /* hrawclock is 1/4 the FSB frequency */
 283 static int
 284 intel_hrawclk(struct drm_device *dev)
 285 {
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         uint32_t clkcfg;
 288
 289         clkcfg = I915_READ(CLKCFG);
 290         switch (clkcfg & CLKCFG_FSB_MASK) {
 291         case CLKCFG_FSB_400:
 292                 return 100;
 293         case CLKCFG_FSB_533:
 294                 return 133;
 295         case CLKCFG_FSB_667:
 296                 return 166;
 297         case CLKCFG_FSB_800:
 298                 return 200;
 299         case CLKCFG_FSB_1067:
 300                 return 266;
 301         case CLKCFG_FSB_1333:
 302                 return 333;
 303         /* these two are just a guess; one of them might be right */
 304         case CLKCFG_FSB_1600:
 305         case CLKCFG_FSB_1600_ALT:
 306                 return 400;
 307         default:
 308                 return 133;
 309         }
 310 }
 311
 312 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 313 {
 314         struct drm_device *dev = intel_dp->base.base.dev;
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 318 }
 319
 320 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 321 {
 322         struct drm_device *dev = intel_dp->base.base.dev;
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324
 325         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 326 }
 327
 328 static void
 329 intel_dp_check_edp(struct intel_dp *intel_dp)
 330 {
 331         struct drm_device *dev = intel_dp->base.base.dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         if (!is_edp(intel_dp))
 335                 return;
 336         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 337                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 338                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 339                               I915_READ(PCH_PP_STATUS),
 340                               I915_READ(PCH_PP_CONTROL));
 341         }
 342 }
 343
 344 static int
 345 intel_dp_aux_ch(struct intel_dp *intel_dp,
 346                 uint8_t *send, int send_bytes,
 347                 uint8_t *recv, int recv_size)
 348 {
 349         uint32_t output_reg = intel_dp->output_reg;
 350         struct drm_device *dev = intel_dp->base.base.dev;
 351         struct drm_i915_private *dev_priv = dev->dev_private;
 352         uint32_t ch_ctl = output_reg + 0x10;
 353         uint32_t ch_data = ch_ctl + 4;
 354         int i;
 355         int recv_bytes;
 356         uint32_t status;
 357         uint32_t aux_clock_divider;
 358         int try, precharge;
 359
 360         intel_dp_check_edp(intel_dp);
 361         /* The clock divider is based off the hrawclk,
 362          * and would like to run at 2MHz. So, take the
 363          * hrawclk value and divide by 2 and use that
 364          *
 365          * Note that PCH attached eDP panels should use a 125MHz input
 366          * clock divider.
 367          */
 368         if (is_cpu_edp(intel_dp)) {
 369                 if (IS_GEN6(dev))
 370                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 371                 else
 372                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 373         } else if (HAS_PCH_SPLIT(dev))
 374                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 375         else
 376                 aux_clock_divider = intel_hrawclk(dev) / 2;
 377
 378         if (IS_GEN6(dev))
 379                 precharge = 3;
 380         else
 381                 precharge = 5;
 382
 383         /* Try to wait for any previous AUX channel activity */
 384         for (try = 0; try < 3; try++) {
 385                 status = I915_READ(ch_ctl);
 386                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 387                         break;
 388                 msleep(1);
 389         }
 390
 391         if (try == 3) {
 392                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 393                      I915_READ(ch_ctl));
 394                 return -EBUSY;
 395         }
 396
 397         /* Must try at least 3 times according to DP spec */
 398         for (try = 0; try < 5; try++) {
 399                 /* Load the send data into the aux channel data registers */
 400                 for (i = 0; i < send_bytes; i += 4)
 401                         I915_WRITE(ch_data + i,
 402                                    pack_aux(send + i, send_bytes - i));
 403
 404                 /* Send the command and wait for it to complete */
 405                 I915_WRITE(ch_ctl,
 406                            DP_AUX_CH_CTL_SEND_BUSY |
 407                            DP_AUX_CH_CTL_TIME_OUT_400us |
 408                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 409                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 410                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 411                            DP_AUX_CH_CTL_DONE |
 412                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 413                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 414                 for (;;) {
 415                         status = I915_READ(ch_ctl);
 416                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 417                                 break;
 418                         udelay(100);
 419                 }
 420
 421                 /* Clear done status and any errors */
 422                 I915_WRITE(ch_ctl,
 423                            status |
 424                            DP_AUX_CH_CTL_DONE |
 425                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 426                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 427                 if (status & DP_AUX_CH_CTL_DONE)
 428                         break;
 429         }
 430
 431         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 432                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 433                 return -EBUSY;
 434         }
 435
 436         /* Check for timeout or receive error.
 437          * Timeouts occur when the sink is not connected
 438          */
 439         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 440                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 441                 return -EIO;
 442         }
 443
 444         /* Timeouts occur when the device isn't connected, so they're
 445          * "normal" -- don't fill the kernel log with these */
 446         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 447                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 448                 return -ETIMEDOUT;
 449         }
 450
 451         /* Unload any bytes sent back from the other side */
 452         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 453                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 454         if (recv_bytes > recv_size)
 455                 recv_bytes = recv_size;
 456
 457         for (i = 0; i < recv_bytes; i += 4)
 458                 unpack_aux(I915_READ(ch_data + i),
 459                            recv + i, recv_bytes - i);
 460
 461         return recv_bytes;
 462 }
 463
 464 /* Write data to the aux channel in native mode */
 465 static int
 466 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 467                           uint16_t address, uint8_t *send, int send_bytes)
 468 {
 469         int ret;
 470         uint8_t msg[20];
 471         int msg_bytes;
 472         uint8_t ack;
 473
 474         intel_dp_check_edp(intel_dp);
 475         if (send_bytes > 16)
 476                 return -1;
 477         msg[0] = AUX_NATIVE_WRITE << 4;
 478         msg[1] = address >> 8;
 479         msg[2] = address & 0xff;
 480         msg[3] = send_bytes - 1;
 481         memcpy(&msg[4], send, send_bytes);
 482         msg_bytes = send_bytes + 4;
 483         for (;;) {
 484                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 485                 if (ret < 0)
 486                         return ret;
 487                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 488                         break;
 489                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 490                         udelay(100);
 491                 else
 492                         return -EIO;
 493         }
 494         return send_bytes;
 495 }
 496
 497 /* Write a single byte to the aux channel in native mode */
 498 static int
 499 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 500                             uint16_t address, uint8_t byte)
 501 {
 502         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 503 }
 504
 505 /* read bytes from a native aux channel */
 506 static int
 507 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 508                          uint16_t address, uint8_t *recv, int recv_bytes)
 509 {
 510         uint8_t msg[4];
 511         int msg_bytes;
 512         uint8_t reply[20];
 513         int reply_bytes;
 514         uint8_t ack;
 515         int ret;
 516
 517         intel_dp_check_edp(intel_dp);
 518         msg[0] = AUX_NATIVE_READ << 4;
 519         msg[1] = address >> 8;
 520         msg[2] = address & 0xff;
 521         msg[3] = recv_bytes - 1;
 522
 523         msg_bytes = 4;
 524         reply_bytes = recv_bytes + 1;
 525
 526         for (;;) {
 527                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 528                                       reply, reply_bytes);
 529                 if (ret == 0)
 530                         return -EPROTO;
 531                 if (ret < 0)
 532                         return ret;
 533                 ack = reply[0];
 534                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 535                         memcpy(recv, reply + 1, ret - 1);
 536                         return ret - 1;
 537                 }
 538                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 539                         udelay(100);
 540                 else
 541                         return -EIO;
 542         }
 543 }
 544
 545 static int
 546 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 547                     uint8_t write_byte, uint8_t *read_byte)
 548 {
 549         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 550         struct intel_dp *intel_dp = container_of(adapter,
 551                                                 struct intel_dp,
 552                                                 adapter);
 553         uint16_t address = algo_data->address;
 554         uint8_t msg[5];
 555         uint8_t reply[2];
 556         unsigned retry;
 557         int msg_bytes;
 558         int reply_bytes;
 559         int ret;
 560
 561         intel_dp_check_edp(intel_dp);
 562         /* Set up the command byte */
 563         if (mode & MODE_I2C_READ)
 564                 msg[0] = AUX_I2C_READ << 4;
 565         else
 566                 msg[0] = AUX_I2C_WRITE << 4;
 567
 568         if (!(mode & MODE_I2C_STOP))
 569                 msg[0] |= AUX_I2C_MOT << 4;
 570
 571         msg[1] = address >> 8;
 572         msg[2] = address;
 573
 574         switch (mode) {
 575         case MODE_I2C_WRITE:
 576                 msg[3] = 0;
 577                 msg[4] = write_byte;
 578                 msg_bytes = 5;
 579                 reply_bytes = 1;
 580                 break;
 581         case MODE_I2C_READ:
 582                 msg[3] = 0;
 583                 msg_bytes = 4;
 584                 reply_bytes = 2;
 585                 break;
 586         default:
 587                 msg_bytes = 3;
 588                 reply_bytes = 1;
 589                 break;
 590         }
 591
 592         for (retry = 0; retry < 5; retry++) {
 593                 ret = intel_dp_aux_ch(intel_dp,
 594                                       msg, msg_bytes,
 595                                       reply, reply_bytes);
 596                 if (ret < 0) {
 597                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 598                         return ret;
 599                 }
 600
 601                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 602                 case AUX_NATIVE_REPLY_ACK:
 603                         /* I2C-over-AUX Reply field is only valid
 604                          * when paired with AUX ACK.
 605                          */
 606                         break;
 607                 case AUX_NATIVE_REPLY_NACK:
 608                         DRM_DEBUG_KMS("aux_ch native nack\n");
 609                         return -EREMOTEIO;
 610                 case AUX_NATIVE_REPLY_DEFER:
 611                         udelay(100);
 612                         continue;
 613                 default:
 614                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 615                                   reply[0]);
 616                         return -EREMOTEIO;
 617                 }
 618
 619                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 620                 case AUX_I2C_REPLY_ACK:
 621                         if (mode == MODE_I2C_READ) {
 622                                 *read_byte = reply[1];
 623                         }
 624                         return reply_bytes - 1;
 625                 case AUX_I2C_REPLY_NACK:
 626                         DRM_DEBUG_KMS("aux_i2c nack\n");
 627                         return -EREMOTEIO;
 628                 case AUX_I2C_REPLY_DEFER:
 629                         DRM_DEBUG_KMS("aux_i2c defer\n");
 630                         udelay(100);
 631                         break;
 632                 default:
 633                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 634                         return -EREMOTEIO;
 635                 }
 636         }
 637
 638         DRM_ERROR("too many retries, giving up\n");
 639         return -EREMOTEIO;
 640 }
 641
 642 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 643 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 644
 645 static int
 646 intel_dp_i2c_init(struct intel_dp *intel_dp,
 647                   struct intel_connector *intel_connector, const char *name)
 648 {
 649         int     ret;
 650
 651         DRM_DEBUG_KMS("i2c_init %s\n", name);
 652         intel_dp->algo.running = false;
 653         intel_dp->algo.address = 0;
 654         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 655
 656         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 657         intel_dp->adapter.owner = THIS_MODULE;
 658         intel_dp->adapter.class = I2C_CLASS_DDC;
 659         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 660         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 661         intel_dp->adapter.algo_data = &intel_dp->algo;
 662         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 663
 664         ironlake_edp_panel_vdd_on(intel_dp);
 665         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 666         ironlake_edp_panel_vdd_off(intel_dp, false);
 667         return ret;
 668 }
 669
 670 static bool
 671 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 672                     struct drm_display_mode *adjusted_mode)
 673 {
 674         struct drm_device *dev = encoder->dev;
 675         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 676         int lane_count, clock;
 677         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 678         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 679         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 680
 681         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 682                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 683                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 684                                         mode, adjusted_mode);
 685                 /*
 686                  * the mode->clock is used to calculate the Data&Link M/N
 687                  * of the pipe. For the eDP the fixed clock should be used.
 688                  */
 689                 mode->clock = intel_dp->panel_fixed_mode->clock;
 690         }
 691
 692         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 693                 for (clock = 0; clock <= max_clock; clock++) {
 694                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 695
 696                         if (intel_dp_link_required(intel_dp, mode->clock)
 697                                         <= link_avail) {
 698                                 intel_dp->link_bw = bws[clock];
 699                                 intel_dp->lane_count = lane_count;
 700                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 701                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 702                                                 "count %d clock %d\n",
 703                                        intel_dp->link_bw, intel_dp->lane_count,
 704                                        adjusted_mode->clock);
 705                                 return true;
 706                         }
 707                 }
 708         }
 709
 710         return false;
 711 }
 712
 713 struct intel_dp_m_n {
 714         uint32_t        tu;
 715         uint32_t        gmch_m;
 716         uint32_t        gmch_n;
 717         uint32_t        link_m;
 718         uint32_t        link_n;
 719 };
 720
 721 static void
 722 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 723 {
 724         while (*num > 0xffffff || *den > 0xffffff) {
 725                 *num >>= 1;
 726                 *den >>= 1;
 727         }
 728 }
 729
 730 static void
 731 intel_dp_compute_m_n(int bpp,
 732                      int nlanes,
 733                      int pixel_clock,
 734                      int link_clock,
 735                      struct intel_dp_m_n *m_n)
 736 {
 737         m_n->tu = 64;
 738         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 739         m_n->gmch_n = link_clock * nlanes;
 740         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 741         m_n->link_m = pixel_clock;
 742         m_n->link_n = link_clock;
 743         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 744 }
 745
 746 void
 747 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 748                  struct drm_display_mode *adjusted_mode)
 749 {
 750         struct drm_device *dev = crtc->dev;
 751         struct drm_mode_config *mode_config = &dev->mode_config;
 752         struct drm_encoder *encoder;
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 755         int lane_count = 4;
 756         struct intel_dp_m_n m_n;
 757         int pipe = intel_crtc->pipe;
 758
 759         /*
 760          * Find the lane count in the intel_encoder private
 761          */
 762         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 763                 struct intel_dp *intel_dp;
 764
 765                 if (encoder->crtc != crtc)
 766                         continue;
 767
 768                 intel_dp = enc_to_intel_dp(encoder);
 769                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 770                         lane_count = intel_dp->lane_count;
 771                         break;
 772                 } else if (is_edp(intel_dp)) {
 773                         lane_count = dev_priv->edp.lanes;
 774                         break;
 775                 }
 776         }
 777
 778         /*
 779          * Compute the GMCH and Link ratios. The '3' here is
 780          * the number of bytes_per_pixel post-LUT, which we always
 781          * set up for 8-bits of R/G/B, or 3 bytes total.
 782          */
 783         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 784                              mode->clock, adjusted_mode->clock, &m_n);
 785
 786         if (HAS_PCH_SPLIT(dev)) {
 787                 I915_WRITE(TRANSDATA_M1(pipe),
 788                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 789                            m_n.gmch_m);
 790                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 791                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 792                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 793         } else {
 794                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 795                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 796                            m_n.gmch_m);
 797                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 798                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 799                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 800         }
 801 }
 802
 803 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 804 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 805
 806 static void
 807 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 808                   struct drm_display_mode *adjusted_mode)
 809 {
 810         struct drm_device *dev = encoder->dev;
 811         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 812         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 814
 815         /* Turn on the eDP PLL if needed */
 816         if (is_edp(intel_dp)) {
 817                 if (!is_pch_edp(intel_dp))
 818                         ironlake_edp_pll_on(encoder);
 819                 else
 820                         ironlake_edp_pll_off(encoder);
 821         }
 822
 823         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 824         intel_dp->DP |= intel_dp->color_range;
 825
 826         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 827                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 828         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 829                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 830
 831         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
 832                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 833         else
 834                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 835
 836         switch (intel_dp->lane_count) {
 837         case 1:
 838                 intel_dp->DP |= DP_PORT_WIDTH_1;
 839                 break;
 840         case 2:
 841                 intel_dp->DP |= DP_PORT_WIDTH_2;
 842                 break;
 843         case 4:
 844                 intel_dp->DP |= DP_PORT_WIDTH_4;
 845                 break;
 846         }
 847         if (intel_dp->has_audio) {
 848                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 849                                  pipe_name(intel_crtc->pipe));
 850                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 851                 intel_write_eld(encoder, adjusted_mode);
 852         }
 853
 854         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 855         intel_dp->link_configuration[0] = intel_dp->link_bw;
 856         intel_dp->link_configuration[1] = intel_dp->lane_count;
 857         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 858
 859         /*
 860          * Check for DPCD version > 1.1 and enhanced framing support
 861          */
 862         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 863             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 864                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 865                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 866         }
 867
 868         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 869         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 870                 intel_dp->DP |= DP_PIPEB_SELECT;
 871
 872         if (is_cpu_edp(intel_dp)) {
 873                 /* don't miss out required setting for eDP */
 874                 intel_dp->DP |= DP_PLL_ENABLE;
 875                 if (adjusted_mode->clock < 200000)
 876                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 877                 else
 878                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 879         }
 880 }
 881
 882 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 883 {
 884         unsigned long   off_time;
 885         unsigned long   delay;
 886
 887         DRM_DEBUG_KMS("Wait for panel power off time\n");
 888
 889         if (ironlake_edp_have_panel_power(intel_dp) ||
 890             ironlake_edp_have_panel_vdd(intel_dp))
 891         {
 892                 DRM_DEBUG_KMS("Panel still on, no delay needed\n");
 893                 return;
 894         }
 895
 896         off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay);
 897         if (time_after(jiffies, off_time)) {
 898                 DRM_DEBUG_KMS("Time already passed");
 899                 return;
 900         }
 901         delay = jiffies_to_msecs(off_time - jiffies);
 902         if (delay > intel_dp->panel_power_down_delay)
 903                 delay = intel_dp->panel_power_down_delay;
 904         DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
 905         msleep(delay);
 906 }
 907
 908 /* Read the current pp_control value, unlocking the register if it
 909  * is locked
 910  */
 911
 912 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 913 {
 914         u32     control = I915_READ(PCH_PP_CONTROL);
 915
 916         control &= ~PANEL_UNLOCK_MASK;
 917         control |= PANEL_UNLOCK_REGS;
 918         return control;
 919 }
 920
 921 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 922 {
 923         struct drm_device *dev = intel_dp->base.base.dev;
 924         struct drm_i915_private *dev_priv = dev->dev_private;
 925         u32 pp;
 926
 927         if (!is_edp(intel_dp))
 928                 return;
 929         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 930
 931         WARN(intel_dp->want_panel_vdd,
 932              "eDP VDD already requested on\n");
 933
 934         intel_dp->want_panel_vdd = true;
 935         if (ironlake_edp_have_panel_vdd(intel_dp)) {
 936                 DRM_DEBUG_KMS("eDP VDD already on\n");
 937                 return;
 938         }
 939
 940         ironlake_wait_panel_off(intel_dp);
 941         pp = ironlake_get_pp_control(dev_priv);
 942         pp |= EDP_FORCE_VDD;
 943         I915_WRITE(PCH_PP_CONTROL, pp);
 944         POSTING_READ(PCH_PP_CONTROL);
 945         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 946                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 947
 948         /*
 949          * If the panel wasn't on, delay before accessing aux channel
 950          */
 951         if (!ironlake_edp_have_panel_power(intel_dp)) {
 952                 DRM_DEBUG_KMS("eDP was not running\n");
 953                 msleep(intel_dp->panel_power_up_delay);
 954         }
 955 }
 956
 957 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
 958 {
 959         struct drm_device *dev = intel_dp->base.base.dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         u32 pp;
 962
 963         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
 964                 pp = ironlake_get_pp_control(dev_priv);
 965                 pp &= ~EDP_FORCE_VDD;
 966                 I915_WRITE(PCH_PP_CONTROL, pp);
 967                 POSTING_READ(PCH_PP_CONTROL);
 968
 969                 /* Make sure sequencer is idle before allowing subsequent activity */
 970                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 971                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 972                 intel_dp->panel_off_jiffies = jiffies;
 973         }
 974 }
 975
 976 static void ironlake_panel_vdd_work(struct work_struct *__work)
 977 {
 978         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
 979                                                  struct intel_dp, panel_vdd_work);
 980         struct drm_device *dev = intel_dp->base.base.dev;
 981
 982         mutex_lock(&dev->mode_config.mutex);
 983         ironlake_panel_vdd_off_sync(intel_dp);
 984         mutex_unlock(&dev->mode_config.mutex);
 985 }
 986
 987 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 988 {
 989         if (!is_edp(intel_dp))
 990                 return;
 991
 992         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
 993         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
 994
 995         intel_dp->want_panel_vdd = false;
 996
 997         if (sync) {
 998                 ironlake_panel_vdd_off_sync(intel_dp);
 999         } else {
1000                 /*
1001                  * Queue the timer to fire a long
1002                  * time from now (relative to the power down delay)
1003                  * to keep the panel power up across a sequence of operations
1004                  */
1005                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1006                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1007         }
1008 }
1009
1010 /* Returns true if the panel was already on when called */
1011 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1012 {
1013         struct drm_device *dev = intel_dp->base.base.dev;
1014         struct drm_i915_private *dev_priv = dev->dev_private;
1015         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
1016
1017         if (!is_edp(intel_dp))
1018                 return;
1019         if (ironlake_edp_have_panel_power(intel_dp))
1020                 return;
1021
1022         ironlake_wait_panel_off(intel_dp);
1023         pp = ironlake_get_pp_control(dev_priv);
1024
1025         if (IS_GEN5(dev)) {
1026                 /* ILK workaround: disable reset around power sequence */
1027                 pp &= ~PANEL_POWER_RESET;
1028                 I915_WRITE(PCH_PP_CONTROL, pp);
1029                 POSTING_READ(PCH_PP_CONTROL);
1030         }
1031
1032         pp |= POWER_TARGET_ON;
1033         I915_WRITE(PCH_PP_CONTROL, pp);
1034         POSTING_READ(PCH_PP_CONTROL);
1035
1036         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
1037                      5000))
1038                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
1039                           I915_READ(PCH_PP_STATUS));
1040
1041         if (IS_GEN5(dev)) {
1042                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1043                 I915_WRITE(PCH_PP_CONTROL, pp);
1044                 POSTING_READ(PCH_PP_CONTROL);
1045         }
1046 }
1047
1048 static void ironlake_edp_panel_off(struct drm_encoder *encoder)
1049 {
1050         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1051         struct drm_device *dev = encoder->dev;
1052         struct drm_i915_private *dev_priv = dev->dev_private;
1053         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
1054                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
1055
1056         if (!is_edp(intel_dp))
1057                 return;
1058         pp = ironlake_get_pp_control(dev_priv);
1059
1060         if (IS_GEN5(dev)) {
1061                 /* ILK workaround: disable reset around power sequence */
1062                 pp &= ~PANEL_POWER_RESET;
1063                 I915_WRITE(PCH_PP_CONTROL, pp);
1064                 POSTING_READ(PCH_PP_CONTROL);
1065         }
1066
1067         intel_dp->panel_off_jiffies = jiffies;
1068
1069         if (IS_GEN5(dev)) {
1070                 pp &= ~POWER_TARGET_ON;
1071                 I915_WRITE(PCH_PP_CONTROL, pp);
1072                 POSTING_READ(PCH_PP_CONTROL);
1073                 pp &= ~POWER_TARGET_ON;
1074                 I915_WRITE(PCH_PP_CONTROL, pp);
1075                 POSTING_READ(PCH_PP_CONTROL);
1076                 msleep(intel_dp->panel_power_cycle_delay);
1077
1078                 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
1079                         DRM_ERROR("panel off wait timed out: 0x%08x\n",
1080                                   I915_READ(PCH_PP_STATUS));
1081
1082                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1083                 I915_WRITE(PCH_PP_CONTROL, pp);
1084                 POSTING_READ(PCH_PP_CONTROL);
1085         }
1086 }
1087
1088 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1089 {
1090         struct drm_device *dev = intel_dp->base.base.dev;
1091         struct drm_i915_private *dev_priv = dev->dev_private;
1092         u32 pp;
1093
1094         if (!is_edp(intel_dp))
1095                 return;
1096
1097         DRM_DEBUG_KMS("\n");
1098         /*
1099          * If we enable the backlight right away following a panel power
1100          * on, we may see slight flicker as the panel syncs with the eDP
1101          * link.  So delay a bit to make sure the image is solid before
1102          * allowing it to appear.
1103          */
1104         msleep(intel_dp->backlight_on_delay);
1105         pp = ironlake_get_pp_control(dev_priv);
1106         pp |= EDP_BLC_ENABLE;
1107         I915_WRITE(PCH_PP_CONTROL, pp);
1108         POSTING_READ(PCH_PP_CONTROL);
1109 }
1110
1111 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1112 {
1113         struct drm_device *dev = intel_dp->base.base.dev;
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         u32 pp;
1116
1117         if (!is_edp(intel_dp))
1118                 return;
1119
1120         DRM_DEBUG_KMS("\n");
1121         pp = ironlake_get_pp_control(dev_priv);
1122         pp &= ~EDP_BLC_ENABLE;
1123         I915_WRITE(PCH_PP_CONTROL, pp);
1124         POSTING_READ(PCH_PP_CONTROL);
1125         msleep(intel_dp->backlight_off_delay);
1126 }
1127
1128 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1129 {
1130         struct drm_device *dev = encoder->dev;
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132         u32 dpa_ctl;
1133
1134         DRM_DEBUG_KMS("\n");
1135         dpa_ctl = I915_READ(DP_A);
1136         dpa_ctl |= DP_PLL_ENABLE;
1137         I915_WRITE(DP_A, dpa_ctl);
1138         POSTING_READ(DP_A);
1139         udelay(200);
1140 }
1141
1142 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1143 {
1144         struct drm_device *dev = encoder->dev;
1145         struct drm_i915_private *dev_priv = dev->dev_private;
1146         u32 dpa_ctl;
1147
1148         dpa_ctl = I915_READ(DP_A);
1149         dpa_ctl &= ~DP_PLL_ENABLE;
1150         I915_WRITE(DP_A, dpa_ctl);
1151         POSTING_READ(DP_A);
1152         udelay(200);
1153 }
1154
1155 /* If the sink supports it, try to set the power state appropriately */
1156 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1157 {
1158         int ret, i;
1159
1160         /* Should have a valid DPCD by this point */
1161         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1162                 return;
1163
1164         if (mode != DRM_MODE_DPMS_ON) {
1165                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1166                                                   DP_SET_POWER_D3);
1167                 if (ret != 1)
1168                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1169         } else {
1170                 /*
1171                  * When turning on, we need to retry for 1ms to give the sink
1172                  * time to wake up.
1173                  */
1174                 for (i = 0; i < 3; i++) {
1175                         ret = intel_dp_aux_native_write_1(intel_dp,
1176                                                           DP_SET_POWER,
1177                                                           DP_SET_POWER_D0);
1178                         if (ret == 1)
1179                                 break;
1180                         msleep(1);
1181                 }
1182         }
1183 }
1184
1185 static void intel_dp_prepare(struct drm_encoder *encoder)
1186 {
1187         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1188
1189         /* Wake up the sink first */
1190         ironlake_edp_panel_vdd_on(intel_dp);
1191         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1192         ironlake_edp_panel_vdd_off(intel_dp, false);
1193
1194         /* Make sure the panel is off before trying to
1195          * change the mode
1196          */
1197         ironlake_edp_backlight_off(intel_dp);
1198         intel_dp_link_down(intel_dp);
1199         ironlake_edp_panel_off(encoder);
1200 }
1201
1202 static void intel_dp_commit(struct drm_encoder *encoder)
1203 {
1204         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1205         struct drm_device *dev = encoder->dev;
1206         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1207
1208         ironlake_edp_panel_vdd_on(intel_dp);
1209         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1210         intel_dp_start_link_train(intel_dp);
1211         ironlake_edp_panel_on(intel_dp);
1212         ironlake_edp_panel_vdd_off(intel_dp, true);
1213
1214         intel_dp_complete_link_train(intel_dp);
1215         ironlake_edp_backlight_on(intel_dp);
1216
1217         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1218
1219         if (HAS_PCH_CPT(dev))
1220                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1221 }
1222
1223 static void
1224 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1225 {
1226         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1227         struct drm_device *dev = encoder->dev;
1228         struct drm_i915_private *dev_priv = dev->dev_private;
1229         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1230
1231         if (mode != DRM_MODE_DPMS_ON) {
1232                 ironlake_edp_panel_vdd_on(intel_dp);
1233                 if (is_edp(intel_dp))
1234                         ironlake_edp_backlight_off(intel_dp);
1235                 intel_dp_sink_dpms(intel_dp, mode);
1236                 intel_dp_link_down(intel_dp);
1237                 ironlake_edp_panel_off(encoder);
1238                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1239                         ironlake_edp_pll_off(encoder);
1240                 ironlake_edp_panel_vdd_off(intel_dp, false);
1241         } else {
1242                 ironlake_edp_panel_vdd_on(intel_dp);
1243                 intel_dp_sink_dpms(intel_dp, mode);
1244                 if (!(dp_reg & DP_PORT_EN)) {
1245                         intel_dp_start_link_train(intel_dp);
1246                         ironlake_edp_panel_on(intel_dp);
1247                         ironlake_edp_panel_vdd_off(intel_dp, true);
1248                         intel_dp_complete_link_train(intel_dp);
1249                         ironlake_edp_backlight_on(intel_dp);
1250                 } else
1251                         ironlake_edp_panel_vdd_off(intel_dp, false);
1252                 ironlake_edp_backlight_on(intel_dp);
1253         }
1254         intel_dp->dpms_mode = mode;
1255 }
1256
1257 /*
1258  * Native read with retry for link status and receiver capability reads for
1259  * cases where the sink may still be asleep.
1260  */
1261 static bool
1262 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1263                                uint8_t *recv, int recv_bytes)
1264 {
1265         int ret, i;
1266
1267         /*
1268          * Sinks are *supposed* to come up within 1ms from an off state,
1269          * but we're also supposed to retry 3 times per the spec.
1270          */
1271         for (i = 0; i < 3; i++) {
1272                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1273                                                recv_bytes);
1274                 if (ret == recv_bytes)
1275                         return true;
1276                 msleep(1);
1277         }
1278
1279         return false;
1280 }
1281
1282 /*
1283  * Fetch AUX CH registers 0x202 - 0x207 which contain
1284  * link status information
1285  */
1286 static bool
1287 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1288 {
1289         return intel_dp_aux_native_read_retry(intel_dp,
1290                                               DP_LANE0_1_STATUS,
1291                                               link_status,
1292                                               DP_LINK_STATUS_SIZE);
1293 }
1294
1295 static uint8_t
1296 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1297                      int r)
1298 {
1299         return link_status[r - DP_LANE0_1_STATUS];
1300 }
1301
1302 static uint8_t
1303 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1304                                  int lane)
1305 {
1306         int         s = ((lane & 1) ?
1307                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1308                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1309         uint8_t l = adjust_request[lane>>1];
1310
1311         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1312 }
1313
1314 static uint8_t
1315 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1316                                       int lane)
1317 {
1318         int         s = ((lane & 1) ?
1319                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1320                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1321         uint8_t l = adjust_request[lane>>1];
1322
1323         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1324 }
1325
1326
1327 #if 0
1328 static char     *voltage_names[] = {
1329         "0.4V", "0.6V", "0.8V", "1.2V"
1330 };
1331 static char     *pre_emph_names[] = {
1332         "0dB", "3.5dB", "6dB", "9.5dB"
1333 };
1334 static char     *link_train_names[] = {
1335         "pattern 1", "pattern 2", "idle", "off"
1336 };
1337 #endif
1338
1339 /*
1340  * These are source-specific values; current Intel hardware supports
1341  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1342  */
1343 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1344
1345 static uint8_t
1346 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1347 {
1348         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1349         case DP_TRAIN_VOLTAGE_SWING_400:
1350                 return DP_TRAIN_PRE_EMPHASIS_6;
1351         case DP_TRAIN_VOLTAGE_SWING_600:
1352                 return DP_TRAIN_PRE_EMPHASIS_6;
1353         case DP_TRAIN_VOLTAGE_SWING_800:
1354                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1355         case DP_TRAIN_VOLTAGE_SWING_1200:
1356         default:
1357                 return DP_TRAIN_PRE_EMPHASIS_0;
1358         }
1359 }
1360
1361 static void
1362 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1363 {
1364         struct drm_device *dev = intel_dp->base.base.dev;
1365         uint8_t v = 0;
1366         uint8_t p = 0;
1367         int lane;
1368         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1369         int voltage_max;
1370
1371         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1372                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1373                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1374
1375                 if (this_v > v)
1376                         v = this_v;
1377                 if (this_p > p)
1378                         p = this_p;
1379         }
1380
1381         if (v >= I830_DP_VOLTAGE_MAX)
1382                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1383
1384         if (p >= intel_dp_pre_emphasis_max(v))
1385                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1386
1387         for (lane = 0; lane < 4; lane++)
1388                 intel_dp->train_set[lane] = v | p;
1389 }
1390
1391 static uint32_t
1392 intel_dp_signal_levels(uint8_t train_set)
1393 {
1394         uint32_t        signal_levels = 0;
1395
1396         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1397         case DP_TRAIN_VOLTAGE_SWING_400:
1398         default:
1399                 signal_levels |= DP_VOLTAGE_0_4;
1400                 break;
1401         case DP_TRAIN_VOLTAGE_SWING_600:
1402                 signal_levels |= DP_VOLTAGE_0_6;
1403                 break;
1404         case DP_TRAIN_VOLTAGE_SWING_800:
1405                 signal_levels |= DP_VOLTAGE_0_8;
1406                 break;
1407         case DP_TRAIN_VOLTAGE_SWING_1200:
1408                 signal_levels |= DP_VOLTAGE_1_2;
1409                 break;
1410         }
1411         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1412         case DP_TRAIN_PRE_EMPHASIS_0:
1413         default:
1414                 signal_levels |= DP_PRE_EMPHASIS_0;
1415                 break;
1416         case DP_TRAIN_PRE_EMPHASIS_3_5:
1417                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1418                 break;
1419         case DP_TRAIN_PRE_EMPHASIS_6:
1420                 signal_levels |= DP_PRE_EMPHASIS_6;
1421                 break;
1422         case DP_TRAIN_PRE_EMPHASIS_9_5:
1423                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1424                 break;
1425         }
1426         return signal_levels;
1427 }
1428
1429 /* Gen6's DP voltage swing and pre-emphasis control */
1430 static uint32_t
1431 intel_gen6_edp_signal_levels(uint8_t train_set)
1432 {
1433         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1434                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1435         switch (signal_levels) {
1436         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1437         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1438                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1439         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1440                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1441         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1442         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1443                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1444         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1445         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1446                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1447         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1448         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1449                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1450         default:
1451                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1452                               "0x%x\n", signal_levels);
1453                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1454         }
1455 }
1456
1457 static uint8_t
1458 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1459                       int lane)
1460 {
1461         int s = (lane & 1) * 4;
1462         uint8_t l = link_status[lane>>1];
1463
1464         return (l >> s) & 0xf;
1465 }
1466
1467 /* Check for clock recovery is done on all channels */
1468 static bool
1469 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1470 {
1471         int lane;
1472         uint8_t lane_status;
1473
1474         for (lane = 0; lane < lane_count; lane++) {
1475                 lane_status = intel_get_lane_status(link_status, lane);
1476                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 /* Check to see if channel eq is done on all channels */
1483 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1484                          DP_LANE_CHANNEL_EQ_DONE|\
1485                          DP_LANE_SYMBOL_LOCKED)
1486 static bool
1487 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1488 {
1489         uint8_t lane_align;
1490         uint8_t lane_status;
1491         int lane;
1492
1493         lane_align = intel_dp_link_status(link_status,
1494                                           DP_LANE_ALIGN_STATUS_UPDATED);
1495         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1496                 return false;
1497         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1498                 lane_status = intel_get_lane_status(link_status, lane);
1499                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1500                         return false;
1501         }
1502         return true;
1503 }
1504
1505 static bool
1506 intel_dp_set_link_train(struct intel_dp *intel_dp,
1507                         uint32_t dp_reg_value,
1508                         uint8_t dp_train_pat)
1509 {
1510         struct drm_device *dev = intel_dp->base.base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int ret;
1513
1514         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1515         POSTING_READ(intel_dp->output_reg);
1516
1517         intel_dp_aux_native_write_1(intel_dp,
1518                                     DP_TRAINING_PATTERN_SET,
1519                                     dp_train_pat);
1520
1521         ret = intel_dp_aux_native_write(intel_dp,
1522                                         DP_TRAINING_LANE0_SET,
1523                                         intel_dp->train_set, 4);
1524         if (ret != 4)
1525                 return false;
1526
1527         return true;
1528 }
1529
1530 /* Enable corresponding port and start training pattern 1 */
1531 static void
1532 intel_dp_start_link_train(struct intel_dp *intel_dp)
1533 {
1534         struct drm_device *dev = intel_dp->base.base.dev;
1535         struct drm_i915_private *dev_priv = dev->dev_private;
1536         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1537         int i;
1538         uint8_t voltage;
1539         bool clock_recovery = false;
1540         int tries;
1541         u32 reg;
1542         uint32_t DP = intel_dp->DP;
1543
1544         /*
1545          * On CPT we have to enable the port in training pattern 1, which
1546          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1547          * the port and wait for it to become active.
1548          */
1549         if (!HAS_PCH_CPT(dev)) {
1550                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1551                 POSTING_READ(intel_dp->output_reg);
1552                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1553         }
1554
1555         /* Write the link configuration data */
1556         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1557                                   intel_dp->link_configuration,
1558                                   DP_LINK_CONFIGURATION_SIZE);
1559
1560         DP |= DP_PORT_EN;
1561         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1562                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1563         else
1564                 DP &= ~DP_LINK_TRAIN_MASK;
1565         memset(intel_dp->train_set, 0, 4);
1566         voltage = 0xff;
1567         tries = 0;
1568         clock_recovery = false;
1569         for (;;) {
1570                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1571                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1572                 uint32_t    signal_levels;
1573                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1574                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1575                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1576                 } else {
1577                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1578                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1579                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1580                 }
1581
1582                 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1583                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1584                 else
1585                         reg = DP | DP_LINK_TRAIN_PAT_1;
1586
1587                 if (!intel_dp_set_link_train(intel_dp, reg,
1588                                              DP_TRAINING_PATTERN_1 |
1589                                              DP_LINK_SCRAMBLING_DISABLE))
1590                         break;
1591                 /* Set training pattern 1 */
1592
1593                 udelay(100);
1594                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1595                         DRM_ERROR("failed to get link status\n");
1596                         break;
1597                 }
1598
1599                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1600                         DRM_DEBUG_KMS("clock recovery OK\n");
1601                         clock_recovery = true;
1602                         break;
1603                 }
1604
1605                 /* Check to see if we've tried the max voltage */
1606                 for (i = 0; i < intel_dp->lane_count; i++)
1607                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1608                                 break;
1609                 if (i == intel_dp->lane_count)
1610                         break;
1611
1612                 /* Check to see if we've tried the same voltage 5 times */
1613                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1614                         ++tries;
1615                         if (tries == 5)
1616                                 break;
1617                 } else
1618                         tries = 0;
1619                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1620
1621                 /* Compute new intel_dp->train_set as requested by target */
1622                 intel_get_adjust_train(intel_dp, link_status);
1623         }
1624
1625         intel_dp->DP = DP;
1626 }
1627
1628 static void
1629 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1630 {
1631         struct drm_device *dev = intel_dp->base.base.dev;
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633         bool channel_eq = false;
1634         int tries, cr_tries;
1635         u32 reg;
1636         uint32_t DP = intel_dp->DP;
1637
1638         /* channel equalization */
1639         tries = 0;
1640         cr_tries = 0;
1641         channel_eq = false;
1642         for (;;) {
1643                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1644                 uint32_t    signal_levels;
1645                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1646
1647                 if (cr_tries > 5) {
1648                         DRM_ERROR("failed to train DP, aborting\n");
1649                         intel_dp_link_down(intel_dp);
1650                         break;
1651                 }
1652
1653                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1654                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1655                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1656                 } else {
1657                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1658                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1659                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1660                 }
1661
1662                 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1663                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1664                 else
1665                         reg = DP | DP_LINK_TRAIN_PAT_2;
1666
1667                 /* channel eq pattern */
1668                 if (!intel_dp_set_link_train(intel_dp, reg,
1669                                              DP_TRAINING_PATTERN_2 |
1670                                              DP_LINK_SCRAMBLING_DISABLE))
1671                         break;
1672
1673                 udelay(400);
1674                 if (!intel_dp_get_link_status(intel_dp, link_status))
1675                         break;
1676
1677                 /* Make sure clock is still ok */
1678                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1679                         intel_dp_start_link_train(intel_dp);
1680                         cr_tries++;
1681                         continue;
1682                 }
1683
1684                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1685                         channel_eq = true;
1686                         break;
1687                 }
1688
1689                 /* Try 5 times, then try clock recovery if that fails */
1690                 if (tries > 5) {
1691                         intel_dp_link_down(intel_dp);
1692                         intel_dp_start_link_train(intel_dp);
1693                         tries = 0;
1694                         cr_tries++;
1695                         continue;
1696                 }
1697
1698                 /* Compute new intel_dp->train_set as requested by target */
1699                 intel_get_adjust_train(intel_dp, link_status);
1700                 ++tries;
1701         }
1702
1703         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1704                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1705         else
1706                 reg = DP | DP_LINK_TRAIN_OFF;
1707
1708         I915_WRITE(intel_dp->output_reg, reg);
1709         POSTING_READ(intel_dp->output_reg);
1710         intel_dp_aux_native_write_1(intel_dp,
1711                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1712 }
1713
1714 static void
1715 intel_dp_link_down(struct intel_dp *intel_dp)
1716 {
1717         struct drm_device *dev = intel_dp->base.base.dev;
1718         struct drm_i915_private *dev_priv = dev->dev_private;
1719         uint32_t DP = intel_dp->DP;
1720
1721         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1722                 return;
1723
1724         DRM_DEBUG_KMS("\n");
1725
1726         if (is_edp(intel_dp)) {
1727                 DP &= ~DP_PLL_ENABLE;
1728                 I915_WRITE(intel_dp->output_reg, DP);
1729                 POSTING_READ(intel_dp->output_reg);
1730                 udelay(100);
1731         }
1732
1733         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
1734                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1735                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1736         } else {
1737                 DP &= ~DP_LINK_TRAIN_MASK;
1738                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1739         }
1740         POSTING_READ(intel_dp->output_reg);
1741
1742         msleep(17);
1743
1744         if (is_edp(intel_dp))
1745                 DP |= DP_LINK_TRAIN_OFF;
1746
1747         if (!HAS_PCH_CPT(dev) &&
1748             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1749                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1750
1751                 /* Hardware workaround: leaving our transcoder select
1752                  * set to transcoder B while it's off will prevent the
1753                  * corresponding HDMI output on transcoder A.
1754                  *
1755                  * Combine this with another hardware workaround:
1756                  * transcoder select bit can only be cleared while the
1757                  * port is enabled.
1758                  */
1759                 DP &= ~DP_PIPEB_SELECT;
1760                 I915_WRITE(intel_dp->output_reg, DP);
1761
1762                 /* Changes to enable or select take place the vblank
1763                  * after being written.
1764                  */
1765                 if (crtc == NULL) {
1766                         /* We can arrive here never having been attached
1767                          * to a CRTC, for instance, due to inheriting
1768                          * random state from the BIOS.
1769                          *
1770                          * If the pipe is not running, play safe and
1771                          * wait for the clocks to stabilise before
1772                          * continuing.
1773                          */
1774                         POSTING_READ(intel_dp->output_reg);
1775                         msleep(50);
1776                 } else
1777                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1778         }
1779
1780         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1781         POSTING_READ(intel_dp->output_reg);
1782         msleep(intel_dp->panel_power_down_delay);
1783 }
1784
1785 static bool
1786 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1787 {
1788         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1789                                            sizeof(intel_dp->dpcd)) &&
1790             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1791                 return true;
1792         }
1793
1794         return false;
1795 }
1796
1797 static bool
1798 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1799 {
1800         int ret;
1801
1802         ret = intel_dp_aux_native_read_retry(intel_dp,
1803                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1804                                              sink_irq_vector, 1);
1805         if (!ret)
1806                 return false;
1807
1808         return true;
1809 }
1810
1811 static void
1812 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1813 {
1814         /* NAK by default */
1815         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1816 }
1817
1818 /*
1819  * According to DP spec
1820  * 5.1.2:
1821  *  1. Read DPCD
1822  *  2. Configure link according to Receiver Capabilities
1823  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1824  *  4. Check link status on receipt of hot-plug interrupt
1825  */
1826
1827 static void
1828 intel_dp_check_link_status(struct intel_dp *intel_dp)
1829 {
1830         u8 sink_irq_vector;
1831         u8 link_status[DP_LINK_STATUS_SIZE];
1832
1833         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1834                 return;
1835
1836         if (!intel_dp->base.base.crtc)
1837                 return;
1838
1839         /* Try to read receiver status if the link appears to be up */
1840         if (!intel_dp_get_link_status(intel_dp, link_status)) {
1841                 intel_dp_link_down(intel_dp);
1842                 return;
1843         }
1844
1845         /* Now read the DPCD to see if it's actually running */
1846         if (!intel_dp_get_dpcd(intel_dp)) {
1847                 intel_dp_link_down(intel_dp);
1848                 return;
1849         }
1850
1851         /* Try to read the source of the interrupt */
1852         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1853             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1854                 /* Clear interrupt source */
1855                 intel_dp_aux_native_write_1(intel_dp,
1856                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
1857                                             sink_irq_vector);
1858
1859                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1860                         intel_dp_handle_test_request(intel_dp);
1861                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1862                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1863         }
1864
1865         if (!intel_channel_eq_ok(intel_dp, link_status)) {
1866                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1867                               drm_get_encoder_name(&intel_dp->base.base));
1868                 intel_dp_start_link_train(intel_dp);
1869                 intel_dp_complete_link_train(intel_dp);
1870         }
1871 }
1872
1873 static enum drm_connector_status
1874 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1875 {
1876         if (intel_dp_get_dpcd(intel_dp))
1877                 return connector_status_connected;
1878         return connector_status_disconnected;
1879 }
1880
1881 static enum drm_connector_status
1882 ironlake_dp_detect(struct intel_dp *intel_dp)
1883 {
1884         enum drm_connector_status status;
1885
1886         /* Can't disconnect eDP, but you can close the lid... */
1887         if (is_edp(intel_dp)) {
1888                 status = intel_panel_detect(intel_dp->base.base.dev);
1889                 if (status == connector_status_unknown)
1890                         status = connector_status_connected;
1891                 return status;
1892         }
1893
1894         return intel_dp_detect_dpcd(intel_dp);
1895 }
1896
1897 static enum drm_connector_status
1898 g4x_dp_detect(struct intel_dp *intel_dp)
1899 {
1900         struct drm_device *dev = intel_dp->base.base.dev;
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         uint32_t temp, bit;
1903
1904         switch (intel_dp->output_reg) {
1905         case DP_B:
1906                 bit = DPB_HOTPLUG_INT_STATUS;
1907                 break;
1908         case DP_C:
1909                 bit = DPC_HOTPLUG_INT_STATUS;
1910                 break;
1911         case DP_D:
1912                 bit = DPD_HOTPLUG_INT_STATUS;
1913                 break;
1914         default:
1915                 return connector_status_unknown;
1916         }
1917
1918         temp = I915_READ(PORT_HOTPLUG_STAT);
1919
1920         if ((temp & bit) == 0)
1921                 return connector_status_disconnected;
1922
1923         return intel_dp_detect_dpcd(intel_dp);
1924 }
1925
1926 static struct edid *
1927 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1928 {
1929         struct intel_dp *intel_dp = intel_attached_dp(connector);
1930         struct edid     *edid;
1931
1932         ironlake_edp_panel_vdd_on(intel_dp);
1933         edid = drm_get_edid(connector, adapter);
1934         ironlake_edp_panel_vdd_off(intel_dp, false);
1935         return edid;
1936 }
1937
1938 static int
1939 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1940 {
1941         struct intel_dp *intel_dp = intel_attached_dp(connector);
1942         int     ret;
1943
1944         ironlake_edp_panel_vdd_on(intel_dp);
1945         ret = intel_ddc_get_modes(connector, adapter);
1946         ironlake_edp_panel_vdd_off(intel_dp, false);
1947         return ret;
1948 }
1949
1950
1951 /**
1952  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1953  *
1954  * \return true if DP port is connected.
1955  * \return false if DP port is disconnected.
1956  */
1957 static enum drm_connector_status
1958 intel_dp_detect(struct drm_connector *connector, bool force)
1959 {
1960         struct intel_dp *intel_dp = intel_attached_dp(connector);
1961         struct drm_device *dev = intel_dp->base.base.dev;
1962         enum drm_connector_status status;
1963         struct edid *edid = NULL;
1964
1965         intel_dp->has_audio = false;
1966
1967         if (HAS_PCH_SPLIT(dev))
1968                 status = ironlake_dp_detect(intel_dp);
1969         else
1970                 status = g4x_dp_detect(intel_dp);
1971
1972         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1973                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1974                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1975                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1976
1977         if (status != connector_status_connected)
1978                 return status;
1979
1980         if (intel_dp->force_audio) {
1981                 intel_dp->has_audio = intel_dp->force_audio > 0;
1982         } else {
1983                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1984                 if (edid) {
1985                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1986                         connector->display_info.raw_edid = NULL;
1987                         kfree(edid);
1988                 }
1989         }
1990
1991         return connector_status_connected;
1992 }
1993
1994 static int intel_dp_get_modes(struct drm_connector *connector)
1995 {
1996         struct intel_dp *intel_dp = intel_attached_dp(connector);
1997         struct drm_device *dev = intel_dp->base.base.dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         int ret;
2000
2001         /* We should parse the EDID data and find out if it has an audio sink
2002          */
2003
2004         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2005         if (ret) {
2006                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2007                         struct drm_display_mode *newmode;
2008                         list_for_each_entry(newmode, &connector->probed_modes,
2009                                             head) {
2010                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2011                                         intel_dp->panel_fixed_mode =
2012                                                 drm_mode_duplicate(dev, newmode);
2013                                         break;
2014                                 }
2015                         }
2016                 }
2017                 return ret;
2018         }
2019
2020         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2021         if (is_edp(intel_dp)) {
2022                 /* initialize panel mode from VBT if available for eDP */
2023                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2024                         intel_dp->panel_fixed_mode =
2025                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2026                         if (intel_dp->panel_fixed_mode) {
2027                                 intel_dp->panel_fixed_mode->type |=
2028                                         DRM_MODE_TYPE_PREFERRED;
2029                         }
2030                 }
2031                 if (intel_dp->panel_fixed_mode) {
2032                         struct drm_display_mode *mode;
2033                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2034                         drm_mode_probed_add(connector, mode);
2035                         return 1;
2036                 }
2037         }
2038         return 0;
2039 }
2040
2041 static bool
2042 intel_dp_detect_audio(struct drm_connector *connector)
2043 {
2044         struct intel_dp *intel_dp = intel_attached_dp(connector);
2045         struct edid *edid;
2046         bool has_audio = false;
2047
2048         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2049         if (edid) {
2050                 has_audio = drm_detect_monitor_audio(edid);
2051
2052                 connector->display_info.raw_edid = NULL;
2053                 kfree(edid);
2054         }
2055
2056         return has_audio;
2057 }
2058
2059 static int
2060 intel_dp_set_property(struct drm_connector *connector,
2061                       struct drm_property *property,
2062                       uint64_t val)
2063 {
2064         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2065         struct intel_dp *intel_dp = intel_attached_dp(connector);
2066         int ret;
2067
2068         ret = drm_connector_property_set_value(connector, property, val);
2069         if (ret)
2070                 return ret;
2071
2072         if (property == dev_priv->force_audio_property) {
2073                 int i = val;
2074                 bool has_audio;
2075
2076                 if (i == intel_dp->force_audio)
2077                         return 0;
2078
2079                 intel_dp->force_audio = i;
2080
2081                 if (i == 0)
2082                         has_audio = intel_dp_detect_audio(connector);
2083                 else
2084                         has_audio = i > 0;
2085
2086                 if (has_audio == intel_dp->has_audio)
2087                         return 0;
2088
2089                 intel_dp->has_audio = has_audio;
2090                 goto done;
2091         }
2092
2093         if (property == dev_priv->broadcast_rgb_property) {
2094                 if (val == !!intel_dp->color_range)
2095                         return 0;
2096
2097                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2098                 goto done;
2099         }
2100
2101         return -EINVAL;
2102
2103 done:
2104         if (intel_dp->base.base.crtc) {
2105                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2106                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2107                                          crtc->x, crtc->y,
2108                                          crtc->fb);
2109         }
2110
2111         return 0;
2112 }
2113
2114 static void
2115 intel_dp_destroy(struct drm_connector *connector)
2116 {
2117         struct drm_device *dev = connector->dev;
2118
2119         if (intel_dpd_is_edp(dev))
2120                 intel_panel_destroy_backlight(dev);
2121
2122         drm_sysfs_connector_remove(connector);
2123         drm_connector_cleanup(connector);
2124         kfree(connector);
2125 }
2126
2127 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2128 {
2129         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2130
2131         i2c_del_adapter(&intel_dp->adapter);
2132         drm_encoder_cleanup(encoder);
2133         if (is_edp(intel_dp)) {
2134                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2135                 ironlake_panel_vdd_off_sync(intel_dp);
2136         }
2137         kfree(intel_dp);
2138 }
2139
2140 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2141         .dpms = intel_dp_dpms,
2142         .mode_fixup = intel_dp_mode_fixup,
2143         .prepare = intel_dp_prepare,
2144         .mode_set = intel_dp_mode_set,
2145         .commit = intel_dp_commit,
2146 };
2147
2148 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2149         .dpms = drm_helper_connector_dpms,
2150         .detect = intel_dp_detect,
2151         .fill_modes = drm_helper_probe_single_connector_modes,
2152         .set_property = intel_dp_set_property,
2153         .destroy = intel_dp_destroy,
2154 };
2155
2156 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2157         .get_modes = intel_dp_get_modes,
2158         .mode_valid = intel_dp_mode_valid,
2159         .best_encoder = intel_best_encoder,
2160 };
2161
2162 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2163         .destroy = intel_dp_encoder_destroy,
2164 };
2165
2166 static void
2167 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2168 {
2169         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2170
2171         intel_dp_check_link_status(intel_dp);
2172 }
2173
2174 /* Return which DP Port should be selected for Transcoder DP control */
2175 int
2176 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2177 {
2178         struct drm_device *dev = crtc->dev;
2179         struct drm_mode_config *mode_config = &dev->mode_config;
2180         struct drm_encoder *encoder;
2181
2182         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2183                 struct intel_dp *intel_dp;
2184
2185                 if (encoder->crtc != crtc)
2186                         continue;
2187
2188                 intel_dp = enc_to_intel_dp(encoder);
2189                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2190                         return intel_dp->output_reg;
2191         }
2192
2193         return -1;
2194 }
2195
2196 /* check the VBT to see whether the eDP is on DP-D port */
2197 bool intel_dpd_is_edp(struct drm_device *dev)
2198 {
2199         struct drm_i915_private *dev_priv = dev->dev_private;
2200         struct child_device_config *p_child;
2201         int i;
2202
2203         if (!dev_priv->child_dev_num)
2204                 return false;
2205
2206         for (i = 0; i < dev_priv->child_dev_num; i++) {
2207                 p_child = dev_priv->child_dev + i;
2208
2209                 if (p_child->dvo_port == PORT_IDPD &&
2210                     p_child->device_type == DEVICE_TYPE_eDP)
2211                         return true;
2212         }
2213         return false;
2214 }
2215
2216 static void
2217 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2218 {
2219         intel_attach_force_audio_property(connector);
2220         intel_attach_broadcast_rgb_property(connector);
2221 }
2222
2223 void
2224 intel_dp_init(struct drm_device *dev, int output_reg)
2225 {
2226         struct drm_i915_private *dev_priv = dev->dev_private;
2227         struct drm_connector *connector;
2228         struct intel_dp *intel_dp;
2229         struct intel_encoder *intel_encoder;
2230         struct intel_connector *intel_connector;
2231         const char *name = NULL;
2232         int type;
2233
2234         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2235         if (!intel_dp)
2236                 return;
2237
2238         intel_dp->output_reg = output_reg;
2239         intel_dp->dpms_mode = -1;
2240
2241         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2242         if (!intel_connector) {
2243                 kfree(intel_dp);
2244                 return;
2245         }
2246         intel_encoder = &intel_dp->base;
2247
2248         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2249                 if (intel_dpd_is_edp(dev))
2250                         intel_dp->is_pch_edp = true;
2251
2252         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2253                 type = DRM_MODE_CONNECTOR_eDP;
2254                 intel_encoder->type = INTEL_OUTPUT_EDP;
2255         } else {
2256                 type = DRM_MODE_CONNECTOR_DisplayPort;
2257                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2258         }
2259
2260         connector = &intel_connector->base;
2261         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2262         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2263
2264         connector->polled = DRM_CONNECTOR_POLL_HPD;
2265
2266         if (output_reg == DP_B || output_reg == PCH_DP_B)
2267                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2268         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2269                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2270         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2271                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2272
2273         if (is_edp(intel_dp)) {
2274                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2275                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2276                                   ironlake_panel_vdd_work);
2277         }
2278
2279         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2280         connector->interlace_allowed = true;
2281         connector->doublescan_allowed = 0;
2282
2283         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2284                          DRM_MODE_ENCODER_TMDS);
2285         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2286
2287         intel_connector_attach_encoder(intel_connector, intel_encoder);
2288         drm_sysfs_connector_add(connector);
2289
2290         /* Set up the DDC bus. */
2291         switch (output_reg) {
2292                 case DP_A:
2293                         name = "DPDDC-A";
2294                         break;
2295                 case DP_B:
2296                 case PCH_DP_B:
2297                         dev_priv->hotplug_supported_mask |=
2298                                 HDMIB_HOTPLUG_INT_STATUS;
2299                         name = "DPDDC-B";
2300                         break;
2301                 case DP_C:
2302                 case PCH_DP_C:
2303                         dev_priv->hotplug_supported_mask |=
2304                                 HDMIC_HOTPLUG_INT_STATUS;
2305                         name = "DPDDC-C";
2306                         break;
2307                 case DP_D:
2308                 case PCH_DP_D:
2309                         dev_priv->hotplug_supported_mask |=
2310                                 HDMID_HOTPLUG_INT_STATUS;
2311                         name = "DPDDC-D";
2312                         break;
2313         }
2314
2315         /* Cache some DPCD data in the eDP case */
2316         if (is_edp(intel_dp)) {
2317                 bool ret;
2318                 struct edp_power_seq    cur, vbt;
2319                 u32 pp_on, pp_off, pp_div;
2320
2321                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2322                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2323                 pp_div = I915_READ(PCH_PP_DIVISOR);
2324
2325                 /* Pull timing values out of registers */
2326                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2327                         PANEL_POWER_UP_DELAY_SHIFT;
2328
2329                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2330                         PANEL_LIGHT_ON_DELAY_SHIFT;
2331
2332                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2333                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2334
2335                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2336                         PANEL_POWER_DOWN_DELAY_SHIFT;
2337
2338                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2339                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2340
2341                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2342                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2343
2344                 vbt = dev_priv->edp.pps;
2345
2346                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2347                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2348
2349 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2350
2351                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2352                 intel_dp->backlight_on_delay = get_delay(t8);
2353                 intel_dp->backlight_off_delay = get_delay(t9);
2354                 intel_dp->panel_power_down_delay = get_delay(t10);
2355                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2356
2357                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2358                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2359                               intel_dp->panel_power_cycle_delay);
2360
2361                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2362                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2363
2364                 intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay;
2365
2366                 ironlake_edp_panel_vdd_on(intel_dp);
2367                 ret = intel_dp_get_dpcd(intel_dp);
2368                 ironlake_edp_panel_vdd_off(intel_dp, false);
2369                 if (ret) {
2370                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2371                                 dev_priv->no_aux_handshake =
2372                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2373                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2374                 } else {
2375                         /* if this fails, presume the device is a ghost */
2376                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2377                         intel_dp_encoder_destroy(&intel_dp->base.base);
2378                         intel_dp_destroy(&intel_connector->base);
2379                         return;
2380                 }
2381         }
2382
2383         intel_dp_i2c_init(intel_dp, intel_connector, name);
2384
2385         intel_encoder->hot_plug = intel_dp_hot_plug;
2386
2387         if (is_edp(intel_dp)) {
2388                 dev_priv->int_edp_connector = connector;
2389                 intel_panel_setup_backlight(dev);
2390         }
2391
2392         intel_dp_add_properties(intel_dp, connector);
2393
2394         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2395          * 0xd.  Failure to do so will result in spurious interrupts being
2396          * generated on the port when a cable is not attached.
2397          */
2398         if (IS_G4X(dev) && !IS_GM45(dev)) {
2399                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2400                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2401         }
2402 }