2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
46 struct intel_encoder base;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
55 struct i2c_adapter adapter;
56 struct i2c_algo_dp_aux_data algo;
59 uint8_t link_status[DP_LINK_STATUS_SIZE];
63 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
64 * @intel_dp: DP struct
66 * If a CPU or PCH DP output is attached to an eDP panel, this function
67 * will return true, and false otherwise.
69 static bool is_edp(struct intel_dp *intel_dp)
71 return intel_dp->base.type == INTEL_OUTPUT_EDP;
75 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
76 * @intel_dp: DP struct
78 * Returns true if the given DP struct corresponds to a PCH DP port attached
79 * to an eDP panel, false otherwise. Helpful for determining whether we
80 * may need FDI resources for a given DP output or not.
82 static bool is_pch_edp(struct intel_dp *intel_dp)
84 return intel_dp->is_pch_edp;
87 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
89 return container_of(encoder, struct intel_dp, base.base);
92 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
94 return container_of(intel_attached_encoder(connector),
95 struct intel_dp, base);
99 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
100 * @encoder: DRM encoder
102 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
103 * by intel_display.c.
105 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
107 struct intel_dp *intel_dp;
112 intel_dp = enc_to_intel_dp(encoder);
114 return is_pch_edp(intel_dp);
117 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
118 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
119 static void intel_dp_link_down(struct intel_dp *intel_dp);
122 intel_edp_link_config (struct intel_encoder *intel_encoder,
123 int *lane_num, int *link_bw)
125 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
127 *lane_num = intel_dp->lane_count;
128 if (intel_dp->link_bw == DP_LINK_BW_1_62)
130 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
135 intel_dp_max_lane_count(struct intel_dp *intel_dp)
137 int max_lane_count = 4;
139 if (intel_dp->dpcd[0] >= 0x11) {
140 max_lane_count = intel_dp->dpcd[2] & 0x1f;
141 switch (max_lane_count) {
142 case 1: case 2: case 4:
148 return max_lane_count;
152 intel_dp_max_link_bw(struct intel_dp *intel_dp)
154 int max_link_bw = intel_dp->dpcd[1];
156 switch (max_link_bw) {
157 case DP_LINK_BW_1_62:
161 max_link_bw = DP_LINK_BW_1_62;
168 intel_dp_link_clock(uint8_t link_bw)
170 if (link_bw == DP_LINK_BW_2_7)
176 /* I think this is a fiction */
178 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
180 struct drm_i915_private *dev_priv = dev->dev_private;
182 if (is_edp(intel_dp))
183 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
185 return pixel_clock * 3;
189 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
191 return (max_link_clock * max_lanes * 8) / 10;
195 intel_dp_mode_valid(struct drm_connector *connector,
196 struct drm_display_mode *mode)
198 struct intel_dp *intel_dp = intel_attached_dp(connector);
199 struct drm_device *dev = connector->dev;
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
202 int max_lanes = intel_dp_max_lane_count(intel_dp);
204 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
205 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
208 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
212 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
213 which are outside spec tolerances but somehow work by magic */
214 if (!is_edp(intel_dp) &&
215 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
216 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
217 return MODE_CLOCK_HIGH;
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
226 pack_aux(uint8_t *src, int src_bytes)
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
248 /* hrawclock is 1/4 the FSB frequency */
250 intel_hrawclk(struct drm_device *dev)
252 struct drm_i915_private *dev_priv = dev->dev_private;
255 clkcfg = I915_READ(CLKCFG);
256 switch (clkcfg & CLKCFG_FSB_MASK) {
265 case CLKCFG_FSB_1067:
267 case CLKCFG_FSB_1333:
269 /* these two are just a guess; one of them might be right */
270 case CLKCFG_FSB_1600:
271 case CLKCFG_FSB_1600_ALT:
279 intel_dp_aux_ch(struct intel_dp *intel_dp,
280 uint8_t *send, int send_bytes,
281 uint8_t *recv, int recv_size)
283 uint32_t output_reg = intel_dp->output_reg;
284 struct drm_device *dev = intel_dp->base.base.dev;
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 uint32_t ch_ctl = output_reg + 0x10;
287 uint32_t ch_data = ch_ctl + 4;
291 uint32_t aux_clock_divider;
294 /* The clock divider is based off the hrawclk,
295 * and would like to run at 2MHz. So, take the
296 * hrawclk value and divide by 2 and use that
298 * Note that PCH attached eDP panels should use a 125MHz input
301 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
303 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
305 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
306 } else if (HAS_PCH_SPLIT(dev))
307 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
309 aux_clock_divider = intel_hrawclk(dev) / 2;
316 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
317 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
322 /* Must try at least 3 times according to DP spec */
323 for (try = 0; try < 5; try++) {
324 /* Load the send data into the aux channel data registers */
325 for (i = 0; i < send_bytes; i += 4)
326 I915_WRITE(ch_data + i,
327 pack_aux(send + i, send_bytes - i));
329 /* Send the command and wait for it to complete */
331 DP_AUX_CH_CTL_SEND_BUSY |
332 DP_AUX_CH_CTL_TIME_OUT_400us |
333 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
334 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
335 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
337 DP_AUX_CH_CTL_TIME_OUT_ERROR |
338 DP_AUX_CH_CTL_RECEIVE_ERROR);
340 status = I915_READ(ch_ctl);
341 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
346 /* Clear done status and any errors */
350 DP_AUX_CH_CTL_TIME_OUT_ERROR |
351 DP_AUX_CH_CTL_RECEIVE_ERROR);
352 if (status & DP_AUX_CH_CTL_DONE)
356 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
357 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
361 /* Check for timeout or receive error.
362 * Timeouts occur when the sink is not connected
364 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
365 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
369 /* Timeouts occur when the device isn't connected, so they're
370 * "normal" -- don't fill the kernel log with these */
371 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
372 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
376 /* Unload any bytes sent back from the other side */
377 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
378 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
379 if (recv_bytes > recv_size)
380 recv_bytes = recv_size;
382 for (i = 0; i < recv_bytes; i += 4)
383 unpack_aux(I915_READ(ch_data + i),
384 recv + i, recv_bytes - i);
389 /* Write data to the aux channel in native mode */
391 intel_dp_aux_native_write(struct intel_dp *intel_dp,
392 uint16_t address, uint8_t *send, int send_bytes)
401 msg[0] = AUX_NATIVE_WRITE << 4;
402 msg[1] = address >> 8;
403 msg[2] = address & 0xff;
404 msg[3] = send_bytes - 1;
405 memcpy(&msg[4], send, send_bytes);
406 msg_bytes = send_bytes + 4;
408 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
411 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
413 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
421 /* Write a single byte to the aux channel in native mode */
423 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
424 uint16_t address, uint8_t byte)
426 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
429 /* read bytes from a native aux channel */
431 intel_dp_aux_native_read(struct intel_dp *intel_dp,
432 uint16_t address, uint8_t *recv, int recv_bytes)
441 msg[0] = AUX_NATIVE_READ << 4;
442 msg[1] = address >> 8;
443 msg[2] = address & 0xff;
444 msg[3] = recv_bytes - 1;
447 reply_bytes = recv_bytes + 1;
450 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
457 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
458 memcpy(recv, reply + 1, ret - 1);
461 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
469 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
470 uint8_t write_byte, uint8_t *read_byte)
472 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
473 struct intel_dp *intel_dp = container_of(adapter,
476 uint16_t address = algo_data->address;
483 /* Set up the command byte */
484 if (mode & MODE_I2C_READ)
485 msg[0] = AUX_I2C_READ << 4;
487 msg[0] = AUX_I2C_WRITE << 4;
489 if (!(mode & MODE_I2C_STOP))
490 msg[0] |= AUX_I2C_MOT << 4;
492 msg[1] = address >> 8;
514 ret = intel_dp_aux_ch(intel_dp,
518 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
521 switch (reply[0] & AUX_I2C_REPLY_MASK) {
522 case AUX_I2C_REPLY_ACK:
523 if (mode == MODE_I2C_READ) {
524 *read_byte = reply[1];
526 return reply_bytes - 1;
527 case AUX_I2C_REPLY_NACK:
528 DRM_DEBUG_KMS("aux_ch nack\n");
530 case AUX_I2C_REPLY_DEFER:
531 DRM_DEBUG_KMS("aux_ch defer\n");
535 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
542 intel_dp_i2c_init(struct intel_dp *intel_dp,
543 struct intel_connector *intel_connector, const char *name)
545 DRM_DEBUG_KMS("i2c_init %s\n", name);
546 intel_dp->algo.running = false;
547 intel_dp->algo.address = 0;
548 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
550 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
551 intel_dp->adapter.owner = THIS_MODULE;
552 intel_dp->adapter.class = I2C_CLASS_DDC;
553 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
554 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
555 intel_dp->adapter.algo_data = &intel_dp->algo;
556 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
558 return i2c_dp_aux_add_bus(&intel_dp->adapter);
562 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
563 struct drm_display_mode *adjusted_mode)
565 struct drm_device *dev = encoder->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
568 int lane_count, clock;
569 int max_lane_count = intel_dp_max_lane_count(intel_dp);
570 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
571 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
573 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
574 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
575 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
576 mode, adjusted_mode);
578 * the mode->clock is used to calculate the Data&Link M/N
579 * of the pipe. For the eDP the fixed clock should be used.
581 mode->clock = dev_priv->panel_fixed_mode->clock;
584 /* Just use VBT values for eDP */
585 if (is_edp(intel_dp)) {
586 intel_dp->lane_count = dev_priv->edp.lanes;
587 intel_dp->link_bw = dev_priv->edp.rate;
588 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
589 DRM_DEBUG_KMS("eDP link bw %02x lane count %d clock %d\n",
590 intel_dp->link_bw, intel_dp->lane_count,
591 adjusted_mode->clock);
595 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
596 for (clock = 0; clock <= max_clock; clock++) {
597 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
599 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
601 intel_dp->link_bw = bws[clock];
602 intel_dp->lane_count = lane_count;
603 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
604 DRM_DEBUG_KMS("Display port link bw %02x lane "
605 "count %d clock %d\n",
606 intel_dp->link_bw, intel_dp->lane_count,
607 adjusted_mode->clock);
616 struct intel_dp_m_n {
625 intel_reduce_ratio(uint32_t *num, uint32_t *den)
627 while (*num > 0xffffff || *den > 0xffffff) {
634 intel_dp_compute_m_n(int bpp,
638 struct intel_dp_m_n *m_n)
641 m_n->gmch_m = (pixel_clock * bpp) >> 3;
642 m_n->gmch_n = link_clock * nlanes;
643 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
644 m_n->link_m = pixel_clock;
645 m_n->link_n = link_clock;
646 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
650 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
651 struct drm_display_mode *adjusted_mode)
653 struct drm_device *dev = crtc->dev;
654 struct drm_mode_config *mode_config = &dev->mode_config;
655 struct drm_encoder *encoder;
656 struct drm_i915_private *dev_priv = dev->dev_private;
657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
658 int lane_count = 4, bpp = 24;
659 struct intel_dp_m_n m_n;
662 * Find the lane count in the intel_encoder private
664 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
665 struct intel_dp *intel_dp;
667 if (encoder->crtc != crtc)
670 intel_dp = enc_to_intel_dp(encoder);
671 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
672 lane_count = intel_dp->lane_count;
674 } else if (is_edp(intel_dp)) {
675 lane_count = dev_priv->edp.lanes;
676 bpp = dev_priv->edp.bpp;
682 * Compute the GMCH and Link ratios. The '3' here is
683 * the number of bytes_per_pixel post-LUT, which we always
684 * set up for 8-bits of R/G/B, or 3 bytes total.
686 intel_dp_compute_m_n(bpp, lane_count,
687 mode->clock, adjusted_mode->clock, &m_n);
689 if (HAS_PCH_SPLIT(dev)) {
690 if (intel_crtc->pipe == 0) {
691 I915_WRITE(TRANSA_DATA_M1,
692 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
694 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
695 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
696 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
698 I915_WRITE(TRANSB_DATA_M1,
699 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
701 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
702 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
703 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
706 if (intel_crtc->pipe == 0) {
707 I915_WRITE(PIPEA_GMCH_DATA_M,
708 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
710 I915_WRITE(PIPEA_GMCH_DATA_N,
712 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
713 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
715 I915_WRITE(PIPEB_GMCH_DATA_M,
716 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
718 I915_WRITE(PIPEB_GMCH_DATA_N,
720 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
721 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
727 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
728 struct drm_display_mode *adjusted_mode)
730 struct drm_device *dev = encoder->dev;
731 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
732 struct drm_crtc *crtc = intel_dp->base.base.crtc;
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
735 intel_dp->DP = (DP_VOLTAGE_0_4 |
738 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
739 intel_dp->DP |= DP_SYNC_HS_HIGH;
740 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
741 intel_dp->DP |= DP_SYNC_VS_HIGH;
743 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
744 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
746 intel_dp->DP |= DP_LINK_TRAIN_OFF;
748 switch (intel_dp->lane_count) {
750 intel_dp->DP |= DP_PORT_WIDTH_1;
753 intel_dp->DP |= DP_PORT_WIDTH_2;
756 intel_dp->DP |= DP_PORT_WIDTH_4;
759 if (intel_dp->has_audio)
760 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
762 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
763 intel_dp->link_configuration[0] = intel_dp->link_bw;
764 intel_dp->link_configuration[1] = intel_dp->lane_count;
767 * Check for DPCD version > 1.1 and enhanced framing support
769 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
770 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
771 intel_dp->DP |= DP_ENHANCED_FRAMING;
774 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
775 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
776 intel_dp->DP |= DP_PIPEB_SELECT;
778 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
779 /* don't miss out required setting for eDP */
780 intel_dp->DP |= DP_PLL_ENABLE;
781 if (adjusted_mode->clock < 200000)
782 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
784 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
788 /* Returns true if the panel was already on when called */
789 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
791 struct drm_device *dev = intel_dp->base.base.dev;
792 struct drm_i915_private *dev_priv = dev->dev_private;
793 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
795 if (I915_READ(PCH_PP_STATUS) & PP_ON)
798 pp = I915_READ(PCH_PP_CONTROL);
800 /* ILK workaround: disable reset around power sequence */
801 pp &= ~PANEL_POWER_RESET;
802 I915_WRITE(PCH_PP_CONTROL, pp);
803 POSTING_READ(PCH_PP_CONTROL);
805 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
806 I915_WRITE(PCH_PP_CONTROL, pp);
807 POSTING_READ(PCH_PP_CONTROL);
809 /* Ouch. We need to wait here for some panels, like Dell e6510
810 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
814 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
816 DRM_ERROR("panel on wait timed out: 0x%08x\n",
817 I915_READ(PCH_PP_STATUS));
819 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
820 I915_WRITE(PCH_PP_CONTROL, pp);
821 POSTING_READ(PCH_PP_CONTROL);
826 static void ironlake_edp_panel_off (struct drm_device *dev)
828 struct drm_i915_private *dev_priv = dev->dev_private;
829 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
830 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
832 pp = I915_READ(PCH_PP_CONTROL);
834 /* ILK workaround: disable reset around power sequence */
835 pp &= ~PANEL_POWER_RESET;
836 I915_WRITE(PCH_PP_CONTROL, pp);
837 POSTING_READ(PCH_PP_CONTROL);
839 pp &= ~POWER_TARGET_ON;
840 I915_WRITE(PCH_PP_CONTROL, pp);
841 POSTING_READ(PCH_PP_CONTROL);
843 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
844 DRM_ERROR("panel off wait timed out: 0x%08x\n",
845 I915_READ(PCH_PP_STATUS));
847 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
848 I915_WRITE(PCH_PP_CONTROL, pp);
849 POSTING_READ(PCH_PP_CONTROL);
851 /* Ouch. We need to wait here for some panels, like Dell e6510
852 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
857 static void ironlake_edp_backlight_on (struct drm_device *dev)
859 struct drm_i915_private *dev_priv = dev->dev_private;
864 * If we enable the backlight right away following a panel power
865 * on, we may see slight flicker as the panel syncs with the eDP
866 * link. So delay a bit to make sure the image is solid before
867 * allowing it to appear.
870 pp = I915_READ(PCH_PP_CONTROL);
871 pp |= EDP_BLC_ENABLE;
872 I915_WRITE(PCH_PP_CONTROL, pp);
875 static void ironlake_edp_backlight_off (struct drm_device *dev)
877 struct drm_i915_private *dev_priv = dev->dev_private;
881 pp = I915_READ(PCH_PP_CONTROL);
882 pp &= ~EDP_BLC_ENABLE;
883 I915_WRITE(PCH_PP_CONTROL, pp);
886 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
888 struct drm_device *dev = encoder->dev;
889 struct drm_i915_private *dev_priv = dev->dev_private;
893 dpa_ctl = I915_READ(DP_A);
894 dpa_ctl |= DP_PLL_ENABLE;
895 I915_WRITE(DP_A, dpa_ctl);
900 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
902 struct drm_device *dev = encoder->dev;
903 struct drm_i915_private *dev_priv = dev->dev_private;
906 dpa_ctl = I915_READ(DP_A);
907 dpa_ctl &= ~DP_PLL_ENABLE;
908 I915_WRITE(DP_A, dpa_ctl);
913 static void intel_dp_prepare(struct drm_encoder *encoder)
915 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
916 struct drm_device *dev = encoder->dev;
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
920 if (is_edp(intel_dp)) {
921 ironlake_edp_backlight_off(dev);
922 ironlake_edp_panel_on(intel_dp);
923 if (!is_pch_edp(intel_dp))
924 ironlake_edp_pll_on(encoder);
926 ironlake_edp_pll_off(encoder);
928 if (dp_reg & DP_PORT_EN)
929 intel_dp_link_down(intel_dp);
932 static void intel_dp_commit(struct drm_encoder *encoder)
934 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
935 struct drm_device *dev = encoder->dev;
937 intel_dp_start_link_train(intel_dp);
939 if (is_edp(intel_dp))
940 ironlake_edp_panel_on(intel_dp);
942 intel_dp_complete_link_train(intel_dp);
944 if (is_edp(intel_dp))
945 ironlake_edp_backlight_on(dev);
949 intel_dp_dpms(struct drm_encoder *encoder, int mode)
951 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
952 struct drm_device *dev = encoder->dev;
953 struct drm_i915_private *dev_priv = dev->dev_private;
954 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
956 if (mode != DRM_MODE_DPMS_ON) {
957 if (is_edp(intel_dp))
958 ironlake_edp_backlight_off(dev);
959 if (dp_reg & DP_PORT_EN)
960 intel_dp_link_down(intel_dp);
961 if (is_edp(intel_dp))
962 ironlake_edp_panel_off(dev);
963 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
964 ironlake_edp_pll_off(encoder);
966 if (!(dp_reg & DP_PORT_EN)) {
967 if (is_edp(intel_dp))
968 ironlake_edp_panel_on(intel_dp);
969 intel_dp_start_link_train(intel_dp);
970 intel_dp_complete_link_train(intel_dp);
971 if (is_edp(intel_dp))
972 ironlake_edp_backlight_on(dev);
975 intel_dp->dpms_mode = mode;
979 * Fetch AUX CH registers 0x202 - 0x207 which contain
980 * link status information
983 intel_dp_get_link_status(struct intel_dp *intel_dp)
987 ret = intel_dp_aux_native_read(intel_dp,
989 intel_dp->link_status, DP_LINK_STATUS_SIZE);
990 if (ret != DP_LINK_STATUS_SIZE)
996 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
999 return link_status[r - DP_LANE0_1_STATUS];
1003 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1006 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1007 int s = ((lane & 1) ?
1008 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1009 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1010 uint8_t l = intel_dp_link_status(link_status, i);
1012 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1016 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1019 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1020 int s = ((lane & 1) ?
1021 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1022 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1023 uint8_t l = intel_dp_link_status(link_status, i);
1025 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1030 static char *voltage_names[] = {
1031 "0.4V", "0.6V", "0.8V", "1.2V"
1033 static char *pre_emph_names[] = {
1034 "0dB", "3.5dB", "6dB", "9.5dB"
1036 static char *link_train_names[] = {
1037 "pattern 1", "pattern 2", "idle", "off"
1042 * These are source-specific values; current Intel hardware supports
1043 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1045 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1048 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1050 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1051 case DP_TRAIN_VOLTAGE_SWING_400:
1052 return DP_TRAIN_PRE_EMPHASIS_6;
1053 case DP_TRAIN_VOLTAGE_SWING_600:
1054 return DP_TRAIN_PRE_EMPHASIS_6;
1055 case DP_TRAIN_VOLTAGE_SWING_800:
1056 return DP_TRAIN_PRE_EMPHASIS_3_5;
1057 case DP_TRAIN_VOLTAGE_SWING_1200:
1059 return DP_TRAIN_PRE_EMPHASIS_0;
1064 intel_get_adjust_train(struct intel_dp *intel_dp)
1070 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1071 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1072 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1080 if (v >= I830_DP_VOLTAGE_MAX)
1081 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1083 if (p >= intel_dp_pre_emphasis_max(v))
1084 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1086 for (lane = 0; lane < 4; lane++)
1087 intel_dp->train_set[lane] = v | p;
1091 intel_dp_signal_levels(struct intel_dp *intel_dp)
1093 struct drm_device *dev = intel_dp->base.base.dev;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 uint32_t signal_levels = 0;
1096 u8 train_set = intel_dp->train_set[0];
1097 u32 vswing = train_set & DP_TRAIN_VOLTAGE_SWING_MASK;
1098 u32 preemphasis = train_set & DP_TRAIN_PRE_EMPHASIS_MASK;
1100 if (is_edp(intel_dp)) {
1101 vswing = dev_priv->edp.vswing;
1102 preemphasis = dev_priv->edp.preemphasis;
1106 case DP_TRAIN_VOLTAGE_SWING_400:
1108 signal_levels |= DP_VOLTAGE_0_4;
1110 case DP_TRAIN_VOLTAGE_SWING_600:
1111 signal_levels |= DP_VOLTAGE_0_6;
1113 case DP_TRAIN_VOLTAGE_SWING_800:
1114 signal_levels |= DP_VOLTAGE_0_8;
1116 case DP_TRAIN_VOLTAGE_SWING_1200:
1117 signal_levels |= DP_VOLTAGE_1_2;
1120 switch (preemphasis) {
1121 case DP_TRAIN_PRE_EMPHASIS_0:
1123 signal_levels |= DP_PRE_EMPHASIS_0;
1125 case DP_TRAIN_PRE_EMPHASIS_3_5:
1126 signal_levels |= DP_PRE_EMPHASIS_3_5;
1128 case DP_TRAIN_PRE_EMPHASIS_6:
1129 signal_levels |= DP_PRE_EMPHASIS_6;
1131 case DP_TRAIN_PRE_EMPHASIS_9_5:
1132 signal_levels |= DP_PRE_EMPHASIS_9_5;
1135 return signal_levels;
1138 /* Gen6's DP voltage swing and pre-emphasis control */
1140 intel_gen6_edp_signal_levels(uint8_t train_set)
1142 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1143 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1144 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1145 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1146 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1147 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1148 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1149 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1150 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1152 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1153 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1158 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1161 int i = DP_LANE0_1_STATUS + (lane >> 1);
1162 int s = (lane & 1) * 4;
1163 uint8_t l = intel_dp_link_status(link_status, i);
1165 return (l >> s) & 0xf;
1168 /* Check for clock recovery is done on all channels */
1170 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1173 uint8_t lane_status;
1175 for (lane = 0; lane < lane_count; lane++) {
1176 lane_status = intel_get_lane_status(link_status, lane);
1177 if ((lane_status & DP_LANE_CR_DONE) == 0)
1183 /* Check to see if channel eq is done on all channels */
1184 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1185 DP_LANE_CHANNEL_EQ_DONE|\
1186 DP_LANE_SYMBOL_LOCKED)
1188 intel_channel_eq_ok(struct intel_dp *intel_dp)
1191 uint8_t lane_status;
1194 lane_align = intel_dp_link_status(intel_dp->link_status,
1195 DP_LANE_ALIGN_STATUS_UPDATED);
1196 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1198 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1199 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1200 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1207 intel_dp_aux_handshake_required(struct intel_dp *intel_dp)
1209 struct drm_device *dev = intel_dp->base.base.dev;
1210 struct drm_i915_private *dev_priv = dev->dev_private;
1212 if (is_edp(intel_dp) && dev_priv->no_aux_handshake)
1219 intel_dp_set_link_train(struct intel_dp *intel_dp,
1220 uint32_t dp_reg_value,
1221 uint8_t dp_train_pat)
1223 struct drm_device *dev = intel_dp->base.base.dev;
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1227 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1228 POSTING_READ(intel_dp->output_reg);
1230 if (!intel_dp_aux_handshake_required(intel_dp))
1233 intel_dp_aux_native_write_1(intel_dp,
1234 DP_TRAINING_PATTERN_SET,
1237 ret = intel_dp_aux_native_write(intel_dp,
1238 DP_TRAINING_LANE0_SET,
1239 intel_dp->train_set, 4);
1246 /* Enable corresponding port and start training pattern 1 */
1248 intel_dp_start_link_train(struct intel_dp *intel_dp)
1250 struct drm_device *dev = intel_dp->base.base.dev;
1251 struct drm_i915_private *dev_priv = dev->dev_private;
1252 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1255 bool clock_recovery = false;
1258 uint32_t DP = intel_dp->DP;
1260 /* Enable output, wait for it to become active */
1261 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1262 POSTING_READ(intel_dp->output_reg);
1263 intel_wait_for_vblank(dev, intel_crtc->pipe);
1265 if (intel_dp_aux_handshake_required(intel_dp))
1266 /* Write the link configuration data */
1267 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1268 intel_dp->link_configuration,
1269 DP_LINK_CONFIGURATION_SIZE);
1272 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1273 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1275 DP &= ~DP_LINK_TRAIN_MASK;
1276 memset(intel_dp->train_set, 0, 4);
1279 clock_recovery = false;
1281 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1282 uint32_t signal_levels;
1283 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1284 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1285 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1287 signal_levels = intel_dp_signal_levels(intel_dp);
1288 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1291 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1292 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1294 reg = DP | DP_LINK_TRAIN_PAT_1;
1296 if (!intel_dp_set_link_train(intel_dp, reg,
1297 DP_TRAINING_PATTERN_1))
1299 /* Set training pattern 1 */
1302 if (intel_dp_aux_handshake_required(intel_dp)) {
1305 if (!intel_dp_get_link_status(intel_dp))
1308 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1309 clock_recovery = true;
1313 /* Check to see if we've tried the max voltage */
1314 for (i = 0; i < intel_dp->lane_count; i++)
1315 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1317 if (i == intel_dp->lane_count)
1320 /* Check to see if we've tried the same voltage 5 times */
1321 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1327 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1329 /* Compute new intel_dp->train_set as requested by target */
1330 intel_get_adjust_train(intel_dp);
1338 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1340 struct drm_device *dev = intel_dp->base.base.dev;
1341 struct drm_i915_private *dev_priv = dev->dev_private;
1342 bool channel_eq = false;
1345 uint32_t DP = intel_dp->DP;
1347 /* channel equalization */
1351 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1352 uint32_t signal_levels;
1354 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1355 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1356 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1358 signal_levels = intel_dp_signal_levels(intel_dp);
1359 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1362 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1363 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1365 reg = DP | DP_LINK_TRAIN_PAT_2;
1367 /* channel eq pattern */
1368 if (!intel_dp_set_link_train(intel_dp, reg,
1369 DP_TRAINING_PATTERN_2))
1374 if (!intel_dp_aux_handshake_required(intel_dp)) {
1377 if (!intel_dp_get_link_status(intel_dp))
1380 if (intel_channel_eq_ok(intel_dp)) {
1389 /* Compute new intel_dp->train_set as requested by target */
1390 intel_get_adjust_train(intel_dp);
1394 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1395 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1397 reg = DP | DP_LINK_TRAIN_OFF;
1399 I915_WRITE(intel_dp->output_reg, reg);
1400 POSTING_READ(intel_dp->output_reg);
1401 intel_dp_aux_native_write_1(intel_dp,
1402 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1406 intel_dp_link_down(struct intel_dp *intel_dp)
1408 struct drm_device *dev = intel_dp->base.base.dev;
1409 struct drm_i915_private *dev_priv = dev->dev_private;
1410 uint32_t DP = intel_dp->DP;
1412 DRM_DEBUG_KMS("\n");
1414 if (is_edp(intel_dp)) {
1415 DP &= ~DP_PLL_ENABLE;
1416 I915_WRITE(intel_dp->output_reg, DP);
1417 POSTING_READ(intel_dp->output_reg);
1421 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1422 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1423 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1425 DP &= ~DP_LINK_TRAIN_MASK;
1426 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1428 POSTING_READ(intel_dp->output_reg);
1432 if (is_edp(intel_dp))
1433 DP |= DP_LINK_TRAIN_OFF;
1434 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1435 POSTING_READ(intel_dp->output_reg);
1439 * According to DP spec
1442 * 2. Configure link according to Receiver Capabilities
1443 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1444 * 4. Check link status on receipt of hot-plug interrupt
1448 intel_dp_check_link_status(struct intel_dp *intel_dp)
1450 if (!intel_dp->base.base.crtc)
1453 if (!intel_dp_get_link_status(intel_dp)) {
1454 intel_dp_link_down(intel_dp);
1458 if (!intel_channel_eq_ok(intel_dp)) {
1459 intel_dp_start_link_train(intel_dp);
1460 intel_dp_complete_link_train(intel_dp);
1464 static enum drm_connector_status
1465 ironlake_dp_detect(struct drm_connector *connector)
1467 struct intel_dp *intel_dp = intel_attached_dp(connector);
1468 enum drm_connector_status status;
1470 /* Can't disconnect eDP */
1471 if (is_edp(intel_dp))
1472 return connector_status_connected;
1474 status = connector_status_disconnected;
1475 if (intel_dp_aux_native_read(intel_dp,
1476 0x000, intel_dp->dpcd,
1477 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1479 if (intel_dp->dpcd[0] != 0)
1480 status = connector_status_connected;
1482 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1483 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1488 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1490 * \return true if DP port is connected.
1491 * \return false if DP port is disconnected.
1493 static enum drm_connector_status
1494 intel_dp_detect(struct drm_connector *connector, bool force)
1496 struct intel_dp *intel_dp = intel_attached_dp(connector);
1497 struct drm_device *dev = intel_dp->base.base.dev;
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1500 enum drm_connector_status status;
1502 intel_dp->has_audio = false;
1504 if (HAS_PCH_SPLIT(dev))
1505 return ironlake_dp_detect(connector);
1507 switch (intel_dp->output_reg) {
1509 bit = DPB_HOTPLUG_INT_STATUS;
1512 bit = DPC_HOTPLUG_INT_STATUS;
1515 bit = DPD_HOTPLUG_INT_STATUS;
1518 return connector_status_unknown;
1521 temp = I915_READ(PORT_HOTPLUG_STAT);
1523 if ((temp & bit) == 0)
1524 return connector_status_disconnected;
1526 status = connector_status_disconnected;
1527 if (intel_dp_aux_native_read(intel_dp,
1528 0x000, intel_dp->dpcd,
1529 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1531 if (intel_dp->dpcd[0] != 0)
1532 status = connector_status_connected;
1537 static int intel_dp_get_modes(struct drm_connector *connector)
1539 struct intel_dp *intel_dp = intel_attached_dp(connector);
1540 struct drm_device *dev = intel_dp->base.base.dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1544 /* We should parse the EDID data and find out if it has an audio sink
1547 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1549 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1550 struct drm_display_mode *newmode;
1551 list_for_each_entry(newmode, &connector->probed_modes,
1553 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1554 dev_priv->panel_fixed_mode =
1555 drm_mode_duplicate(dev, newmode);
1564 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1565 if (is_edp(intel_dp)) {
1566 if (dev_priv->panel_fixed_mode != NULL) {
1567 struct drm_display_mode *mode;
1568 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1569 drm_mode_probed_add(connector, mode);
1577 intel_dp_destroy (struct drm_connector *connector)
1579 drm_sysfs_connector_remove(connector);
1580 drm_connector_cleanup(connector);
1584 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1586 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1588 i2c_del_adapter(&intel_dp->adapter);
1589 drm_encoder_cleanup(encoder);
1593 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1594 .dpms = intel_dp_dpms,
1595 .mode_fixup = intel_dp_mode_fixup,
1596 .prepare = intel_dp_prepare,
1597 .mode_set = intel_dp_mode_set,
1598 .commit = intel_dp_commit,
1601 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1602 .dpms = drm_helper_connector_dpms,
1603 .detect = intel_dp_detect,
1604 .fill_modes = drm_helper_probe_single_connector_modes,
1605 .destroy = intel_dp_destroy,
1608 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1609 .get_modes = intel_dp_get_modes,
1610 .mode_valid = intel_dp_mode_valid,
1611 .best_encoder = intel_best_encoder,
1614 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1615 .destroy = intel_dp_encoder_destroy,
1619 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1621 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1623 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1624 intel_dp_check_link_status(intel_dp);
1627 /* Return which DP Port should be selected for Transcoder DP control */
1629 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1631 struct drm_device *dev = crtc->dev;
1632 struct drm_mode_config *mode_config = &dev->mode_config;
1633 struct drm_encoder *encoder;
1635 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1636 struct intel_dp *intel_dp;
1638 if (encoder->crtc != crtc)
1641 intel_dp = enc_to_intel_dp(encoder);
1642 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1643 return intel_dp->output_reg;
1649 /* check the VBT to see whether the eDP is on DP-D port */
1650 bool intel_dpd_is_edp(struct drm_device *dev)
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 struct child_device_config *p_child;
1656 if (!dev_priv->child_dev_num)
1659 for (i = 0; i < dev_priv->child_dev_num; i++) {
1660 p_child = dev_priv->child_dev + i;
1662 if (p_child->dvo_port == PORT_IDPD &&
1663 p_child->device_type == DEVICE_TYPE_eDP)
1670 intel_dp_init(struct drm_device *dev, int output_reg)
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 struct drm_connector *connector;
1674 struct intel_dp *intel_dp;
1675 struct intel_encoder *intel_encoder;
1676 struct intel_connector *intel_connector;
1677 const char *name = NULL;
1680 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1684 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1685 if (!intel_connector) {
1689 intel_encoder = &intel_dp->base;
1691 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1692 if (intel_dpd_is_edp(dev))
1693 intel_dp->is_pch_edp = true;
1695 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1696 type = DRM_MODE_CONNECTOR_eDP;
1697 intel_encoder->type = INTEL_OUTPUT_EDP;
1699 type = DRM_MODE_CONNECTOR_DisplayPort;
1700 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1703 connector = &intel_connector->base;
1704 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1705 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1707 connector->polled = DRM_CONNECTOR_POLL_HPD;
1709 if (output_reg == DP_B || output_reg == PCH_DP_B)
1710 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1711 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1712 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1713 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1714 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1716 if (is_edp(intel_dp))
1717 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1719 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1720 connector->interlace_allowed = true;
1721 connector->doublescan_allowed = 0;
1723 intel_dp->output_reg = output_reg;
1724 intel_dp->has_audio = false;
1725 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1727 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1728 DRM_MODE_ENCODER_TMDS);
1729 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1731 intel_connector_attach_encoder(intel_connector, intel_encoder);
1732 drm_sysfs_connector_add(connector);
1734 /* Set up the DDC bus. */
1735 switch (output_reg) {
1741 dev_priv->hotplug_supported_mask |=
1742 HDMIB_HOTPLUG_INT_STATUS;
1747 dev_priv->hotplug_supported_mask |=
1748 HDMIC_HOTPLUG_INT_STATUS;
1753 dev_priv->hotplug_supported_mask |=
1754 HDMID_HOTPLUG_INT_STATUS;
1759 intel_dp_i2c_init(intel_dp, intel_connector, name);
1761 /* Cache some DPCD data in the eDP case */
1762 if (is_edp(intel_dp)) {
1766 was_on = ironlake_edp_panel_on(intel_dp);
1767 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1769 sizeof(intel_dp->dpcd));
1770 if (ret == sizeof(intel_dp->dpcd)) {
1771 if (intel_dp->dpcd[0] >= 0x11)
1772 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1773 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1775 DRM_ERROR("failed to retrieve link info\n");
1778 ironlake_edp_panel_off(dev);
1781 intel_encoder->hot_plug = intel_dp_hot_plug;
1783 if (is_edp(intel_dp)) {
1784 /* initialize panel mode from VBT if available for eDP */
1785 if (dev_priv->lfp_lvds_vbt_mode) {
1786 dev_priv->panel_fixed_mode =
1787 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1788 if (dev_priv->panel_fixed_mode) {
1789 dev_priv->panel_fixed_mode->type |=
1790 DRM_MODE_TYPE_PREFERRED;
1795 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1796 * 0xd. Failure to do so will result in spurious interrupts being
1797 * generated on the port when a cable is not attached.
1799 if (IS_G4X(dev) && !IS_GM45(dev)) {
1800 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1801 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);