drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 364 {
 365         unsigned long flags;
 366         u32 val = 0;
 367
 368         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 369         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 370                 DRM_ERROR("DPIO idle wait timed out\n");
 371                 goto out_unlock;
 372         }
 373
 374         I915_WRITE(DPIO_REG, reg);
 375         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 376                    DPIO_BYTE);
 377         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 378                 DRM_ERROR("DPIO read wait timed out\n");
 379                 goto out_unlock;
 380         }
 381         val = I915_READ(DPIO_DATA);
 382
 383 out_unlock:
 384         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 385         return val;
 386 }
 387
 388 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 389                              u32 val)
 390 {
 391         unsigned long flags;
 392
 393         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 394         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 395                 DRM_ERROR("DPIO idle wait timed out\n");
 396                 goto out_unlock;
 397         }
 398
 399         I915_WRITE(DPIO_DATA, val);
 400         I915_WRITE(DPIO_REG, reg);
 401         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 402                    DPIO_BYTE);
 403         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 404                 DRM_ERROR("DPIO write wait timed out\n");
 405
 406 out_unlock:
 407         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 408 }
 409
 410 static void vlv_init_dpio(struct drm_device *dev)
 411 {
 412         struct drm_i915_private *dev_priv = dev->dev_private;
 413
 414         /* Reset the DPIO config */
 415         I915_WRITE(DPIO_CTL, 0);
 416         POSTING_READ(DPIO_CTL);
 417         I915_WRITE(DPIO_CTL, 1);
 418         POSTING_READ(DPIO_CTL);
 419 }
 420
 421 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 422                               unsigned int reg)
 423 {
 424         unsigned int val;
 425
 426         /* use the module option value if specified */
 427         if (i915_lvds_channel_mode > 0)
 428                 return i915_lvds_channel_mode == 2;
 429
 430         if (dev_priv->lvds_val)
 431                 val = dev_priv->lvds_val;
 432         else {
 433                 /* BIOS should set the proper LVDS register value at boot, but
 434                  * in reality, it doesn't set the value when the lid is closed;
 435                  * we need to check "the value to be set" in VBT when LVDS
 436                  * register is uninitialized.
 437                  */
 438                 val = I915_READ(reg);
 439                 if (!(val & ~LVDS_DETECTED))
 440                         val = dev_priv->bios_lvds_val;
 441                 dev_priv->lvds_val = val;
 442         }
 443         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 444 }
 445
 446 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 447                                                 int refclk)
 448 {
 449         struct drm_device *dev = crtc->dev;
 450         struct drm_i915_private *dev_priv = dev->dev_private;
 451         const intel_limit_t *limit;
 452
 453         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 454                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 455                         /* LVDS dual channel */
 456                         if (refclk == 100000)
 457                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 458                         else
 459                                 limit = &intel_limits_ironlake_dual_lvds;
 460                 } else {
 461                         if (refclk == 100000)
 462                                 limit = &intel_limits_ironlake_single_lvds_100m;
 463                         else
 464                                 limit = &intel_limits_ironlake_single_lvds;
 465                 }
 466         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 467                         HAS_eDP)
 468                 limit = &intel_limits_ironlake_display_port;
 469         else
 470                 limit = &intel_limits_ironlake_dac;
 471
 472         return limit;
 473 }
 474
 475 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 476 {
 477         struct drm_device *dev = crtc->dev;
 478         struct drm_i915_private *dev_priv = dev->dev_private;
 479         const intel_limit_t *limit;
 480
 481         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 482                 if (is_dual_link_lvds(dev_priv, LVDS))
 483                         /* LVDS with dual channel */
 484                         limit = &intel_limits_g4x_dual_channel_lvds;
 485                 else
 486                         /* LVDS with dual channel */
 487                         limit = &intel_limits_g4x_single_channel_lvds;
 488         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 489                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 490                 limit = &intel_limits_g4x_hdmi;
 491         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 492                 limit = &intel_limits_g4x_sdvo;
 493         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 494                 limit = &intel_limits_g4x_display_port;
 495         } else /* The option is for other outputs */
 496                 limit = &intel_limits_i9xx_sdvo;
 497
 498         return limit;
 499 }
 500
 501 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 502 {
 503         struct drm_device *dev = crtc->dev;
 504         const intel_limit_t *limit;
 505
 506         if (HAS_PCH_SPLIT(dev))
 507                 limit = intel_ironlake_limit(crtc, refclk);
 508         else if (IS_G4X(dev)) {
 509                 limit = intel_g4x_limit(crtc);
 510         } else if (IS_PINEVIEW(dev)) {
 511                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 512                         limit = &intel_limits_pineview_lvds;
 513                 else
 514                         limit = &intel_limits_pineview_sdvo;
 515         } else if (!IS_GEN2(dev)) {
 516                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 517                         limit = &intel_limits_i9xx_lvds;
 518                 else
 519                         limit = &intel_limits_i9xx_sdvo;
 520         } else {
 521                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 522                         limit = &intel_limits_i8xx_lvds;
 523                 else
 524                         limit = &intel_limits_i8xx_dvo;
 525         }
 526         return limit;
 527 }
 528
 529 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 530 static void pineview_clock(int refclk, intel_clock_t *clock)
 531 {
 532         clock->m = clock->m2 + 2;
 533         clock->p = clock->p1 * clock->p2;
 534         clock->vco = refclk * clock->m / clock->n;
 535         clock->dot = clock->vco / clock->p;
 536 }
 537
 538 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 539 {
 540         if (IS_PINEVIEW(dev)) {
 541                 pineview_clock(refclk, clock);
 542                 return;
 543         }
 544         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 545         clock->p = clock->p1 * clock->p2;
 546         clock->vco = refclk * clock->m / (clock->n + 2);
 547         clock->dot = clock->vco / clock->p;
 548 }
 549
 550 /**
 551  * Returns whether any output on the specified pipe is of the specified type
 552  */
 553 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 554 {
 555         struct drm_device *dev = crtc->dev;
 556         struct drm_mode_config *mode_config = &dev->mode_config;
 557         struct intel_encoder *encoder;
 558
 559         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 560                 if (encoder->base.crtc == crtc && encoder->type == type)
 561                         return true;
 562
 563         return false;
 564 }
 565
 566 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 567 /**
 568  * Returns whether the given set of divisors are valid for a given refclk with
 569  * the given connectors.
 570  */
 571
 572 static bool intel_PLL_is_valid(struct drm_device *dev,
 573                                const intel_limit_t *limit,
 574                                const intel_clock_t *clock)
 575 {
 576         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 577                 INTELPllInvalid("p1 out of range\n");
 578         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 579                 INTELPllInvalid("p out of range\n");
 580         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 581                 INTELPllInvalid("m2 out of range\n");
 582         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 583                 INTELPllInvalid("m1 out of range\n");
 584         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 585                 INTELPllInvalid("m1 <= m2\n");
 586         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 587                 INTELPllInvalid("m out of range\n");
 588         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 589                 INTELPllInvalid("n out of range\n");
 590         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 591                 INTELPllInvalid("vco out of range\n");
 592         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 593          * connector, etc., rather than just a single range.
 594          */
 595         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 596                 INTELPllInvalid("dot out of range\n");
 597
 598         return true;
 599 }
 600
 601 static bool
 602 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 603                     int target, int refclk, intel_clock_t *match_clock,
 604                     intel_clock_t *best_clock)
 605
 606 {
 607         struct drm_device *dev = crtc->dev;
 608         struct drm_i915_private *dev_priv = dev->dev_private;
 609         intel_clock_t clock;
 610         int err = target;
 611
 612         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 613             (I915_READ(LVDS)) != 0) {
 614                 /*
 615                  * For LVDS, if the panel is on, just rely on its current
 616                  * settings for dual-channel.  We haven't figured out how to
 617                  * reliably set up different single/dual channel state, if we
 618                  * even can.
 619                  */
 620                 if (is_dual_link_lvds(dev_priv, LVDS))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632
 633         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 634              clock.m1++) {
 635                 for (clock.m2 = limit->m2.min;
 636                      clock.m2 <= limit->m2.max; clock.m2++) {
 637                         /* m1 is always 0 in Pineview */
 638                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 639                                 break;
 640                         for (clock.n = limit->n.min;
 641                              clock.n <= limit->n.max; clock.n++) {
 642                                 for (clock.p1 = limit->p1.min;
 643                                         clock.p1 <= limit->p1.max; clock.p1++) {
 644                                         int this_err;
 645
 646                                         intel_clock(dev, refclk, &clock);
 647                                         if (!intel_PLL_is_valid(dev, limit,
 648                                                                 &clock))
 649                                                 continue;
 650                                         if (match_clock &&
 651                                             clock.p != match_clock->p)
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err) {
 656                                                 *best_clock = clock;
 657                                                 err = this_err;
 658                                         }
 659                                 }
 660                         }
 661                 }
 662         }
 663
 664         return (err != target);
 665 }
 666
 667 static bool
 668 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 669                         int target, int refclk, intel_clock_t *match_clock,
 670                         intel_clock_t *best_clock)
 671 {
 672         struct drm_device *dev = crtc->dev;
 673         struct drm_i915_private *dev_priv = dev->dev_private;
 674         intel_clock_t clock;
 675         int max_n;
 676         bool found;
 677         /* approximately equals target * 0.00585 */
 678         int err_most = (target >> 8) + (target >> 9);
 679         found = false;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 int lvds_reg;
 683
 684                 if (HAS_PCH_SPLIT(dev))
 685                         lvds_reg = PCH_LVDS;
 686                 else
 687                         lvds_reg = LVDS;
 688                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 689                     LVDS_CLKB_POWER_UP)
 690                         clock.p2 = limit->p2.p2_fast;
 691                 else
 692                         clock.p2 = limit->p2.p2_slow;
 693         } else {
 694                 if (target < limit->p2.dot_limit)
 695                         clock.p2 = limit->p2.p2_slow;
 696                 else
 697                         clock.p2 = limit->p2.p2_fast;
 698         }
 699
 700         memset(best_clock, 0, sizeof(*best_clock));
 701         max_n = limit->n.max;
 702         /* based on hardware requirement, prefer smaller n to precision */
 703         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 704                 /* based on hardware requirement, prefere larger m1,m2 */
 705                 for (clock.m1 = limit->m1.max;
 706                      clock.m1 >= limit->m1.min; clock.m1--) {
 707                         for (clock.m2 = limit->m2.max;
 708                              clock.m2 >= limit->m2.min; clock.m2--) {
 709                                 for (clock.p1 = limit->p1.max;
 710                                      clock.p1 >= limit->p1.min; clock.p1--) {
 711                                         int this_err;
 712
 713                                         intel_clock(dev, refclk, &clock);
 714                                         if (!intel_PLL_is_valid(dev, limit,
 715                                                                 &clock))
 716                                                 continue;
 717                                         if (match_clock &&
 718                                             clock.p != match_clock->p)
 719                                                 continue;
 720
 721                                         this_err = abs(clock.dot - target);
 722                                         if (this_err < err_most) {
 723                                                 *best_clock = clock;
 724                                                 err_most = this_err;
 725                                                 max_n = clock.n;
 726                                                 found = true;
 727                                         }
 728                                 }
 729                         }
 730                 }
 731         }
 732         return found;
 733 }
 734
 735 static bool
 736 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 737                            int target, int refclk, intel_clock_t *match_clock,
 738                            intel_clock_t *best_clock)
 739 {
 740         struct drm_device *dev = crtc->dev;
 741         intel_clock_t clock;
 742
 743         if (target < 200000) {
 744                 clock.n = 1;
 745                 clock.p1 = 2;
 746                 clock.p2 = 10;
 747                 clock.m1 = 12;
 748                 clock.m2 = 9;
 749         } else {
 750                 clock.n = 2;
 751                 clock.p1 = 1;
 752                 clock.p2 = 10;
 753                 clock.m1 = 14;
 754                 clock.m2 = 8;
 755         }
 756         intel_clock(dev, refclk, &clock);
 757         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 758         return true;
 759 }
 760
 761 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 762 static bool
 763 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 764                       int target, int refclk, intel_clock_t *match_clock,
 765                       intel_clock_t *best_clock)
 766 {
 767         intel_clock_t clock;
 768         if (target < 200000) {
 769                 clock.p1 = 2;
 770                 clock.p2 = 10;
 771                 clock.n = 2;
 772                 clock.m1 = 23;
 773                 clock.m2 = 8;
 774         } else {
 775                 clock.p1 = 1;
 776                 clock.p2 = 10;
 777                 clock.n = 1;
 778                 clock.m1 = 14;
 779                 clock.m2 = 2;
 780         }
 781         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 782         clock.p = (clock.p1 * clock.p2);
 783         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 784         clock.vco = 0;
 785         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 786         return true;
 787 }
 788
 789 /**
 790  * intel_wait_for_vblank - wait for vblank on a given pipe
 791  * @dev: drm device
 792  * @pipe: pipe to wait for
 793  *
 794  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 795  * mode setting code.
 796  */
 797 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 798 {
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         int pipestat_reg = PIPESTAT(pipe);
 801
 802         /* Clear existing vblank status. Note this will clear any other
 803          * sticky status fields as well.
 804          *
 805          * This races with i915_driver_irq_handler() with the result
 806          * that either function could miss a vblank event.  Here it is not
 807          * fatal, as we will either wait upon the next vblank interrupt or
 808          * timeout.  Generally speaking intel_wait_for_vblank() is only
 809          * called during modeset at which time the GPU should be idle and
 810          * should *not* be performing page flips and thus not waiting on
 811          * vblanks...
 812          * Currently, the result of us stealing a vblank from the irq
 813          * handler is that a single frame will be skipped during swapbuffers.
 814          */
 815         I915_WRITE(pipestat_reg,
 816                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 817
 818         /* Wait for vblank interrupt bit to set */
 819         if (wait_for(I915_READ(pipestat_reg) &
 820                      PIPE_VBLANK_INTERRUPT_STATUS,
 821                      50))
 822                 DRM_DEBUG_KMS("vblank wait timed out\n");
 823 }
 824
 825 /*
 826  * intel_wait_for_pipe_off - wait for pipe to turn off
 827  * @dev: drm device
 828  * @pipe: pipe to wait for
 829  *
 830  * After disabling a pipe, we can't wait for vblank in the usual way,
 831  * spinning on the vblank interrupt status bit, since we won't actually
 832  * see an interrupt when the pipe is disabled.
 833  *
 834  * On Gen4 and above:
 835  *   wait for the pipe register state bit to turn off
 836  *
 837  * Otherwise:
 838  *   wait for the display line value to settle (it usually
 839  *   ends up stopping at the start of the next frame).
 840  *
 841  */
 842 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 843 {
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845
 846         if (INTEL_INFO(dev)->gen >= 4) {
 847                 int reg = PIPECONF(pipe);
 848
 849                 /* Wait for the Pipe State to go off */
 850                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 851                              100))
 852                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 853         } else {
 854                 u32 last_line;
 855                 int reg = PIPEDSL(pipe);
 856                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 857
 858                 /* Wait for the display line to settle */
 859                 do {
 860                         last_line = I915_READ(reg) & DSL_LINEMASK;
 861                         mdelay(5);
 862                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 863                          time_after(timeout, jiffies));
 864                 if (time_after(jiffies, timeout))
 865                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 866         }
 867 }
 868
 869 static const char *state_string(bool enabled)
 870 {
 871         return enabled ? "on" : "off";
 872 }
 873
 874 /* Only for pre-ILK configs */
 875 static void assert_pll(struct drm_i915_private *dev_priv,
 876                        enum pipe pipe, bool state)
 877 {
 878         int reg;
 879         u32 val;
 880         bool cur_state;
 881
 882         reg = DPLL(pipe);
 883         val = I915_READ(reg);
 884         cur_state = !!(val & DPLL_VCO_ENABLE);
 885         WARN(cur_state != state,
 886              "PLL state assertion failure (expected %s, current %s)\n",
 887              state_string(state), state_string(cur_state));
 888 }
 889 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 890 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 891
 892 /* For ILK+ */
 893 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 894                            enum pipe pipe, bool state)
 895 {
 896         int reg;
 897         u32 val;
 898         bool cur_state;
 899
 900         if (HAS_PCH_CPT(dev_priv->dev)) {
 901                 u32 pch_dpll;
 902
 903                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 904
 905                 /* Make sure the selected PLL is enabled to the transcoder */
 906                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 907                      "transcoder %d PLL not enabled\n", pipe);
 908
 909                 /* Convert the transcoder pipe number to a pll pipe number */
 910                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 911         }
 912
 913         reg = PCH_DPLL(pipe);
 914         val = I915_READ(reg);
 915         cur_state = !!(val & DPLL_VCO_ENABLE);
 916         WARN(cur_state != state,
 917              "PCH PLL state assertion failure (expected %s, current %s)\n",
 918              state_string(state), state_string(cur_state));
 919 }
 920 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 921 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 922
 923 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 924                           enum pipe pipe, bool state)
 925 {
 926         int reg;
 927         u32 val;
 928         bool cur_state;
 929
 930         reg = FDI_TX_CTL(pipe);
 931         val = I915_READ(reg);
 932         cur_state = !!(val & FDI_TX_ENABLE);
 933         WARN(cur_state != state,
 934              "FDI TX state assertion failure (expected %s, current %s)\n",
 935              state_string(state), state_string(cur_state));
 936 }
 937 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 938 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 939
 940 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 941                           enum pipe pipe, bool state)
 942 {
 943         int reg;
 944         u32 val;
 945         bool cur_state;
 946
 947         reg = FDI_RX_CTL(pipe);
 948         val = I915_READ(reg);
 949         cur_state = !!(val & FDI_RX_ENABLE);
 950         WARN(cur_state != state,
 951              "FDI RX state assertion failure (expected %s, current %s)\n",
 952              state_string(state), state_string(cur_state));
 953 }
 954 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 955 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 956
 957 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 958                                       enum pipe pipe)
 959 {
 960         int reg;
 961         u32 val;
 962
 963         /* ILK FDI PLL is always enabled */
 964         if (dev_priv->info->gen == 5)
 965                 return;
 966
 967         reg = FDI_TX_CTL(pipe);
 968         val = I915_READ(reg);
 969         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 970 }
 971
 972 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 973                                       enum pipe pipe)
 974 {
 975         int reg;
 976         u32 val;
 977
 978         reg = FDI_RX_CTL(pipe);
 979         val = I915_READ(reg);
 980         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 981 }
 982
 983 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 984                                   enum pipe pipe)
 985 {
 986         int pp_reg, lvds_reg;
 987         u32 val;
 988         enum pipe panel_pipe = PIPE_A;
 989         bool locked = true;
 990
 991         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 992                 pp_reg = PCH_PP_CONTROL;
 993                 lvds_reg = PCH_LVDS;
 994         } else {
 995                 pp_reg = PP_CONTROL;
 996                 lvds_reg = LVDS;
 997         }
 998
 999         val = I915_READ(pp_reg);
1000         if (!(val & PANEL_POWER_ON) ||
1001             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1002                 locked = false;
1003
1004         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1005                 panel_pipe = PIPE_B;
1006
1007         WARN(panel_pipe == pipe && locked,
1008              "panel assertion failure, pipe %c regs locked\n",
1009              pipe_name(pipe));
1010 }
1011
1012 void assert_pipe(struct drm_i915_private *dev_priv,
1013                  enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         /* if we need the pipe A quirk it must be always on */
1020         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1021                 state = true;
1022
1023         reg = PIPECONF(pipe);
1024         val = I915_READ(reg);
1025         cur_state = !!(val & PIPECONF_ENABLE);
1026         WARN(cur_state != state,
1027              "pipe %c assertion failure (expected %s, current %s)\n",
1028              pipe_name(pipe), state_string(state), state_string(cur_state));
1029 }
1030
1031 static void assert_plane(struct drm_i915_private *dev_priv,
1032                          enum plane plane, bool state)
1033 {
1034         int reg;
1035         u32 val;
1036         bool cur_state;
1037
1038         reg = DSPCNTR(plane);
1039         val = I915_READ(reg);
1040         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1041         WARN(cur_state != state,
1042              "plane %c assertion failure (expected %s, current %s)\n",
1043              plane_name(plane), state_string(state), state_string(cur_state));
1044 }
1045
1046 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1047 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1048
1049 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1050                                    enum pipe pipe)
1051 {
1052         int reg, i;
1053         u32 val;
1054         int cur_pipe;
1055
1056         /* Planes are fixed to pipes on ILK+ */
1057         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1058                 reg = DSPCNTR(pipe);
1059                 val = I915_READ(reg);
1060                 WARN((val & DISPLAY_PLANE_ENABLE),
1061                      "plane %c assertion failure, should be disabled but not\n",
1062                      plane_name(pipe));
1063                 return;
1064         }
1065
1066         /* Need to check both planes against the pipe */
1067         for (i = 0; i < 2; i++) {
1068                 reg = DSPCNTR(i);
1069                 val = I915_READ(reg);
1070                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1071                         DISPPLANE_SEL_PIPE_SHIFT;
1072                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1073                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1074                      plane_name(i), pipe_name(pipe));
1075         }
1076 }
1077
1078 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1079 {
1080         u32 val;
1081         bool enabled;
1082
1083         val = I915_READ(PCH_DREF_CONTROL);
1084         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1085                             DREF_SUPERSPREAD_SOURCE_MASK));
1086         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1087 }
1088
1089 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1090                                        enum pipe pipe)
1091 {
1092         int reg;
1093         u32 val;
1094         bool enabled;
1095
1096         reg = TRANSCONF(pipe);
1097         val = I915_READ(reg);
1098         enabled = !!(val & TRANS_ENABLE);
1099         WARN(enabled,
1100              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1101              pipe_name(pipe));
1102 }
1103
1104 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1105                             enum pipe pipe, u32 port_sel, u32 val)
1106 {
1107         if ((val & DP_PORT_EN) == 0)
1108                 return false;
1109
1110         if (HAS_PCH_CPT(dev_priv->dev)) {
1111                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1112                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1113                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1114                         return false;
1115         } else {
1116                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1117                         return false;
1118         }
1119         return true;
1120 }
1121
1122 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1123                               enum pipe pipe, u32 val)
1124 {
1125         if ((val & PORT_ENABLE) == 0)
1126                 return false;
1127
1128         if (HAS_PCH_CPT(dev_priv->dev)) {
1129                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1130                         return false;
1131         } else {
1132                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1133                         return false;
1134         }
1135         return true;
1136 }
1137
1138 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1139                               enum pipe pipe, u32 val)
1140 {
1141         if ((val & LVDS_PORT_EN) == 0)
1142                 return false;
1143
1144         if (HAS_PCH_CPT(dev_priv->dev)) {
1145                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1146                         return false;
1147         } else {
1148                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1149                         return false;
1150         }
1151         return true;
1152 }
1153
1154 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1155                               enum pipe pipe, u32 val)
1156 {
1157         if ((val & ADPA_DAC_ENABLE) == 0)
1158                 return false;
1159         if (HAS_PCH_CPT(dev_priv->dev)) {
1160                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1161                         return false;
1162         } else {
1163                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1164                         return false;
1165         }
1166         return true;
1167 }
1168
1169 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1170                                    enum pipe pipe, int reg, u32 port_sel)
1171 {
1172         u32 val = I915_READ(reg);
1173         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1174              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1175              reg, pipe_name(pipe));
1176 }
1177
1178 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1179                                      enum pipe pipe, int reg)
1180 {
1181         u32 val = I915_READ(reg);
1182         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1183              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1184              reg, pipe_name(pipe));
1185 }
1186
1187 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1188                                       enum pipe pipe)
1189 {
1190         int reg;
1191         u32 val;
1192
1193         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1194         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1195         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1196
1197         reg = PCH_ADPA;
1198         val = I915_READ(reg);
1199         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1200              "PCH VGA enabled on transcoder %c, should be disabled\n",
1201              pipe_name(pipe));
1202
1203         reg = PCH_LVDS;
1204         val = I915_READ(reg);
1205         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1206              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1207              pipe_name(pipe));
1208
1209         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1210         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1211         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1212 }
1213
1214 /**
1215  * intel_enable_pll - enable a PLL
1216  * @dev_priv: i915 private structure
1217  * @pipe: pipe PLL to enable
1218  *
1219  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1220  * make sure the PLL reg is writable first though, since the panel write
1221  * protect mechanism may be enabled.
1222  *
1223  * Note!  This is for pre-ILK only.
1224  */
1225 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1226 {
1227         int reg;
1228         u32 val;
1229
1230         /* No really, not for ILK+ */
1231         BUG_ON(dev_priv->info->gen >= 5);
1232
1233         /* PLL is protected by panel, make sure we can write it */
1234         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1235                 assert_panel_unlocked(dev_priv, pipe);
1236
1237         reg = DPLL(pipe);
1238         val = I915_READ(reg);
1239         val |= DPLL_VCO_ENABLE;
1240
1241         /* We do this three times for luck */
1242         I915_WRITE(reg, val);
1243         POSTING_READ(reg);
1244         udelay(150); /* wait for warmup */
1245         I915_WRITE(reg, val);
1246         POSTING_READ(reg);
1247         udelay(150); /* wait for warmup */
1248         I915_WRITE(reg, val);
1249         POSTING_READ(reg);
1250         udelay(150); /* wait for warmup */
1251 }
1252
1253 /**
1254  * intel_disable_pll - disable a PLL
1255  * @dev_priv: i915 private structure
1256  * @pipe: pipe PLL to disable
1257  *
1258  * Disable the PLL for @pipe, making sure the pipe is off first.
1259  *
1260  * Note!  This is for pre-ILK only.
1261  */
1262 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1263 {
1264         int reg;
1265         u32 val;
1266
1267         /* Don't disable pipe A or pipe A PLLs if needed */
1268         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1269                 return;
1270
1271         /* Make sure the pipe isn't still relying on us */
1272         assert_pipe_disabled(dev_priv, pipe);
1273
1274         reg = DPLL(pipe);
1275         val = I915_READ(reg);
1276         val &= ~DPLL_VCO_ENABLE;
1277         I915_WRITE(reg, val);
1278         POSTING_READ(reg);
1279 }
1280
1281 /**
1282  * intel_enable_pch_pll - enable PCH PLL
1283  * @dev_priv: i915 private structure
1284  * @pipe: pipe PLL to enable
1285  *
1286  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1287  * drives the transcoder clock.
1288  */
1289 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1290                                  enum pipe pipe)
1291 {
1292         int reg;
1293         u32 val;
1294
1295         if (pipe > 1)
1296                 return;
1297
1298         /* PCH only available on ILK+ */
1299         BUG_ON(dev_priv->info->gen < 5);
1300
1301         /* PCH refclock must be enabled first */
1302         assert_pch_refclk_enabled(dev_priv);
1303
1304         reg = PCH_DPLL(pipe);
1305         val = I915_READ(reg);
1306         val |= DPLL_VCO_ENABLE;
1307         I915_WRITE(reg, val);
1308         POSTING_READ(reg);
1309         udelay(200);
1310 }
1311
1312 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1313                                   enum pipe pipe)
1314 {
1315         int reg;
1316         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1317                 pll_sel = TRANSC_DPLL_ENABLE;
1318
1319         if (pipe > 1)
1320                 return;
1321
1322         /* PCH only available on ILK+ */
1323         BUG_ON(dev_priv->info->gen < 5);
1324
1325         /* Make sure transcoder isn't still depending on us */
1326         assert_transcoder_disabled(dev_priv, pipe);
1327
1328         if (pipe == 0)
1329                 pll_sel |= TRANSC_DPLLA_SEL;
1330         else if (pipe == 1)
1331                 pll_sel |= TRANSC_DPLLB_SEL;
1332
1333
1334         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1335                 return;
1336
1337         reg = PCH_DPLL(pipe);
1338         val = I915_READ(reg);
1339         val &= ~DPLL_VCO_ENABLE;
1340         I915_WRITE(reg, val);
1341         POSTING_READ(reg);
1342         udelay(200);
1343 }
1344
1345 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1346                                     enum pipe pipe)
1347 {
1348         int reg;
1349         u32 val, pipeconf_val;
1350         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1351
1352         /* PCH only available on ILK+ */
1353         BUG_ON(dev_priv->info->gen < 5);
1354
1355         /* Make sure PCH DPLL is enabled */
1356         assert_pch_pll_enabled(dev_priv, pipe);
1357
1358         /* FDI must be feeding us bits for PCH ports */
1359         assert_fdi_tx_enabled(dev_priv, pipe);
1360         assert_fdi_rx_enabled(dev_priv, pipe);
1361
1362         reg = TRANSCONF(pipe);
1363         val = I915_READ(reg);
1364         pipeconf_val = I915_READ(PIPECONF(pipe));
1365
1366         if (HAS_PCH_IBX(dev_priv->dev)) {
1367                 /*
1368                  * make the BPC in transcoder be consistent with
1369                  * that in pipeconf reg.
1370                  */
1371                 val &= ~PIPE_BPC_MASK;
1372                 val |= pipeconf_val & PIPE_BPC_MASK;
1373         }
1374
1375         val &= ~TRANS_INTERLACE_MASK;
1376         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1377                 if (HAS_PCH_IBX(dev_priv->dev) &&
1378                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1379                         val |= TRANS_LEGACY_INTERLACED_ILK;
1380                 else
1381                         val |= TRANS_INTERLACED;
1382         else
1383                 val |= TRANS_PROGRESSIVE;
1384
1385         I915_WRITE(reg, val | TRANS_ENABLE);
1386         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1387                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1388 }
1389
1390 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1391                                      enum pipe pipe)
1392 {
1393         int reg;
1394         u32 val;
1395
1396         /* FDI relies on the transcoder */
1397         assert_fdi_tx_disabled(dev_priv, pipe);
1398         assert_fdi_rx_disabled(dev_priv, pipe);
1399
1400         /* Ports must be off as well */
1401         assert_pch_ports_disabled(dev_priv, pipe);
1402
1403         reg = TRANSCONF(pipe);
1404         val = I915_READ(reg);
1405         val &= ~TRANS_ENABLE;
1406         I915_WRITE(reg, val);
1407         /* wait for PCH transcoder off, transcoder state */
1408         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1409                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1410 }
1411
1412 /**
1413  * intel_enable_pipe - enable a pipe, asserting requirements
1414  * @dev_priv: i915 private structure
1415  * @pipe: pipe to enable
1416  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1417  *
1418  * Enable @pipe, making sure that various hardware specific requirements
1419  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1420  *
1421  * @pipe should be %PIPE_A or %PIPE_B.
1422  *
1423  * Will wait until the pipe is actually running (i.e. first vblank) before
1424  * returning.
1425  */
1426 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1427                               bool pch_port)
1428 {
1429         int reg;
1430         u32 val;
1431
1432         /*
1433          * A pipe without a PLL won't actually be able to drive bits from
1434          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1435          * need the check.
1436          */
1437         if (!HAS_PCH_SPLIT(dev_priv->dev))
1438                 assert_pll_enabled(dev_priv, pipe);
1439         else {
1440                 if (pch_port) {
1441                         /* if driving the PCH, we need FDI enabled */
1442                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1443                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1444                 }
1445                 /* FIXME: assert CPU port conditions for SNB+ */
1446         }
1447
1448         reg = PIPECONF(pipe);
1449         val = I915_READ(reg);
1450         if (val & PIPECONF_ENABLE)
1451                 return;
1452
1453         I915_WRITE(reg, val | PIPECONF_ENABLE);
1454         intel_wait_for_vblank(dev_priv->dev, pipe);
1455 }
1456
1457 /**
1458  * intel_disable_pipe - disable a pipe, asserting requirements
1459  * @dev_priv: i915 private structure
1460  * @pipe: pipe to disable
1461  *
1462  * Disable @pipe, making sure that various hardware specific requirements
1463  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1464  *
1465  * @pipe should be %PIPE_A or %PIPE_B.
1466  *
1467  * Will wait until the pipe has shut down before returning.
1468  */
1469 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1470                                enum pipe pipe)
1471 {
1472         int reg;
1473         u32 val;
1474
1475         /*
1476          * Make sure planes won't keep trying to pump pixels to us,
1477          * or we might hang the display.
1478          */
1479         assert_planes_disabled(dev_priv, pipe);
1480
1481         /* Don't disable pipe A or pipe A PLLs if needed */
1482         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1483                 return;
1484
1485         reg = PIPECONF(pipe);
1486         val = I915_READ(reg);
1487         if ((val & PIPECONF_ENABLE) == 0)
1488                 return;
1489
1490         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1491         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1492 }
1493
1494 /*
1495  * Plane regs are double buffered, going from enabled->disabled needs a
1496  * trigger in order to latch.  The display address reg provides this.
1497  */
1498 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1499                                       enum plane plane)
1500 {
1501         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1502         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1503 }
1504
1505 /**
1506  * intel_enable_plane - enable a display plane on a given pipe
1507  * @dev_priv: i915 private structure
1508  * @plane: plane to enable
1509  * @pipe: pipe being fed
1510  *
1511  * Enable @plane on @pipe, making sure that @pipe is running first.
1512  */
1513 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1514                                enum plane plane, enum pipe pipe)
1515 {
1516         int reg;
1517         u32 val;
1518
1519         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1520         assert_pipe_enabled(dev_priv, pipe);
1521
1522         reg = DSPCNTR(plane);
1523         val = I915_READ(reg);
1524         if (val & DISPLAY_PLANE_ENABLE)
1525                 return;
1526
1527         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1528         intel_flush_display_plane(dev_priv, plane);
1529         intel_wait_for_vblank(dev_priv->dev, pipe);
1530 }
1531
1532 /**
1533  * intel_disable_plane - disable a display plane
1534  * @dev_priv: i915 private structure
1535  * @plane: plane to disable
1536  * @pipe: pipe consuming the data
1537  *
1538  * Disable @plane; should be an independent operation.
1539  */
1540 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1541                                 enum plane plane, enum pipe pipe)
1542 {
1543         int reg;
1544         u32 val;
1545
1546         reg = DSPCNTR(plane);
1547         val = I915_READ(reg);
1548         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1549                 return;
1550
1551         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1552         intel_flush_display_plane(dev_priv, plane);
1553         intel_wait_for_vblank(dev_priv->dev, pipe);
1554 }
1555
1556 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1557                            enum pipe pipe, int reg, u32 port_sel)
1558 {
1559         u32 val = I915_READ(reg);
1560         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1561                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1562                 I915_WRITE(reg, val & ~DP_PORT_EN);
1563         }
1564 }
1565
1566 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1567                              enum pipe pipe, int reg)
1568 {
1569         u32 val = I915_READ(reg);
1570         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1571                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1572                               reg, pipe);
1573                 I915_WRITE(reg, val & ~PORT_ENABLE);
1574         }
1575 }
1576
1577 /* Disable any ports connected to this transcoder */
1578 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1579                                     enum pipe pipe)
1580 {
1581         u32 reg, val;
1582
1583         val = I915_READ(PCH_PP_CONTROL);
1584         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1585
1586         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1587         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1588         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1589
1590         reg = PCH_ADPA;
1591         val = I915_READ(reg);
1592         if (adpa_pipe_enabled(dev_priv, val, pipe))
1593                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1594
1595         reg = PCH_LVDS;
1596         val = I915_READ(reg);
1597         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1598                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1599                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1600                 POSTING_READ(reg);
1601                 udelay(100);
1602         }
1603
1604         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1605         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1606         disable_pch_hdmi(dev_priv, pipe, HDMID);
1607 }
1608
1609 static void i8xx_disable_fbc(struct drm_device *dev)
1610 {
1611         struct drm_i915_private *dev_priv = dev->dev_private;
1612         u32 fbc_ctl;
1613
1614         /* Disable compression */
1615         fbc_ctl = I915_READ(FBC_CONTROL);
1616         if ((fbc_ctl & FBC_CTL_EN) == 0)
1617                 return;
1618
1619         fbc_ctl &= ~FBC_CTL_EN;
1620         I915_WRITE(FBC_CONTROL, fbc_ctl);
1621
1622         /* Wait for compressing bit to clear */
1623         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1624                 DRM_DEBUG_KMS("FBC idle timed out\n");
1625                 return;
1626         }
1627
1628         DRM_DEBUG_KMS("disabled FBC\n");
1629 }
1630
1631 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1632 {
1633         struct drm_device *dev = crtc->dev;
1634         struct drm_i915_private *dev_priv = dev->dev_private;
1635         struct drm_framebuffer *fb = crtc->fb;
1636         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1637         struct drm_i915_gem_object *obj = intel_fb->obj;
1638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1639         int cfb_pitch;
1640         int plane, i;
1641         u32 fbc_ctl, fbc_ctl2;
1642
1643         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1644         if (fb->pitches[0] < cfb_pitch)
1645                 cfb_pitch = fb->pitches[0];
1646
1647         /* FBC_CTL wants 64B units */
1648         cfb_pitch = (cfb_pitch / 64) - 1;
1649         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1650
1651         /* Clear old tags */
1652         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1653                 I915_WRITE(FBC_TAG + (i * 4), 0);
1654
1655         /* Set it up... */
1656         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1657         fbc_ctl2 |= plane;
1658         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1659         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1660
1661         /* enable it... */
1662         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1663         if (IS_I945GM(dev))
1664                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1665         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1666         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1667         fbc_ctl |= obj->fence_reg;
1668         I915_WRITE(FBC_CONTROL, fbc_ctl);
1669
1670         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1671                       cfb_pitch, crtc->y, intel_crtc->plane);
1672 }
1673
1674 static bool i8xx_fbc_enabled(struct drm_device *dev)
1675 {
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677
1678         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1679 }
1680
1681 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1682 {
1683         struct drm_device *dev = crtc->dev;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         struct drm_framebuffer *fb = crtc->fb;
1686         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1687         struct drm_i915_gem_object *obj = intel_fb->obj;
1688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1689         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1690         unsigned long stall_watermark = 200;
1691         u32 dpfc_ctl;
1692
1693         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1694         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1695         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1696
1697         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1698                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1699                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1700         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1701
1702         /* enable it... */
1703         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1704
1705         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706 }
1707
1708 static void g4x_disable_fbc(struct drm_device *dev)
1709 {
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         u32 dpfc_ctl;
1712
1713         /* Disable compression */
1714         dpfc_ctl = I915_READ(DPFC_CONTROL);
1715         if (dpfc_ctl & DPFC_CTL_EN) {
1716                 dpfc_ctl &= ~DPFC_CTL_EN;
1717                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1718
1719                 DRM_DEBUG_KMS("disabled FBC\n");
1720         }
1721 }
1722
1723 static bool g4x_fbc_enabled(struct drm_device *dev)
1724 {
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1728 }
1729
1730 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         u32 blt_ecoskpd;
1734
1735         /* Make sure blitter notifies FBC of writes */
1736         gen6_gt_force_wake_get(dev_priv);
1737         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1738         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1739                 GEN6_BLITTER_LOCK_SHIFT;
1740         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1741         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1742         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1743         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1744                          GEN6_BLITTER_LOCK_SHIFT);
1745         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1746         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1747         gen6_gt_force_wake_put(dev_priv);
1748 }
1749
1750 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1751 {
1752         struct drm_device *dev = crtc->dev;
1753         struct drm_i915_private *dev_priv = dev->dev_private;
1754         struct drm_framebuffer *fb = crtc->fb;
1755         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1756         struct drm_i915_gem_object *obj = intel_fb->obj;
1757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1758         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1759         unsigned long stall_watermark = 200;
1760         u32 dpfc_ctl;
1761
1762         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1763         dpfc_ctl &= DPFC_RESERVED;
1764         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1765         /* Set persistent mode for front-buffer rendering, ala X. */
1766         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1767         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1768         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1769
1770         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1771                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1772                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1773         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1774         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1775         /* enable it... */
1776         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1777
1778         if (IS_GEN6(dev)) {
1779                 I915_WRITE(SNB_DPFC_CTL_SA,
1780                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1781                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1782                 sandybridge_blit_fbc_update(dev);
1783         }
1784
1785         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1786 }
1787
1788 static void ironlake_disable_fbc(struct drm_device *dev)
1789 {
1790         struct drm_i915_private *dev_priv = dev->dev_private;
1791         u32 dpfc_ctl;
1792
1793         /* Disable compression */
1794         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1795         if (dpfc_ctl & DPFC_CTL_EN) {
1796                 dpfc_ctl &= ~DPFC_CTL_EN;
1797                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1798
1799                 DRM_DEBUG_KMS("disabled FBC\n");
1800         }
1801 }
1802
1803 static bool ironlake_fbc_enabled(struct drm_device *dev)
1804 {
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806
1807         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1808 }
1809
1810 bool intel_fbc_enabled(struct drm_device *dev)
1811 {
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813
1814         if (!dev_priv->display.fbc_enabled)
1815                 return false;
1816
1817         return dev_priv->display.fbc_enabled(dev);
1818 }
1819
1820 static void intel_fbc_work_fn(struct work_struct *__work)
1821 {
1822         struct intel_fbc_work *work =
1823                 container_of(to_delayed_work(__work),
1824                              struct intel_fbc_work, work);
1825         struct drm_device *dev = work->crtc->dev;
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827
1828         mutex_lock(&dev->struct_mutex);
1829         if (work == dev_priv->fbc_work) {
1830                 /* Double check that we haven't switched fb without cancelling
1831                  * the prior work.
1832                  */
1833                 if (work->crtc->fb == work->fb) {
1834                         dev_priv->display.enable_fbc(work->crtc,
1835                                                      work->interval);
1836
1837                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1838                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1839                         dev_priv->cfb_y = work->crtc->y;
1840                 }
1841
1842                 dev_priv->fbc_work = NULL;
1843         }
1844         mutex_unlock(&dev->struct_mutex);
1845
1846         kfree(work);
1847 }
1848
1849 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1850 {
1851         if (dev_priv->fbc_work == NULL)
1852                 return;
1853
1854         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1855
1856         /* Synchronisation is provided by struct_mutex and checking of
1857          * dev_priv->fbc_work, so we can perform the cancellation
1858          * entirely asynchronously.
1859          */
1860         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1861                 /* tasklet was killed before being run, clean up */
1862                 kfree(dev_priv->fbc_work);
1863
1864         /* Mark the work as no longer wanted so that if it does
1865          * wake-up (because the work was already running and waiting
1866          * for our mutex), it will discover that is no longer
1867          * necessary to run.
1868          */
1869         dev_priv->fbc_work = NULL;
1870 }
1871
1872 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1873 {
1874         struct intel_fbc_work *work;
1875         struct drm_device *dev = crtc->dev;
1876         struct drm_i915_private *dev_priv = dev->dev_private;
1877
1878         if (!dev_priv->display.enable_fbc)
1879                 return;
1880
1881         intel_cancel_fbc_work(dev_priv);
1882
1883         work = kzalloc(sizeof *work, GFP_KERNEL);
1884         if (work == NULL) {
1885                 dev_priv->display.enable_fbc(crtc, interval);
1886                 return;
1887         }
1888
1889         work->crtc = crtc;
1890         work->fb = crtc->fb;
1891         work->interval = interval;
1892         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1893
1894         dev_priv->fbc_work = work;
1895
1896         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1897
1898         /* Delay the actual enabling to let pageflipping cease and the
1899          * display to settle before starting the compression. Note that
1900          * this delay also serves a second purpose: it allows for a
1901          * vblank to pass after disabling the FBC before we attempt
1902          * to modify the control registers.
1903          *
1904          * A more complicated solution would involve tracking vblanks
1905          * following the termination of the page-flipping sequence
1906          * and indeed performing the enable as a co-routine and not
1907          * waiting synchronously upon the vblank.
1908          */
1909         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1910 }
1911
1912 void intel_disable_fbc(struct drm_device *dev)
1913 {
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915
1916         intel_cancel_fbc_work(dev_priv);
1917
1918         if (!dev_priv->display.disable_fbc)
1919                 return;
1920
1921         dev_priv->display.disable_fbc(dev);
1922         dev_priv->cfb_plane = -1;
1923 }
1924
1925 /**
1926  * intel_update_fbc - enable/disable FBC as needed
1927  * @dev: the drm_device
1928  *
1929  * Set up the framebuffer compression hardware at mode set time.  We
1930  * enable it if possible:
1931  *   - plane A only (on pre-965)
1932  *   - no pixel mulitply/line duplication
1933  *   - no alpha buffer discard
1934  *   - no dual wide
1935  *   - framebuffer <= 2048 in width, 1536 in height
1936  *
1937  * We can't assume that any compression will take place (worst case),
1938  * so the compressed buffer has to be the same size as the uncompressed
1939  * one.  It also must reside (along with the line length buffer) in
1940  * stolen memory.
1941  *
1942  * We need to enable/disable FBC on a global basis.
1943  */
1944 static void intel_update_fbc(struct drm_device *dev)
1945 {
1946         struct drm_i915_private *dev_priv = dev->dev_private;
1947         struct drm_crtc *crtc = NULL, *tmp_crtc;
1948         struct intel_crtc *intel_crtc;
1949         struct drm_framebuffer *fb;
1950         struct intel_framebuffer *intel_fb;
1951         struct drm_i915_gem_object *obj;
1952         int enable_fbc;
1953
1954         DRM_DEBUG_KMS("\n");
1955
1956         if (!i915_powersave)
1957                 return;
1958
1959         if (!I915_HAS_FBC(dev))
1960                 return;
1961
1962         /*
1963          * If FBC is already on, we just have to verify that we can
1964          * keep it that way...
1965          * Need to disable if:
1966          *   - more than one pipe is active
1967          *   - changing FBC params (stride, fence, mode)
1968          *   - new fb is too large to fit in compressed buffer
1969          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1970          */
1971         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1972                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1973                         if (crtc) {
1974                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1975                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1976                                 goto out_disable;
1977                         }
1978                         crtc = tmp_crtc;
1979                 }
1980         }
1981
1982         if (!crtc || crtc->fb == NULL) {
1983                 DRM_DEBUG_KMS("no output, disabling\n");
1984                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1985                 goto out_disable;
1986         }
1987
1988         intel_crtc = to_intel_crtc(crtc);
1989         fb = crtc->fb;
1990         intel_fb = to_intel_framebuffer(fb);
1991         obj = intel_fb->obj;
1992
1993         enable_fbc = i915_enable_fbc;
1994         if (enable_fbc < 0) {
1995                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1996                 enable_fbc = 1;
1997                 if (INTEL_INFO(dev)->gen <= 6)
1998                         enable_fbc = 0;
1999         }
2000         if (!enable_fbc) {
2001                 DRM_DEBUG_KMS("fbc disabled per module param\n");
2002                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
2003                 goto out_disable;
2004         }
2005         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2006                 DRM_DEBUG_KMS("framebuffer too large, disabling "
2007                               "compression\n");
2008                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2009                 goto out_disable;
2010         }
2011         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2012             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2013                 DRM_DEBUG_KMS("mode incompatible with compression, "
2014                               "disabling\n");
2015                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2016                 goto out_disable;
2017         }
2018         if ((crtc->mode.hdisplay > 2048) ||
2019             (crtc->mode.vdisplay > 1536)) {
2020                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2021                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2022                 goto out_disable;
2023         }
2024         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
2025                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2026                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2027                 goto out_disable;
2028         }
2029
2030         /* The use of a CPU fence is mandatory in order to detect writes
2031          * by the CPU to the scanout and trigger updates to the FBC.
2032          */
2033         if (obj->tiling_mode != I915_TILING_X ||
2034             obj->fence_reg == I915_FENCE_REG_NONE) {
2035                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
2036                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
2037                 goto out_disable;
2038         }
2039
2040         /* If the kernel debugger is active, always disable compression */
2041         if (in_dbg_master())
2042                 goto out_disable;
2043
2044         /* If the scanout has not changed, don't modify the FBC settings.
2045          * Note that we make the fundamental assumption that the fb->obj
2046          * cannot be unpinned (and have its GTT offset and fence revoked)
2047          * without first being decoupled from the scanout and FBC disabled.
2048          */
2049         if (dev_priv->cfb_plane == intel_crtc->plane &&
2050             dev_priv->cfb_fb == fb->base.id &&
2051             dev_priv->cfb_y == crtc->y)
2052                 return;
2053
2054         if (intel_fbc_enabled(dev)) {
2055                 /* We update FBC along two paths, after changing fb/crtc
2056                  * configuration (modeswitching) and after page-flipping
2057                  * finishes. For the latter, we know that not only did
2058                  * we disable the FBC at the start of the page-flip
2059                  * sequence, but also more than one vblank has passed.
2060                  *
2061                  * For the former case of modeswitching, it is possible
2062                  * to switch between two FBC valid configurations
2063                  * instantaneously so we do need to disable the FBC
2064                  * before we can modify its control registers. We also
2065                  * have to wait for the next vblank for that to take
2066                  * effect. However, since we delay enabling FBC we can
2067                  * assume that a vblank has passed since disabling and
2068                  * that we can safely alter the registers in the deferred
2069                  * callback.
2070                  *
2071                  * In the scenario that we go from a valid to invalid
2072                  * and then back to valid FBC configuration we have
2073                  * no strict enforcement that a vblank occurred since
2074                  * disabling the FBC. However, along all current pipe
2075                  * disabling paths we do need to wait for a vblank at
2076                  * some point. And we wait before enabling FBC anyway.
2077                  */
2078                 DRM_DEBUG_KMS("disabling active FBC for update\n");
2079                 intel_disable_fbc(dev);
2080         }
2081
2082         intel_enable_fbc(crtc, 500);
2083         return;
2084
2085 out_disable:
2086         /* Multiple disables should be harmless */
2087         if (intel_fbc_enabled(dev)) {
2088                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2089                 intel_disable_fbc(dev);
2090         }
2091 }
2092
2093 int
2094 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2095                            struct drm_i915_gem_object *obj,
2096                            struct intel_ring_buffer *pipelined)
2097 {
2098         struct drm_i915_private *dev_priv = dev->dev_private;
2099         u32 alignment;
2100         int ret;
2101
2102         switch (obj->tiling_mode) {
2103         case I915_TILING_NONE:
2104                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2105                         alignment = 128 * 1024;
2106                 else if (INTEL_INFO(dev)->gen >= 4)
2107                         alignment = 4 * 1024;
2108                 else
2109                         alignment = 64 * 1024;
2110                 break;
2111         case I915_TILING_X:
2112                 /* pin() will align the object as required by fence */
2113                 alignment = 0;
2114                 break;
2115         case I915_TILING_Y:
2116                 /* FIXME: Is this true? */
2117                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2118                 return -EINVAL;
2119         default:
2120                 BUG();
2121         }
2122
2123         dev_priv->mm.interruptible = false;
2124         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2125         if (ret)
2126                 goto err_interruptible;
2127
2128         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2129          * fence, whereas 965+ only requires a fence if using
2130          * framebuffer compression.  For simplicity, we always install
2131          * a fence as the cost is not that onerous.
2132          */
2133         if (obj->tiling_mode != I915_TILING_NONE) {
2134                 ret = i915_gem_object_get_fence(obj, pipelined);
2135                 if (ret)
2136                         goto err_unpin;
2137
2138                 i915_gem_object_pin_fence(obj);
2139         }
2140
2141         dev_priv->mm.interruptible = true;
2142         return 0;
2143
2144 err_unpin:
2145         i915_gem_object_unpin(obj);
2146 err_interruptible:
2147         dev_priv->mm.interruptible = true;
2148         return ret;
2149 }
2150
2151 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2152 {
2153         i915_gem_object_unpin_fence(obj);
2154         i915_gem_object_unpin(obj);
2155 }
2156
2157 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2158                              int x, int y)
2159 {
2160         struct drm_device *dev = crtc->dev;
2161         struct drm_i915_private *dev_priv = dev->dev_private;
2162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2163         struct intel_framebuffer *intel_fb;
2164         struct drm_i915_gem_object *obj;
2165         int plane = intel_crtc->plane;
2166         unsigned long Start, Offset;
2167         u32 dspcntr;
2168         u32 reg;
2169
2170         switch (plane) {
2171         case 0:
2172         case 1:
2173                 break;
2174         default:
2175                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2176                 return -EINVAL;
2177         }
2178
2179         intel_fb = to_intel_framebuffer(fb);
2180         obj = intel_fb->obj;
2181
2182         reg = DSPCNTR(plane);
2183         dspcntr = I915_READ(reg);
2184         /* Mask out pixel format bits in case we change it */
2185         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2186         switch (fb->bits_per_pixel) {
2187         case 8:
2188                 dspcntr |= DISPPLANE_8BPP;
2189                 break;
2190         case 16:
2191                 if (fb->depth == 15)
2192                         dspcntr |= DISPPLANE_15_16BPP;
2193                 else
2194                         dspcntr |= DISPPLANE_16BPP;
2195                 break;
2196         case 24:
2197         case 32:
2198                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2199                 break;
2200         default:
2201                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2202                 return -EINVAL;
2203         }
2204         if (INTEL_INFO(dev)->gen >= 4) {
2205                 if (obj->tiling_mode != I915_TILING_NONE)
2206                         dspcntr |= DISPPLANE_TILED;
2207                 else
2208                         dspcntr &= ~DISPPLANE_TILED;
2209         }
2210
2211         I915_WRITE(reg, dspcntr);
2212
2213         Start = obj->gtt_offset;
2214         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2215
2216         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2217                       Start, Offset, x, y, fb->pitches[0]);
2218         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2219         if (INTEL_INFO(dev)->gen >= 4) {
2220                 I915_WRITE(DSPSURF(plane), Start);
2221                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222                 I915_WRITE(DSPADDR(plane), Offset);
2223         } else
2224                 I915_WRITE(DSPADDR(plane), Start + Offset);
2225         POSTING_READ(reg);
2226
2227         return 0;
2228 }
2229
2230 static int ironlake_update_plane(struct drm_crtc *crtc,
2231                                  struct drm_framebuffer *fb, int x, int y)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236         struct intel_framebuffer *intel_fb;
2237         struct drm_i915_gem_object *obj;
2238         int plane = intel_crtc->plane;
2239         unsigned long Start, Offset;
2240         u32 dspcntr;
2241         u32 reg;
2242
2243         switch (plane) {
2244         case 0:
2245         case 1:
2246         case 2:
2247                 break;
2248         default:
2249                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2250                 return -EINVAL;
2251         }
2252
2253         intel_fb = to_intel_framebuffer(fb);
2254         obj = intel_fb->obj;
2255
2256         reg = DSPCNTR(plane);
2257         dspcntr = I915_READ(reg);
2258         /* Mask out pixel format bits in case we change it */
2259         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2260         switch (fb->bits_per_pixel) {
2261         case 8:
2262                 dspcntr |= DISPPLANE_8BPP;
2263                 break;
2264         case 16:
2265                 if (fb->depth != 16)
2266                         return -EINVAL;
2267
2268                 dspcntr |= DISPPLANE_16BPP;
2269                 break;
2270         case 24:
2271         case 32:
2272                 if (fb->depth == 24)
2273                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2274                 else if (fb->depth == 30)
2275                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2276                 else
2277                         return -EINVAL;
2278                 break;
2279         default:
2280                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2281                 return -EINVAL;
2282         }
2283
2284         if (obj->tiling_mode != I915_TILING_NONE)
2285                 dspcntr |= DISPPLANE_TILED;
2286         else
2287                 dspcntr &= ~DISPPLANE_TILED;
2288
2289         /* must disable */
2290         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2291
2292         I915_WRITE(reg, dspcntr);
2293
2294         Start = obj->gtt_offset;
2295         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2296
2297         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2298                       Start, Offset, x, y, fb->pitches[0]);
2299         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2300         I915_WRITE(DSPSURF(plane), Start);
2301         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2302         I915_WRITE(DSPADDR(plane), Offset);
2303         POSTING_READ(reg);
2304
2305         return 0;
2306 }
2307
2308 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2309 static int
2310 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2311                            int x, int y, enum mode_set_atomic state)
2312 {
2313         struct drm_device *dev = crtc->dev;
2314         struct drm_i915_private *dev_priv = dev->dev_private;
2315         int ret;
2316
2317         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2318         if (ret)
2319                 return ret;
2320
2321         intel_update_fbc(dev);
2322         intel_increase_pllclock(crtc);
2323
2324         return 0;
2325 }
2326
2327 static int
2328 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2329                     struct drm_framebuffer *old_fb)
2330 {
2331         struct drm_device *dev = crtc->dev;
2332         struct drm_i915_master_private *master_priv;
2333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2334         int ret;
2335
2336         /* no fb bound */
2337         if (!crtc->fb) {
2338                 DRM_ERROR("No FB bound\n");
2339                 return 0;
2340         }
2341
2342         switch (intel_crtc->plane) {
2343         case 0:
2344         case 1:
2345                 break;
2346         case 2:
2347                 if (IS_IVYBRIDGE(dev))
2348                         break;
2349                 /* fall through otherwise */
2350         default:
2351                 DRM_ERROR("no plane for crtc\n");
2352                 return -EINVAL;
2353         }
2354
2355         mutex_lock(&dev->struct_mutex);
2356         ret = intel_pin_and_fence_fb_obj(dev,
2357                                          to_intel_framebuffer(crtc->fb)->obj,
2358                                          NULL);
2359         if (ret != 0) {
2360                 mutex_unlock(&dev->struct_mutex);
2361                 DRM_ERROR("pin & fence failed\n");
2362                 return ret;
2363         }
2364
2365         if (old_fb) {
2366                 struct drm_i915_private *dev_priv = dev->dev_private;
2367                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2368
2369                 wait_event(dev_priv->pending_flip_queue,
2370                            atomic_read(&dev_priv->mm.wedged) ||
2371                            atomic_read(&obj->pending_flip) == 0);
2372
2373                 /* Big Hammer, we also need to ensure that any pending
2374                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2375                  * current scanout is retired before unpinning the old
2376                  * framebuffer.
2377                  *
2378                  * This should only fail upon a hung GPU, in which case we
2379                  * can safely continue.
2380                  */
2381                 ret = i915_gem_object_finish_gpu(obj);
2382                 (void) ret;
2383         }
2384
2385         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2386                                          LEAVE_ATOMIC_MODE_SET);
2387         if (ret) {
2388                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2389                 mutex_unlock(&dev->struct_mutex);
2390                 DRM_ERROR("failed to update base address\n");
2391                 return ret;
2392         }
2393
2394         if (old_fb) {
2395                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2396                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2397         }
2398
2399         mutex_unlock(&dev->struct_mutex);
2400
2401         if (!dev->primary->master)
2402                 return 0;
2403
2404         master_priv = dev->primary->master->driver_priv;
2405         if (!master_priv->sarea_priv)
2406                 return 0;
2407
2408         if (intel_crtc->pipe) {
2409                 master_priv->sarea_priv->pipeB_x = x;
2410                 master_priv->sarea_priv->pipeB_y = y;
2411         } else {
2412                 master_priv->sarea_priv->pipeA_x = x;
2413                 master_priv->sarea_priv->pipeA_y = y;
2414         }
2415
2416         return 0;
2417 }
2418
2419 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2420 {
2421         struct drm_device *dev = crtc->dev;
2422         struct drm_i915_private *dev_priv = dev->dev_private;
2423         u32 dpa_ctl;
2424
2425         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2426         dpa_ctl = I915_READ(DP_A);
2427         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2428
2429         if (clock < 200000) {
2430                 u32 temp;
2431                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2432                 /* workaround for 160Mhz:
2433                    1) program 0x4600c bits 15:0 = 0x8124
2434                    2) program 0x46010 bit 0 = 1
2435                    3) program 0x46034 bit 24 = 1
2436                    4) program 0x64000 bit 14 = 1
2437                    */
2438                 temp = I915_READ(0x4600c);
2439                 temp &= 0xffff0000;
2440                 I915_WRITE(0x4600c, temp | 0x8124);
2441
2442                 temp = I915_READ(0x46010);
2443                 I915_WRITE(0x46010, temp | 1);
2444
2445                 temp = I915_READ(0x46034);
2446                 I915_WRITE(0x46034, temp | (1 << 24));
2447         } else {
2448                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2449         }
2450         I915_WRITE(DP_A, dpa_ctl);
2451
2452         POSTING_READ(DP_A);
2453         udelay(500);
2454 }
2455
2456 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2457 {
2458         struct drm_device *dev = crtc->dev;
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461         int pipe = intel_crtc->pipe;
2462         u32 reg, temp;
2463
2464         /* enable normal train */
2465         reg = FDI_TX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         if (IS_IVYBRIDGE(dev)) {
2468                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2469                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2470         } else {
2471                 temp &= ~FDI_LINK_TRAIN_NONE;
2472                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2473         }
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         if (HAS_PCH_CPT(dev)) {
2479                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2480                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2481         } else {
2482                 temp &= ~FDI_LINK_TRAIN_NONE;
2483                 temp |= FDI_LINK_TRAIN_NONE;
2484         }
2485         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2486
2487         /* wait one idle pattern time */
2488         POSTING_READ(reg);
2489         udelay(1000);
2490
2491         /* IVB wants error correction enabled */
2492         if (IS_IVYBRIDGE(dev))
2493                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2494                            FDI_FE_ERRC_ENABLE);
2495 }
2496
2497 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2498 {
2499         struct drm_i915_private *dev_priv = dev->dev_private;
2500         u32 flags = I915_READ(SOUTH_CHICKEN1);
2501
2502         flags |= FDI_PHASE_SYNC_OVR(pipe);
2503         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2504         flags |= FDI_PHASE_SYNC_EN(pipe);
2505         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2506         POSTING_READ(SOUTH_CHICKEN1);
2507 }
2508
2509 /* The FDI link training functions for ILK/Ibexpeak. */
2510 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2511 {
2512         struct drm_device *dev = crtc->dev;
2513         struct drm_i915_private *dev_priv = dev->dev_private;
2514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2515         int pipe = intel_crtc->pipe;
2516         int plane = intel_crtc->plane;
2517         u32 reg, temp, tries;
2518
2519         /* FDI needs bits from pipe & plane first */
2520         assert_pipe_enabled(dev_priv, pipe);
2521         assert_plane_enabled(dev_priv, plane);
2522
2523         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2524            for train result */
2525         reg = FDI_RX_IMR(pipe);
2526         temp = I915_READ(reg);
2527         temp &= ~FDI_RX_SYMBOL_LOCK;
2528         temp &= ~FDI_RX_BIT_LOCK;
2529         I915_WRITE(reg, temp);
2530         I915_READ(reg);
2531         udelay(150);
2532
2533         /* enable CPU FDI TX and PCH FDI RX */
2534         reg = FDI_TX_CTL(pipe);
2535         temp = I915_READ(reg);
2536         temp &= ~(7 << 19);
2537         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2538         temp &= ~FDI_LINK_TRAIN_NONE;
2539         temp |= FDI_LINK_TRAIN_PATTERN_1;
2540         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2541
2542         reg = FDI_RX_CTL(pipe);
2543         temp = I915_READ(reg);
2544         temp &= ~FDI_LINK_TRAIN_NONE;
2545         temp |= FDI_LINK_TRAIN_PATTERN_1;
2546         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2547
2548         POSTING_READ(reg);
2549         udelay(150);
2550
2551         /* Ironlake workaround, enable clock pointer after FDI enable*/
2552         if (HAS_PCH_IBX(dev)) {
2553                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2554                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2555                            FDI_RX_PHASE_SYNC_POINTER_EN);
2556         }
2557
2558         reg = FDI_RX_IIR(pipe);
2559         for (tries = 0; tries < 5; tries++) {
2560                 temp = I915_READ(reg);
2561                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562
2563                 if ((temp & FDI_RX_BIT_LOCK)) {
2564                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2565                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2566                         break;
2567                 }
2568         }
2569         if (tries == 5)
2570                 DRM_ERROR("FDI train 1 fail!\n");
2571
2572         /* Train 2 */
2573         reg = FDI_TX_CTL(pipe);
2574         temp = I915_READ(reg);
2575         temp &= ~FDI_LINK_TRAIN_NONE;
2576         temp |= FDI_LINK_TRAIN_PATTERN_2;
2577         I915_WRITE(reg, temp);
2578
2579         reg = FDI_RX_CTL(pipe);
2580         temp = I915_READ(reg);
2581         temp &= ~FDI_LINK_TRAIN_NONE;
2582         temp |= FDI_LINK_TRAIN_PATTERN_2;
2583         I915_WRITE(reg, temp);
2584
2585         POSTING_READ(reg);
2586         udelay(150);
2587
2588         reg = FDI_RX_IIR(pipe);
2589         for (tries = 0; tries < 5; tries++) {
2590                 temp = I915_READ(reg);
2591                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2592
2593                 if (temp & FDI_RX_SYMBOL_LOCK) {
2594                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2595                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2596                         break;
2597                 }
2598         }
2599         if (tries == 5)
2600                 DRM_ERROR("FDI train 2 fail!\n");
2601
2602         DRM_DEBUG_KMS("FDI train done\n");
2603
2604 }
2605
2606 static const int snb_b_fdi_train_param[] = {
2607         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2608         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2609         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2610         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2611 };
2612
2613 /* The FDI link training functions for SNB/Cougarpoint. */
2614 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2615 {
2616         struct drm_device *dev = crtc->dev;
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2619         int pipe = intel_crtc->pipe;
2620         u32 reg, temp, i, retry;
2621
2622         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2623            for train result */
2624         reg = FDI_RX_IMR(pipe);
2625         temp = I915_READ(reg);
2626         temp &= ~FDI_RX_SYMBOL_LOCK;
2627         temp &= ~FDI_RX_BIT_LOCK;
2628         I915_WRITE(reg, temp);
2629
2630         POSTING_READ(reg);
2631         udelay(150);
2632
2633         /* enable CPU FDI TX and PCH FDI RX */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~(7 << 19);
2637         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2638         temp &= ~FDI_LINK_TRAIN_NONE;
2639         temp |= FDI_LINK_TRAIN_PATTERN_1;
2640         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641         /* SNB-B */
2642         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2644
2645         reg = FDI_RX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         if (HAS_PCH_CPT(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2650         } else {
2651                 temp &= ~FDI_LINK_TRAIN_NONE;
2652                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2653         }
2654         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2655
2656         POSTING_READ(reg);
2657         udelay(150);
2658
2659         if (HAS_PCH_CPT(dev))
2660                 cpt_phase_pointer_enable(dev, pipe);
2661
2662         for (i = 0; i < 4; i++) {
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666                 temp |= snb_b_fdi_train_param[i];
2667                 I915_WRITE(reg, temp);
2668
2669                 POSTING_READ(reg);
2670                 udelay(500);
2671
2672                 for (retry = 0; retry < 5; retry++) {
2673                         reg = FDI_RX_IIR(pipe);
2674                         temp = I915_READ(reg);
2675                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676                         if (temp & FDI_RX_BIT_LOCK) {
2677                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2678                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2679                                 break;
2680                         }
2681                         udelay(50);
2682                 }
2683                 if (retry < 5)
2684                         break;
2685         }
2686         if (i == 4)
2687                 DRM_ERROR("FDI train 1 fail!\n");
2688
2689         /* Train 2 */
2690         reg = FDI_TX_CTL(pipe);
2691         temp = I915_READ(reg);
2692         temp &= ~FDI_LINK_TRAIN_NONE;
2693         temp |= FDI_LINK_TRAIN_PATTERN_2;
2694         if (IS_GEN6(dev)) {
2695                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2696                 /* SNB-B */
2697                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2698         }
2699         I915_WRITE(reg, temp);
2700
2701         reg = FDI_RX_CTL(pipe);
2702         temp = I915_READ(reg);
2703         if (HAS_PCH_CPT(dev)) {
2704                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2705                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2706         } else {
2707                 temp &= ~FDI_LINK_TRAIN_NONE;
2708                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2709         }
2710         I915_WRITE(reg, temp);
2711
2712         POSTING_READ(reg);
2713         udelay(150);
2714
2715         for (i = 0; i < 4; i++) {
2716                 reg = FDI_TX_CTL(pipe);
2717                 temp = I915_READ(reg);
2718                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719                 temp |= snb_b_fdi_train_param[i];
2720                 I915_WRITE(reg, temp);
2721
2722                 POSTING_READ(reg);
2723                 udelay(500);
2724
2725                 for (retry = 0; retry < 5; retry++) {
2726                         reg = FDI_RX_IIR(pipe);
2727                         temp = I915_READ(reg);
2728                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2729                         if (temp & FDI_RX_SYMBOL_LOCK) {
2730                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2731                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2732                                 break;
2733                         }
2734                         udelay(50);
2735                 }
2736                 if (retry < 5)
2737                         break;
2738         }
2739         if (i == 4)
2740                 DRM_ERROR("FDI train 2 fail!\n");
2741
2742         DRM_DEBUG_KMS("FDI train done.\n");
2743 }
2744
2745 /* Manual link training for Ivy Bridge A0 parts */
2746 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2747 {
2748         struct drm_device *dev = crtc->dev;
2749         struct drm_i915_private *dev_priv = dev->dev_private;
2750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2751         int pipe = intel_crtc->pipe;
2752         u32 reg, temp, i;
2753
2754         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2755            for train result */
2756         reg = FDI_RX_IMR(pipe);
2757         temp = I915_READ(reg);
2758         temp &= ~FDI_RX_SYMBOL_LOCK;
2759         temp &= ~FDI_RX_BIT_LOCK;
2760         I915_WRITE(reg, temp);
2761
2762         POSTING_READ(reg);
2763         udelay(150);
2764
2765         /* enable CPU FDI TX and PCH FDI RX */
2766         reg = FDI_TX_CTL(pipe);
2767         temp = I915_READ(reg);
2768         temp &= ~(7 << 19);
2769         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2770         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2771         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2772         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2773         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2774         temp |= FDI_COMPOSITE_SYNC;
2775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2776
2777         reg = FDI_RX_CTL(pipe);
2778         temp = I915_READ(reg);
2779         temp &= ~FDI_LINK_TRAIN_AUTO;
2780         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2782         temp |= FDI_COMPOSITE_SYNC;
2783         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2784
2785         POSTING_READ(reg);
2786         udelay(150);
2787
2788         if (HAS_PCH_CPT(dev))
2789                 cpt_phase_pointer_enable(dev, pipe);
2790
2791         for (i = 0; i < 4; i++) {
2792                 reg = FDI_TX_CTL(pipe);
2793                 temp = I915_READ(reg);
2794                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2795                 temp |= snb_b_fdi_train_param[i];
2796                 I915_WRITE(reg, temp);
2797
2798                 POSTING_READ(reg);
2799                 udelay(500);
2800
2801                 reg = FDI_RX_IIR(pipe);
2802                 temp = I915_READ(reg);
2803                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2804
2805                 if (temp & FDI_RX_BIT_LOCK ||
2806                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2807                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2808                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2809                         break;
2810                 }
2811         }
2812         if (i == 4)
2813                 DRM_ERROR("FDI train 1 fail!\n");
2814
2815         /* Train 2 */
2816         reg = FDI_TX_CTL(pipe);
2817         temp = I915_READ(reg);
2818         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2819         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2820         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2821         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2822         I915_WRITE(reg, temp);
2823
2824         reg = FDI_RX_CTL(pipe);
2825         temp = I915_READ(reg);
2826         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2827         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2828         I915_WRITE(reg, temp);
2829
2830         POSTING_READ(reg);
2831         udelay(150);
2832
2833         for (i = 0; i < 4; i++) {
2834                 reg = FDI_TX_CTL(pipe);
2835                 temp = I915_READ(reg);
2836                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2837                 temp |= snb_b_fdi_train_param[i];
2838                 I915_WRITE(reg, temp);
2839
2840                 POSTING_READ(reg);
2841                 udelay(500);
2842
2843                 reg = FDI_RX_IIR(pipe);
2844                 temp = I915_READ(reg);
2845                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2846
2847                 if (temp & FDI_RX_SYMBOL_LOCK) {
2848                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2849                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2850                         break;
2851                 }
2852         }
2853         if (i == 4)
2854                 DRM_ERROR("FDI train 2 fail!\n");
2855
2856         DRM_DEBUG_KMS("FDI train done.\n");
2857 }
2858
2859 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2860 {
2861         struct drm_device *dev = crtc->dev;
2862         struct drm_i915_private *dev_priv = dev->dev_private;
2863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864         int pipe = intel_crtc->pipe;
2865         u32 reg, temp;
2866
2867         /* Write the TU size bits so error detection works */
2868         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2869                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2870
2871         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2872         reg = FDI_RX_CTL(pipe);
2873         temp = I915_READ(reg);
2874         temp &= ~((0x7 << 19) | (0x7 << 16));
2875         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2876         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2877         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2878
2879         POSTING_READ(reg);
2880         udelay(200);
2881
2882         /* Switch from Rawclk to PCDclk */
2883         temp = I915_READ(reg);
2884         I915_WRITE(reg, temp | FDI_PCDCLK);
2885
2886         POSTING_READ(reg);
2887         udelay(200);
2888
2889         /* Enable CPU FDI TX PLL, always on for Ironlake */
2890         reg = FDI_TX_CTL(pipe);
2891         temp = I915_READ(reg);
2892         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2893                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2894
2895                 POSTING_READ(reg);
2896                 udelay(100);
2897         }
2898 }
2899
2900 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2901 {
2902         struct drm_i915_private *dev_priv = dev->dev_private;
2903         u32 flags = I915_READ(SOUTH_CHICKEN1);
2904
2905         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2906         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2907         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2908         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2909         POSTING_READ(SOUTH_CHICKEN1);
2910 }
2911 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2912 {
2913         struct drm_device *dev = crtc->dev;
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2916         int pipe = intel_crtc->pipe;
2917         u32 reg, temp;
2918
2919         /* disable CPU FDI tx and PCH FDI rx */
2920         reg = FDI_TX_CTL(pipe);
2921         temp = I915_READ(reg);
2922         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2923         POSTING_READ(reg);
2924
2925         reg = FDI_RX_CTL(pipe);
2926         temp = I915_READ(reg);
2927         temp &= ~(0x7 << 16);
2928         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2929         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2930
2931         POSTING_READ(reg);
2932         udelay(100);
2933
2934         /* Ironlake workaround, disable clock pointer after downing FDI */
2935         if (HAS_PCH_IBX(dev)) {
2936                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2937                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2938                            I915_READ(FDI_RX_CHICKEN(pipe) &
2939                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2940         } else if (HAS_PCH_CPT(dev)) {
2941                 cpt_phase_pointer_disable(dev, pipe);
2942         }
2943
2944         /* still set train pattern 1 */
2945         reg = FDI_TX_CTL(pipe);
2946         temp = I915_READ(reg);
2947         temp &= ~FDI_LINK_TRAIN_NONE;
2948         temp |= FDI_LINK_TRAIN_PATTERN_1;
2949         I915_WRITE(reg, temp);
2950
2951         reg = FDI_RX_CTL(pipe);
2952         temp = I915_READ(reg);
2953         if (HAS_PCH_CPT(dev)) {
2954                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2955                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2956         } else {
2957                 temp &= ~FDI_LINK_TRAIN_NONE;
2958                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2959         }
2960         /* BPC in FDI rx is consistent with that in PIPECONF */
2961         temp &= ~(0x07 << 16);
2962         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2963         I915_WRITE(reg, temp);
2964
2965         POSTING_READ(reg);
2966         udelay(100);
2967 }
2968
2969 /*
2970  * When we disable a pipe, we need to clear any pending scanline wait events
2971  * to avoid hanging the ring, which we assume we are waiting on.
2972  */
2973 static void intel_clear_scanline_wait(struct drm_device *dev)
2974 {
2975         struct drm_i915_private *dev_priv = dev->dev_private;
2976         struct intel_ring_buffer *ring;
2977         u32 tmp;
2978
2979         if (IS_GEN2(dev))
2980                 /* Can't break the hang on i8xx */
2981                 return;
2982
2983         ring = LP_RING(dev_priv);
2984         tmp = I915_READ_CTL(ring);
2985         if (tmp & RING_WAIT)
2986                 I915_WRITE_CTL(ring, tmp);
2987 }
2988
2989 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2990 {
2991         struct drm_i915_gem_object *obj;
2992         struct drm_i915_private *dev_priv;
2993
2994         if (crtc->fb == NULL)
2995                 return;
2996
2997         obj = to_intel_framebuffer(crtc->fb)->obj;
2998         dev_priv = crtc->dev->dev_private;
2999         wait_event(dev_priv->pending_flip_queue,
3000                    atomic_read(&obj->pending_flip) == 0);
3001 }
3002
3003 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
3004 {
3005         struct drm_device *dev = crtc->dev;
3006         struct drm_mode_config *mode_config = &dev->mode_config;
3007         struct intel_encoder *encoder;
3008
3009         /*
3010          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3011          * must be driven by its own crtc; no sharing is possible.
3012          */
3013         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3014                 if (encoder->base.crtc != crtc)
3015                         continue;
3016
3017                 switch (encoder->type) {
3018                 case INTEL_OUTPUT_EDP:
3019                         if (!intel_encoder_is_pch_edp(&encoder->base))
3020                                 return false;
3021                         continue;
3022                 }
3023         }
3024
3025         return true;
3026 }
3027
3028 /*
3029  * Enable PCH resources required for PCH ports:
3030  *   - PCH PLLs
3031  *   - FDI training & RX/TX
3032  *   - update transcoder timings
3033  *   - DP transcoding bits
3034  *   - transcoder
3035  */
3036 static void ironlake_pch_enable(struct drm_crtc *crtc)
3037 {
3038         struct drm_device *dev = crtc->dev;
3039         struct drm_i915_private *dev_priv = dev->dev_private;
3040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041         int pipe = intel_crtc->pipe;
3042         u32 reg, temp, transc_sel;
3043
3044         /* For PCH output, training FDI link */
3045         dev_priv->display.fdi_link_train(crtc);
3046
3047         intel_enable_pch_pll(dev_priv, pipe);
3048
3049         if (HAS_PCH_CPT(dev)) {
3050                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
3051                         TRANSC_DPLLB_SEL;
3052
3053                 /* Be sure PCH DPLL SEL is set */
3054                 temp = I915_READ(PCH_DPLL_SEL);
3055                 if (pipe == 0) {
3056                         temp &= ~(TRANSA_DPLLB_SEL);
3057                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3058                 } else if (pipe == 1) {
3059                         temp &= ~(TRANSB_DPLLB_SEL);
3060                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3061                 } else if (pipe == 2) {
3062                         temp &= ~(TRANSC_DPLLB_SEL);
3063                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3064                 }
3065                 I915_WRITE(PCH_DPLL_SEL, temp);
3066         }
3067
3068         /* set transcoder timing, panel must allow it */
3069         assert_panel_unlocked(dev_priv, pipe);
3070         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3071         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3072         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3073
3074         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3075         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3076         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3077         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3078
3079         intel_fdi_normal_train(crtc);
3080
3081         /* For PCH DP, enable TRANS_DP_CTL */
3082         if (HAS_PCH_CPT(dev) &&
3083             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3085                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3086                 reg = TRANS_DP_CTL(pipe);
3087                 temp = I915_READ(reg);
3088                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3089                           TRANS_DP_SYNC_MASK |
3090                           TRANS_DP_BPC_MASK);
3091                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092                          TRANS_DP_ENH_FRAMING);
3093                 temp |= bpc << 9; /* same format but at 11:9 */
3094
3095                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3096                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3097                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3098                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3099
3100                 switch (intel_trans_dp_port_sel(crtc)) {
3101                 case PCH_DP_B:
3102                         temp |= TRANS_DP_PORT_SEL_B;
3103                         break;
3104                 case PCH_DP_C:
3105                         temp |= TRANS_DP_PORT_SEL_C;
3106                         break;
3107                 case PCH_DP_D:
3108                         temp |= TRANS_DP_PORT_SEL_D;
3109                         break;
3110                 default:
3111                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3112                         temp |= TRANS_DP_PORT_SEL_B;
3113                         break;
3114                 }
3115
3116                 I915_WRITE(reg, temp);
3117         }
3118
3119         intel_enable_transcoder(dev_priv, pipe);
3120 }
3121
3122 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3123 {
3124         struct drm_i915_private *dev_priv = dev->dev_private;
3125         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3126         u32 temp;
3127
3128         temp = I915_READ(dslreg);
3129         udelay(500);
3130         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3131                 /* Without this, mode sets may fail silently on FDI */
3132                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3133                 udelay(250);
3134                 I915_WRITE(tc2reg, 0);
3135                 if (wait_for(I915_READ(dslreg) != temp, 5))
3136                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3137         }
3138 }
3139
3140 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3141 {
3142         struct drm_device *dev = crtc->dev;
3143         struct drm_i915_private *dev_priv = dev->dev_private;
3144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3145         int pipe = intel_crtc->pipe;
3146         int plane = intel_crtc->plane;
3147         u32 temp;
3148         bool is_pch_port;
3149
3150         if (intel_crtc->active)
3151                 return;
3152
3153         intel_crtc->active = true;
3154         intel_update_watermarks(dev);
3155
3156         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3157                 temp = I915_READ(PCH_LVDS);
3158                 if ((temp & LVDS_PORT_EN) == 0)
3159                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3160         }
3161
3162         is_pch_port = intel_crtc_driving_pch(crtc);
3163
3164         if (is_pch_port)
3165                 ironlake_fdi_pll_enable(crtc);
3166         else
3167                 ironlake_fdi_disable(crtc);
3168
3169         /* Enable panel fitting for LVDS */
3170         if (dev_priv->pch_pf_size &&
3171             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3172                 /* Force use of hard-coded filter coefficients
3173                  * as some pre-programmed values are broken,
3174                  * e.g. x201.
3175                  */
3176                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3177                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3178                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3179         }
3180
3181         /*
3182          * On ILK+ LUT must be loaded before the pipe is running but with
3183          * clocks enabled
3184          */
3185         intel_crtc_load_lut(crtc);
3186
3187         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3188         intel_enable_plane(dev_priv, plane, pipe);
3189
3190         if (is_pch_port)
3191                 ironlake_pch_enable(crtc);
3192
3193         mutex_lock(&dev->struct_mutex);
3194         intel_update_fbc(dev);
3195         mutex_unlock(&dev->struct_mutex);
3196
3197         intel_crtc_update_cursor(crtc, true);
3198 }
3199
3200 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205         int pipe = intel_crtc->pipe;
3206         int plane = intel_crtc->plane;
3207         u32 reg, temp;
3208
3209         if (!intel_crtc->active)
3210                 return;
3211
3212         intel_crtc_wait_for_pending_flips(crtc);
3213         drm_vblank_off(dev, pipe);
3214         intel_crtc_update_cursor(crtc, false);
3215
3216         intel_disable_plane(dev_priv, plane, pipe);
3217
3218         if (dev_priv->cfb_plane == plane)
3219                 intel_disable_fbc(dev);
3220
3221         intel_disable_pipe(dev_priv, pipe);
3222
3223         /* Disable PF */
3224         I915_WRITE(PF_CTL(pipe), 0);
3225         I915_WRITE(PF_WIN_SZ(pipe), 0);
3226
3227         ironlake_fdi_disable(crtc);
3228
3229         /* This is a horrible layering violation; we should be doing this in
3230          * the connector/encoder ->prepare instead, but we don't always have
3231          * enough information there about the config to know whether it will
3232          * actually be necessary or just cause undesired flicker.
3233          */
3234         intel_disable_pch_ports(dev_priv, pipe);
3235
3236         intel_disable_transcoder(dev_priv, pipe);
3237
3238         if (HAS_PCH_CPT(dev)) {
3239                 /* disable TRANS_DP_CTL */
3240                 reg = TRANS_DP_CTL(pipe);
3241                 temp = I915_READ(reg);
3242                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3243                 temp |= TRANS_DP_PORT_SEL_NONE;
3244                 I915_WRITE(reg, temp);
3245
3246                 /* disable DPLL_SEL */
3247                 temp = I915_READ(PCH_DPLL_SEL);
3248                 switch (pipe) {
3249                 case 0:
3250                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3251                         break;
3252                 case 1:
3253                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3254                         break;
3255                 case 2:
3256                         /* C shares PLL A or B */
3257                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3258                         break;
3259                 default:
3260                         BUG(); /* wtf */
3261                 }
3262                 I915_WRITE(PCH_DPLL_SEL, temp);
3263         }
3264
3265         /* disable PCH DPLL */
3266         if (!intel_crtc->no_pll)
3267                 intel_disable_pch_pll(dev_priv, pipe);
3268
3269         /* Switch from PCDclk to Rawclk */
3270         reg = FDI_RX_CTL(pipe);
3271         temp = I915_READ(reg);
3272         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3273
3274         /* Disable CPU FDI TX PLL */
3275         reg = FDI_TX_CTL(pipe);
3276         temp = I915_READ(reg);
3277         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3278
3279         POSTING_READ(reg);
3280         udelay(100);
3281
3282         reg = FDI_RX_CTL(pipe);
3283         temp = I915_READ(reg);
3284         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3285
3286         /* Wait for the clocks to turn off. */
3287         POSTING_READ(reg);
3288         udelay(100);
3289
3290         intel_crtc->active = false;
3291         intel_update_watermarks(dev);
3292
3293         mutex_lock(&dev->struct_mutex);
3294         intel_update_fbc(dev);
3295         intel_clear_scanline_wait(dev);
3296         mutex_unlock(&dev->struct_mutex);
3297 }
3298
3299 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3300 {
3301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3302         int pipe = intel_crtc->pipe;
3303         int plane = intel_crtc->plane;
3304
3305         /* XXX: When our outputs are all unaware of DPMS modes other than off
3306          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3307          */
3308         switch (mode) {
3309         case DRM_MODE_DPMS_ON:
3310         case DRM_MODE_DPMS_STANDBY:
3311         case DRM_MODE_DPMS_SUSPEND:
3312                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3313                 ironlake_crtc_enable(crtc);
3314                 break;
3315
3316         case DRM_MODE_DPMS_OFF:
3317                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3318                 ironlake_crtc_disable(crtc);
3319                 break;
3320         }
3321 }
3322
3323 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3324 {
3325         if (!enable && intel_crtc->overlay) {
3326                 struct drm_device *dev = intel_crtc->base.dev;
3327                 struct drm_i915_private *dev_priv = dev->dev_private;
3328
3329                 mutex_lock(&dev->struct_mutex);
3330                 dev_priv->mm.interruptible = false;
3331                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3332                 dev_priv->mm.interruptible = true;
3333                 mutex_unlock(&dev->struct_mutex);
3334         }
3335
3336         /* Let userspace switch the overlay on again. In most cases userspace
3337          * has to recompute where to put it anyway.
3338          */
3339 }
3340
3341 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346         int pipe = intel_crtc->pipe;
3347         int plane = intel_crtc->plane;
3348
3349         if (intel_crtc->active)
3350                 return;
3351
3352         intel_crtc->active = true;
3353         intel_update_watermarks(dev);
3354
3355         intel_enable_pll(dev_priv, pipe);
3356         intel_enable_pipe(dev_priv, pipe, false);
3357         intel_enable_plane(dev_priv, plane, pipe);
3358
3359         intel_crtc_load_lut(crtc);
3360         intel_update_fbc(dev);
3361
3362         /* Give the overlay scaler a chance to enable if it's on this pipe */
3363         intel_crtc_dpms_overlay(intel_crtc, true);
3364         intel_crtc_update_cursor(crtc, true);
3365 }
3366
3367 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3368 {
3369         struct drm_device *dev = crtc->dev;
3370         struct drm_i915_private *dev_priv = dev->dev_private;
3371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3372         int pipe = intel_crtc->pipe;
3373         int plane = intel_crtc->plane;
3374
3375         if (!intel_crtc->active)
3376                 return;
3377
3378         /* Give the overlay scaler a chance to disable if it's on this pipe */
3379         intel_crtc_wait_for_pending_flips(crtc);
3380         drm_vblank_off(dev, pipe);
3381         intel_crtc_dpms_overlay(intel_crtc, false);
3382         intel_crtc_update_cursor(crtc, false);
3383
3384         if (dev_priv->cfb_plane == plane)
3385                 intel_disable_fbc(dev);
3386
3387         intel_disable_plane(dev_priv, plane, pipe);
3388         intel_disable_pipe(dev_priv, pipe);
3389         intel_disable_pll(dev_priv, pipe);
3390
3391         intel_crtc->active = false;
3392         intel_update_fbc(dev);
3393         intel_update_watermarks(dev);
3394         intel_clear_scanline_wait(dev);
3395 }
3396
3397 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3398 {
3399         /* XXX: When our outputs are all unaware of DPMS modes other than off
3400          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3401          */
3402         switch (mode) {
3403         case DRM_MODE_DPMS_ON:
3404         case DRM_MODE_DPMS_STANDBY:
3405         case DRM_MODE_DPMS_SUSPEND:
3406                 i9xx_crtc_enable(crtc);
3407                 break;
3408         case DRM_MODE_DPMS_OFF:
3409                 i9xx_crtc_disable(crtc);
3410                 break;
3411         }
3412 }
3413
3414 /**
3415  * Sets the power management mode of the pipe and plane.
3416  */
3417 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3418 {
3419         struct drm_device *dev = crtc->dev;
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         struct drm_i915_master_private *master_priv;
3422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423         int pipe = intel_crtc->pipe;
3424         bool enabled;
3425
3426         if (intel_crtc->dpms_mode == mode)
3427                 return;
3428
3429         intel_crtc->dpms_mode = mode;
3430
3431         dev_priv->display.dpms(crtc, mode);
3432
3433         if (!dev->primary->master)
3434                 return;
3435
3436         master_priv = dev->primary->master->driver_priv;
3437         if (!master_priv->sarea_priv)
3438                 return;
3439
3440         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3441
3442         switch (pipe) {
3443         case 0:
3444                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3445                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3446                 break;
3447         case 1:
3448                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3449                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3450                 break;
3451         default:
3452                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3453                 break;
3454         }
3455 }
3456
3457 static void intel_crtc_disable(struct drm_crtc *crtc)
3458 {
3459         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3460         struct drm_device *dev = crtc->dev;
3461
3462         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3463         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3464         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3465
3466         if (crtc->fb) {
3467                 mutex_lock(&dev->struct_mutex);
3468                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3469                 mutex_unlock(&dev->struct_mutex);
3470         }
3471 }
3472
3473 /* Prepare for a mode set.
3474  *
3475  * Note we could be a lot smarter here.  We need to figure out which outputs
3476  * will be enabled, which disabled (in short, how the config will changes)
3477  * and perform the minimum necessary steps to accomplish that, e.g. updating
3478  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3479  * panel fitting is in the proper state, etc.
3480  */
3481 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3482 {
3483         i9xx_crtc_disable(crtc);
3484 }
3485
3486 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3487 {
3488         i9xx_crtc_enable(crtc);
3489 }
3490
3491 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3492 {
3493         ironlake_crtc_disable(crtc);
3494 }
3495
3496 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3497 {
3498         ironlake_crtc_enable(crtc);
3499 }
3500
3501 void intel_encoder_prepare(struct drm_encoder *encoder)
3502 {
3503         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3504         /* lvds has its own version of prepare see intel_lvds_prepare */
3505         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3506 }
3507
3508 void intel_encoder_commit(struct drm_encoder *encoder)
3509 {
3510         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3511         struct drm_device *dev = encoder->dev;
3512         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3513         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3514
3515         /* lvds has its own version of commit see intel_lvds_commit */
3516         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3517
3518         if (HAS_PCH_CPT(dev))
3519                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3520 }
3521
3522 void intel_encoder_destroy(struct drm_encoder *encoder)
3523 {
3524         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3525
3526         drm_encoder_cleanup(encoder);
3527         kfree(intel_encoder);
3528 }
3529
3530 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3531                                   struct drm_display_mode *mode,
3532                                   struct drm_display_mode *adjusted_mode)
3533 {
3534         struct drm_device *dev = crtc->dev;
3535
3536         if (HAS_PCH_SPLIT(dev)) {
3537                 /* FDI link clock is fixed at 2.7G */
3538                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3539                         return false;
3540         }
3541
3542         /* All interlaced capable intel hw wants timings in frames. */
3543         drm_mode_set_crtcinfo(adjusted_mode, 0);
3544
3545         return true;
3546 }
3547
3548 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3549 {
3550         return 400000; /* FIXME */
3551 }
3552
3553 static int i945_get_display_clock_speed(struct drm_device *dev)
3554 {
3555         return 400000;
3556 }
3557
3558 static int i915_get_display_clock_speed(struct drm_device *dev)
3559 {
3560         return 333000;
3561 }
3562
3563 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3564 {
3565         return 200000;
3566 }
3567
3568 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3569 {
3570         u16 gcfgc = 0;
3571
3572         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3573
3574         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3575                 return 133000;
3576         else {
3577                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3578                 case GC_DISPLAY_CLOCK_333_MHZ:
3579                         return 333000;
3580                 default:
3581                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3582                         return 190000;
3583                 }
3584         }
3585 }
3586
3587 static int i865_get_display_clock_speed(struct drm_device *dev)
3588 {
3589         return 266000;
3590 }
3591
3592 static int i855_get_display_clock_speed(struct drm_device *dev)
3593 {
3594         u16 hpllcc = 0;
3595         /* Assume that the hardware is in the high speed state.  This
3596          * should be the default.
3597          */
3598         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3599         case GC_CLOCK_133_200:
3600         case GC_CLOCK_100_200:
3601                 return 200000;
3602         case GC_CLOCK_166_250:
3603                 return 250000;
3604         case GC_CLOCK_100_133:
3605                 return 133000;
3606         }
3607
3608         /* Shouldn't happen */
3609         return 0;
3610 }
3611
3612 static int i830_get_display_clock_speed(struct drm_device *dev)
3613 {
3614         return 133000;
3615 }
3616
3617 struct fdi_m_n {
3618         u32        tu;
3619         u32        gmch_m;
3620         u32        gmch_n;
3621         u32        link_m;
3622         u32        link_n;
3623 };
3624
3625 static void
3626 fdi_reduce_ratio(u32 *num, u32 *den)
3627 {
3628         while (*num > 0xffffff || *den > 0xffffff) {
3629                 *num >>= 1;
3630                 *den >>= 1;
3631         }
3632 }
3633
3634 static void
3635 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3636                      int link_clock, struct fdi_m_n *m_n)
3637 {
3638         m_n->tu = 64; /* default size */
3639
3640         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3641         m_n->gmch_m = bits_per_pixel * pixel_clock;
3642         m_n->gmch_n = link_clock * nlanes * 8;
3643         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3644
3645         m_n->link_m = pixel_clock;
3646         m_n->link_n = link_clock;
3647         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3648 }
3649
3650
3651 struct intel_watermark_params {
3652         unsigned long fifo_size;
3653         unsigned long max_wm;
3654         unsigned long default_wm;
3655         unsigned long guard_size;
3656         unsigned long cacheline_size;
3657 };
3658
3659 /* Pineview has different values for various configs */
3660 static const struct intel_watermark_params pineview_display_wm = {
3661         PINEVIEW_DISPLAY_FIFO,
3662         PINEVIEW_MAX_WM,
3663         PINEVIEW_DFT_WM,
3664         PINEVIEW_GUARD_WM,
3665         PINEVIEW_FIFO_LINE_SIZE
3666 };
3667 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3668         PINEVIEW_DISPLAY_FIFO,
3669         PINEVIEW_MAX_WM,
3670         PINEVIEW_DFT_HPLLOFF_WM,
3671         PINEVIEW_GUARD_WM,
3672         PINEVIEW_FIFO_LINE_SIZE
3673 };
3674 static const struct intel_watermark_params pineview_cursor_wm = {
3675         PINEVIEW_CURSOR_FIFO,
3676         PINEVIEW_CURSOR_MAX_WM,
3677         PINEVIEW_CURSOR_DFT_WM,
3678         PINEVIEW_CURSOR_GUARD_WM,
3679         PINEVIEW_FIFO_LINE_SIZE,
3680 };
3681 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3682         PINEVIEW_CURSOR_FIFO,
3683         PINEVIEW_CURSOR_MAX_WM,
3684         PINEVIEW_CURSOR_DFT_WM,
3685         PINEVIEW_CURSOR_GUARD_WM,
3686         PINEVIEW_FIFO_LINE_SIZE
3687 };
3688 static const struct intel_watermark_params g4x_wm_info = {
3689         G4X_FIFO_SIZE,
3690         G4X_MAX_WM,
3691         G4X_MAX_WM,
3692         2,
3693         G4X_FIFO_LINE_SIZE,
3694 };
3695 static const struct intel_watermark_params g4x_cursor_wm_info = {
3696         I965_CURSOR_FIFO,
3697         I965_CURSOR_MAX_WM,
3698         I965_CURSOR_DFT_WM,
3699         2,
3700         G4X_FIFO_LINE_SIZE,
3701 };
3702 static const struct intel_watermark_params valleyview_wm_info = {
3703         VALLEYVIEW_FIFO_SIZE,
3704         VALLEYVIEW_MAX_WM,
3705         VALLEYVIEW_MAX_WM,
3706         2,
3707         G4X_FIFO_LINE_SIZE,
3708 };
3709 static const struct intel_watermark_params valleyview_cursor_wm_info = {
3710         I965_CURSOR_FIFO,
3711         VALLEYVIEW_CURSOR_MAX_WM,
3712         I965_CURSOR_DFT_WM,
3713         2,
3714         G4X_FIFO_LINE_SIZE,
3715 };
3716 static const struct intel_watermark_params i965_cursor_wm_info = {
3717         I965_CURSOR_FIFO,
3718         I965_CURSOR_MAX_WM,
3719         I965_CURSOR_DFT_WM,
3720         2,
3721         I915_FIFO_LINE_SIZE,
3722 };
3723 static const struct intel_watermark_params i945_wm_info = {
3724         I945_FIFO_SIZE,
3725         I915_MAX_WM,
3726         1,
3727         2,
3728         I915_FIFO_LINE_SIZE
3729 };
3730 static const struct intel_watermark_params i915_wm_info = {
3731         I915_FIFO_SIZE,
3732         I915_MAX_WM,
3733         1,
3734         2,
3735         I915_FIFO_LINE_SIZE
3736 };
3737 static const struct intel_watermark_params i855_wm_info = {
3738         I855GM_FIFO_SIZE,
3739         I915_MAX_WM,
3740         1,
3741         2,
3742         I830_FIFO_LINE_SIZE
3743 };
3744 static const struct intel_watermark_params i830_wm_info = {
3745         I830_FIFO_SIZE,
3746         I915_MAX_WM,
3747         1,
3748         2,
3749         I830_FIFO_LINE_SIZE
3750 };
3751
3752 static const struct intel_watermark_params ironlake_display_wm_info = {
3753         ILK_DISPLAY_FIFO,
3754         ILK_DISPLAY_MAXWM,
3755         ILK_DISPLAY_DFTWM,
3756         2,
3757         ILK_FIFO_LINE_SIZE
3758 };
3759 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3760         ILK_CURSOR_FIFO,
3761         ILK_CURSOR_MAXWM,
3762         ILK_CURSOR_DFTWM,
3763         2,
3764         ILK_FIFO_LINE_SIZE
3765 };
3766 static const struct intel_watermark_params ironlake_display_srwm_info = {
3767         ILK_DISPLAY_SR_FIFO,
3768         ILK_DISPLAY_MAX_SRWM,
3769         ILK_DISPLAY_DFT_SRWM,
3770         2,
3771         ILK_FIFO_LINE_SIZE
3772 };
3773 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3774         ILK_CURSOR_SR_FIFO,
3775         ILK_CURSOR_MAX_SRWM,
3776         ILK_CURSOR_DFT_SRWM,
3777         2,
3778         ILK_FIFO_LINE_SIZE
3779 };
3780
3781 static const struct intel_watermark_params sandybridge_display_wm_info = {
3782         SNB_DISPLAY_FIFO,
3783         SNB_DISPLAY_MAXWM,
3784         SNB_DISPLAY_DFTWM,
3785         2,
3786         SNB_FIFO_LINE_SIZE
3787 };
3788 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3789         SNB_CURSOR_FIFO,
3790         SNB_CURSOR_MAXWM,
3791         SNB_CURSOR_DFTWM,
3792         2,
3793         SNB_FIFO_LINE_SIZE
3794 };
3795 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3796         SNB_DISPLAY_SR_FIFO,
3797         SNB_DISPLAY_MAX_SRWM,
3798         SNB_DISPLAY_DFT_SRWM,
3799         2,
3800         SNB_FIFO_LINE_SIZE
3801 };
3802 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3803         SNB_CURSOR_SR_FIFO,
3804         SNB_CURSOR_MAX_SRWM,
3805         SNB_CURSOR_DFT_SRWM,
3806         2,
3807         SNB_FIFO_LINE_SIZE
3808 };
3809
3810
3811 /**
3812  * intel_calculate_wm - calculate watermark level
3813  * @clock_in_khz: pixel clock
3814  * @wm: chip FIFO params
3815  * @pixel_size: display pixel size
3816  * @latency_ns: memory latency for the platform
3817  *
3818  * Calculate the watermark level (the level at which the display plane will
3819  * start fetching from memory again).  Each chip has a different display
3820  * FIFO size and allocation, so the caller needs to figure that out and pass
3821  * in the correct intel_watermark_params structure.
3822  *
3823  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3824  * on the pixel size.  When it reaches the watermark level, it'll start
3825  * fetching FIFO line sized based chunks from memory until the FIFO fills
3826  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3827  * will occur, and a display engine hang could result.
3828  */
3829 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3830                                         const struct intel_watermark_params *wm,
3831                                         int fifo_size,
3832                                         int pixel_size,
3833                                         unsigned long latency_ns)
3834 {
3835         long entries_required, wm_size;
3836
3837         /*
3838          * Note: we need to make sure we don't overflow for various clock &
3839          * latency values.
3840          * clocks go from a few thousand to several hundred thousand.
3841          * latency is usually a few thousand
3842          */
3843         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3844                 1000;
3845         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3846
3847         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3848
3849         wm_size = fifo_size - (entries_required + wm->guard_size);
3850
3851         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3852
3853         /* Don't promote wm_size to unsigned... */
3854         if (wm_size > (long)wm->max_wm)
3855                 wm_size = wm->max_wm;
3856         if (wm_size <= 0)
3857                 wm_size = wm->default_wm;
3858         return wm_size;
3859 }
3860
3861 struct cxsr_latency {
3862         int is_desktop;
3863         int is_ddr3;
3864         unsigned long fsb_freq;
3865         unsigned long mem_freq;
3866         unsigned long display_sr;
3867         unsigned long display_hpll_disable;
3868         unsigned long cursor_sr;
3869         unsigned long cursor_hpll_disable;
3870 };
3871
3872 static const struct cxsr_latency cxsr_latency_table[] = {
3873         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3874         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3875         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3876         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3877         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3878
3879         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3880         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3881         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3882         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3883         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3884
3885         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3886         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3887         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3888         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3889         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3890
3891         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3892         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3893         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3894         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3895         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3896
3897         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3898         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3899         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3900         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3901         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3902
3903         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3904         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3905         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3906         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3907         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3908 };
3909
3910 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3911                                                          int is_ddr3,
3912                                                          int fsb,
3913                                                          int mem)
3914 {
3915         const struct cxsr_latency *latency;
3916         int i;
3917
3918         if (fsb == 0 || mem == 0)
3919                 return NULL;
3920
3921         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3922                 latency = &cxsr_latency_table[i];
3923                 if (is_desktop == latency->is_desktop &&
3924                     is_ddr3 == latency->is_ddr3 &&
3925                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3926                         return latency;
3927         }
3928
3929         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3930
3931         return NULL;
3932 }
3933
3934 static void pineview_disable_cxsr(struct drm_device *dev)
3935 {
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937
3938         /* deactivate cxsr */
3939         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3940 }
3941
3942 /*
3943  * Latency for FIFO fetches is dependent on several factors:
3944  *   - memory configuration (speed, channels)
3945  *   - chipset
3946  *   - current MCH state
3947  * It can be fairly high in some situations, so here we assume a fairly
3948  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3949  * set this value too high, the FIFO will fetch frequently to stay full)
3950  * and power consumption (set it too low to save power and we might see
3951  * FIFO underruns and display "flicker").
3952  *
3953  * A value of 5us seems to be a good balance; safe for very low end
3954  * platforms but not overly aggressive on lower latency configs.
3955  */
3956 static const int latency_ns = 5000;
3957
3958 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3959 {
3960         struct drm_i915_private *dev_priv = dev->dev_private;
3961         uint32_t dsparb = I915_READ(DSPARB);
3962         int size;
3963
3964         size = dsparb & 0x7f;
3965         if (plane)
3966                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3967
3968         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3969                       plane ? "B" : "A", size);
3970
3971         return size;
3972 }
3973
3974 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3975 {
3976         struct drm_i915_private *dev_priv = dev->dev_private;
3977         uint32_t dsparb = I915_READ(DSPARB);
3978         int size;
3979
3980         size = dsparb & 0x1ff;
3981         if (plane)
3982                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3983         size >>= 1; /* Convert to cachelines */
3984
3985         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3986                       plane ? "B" : "A", size);
3987
3988         return size;
3989 }
3990
3991 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3992 {
3993         struct drm_i915_private *dev_priv = dev->dev_private;
3994         uint32_t dsparb = I915_READ(DSPARB);
3995         int size;
3996
3997         size = dsparb & 0x7f;
3998         size >>= 2; /* Convert to cachelines */
3999
4000         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4001                       plane ? "B" : "A",
4002                       size);
4003
4004         return size;
4005 }
4006
4007 static int i830_get_fifo_size(struct drm_device *dev, int plane)
4008 {
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         uint32_t dsparb = I915_READ(DSPARB);
4011         int size;
4012
4013         size = dsparb & 0x7f;
4014         size >>= 1; /* Convert to cachelines */
4015
4016         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4017                       plane ? "B" : "A", size);
4018
4019         return size;
4020 }
4021
4022 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
4023 {
4024         struct drm_crtc *crtc, *enabled = NULL;
4025
4026         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4027                 if (crtc->enabled && crtc->fb) {
4028                         if (enabled)
4029                                 return NULL;
4030                         enabled = crtc;
4031                 }
4032         }
4033
4034         return enabled;
4035 }
4036
4037 static void pineview_update_wm(struct drm_device *dev)
4038 {
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040         struct drm_crtc *crtc;
4041         const struct cxsr_latency *latency;
4042         u32 reg;
4043         unsigned long wm;
4044
4045         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
4046                                          dev_priv->fsb_freq, dev_priv->mem_freq);
4047         if (!latency) {
4048                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
4049                 pineview_disable_cxsr(dev);
4050                 return;
4051         }
4052
4053         crtc = single_enabled_crtc(dev);
4054         if (crtc) {
4055                 int clock = crtc->mode.clock;
4056                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4057
4058                 /* Display SR */
4059                 wm = intel_calculate_wm(clock, &pineview_display_wm,
4060                                         pineview_display_wm.fifo_size,
4061                                         pixel_size, latency->display_sr);
4062                 reg = I915_READ(DSPFW1);
4063                 reg &= ~DSPFW_SR_MASK;
4064                 reg |= wm << DSPFW_SR_SHIFT;
4065                 I915_WRITE(DSPFW1, reg);
4066                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4067
4068                 /* cursor SR */
4069                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4070                                         pineview_display_wm.fifo_size,
4071                                         pixel_size, latency->cursor_sr);
4072                 reg = I915_READ(DSPFW3);
4073                 reg &= ~DSPFW_CURSOR_SR_MASK;
4074                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4075                 I915_WRITE(DSPFW3, reg);
4076
4077                 /* Display HPLL off SR */
4078                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4079                                         pineview_display_hplloff_wm.fifo_size,
4080                                         pixel_size, latency->display_hpll_disable);
4081                 reg = I915_READ(DSPFW3);
4082                 reg &= ~DSPFW_HPLL_SR_MASK;
4083                 reg |= wm & DSPFW_HPLL_SR_MASK;
4084                 I915_WRITE(DSPFW3, reg);
4085
4086                 /* cursor HPLL off SR */
4087                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4088                                         pineview_display_hplloff_wm.fifo_size,
4089                                         pixel_size, latency->cursor_hpll_disable);
4090                 reg = I915_READ(DSPFW3);
4091                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4092                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4093                 I915_WRITE(DSPFW3, reg);
4094                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4095
4096                 /* activate cxsr */
4097                 I915_WRITE(DSPFW3,
4098                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4099                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4100         } else {
4101                 pineview_disable_cxsr(dev);
4102                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4103         }
4104 }
4105
4106 static bool g4x_compute_wm0(struct drm_device *dev,
4107                             int plane,
4108                             const struct intel_watermark_params *display,
4109                             int display_latency_ns,
4110                             const struct intel_watermark_params *cursor,
4111                             int cursor_latency_ns,
4112                             int *plane_wm,
4113                             int *cursor_wm)
4114 {
4115         struct drm_crtc *crtc;
4116         int htotal, hdisplay, clock, pixel_size;
4117         int line_time_us, line_count;
4118         int entries, tlb_miss;
4119
4120         crtc = intel_get_crtc_for_plane(dev, plane);
4121         if (crtc->fb == NULL || !crtc->enabled) {
4122                 *cursor_wm = cursor->guard_size;
4123                 *plane_wm = display->guard_size;
4124                 return false;
4125         }
4126
4127         htotal = crtc->mode.htotal;
4128         hdisplay = crtc->mode.hdisplay;
4129         clock = crtc->mode.clock;
4130         pixel_size = crtc->fb->bits_per_pixel / 8;
4131
4132         /* Use the small buffer method to calculate plane watermark */
4133         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4134         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4135         if (tlb_miss > 0)
4136                 entries += tlb_miss;
4137         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4138         *plane_wm = entries + display->guard_size;
4139         if (*plane_wm > (int)display->max_wm)
4140                 *plane_wm = display->max_wm;
4141
4142         /* Use the large buffer method to calculate cursor watermark */
4143         line_time_us = ((htotal * 1000) / clock);
4144         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4145         entries = line_count * 64 * pixel_size;
4146         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4147         if (tlb_miss > 0)
4148                 entries += tlb_miss;
4149         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4150         *cursor_wm = entries + cursor->guard_size;
4151         if (*cursor_wm > (int)cursor->max_wm)
4152                 *cursor_wm = (int)cursor->max_wm;
4153
4154         return true;
4155 }
4156
4157 /*
4158  * Check the wm result.
4159  *
4160  * If any calculated watermark values is larger than the maximum value that
4161  * can be programmed into the associated watermark register, that watermark
4162  * must be disabled.
4163  */
4164 static bool g4x_check_srwm(struct drm_device *dev,
4165                            int display_wm, int cursor_wm,
4166                            const struct intel_watermark_params *display,
4167                            const struct intel_watermark_params *cursor)
4168 {
4169         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4170                       display_wm, cursor_wm);
4171
4172         if (display_wm > display->max_wm) {
4173                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4174                               display_wm, display->max_wm);
4175                 return false;
4176         }
4177
4178         if (cursor_wm > cursor->max_wm) {
4179                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4180                               cursor_wm, cursor->max_wm);
4181                 return false;
4182         }
4183
4184         if (!(display_wm || cursor_wm)) {
4185                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4186                 return false;
4187         }
4188
4189         return true;
4190 }
4191
4192 static bool g4x_compute_srwm(struct drm_device *dev,
4193                              int plane,
4194                              int latency_ns,
4195                              const struct intel_watermark_params *display,
4196                              const struct intel_watermark_params *cursor,
4197                              int *display_wm, int *cursor_wm)
4198 {
4199         struct drm_crtc *crtc;
4200         int hdisplay, htotal, pixel_size, clock;
4201         unsigned long line_time_us;
4202         int line_count, line_size;
4203         int small, large;
4204         int entries;
4205
4206         if (!latency_ns) {
4207                 *display_wm = *cursor_wm = 0;
4208                 return false;
4209         }
4210
4211         crtc = intel_get_crtc_for_plane(dev, plane);
4212         hdisplay = crtc->mode.hdisplay;
4213         htotal = crtc->mode.htotal;
4214         clock = crtc->mode.clock;
4215         pixel_size = crtc->fb->bits_per_pixel / 8;
4216
4217         line_time_us = (htotal * 1000) / clock;
4218         line_count = (latency_ns / line_time_us + 1000) / 1000;
4219         line_size = hdisplay * pixel_size;
4220
4221         /* Use the minimum of the small and large buffer method for primary */
4222         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4223         large = line_count * line_size;
4224
4225         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4226         *display_wm = entries + display->guard_size;
4227
4228         /* calculate the self-refresh watermark for display cursor */
4229         entries = line_count * pixel_size * 64;
4230         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4231         *cursor_wm = entries + cursor->guard_size;
4232
4233         return g4x_check_srwm(dev,
4234                               *display_wm, *cursor_wm,
4235                               display, cursor);
4236 }
4237
4238 #define single_plane_enabled(mask) is_power_of_2(mask)
4239
4240 static void valleyview_update_wm(struct drm_device *dev)
4241 {
4242         static const int sr_latency_ns = 12000;
4243         struct drm_i915_private *dev_priv = dev->dev_private;
4244         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4245         int plane_sr, cursor_sr;
4246         unsigned int enabled = 0;
4247
4248         if (g4x_compute_wm0(dev, 0,
4249                             &valleyview_wm_info, latency_ns,
4250                             &valleyview_cursor_wm_info, latency_ns,
4251                             &planea_wm, &cursora_wm))
4252                 enabled |= 1;
4253
4254         if (g4x_compute_wm0(dev, 1,
4255                             &valleyview_wm_info, latency_ns,
4256                             &valleyview_cursor_wm_info, latency_ns,
4257                             &planeb_wm, &cursorb_wm))
4258                 enabled |= 2;
4259
4260         plane_sr = cursor_sr = 0;
4261         if (single_plane_enabled(enabled) &&
4262             g4x_compute_srwm(dev, ffs(enabled) - 1,
4263                              sr_latency_ns,
4264                              &valleyview_wm_info,
4265                              &valleyview_cursor_wm_info,
4266                              &plane_sr, &cursor_sr))
4267                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
4268         else
4269                 I915_WRITE(FW_BLC_SELF_VLV,
4270                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
4271
4272         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4273                       planea_wm, cursora_wm,
4274                       planeb_wm, cursorb_wm,
4275                       plane_sr, cursor_sr);
4276
4277         I915_WRITE(DSPFW1,
4278                    (plane_sr << DSPFW_SR_SHIFT) |
4279                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4280                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4281                    planea_wm);
4282         I915_WRITE(DSPFW2,
4283                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4284                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4285         I915_WRITE(DSPFW3,
4286                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
4287 }
4288
4289 static void g4x_update_wm(struct drm_device *dev)
4290 {
4291         static const int sr_latency_ns = 12000;
4292         struct drm_i915_private *dev_priv = dev->dev_private;
4293         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4294         int plane_sr, cursor_sr;
4295         unsigned int enabled = 0;
4296
4297         if (g4x_compute_wm0(dev, 0,
4298                             &g4x_wm_info, latency_ns,
4299                             &g4x_cursor_wm_info, latency_ns,
4300                             &planea_wm, &cursora_wm))
4301                 enabled |= 1;
4302
4303         if (g4x_compute_wm0(dev, 1,
4304                             &g4x_wm_info, latency_ns,
4305                             &g4x_cursor_wm_info, latency_ns,
4306                             &planeb_wm, &cursorb_wm))
4307                 enabled |= 2;
4308
4309         plane_sr = cursor_sr = 0;
4310         if (single_plane_enabled(enabled) &&
4311             g4x_compute_srwm(dev, ffs(enabled) - 1,
4312                              sr_latency_ns,
4313                              &g4x_wm_info,
4314                              &g4x_cursor_wm_info,
4315                              &plane_sr, &cursor_sr))
4316                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4317         else
4318                 I915_WRITE(FW_BLC_SELF,
4319                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4320
4321         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4322                       planea_wm, cursora_wm,
4323                       planeb_wm, cursorb_wm,
4324                       plane_sr, cursor_sr);
4325
4326         I915_WRITE(DSPFW1,
4327                    (plane_sr << DSPFW_SR_SHIFT) |
4328                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4329                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4330                    planea_wm);
4331         I915_WRITE(DSPFW2,
4332                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4333                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4334         /* HPLL off in SR has some issues on G4x... disable it */
4335         I915_WRITE(DSPFW3,
4336                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4337                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4338 }
4339
4340 static void i965_update_wm(struct drm_device *dev)
4341 {
4342         struct drm_i915_private *dev_priv = dev->dev_private;
4343         struct drm_crtc *crtc;
4344         int srwm = 1;
4345         int cursor_sr = 16;
4346
4347         /* Calc sr entries for one plane configs */
4348         crtc = single_enabled_crtc(dev);
4349         if (crtc) {
4350                 /* self-refresh has much higher latency */
4351                 static const int sr_latency_ns = 12000;
4352                 int clock = crtc->mode.clock;
4353                 int htotal = crtc->mode.htotal;
4354                 int hdisplay = crtc->mode.hdisplay;
4355                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4356                 unsigned long line_time_us;
4357                 int entries;
4358
4359                 line_time_us = ((htotal * 1000) / clock);
4360
4361                 /* Use ns/us then divide to preserve precision */
4362                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4363                         pixel_size * hdisplay;
4364                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4365                 srwm = I965_FIFO_SIZE - entries;
4366                 if (srwm < 0)
4367                         srwm = 1;
4368                 srwm &= 0x1ff;
4369                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4370                               entries, srwm);
4371
4372                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4373                         pixel_size * 64;
4374                 entries = DIV_ROUND_UP(entries,
4375                                           i965_cursor_wm_info.cacheline_size);
4376                 cursor_sr = i965_cursor_wm_info.fifo_size -
4377                         (entries + i965_cursor_wm_info.guard_size);
4378
4379                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4380                         cursor_sr = i965_cursor_wm_info.max_wm;
4381
4382                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4383                               "cursor %d\n", srwm, cursor_sr);
4384
4385                 if (IS_CRESTLINE(dev))
4386                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4387         } else {
4388                 /* Turn off self refresh if both pipes are enabled */
4389                 if (IS_CRESTLINE(dev))
4390                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4391                                    & ~FW_BLC_SELF_EN);
4392         }
4393
4394         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4395                       srwm);
4396
4397         /* 965 has limitations... */
4398         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4399                    (8 << 16) | (8 << 8) | (8 << 0));
4400         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4401         /* update cursor SR watermark */
4402         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4403 }
4404
4405 static void i9xx_update_wm(struct drm_device *dev)
4406 {
4407         struct drm_i915_private *dev_priv = dev->dev_private;
4408         const struct intel_watermark_params *wm_info;
4409         uint32_t fwater_lo;
4410         uint32_t fwater_hi;
4411         int cwm, srwm = 1;
4412         int fifo_size;
4413         int planea_wm, planeb_wm;
4414         struct drm_crtc *crtc, *enabled = NULL;
4415
4416         if (IS_I945GM(dev))
4417                 wm_info = &i945_wm_info;
4418         else if (!IS_GEN2(dev))
4419                 wm_info = &i915_wm_info;
4420         else
4421                 wm_info = &i855_wm_info;
4422
4423         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4424         crtc = intel_get_crtc_for_plane(dev, 0);
4425         if (crtc->enabled && crtc->fb) {
4426                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4427                                                wm_info, fifo_size,
4428                                                crtc->fb->bits_per_pixel / 8,
4429                                                latency_ns);
4430                 enabled = crtc;
4431         } else
4432                 planea_wm = fifo_size - wm_info->guard_size;
4433
4434         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4435         crtc = intel_get_crtc_for_plane(dev, 1);
4436         if (crtc->enabled && crtc->fb) {
4437                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4438                                                wm_info, fifo_size,
4439                                                crtc->fb->bits_per_pixel / 8,
4440                                                latency_ns);
4441                 if (enabled == NULL)
4442                         enabled = crtc;
4443                 else
4444                         enabled = NULL;
4445         } else
4446                 planeb_wm = fifo_size - wm_info->guard_size;
4447
4448         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4449
4450         /*
4451          * Overlay gets an aggressive default since video jitter is bad.
4452          */
4453         cwm = 2;
4454
4455         /* Play safe and disable self-refresh before adjusting watermarks. */
4456         if (IS_I945G(dev) || IS_I945GM(dev))
4457                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4458         else if (IS_I915GM(dev))
4459                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4460
4461         /* Calc sr entries for one plane configs */
4462         if (HAS_FW_BLC(dev) && enabled) {
4463                 /* self-refresh has much higher latency */
4464                 static const int sr_latency_ns = 6000;
4465                 int clock = enabled->mode.clock;
4466                 int htotal = enabled->mode.htotal;
4467                 int hdisplay = enabled->mode.hdisplay;
4468                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4469                 unsigned long line_time_us;
4470                 int entries;
4471
4472                 line_time_us = (htotal * 1000) / clock;
4473
4474                 /* Use ns/us then divide to preserve precision */
4475                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4476                         pixel_size * hdisplay;
4477                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4478                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4479                 srwm = wm_info->fifo_size - entries;
4480                 if (srwm < 0)
4481                         srwm = 1;
4482
4483                 if (IS_I945G(dev) || IS_I945GM(dev))
4484                         I915_WRITE(FW_BLC_SELF,
4485                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4486                 else if (IS_I915GM(dev))
4487                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4488         }
4489
4490         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4491                       planea_wm, planeb_wm, cwm, srwm);
4492
4493         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4494         fwater_hi = (cwm & 0x1f);
4495
4496         /* Set request length to 8 cachelines per fetch */
4497         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4498         fwater_hi = fwater_hi | (1 << 8);
4499
4500         I915_WRITE(FW_BLC, fwater_lo);
4501         I915_WRITE(FW_BLC2, fwater_hi);
4502
4503         if (HAS_FW_BLC(dev)) {
4504                 if (enabled) {
4505                         if (IS_I945G(dev) || IS_I945GM(dev))
4506                                 I915_WRITE(FW_BLC_SELF,
4507                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4508                         else if (IS_I915GM(dev))
4509                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4510                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4511                 } else
4512                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4513         }
4514 }
4515
4516 static void i830_update_wm(struct drm_device *dev)
4517 {
4518         struct drm_i915_private *dev_priv = dev->dev_private;
4519         struct drm_crtc *crtc;
4520         uint32_t fwater_lo;
4521         int planea_wm;
4522
4523         crtc = single_enabled_crtc(dev);
4524         if (crtc == NULL)
4525                 return;
4526
4527         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4528                                        dev_priv->display.get_fifo_size(dev, 0),
4529                                        crtc->fb->bits_per_pixel / 8,
4530                                        latency_ns);
4531         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4532         fwater_lo |= (3<<8) | planea_wm;
4533
4534         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4535
4536         I915_WRITE(FW_BLC, fwater_lo);
4537 }
4538
4539 #define ILK_LP0_PLANE_LATENCY           700
4540 #define ILK_LP0_CURSOR_LATENCY          1300
4541
4542 /*
4543  * Check the wm result.
4544  *
4545  * If any calculated watermark values is larger than the maximum value that
4546  * can be programmed into the associated watermark register, that watermark
4547  * must be disabled.
4548  */
4549 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4550                                 int fbc_wm, int display_wm, int cursor_wm,
4551                                 const struct intel_watermark_params *display,
4552                                 const struct intel_watermark_params *cursor)
4553 {
4554         struct drm_i915_private *dev_priv = dev->dev_private;
4555
4556         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4557                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4558
4559         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4560                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4561                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4562
4563                 /* fbc has it's own way to disable FBC WM */
4564                 I915_WRITE(DISP_ARB_CTL,
4565                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4566                 return false;
4567         }
4568
4569         if (display_wm > display->max_wm) {
4570                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4571                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4572                 return false;
4573         }
4574
4575         if (cursor_wm > cursor->max_wm) {
4576                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4577                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4578                 return false;
4579         }
4580
4581         if (!(fbc_wm || display_wm || cursor_wm)) {
4582                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4583                 return false;
4584         }
4585
4586         return true;
4587 }
4588
4589 /*
4590  * Compute watermark values of WM[1-3],
4591  */
4592 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4593                                   int latency_ns,
4594                                   const struct intel_watermark_params *display,
4595                                   const struct intel_watermark_params *cursor,
4596                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4597 {
4598         struct drm_crtc *crtc;
4599         unsigned long line_time_us;
4600         int hdisplay, htotal, pixel_size, clock;
4601         int line_count, line_size;
4602         int small, large;
4603         int entries;
4604
4605         if (!latency_ns) {
4606                 *fbc_wm = *display_wm = *cursor_wm = 0;
4607                 return false;
4608         }
4609
4610         crtc = intel_get_crtc_for_plane(dev, plane);
4611         hdisplay = crtc->mode.hdisplay;
4612         htotal = crtc->mode.htotal;
4613         clock = crtc->mode.clock;
4614         pixel_size = crtc->fb->bits_per_pixel / 8;
4615
4616         line_time_us = (htotal * 1000) / clock;
4617         line_count = (latency_ns / line_time_us + 1000) / 1000;
4618         line_size = hdisplay * pixel_size;
4619
4620         /* Use the minimum of the small and large buffer method for primary */
4621         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4622         large = line_count * line_size;
4623
4624         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4625         *display_wm = entries + display->guard_size;
4626
4627         /*
4628          * Spec says:
4629          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4630          */
4631         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4632
4633         /* calculate the self-refresh watermark for display cursor */
4634         entries = line_count * pixel_size * 64;
4635         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4636         *cursor_wm = entries + cursor->guard_size;
4637
4638         return ironlake_check_srwm(dev, level,
4639                                    *fbc_wm, *display_wm, *cursor_wm,
4640                                    display, cursor);
4641 }
4642
4643 static void ironlake_update_wm(struct drm_device *dev)
4644 {
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         int fbc_wm, plane_wm, cursor_wm;
4647         unsigned int enabled;
4648
4649         enabled = 0;
4650         if (g4x_compute_wm0(dev, 0,
4651                             &ironlake_display_wm_info,
4652                             ILK_LP0_PLANE_LATENCY,
4653                             &ironlake_cursor_wm_info,
4654                             ILK_LP0_CURSOR_LATENCY,
4655                             &plane_wm, &cursor_wm)) {
4656                 I915_WRITE(WM0_PIPEA_ILK,
4657                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4658                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4659                               " plane %d, " "cursor: %d\n",
4660                               plane_wm, cursor_wm);
4661                 enabled |= 1;
4662         }
4663
4664         if (g4x_compute_wm0(dev, 1,
4665                             &ironlake_display_wm_info,
4666                             ILK_LP0_PLANE_LATENCY,
4667                             &ironlake_cursor_wm_info,
4668                             ILK_LP0_CURSOR_LATENCY,
4669                             &plane_wm, &cursor_wm)) {
4670                 I915_WRITE(WM0_PIPEB_ILK,
4671                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4672                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4673                               " plane %d, cursor: %d\n",
4674                               plane_wm, cursor_wm);
4675                 enabled |= 2;
4676         }
4677
4678         /*
4679          * Calculate and update the self-refresh watermark only when one
4680          * display plane is used.
4681          */
4682         I915_WRITE(WM3_LP_ILK, 0);
4683         I915_WRITE(WM2_LP_ILK, 0);
4684         I915_WRITE(WM1_LP_ILK, 0);
4685
4686         if (!single_plane_enabled(enabled))
4687                 return;
4688         enabled = ffs(enabled) - 1;
4689
4690         /* WM1 */
4691         if (!ironlake_compute_srwm(dev, 1, enabled,
4692                                    ILK_READ_WM1_LATENCY() * 500,
4693                                    &ironlake_display_srwm_info,
4694                                    &ironlake_cursor_srwm_info,
4695                                    &fbc_wm, &plane_wm, &cursor_wm))
4696                 return;
4697
4698         I915_WRITE(WM1_LP_ILK,
4699                    WM1_LP_SR_EN |
4700                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4701                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4702                    (plane_wm << WM1_LP_SR_SHIFT) |
4703                    cursor_wm);
4704
4705         /* WM2 */
4706         if (!ironlake_compute_srwm(dev, 2, enabled,
4707                                    ILK_READ_WM2_LATENCY() * 500,
4708                                    &ironlake_display_srwm_info,
4709                                    &ironlake_cursor_srwm_info,
4710                                    &fbc_wm, &plane_wm, &cursor_wm))
4711                 return;
4712
4713         I915_WRITE(WM2_LP_ILK,
4714                    WM2_LP_EN |
4715                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4716                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4717                    (plane_wm << WM1_LP_SR_SHIFT) |
4718                    cursor_wm);
4719
4720         /*
4721          * WM3 is unsupported on ILK, probably because we don't have latency
4722          * data for that power state
4723          */
4724 }
4725
4726 void sandybridge_update_wm(struct drm_device *dev)
4727 {
4728         struct drm_i915_private *dev_priv = dev->dev_private;
4729         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4730         u32 val;
4731         int fbc_wm, plane_wm, cursor_wm;
4732         unsigned int enabled;
4733
4734         enabled = 0;
4735         if (g4x_compute_wm0(dev, 0,
4736                             &sandybridge_display_wm_info, latency,
4737                             &sandybridge_cursor_wm_info, latency,
4738                             &plane_wm, &cursor_wm)) {
4739                 val = I915_READ(WM0_PIPEA_ILK);
4740                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4741                 I915_WRITE(WM0_PIPEA_ILK, val |
4742                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4743                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4744                               " plane %d, " "cursor: %d\n",
4745                               plane_wm, cursor_wm);
4746                 enabled |= 1;
4747         }
4748
4749         if (g4x_compute_wm0(dev, 1,
4750                             &sandybridge_display_wm_info, latency,
4751                             &sandybridge_cursor_wm_info, latency,
4752                             &plane_wm, &cursor_wm)) {
4753                 val = I915_READ(WM0_PIPEB_ILK);
4754                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4755                 I915_WRITE(WM0_PIPEB_ILK, val |
4756                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4757                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4758                               " plane %d, cursor: %d\n",
4759                               plane_wm, cursor_wm);
4760                 enabled |= 2;
4761         }
4762
4763         /* IVB has 3 pipes */
4764         if (IS_IVYBRIDGE(dev) &&
4765             g4x_compute_wm0(dev, 2,
4766                             &sandybridge_display_wm_info, latency,
4767                             &sandybridge_cursor_wm_info, latency,
4768                             &plane_wm, &cursor_wm)) {
4769                 val = I915_READ(WM0_PIPEC_IVB);
4770                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4771                 I915_WRITE(WM0_PIPEC_IVB, val |
4772                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4773                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4774                               " plane %d, cursor: %d\n",
4775                               plane_wm, cursor_wm);
4776                 enabled |= 3;
4777         }
4778
4779         /*
4780          * Calculate and update the self-refresh watermark only when one
4781          * display plane is used.
4782          *
4783          * SNB support 3 levels of watermark.
4784          *
4785          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4786          * and disabled in the descending order
4787          *
4788          */
4789         I915_WRITE(WM3_LP_ILK, 0);
4790         I915_WRITE(WM2_LP_ILK, 0);
4791         I915_WRITE(WM1_LP_ILK, 0);
4792
4793         if (!single_plane_enabled(enabled) ||
4794             dev_priv->sprite_scaling_enabled)
4795                 return;
4796         enabled = ffs(enabled) - 1;
4797
4798         /* WM1 */
4799         if (!ironlake_compute_srwm(dev, 1, enabled,
4800                                    SNB_READ_WM1_LATENCY() * 500,
4801                                    &sandybridge_display_srwm_info,
4802                                    &sandybridge_cursor_srwm_info,
4803                                    &fbc_wm, &plane_wm, &cursor_wm))
4804                 return;
4805
4806         I915_WRITE(WM1_LP_ILK,
4807                    WM1_LP_SR_EN |
4808                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4809                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4810                    (plane_wm << WM1_LP_SR_SHIFT) |
4811                    cursor_wm);
4812
4813         /* WM2 */
4814         if (!ironlake_compute_srwm(dev, 2, enabled,
4815                                    SNB_READ_WM2_LATENCY() * 500,
4816                                    &sandybridge_display_srwm_info,
4817                                    &sandybridge_cursor_srwm_info,
4818                                    &fbc_wm, &plane_wm, &cursor_wm))
4819                 return;
4820
4821         I915_WRITE(WM2_LP_ILK,
4822                    WM2_LP_EN |
4823                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4824                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4825                    (plane_wm << WM1_LP_SR_SHIFT) |
4826                    cursor_wm);
4827
4828         /* WM3 */
4829         if (!ironlake_compute_srwm(dev, 3, enabled,
4830                                    SNB_READ_WM3_LATENCY() * 500,
4831                                    &sandybridge_display_srwm_info,
4832                                    &sandybridge_cursor_srwm_info,
4833                                    &fbc_wm, &plane_wm, &cursor_wm))
4834                 return;
4835
4836         I915_WRITE(WM3_LP_ILK,
4837                    WM3_LP_EN |
4838                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4839                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4840                    (plane_wm << WM1_LP_SR_SHIFT) |
4841                    cursor_wm);
4842 }
4843
4844 static bool
4845 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4846                               uint32_t sprite_width, int pixel_size,
4847                               const struct intel_watermark_params *display,
4848                               int display_latency_ns, int *sprite_wm)
4849 {
4850         struct drm_crtc *crtc;
4851         int clock;
4852         int entries, tlb_miss;
4853
4854         crtc = intel_get_crtc_for_plane(dev, plane);
4855         if (crtc->fb == NULL || !crtc->enabled) {
4856                 *sprite_wm = display->guard_size;
4857                 return false;
4858         }
4859
4860         clock = crtc->mode.clock;
4861
4862         /* Use the small buffer method to calculate the sprite watermark */
4863         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4864         tlb_miss = display->fifo_size*display->cacheline_size -
4865                 sprite_width * 8;
4866         if (tlb_miss > 0)
4867                 entries += tlb_miss;
4868         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4869         *sprite_wm = entries + display->guard_size;
4870         if (*sprite_wm > (int)display->max_wm)
4871                 *sprite_wm = display->max_wm;
4872
4873         return true;
4874 }
4875
4876 static bool
4877 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4878                                 uint32_t sprite_width, int pixel_size,
4879                                 const struct intel_watermark_params *display,
4880                                 int latency_ns, int *sprite_wm)
4881 {
4882         struct drm_crtc *crtc;
4883         unsigned long line_time_us;
4884         int clock;
4885         int line_count, line_size;
4886         int small, large;
4887         int entries;
4888
4889         if (!latency_ns) {
4890                 *sprite_wm = 0;
4891                 return false;
4892         }
4893
4894         crtc = intel_get_crtc_for_plane(dev, plane);
4895         clock = crtc->mode.clock;
4896
4897         line_time_us = (sprite_width * 1000) / clock;
4898         line_count = (latency_ns / line_time_us + 1000) / 1000;
4899         line_size = sprite_width * pixel_size;
4900
4901         /* Use the minimum of the small and large buffer method for primary */
4902         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4903         large = line_count * line_size;
4904
4905         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4906         *sprite_wm = entries + display->guard_size;
4907
4908         return *sprite_wm > 0x3ff ? false : true;
4909 }
4910
4911 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4912                                          uint32_t sprite_width, int pixel_size)
4913 {
4914         struct drm_i915_private *dev_priv = dev->dev_private;
4915         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4916         u32 val;
4917         int sprite_wm, reg;
4918         int ret;
4919
4920         switch (pipe) {
4921         case 0:
4922                 reg = WM0_PIPEA_ILK;
4923                 break;
4924         case 1:
4925                 reg = WM0_PIPEB_ILK;
4926                 break;
4927         case 2:
4928                 reg = WM0_PIPEC_IVB;
4929                 break;
4930         default:
4931                 return; /* bad pipe */
4932         }
4933
4934         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4935                                             &sandybridge_display_wm_info,
4936                                             latency, &sprite_wm);
4937         if (!ret) {
4938                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4939                               pipe);
4940                 return;
4941         }
4942
4943         val = I915_READ(reg);
4944         val &= ~WM0_PIPE_SPRITE_MASK;
4945         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4946         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4947
4948
4949         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4950                                               pixel_size,
4951                                               &sandybridge_display_srwm_info,
4952                                               SNB_READ_WM1_LATENCY() * 500,
4953                                               &sprite_wm);
4954         if (!ret) {
4955                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4956                               pipe);
4957                 return;
4958         }
4959         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4960
4961         /* Only IVB has two more LP watermarks for sprite */
4962         if (!IS_IVYBRIDGE(dev))
4963                 return;
4964
4965         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4966                                               pixel_size,
4967                                               &sandybridge_display_srwm_info,
4968                                               SNB_READ_WM2_LATENCY() * 500,
4969                                               &sprite_wm);
4970         if (!ret) {
4971                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4972                               pipe);
4973                 return;
4974         }
4975         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4976
4977         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4978                                               pixel_size,
4979                                               &sandybridge_display_srwm_info,
4980                                               SNB_READ_WM3_LATENCY() * 500,
4981                                               &sprite_wm);
4982         if (!ret) {
4983                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4984                               pipe);
4985                 return;
4986         }
4987         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4988 }
4989
4990 /**
4991  * intel_update_watermarks - update FIFO watermark values based on current modes
4992  *
4993  * Calculate watermark values for the various WM regs based on current mode
4994  * and plane configuration.
4995  *
4996  * There are several cases to deal with here:
4997  *   - normal (i.e. non-self-refresh)
4998  *   - self-refresh (SR) mode
4999  *   - lines are large relative to FIFO size (buffer can hold up to 2)
5000  *   - lines are small relative to FIFO size (buffer can hold more than 2
5001  *     lines), so need to account for TLB latency
5002  *
5003  *   The normal calculation is:
5004  *     watermark = dotclock * bytes per pixel * latency
5005  *   where latency is platform & configuration dependent (we assume pessimal
5006  *   values here).
5007  *
5008  *   The SR calculation is:
5009  *     watermark = (trunc(latency/line time)+1) * surface width *
5010  *       bytes per pixel
5011  *   where
5012  *     line time = htotal / dotclock
5013  *     surface width = hdisplay for normal plane and 64 for cursor
5014  *   and latency is assumed to be high, as above.
5015  *
5016  * The final value programmed to the register should always be rounded up,
5017  * and include an extra 2 entries to account for clock crossings.
5018  *
5019  * We don't use the sprite, so we can ignore that.  And on Crestline we have
5020  * to set the non-SR watermarks to 8.
5021  */
5022 static void intel_update_watermarks(struct drm_device *dev)
5023 {
5024         struct drm_i915_private *dev_priv = dev->dev_private;
5025
5026         if (dev_priv->display.update_wm)
5027                 dev_priv->display.update_wm(dev);
5028 }
5029
5030 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
5031                                     uint32_t sprite_width, int pixel_size)
5032 {
5033         struct drm_i915_private *dev_priv = dev->dev_private;
5034
5035         if (dev_priv->display.update_sprite_wm)
5036                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
5037                                                    pixel_size);
5038 }
5039
5040 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5041 {
5042         if (i915_panel_use_ssc >= 0)
5043                 return i915_panel_use_ssc != 0;
5044         return dev_priv->lvds_use_ssc
5045                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5046 }
5047
5048 /**
5049  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
5050  * @crtc: CRTC structure
5051  * @mode: requested mode
5052  *
5053  * A pipe may be connected to one or more outputs.  Based on the depth of the
5054  * attached framebuffer, choose a good color depth to use on the pipe.
5055  *
5056  * If possible, match the pipe depth to the fb depth.  In some cases, this
5057  * isn't ideal, because the connected output supports a lesser or restricted
5058  * set of depths.  Resolve that here:
5059  *    LVDS typically supports only 6bpc, so clamp down in that case
5060  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
5061  *    Displays may support a restricted set as well, check EDID and clamp as
5062  *      appropriate.
5063  *    DP may want to dither down to 6bpc to fit larger modes
5064  *
5065  * RETURNS:
5066  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
5067  * true if they don't match).
5068  */
5069 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
5070                                          unsigned int *pipe_bpp,
5071                                          struct drm_display_mode *mode)
5072 {
5073         struct drm_device *dev = crtc->dev;
5074         struct drm_i915_private *dev_priv = dev->dev_private;
5075         struct drm_encoder *encoder;
5076         struct drm_connector *connector;
5077         unsigned int display_bpc = UINT_MAX, bpc;
5078
5079         /* Walk the encoders & connectors on this crtc, get min bpc */
5080         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5081                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5082
5083                 if (encoder->crtc != crtc)
5084                         continue;
5085
5086                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5087                         unsigned int lvds_bpc;
5088
5089                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5090                             LVDS_A3_POWER_UP)
5091                                 lvds_bpc = 8;
5092                         else
5093                                 lvds_bpc = 6;
5094
5095                         if (lvds_bpc < display_bpc) {
5096                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5097                                 display_bpc = lvds_bpc;
5098                         }
5099                         continue;
5100                 }
5101
5102                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5103                         /* Use VBT settings if we have an eDP panel */
5104                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5105
5106                         if (edp_bpc < display_bpc) {
5107                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5108                                 display_bpc = edp_bpc;
5109                         }
5110                         continue;
5111                 }
5112
5113                 /* Not one of the known troublemakers, check the EDID */
5114                 list_for_each_entry(connector, &dev->mode_config.connector_list,
5115                                     head) {
5116                         if (connector->encoder != encoder)
5117                                 continue;
5118
5119                         /* Don't use an invalid EDID bpc value */
5120                         if (connector->display_info.bpc &&
5121                             connector->display_info.bpc < display_bpc) {
5122                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5123                                 display_bpc = connector->display_info.bpc;
5124                         }
5125                 }
5126
5127                 /*
5128                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5129                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5130                  */
5131                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5132                         if (display_bpc > 8 && display_bpc < 12) {
5133                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5134                                 display_bpc = 12;
5135                         } else {
5136                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5137                                 display_bpc = 8;
5138                         }
5139                 }
5140         }
5141
5142         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5143                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5144                 display_bpc = 6;
5145         }
5146
5147         /*
5148          * We could just drive the pipe at the highest bpc all the time and
5149          * enable dithering as needed, but that costs bandwidth.  So choose
5150          * the minimum value that expresses the full color range of the fb but
5151          * also stays within the max display bpc discovered above.
5152          */
5153
5154         switch (crtc->fb->depth) {
5155         case 8:
5156                 bpc = 8; /* since we go through a colormap */
5157                 break;
5158         case 15:
5159         case 16:
5160                 bpc = 6; /* min is 18bpp */
5161                 break;
5162         case 24:
5163                 bpc = 8;
5164                 break;
5165         case 30:
5166                 bpc = 10;
5167                 break;
5168         case 48:
5169                 bpc = 12;
5170                 break;
5171         default:
5172                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5173                 bpc = min((unsigned int)8, display_bpc);
5174                 break;
5175         }
5176
5177         display_bpc = min(display_bpc, bpc);
5178
5179         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5180                       bpc, display_bpc);
5181
5182         *pipe_bpp = display_bpc * 3;
5183
5184         return display_bpc != bpc;
5185 }
5186
5187 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5188 {
5189         struct drm_device *dev = crtc->dev;
5190         struct drm_i915_private *dev_priv = dev->dev_private;
5191         int refclk;
5192
5193         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5194             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5195                 refclk = dev_priv->lvds_ssc_freq * 1000;
5196                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5197                               refclk / 1000);
5198         } else if (!IS_GEN2(dev)) {
5199                 refclk = 96000;
5200         } else {
5201                 refclk = 48000;
5202         }
5203
5204         return refclk;
5205 }
5206
5207 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5208                                       intel_clock_t *clock)
5209 {
5210         /* SDVO TV has fixed PLL values depend on its clock range,
5211            this mirrors vbios setting. */
5212         if (adjusted_mode->clock >= 100000
5213             && adjusted_mode->clock < 140500) {
5214                 clock->p1 = 2;
5215                 clock->p2 = 10;
5216                 clock->n = 3;
5217                 clock->m1 = 16;
5218                 clock->m2 = 8;
5219         } else if (adjusted_mode->clock >= 140500
5220                    && adjusted_mode->clock <= 200000) {
5221                 clock->p1 = 1;
5222                 clock->p2 = 10;
5223                 clock->n = 6;
5224                 clock->m1 = 12;
5225                 clock->m2 = 8;
5226         }
5227 }
5228
5229 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5230                                      intel_clock_t *clock,
5231                                      intel_clock_t *reduced_clock)
5232 {
5233         struct drm_device *dev = crtc->dev;
5234         struct drm_i915_private *dev_priv = dev->dev_private;
5235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236         int pipe = intel_crtc->pipe;
5237         u32 fp, fp2 = 0;
5238
5239         if (IS_PINEVIEW(dev)) {
5240                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5241                 if (reduced_clock)
5242                         fp2 = (1 << reduced_clock->n) << 16 |
5243                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5244         } else {
5245                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5246                 if (reduced_clock)
5247                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5248                                 reduced_clock->m2;
5249         }
5250
5251         I915_WRITE(FP0(pipe), fp);
5252
5253         intel_crtc->lowfreq_avail = false;
5254         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5255             reduced_clock && i915_powersave) {
5256                 I915_WRITE(FP1(pipe), fp2);
5257                 intel_crtc->lowfreq_avail = true;
5258         } else {
5259                 I915_WRITE(FP1(pipe), fp);
5260         }
5261 }
5262
5263 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5264                               struct drm_display_mode *adjusted_mode)
5265 {
5266         struct drm_device *dev = crtc->dev;
5267         struct drm_i915_private *dev_priv = dev->dev_private;
5268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5269         int pipe = intel_crtc->pipe;
5270         u32 temp, lvds_sync = 0;
5271
5272         temp = I915_READ(LVDS);
5273         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5274         if (pipe == 1) {
5275                 temp |= LVDS_PIPEB_SELECT;
5276         } else {
5277                 temp &= ~LVDS_PIPEB_SELECT;
5278         }
5279         /* set the corresponsding LVDS_BORDER bit */
5280         temp |= dev_priv->lvds_border_bits;
5281         /* Set the B0-B3 data pairs corresponding to whether we're going to
5282          * set the DPLLs for dual-channel mode or not.
5283          */
5284         if (clock->p2 == 7)
5285                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5286         else
5287                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5288
5289         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5290          * appropriately here, but we need to look more thoroughly into how
5291          * panels behave in the two modes.
5292          */
5293         /* set the dithering flag on LVDS as needed */
5294         if (INTEL_INFO(dev)->gen >= 4) {
5295                 if (dev_priv->lvds_dither)
5296                         temp |= LVDS_ENABLE_DITHER;
5297                 else
5298                         temp &= ~LVDS_ENABLE_DITHER;
5299         }
5300         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5301                 lvds_sync |= LVDS_HSYNC_POLARITY;
5302         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5303                 lvds_sync |= LVDS_VSYNC_POLARITY;
5304         if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5305             != lvds_sync) {
5306                 char flags[2] = "-+";
5307                 DRM_INFO("Changing LVDS panel from "
5308                          "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5309                          flags[!(temp & LVDS_HSYNC_POLARITY)],
5310                          flags[!(temp & LVDS_VSYNC_POLARITY)],
5311                          flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5312                          flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5313                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5314                 temp |= lvds_sync;
5315         }
5316         I915_WRITE(LVDS, temp);
5317 }
5318
5319 static void i9xx_update_pll(struct drm_crtc *crtc,
5320                             struct drm_display_mode *mode,
5321                             struct drm_display_mode *adjusted_mode,
5322                             intel_clock_t *clock, intel_clock_t *reduced_clock,
5323                             int num_connectors)
5324 {
5325         struct drm_device *dev = crtc->dev;
5326         struct drm_i915_private *dev_priv = dev->dev_private;
5327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5328         int pipe = intel_crtc->pipe;
5329         u32 dpll;
5330         bool is_sdvo;
5331
5332         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5333                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5334
5335         dpll = DPLL_VGA_MODE_DIS;
5336
5337         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5338                 dpll |= DPLLB_MODE_LVDS;
5339         else
5340                 dpll |= DPLLB_MODE_DAC_SERIAL;
5341         if (is_sdvo) {
5342                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5343                 if (pixel_multiplier > 1) {
5344                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5345                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5346                 }
5347                 dpll |= DPLL_DVO_HIGH_SPEED;
5348         }
5349         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5350                 dpll |= DPLL_DVO_HIGH_SPEED;
5351
5352         /* compute bitmask from p1 value */
5353         if (IS_PINEVIEW(dev))
5354                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5355         else {
5356                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5357                 if (IS_G4X(dev) && reduced_clock)
5358                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5359         }
5360         switch (clock->p2) {
5361         case 5:
5362                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5363                 break;
5364         case 7:
5365                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5366                 break;
5367         case 10:
5368                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5369                 break;
5370         case 14:
5371                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5372                 break;
5373         }
5374         if (INTEL_INFO(dev)->gen >= 4)
5375                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5376
5377         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5378                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5379         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5380                 /* XXX: just matching BIOS for now */
5381                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5382                 dpll |= 3;
5383         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5384                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5385                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5386         else
5387                 dpll |= PLL_REF_INPUT_DREFCLK;
5388
5389         dpll |= DPLL_VCO_ENABLE;
5390         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5391         POSTING_READ(DPLL(pipe));
5392         udelay(150);
5393
5394         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5395          * This is an exception to the general rule that mode_set doesn't turn
5396          * things on.
5397          */
5398         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5399                 intel_update_lvds(crtc, clock, adjusted_mode);
5400
5401         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5402                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5403
5404         I915_WRITE(DPLL(pipe), dpll);
5405
5406         /* Wait for the clocks to stabilize. */
5407         POSTING_READ(DPLL(pipe));
5408         udelay(150);
5409
5410         if (INTEL_INFO(dev)->gen >= 4) {
5411                 u32 temp = 0;
5412                 if (is_sdvo) {
5413                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5414                         if (temp > 1)
5415                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5416                         else
5417                                 temp = 0;
5418                 }
5419                 I915_WRITE(DPLL_MD(pipe), temp);
5420         } else {
5421                 /* The pixel multiplier can only be updated once the
5422                  * DPLL is enabled and the clocks are stable.
5423                  *
5424                  * So write it again.
5425                  */
5426                 I915_WRITE(DPLL(pipe), dpll);
5427         }
5428 }
5429
5430 static void i8xx_update_pll(struct drm_crtc *crtc,
5431                             struct drm_display_mode *adjusted_mode,
5432                             intel_clock_t *clock,
5433                             int num_connectors)
5434 {
5435         struct drm_device *dev = crtc->dev;
5436         struct drm_i915_private *dev_priv = dev->dev_private;
5437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5438         int pipe = intel_crtc->pipe;
5439         u32 dpll;
5440
5441         dpll = DPLL_VGA_MODE_DIS;
5442
5443         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
5444                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5445         } else {
5446                 if (clock->p1 == 2)
5447                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5448                 else
5449                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5450                 if (clock->p2 == 4)
5451                         dpll |= PLL_P2_DIVIDE_BY_4;
5452         }
5453
5454         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5455                 /* XXX: just matching BIOS for now */
5456                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5457                 dpll |= 3;
5458         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5459                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5460                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5461         else
5462                 dpll |= PLL_REF_INPUT_DREFCLK;
5463
5464         dpll |= DPLL_VCO_ENABLE;
5465         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5466         POSTING_READ(DPLL(pipe));
5467         udelay(150);
5468
5469         I915_WRITE(DPLL(pipe), dpll);
5470
5471         /* Wait for the clocks to stabilize. */
5472         POSTING_READ(DPLL(pipe));
5473         udelay(150);
5474
5475         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5476          * This is an exception to the general rule that mode_set doesn't turn
5477          * things on.
5478          */
5479         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5480                 intel_update_lvds(crtc, clock, adjusted_mode);
5481
5482         /* The pixel multiplier can only be updated once the
5483          * DPLL is enabled and the clocks are stable.
5484          *
5485          * So write it again.
5486          */
5487         I915_WRITE(DPLL(pipe), dpll);
5488 }
5489
5490 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5491                               struct drm_display_mode *mode,
5492                               struct drm_display_mode *adjusted_mode,
5493                               int x, int y,
5494                               struct drm_framebuffer *old_fb)
5495 {
5496         struct drm_device *dev = crtc->dev;
5497         struct drm_i915_private *dev_priv = dev->dev_private;
5498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5499         int pipe = intel_crtc->pipe;
5500         int plane = intel_crtc->plane;
5501         int refclk, num_connectors = 0;
5502         intel_clock_t clock, reduced_clock;
5503         u32 dspcntr, pipeconf, vsyncshift;
5504         bool ok, has_reduced_clock = false, is_sdvo = false;
5505         bool is_lvds = false, is_tv = false, is_dp = false;
5506         struct drm_mode_config *mode_config = &dev->mode_config;
5507         struct intel_encoder *encoder;
5508         const intel_limit_t *limit;
5509         int ret;
5510
5511         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5512                 if (encoder->base.crtc != crtc)
5513                         continue;
5514
5515                 switch (encoder->type) {
5516                 case INTEL_OUTPUT_LVDS:
5517                         is_lvds = true;
5518                         break;
5519                 case INTEL_OUTPUT_SDVO:
5520                 case INTEL_OUTPUT_HDMI:
5521                         is_sdvo = true;
5522                         if (encoder->needs_tv_clock)
5523                                 is_tv = true;
5524                         break;
5525                 case INTEL_OUTPUT_TVOUT:
5526                         is_tv = true;
5527                         break;
5528                 case INTEL_OUTPUT_DISPLAYPORT:
5529                         is_dp = true;
5530                         break;
5531                 }
5532
5533                 num_connectors++;
5534         }
5535
5536         refclk = i9xx_get_refclk(crtc, num_connectors);
5537
5538         /*
5539          * Returns a set of divisors for the desired target clock with the given
5540          * refclk, or FALSE.  The returned values represent the clock equation:
5541          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5542          */
5543         limit = intel_limit(crtc, refclk);
5544         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5545                              &clock);
5546         if (!ok) {
5547                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5548                 return -EINVAL;
5549         }
5550
5551         /* Ensure that the cursor is valid for the new mode before changing... */
5552         intel_crtc_update_cursor(crtc, true);
5553
5554         if (is_lvds && dev_priv->lvds_downclock_avail) {
5555                 /*
5556                  * Ensure we match the reduced clock's P to the target clock.
5557                  * If the clocks don't match, we can't switch the display clock
5558                  * by using the FP0/FP1. In such case we will disable the LVDS
5559                  * downclock feature.
5560                 */
5561                 has_reduced_clock = limit->find_pll(limit, crtc,
5562                                                     dev_priv->lvds_downclock,
5563                                                     refclk,
5564                                                     &clock,
5565                                                     &reduced_clock);
5566         }
5567
5568         if (is_sdvo && is_tv)
5569                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5570
5571         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5572                                  &reduced_clock : NULL);
5573
5574         if (IS_GEN2(dev))
5575                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
5576         else
5577                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
5578                                 has_reduced_clock ? &reduced_clock : NULL,
5579                                 num_connectors);
5580
5581         /* setup pipeconf */
5582         pipeconf = I915_READ(PIPECONF(pipe));
5583
5584         /* Set up the display plane register */
5585         dspcntr = DISPPLANE_GAMMA_ENABLE;
5586
5587         if (pipe == 0)
5588                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5589         else
5590                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5591
5592         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5593                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5594                  * core speed.
5595                  *
5596                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5597                  * pipe == 0 check?
5598                  */
5599                 if (mode->clock >
5600                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5601                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5602                 else
5603                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5604         }
5605
5606         /* default to 8bpc */
5607         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5608         if (is_dp) {
5609                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5610                         pipeconf |= PIPECONF_BPP_6 |
5611                                     PIPECONF_DITHER_EN |
5612                                     PIPECONF_DITHER_TYPE_SP;
5613                 }
5614         }
5615
5616         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5617         drm_mode_debug_printmodeline(mode);
5618
5619         if (HAS_PIPE_CXSR(dev)) {
5620                 if (intel_crtc->lowfreq_avail) {
5621                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5622                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5623                 } else {
5624                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5625                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5626                 }
5627         }
5628
5629         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5630         if (!IS_GEN2(dev) &&
5631             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5632                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5633                 /* the chip adds 2 halflines automatically */
5634                 adjusted_mode->crtc_vtotal -= 1;
5635                 adjusted_mode->crtc_vblank_end -= 1;
5636                 vsyncshift = adjusted_mode->crtc_hsync_start
5637                              - adjusted_mode->crtc_htotal/2;
5638         } else {
5639                 pipeconf |= PIPECONF_PROGRESSIVE;
5640                 vsyncshift = 0;
5641         }
5642
5643         if (!IS_GEN3(dev))
5644                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5645
5646         I915_WRITE(HTOTAL(pipe),
5647                    (adjusted_mode->crtc_hdisplay - 1) |
5648                    ((adjusted_mode->crtc_htotal - 1) << 16));
5649         I915_WRITE(HBLANK(pipe),
5650                    (adjusted_mode->crtc_hblank_start - 1) |
5651                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5652         I915_WRITE(HSYNC(pipe),
5653                    (adjusted_mode->crtc_hsync_start - 1) |
5654                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5655
5656         I915_WRITE(VTOTAL(pipe),
5657                    (adjusted_mode->crtc_vdisplay - 1) |
5658                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5659         I915_WRITE(VBLANK(pipe),
5660                    (adjusted_mode->crtc_vblank_start - 1) |
5661                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5662         I915_WRITE(VSYNC(pipe),
5663                    (adjusted_mode->crtc_vsync_start - 1) |
5664                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5665
5666         /* pipesrc and dspsize control the size that is scaled from,
5667          * which should always be the user's requested size.
5668          */
5669         I915_WRITE(DSPSIZE(plane),
5670                    ((mode->vdisplay - 1) << 16) |
5671                    (mode->hdisplay - 1));
5672         I915_WRITE(DSPPOS(plane), 0);
5673         I915_WRITE(PIPESRC(pipe),
5674                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5675
5676         I915_WRITE(PIPECONF(pipe), pipeconf);
5677         POSTING_READ(PIPECONF(pipe));
5678         intel_enable_pipe(dev_priv, pipe, false);
5679
5680         intel_wait_for_vblank(dev, pipe);
5681
5682         I915_WRITE(DSPCNTR(plane), dspcntr);
5683         POSTING_READ(DSPCNTR(plane));
5684         intel_enable_plane(dev_priv, plane, pipe);
5685
5686         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5687
5688         intel_update_watermarks(dev);
5689
5690         return ret;
5691 }
5692
5693 /*
5694  * Initialize reference clocks when the driver loads
5695  */
5696 void ironlake_init_pch_refclk(struct drm_device *dev)
5697 {
5698         struct drm_i915_private *dev_priv = dev->dev_private;
5699         struct drm_mode_config *mode_config = &dev->mode_config;
5700         struct intel_encoder *encoder;
5701         u32 temp;
5702         bool has_lvds = false;
5703         bool has_cpu_edp = false;
5704         bool has_pch_edp = false;
5705         bool has_panel = false;
5706         bool has_ck505 = false;
5707         bool can_ssc = false;
5708
5709         /* We need to take the global config into account */
5710         list_for_each_entry(encoder, &mode_config->encoder_list,
5711                             base.head) {
5712                 switch (encoder->type) {
5713                 case INTEL_OUTPUT_LVDS:
5714                         has_panel = true;
5715                         has_lvds = true;
5716                         break;
5717                 case INTEL_OUTPUT_EDP:
5718                         has_panel = true;
5719                         if (intel_encoder_is_pch_edp(&encoder->base))
5720                                 has_pch_edp = true;
5721                         else
5722                                 has_cpu_edp = true;
5723                         break;
5724                 }
5725         }
5726
5727         if (HAS_PCH_IBX(dev)) {
5728                 has_ck505 = dev_priv->display_clock_mode;
5729                 can_ssc = has_ck505;
5730         } else {
5731                 has_ck505 = false;
5732                 can_ssc = true;
5733         }
5734
5735         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5736                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5737                       has_ck505);
5738
5739         /* Ironlake: try to setup display ref clock before DPLL
5740          * enabling. This is only under driver's control after
5741          * PCH B stepping, previous chipset stepping should be
5742          * ignoring this setting.
5743          */
5744         temp = I915_READ(PCH_DREF_CONTROL);
5745         /* Always enable nonspread source */
5746         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5747
5748         if (has_ck505)
5749                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5750         else
5751                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5752
5753         if (has_panel) {
5754                 temp &= ~DREF_SSC_SOURCE_MASK;
5755                 temp |= DREF_SSC_SOURCE_ENABLE;
5756
5757                 /* SSC must be turned on before enabling the CPU output  */
5758                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5759                         DRM_DEBUG_KMS("Using SSC on panel\n");
5760                         temp |= DREF_SSC1_ENABLE;
5761                 }
5762
5763                 /* Get SSC going before enabling the outputs */
5764                 I915_WRITE(PCH_DREF_CONTROL, temp);
5765                 POSTING_READ(PCH_DREF_CONTROL);
5766                 udelay(200);
5767
5768                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5769
5770                 /* Enable CPU source on CPU attached eDP */
5771                 if (has_cpu_edp) {
5772                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5773                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5774                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5775                         }
5776                         else
5777                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5778                 } else
5779                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5780
5781                 I915_WRITE(PCH_DREF_CONTROL, temp);
5782                 POSTING_READ(PCH_DREF_CONTROL);
5783                 udelay(200);
5784         } else {
5785                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5786
5787                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5788
5789                 /* Turn off CPU output */
5790                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5791
5792                 I915_WRITE(PCH_DREF_CONTROL, temp);
5793                 POSTING_READ(PCH_DREF_CONTROL);
5794                 udelay(200);
5795
5796                 /* Turn off the SSC source */
5797                 temp &= ~DREF_SSC_SOURCE_MASK;
5798                 temp |= DREF_SSC_SOURCE_DISABLE;
5799
5800                 /* Turn off SSC1 */
5801                 temp &= ~ DREF_SSC1_ENABLE;
5802
5803                 I915_WRITE(PCH_DREF_CONTROL, temp);
5804                 POSTING_READ(PCH_DREF_CONTROL);
5805                 udelay(200);
5806         }
5807 }
5808
5809 static int ironlake_get_refclk(struct drm_crtc *crtc)
5810 {
5811         struct drm_device *dev = crtc->dev;
5812         struct drm_i915_private *dev_priv = dev->dev_private;
5813         struct intel_encoder *encoder;
5814         struct drm_mode_config *mode_config = &dev->mode_config;
5815         struct intel_encoder *edp_encoder = NULL;
5816         int num_connectors = 0;
5817         bool is_lvds = false;
5818
5819         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5820                 if (encoder->base.crtc != crtc)
5821                         continue;
5822
5823                 switch (encoder->type) {
5824                 case INTEL_OUTPUT_LVDS:
5825                         is_lvds = true;
5826                         break;
5827                 case INTEL_OUTPUT_EDP:
5828                         edp_encoder = encoder;
5829                         break;
5830                 }
5831                 num_connectors++;
5832         }
5833
5834         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5835                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5836                               dev_priv->lvds_ssc_freq);
5837                 return dev_priv->lvds_ssc_freq * 1000;
5838         }
5839
5840         return 120000;
5841 }
5842
5843 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5844                                   struct drm_display_mode *mode,
5845                                   struct drm_display_mode *adjusted_mode,
5846                                   int x, int y,
5847                                   struct drm_framebuffer *old_fb)
5848 {
5849         struct drm_device *dev = crtc->dev;
5850         struct drm_i915_private *dev_priv = dev->dev_private;
5851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5852         int pipe = intel_crtc->pipe;
5853         int plane = intel_crtc->plane;
5854         int refclk, num_connectors = 0;
5855         intel_clock_t clock, reduced_clock;
5856         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5857         bool ok, has_reduced_clock = false, is_sdvo = false;
5858         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5859         struct intel_encoder *has_edp_encoder = NULL;
5860         struct drm_mode_config *mode_config = &dev->mode_config;
5861         struct intel_encoder *encoder;
5862         const intel_limit_t *limit;
5863         int ret;
5864         struct fdi_m_n m_n = {0};
5865         u32 temp;
5866         u32 lvds_sync = 0;
5867         int target_clock, pixel_multiplier, lane, link_bw, factor;
5868         unsigned int pipe_bpp;
5869         bool dither;
5870
5871         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5872                 if (encoder->base.crtc != crtc)
5873                         continue;
5874
5875                 switch (encoder->type) {
5876                 case INTEL_OUTPUT_LVDS:
5877                         is_lvds = true;
5878                         break;
5879                 case INTEL_OUTPUT_SDVO:
5880                 case INTEL_OUTPUT_HDMI:
5881                         is_sdvo = true;
5882                         if (encoder->needs_tv_clock)
5883                                 is_tv = true;
5884                         break;
5885                 case INTEL_OUTPUT_TVOUT:
5886                         is_tv = true;
5887                         break;
5888                 case INTEL_OUTPUT_ANALOG:
5889                         is_crt = true;
5890                         break;
5891                 case INTEL_OUTPUT_DISPLAYPORT:
5892                         is_dp = true;
5893                         break;
5894                 case INTEL_OUTPUT_EDP:
5895                         has_edp_encoder = encoder;
5896                         break;
5897                 }
5898
5899                 num_connectors++;
5900         }
5901
5902         refclk = ironlake_get_refclk(crtc);
5903
5904         /*
5905          * Returns a set of divisors for the desired target clock with the given
5906          * refclk, or FALSE.  The returned values represent the clock equation:
5907          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5908          */
5909         limit = intel_limit(crtc, refclk);
5910         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5911                              &clock);
5912         if (!ok) {
5913                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5914                 return -EINVAL;
5915         }
5916
5917         /* Ensure that the cursor is valid for the new mode before changing... */
5918         intel_crtc_update_cursor(crtc, true);
5919
5920         if (is_lvds && dev_priv->lvds_downclock_avail) {
5921                 /*
5922                  * Ensure we match the reduced clock's P to the target clock.
5923                  * If the clocks don't match, we can't switch the display clock
5924                  * by using the FP0/FP1. In such case we will disable the LVDS
5925                  * downclock feature.
5926                 */
5927                 has_reduced_clock = limit->find_pll(limit, crtc,
5928                                                     dev_priv->lvds_downclock,
5929                                                     refclk,
5930                                                     &clock,
5931                                                     &reduced_clock);
5932         }
5933         /* SDVO TV has fixed PLL values depend on its clock range,
5934            this mirrors vbios setting. */
5935         if (is_sdvo && is_tv) {
5936                 if (adjusted_mode->clock >= 100000
5937                     && adjusted_mode->clock < 140500) {
5938                         clock.p1 = 2;
5939                         clock.p2 = 10;
5940                         clock.n = 3;
5941                         clock.m1 = 16;
5942                         clock.m2 = 8;
5943                 } else if (adjusted_mode->clock >= 140500
5944                            && adjusted_mode->clock <= 200000) {
5945                         clock.p1 = 1;
5946                         clock.p2 = 10;
5947                         clock.n = 6;
5948                         clock.m1 = 12;
5949                         clock.m2 = 8;
5950                 }
5951         }
5952
5953         /* FDI link */
5954         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5955         lane = 0;
5956         /* CPU eDP doesn't require FDI link, so just set DP M/N
5957            according to current link config */
5958         if (has_edp_encoder &&
5959             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5960                 target_clock = mode->clock;
5961                 intel_edp_link_config(has_edp_encoder,
5962                                       &lane, &link_bw);
5963         } else {
5964                 /* [e]DP over FDI requires target mode clock
5965                    instead of link clock */
5966                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5967                         target_clock = mode->clock;
5968                 else
5969                         target_clock = adjusted_mode->clock;
5970
5971                 /* FDI is a binary signal running at ~2.7GHz, encoding
5972                  * each output octet as 10 bits. The actual frequency
5973                  * is stored as a divider into a 100MHz clock, and the
5974                  * mode pixel clock is stored in units of 1KHz.
5975                  * Hence the bw of each lane in terms of the mode signal
5976                  * is:
5977                  */
5978                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5979         }
5980
5981         /* determine panel color depth */
5982         temp = I915_READ(PIPECONF(pipe));
5983         temp &= ~PIPE_BPC_MASK;
5984         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5985         switch (pipe_bpp) {
5986         case 18:
5987                 temp |= PIPE_6BPC;
5988                 break;
5989         case 24:
5990                 temp |= PIPE_8BPC;
5991                 break;
5992         case 30:
5993                 temp |= PIPE_10BPC;
5994                 break;
5995         case 36:
5996                 temp |= PIPE_12BPC;
5997                 break;
5998         default:
5999                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
6000                         pipe_bpp);
6001                 temp |= PIPE_8BPC;
6002                 pipe_bpp = 24;
6003                 break;
6004         }
6005
6006         intel_crtc->bpp = pipe_bpp;
6007         I915_WRITE(PIPECONF(pipe), temp);
6008
6009         if (!lane) {
6010                 /*
6011                  * Account for spread spectrum to avoid
6012                  * oversubscribing the link. Max center spread
6013                  * is 2.5%; use 5% for safety's sake.
6014                  */
6015                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
6016                 lane = bps / (link_bw * 8) + 1;
6017         }
6018
6019         intel_crtc->fdi_lanes = lane;
6020
6021         if (pixel_multiplier > 1)
6022                 link_bw *= pixel_multiplier;
6023         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
6024                              &m_n);
6025
6026         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
6027         if (has_reduced_clock)
6028                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
6029                         reduced_clock.m2;
6030
6031         /* Enable autotuning of the PLL clock (if permissible) */
6032         factor = 21;
6033         if (is_lvds) {
6034                 if ((intel_panel_use_ssc(dev_priv) &&
6035                      dev_priv->lvds_ssc_freq == 100) ||
6036                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
6037                         factor = 25;
6038         } else if (is_sdvo && is_tv)
6039                 factor = 20;
6040
6041         if (clock.m < factor * clock.n)
6042                 fp |= FP_CB_TUNE;
6043
6044         dpll = 0;
6045
6046         if (is_lvds)
6047                 dpll |= DPLLB_MODE_LVDS;
6048         else
6049                 dpll |= DPLLB_MODE_DAC_SERIAL;
6050         if (is_sdvo) {
6051                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
6052                 if (pixel_multiplier > 1) {
6053                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6054                 }
6055                 dpll |= DPLL_DVO_HIGH_SPEED;
6056         }
6057         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
6058                 dpll |= DPLL_DVO_HIGH_SPEED;
6059
6060         /* compute bitmask from p1 value */
6061         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6062         /* also FPA1 */
6063         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6064
6065         switch (clock.p2) {
6066         case 5:
6067                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6068                 break;
6069         case 7:
6070                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6071                 break;
6072         case 10:
6073                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6074                 break;
6075         case 14:
6076                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6077                 break;
6078         }
6079
6080         if (is_sdvo && is_tv)
6081                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6082         else if (is_tv)
6083                 /* XXX: just matching BIOS for now */
6084                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
6085                 dpll |= 3;
6086         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6087                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6088         else
6089                 dpll |= PLL_REF_INPUT_DREFCLK;
6090
6091         /* setup pipeconf */
6092         pipeconf = I915_READ(PIPECONF(pipe));
6093
6094         /* Set up the display plane register */
6095         dspcntr = DISPPLANE_GAMMA_ENABLE;
6096
6097         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
6098         drm_mode_debug_printmodeline(mode);
6099
6100         /* PCH eDP needs FDI, but CPU eDP does not */
6101         if (!intel_crtc->no_pll) {
6102                 if (!has_edp_encoder ||
6103                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6104                         I915_WRITE(PCH_FP0(pipe), fp);
6105                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
6106
6107                         POSTING_READ(PCH_DPLL(pipe));
6108                         udelay(150);
6109                 }
6110         } else {
6111                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
6112                     fp == I915_READ(PCH_FP0(0))) {
6113                         intel_crtc->use_pll_a = true;
6114                         DRM_DEBUG_KMS("using pipe a dpll\n");
6115                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
6116                            fp == I915_READ(PCH_FP0(1))) {
6117                         intel_crtc->use_pll_a = false;
6118                         DRM_DEBUG_KMS("using pipe b dpll\n");
6119                 } else {
6120                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
6121                         return -EINVAL;
6122                 }
6123         }
6124
6125         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
6126          * This is an exception to the general rule that mode_set doesn't turn
6127          * things on.
6128          */
6129         if (is_lvds) {
6130                 temp = I915_READ(PCH_LVDS);
6131                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
6132                 if (HAS_PCH_CPT(dev)) {
6133                         temp &= ~PORT_TRANS_SEL_MASK;
6134                         temp |= PORT_TRANS_SEL_CPT(pipe);
6135                 } else {
6136                         if (pipe == 1)
6137                                 temp |= LVDS_PIPEB_SELECT;
6138                         else
6139                                 temp &= ~LVDS_PIPEB_SELECT;
6140                 }
6141
6142                 /* set the corresponsding LVDS_BORDER bit */
6143                 temp |= dev_priv->lvds_border_bits;
6144                 /* Set the B0-B3 data pairs corresponding to whether we're going to
6145                  * set the DPLLs for dual-channel mode or not.
6146                  */
6147                 if (clock.p2 == 7)
6148                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6149                 else
6150                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6151
6152                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6153                  * appropriately here, but we need to look more thoroughly into how
6154                  * panels behave in the two modes.
6155                  */
6156                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6157                         lvds_sync |= LVDS_HSYNC_POLARITY;
6158                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6159                         lvds_sync |= LVDS_VSYNC_POLARITY;
6160                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6161                     != lvds_sync) {
6162                         char flags[2] = "-+";
6163                         DRM_INFO("Changing LVDS panel from "
6164                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6165                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
6166                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
6167                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6168                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6169                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6170                         temp |= lvds_sync;
6171                 }
6172                 I915_WRITE(PCH_LVDS, temp);
6173         }
6174
6175         pipeconf &= ~PIPECONF_DITHER_EN;
6176         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
6177         if ((is_lvds && dev_priv->lvds_dither) || dither) {
6178                 pipeconf |= PIPECONF_DITHER_EN;
6179                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6180         }
6181         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6182                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6183         } else {
6184                 /* For non-DP output, clear any trans DP clock recovery setting.*/
6185                 I915_WRITE(TRANSDATA_M1(pipe), 0);
6186                 I915_WRITE(TRANSDATA_N1(pipe), 0);
6187                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6188                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6189         }
6190
6191         if (!intel_crtc->no_pll &&
6192             (!has_edp_encoder ||
6193              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6194                 I915_WRITE(PCH_DPLL(pipe), dpll);
6195
6196                 /* Wait for the clocks to stabilize. */
6197                 POSTING_READ(PCH_DPLL(pipe));
6198                 udelay(150);
6199
6200                 /* The pixel multiplier can only be updated once the
6201                  * DPLL is enabled and the clocks are stable.
6202                  *
6203                  * So write it again.
6204                  */
6205                 I915_WRITE(PCH_DPLL(pipe), dpll);
6206         }
6207
6208         intel_crtc->lowfreq_avail = false;
6209         if (!intel_crtc->no_pll) {
6210                 if (is_lvds && has_reduced_clock && i915_powersave) {
6211                         I915_WRITE(PCH_FP1(pipe), fp2);
6212                         intel_crtc->lowfreq_avail = true;
6213                         if (HAS_PIPE_CXSR(dev)) {
6214                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6215                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6216                         }
6217                 } else {
6218                         I915_WRITE(PCH_FP1(pipe), fp);
6219                         if (HAS_PIPE_CXSR(dev)) {
6220                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6221                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6222                         }
6223                 }
6224         }
6225
6226         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6227         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6228                 pipeconf |= PIPECONF_INTERLACED_ILK;
6229                 /* the chip adds 2 halflines automatically */
6230                 adjusted_mode->crtc_vtotal -= 1;
6231                 adjusted_mode->crtc_vblank_end -= 1;
6232                 I915_WRITE(VSYNCSHIFT(pipe),
6233                            adjusted_mode->crtc_hsync_start
6234                            - adjusted_mode->crtc_htotal/2);
6235         } else {
6236                 pipeconf |= PIPECONF_PROGRESSIVE;
6237                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6238         }
6239
6240         I915_WRITE(HTOTAL(pipe),
6241                    (adjusted_mode->crtc_hdisplay - 1) |
6242                    ((adjusted_mode->crtc_htotal - 1) << 16));
6243         I915_WRITE(HBLANK(pipe),
6244                    (adjusted_mode->crtc_hblank_start - 1) |
6245                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6246         I915_WRITE(HSYNC(pipe),
6247                    (adjusted_mode->crtc_hsync_start - 1) |
6248                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6249
6250         I915_WRITE(VTOTAL(pipe),
6251                    (adjusted_mode->crtc_vdisplay - 1) |
6252                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6253         I915_WRITE(VBLANK(pipe),
6254                    (adjusted_mode->crtc_vblank_start - 1) |
6255                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6256         I915_WRITE(VSYNC(pipe),
6257                    (adjusted_mode->crtc_vsync_start - 1) |
6258                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6259
6260         /* pipesrc controls the size that is scaled from, which should
6261          * always be the user's requested size.
6262          */
6263         I915_WRITE(PIPESRC(pipe),
6264                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6265
6266         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6267         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6268         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6269         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6270
6271         if (has_edp_encoder &&
6272             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6273                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6274         }
6275
6276         I915_WRITE(PIPECONF(pipe), pipeconf);
6277         POSTING_READ(PIPECONF(pipe));
6278
6279         intel_wait_for_vblank(dev, pipe);
6280
6281         I915_WRITE(DSPCNTR(plane), dspcntr);
6282         POSTING_READ(DSPCNTR(plane));
6283
6284         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6285
6286         intel_update_watermarks(dev);
6287
6288         return ret;
6289 }
6290
6291 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6292                                struct drm_display_mode *mode,
6293                                struct drm_display_mode *adjusted_mode,
6294                                int x, int y,
6295                                struct drm_framebuffer *old_fb)
6296 {
6297         struct drm_device *dev = crtc->dev;
6298         struct drm_i915_private *dev_priv = dev->dev_private;
6299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6300         int pipe = intel_crtc->pipe;
6301         int ret;
6302
6303         drm_vblank_pre_modeset(dev, pipe);
6304
6305         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6306                                               x, y, old_fb);
6307         drm_vblank_post_modeset(dev, pipe);
6308
6309         if (ret)
6310                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6311         else
6312                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6313
6314         return ret;
6315 }
6316
6317 static bool intel_eld_uptodate(struct drm_connector *connector,
6318                                int reg_eldv, uint32_t bits_eldv,
6319                                int reg_elda, uint32_t bits_elda,
6320                                int reg_edid)
6321 {
6322         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6323         uint8_t *eld = connector->eld;
6324         uint32_t i;
6325
6326         i = I915_READ(reg_eldv);
6327         i &= bits_eldv;
6328
6329         if (!eld[0])
6330                 return !i;
6331
6332         if (!i)
6333                 return false;
6334
6335         i = I915_READ(reg_elda);
6336         i &= ~bits_elda;
6337         I915_WRITE(reg_elda, i);
6338
6339         for (i = 0; i < eld[2]; i++)
6340                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6341                         return false;
6342
6343         return true;
6344 }
6345
6346 static void g4x_write_eld(struct drm_connector *connector,
6347                           struct drm_crtc *crtc)
6348 {
6349         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6350         uint8_t *eld = connector->eld;
6351         uint32_t eldv;
6352         uint32_t len;
6353         uint32_t i;
6354
6355         i = I915_READ(G4X_AUD_VID_DID);
6356
6357         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6358                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6359         else
6360                 eldv = G4X_ELDV_DEVCTG;
6361
6362         if (intel_eld_uptodate(connector,
6363                                G4X_AUD_CNTL_ST, eldv,
6364                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6365                                G4X_HDMIW_HDMIEDID))
6366                 return;
6367
6368         i = I915_READ(G4X_AUD_CNTL_ST);
6369         i &= ~(eldv | G4X_ELD_ADDR);
6370         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6371         I915_WRITE(G4X_AUD_CNTL_ST, i);
6372
6373         if (!eld[0])
6374                 return;
6375
6376         len = min_t(uint8_t, eld[2], len);
6377         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6378         for (i = 0; i < len; i++)
6379                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6380
6381         i = I915_READ(G4X_AUD_CNTL_ST);
6382         i |= eldv;
6383         I915_WRITE(G4X_AUD_CNTL_ST, i);
6384 }
6385
6386 static void ironlake_write_eld(struct drm_connector *connector,
6387                                      struct drm_crtc *crtc)
6388 {
6389         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6390         uint8_t *eld = connector->eld;
6391         uint32_t eldv;
6392         uint32_t i;
6393         int len;
6394         int hdmiw_hdmiedid;
6395         int aud_config;
6396         int aud_cntl_st;
6397         int aud_cntrl_st2;
6398
6399         if (HAS_PCH_IBX(connector->dev)) {
6400                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6401                 aud_config = IBX_AUD_CONFIG_A;
6402                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6403                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6404         } else {
6405                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6406                 aud_config = CPT_AUD_CONFIG_A;
6407                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6408                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6409         }
6410
6411         i = to_intel_crtc(crtc)->pipe;
6412         hdmiw_hdmiedid += i * 0x100;
6413         aud_cntl_st += i * 0x100;
6414         aud_config += i * 0x100;
6415
6416         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6417
6418         i = I915_READ(aud_cntl_st);
6419         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6420         if (!i) {
6421                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6422                 /* operate blindly on all ports */
6423                 eldv = IBX_ELD_VALIDB;
6424                 eldv |= IBX_ELD_VALIDB << 4;
6425                 eldv |= IBX_ELD_VALIDB << 8;
6426         } else {
6427                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6428                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6429         }
6430
6431         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6432                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6433                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6434                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6435         } else
6436                 I915_WRITE(aud_config, 0);
6437
6438         if (intel_eld_uptodate(connector,
6439                                aud_cntrl_st2, eldv,
6440                                aud_cntl_st, IBX_ELD_ADDRESS,
6441                                hdmiw_hdmiedid))
6442                 return;
6443
6444         i = I915_READ(aud_cntrl_st2);
6445         i &= ~eldv;
6446         I915_WRITE(aud_cntrl_st2, i);
6447
6448         if (!eld[0])
6449                 return;
6450
6451         i = I915_READ(aud_cntl_st);
6452         i &= ~IBX_ELD_ADDRESS;
6453         I915_WRITE(aud_cntl_st, i);
6454
6455         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6456         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6457         for (i = 0; i < len; i++)
6458                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6459
6460         i = I915_READ(aud_cntrl_st2);
6461         i |= eldv;
6462         I915_WRITE(aud_cntrl_st2, i);
6463 }
6464
6465 void intel_write_eld(struct drm_encoder *encoder,
6466                      struct drm_display_mode *mode)
6467 {
6468         struct drm_crtc *crtc = encoder->crtc;
6469         struct drm_connector *connector;
6470         struct drm_device *dev = encoder->dev;
6471         struct drm_i915_private *dev_priv = dev->dev_private;
6472
6473         connector = drm_select_eld(encoder, mode);
6474         if (!connector)
6475                 return;
6476
6477         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6478                          connector->base.id,
6479                          drm_get_connector_name(connector),
6480                          connector->encoder->base.id,
6481                          drm_get_encoder_name(connector->encoder));
6482
6483         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6484
6485         if (dev_priv->display.write_eld)
6486                 dev_priv->display.write_eld(connector, crtc);
6487 }
6488
6489 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6490 void intel_crtc_load_lut(struct drm_crtc *crtc)
6491 {
6492         struct drm_device *dev = crtc->dev;
6493         struct drm_i915_private *dev_priv = dev->dev_private;
6494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6495         int palreg = PALETTE(intel_crtc->pipe);
6496         int i;
6497
6498         /* The clocks have to be on to load the palette. */
6499         if (!crtc->enabled)
6500                 return;
6501
6502         /* use legacy palette for Ironlake */
6503         if (HAS_PCH_SPLIT(dev))
6504                 palreg = LGC_PALETTE(intel_crtc->pipe);
6505
6506         for (i = 0; i < 256; i++) {
6507                 I915_WRITE(palreg + 4 * i,
6508                            (intel_crtc->lut_r[i] << 16) |
6509                            (intel_crtc->lut_g[i] << 8) |
6510                            intel_crtc->lut_b[i]);
6511         }
6512 }
6513
6514 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6515 {
6516         struct drm_device *dev = crtc->dev;
6517         struct drm_i915_private *dev_priv = dev->dev_private;
6518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6519         bool visible = base != 0;
6520         u32 cntl;
6521
6522         if (intel_crtc->cursor_visible == visible)
6523                 return;
6524
6525         cntl = I915_READ(_CURACNTR);
6526         if (visible) {
6527                 /* On these chipsets we can only modify the base whilst
6528                  * the cursor is disabled.
6529                  */
6530                 I915_WRITE(_CURABASE, base);
6531
6532                 cntl &= ~(CURSOR_FORMAT_MASK);
6533                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6534                 cntl |= CURSOR_ENABLE |
6535                         CURSOR_GAMMA_ENABLE |
6536                         CURSOR_FORMAT_ARGB;
6537         } else
6538                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6539         I915_WRITE(_CURACNTR, cntl);
6540
6541         intel_crtc->cursor_visible = visible;
6542 }
6543
6544 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6545 {
6546         struct drm_device *dev = crtc->dev;
6547         struct drm_i915_private *dev_priv = dev->dev_private;
6548         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6549         int pipe = intel_crtc->pipe;
6550         bool visible = base != 0;
6551
6552         if (intel_crtc->cursor_visible != visible) {
6553                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6554                 if (base) {
6555                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6556                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6557                         cntl |= pipe << 28; /* Connect to correct pipe */
6558                 } else {
6559                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6560                         cntl |= CURSOR_MODE_DISABLE;
6561                 }
6562                 I915_WRITE(CURCNTR(pipe), cntl);
6563
6564                 intel_crtc->cursor_visible = visible;
6565         }
6566         /* and commit changes on next vblank */
6567         I915_WRITE(CURBASE(pipe), base);
6568 }
6569
6570 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6571 {
6572         struct drm_device *dev = crtc->dev;
6573         struct drm_i915_private *dev_priv = dev->dev_private;
6574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575         int pipe = intel_crtc->pipe;
6576         bool visible = base != 0;
6577
6578         if (intel_crtc->cursor_visible != visible) {
6579                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6580                 if (base) {
6581                         cntl &= ~CURSOR_MODE;
6582                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6583                 } else {
6584                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6585                         cntl |= CURSOR_MODE_DISABLE;
6586                 }
6587                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6588
6589                 intel_crtc->cursor_visible = visible;
6590         }
6591         /* and commit changes on next vblank */
6592         I915_WRITE(CURBASE_IVB(pipe), base);
6593 }
6594
6595 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6596 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6597                                      bool on)
6598 {
6599         struct drm_device *dev = crtc->dev;
6600         struct drm_i915_private *dev_priv = dev->dev_private;
6601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602         int pipe = intel_crtc->pipe;
6603         int x = intel_crtc->cursor_x;
6604         int y = intel_crtc->cursor_y;
6605         u32 base, pos;
6606         bool visible;
6607
6608         pos = 0;
6609
6610         if (on && crtc->enabled && crtc->fb) {
6611                 base = intel_crtc->cursor_addr;
6612                 if (x > (int) crtc->fb->width)
6613                         base = 0;
6614
6615                 if (y > (int) crtc->fb->height)
6616                         base = 0;
6617         } else
6618                 base = 0;
6619
6620         if (x < 0) {
6621                 if (x + intel_crtc->cursor_width < 0)
6622                         base = 0;
6623
6624                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6625                 x = -x;
6626         }
6627         pos |= x << CURSOR_X_SHIFT;
6628
6629         if (y < 0) {
6630                 if (y + intel_crtc->cursor_height < 0)
6631                         base = 0;
6632
6633                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6634                 y = -y;
6635         }
6636         pos |= y << CURSOR_Y_SHIFT;
6637
6638         visible = base != 0;
6639         if (!visible && !intel_crtc->cursor_visible)
6640                 return;
6641
6642         if (IS_IVYBRIDGE(dev)) {
6643                 I915_WRITE(CURPOS_IVB(pipe), pos);
6644                 ivb_update_cursor(crtc, base);
6645         } else {
6646                 I915_WRITE(CURPOS(pipe), pos);
6647                 if (IS_845G(dev) || IS_I865G(dev))
6648                         i845_update_cursor(crtc, base);
6649                 else
6650                         i9xx_update_cursor(crtc, base);
6651         }
6652
6653         if (visible)
6654                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6655 }
6656
6657 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6658                                  struct drm_file *file,
6659                                  uint32_t handle,
6660                                  uint32_t width, uint32_t height)
6661 {
6662         struct drm_device *dev = crtc->dev;
6663         struct drm_i915_private *dev_priv = dev->dev_private;
6664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665         struct drm_i915_gem_object *obj;
6666         uint32_t addr;
6667         int ret;
6668
6669         DRM_DEBUG_KMS("\n");
6670
6671         /* if we want to turn off the cursor ignore width and height */
6672         if (!handle) {
6673                 DRM_DEBUG_KMS("cursor off\n");
6674                 addr = 0;
6675                 obj = NULL;
6676                 mutex_lock(&dev->struct_mutex);
6677                 goto finish;
6678         }
6679
6680         /* Currently we only support 64x64 cursors */
6681         if (width != 64 || height != 64) {
6682                 DRM_ERROR("we currently only support 64x64 cursors\n");
6683                 return -EINVAL;
6684         }
6685
6686         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6687         if (&obj->base == NULL)
6688                 return -ENOENT;
6689
6690         if (obj->base.size < width * height * 4) {
6691                 DRM_ERROR("buffer is to small\n");
6692                 ret = -ENOMEM;
6693                 goto fail;
6694         }
6695
6696         /* we only need to pin inside GTT if cursor is non-phy */
6697         mutex_lock(&dev->struct_mutex);
6698         if (!dev_priv->info->cursor_needs_physical) {
6699                 if (obj->tiling_mode) {
6700                         DRM_ERROR("cursor cannot be tiled\n");
6701                         ret = -EINVAL;
6702                         goto fail_locked;
6703                 }
6704
6705                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6706                 if (ret) {
6707                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6708                         goto fail_locked;
6709                 }
6710
6711                 ret = i915_gem_object_put_fence(obj);
6712                 if (ret) {
6713                         DRM_ERROR("failed to release fence for cursor");
6714                         goto fail_unpin;
6715                 }
6716
6717                 addr = obj->gtt_offset;
6718         } else {
6719                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6720                 ret = i915_gem_attach_phys_object(dev, obj,
6721                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6722                                                   align);
6723                 if (ret) {
6724                         DRM_ERROR("failed to attach phys object\n");
6725                         goto fail_locked;
6726                 }
6727                 addr = obj->phys_obj->handle->busaddr;
6728         }
6729
6730         if (IS_GEN2(dev))
6731                 I915_WRITE(CURSIZE, (height << 12) | width);
6732
6733  finish:
6734         if (intel_crtc->cursor_bo) {
6735                 if (dev_priv->info->cursor_needs_physical) {
6736                         if (intel_crtc->cursor_bo != obj)
6737                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6738                 } else
6739                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6740                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6741         }
6742
6743         mutex_unlock(&dev->struct_mutex);
6744
6745         intel_crtc->cursor_addr = addr;
6746         intel_crtc->cursor_bo = obj;
6747         intel_crtc->cursor_width = width;
6748         intel_crtc->cursor_height = height;
6749
6750         intel_crtc_update_cursor(crtc, true);
6751
6752         return 0;
6753 fail_unpin:
6754         i915_gem_object_unpin(obj);
6755 fail_locked:
6756         mutex_unlock(&dev->struct_mutex);
6757 fail:
6758         drm_gem_object_unreference_unlocked(&obj->base);
6759         return ret;
6760 }
6761
6762 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6763 {
6764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6765
6766         intel_crtc->cursor_x = x;
6767         intel_crtc->cursor_y = y;
6768
6769         intel_crtc_update_cursor(crtc, true);
6770
6771         return 0;
6772 }
6773
6774 /** Sets the color ramps on behalf of RandR */
6775 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6776                                  u16 blue, int regno)
6777 {
6778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6779
6780         intel_crtc->lut_r[regno] = red >> 8;
6781         intel_crtc->lut_g[regno] = green >> 8;
6782         intel_crtc->lut_b[regno] = blue >> 8;
6783 }
6784
6785 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6786                              u16 *blue, int regno)
6787 {
6788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6789
6790         *red = intel_crtc->lut_r[regno] << 8;
6791         *green = intel_crtc->lut_g[regno] << 8;
6792         *blue = intel_crtc->lut_b[regno] << 8;
6793 }
6794
6795 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6796                                  u16 *blue, uint32_t start, uint32_t size)
6797 {
6798         int end = (start + size > 256) ? 256 : start + size, i;
6799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6800
6801         for (i = start; i < end; i++) {
6802                 intel_crtc->lut_r[i] = red[i] >> 8;
6803                 intel_crtc->lut_g[i] = green[i] >> 8;
6804                 intel_crtc->lut_b[i] = blue[i] >> 8;
6805         }
6806
6807         intel_crtc_load_lut(crtc);
6808 }
6809
6810 /**
6811  * Get a pipe with a simple mode set on it for doing load-based monitor
6812  * detection.
6813  *
6814  * It will be up to the load-detect code to adjust the pipe as appropriate for
6815  * its requirements.  The pipe will be connected to no other encoders.
6816  *
6817  * Currently this code will only succeed if there is a pipe with no encoders
6818  * configured for it.  In the future, it could choose to temporarily disable
6819  * some outputs to free up a pipe for its use.
6820  *
6821  * \return crtc, or NULL if no pipes are available.
6822  */
6823
6824 /* VESA 640x480x72Hz mode to set on the pipe */
6825 static struct drm_display_mode load_detect_mode = {
6826         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6827                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6828 };
6829
6830 static struct drm_framebuffer *
6831 intel_framebuffer_create(struct drm_device *dev,
6832                          struct drm_mode_fb_cmd2 *mode_cmd,
6833                          struct drm_i915_gem_object *obj)
6834 {
6835         struct intel_framebuffer *intel_fb;
6836         int ret;
6837
6838         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6839         if (!intel_fb) {
6840                 drm_gem_object_unreference_unlocked(&obj->base);
6841                 return ERR_PTR(-ENOMEM);
6842         }
6843
6844         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6845         if (ret) {
6846                 drm_gem_object_unreference_unlocked(&obj->base);
6847                 kfree(intel_fb);
6848                 return ERR_PTR(ret);
6849         }
6850
6851         return &intel_fb->base;
6852 }
6853
6854 static u32
6855 intel_framebuffer_pitch_for_width(int width, int bpp)
6856 {
6857         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6858         return ALIGN(pitch, 64);
6859 }
6860
6861 static u32
6862 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6863 {
6864         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6865         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6866 }
6867
6868 static struct drm_framebuffer *
6869 intel_framebuffer_create_for_mode(struct drm_device *dev,
6870                                   struct drm_display_mode *mode,
6871                                   int depth, int bpp)
6872 {
6873         struct drm_i915_gem_object *obj;
6874         struct drm_mode_fb_cmd2 mode_cmd;
6875
6876         obj = i915_gem_alloc_object(dev,
6877                                     intel_framebuffer_size_for_mode(mode, bpp));
6878         if (obj == NULL)
6879                 return ERR_PTR(-ENOMEM);
6880
6881         mode_cmd.width = mode->hdisplay;
6882         mode_cmd.height = mode->vdisplay;
6883         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6884                                                                 bpp);
6885         mode_cmd.pixel_format = 0;
6886
6887         return intel_framebuffer_create(dev, &mode_cmd, obj);
6888 }
6889
6890 static struct drm_framebuffer *
6891 mode_fits_in_fbdev(struct drm_device *dev,
6892                    struct drm_display_mode *mode)
6893 {
6894         struct drm_i915_private *dev_priv = dev->dev_private;
6895         struct drm_i915_gem_object *obj;
6896         struct drm_framebuffer *fb;
6897
6898         if (dev_priv->fbdev == NULL)
6899                 return NULL;
6900
6901         obj = dev_priv->fbdev->ifb.obj;
6902         if (obj == NULL)
6903                 return NULL;
6904
6905         fb = &dev_priv->fbdev->ifb.base;
6906         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6907                                                                fb->bits_per_pixel))
6908                 return NULL;
6909
6910         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6911                 return NULL;
6912
6913         return fb;
6914 }
6915
6916 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6917                                 struct drm_connector *connector,
6918                                 struct drm_display_mode *mode,
6919                                 struct intel_load_detect_pipe *old)
6920 {
6921         struct intel_crtc *intel_crtc;
6922         struct drm_crtc *possible_crtc;
6923         struct drm_encoder *encoder = &intel_encoder->base;
6924         struct drm_crtc *crtc = NULL;
6925         struct drm_device *dev = encoder->dev;
6926         struct drm_framebuffer *old_fb;
6927         int i = -1;
6928
6929         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6930                       connector->base.id, drm_get_connector_name(connector),
6931                       encoder->base.id, drm_get_encoder_name(encoder));
6932
6933         /*
6934          * Algorithm gets a little messy:
6935          *
6936          *   - if the connector already has an assigned crtc, use it (but make
6937          *     sure it's on first)
6938          *
6939          *   - try to find the first unused crtc that can drive this connector,
6940          *     and use that if we find one
6941          */
6942
6943         /* See if we already have a CRTC for this connector */
6944         if (encoder->crtc) {
6945                 crtc = encoder->crtc;
6946
6947                 intel_crtc = to_intel_crtc(crtc);
6948                 old->dpms_mode = intel_crtc->dpms_mode;
6949                 old->load_detect_temp = false;
6950
6951                 /* Make sure the crtc and connector are running */
6952                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6953                         struct drm_encoder_helper_funcs *encoder_funcs;
6954                         struct drm_crtc_helper_funcs *crtc_funcs;
6955
6956                         crtc_funcs = crtc->helper_private;
6957                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6958
6959                         encoder_funcs = encoder->helper_private;
6960                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6961                 }
6962
6963                 return true;
6964         }
6965
6966         /* Find an unused one (if possible) */
6967         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6968                 i++;
6969                 if (!(encoder->possible_crtcs & (1 << i)))
6970                         continue;
6971                 if (!possible_crtc->enabled) {
6972                         crtc = possible_crtc;
6973                         break;
6974                 }
6975         }
6976
6977         /*
6978          * If we didn't find an unused CRTC, don't use any.
6979          */
6980         if (!crtc) {
6981                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6982                 return false;
6983         }
6984
6985         encoder->crtc = crtc;
6986         connector->encoder = encoder;
6987
6988         intel_crtc = to_intel_crtc(crtc);
6989         old->dpms_mode = intel_crtc->dpms_mode;
6990         old->load_detect_temp = true;
6991         old->release_fb = NULL;
6992
6993         if (!mode)
6994                 mode = &load_detect_mode;
6995
6996         old_fb = crtc->fb;
6997
6998         /* We need a framebuffer large enough to accommodate all accesses
6999          * that the plane may generate whilst we perform load detection.
7000          * We can not rely on the fbcon either being present (we get called
7001          * during its initialisation to detect all boot displays, or it may
7002          * not even exist) or that it is large enough to satisfy the
7003          * requested mode.
7004          */
7005         crtc->fb = mode_fits_in_fbdev(dev, mode);
7006         if (crtc->fb == NULL) {
7007                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7008                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7009                 old->release_fb = crtc->fb;
7010         } else
7011                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7012         if (IS_ERR(crtc->fb)) {
7013                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7014                 crtc->fb = old_fb;
7015                 return false;
7016         }
7017
7018         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
7019                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7020                 if (old->release_fb)
7021                         old->release_fb->funcs->destroy(old->release_fb);
7022                 crtc->fb = old_fb;
7023                 return false;
7024         }
7025
7026         /* let the connector get through one full cycle before testing */
7027         intel_wait_for_vblank(dev, intel_crtc->pipe);
7028
7029         return true;
7030 }
7031
7032 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
7033                                     struct drm_connector *connector,
7034                                     struct intel_load_detect_pipe *old)
7035 {
7036         struct drm_encoder *encoder = &intel_encoder->base;
7037         struct drm_device *dev = encoder->dev;
7038         struct drm_crtc *crtc = encoder->crtc;
7039         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
7040         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
7041
7042         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7043                       connector->base.id, drm_get_connector_name(connector),
7044                       encoder->base.id, drm_get_encoder_name(encoder));
7045
7046         if (old->load_detect_temp) {
7047                 connector->encoder = NULL;
7048                 drm_helper_disable_unused_functions(dev);
7049
7050                 if (old->release_fb)
7051                         old->release_fb->funcs->destroy(old->release_fb);
7052
7053                 return;
7054         }
7055
7056         /* Switch crtc and encoder back off if necessary */
7057         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
7058                 encoder_funcs->dpms(encoder, old->dpms_mode);
7059                 crtc_funcs->dpms(crtc, old->dpms_mode);
7060         }
7061 }
7062
7063 /* Returns the clock of the currently programmed mode of the given pipe. */
7064 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
7065 {
7066         struct drm_i915_private *dev_priv = dev->dev_private;
7067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7068         int pipe = intel_crtc->pipe;
7069         u32 dpll = I915_READ(DPLL(pipe));
7070         u32 fp;
7071         intel_clock_t clock;
7072
7073         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7074                 fp = I915_READ(FP0(pipe));
7075         else
7076                 fp = I915_READ(FP1(pipe));
7077
7078         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7079         if (IS_PINEVIEW(dev)) {
7080                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7081                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7082         } else {
7083                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7084                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7085         }
7086
7087         if (!IS_GEN2(dev)) {
7088                 if (IS_PINEVIEW(dev))
7089                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7090                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7091                 else
7092                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7093                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7094
7095                 switch (dpll & DPLL_MODE_MASK) {
7096                 case DPLLB_MODE_DAC_SERIAL:
7097                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7098                                 5 : 10;
7099                         break;
7100                 case DPLLB_MODE_LVDS:
7101                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7102                                 7 : 14;
7103                         break;
7104                 default:
7105                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7106                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7107                         return 0;
7108                 }
7109
7110                 /* XXX: Handle the 100Mhz refclk */
7111                 intel_clock(dev, 96000, &clock);
7112         } else {
7113                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7114
7115                 if (is_lvds) {
7116                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7117                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7118                         clock.p2 = 14;
7119
7120                         if ((dpll & PLL_REF_INPUT_MASK) ==
7121                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7122                                 /* XXX: might not be 66MHz */
7123                                 intel_clock(dev, 66000, &clock);
7124                         } else
7125                                 intel_clock(dev, 48000, &clock);
7126                 } else {
7127                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7128                                 clock.p1 = 2;
7129                         else {
7130                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7131                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7132                         }
7133                         if (dpll & PLL_P2_DIVIDE_BY_4)
7134                                 clock.p2 = 4;
7135                         else
7136                                 clock.p2 = 2;
7137
7138                         intel_clock(dev, 48000, &clock);
7139                 }
7140         }
7141
7142         /* XXX: It would be nice to validate the clocks, but we can't reuse
7143          * i830PllIsValid() because it relies on the xf86_config connector
7144          * configuration being accurate, which it isn't necessarily.
7145          */
7146
7147         return clock.dot;
7148 }
7149
7150 /** Returns the currently programmed mode of the given pipe. */
7151 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7152                                              struct drm_crtc *crtc)
7153 {
7154         struct drm_i915_private *dev_priv = dev->dev_private;
7155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7156         int pipe = intel_crtc->pipe;
7157         struct drm_display_mode *mode;
7158         int htot = I915_READ(HTOTAL(pipe));
7159         int hsync = I915_READ(HSYNC(pipe));
7160         int vtot = I915_READ(VTOTAL(pipe));
7161         int vsync = I915_READ(VSYNC(pipe));
7162
7163         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7164         if (!mode)
7165                 return NULL;
7166
7167         mode->clock = intel_crtc_clock_get(dev, crtc);
7168         mode->hdisplay = (htot & 0xffff) + 1;
7169         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7170         mode->hsync_start = (hsync & 0xffff) + 1;
7171         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7172         mode->vdisplay = (vtot & 0xffff) + 1;
7173         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7174         mode->vsync_start = (vsync & 0xffff) + 1;
7175         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7176
7177         drm_mode_set_name(mode);
7178         drm_mode_set_crtcinfo(mode, 0);
7179
7180         return mode;
7181 }
7182
7183 #define GPU_IDLE_TIMEOUT 500 /* ms */
7184
7185 /* When this timer fires, we've been idle for awhile */
7186 static void intel_gpu_idle_timer(unsigned long arg)
7187 {
7188         struct drm_device *dev = (struct drm_device *)arg;
7189         drm_i915_private_t *dev_priv = dev->dev_private;
7190
7191         if (!list_empty(&dev_priv->mm.active_list)) {
7192                 /* Still processing requests, so just re-arm the timer. */
7193                 mod_timer(&dev_priv->idle_timer, jiffies +
7194                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7195                 return;
7196         }
7197
7198         dev_priv->busy = false;
7199         queue_work(dev_priv->wq, &dev_priv->idle_work);
7200 }
7201
7202 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7203
7204 static void intel_crtc_idle_timer(unsigned long arg)
7205 {
7206         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7207         struct drm_crtc *crtc = &intel_crtc->base;
7208         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7209         struct intel_framebuffer *intel_fb;
7210
7211         intel_fb = to_intel_framebuffer(crtc->fb);
7212         if (intel_fb && intel_fb->obj->active) {
7213                 /* The framebuffer is still being accessed by the GPU. */
7214                 mod_timer(&intel_crtc->idle_timer, jiffies +
7215                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7216                 return;
7217         }
7218
7219         intel_crtc->busy = false;
7220         queue_work(dev_priv->wq, &dev_priv->idle_work);
7221 }
7222
7223 static void intel_increase_pllclock(struct drm_crtc *crtc)
7224 {
7225         struct drm_device *dev = crtc->dev;
7226         drm_i915_private_t *dev_priv = dev->dev_private;
7227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7228         int pipe = intel_crtc->pipe;
7229         int dpll_reg = DPLL(pipe);
7230         int dpll;
7231
7232         if (HAS_PCH_SPLIT(dev))
7233                 return;
7234
7235         if (!dev_priv->lvds_downclock_avail)
7236                 return;
7237
7238         dpll = I915_READ(dpll_reg);
7239         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7240                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7241
7242                 assert_panel_unlocked(dev_priv, pipe);
7243
7244                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7245                 I915_WRITE(dpll_reg, dpll);
7246                 intel_wait_for_vblank(dev, pipe);
7247
7248                 dpll = I915_READ(dpll_reg);
7249                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7250                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7251         }
7252
7253         /* Schedule downclock */
7254         mod_timer(&intel_crtc->idle_timer, jiffies +
7255                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7256 }
7257
7258 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7259 {
7260         struct drm_device *dev = crtc->dev;
7261         drm_i915_private_t *dev_priv = dev->dev_private;
7262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7263         int pipe = intel_crtc->pipe;
7264         int dpll_reg = DPLL(pipe);
7265         int dpll = I915_READ(dpll_reg);
7266
7267         if (HAS_PCH_SPLIT(dev))
7268                 return;
7269
7270         if (!dev_priv->lvds_downclock_avail)
7271                 return;
7272
7273         /*
7274          * Since this is called by a timer, we should never get here in
7275          * the manual case.
7276          */
7277         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7278                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7279
7280                 assert_panel_unlocked(dev_priv, pipe);
7281
7282                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7283                 I915_WRITE(dpll_reg, dpll);
7284                 intel_wait_for_vblank(dev, pipe);
7285                 dpll = I915_READ(dpll_reg);
7286                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7287                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7288         }
7289
7290 }
7291
7292 /**
7293  * intel_idle_update - adjust clocks for idleness
7294  * @work: work struct
7295  *
7296  * Either the GPU or display (or both) went idle.  Check the busy status
7297  * here and adjust the CRTC and GPU clocks as necessary.
7298  */
7299 static void intel_idle_update(struct work_struct *work)
7300 {
7301         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7302                                                     idle_work);
7303         struct drm_device *dev = dev_priv->dev;
7304         struct drm_crtc *crtc;
7305         struct intel_crtc *intel_crtc;
7306
7307         if (!i915_powersave)
7308                 return;
7309
7310         mutex_lock(&dev->struct_mutex);
7311
7312         i915_update_gfx_val(dev_priv);
7313
7314         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7315                 /* Skip inactive CRTCs */
7316                 if (!crtc->fb)
7317                         continue;
7318
7319                 intel_crtc = to_intel_crtc(crtc);
7320                 if (!intel_crtc->busy)
7321                         intel_decrease_pllclock(crtc);
7322         }
7323
7324
7325         mutex_unlock(&dev->struct_mutex);
7326 }
7327
7328 /**
7329  * intel_mark_busy - mark the GPU and possibly the display busy
7330  * @dev: drm device
7331  * @obj: object we're operating on
7332  *
7333  * Callers can use this function to indicate that the GPU is busy processing
7334  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7335  * buffer), we'll also mark the display as busy, so we know to increase its
7336  * clock frequency.
7337  */
7338 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7339 {
7340         drm_i915_private_t *dev_priv = dev->dev_private;
7341         struct drm_crtc *crtc = NULL;
7342         struct intel_framebuffer *intel_fb;
7343         struct intel_crtc *intel_crtc;
7344
7345         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7346                 return;
7347
7348         if (!dev_priv->busy)
7349                 dev_priv->busy = true;
7350         else
7351                 mod_timer(&dev_priv->idle_timer, jiffies +
7352                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7353
7354         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7355                 if (!crtc->fb)
7356                         continue;
7357
7358                 intel_crtc = to_intel_crtc(crtc);
7359                 intel_fb = to_intel_framebuffer(crtc->fb);
7360                 if (intel_fb->obj == obj) {
7361                         if (!intel_crtc->busy) {
7362                                 /* Non-busy -> busy, upclock */
7363                                 intel_increase_pllclock(crtc);
7364                                 intel_crtc->busy = true;
7365                         } else {
7366                                 /* Busy -> busy, put off timer */
7367                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7368                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7369                         }
7370                 }
7371         }
7372 }
7373
7374 static void intel_crtc_destroy(struct drm_crtc *crtc)
7375 {
7376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7377         struct drm_device *dev = crtc->dev;
7378         struct intel_unpin_work *work;
7379         unsigned long flags;
7380
7381         spin_lock_irqsave(&dev->event_lock, flags);
7382         work = intel_crtc->unpin_work;
7383         intel_crtc->unpin_work = NULL;
7384         spin_unlock_irqrestore(&dev->event_lock, flags);
7385
7386         if (work) {
7387                 cancel_work_sync(&work->work);
7388                 kfree(work);
7389         }
7390
7391         drm_crtc_cleanup(crtc);
7392
7393         kfree(intel_crtc);
7394 }
7395
7396 static void intel_unpin_work_fn(struct work_struct *__work)
7397 {
7398         struct intel_unpin_work *work =
7399                 container_of(__work, struct intel_unpin_work, work);
7400
7401         mutex_lock(&work->dev->struct_mutex);
7402         intel_unpin_fb_obj(work->old_fb_obj);
7403         drm_gem_object_unreference(&work->pending_flip_obj->base);
7404         drm_gem_object_unreference(&work->old_fb_obj->base);
7405
7406         intel_update_fbc(work->dev);
7407         mutex_unlock(&work->dev->struct_mutex);
7408         kfree(work);
7409 }
7410
7411 static void do_intel_finish_page_flip(struct drm_device *dev,
7412                                       struct drm_crtc *crtc)
7413 {
7414         drm_i915_private_t *dev_priv = dev->dev_private;
7415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7416         struct intel_unpin_work *work;
7417         struct drm_i915_gem_object *obj;
7418         struct drm_pending_vblank_event *e;
7419         struct timeval tnow, tvbl;
7420         unsigned long flags;
7421
7422         /* Ignore early vblank irqs */
7423         if (intel_crtc == NULL)
7424                 return;
7425
7426         do_gettimeofday(&tnow);
7427
7428         spin_lock_irqsave(&dev->event_lock, flags);
7429         work = intel_crtc->unpin_work;
7430         if (work == NULL || !work->pending) {
7431                 spin_unlock_irqrestore(&dev->event_lock, flags);
7432                 return;
7433         }
7434
7435         intel_crtc->unpin_work = NULL;
7436
7437         if (work->event) {
7438                 e = work->event;
7439                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7440
7441                 /* Called before vblank count and timestamps have
7442                  * been updated for the vblank interval of flip
7443                  * completion? Need to increment vblank count and
7444                  * add one videorefresh duration to returned timestamp
7445                  * to account for this. We assume this happened if we
7446                  * get called over 0.9 frame durations after the last
7447                  * timestamped vblank.
7448                  *
7449                  * This calculation can not be used with vrefresh rates
7450                  * below 5Hz (10Hz to be on the safe side) without
7451                  * promoting to 64 integers.
7452                  */
7453                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7454                     9 * crtc->framedur_ns) {
7455                         e->event.sequence++;
7456                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7457                                              crtc->framedur_ns);
7458                 }
7459
7460                 e->event.tv_sec = tvbl.tv_sec;
7461                 e->event.tv_usec = tvbl.tv_usec;
7462
7463                 list_add_tail(&e->base.link,
7464                               &e->base.file_priv->event_list);
7465                 wake_up_interruptible(&e->base.file_priv->event_wait);
7466         }
7467
7468         drm_vblank_put(dev, intel_crtc->pipe);
7469
7470         spin_unlock_irqrestore(&dev->event_lock, flags);
7471
7472         obj = work->old_fb_obj;
7473
7474         atomic_clear_mask(1 << intel_crtc->plane,
7475                           &obj->pending_flip.counter);
7476         if (atomic_read(&obj->pending_flip) == 0)
7477                 wake_up(&dev_priv->pending_flip_queue);
7478
7479         schedule_work(&work->work);
7480
7481         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7482 }
7483
7484 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7485 {
7486         drm_i915_private_t *dev_priv = dev->dev_private;
7487         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7488
7489         do_intel_finish_page_flip(dev, crtc);
7490 }
7491
7492 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7493 {
7494         drm_i915_private_t *dev_priv = dev->dev_private;
7495         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7496
7497         do_intel_finish_page_flip(dev, crtc);
7498 }
7499
7500 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7501 {
7502         drm_i915_private_t *dev_priv = dev->dev_private;
7503         struct intel_crtc *intel_crtc =
7504                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7505         unsigned long flags;
7506
7507         spin_lock_irqsave(&dev->event_lock, flags);
7508         if (intel_crtc->unpin_work) {
7509                 if ((++intel_crtc->unpin_work->pending) > 1)
7510                         DRM_ERROR("Prepared flip multiple times\n");
7511         } else {
7512                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7513         }
7514         spin_unlock_irqrestore(&dev->event_lock, flags);
7515 }
7516
7517 static int intel_gen2_queue_flip(struct drm_device *dev,
7518                                  struct drm_crtc *crtc,
7519                                  struct drm_framebuffer *fb,
7520                                  struct drm_i915_gem_object *obj)
7521 {
7522         struct drm_i915_private *dev_priv = dev->dev_private;
7523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7524         unsigned long offset;
7525         u32 flip_mask;
7526         int ret;
7527
7528         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7529         if (ret)
7530                 goto out;
7531
7532         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7533         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7534
7535         ret = BEGIN_LP_RING(6);
7536         if (ret)
7537                 goto out;
7538
7539         /* Can't queue multiple flips, so wait for the previous
7540          * one to finish before executing the next.
7541          */
7542         if (intel_crtc->plane)
7543                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7544         else
7545                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7546         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7547         OUT_RING(MI_NOOP);
7548         OUT_RING(MI_DISPLAY_FLIP |
7549                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7550         OUT_RING(fb->pitches[0]);
7551         OUT_RING(obj->gtt_offset + offset);
7552         OUT_RING(0); /* aux display base address, unused */
7553         ADVANCE_LP_RING();
7554 out:
7555         return ret;
7556 }
7557
7558 static int intel_gen3_queue_flip(struct drm_device *dev,
7559                                  struct drm_crtc *crtc,
7560                                  struct drm_framebuffer *fb,
7561                                  struct drm_i915_gem_object *obj)
7562 {
7563         struct drm_i915_private *dev_priv = dev->dev_private;
7564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7565         unsigned long offset;
7566         u32 flip_mask;
7567         int ret;
7568
7569         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7570         if (ret)
7571                 goto out;
7572
7573         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7574         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7575
7576         ret = BEGIN_LP_RING(6);
7577         if (ret)
7578                 goto out;
7579
7580         if (intel_crtc->plane)
7581                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7582         else
7583                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7584         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7585         OUT_RING(MI_NOOP);
7586         OUT_RING(MI_DISPLAY_FLIP_I915 |
7587                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7588         OUT_RING(fb->pitches[0]);
7589         OUT_RING(obj->gtt_offset + offset);
7590         OUT_RING(MI_NOOP);
7591
7592         ADVANCE_LP_RING();
7593 out:
7594         return ret;
7595 }
7596
7597 static int intel_gen4_queue_flip(struct drm_device *dev,
7598                                  struct drm_crtc *crtc,
7599                                  struct drm_framebuffer *fb,
7600                                  struct drm_i915_gem_object *obj)
7601 {
7602         struct drm_i915_private *dev_priv = dev->dev_private;
7603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7604         uint32_t pf, pipesrc;
7605         int ret;
7606
7607         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7608         if (ret)
7609                 goto out;
7610
7611         ret = BEGIN_LP_RING(4);
7612         if (ret)
7613                 goto out;
7614
7615         /* i965+ uses the linear or tiled offsets from the
7616          * Display Registers (which do not change across a page-flip)
7617          * so we need only reprogram the base address.
7618          */
7619         OUT_RING(MI_DISPLAY_FLIP |
7620                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7621         OUT_RING(fb->pitches[0]);
7622         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7623
7624         /* XXX Enabling the panel-fitter across page-flip is so far
7625          * untested on non-native modes, so ignore it for now.
7626          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7627          */
7628         pf = 0;
7629         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7630         OUT_RING(pf | pipesrc);
7631         ADVANCE_LP_RING();
7632 out:
7633         return ret;
7634 }
7635
7636 static int intel_gen6_queue_flip(struct drm_device *dev,
7637                                  struct drm_crtc *crtc,
7638                                  struct drm_framebuffer *fb,
7639                                  struct drm_i915_gem_object *obj)
7640 {
7641         struct drm_i915_private *dev_priv = dev->dev_private;
7642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7643         uint32_t pf, pipesrc;
7644         int ret;
7645
7646         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7647         if (ret)
7648                 goto out;
7649
7650         ret = BEGIN_LP_RING(4);
7651         if (ret)
7652                 goto out;
7653
7654         OUT_RING(MI_DISPLAY_FLIP |
7655                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7656         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7657         OUT_RING(obj->gtt_offset);
7658
7659         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7660         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7661         OUT_RING(pf | pipesrc);
7662         ADVANCE_LP_RING();
7663 out:
7664         return ret;
7665 }
7666
7667 /*
7668  * On gen7 we currently use the blit ring because (in early silicon at least)
7669  * the render ring doesn't give us interrpts for page flip completion, which
7670  * means clients will hang after the first flip is queued.  Fortunately the
7671  * blit ring generates interrupts properly, so use it instead.
7672  */
7673 static int intel_gen7_queue_flip(struct drm_device *dev,
7674                                  struct drm_crtc *crtc,
7675                                  struct drm_framebuffer *fb,
7676                                  struct drm_i915_gem_object *obj)
7677 {
7678         struct drm_i915_private *dev_priv = dev->dev_private;
7679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7680         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7681         int ret;
7682
7683         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7684         if (ret)
7685                 goto out;
7686
7687         ret = intel_ring_begin(ring, 4);
7688         if (ret)
7689                 goto out;
7690
7691         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7692         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7693         intel_ring_emit(ring, (obj->gtt_offset));
7694         intel_ring_emit(ring, (MI_NOOP));
7695         intel_ring_advance(ring);
7696 out:
7697         return ret;
7698 }
7699
7700 static int intel_default_queue_flip(struct drm_device *dev,
7701                                     struct drm_crtc *crtc,
7702                                     struct drm_framebuffer *fb,
7703                                     struct drm_i915_gem_object *obj)
7704 {
7705         return -ENODEV;
7706 }
7707
7708 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7709                                 struct drm_framebuffer *fb,
7710                                 struct drm_pending_vblank_event *event)
7711 {
7712         struct drm_device *dev = crtc->dev;
7713         struct drm_i915_private *dev_priv = dev->dev_private;
7714         struct intel_framebuffer *intel_fb;
7715         struct drm_i915_gem_object *obj;
7716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7717         struct intel_unpin_work *work;
7718         unsigned long flags;
7719         int ret;
7720
7721         work = kzalloc(sizeof *work, GFP_KERNEL);
7722         if (work == NULL)
7723                 return -ENOMEM;
7724
7725         work->event = event;
7726         work->dev = crtc->dev;
7727         intel_fb = to_intel_framebuffer(crtc->fb);
7728         work->old_fb_obj = intel_fb->obj;
7729         INIT_WORK(&work->work, intel_unpin_work_fn);
7730
7731         ret = drm_vblank_get(dev, intel_crtc->pipe);
7732         if (ret)
7733                 goto free_work;
7734
7735         /* We borrow the event spin lock for protecting unpin_work */
7736         spin_lock_irqsave(&dev->event_lock, flags);
7737         if (intel_crtc->unpin_work) {
7738                 spin_unlock_irqrestore(&dev->event_lock, flags);
7739                 kfree(work);
7740                 drm_vblank_put(dev, intel_crtc->pipe);
7741
7742                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7743                 return -EBUSY;
7744         }
7745         intel_crtc->unpin_work = work;
7746         spin_unlock_irqrestore(&dev->event_lock, flags);
7747
7748         intel_fb = to_intel_framebuffer(fb);
7749         obj = intel_fb->obj;
7750
7751         mutex_lock(&dev->struct_mutex);
7752
7753         /* Reference the objects for the scheduled work. */
7754         drm_gem_object_reference(&work->old_fb_obj->base);
7755         drm_gem_object_reference(&obj->base);
7756
7757         crtc->fb = fb;
7758
7759         work->pending_flip_obj = obj;
7760
7761         work->enable_stall_check = true;
7762
7763         /* Block clients from rendering to the new back buffer until
7764          * the flip occurs and the object is no longer visible.
7765          */
7766         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7767
7768         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7769         if (ret)
7770                 goto cleanup_pending;
7771
7772         intel_disable_fbc(dev);
7773         mutex_unlock(&dev->struct_mutex);
7774
7775         trace_i915_flip_request(intel_crtc->plane, obj);
7776
7777         return 0;
7778
7779 cleanup_pending:
7780         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7781         drm_gem_object_unreference(&work->old_fb_obj->base);
7782         drm_gem_object_unreference(&obj->base);
7783         mutex_unlock(&dev->struct_mutex);
7784
7785         spin_lock_irqsave(&dev->event_lock, flags);
7786         intel_crtc->unpin_work = NULL;
7787         spin_unlock_irqrestore(&dev->event_lock, flags);
7788
7789         drm_vblank_put(dev, intel_crtc->pipe);
7790 free_work:
7791         kfree(work);
7792
7793         return ret;
7794 }
7795
7796 static void intel_sanitize_modesetting(struct drm_device *dev,
7797                                        int pipe, int plane)
7798 {
7799         struct drm_i915_private *dev_priv = dev->dev_private;
7800         u32 reg, val;
7801
7802         if (HAS_PCH_SPLIT(dev))
7803                 return;
7804
7805         /* Who knows what state these registers were left in by the BIOS or
7806          * grub?
7807          *
7808          * If we leave the registers in a conflicting state (e.g. with the
7809          * display plane reading from the other pipe than the one we intend
7810          * to use) then when we attempt to teardown the active mode, we will
7811          * not disable the pipes and planes in the correct order -- leaving
7812          * a plane reading from a disabled pipe and possibly leading to
7813          * undefined behaviour.
7814          */
7815
7816         reg = DSPCNTR(plane);
7817         val = I915_READ(reg);
7818
7819         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7820                 return;
7821         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7822                 return;
7823
7824         /* This display plane is active and attached to the other CPU pipe. */
7825         pipe = !pipe;
7826
7827         /* Disable the plane and wait for it to stop reading from the pipe. */
7828         intel_disable_plane(dev_priv, plane, pipe);
7829         intel_disable_pipe(dev_priv, pipe);
7830 }
7831
7832 static void intel_crtc_reset(struct drm_crtc *crtc)
7833 {
7834         struct drm_device *dev = crtc->dev;
7835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7836
7837         /* Reset flags back to the 'unknown' status so that they
7838          * will be correctly set on the initial modeset.
7839          */
7840         intel_crtc->dpms_mode = -1;
7841
7842         /* We need to fix up any BIOS configuration that conflicts with
7843          * our expectations.
7844          */
7845         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7846 }
7847
7848 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7849         .dpms = intel_crtc_dpms,
7850         .mode_fixup = intel_crtc_mode_fixup,
7851         .mode_set = intel_crtc_mode_set,
7852         .mode_set_base = intel_pipe_set_base,
7853         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7854         .load_lut = intel_crtc_load_lut,
7855         .disable = intel_crtc_disable,
7856 };
7857
7858 static const struct drm_crtc_funcs intel_crtc_funcs = {
7859         .reset = intel_crtc_reset,
7860         .cursor_set = intel_crtc_cursor_set,
7861         .cursor_move = intel_crtc_cursor_move,
7862         .gamma_set = intel_crtc_gamma_set,
7863         .set_config = drm_crtc_helper_set_config,
7864         .destroy = intel_crtc_destroy,
7865         .page_flip = intel_crtc_page_flip,
7866 };
7867
7868 static void intel_crtc_init(struct drm_device *dev, int pipe)
7869 {
7870         drm_i915_private_t *dev_priv = dev->dev_private;
7871         struct intel_crtc *intel_crtc;
7872         int i;
7873
7874         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7875         if (intel_crtc == NULL)
7876                 return;
7877
7878         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7879
7880         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7881         for (i = 0; i < 256; i++) {
7882                 intel_crtc->lut_r[i] = i;
7883                 intel_crtc->lut_g[i] = i;
7884                 intel_crtc->lut_b[i] = i;
7885         }
7886
7887         /* Swap pipes & planes for FBC on pre-965 */
7888         intel_crtc->pipe = pipe;
7889         intel_crtc->plane = pipe;
7890         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7891                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7892                 intel_crtc->plane = !pipe;
7893         }
7894
7895         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7896                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7897         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7898         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7899
7900         intel_crtc_reset(&intel_crtc->base);
7901         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7902         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7903
7904         if (HAS_PCH_SPLIT(dev)) {
7905                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7906                         intel_crtc->no_pll = true;
7907                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7908                 intel_helper_funcs.commit = ironlake_crtc_commit;
7909         } else {
7910                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7911                 intel_helper_funcs.commit = i9xx_crtc_commit;
7912         }
7913
7914         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7915
7916         intel_crtc->busy = false;
7917
7918         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7919                     (unsigned long)intel_crtc);
7920 }
7921
7922 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7923                                 struct drm_file *file)
7924 {
7925         drm_i915_private_t *dev_priv = dev->dev_private;
7926         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7927         struct drm_mode_object *drmmode_obj;
7928         struct intel_crtc *crtc;
7929
7930         if (!dev_priv) {
7931                 DRM_ERROR("called with no initialization\n");
7932                 return -EINVAL;
7933         }
7934
7935         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7936                         DRM_MODE_OBJECT_CRTC);
7937
7938         if (!drmmode_obj) {
7939                 DRM_ERROR("no such CRTC id\n");
7940                 return -EINVAL;
7941         }
7942
7943         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7944         pipe_from_crtc_id->pipe = crtc->pipe;
7945
7946         return 0;
7947 }
7948
7949 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7950 {
7951         struct intel_encoder *encoder;
7952         int index_mask = 0;
7953         int entry = 0;
7954
7955         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7956                 if (type_mask & encoder->clone_mask)
7957                         index_mask |= (1 << entry);
7958                 entry++;
7959         }
7960
7961         return index_mask;
7962 }
7963
7964 static bool has_edp_a(struct drm_device *dev)
7965 {
7966         struct drm_i915_private *dev_priv = dev->dev_private;
7967
7968         if (!IS_MOBILE(dev))
7969                 return false;
7970
7971         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7972                 return false;
7973
7974         if (IS_GEN5(dev) &&
7975             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7976                 return false;
7977
7978         return true;
7979 }
7980
7981 static void intel_setup_outputs(struct drm_device *dev)
7982 {
7983         struct drm_i915_private *dev_priv = dev->dev_private;
7984         struct intel_encoder *encoder;
7985         bool dpd_is_edp = false;
7986         bool has_lvds;
7987
7988         has_lvds = intel_lvds_init(dev);
7989         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7990                 /* disable the panel fitter on everything but LVDS */
7991                 I915_WRITE(PFIT_CONTROL, 0);
7992         }
7993
7994         if (HAS_PCH_SPLIT(dev)) {
7995                 dpd_is_edp = intel_dpd_is_edp(dev);
7996
7997                 if (has_edp_a(dev))
7998                         intel_dp_init(dev, DP_A);
7999
8000                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8001                         intel_dp_init(dev, PCH_DP_D);
8002         }
8003
8004         intel_crt_init(dev);
8005
8006         if (HAS_PCH_SPLIT(dev)) {
8007                 int found;
8008
8009                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8010                         /* PCH SDVOB multiplex with HDMIB */
8011                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8012                         if (!found)
8013                                 intel_hdmi_init(dev, HDMIB);
8014                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8015                                 intel_dp_init(dev, PCH_DP_B);
8016                 }
8017
8018                 if (I915_READ(HDMIC) & PORT_DETECTED)
8019                         intel_hdmi_init(dev, HDMIC);
8020
8021                 if (I915_READ(HDMID) & PORT_DETECTED)
8022                         intel_hdmi_init(dev, HDMID);
8023
8024                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8025                         intel_dp_init(dev, PCH_DP_C);
8026
8027                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8028                         intel_dp_init(dev, PCH_DP_D);
8029
8030         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8031                 bool found = false;
8032
8033                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8034                         DRM_DEBUG_KMS("probing SDVOB\n");
8035                         found = intel_sdvo_init(dev, SDVOB, true);
8036                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8037                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8038                                 intel_hdmi_init(dev, SDVOB);
8039                         }
8040
8041                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8042                                 DRM_DEBUG_KMS("probing DP_B\n");
8043                                 intel_dp_init(dev, DP_B);
8044                         }
8045                 }
8046
8047                 /* Before G4X SDVOC doesn't have its own detect register */
8048
8049                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8050                         DRM_DEBUG_KMS("probing SDVOC\n");
8051                         found = intel_sdvo_init(dev, SDVOC, false);
8052                 }
8053
8054                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8055
8056                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8057                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8058                                 intel_hdmi_init(dev, SDVOC);
8059                         }
8060                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8061                                 DRM_DEBUG_KMS("probing DP_C\n");
8062                                 intel_dp_init(dev, DP_C);
8063                         }
8064                 }
8065
8066                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8067                     (I915_READ(DP_D) & DP_DETECTED)) {
8068                         DRM_DEBUG_KMS("probing DP_D\n");
8069                         intel_dp_init(dev, DP_D);
8070                 }
8071         } else if (IS_GEN2(dev))
8072                 intel_dvo_init(dev);
8073
8074         if (SUPPORTS_TV(dev))
8075                 intel_tv_init(dev);
8076
8077         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8078                 encoder->base.possible_crtcs = encoder->crtc_mask;
8079                 encoder->base.possible_clones =
8080                         intel_encoder_clones(dev, encoder->clone_mask);
8081         }
8082
8083         /* disable all the possible outputs/crtcs before entering KMS mode */
8084         drm_helper_disable_unused_functions(dev);
8085
8086         if (HAS_PCH_SPLIT(dev))
8087                 ironlake_init_pch_refclk(dev);
8088 }
8089
8090 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8091 {
8092         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8093
8094         drm_framebuffer_cleanup(fb);
8095         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8096
8097         kfree(intel_fb);
8098 }
8099
8100 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8101                                                 struct drm_file *file,
8102                                                 unsigned int *handle)
8103 {
8104         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8105         struct drm_i915_gem_object *obj = intel_fb->obj;
8106
8107         return drm_gem_handle_create(file, &obj->base, handle);
8108 }
8109
8110 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8111         .destroy = intel_user_framebuffer_destroy,
8112         .create_handle = intel_user_framebuffer_create_handle,
8113 };
8114
8115 int intel_framebuffer_init(struct drm_device *dev,
8116                            struct intel_framebuffer *intel_fb,
8117                            struct drm_mode_fb_cmd2 *mode_cmd,
8118                            struct drm_i915_gem_object *obj)
8119 {
8120         int ret;
8121
8122         if (obj->tiling_mode == I915_TILING_Y)
8123                 return -EINVAL;
8124
8125         if (mode_cmd->pitches[0] & 63)
8126                 return -EINVAL;
8127
8128         switch (mode_cmd->pixel_format) {
8129         case DRM_FORMAT_RGB332:
8130         case DRM_FORMAT_RGB565:
8131         case DRM_FORMAT_XRGB8888:
8132         case DRM_FORMAT_ARGB8888:
8133         case DRM_FORMAT_XRGB2101010:
8134         case DRM_FORMAT_ARGB2101010:
8135                 /* RGB formats are common across chipsets */
8136                 break;
8137         case DRM_FORMAT_YUYV:
8138         case DRM_FORMAT_UYVY:
8139         case DRM_FORMAT_YVYU:
8140         case DRM_FORMAT_VYUY:
8141                 break;
8142         default:
8143                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8144                                 mode_cmd->pixel_format);
8145                 return -EINVAL;
8146         }
8147
8148         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8149         if (ret) {
8150                 DRM_ERROR("framebuffer init failed %d\n", ret);
8151                 return ret;
8152         }
8153
8154         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8155         intel_fb->obj = obj;
8156         return 0;
8157 }
8158
8159 static struct drm_framebuffer *
8160 intel_user_framebuffer_create(struct drm_device *dev,
8161                               struct drm_file *filp,
8162                               struct drm_mode_fb_cmd2 *mode_cmd)
8163 {
8164         struct drm_i915_gem_object *obj;
8165
8166         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8167                                                 mode_cmd->handles[0]));
8168         if (&obj->base == NULL)
8169                 return ERR_PTR(-ENOENT);
8170
8171         return intel_framebuffer_create(dev, mode_cmd, obj);
8172 }
8173
8174 static const struct drm_mode_config_funcs intel_mode_funcs = {
8175         .fb_create = intel_user_framebuffer_create,
8176         .output_poll_changed = intel_fb_output_poll_changed,
8177 };
8178
8179 static struct drm_i915_gem_object *
8180 intel_alloc_context_page(struct drm_device *dev)
8181 {
8182         struct drm_i915_gem_object *ctx;
8183         int ret;
8184
8185         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8186
8187         ctx = i915_gem_alloc_object(dev, 4096);
8188         if (!ctx) {
8189                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8190                 return NULL;
8191         }
8192
8193         ret = i915_gem_object_pin(ctx, 4096, true);
8194         if (ret) {
8195                 DRM_ERROR("failed to pin power context: %d\n", ret);
8196                 goto err_unref;
8197         }
8198
8199         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8200         if (ret) {
8201                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8202                 goto err_unpin;
8203         }
8204
8205         return ctx;
8206
8207 err_unpin:
8208         i915_gem_object_unpin(ctx);
8209 err_unref:
8210         drm_gem_object_unreference(&ctx->base);
8211         mutex_unlock(&dev->struct_mutex);
8212         return NULL;
8213 }
8214
8215 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8216 {
8217         struct drm_i915_private *dev_priv = dev->dev_private;
8218         u16 rgvswctl;
8219
8220         rgvswctl = I915_READ16(MEMSWCTL);
8221         if (rgvswctl & MEMCTL_CMD_STS) {
8222                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8223                 return false; /* still busy with another command */
8224         }
8225
8226         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8227                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8228         I915_WRITE16(MEMSWCTL, rgvswctl);
8229         POSTING_READ16(MEMSWCTL);
8230
8231         rgvswctl |= MEMCTL_CMD_STS;
8232         I915_WRITE16(MEMSWCTL, rgvswctl);
8233
8234         return true;
8235 }
8236
8237 void ironlake_enable_drps(struct drm_device *dev)
8238 {
8239         struct drm_i915_private *dev_priv = dev->dev_private;
8240         u32 rgvmodectl = I915_READ(MEMMODECTL);
8241         u8 fmax, fmin, fstart, vstart;
8242
8243         /* Enable temp reporting */
8244         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8245         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8246
8247         /* 100ms RC evaluation intervals */
8248         I915_WRITE(RCUPEI, 100000);
8249         I915_WRITE(RCDNEI, 100000);
8250
8251         /* Set max/min thresholds to 90ms and 80ms respectively */
8252         I915_WRITE(RCBMAXAVG, 90000);
8253         I915_WRITE(RCBMINAVG, 80000);
8254
8255         I915_WRITE(MEMIHYST, 1);
8256
8257         /* Set up min, max, and cur for interrupt handling */
8258         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8259         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8260         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8261                 MEMMODE_FSTART_SHIFT;
8262
8263         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8264                 PXVFREQ_PX_SHIFT;
8265
8266         dev_priv->fmax = fmax; /* IPS callback will increase this */
8267         dev_priv->fstart = fstart;
8268
8269         dev_priv->max_delay = fstart;
8270         dev_priv->min_delay = fmin;
8271         dev_priv->cur_delay = fstart;
8272
8273         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8274                          fmax, fmin, fstart);
8275
8276         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8277
8278         /*
8279          * Interrupts will be enabled in ironlake_irq_postinstall
8280          */
8281
8282         I915_WRITE(VIDSTART, vstart);
8283         POSTING_READ(VIDSTART);
8284
8285         rgvmodectl |= MEMMODE_SWMODE_EN;
8286         I915_WRITE(MEMMODECTL, rgvmodectl);
8287
8288         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8289                 DRM_ERROR("stuck trying to change perf mode\n");
8290         msleep(1);
8291
8292         ironlake_set_drps(dev, fstart);
8293
8294         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8295                 I915_READ(0x112e0);
8296         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8297         dev_priv->last_count2 = I915_READ(0x112f4);
8298         getrawmonotonic(&dev_priv->last_time2);
8299 }
8300
8301 void ironlake_disable_drps(struct drm_device *dev)
8302 {
8303         struct drm_i915_private *dev_priv = dev->dev_private;
8304         u16 rgvswctl = I915_READ16(MEMSWCTL);
8305
8306         /* Ack interrupts, disable EFC interrupt */
8307         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8308         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8309         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8310         I915_WRITE(DEIIR, DE_PCU_EVENT);
8311         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8312
8313         /* Go back to the starting frequency */
8314         ironlake_set_drps(dev, dev_priv->fstart);
8315         msleep(1);
8316         rgvswctl |= MEMCTL_CMD_STS;
8317         I915_WRITE(MEMSWCTL, rgvswctl);
8318         msleep(1);
8319
8320 }
8321
8322 void gen6_set_rps(struct drm_device *dev, u8 val)
8323 {
8324         struct drm_i915_private *dev_priv = dev->dev_private;
8325         u32 swreq;
8326
8327         swreq = (val & 0x3ff) << 25;
8328         I915_WRITE(GEN6_RPNSWREQ, swreq);
8329 }
8330
8331 void gen6_disable_rps(struct drm_device *dev)
8332 {
8333         struct drm_i915_private *dev_priv = dev->dev_private;
8334
8335         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8336         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8337         I915_WRITE(GEN6_PMIER, 0);
8338         /* Complete PM interrupt masking here doesn't race with the rps work
8339          * item again unmasking PM interrupts because that is using a different
8340          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8341          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8342
8343         spin_lock_irq(&dev_priv->rps_lock);
8344         dev_priv->pm_iir = 0;
8345         spin_unlock_irq(&dev_priv->rps_lock);
8346
8347         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8348 }
8349
8350 static unsigned long intel_pxfreq(u32 vidfreq)
8351 {
8352         unsigned long freq;
8353         int div = (vidfreq & 0x3f0000) >> 16;
8354         int post = (vidfreq & 0x3000) >> 12;
8355         int pre = (vidfreq & 0x7);
8356
8357         if (!pre)
8358                 return 0;
8359
8360         freq = ((div * 133333) / ((1<<post) * pre));
8361
8362         return freq;
8363 }
8364
8365 void intel_init_emon(struct drm_device *dev)
8366 {
8367         struct drm_i915_private *dev_priv = dev->dev_private;
8368         u32 lcfuse;
8369         u8 pxw[16];
8370         int i;
8371
8372         /* Disable to program */
8373         I915_WRITE(ECR, 0);
8374         POSTING_READ(ECR);
8375
8376         /* Program energy weights for various events */
8377         I915_WRITE(SDEW, 0x15040d00);
8378         I915_WRITE(CSIEW0, 0x007f0000);
8379         I915_WRITE(CSIEW1, 0x1e220004);
8380         I915_WRITE(CSIEW2, 0x04000004);
8381
8382         for (i = 0; i < 5; i++)
8383                 I915_WRITE(PEW + (i * 4), 0);
8384         for (i = 0; i < 3; i++)
8385                 I915_WRITE(DEW + (i * 4), 0);
8386
8387         /* Program P-state weights to account for frequency power adjustment */
8388         for (i = 0; i < 16; i++) {
8389                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8390                 unsigned long freq = intel_pxfreq(pxvidfreq);
8391                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8392                         PXVFREQ_PX_SHIFT;
8393                 unsigned long val;
8394
8395                 val = vid * vid;
8396                 val *= (freq / 1000);
8397                 val *= 255;
8398                 val /= (127*127*900);
8399                 if (val > 0xff)
8400                         DRM_ERROR("bad pxval: %ld\n", val);
8401                 pxw[i] = val;
8402         }
8403         /* Render standby states get 0 weight */
8404         pxw[14] = 0;
8405         pxw[15] = 0;
8406
8407         for (i = 0; i < 4; i++) {
8408                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8409                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8410                 I915_WRITE(PXW + (i * 4), val);
8411         }
8412
8413         /* Adjust magic regs to magic values (more experimental results) */
8414         I915_WRITE(OGW0, 0);
8415         I915_WRITE(OGW1, 0);
8416         I915_WRITE(EG0, 0x00007f00);
8417         I915_WRITE(EG1, 0x0000000e);
8418         I915_WRITE(EG2, 0x000e0000);
8419         I915_WRITE(EG3, 0x68000300);
8420         I915_WRITE(EG4, 0x42000000);
8421         I915_WRITE(EG5, 0x00140031);
8422         I915_WRITE(EG6, 0);
8423         I915_WRITE(EG7, 0);
8424
8425         for (i = 0; i < 8; i++)
8426                 I915_WRITE(PXWL + (i * 4), 0);
8427
8428         /* Enable PMON + select events */
8429         I915_WRITE(ECR, 0x80000019);
8430
8431         lcfuse = I915_READ(LCFUSE02);
8432
8433         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8434 }
8435
8436 static bool intel_enable_rc6(struct drm_device *dev)
8437 {
8438         /*
8439          * Respect the kernel parameter if it is set
8440          */
8441         if (i915_enable_rc6 >= 0)
8442                 return i915_enable_rc6;
8443
8444         /*
8445          * Disable RC6 on Ironlake
8446          */
8447         if (INTEL_INFO(dev)->gen == 5)
8448                 return 0;
8449
8450         /*
8451          * Disable rc6 on Sandybridge
8452          */
8453         if (INTEL_INFO(dev)->gen == 6) {
8454                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8455                 return 0;
8456         }
8457         DRM_DEBUG_DRIVER("RC6 enabled\n");
8458         return 1;
8459 }
8460
8461 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8462 {
8463         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8464         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8465         u32 pcu_mbox, rc6_mask = 0;
8466         u32 gtfifodbg;
8467         int cur_freq, min_freq, max_freq;
8468         int i;
8469
8470         /* Here begins a magic sequence of register writes to enable
8471          * auto-downclocking.
8472          *
8473          * Perhaps there might be some value in exposing these to
8474          * userspace...
8475          */
8476         I915_WRITE(GEN6_RC_STATE, 0);
8477         mutex_lock(&dev_priv->dev->struct_mutex);
8478
8479         /* Clear the DBG now so we don't confuse earlier errors */
8480         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8481                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8482                 I915_WRITE(GTFIFODBG, gtfifodbg);
8483         }
8484
8485         gen6_gt_force_wake_get(dev_priv);
8486
8487         /* disable the counters and set deterministic thresholds */
8488         I915_WRITE(GEN6_RC_CONTROL, 0);
8489
8490         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8491         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8492         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8493         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8494         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8495
8496         for (i = 0; i < I915_NUM_RINGS; i++)
8497                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8498
8499         I915_WRITE(GEN6_RC_SLEEP, 0);
8500         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8501         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8502         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8503         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8504
8505         if (intel_enable_rc6(dev_priv->dev))
8506                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8507                         GEN6_RC_CTL_RC6_ENABLE;
8508
8509         I915_WRITE(GEN6_RC_CONTROL,
8510                    rc6_mask |
8511                    GEN6_RC_CTL_EI_MODE(1) |
8512                    GEN6_RC_CTL_HW_ENABLE);
8513
8514         I915_WRITE(GEN6_RPNSWREQ,
8515                    GEN6_FREQUENCY(10) |
8516                    GEN6_OFFSET(0) |
8517                    GEN6_AGGRESSIVE_TURBO);
8518         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8519                    GEN6_FREQUENCY(12));
8520
8521         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8522         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8523                    18 << 24 |
8524                    6 << 16);
8525         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8526         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8527         I915_WRITE(GEN6_RP_UP_EI, 100000);
8528         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8529         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8530         I915_WRITE(GEN6_RP_CONTROL,
8531                    GEN6_RP_MEDIA_TURBO |
8532                    GEN6_RP_MEDIA_HW_MODE |
8533                    GEN6_RP_MEDIA_IS_GFX |
8534                    GEN6_RP_ENABLE |
8535                    GEN6_RP_UP_BUSY_AVG |
8536                    GEN6_RP_DOWN_IDLE_CONT);
8537
8538         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8539                      500))
8540                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8541
8542         I915_WRITE(GEN6_PCODE_DATA, 0);
8543         I915_WRITE(GEN6_PCODE_MAILBOX,
8544                    GEN6_PCODE_READY |
8545                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8546         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8547                      500))
8548                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8549
8550         min_freq = (rp_state_cap & 0xff0000) >> 16;
8551         max_freq = rp_state_cap & 0xff;
8552         cur_freq = (gt_perf_status & 0xff00) >> 8;
8553
8554         /* Check for overclock support */
8555         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8556                      500))
8557                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8558         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8559         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8560         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8561                      500))
8562                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8563         if (pcu_mbox & (1<<31)) { /* OC supported */
8564                 max_freq = pcu_mbox & 0xff;
8565                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8566         }
8567
8568         /* In units of 100MHz */
8569         dev_priv->max_delay = max_freq;
8570         dev_priv->min_delay = min_freq;
8571         dev_priv->cur_delay = cur_freq;
8572
8573         /* requires MSI enabled */
8574         I915_WRITE(GEN6_PMIER,
8575                    GEN6_PM_MBOX_EVENT |
8576                    GEN6_PM_THERMAL_EVENT |
8577                    GEN6_PM_RP_DOWN_TIMEOUT |
8578                    GEN6_PM_RP_UP_THRESHOLD |
8579                    GEN6_PM_RP_DOWN_THRESHOLD |
8580                    GEN6_PM_RP_UP_EI_EXPIRED |
8581                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8582         spin_lock_irq(&dev_priv->rps_lock);
8583         WARN_ON(dev_priv->pm_iir != 0);
8584         I915_WRITE(GEN6_PMIMR, 0);
8585         spin_unlock_irq(&dev_priv->rps_lock);
8586         /* enable all PM interrupts */
8587         I915_WRITE(GEN6_PMINTRMSK, 0);
8588
8589         gen6_gt_force_wake_put(dev_priv);
8590         mutex_unlock(&dev_priv->dev->struct_mutex);
8591 }
8592
8593 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8594 {
8595         int min_freq = 15;
8596         int gpu_freq, ia_freq, max_ia_freq;
8597         int scaling_factor = 180;
8598
8599         max_ia_freq = cpufreq_quick_get_max(0);
8600         /*
8601          * Default to measured freq if none found, PCU will ensure we don't go
8602          * over
8603          */
8604         if (!max_ia_freq)
8605                 max_ia_freq = tsc_khz;
8606
8607         /* Convert from kHz to MHz */
8608         max_ia_freq /= 1000;
8609
8610         mutex_lock(&dev_priv->dev->struct_mutex);
8611
8612         /*
8613          * For each potential GPU frequency, load a ring frequency we'd like
8614          * to use for memory access.  We do this by specifying the IA frequency
8615          * the PCU should use as a reference to determine the ring frequency.
8616          */
8617         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8618              gpu_freq--) {
8619                 int diff = dev_priv->max_delay - gpu_freq;
8620
8621                 /*
8622                  * For GPU frequencies less than 750MHz, just use the lowest
8623                  * ring freq.
8624                  */
8625                 if (gpu_freq < min_freq)
8626                         ia_freq = 800;
8627                 else
8628                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8629                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8630
8631                 I915_WRITE(GEN6_PCODE_DATA,
8632                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8633                            gpu_freq);
8634                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8635                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8636                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8637                               GEN6_PCODE_READY) == 0, 10)) {
8638                         DRM_ERROR("pcode write of freq table timed out\n");
8639                         continue;
8640                 }
8641         }
8642
8643         mutex_unlock(&dev_priv->dev->struct_mutex);
8644 }
8645
8646 static void ironlake_init_clock_gating(struct drm_device *dev)
8647 {
8648         struct drm_i915_private *dev_priv = dev->dev_private;
8649         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8650
8651         /* Required for FBC */
8652         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8653                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8654                 DPFDUNIT_CLOCK_GATE_DISABLE;
8655         /* Required for CxSR */
8656         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8657
8658         I915_WRITE(PCH_3DCGDIS0,
8659                    MARIUNIT_CLOCK_GATE_DISABLE |
8660                    SVSMUNIT_CLOCK_GATE_DISABLE);
8661         I915_WRITE(PCH_3DCGDIS1,
8662                    VFMUNIT_CLOCK_GATE_DISABLE);
8663
8664         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8665
8666         /*
8667          * According to the spec the following bits should be set in
8668          * order to enable memory self-refresh
8669          * The bit 22/21 of 0x42004
8670          * The bit 5 of 0x42020
8671          * The bit 15 of 0x45000
8672          */
8673         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8674                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8675                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8676         I915_WRITE(ILK_DSPCLK_GATE,
8677                    (I915_READ(ILK_DSPCLK_GATE) |
8678                     ILK_DPARB_CLK_GATE));
8679         I915_WRITE(DISP_ARB_CTL,
8680                    (I915_READ(DISP_ARB_CTL) |
8681                     DISP_FBC_WM_DIS));
8682         I915_WRITE(WM3_LP_ILK, 0);
8683         I915_WRITE(WM2_LP_ILK, 0);
8684         I915_WRITE(WM1_LP_ILK, 0);
8685
8686         /*
8687          * Based on the document from hardware guys the following bits
8688          * should be set unconditionally in order to enable FBC.
8689          * The bit 22 of 0x42000
8690          * The bit 22 of 0x42004
8691          * The bit 7,8,9 of 0x42020.
8692          */
8693         if (IS_IRONLAKE_M(dev)) {
8694                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8695                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8696                            ILK_FBCQ_DIS);
8697                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8698                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8699                            ILK_DPARB_GATE);
8700                 I915_WRITE(ILK_DSPCLK_GATE,
8701                            I915_READ(ILK_DSPCLK_GATE) |
8702                            ILK_DPFC_DIS1 |
8703                            ILK_DPFC_DIS2 |
8704                            ILK_CLK_FBC);
8705         }
8706
8707         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8708                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8709                    ILK_ELPIN_409_SELECT);
8710         I915_WRITE(_3D_CHICKEN2,
8711                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8712                    _3D_CHICKEN2_WM_READ_PIPELINED);
8713 }
8714
8715 static void gen6_init_clock_gating(struct drm_device *dev)
8716 {
8717         struct drm_i915_private *dev_priv = dev->dev_private;
8718         int pipe;
8719         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8720
8721         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8722
8723         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8724                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8725                    ILK_ELPIN_409_SELECT);
8726
8727         I915_WRITE(WM3_LP_ILK, 0);
8728         I915_WRITE(WM2_LP_ILK, 0);
8729         I915_WRITE(WM1_LP_ILK, 0);
8730
8731         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8732          * gating disable must be set.  Failure to set it results in
8733          * flickering pixels due to Z write ordering failures after
8734          * some amount of runtime in the Mesa "fire" demo, and Unigine
8735          * Sanctuary and Tropics, and apparently anything else with
8736          * alpha test or pixel discard.
8737          *
8738          * According to the spec, bit 11 (RCCUNIT) must also be set,
8739          * but we didn't debug actual testcases to find it out.
8740          */
8741         I915_WRITE(GEN6_UCGCTL2,
8742                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8743                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8744
8745         /*
8746          * According to the spec the following bits should be
8747          * set in order to enable memory self-refresh and fbc:
8748          * The bit21 and bit22 of 0x42000
8749          * The bit21 and bit22 of 0x42004
8750          * The bit5 and bit7 of 0x42020
8751          * The bit14 of 0x70180
8752          * The bit14 of 0x71180
8753          */
8754         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8755                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8756                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8757         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8758                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8759                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8760         I915_WRITE(ILK_DSPCLK_GATE,
8761                    I915_READ(ILK_DSPCLK_GATE) |
8762                    ILK_DPARB_CLK_GATE  |
8763                    ILK_DPFD_CLK_GATE);
8764
8765         for_each_pipe(pipe) {
8766                 I915_WRITE(DSPCNTR(pipe),
8767                            I915_READ(DSPCNTR(pipe)) |
8768                            DISPPLANE_TRICKLE_FEED_DISABLE);
8769                 intel_flush_display_plane(dev_priv, pipe);
8770         }
8771 }
8772
8773 static void ivybridge_init_clock_gating(struct drm_device *dev)
8774 {
8775         struct drm_i915_private *dev_priv = dev->dev_private;
8776         int pipe;
8777         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8778
8779         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8780
8781         I915_WRITE(WM3_LP_ILK, 0);
8782         I915_WRITE(WM2_LP_ILK, 0);
8783         I915_WRITE(WM1_LP_ILK, 0);
8784
8785         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8786
8787         I915_WRITE(IVB_CHICKEN3,
8788                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8789                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8790
8791         for_each_pipe(pipe) {
8792                 I915_WRITE(DSPCNTR(pipe),
8793                            I915_READ(DSPCNTR(pipe)) |
8794                            DISPPLANE_TRICKLE_FEED_DISABLE);
8795                 intel_flush_display_plane(dev_priv, pipe);
8796         }
8797 }
8798
8799 static void valleyview_init_clock_gating(struct drm_device *dev)
8800 {
8801         struct drm_i915_private *dev_priv = dev->dev_private;
8802         int pipe;
8803         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8804
8805         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8806
8807         I915_WRITE(WM3_LP_ILK, 0);
8808         I915_WRITE(WM2_LP_ILK, 0);
8809         I915_WRITE(WM1_LP_ILK, 0);
8810
8811         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8812          * This implements the WaDisableRCZUnitClockGating workaround.
8813          */
8814         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8815
8816         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8817
8818         I915_WRITE(IVB_CHICKEN3,
8819                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8820                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8821
8822         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8823         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8824                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8825
8826         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8827         I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
8828         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
8829
8830         /* This is required by WaCatErrorRejectionIssue */
8831         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8832                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8833                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8834
8835         for_each_pipe(pipe) {
8836                 I915_WRITE(DSPCNTR(pipe),
8837                            I915_READ(DSPCNTR(pipe)) |
8838                            DISPPLANE_TRICKLE_FEED_DISABLE);
8839                 intel_flush_display_plane(dev_priv, pipe);
8840         }
8841
8842         I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
8843                    (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
8844                    PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
8845 }
8846
8847 static void g4x_init_clock_gating(struct drm_device *dev)
8848 {
8849         struct drm_i915_private *dev_priv = dev->dev_private;
8850         uint32_t dspclk_gate;
8851
8852         I915_WRITE(RENCLK_GATE_D1, 0);
8853         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8854                    GS_UNIT_CLOCK_GATE_DISABLE |
8855                    CL_UNIT_CLOCK_GATE_DISABLE);
8856         I915_WRITE(RAMCLK_GATE_D, 0);
8857         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8858                 OVRUNIT_CLOCK_GATE_DISABLE |
8859                 OVCUNIT_CLOCK_GATE_DISABLE;
8860         if (IS_GM45(dev))
8861                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8862         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8863 }
8864
8865 static void crestline_init_clock_gating(struct drm_device *dev)
8866 {
8867         struct drm_i915_private *dev_priv = dev->dev_private;
8868
8869         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8870         I915_WRITE(RENCLK_GATE_D2, 0);
8871         I915_WRITE(DSPCLK_GATE_D, 0);
8872         I915_WRITE(RAMCLK_GATE_D, 0);
8873         I915_WRITE16(DEUC, 0);
8874 }
8875
8876 static void broadwater_init_clock_gating(struct drm_device *dev)
8877 {
8878         struct drm_i915_private *dev_priv = dev->dev_private;
8879
8880         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8881                    I965_RCC_CLOCK_GATE_DISABLE |
8882                    I965_RCPB_CLOCK_GATE_DISABLE |
8883                    I965_ISC_CLOCK_GATE_DISABLE |
8884                    I965_FBC_CLOCK_GATE_DISABLE);
8885         I915_WRITE(RENCLK_GATE_D2, 0);
8886 }
8887
8888 static void gen3_init_clock_gating(struct drm_device *dev)
8889 {
8890         struct drm_i915_private *dev_priv = dev->dev_private;
8891         u32 dstate = I915_READ(D_STATE);
8892
8893         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8894                 DSTATE_DOT_CLOCK_GATING;
8895         I915_WRITE(D_STATE, dstate);
8896 }
8897
8898 static void i85x_init_clock_gating(struct drm_device *dev)
8899 {
8900         struct drm_i915_private *dev_priv = dev->dev_private;
8901
8902         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8903 }
8904
8905 static void i830_init_clock_gating(struct drm_device *dev)
8906 {
8907         struct drm_i915_private *dev_priv = dev->dev_private;
8908
8909         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8910 }
8911
8912 static void ibx_init_clock_gating(struct drm_device *dev)
8913 {
8914         struct drm_i915_private *dev_priv = dev->dev_private;
8915
8916         /*
8917          * On Ibex Peak and Cougar Point, we need to disable clock
8918          * gating for the panel power sequencer or it will fail to
8919          * start up when no ports are active.
8920          */
8921         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8922 }
8923
8924 static void cpt_init_clock_gating(struct drm_device *dev)
8925 {
8926         struct drm_i915_private *dev_priv = dev->dev_private;
8927         int pipe;
8928
8929         /*
8930          * On Ibex Peak and Cougar Point, we need to disable clock
8931          * gating for the panel power sequencer or it will fail to
8932          * start up when no ports are active.
8933          */
8934         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8935         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8936                    DPLS_EDP_PPS_FIX_DIS);
8937         /* Without this, mode sets may fail silently on FDI */
8938         for_each_pipe(pipe)
8939                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8940 }
8941
8942 static void ironlake_teardown_rc6(struct drm_device *dev)
8943 {
8944         struct drm_i915_private *dev_priv = dev->dev_private;
8945
8946         if (dev_priv->renderctx) {
8947                 i915_gem_object_unpin(dev_priv->renderctx);
8948                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8949                 dev_priv->renderctx = NULL;
8950         }
8951
8952         if (dev_priv->pwrctx) {
8953                 i915_gem_object_unpin(dev_priv->pwrctx);
8954                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8955                 dev_priv->pwrctx = NULL;
8956         }
8957 }
8958
8959 static void ironlake_disable_rc6(struct drm_device *dev)
8960 {
8961         struct drm_i915_private *dev_priv = dev->dev_private;
8962
8963         if (I915_READ(PWRCTXA)) {
8964                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8965                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8966                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8967                          50);
8968
8969                 I915_WRITE(PWRCTXA, 0);
8970                 POSTING_READ(PWRCTXA);
8971
8972                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8973                 POSTING_READ(RSTDBYCTL);
8974         }
8975
8976         ironlake_teardown_rc6(dev);
8977 }
8978
8979 static int ironlake_setup_rc6(struct drm_device *dev)
8980 {
8981         struct drm_i915_private *dev_priv = dev->dev_private;
8982
8983         if (dev_priv->renderctx == NULL)
8984                 dev_priv->renderctx = intel_alloc_context_page(dev);
8985         if (!dev_priv->renderctx)
8986                 return -ENOMEM;
8987
8988         if (dev_priv->pwrctx == NULL)
8989                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8990         if (!dev_priv->pwrctx) {
8991                 ironlake_teardown_rc6(dev);
8992                 return -ENOMEM;
8993         }
8994
8995         return 0;
8996 }
8997
8998 void ironlake_enable_rc6(struct drm_device *dev)
8999 {
9000         struct drm_i915_private *dev_priv = dev->dev_private;
9001         int ret;
9002
9003         /* rc6 disabled by default due to repeated reports of hanging during
9004          * boot and resume.
9005          */
9006         if (!intel_enable_rc6(dev))
9007                 return;
9008
9009         mutex_lock(&dev->struct_mutex);
9010         ret = ironlake_setup_rc6(dev);
9011         if (ret) {
9012                 mutex_unlock(&dev->struct_mutex);
9013                 return;
9014         }
9015
9016         /*
9017          * GPU can automatically power down the render unit if given a page
9018          * to save state.
9019          */
9020         ret = BEGIN_LP_RING(6);
9021         if (ret) {
9022                 ironlake_teardown_rc6(dev);
9023                 mutex_unlock(&dev->struct_mutex);
9024                 return;
9025         }
9026
9027         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
9028         OUT_RING(MI_SET_CONTEXT);
9029         OUT_RING(dev_priv->renderctx->gtt_offset |
9030                  MI_MM_SPACE_GTT |
9031                  MI_SAVE_EXT_STATE_EN |
9032                  MI_RESTORE_EXT_STATE_EN |
9033                  MI_RESTORE_INHIBIT);
9034         OUT_RING(MI_SUSPEND_FLUSH);
9035         OUT_RING(MI_NOOP);
9036         OUT_RING(MI_FLUSH);
9037         ADVANCE_LP_RING();
9038
9039         /*
9040          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
9041          * does an implicit flush, combined with MI_FLUSH above, it should be
9042          * safe to assume that renderctx is valid
9043          */
9044         ret = intel_wait_ring_idle(LP_RING(dev_priv));
9045         if (ret) {
9046                 DRM_ERROR("failed to enable ironlake power power savings\n");
9047                 ironlake_teardown_rc6(dev);
9048                 mutex_unlock(&dev->struct_mutex);
9049                 return;
9050         }
9051
9052         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
9053         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
9054         mutex_unlock(&dev->struct_mutex);
9055 }
9056
9057 void intel_init_clock_gating(struct drm_device *dev)
9058 {
9059         struct drm_i915_private *dev_priv = dev->dev_private;
9060
9061         dev_priv->display.init_clock_gating(dev);
9062
9063         if (dev_priv->display.init_pch_clock_gating)
9064                 dev_priv->display.init_pch_clock_gating(dev);
9065 }
9066
9067 /* Set up chip specific display functions */
9068 static void intel_init_display(struct drm_device *dev)
9069 {
9070         struct drm_i915_private *dev_priv = dev->dev_private;
9071
9072         /* We always want a DPMS function */
9073         if (HAS_PCH_SPLIT(dev)) {
9074                 dev_priv->display.dpms = ironlake_crtc_dpms;
9075                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9076                 dev_priv->display.update_plane = ironlake_update_plane;
9077         } else {
9078                 dev_priv->display.dpms = i9xx_crtc_dpms;
9079                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9080                 dev_priv->display.update_plane = i9xx_update_plane;
9081         }
9082
9083         if (I915_HAS_FBC(dev)) {
9084                 if (HAS_PCH_SPLIT(dev)) {
9085                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
9086                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
9087                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
9088                 } else if (IS_GM45(dev)) {
9089                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
9090                         dev_priv->display.enable_fbc = g4x_enable_fbc;
9091                         dev_priv->display.disable_fbc = g4x_disable_fbc;
9092                 } else if (IS_CRESTLINE(dev)) {
9093                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
9094                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
9095                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
9096                 }
9097                 /* 855GM needs testing */
9098         }
9099
9100         /* Returns the core display clock speed */
9101         if (IS_VALLEYVIEW(dev))
9102                 dev_priv->display.get_display_clock_speed =
9103                         valleyview_get_display_clock_speed;
9104         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9105                 dev_priv->display.get_display_clock_speed =
9106                         i945_get_display_clock_speed;
9107         else if (IS_I915G(dev))
9108                 dev_priv->display.get_display_clock_speed =
9109                         i915_get_display_clock_speed;
9110         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9111                 dev_priv->display.get_display_clock_speed =
9112                         i9xx_misc_get_display_clock_speed;
9113         else if (IS_I915GM(dev))
9114                 dev_priv->display.get_display_clock_speed =
9115                         i915gm_get_display_clock_speed;
9116         else if (IS_I865G(dev))
9117                 dev_priv->display.get_display_clock_speed =
9118                         i865_get_display_clock_speed;
9119         else if (IS_I85X(dev))
9120                 dev_priv->display.get_display_clock_speed =
9121                         i855_get_display_clock_speed;
9122         else /* 852, 830 */
9123                 dev_priv->display.get_display_clock_speed =
9124                         i830_get_display_clock_speed;
9125
9126         /* For FIFO watermark updates */
9127         if (HAS_PCH_SPLIT(dev)) {
9128                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9129                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9130
9131                 /* IVB configs may use multi-threaded forcewake */
9132                 if (IS_IVYBRIDGE(dev)) {
9133                         u32     ecobus;
9134
9135                         /* A small trick here - if the bios hasn't configured MT forcewake,
9136                          * and if the device is in RC6, then force_wake_mt_get will not wake
9137                          * the device and the ECOBUS read will return zero. Which will be
9138                          * (correctly) interpreted by the test below as MT forcewake being
9139                          * disabled.
9140                          */
9141                         mutex_lock(&dev->struct_mutex);
9142                         __gen6_gt_force_wake_mt_get(dev_priv);
9143                         ecobus = I915_READ_NOTRACE(ECOBUS);
9144                         __gen6_gt_force_wake_mt_put(dev_priv);
9145                         mutex_unlock(&dev->struct_mutex);
9146
9147                         if (ecobus & FORCEWAKE_MT_ENABLE) {
9148                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9149                                 dev_priv->display.force_wake_get =
9150                                         __gen6_gt_force_wake_mt_get;
9151                                 dev_priv->display.force_wake_put =
9152                                         __gen6_gt_force_wake_mt_put;
9153                         }
9154                 }
9155
9156                 if (HAS_PCH_IBX(dev))
9157                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9158                 else if (HAS_PCH_CPT(dev))
9159                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9160
9161                 if (IS_GEN5(dev)) {
9162                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9163                                 dev_priv->display.update_wm = ironlake_update_wm;
9164                         else {
9165                                 DRM_DEBUG_KMS("Failed to get proper latency. "
9166                                               "Disable CxSR\n");
9167                                 dev_priv->display.update_wm = NULL;
9168                         }
9169                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9170                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
9171                         dev_priv->display.write_eld = ironlake_write_eld;
9172                 } else if (IS_GEN6(dev)) {
9173                         if (SNB_READ_WM0_LATENCY()) {
9174                                 dev_priv->display.update_wm = sandybridge_update_wm;
9175                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9176                         } else {
9177                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9178                                               "Disable CxSR\n");
9179                                 dev_priv->display.update_wm = NULL;
9180                         }
9181                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9182                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9183                         dev_priv->display.write_eld = ironlake_write_eld;
9184                 } else if (IS_IVYBRIDGE(dev)) {
9185                         /* FIXME: detect B0+ stepping and use auto training */
9186                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9187                         if (SNB_READ_WM0_LATENCY()) {
9188                                 dev_priv->display.update_wm = sandybridge_update_wm;
9189                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9190                         } else {
9191                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9192                                               "Disable CxSR\n");
9193                                 dev_priv->display.update_wm = NULL;
9194                         }
9195                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9196                         dev_priv->display.write_eld = ironlake_write_eld;
9197                 } else
9198                         dev_priv->display.update_wm = NULL;
9199         } else if (IS_VALLEYVIEW(dev)) {
9200                 dev_priv->display.update_wm = valleyview_update_wm;
9201                 dev_priv->display.init_clock_gating =
9202                         valleyview_init_clock_gating;
9203         } else if (IS_PINEVIEW(dev)) {
9204                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9205                                             dev_priv->is_ddr3,
9206                                             dev_priv->fsb_freq,
9207                                             dev_priv->mem_freq)) {
9208                         DRM_INFO("failed to find known CxSR latency "
9209                                  "(found ddr%s fsb freq %d, mem freq %d), "
9210                                  "disabling CxSR\n",
9211                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9212                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9213                         /* Disable CxSR and never update its watermark again */
9214                         pineview_disable_cxsr(dev);
9215                         dev_priv->display.update_wm = NULL;
9216                 } else
9217                         dev_priv->display.update_wm = pineview_update_wm;
9218                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9219         } else if (IS_G4X(dev)) {
9220                 dev_priv->display.write_eld = g4x_write_eld;
9221                 dev_priv->display.update_wm = g4x_update_wm;
9222                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9223         } else if (IS_GEN4(dev)) {
9224                 dev_priv->display.update_wm = i965_update_wm;
9225                 if (IS_CRESTLINE(dev))
9226                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9227                 else if (IS_BROADWATER(dev))
9228                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9229         } else if (IS_GEN3(dev)) {
9230                 dev_priv->display.update_wm = i9xx_update_wm;
9231                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9232                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9233         } else if (IS_I865G(dev)) {
9234                 dev_priv->display.update_wm = i830_update_wm;
9235                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9236                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9237         } else if (IS_I85X(dev)) {
9238                 dev_priv->display.update_wm = i9xx_update_wm;
9239                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9240                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9241         } else {
9242                 dev_priv->display.update_wm = i830_update_wm;
9243                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9244                 if (IS_845G(dev))
9245                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9246                 else
9247                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9248         }
9249
9250         /* Default just returns -ENODEV to indicate unsupported */
9251         dev_priv->display.queue_flip = intel_default_queue_flip;
9252
9253         switch (INTEL_INFO(dev)->gen) {
9254         case 2:
9255                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9256                 break;
9257
9258         case 3:
9259                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9260                 break;
9261
9262         case 4:
9263         case 5:
9264                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9265                 break;
9266
9267         case 6:
9268                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9269                 break;
9270         case 7:
9271                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9272                 break;
9273         }
9274 }
9275
9276 /*
9277  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9278  * resume, or other times.  This quirk makes sure that's the case for
9279  * affected systems.
9280  */
9281 static void quirk_pipea_force(struct drm_device *dev)
9282 {
9283         struct drm_i915_private *dev_priv = dev->dev_private;
9284
9285         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9286         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9287 }
9288
9289 /*
9290  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9291  */
9292 static void quirk_ssc_force_disable(struct drm_device *dev)
9293 {
9294         struct drm_i915_private *dev_priv = dev->dev_private;
9295         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9296 }
9297
9298 /*
9299  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9300  * brightness value
9301  */
9302 static void quirk_invert_brightness(struct drm_device *dev)
9303 {
9304         struct drm_i915_private *dev_priv = dev->dev_private;
9305         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9306 }
9307
9308 struct intel_quirk {
9309         int device;
9310         int subsystem_vendor;
9311         int subsystem_device;
9312         void (*hook)(struct drm_device *dev);
9313 };
9314
9315 struct intel_quirk intel_quirks[] = {
9316         /* HP Mini needs pipe A force quirk (LP: #322104) */
9317         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9318
9319         /* Thinkpad R31 needs pipe A force quirk */
9320         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9321         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9322         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9323
9324         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9325         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9326         /* ThinkPad X40 needs pipe A force quirk */
9327
9328         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9329         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9330
9331         /* 855 & before need to leave pipe A & dpll A up */
9332         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9333         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9334
9335         /* Lenovo U160 cannot use SSC on LVDS */
9336         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9337
9338         /* Sony Vaio Y cannot use SSC on LVDS */
9339         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9340
9341         /* Acer Aspire 5734Z must invert backlight brightness */
9342         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9343 };
9344
9345 static void intel_init_quirks(struct drm_device *dev)
9346 {
9347         struct pci_dev *d = dev->pdev;
9348         int i;
9349
9350         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9351                 struct intel_quirk *q = &intel_quirks[i];
9352
9353                 if (d->device == q->device &&
9354                     (d->subsystem_vendor == q->subsystem_vendor ||
9355                      q->subsystem_vendor == PCI_ANY_ID) &&
9356                     (d->subsystem_device == q->subsystem_device ||
9357                      q->subsystem_device == PCI_ANY_ID))
9358                         q->hook(dev);
9359         }
9360 }
9361
9362 /* Disable the VGA plane that we never use */
9363 static void i915_disable_vga(struct drm_device *dev)
9364 {
9365         struct drm_i915_private *dev_priv = dev->dev_private;
9366         u8 sr1;
9367         u32 vga_reg;
9368
9369         if (HAS_PCH_SPLIT(dev))
9370                 vga_reg = CPU_VGACNTRL;
9371         else
9372                 vga_reg = VGACNTRL;
9373
9374         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9375         outb(1, VGA_SR_INDEX);
9376         sr1 = inb(VGA_SR_DATA);
9377         outb(sr1 | 1<<5, VGA_SR_DATA);
9378         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9379         udelay(300);
9380
9381         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9382         POSTING_READ(vga_reg);
9383 }
9384
9385 void intel_modeset_init(struct drm_device *dev)
9386 {
9387         struct drm_i915_private *dev_priv = dev->dev_private;
9388         int i, ret;
9389
9390         drm_mode_config_init(dev);
9391
9392         dev->mode_config.min_width = 0;
9393         dev->mode_config.min_height = 0;
9394
9395         dev->mode_config.preferred_depth = 24;
9396         dev->mode_config.prefer_shadow = 1;
9397
9398         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9399
9400         intel_init_quirks(dev);
9401
9402         intel_init_display(dev);
9403
9404         if (IS_GEN2(dev)) {
9405                 dev->mode_config.max_width = 2048;
9406                 dev->mode_config.max_height = 2048;
9407         } else if (IS_GEN3(dev)) {
9408                 dev->mode_config.max_width = 4096;
9409                 dev->mode_config.max_height = 4096;
9410         } else {
9411                 dev->mode_config.max_width = 8192;
9412                 dev->mode_config.max_height = 8192;
9413         }
9414         dev->mode_config.fb_base = dev->agp->base;
9415
9416         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9417                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9418
9419         for (i = 0; i < dev_priv->num_pipe; i++) {
9420                 intel_crtc_init(dev, i);
9421                 ret = intel_plane_init(dev, i);
9422                 if (ret)
9423                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9424         }
9425
9426         /* Just disable it once at startup */
9427         i915_disable_vga(dev);
9428         intel_setup_outputs(dev);
9429
9430         intel_init_clock_gating(dev);
9431
9432         if (IS_IRONLAKE_M(dev)) {
9433                 ironlake_enable_drps(dev);
9434                 intel_init_emon(dev);
9435         }
9436
9437         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9438                 gen6_enable_rps(dev_priv);
9439                 gen6_update_ring_freq(dev_priv);
9440         }
9441
9442         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9443         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9444                     (unsigned long)dev);
9445 }
9446
9447 void intel_modeset_gem_init(struct drm_device *dev)
9448 {
9449         if (IS_IRONLAKE_M(dev))
9450                 ironlake_enable_rc6(dev);
9451
9452         intel_setup_overlay(dev);
9453 }
9454
9455 void intel_modeset_cleanup(struct drm_device *dev)
9456 {
9457         struct drm_i915_private *dev_priv = dev->dev_private;
9458         struct drm_crtc *crtc;
9459         struct intel_crtc *intel_crtc;
9460
9461         drm_kms_helper_poll_fini(dev);
9462         mutex_lock(&dev->struct_mutex);
9463
9464         intel_unregister_dsm_handler();
9465
9466
9467         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9468                 /* Skip inactive CRTCs */
9469                 if (!crtc->fb)
9470                         continue;
9471
9472                 intel_crtc = to_intel_crtc(crtc);
9473                 intel_increase_pllclock(crtc);
9474         }
9475
9476         intel_disable_fbc(dev);
9477
9478         if (IS_IRONLAKE_M(dev))
9479                 ironlake_disable_drps(dev);
9480         if (IS_GEN6(dev) || IS_GEN7(dev))
9481                 gen6_disable_rps(dev);
9482
9483         if (IS_IRONLAKE_M(dev))
9484                 ironlake_disable_rc6(dev);
9485
9486         if (IS_VALLEYVIEW(dev))
9487                 vlv_init_dpio(dev);
9488
9489         mutex_unlock(&dev->struct_mutex);
9490
9491         /* Disable the irq before mode object teardown, for the irq might
9492          * enqueue unpin/hotplug work. */
9493         drm_irq_uninstall(dev);
9494         cancel_work_sync(&dev_priv->hotplug_work);
9495         cancel_work_sync(&dev_priv->rps_work);
9496
9497         /* flush any delayed tasks or pending work */
9498         flush_scheduled_work();
9499
9500         /* Shut off idle work before the crtcs get freed. */
9501         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9502                 intel_crtc = to_intel_crtc(crtc);
9503                 del_timer_sync(&intel_crtc->idle_timer);
9504         }
9505         del_timer_sync(&dev_priv->idle_timer);
9506         cancel_work_sync(&dev_priv->idle_work);
9507
9508         drm_mode_config_cleanup(dev);
9509 }
9510
9511 /*
9512  * Return which encoder is currently attached for connector.
9513  */
9514 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9515 {
9516         return &intel_attached_encoder(connector)->base;
9517 }
9518
9519 void intel_connector_attach_encoder(struct intel_connector *connector,
9520                                     struct intel_encoder *encoder)
9521 {
9522         connector->encoder = encoder;
9523         drm_mode_connector_attach_encoder(&connector->base,
9524                                           &encoder->base);
9525 }
9526
9527 /*
9528  * set vga decode state - true == enable VGA decode
9529  */
9530 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9531 {
9532         struct drm_i915_private *dev_priv = dev->dev_private;
9533         u16 gmch_ctrl;
9534
9535         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9536         if (state)
9537                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9538         else
9539                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9540         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9541         return 0;
9542 }
9543
9544 #ifdef CONFIG_DEBUG_FS
9545 #include <linux/seq_file.h>
9546
9547 struct intel_display_error_state {
9548         struct intel_cursor_error_state {
9549                 u32 control;
9550                 u32 position;
9551                 u32 base;
9552                 u32 size;
9553         } cursor[2];
9554
9555         struct intel_pipe_error_state {
9556                 u32 conf;
9557                 u32 source;
9558
9559                 u32 htotal;
9560                 u32 hblank;
9561                 u32 hsync;
9562                 u32 vtotal;
9563                 u32 vblank;
9564                 u32 vsync;
9565         } pipe[2];
9566
9567         struct intel_plane_error_state {
9568                 u32 control;
9569                 u32 stride;
9570                 u32 size;
9571                 u32 pos;
9572                 u32 addr;
9573                 u32 surface;
9574                 u32 tile_offset;
9575         } plane[2];
9576 };
9577
9578 struct intel_display_error_state *
9579 intel_display_capture_error_state(struct drm_device *dev)
9580 {
9581         drm_i915_private_t *dev_priv = dev->dev_private;
9582         struct intel_display_error_state *error;
9583         int i;
9584
9585         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9586         if (error == NULL)
9587                 return NULL;
9588
9589         for (i = 0; i < 2; i++) {
9590                 error->cursor[i].control = I915_READ(CURCNTR(i));
9591                 error->cursor[i].position = I915_READ(CURPOS(i));
9592                 error->cursor[i].base = I915_READ(CURBASE(i));
9593
9594                 error->plane[i].control = I915_READ(DSPCNTR(i));
9595                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9596                 error->plane[i].size = I915_READ(DSPSIZE(i));
9597                 error->plane[i].pos = I915_READ(DSPPOS(i));
9598                 error->plane[i].addr = I915_READ(DSPADDR(i));
9599                 if (INTEL_INFO(dev)->gen >= 4) {
9600                         error->plane[i].surface = I915_READ(DSPSURF(i));
9601                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9602                 }
9603
9604                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9605                 error->pipe[i].source = I915_READ(PIPESRC(i));
9606                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9607                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9608                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9609                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9610                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9611                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9612         }
9613
9614         return error;
9615 }
9616
9617 void
9618 intel_display_print_error_state(struct seq_file *m,
9619                                 struct drm_device *dev,
9620                                 struct intel_display_error_state *error)
9621 {
9622         int i;
9623
9624         for (i = 0; i < 2; i++) {
9625                 seq_printf(m, "Pipe [%d]:\n", i);
9626                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9627                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9628                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9629                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9630                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9631                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9632                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9633                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9634
9635                 seq_printf(m, "Plane [%d]:\n", i);
9636                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9637                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9638                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9639                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9640                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9641                 if (INTEL_INFO(dev)->gen >= 4) {
9642                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9643                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9644                 }
9645
9646                 seq_printf(m, "Cursor [%d]:\n", i);
9647                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9648                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9649                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9650         }
9651 }
9652 #endif