drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *best_clock);
  90
  91 static bool
  92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  93                       int target, int refclk, intel_clock_t *best_clock);
  94 static bool
  95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  96                            int target, int refclk, intel_clock_t *best_clock);
  97
  98 static inline u32 /* units of 100MHz */
  99 intel_fdi_link_freq(struct drm_device *dev)
 100 {
 101         if (IS_GEN5(dev)) {
 102                 struct drm_i915_private *dev_priv = dev->dev_private;
 103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 104         } else
 105                 return 27;
 106 }
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 2 },
 119         .find_pll = intel_find_best_PLL,
 120 };
 121
 122 static const intel_limit_t intel_limits_i8xx_lvds = {
 123         .dot = { .min = 25000, .max = 350000 },
 124         .vco = { .min = 930000, .max = 1400000 },
 125         .n = { .min = 3, .max = 16 },
 126         .m = { .min = 96, .max = 140 },
 127         .m1 = { .min = 18, .max = 26 },
 128         .m2 = { .min = 6, .max = 16 },
 129         .p = { .min = 4, .max = 128 },
 130         .p1 = { .min = 1, .max = 6 },
 131         .p2 = { .dot_limit = 165000,
 132                 .p2_slow = 14, .p2_fast = 7 },
 133         .find_pll = intel_find_best_PLL,
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 10, .max = 22 },
 142         .m2 = { .min = 5, .max = 9 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147         .find_pll = intel_find_best_PLL,
 148 };
 149
 150 static const intel_limit_t intel_limits_i9xx_lvds = {
 151         .dot = { .min = 20000, .max = 400000 },
 152         .vco = { .min = 1400000, .max = 2800000 },
 153         .n = { .min = 1, .max = 6 },
 154         .m = { .min = 70, .max = 120 },
 155         .m1 = { .min = 10, .max = 22 },
 156         .m2 = { .min = 5, .max = 9 },
 157         .p = { .min = 7, .max = 98 },
 158         .p1 = { .min = 1, .max = 8 },
 159         .p2 = { .dot_limit = 112000,
 160                 .p2_slow = 14, .p2_fast = 7 },
 161         .find_pll = intel_find_best_PLL,
 162 };
 163
 164
 165 static const intel_limit_t intel_limits_g4x_sdvo = {
 166         .dot = { .min = 25000, .max = 270000 },
 167         .vco = { .min = 1750000, .max = 3500000},
 168         .n = { .min = 1, .max = 4 },
 169         .m = { .min = 104, .max = 138 },
 170         .m1 = { .min = 17, .max = 23 },
 171         .m2 = { .min = 5, .max = 11 },
 172         .p = { .min = 10, .max = 30 },
 173         .p1 = { .min = 1, .max = 3},
 174         .p2 = { .dot_limit = 270000,
 175                 .p2_slow = 10,
 176                 .p2_fast = 10
 177         },
 178         .find_pll = intel_g4x_find_best_PLL,
 179 };
 180
 181 static const intel_limit_t intel_limits_g4x_hdmi = {
 182         .dot = { .min = 22000, .max = 400000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 16, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8},
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192         .find_pll = intel_g4x_find_best_PLL,
 193 };
 194
 195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 196         .dot = { .min = 20000, .max = 115000 },
 197         .vco = { .min = 1750000, .max = 3500000 },
 198         .n = { .min = 1, .max = 3 },
 199         .m = { .min = 104, .max = 138 },
 200         .m1 = { .min = 17, .max = 23 },
 201         .m2 = { .min = 5, .max = 11 },
 202         .p = { .min = 28, .max = 112 },
 203         .p1 = { .min = 2, .max = 8 },
 204         .p2 = { .dot_limit = 0,
 205                 .p2_slow = 14, .p2_fast = 14
 206         },
 207         .find_pll = intel_g4x_find_best_PLL,
 208 };
 209
 210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 211         .dot = { .min = 80000, .max = 224000 },
 212         .vco = { .min = 1750000, .max = 3500000 },
 213         .n = { .min = 1, .max = 3 },
 214         .m = { .min = 104, .max = 138 },
 215         .m1 = { .min = 17, .max = 23 },
 216         .m2 = { .min = 5, .max = 11 },
 217         .p = { .min = 14, .max = 42 },
 218         .p1 = { .min = 2, .max = 6 },
 219         .p2 = { .dot_limit = 0,
 220                 .p2_slow = 7, .p2_fast = 7
 221         },
 222         .find_pll = intel_g4x_find_best_PLL,
 223 };
 224
 225 static const intel_limit_t intel_limits_g4x_display_port = {
 226         .dot = { .min = 161670, .max = 227000 },
 227         .vco = { .min = 1750000, .max = 3500000},
 228         .n = { .min = 1, .max = 2 },
 229         .m = { .min = 97, .max = 108 },
 230         .m1 = { .min = 0x10, .max = 0x12 },
 231         .m2 = { .min = 0x05, .max = 0x06 },
 232         .p = { .min = 10, .max = 20 },
 233         .p1 = { .min = 1, .max = 2},
 234         .p2 = { .dot_limit = 0,
 235                 .p2_slow = 10, .p2_fast = 10 },
 236         .find_pll = intel_find_pll_g4x_dp,
 237 };
 238
 239 static const intel_limit_t intel_limits_pineview_sdvo = {
 240         .dot = { .min = 20000, .max = 400000},
 241         .vco = { .min = 1700000, .max = 3500000 },
 242         /* Pineview's Ncounter is a ring counter */
 243         .n = { .min = 3, .max = 6 },
 244         .m = { .min = 2, .max = 256 },
 245         /* Pineview only has one combined m divider, which we treat as m2. */
 246         .m1 = { .min = 0, .max = 0 },
 247         .m2 = { .min = 0, .max = 254 },
 248         .p = { .min = 5, .max = 80 },
 249         .p1 = { .min = 1, .max = 8 },
 250         .p2 = { .dot_limit = 200000,
 251                 .p2_slow = 10, .p2_fast = 5 },
 252         .find_pll = intel_find_best_PLL,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         .n = { .min = 3, .max = 6 },
 259         .m = { .min = 2, .max = 256 },
 260         .m1 = { .min = 0, .max = 0 },
 261         .m2 = { .min = 0, .max = 254 },
 262         .p = { .min = 7, .max = 112 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 14 },
 266         .find_pll = intel_find_best_PLL,
 267 };
 268
 269 /* Ironlake / Sandybridge
 270  *
 271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 272  * the range value for them is (actual_value - 2).
 273  */
 274 static const intel_limit_t intel_limits_ironlake_dac = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 5 },
 278         .m = { .min = 79, .max = 127 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285         .find_pll = intel_g4x_find_best_PLL,
 286 };
 287
 288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 1760000, .max = 3510000 },
 291         .n = { .min = 1, .max = 3 },
 292         .m = { .min = 79, .max = 118 },
 293         .m1 = { .min = 12, .max = 22 },
 294         .m2 = { .min = 5, .max = 9 },
 295         .p = { .min = 28, .max = 112 },
 296         .p1 = { .min = 2, .max = 8 },
 297         .p2 = { .dot_limit = 225000,
 298                 .p2_slow = 14, .p2_fast = 14 },
 299         .find_pll = intel_g4x_find_best_PLL,
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 127 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 56 },
 310         .p1 = { .min = 2, .max = 8 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313         .find_pll = intel_g4x_find_best_PLL,
 314 };
 315
 316 /* LVDS 100mhz refclk limits. */
 317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 2 },
 321         .m = { .min = 79, .max = 126 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328         .find_pll = intel_g4x_find_best_PLL,
 329 };
 330
 331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 332         .dot = { .min = 25000, .max = 350000 },
 333         .vco = { .min = 1760000, .max = 3510000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 79, .max = 126 },
 336         .m1 = { .min = 12, .max = 22 },
 337         .m2 = { .min = 5, .max = 9 },
 338         .p = { .min = 14, .max = 42 },
 339         .p1 = { .min = 2, .max = 6 },
 340         .p2 = { .dot_limit = 225000,
 341                 .p2_slow = 7, .p2_fast = 7 },
 342         .find_pll = intel_g4x_find_best_PLL,
 343 };
 344
 345 static const intel_limit_t intel_limits_ironlake_display_port = {
 346         .dot = { .min = 25000, .max = 350000 },
 347         .vco = { .min = 1760000, .max = 3510000},
 348         .n = { .min = 1, .max = 2 },
 349         .m = { .min = 81, .max = 90 },
 350         .m1 = { .min = 12, .max = 22 },
 351         .m2 = { .min = 5, .max = 9 },
 352         .p = { .min = 10, .max = 20 },
 353         .p1 = { .min = 1, .max = 2},
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 10, .p2_fast = 10 },
 356         .find_pll = intel_find_pll_ironlake_dp,
 357 };
 358
 359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 360                                                 int refclk)
 361 {
 362         struct drm_device *dev = crtc->dev;
 363         struct drm_i915_private *dev_priv = dev->dev_private;
 364         const intel_limit_t *limit;
 365
 366         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 367                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 368                     LVDS_CLKB_POWER_UP) {
 369                         /* LVDS dual channel */
 370                         if (refclk == 100000)
 371                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 372                         else
 373                                 limit = &intel_limits_ironlake_dual_lvds;
 374                 } else {
 375                         if (refclk == 100000)
 376                                 limit = &intel_limits_ironlake_single_lvds_100m;
 377                         else
 378                                 limit = &intel_limits_ironlake_single_lvds;
 379                 }
 380         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 381                         HAS_eDP)
 382                 limit = &intel_limits_ironlake_display_port;
 383         else
 384                 limit = &intel_limits_ironlake_dac;
 385
 386         return limit;
 387 }
 388
 389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 397                     LVDS_CLKB_POWER_UP)
 398                         /* LVDS with dual channel */
 399                         limit = &intel_limits_g4x_dual_channel_lvds;
 400                 else
 401                         /* LVDS with dual channel */
 402                         limit = &intel_limits_g4x_single_channel_lvds;
 403         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 404                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 405                 limit = &intel_limits_g4x_hdmi;
 406         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 407                 limit = &intel_limits_g4x_sdvo;
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 409                 limit = &intel_limits_g4x_display_port;
 410         } else /* The option is for other outputs */
 411                 limit = &intel_limits_i9xx_sdvo;
 412
 413         return limit;
 414 }
 415
 416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 417 {
 418         struct drm_device *dev = crtc->dev;
 419         const intel_limit_t *limit;
 420
 421         if (HAS_PCH_SPLIT(dev))
 422                 limit = intel_ironlake_limit(crtc, refclk);
 423         else if (IS_G4X(dev)) {
 424                 limit = intel_g4x_limit(crtc);
 425         } else if (IS_PINEVIEW(dev)) {
 426                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 427                         limit = &intel_limits_pineview_lvds;
 428                 else
 429                         limit = &intel_limits_pineview_sdvo;
 430         } else if (!IS_GEN2(dev)) {
 431                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 432                         limit = &intel_limits_i9xx_lvds;
 433                 else
 434                         limit = &intel_limits_i9xx_sdvo;
 435         } else {
 436                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 437                         limit = &intel_limits_i8xx_lvds;
 438                 else
 439                         limit = &intel_limits_i8xx_dvo;
 440         }
 441         return limit;
 442 }
 443
 444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 445 static void pineview_clock(int refclk, intel_clock_t *clock)
 446 {
 447         clock->m = clock->m2 + 2;
 448         clock->p = clock->p1 * clock->p2;
 449         clock->vco = refclk * clock->m / clock->n;
 450         clock->dot = clock->vco / clock->p;
 451 }
 452
 453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 454 {
 455         if (IS_PINEVIEW(dev)) {
 456                 pineview_clock(refclk, clock);
 457                 return;
 458         }
 459         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 460         clock->p = clock->p1 * clock->p2;
 461         clock->vco = refclk * clock->m / (clock->n + 2);
 462         clock->dot = clock->vco / clock->p;
 463 }
 464
 465 /**
 466  * Returns whether any output on the specified pipe is of the specified type
 467  */
 468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 469 {
 470         struct drm_device *dev = crtc->dev;
 471         struct drm_mode_config *mode_config = &dev->mode_config;
 472         struct intel_encoder *encoder;
 473
 474         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 475                 if (encoder->base.crtc == crtc && encoder->type == type)
 476                         return true;
 477
 478         return false;
 479 }
 480
 481 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 482 /**
 483  * Returns whether the given set of divisors are valid for a given refclk with
 484  * the given connectors.
 485  */
 486
 487 static bool intel_PLL_is_valid(struct drm_device *dev,
 488                                const intel_limit_t *limit,
 489                                const intel_clock_t *clock)
 490 {
 491         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 492                 INTELPllInvalid("p1 out of range\n");
 493         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 494                 INTELPllInvalid("p out of range\n");
 495         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 496                 INTELPllInvalid("m2 out of range\n");
 497         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 498                 INTELPllInvalid("m1 out of range\n");
 499         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 500                 INTELPllInvalid("m1 <= m2\n");
 501         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 502                 INTELPllInvalid("m out of range\n");
 503         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 504                 INTELPllInvalid("n out of range\n");
 505         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 506                 INTELPllInvalid("vco out of range\n");
 507         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 508          * connector, etc., rather than just a single range.
 509          */
 510         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 511                 INTELPllInvalid("dot out of range\n");
 512
 513         return true;
 514 }
 515
 516 static bool
 517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 518                     int target, int refclk, intel_clock_t *best_clock)
 519
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         intel_clock_t clock;
 524         int err = target;
 525
 526         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 527             (I915_READ(LVDS)) != 0) {
 528                 /*
 529                  * For LVDS, if the panel is on, just rely on its current
 530                  * settings for dual-channel.  We haven't figured out how to
 531                  * reliably set up different single/dual channel state, if we
 532                  * even can.
 533                  */
 534                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 535                     LVDS_CLKB_POWER_UP)
 536                         clock.p2 = limit->p2.p2_fast;
 537                 else
 538                         clock.p2 = limit->p2.p2_slow;
 539         } else {
 540                 if (target < limit->p2.dot_limit)
 541                         clock.p2 = limit->p2.p2_slow;
 542                 else
 543                         clock.p2 = limit->p2.p2_fast;
 544         }
 545
 546         memset(best_clock, 0, sizeof(*best_clock));
 547
 548         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 549              clock.m1++) {
 550                 for (clock.m2 = limit->m2.min;
 551                      clock.m2 <= limit->m2.max; clock.m2++) {
 552                         /* m1 is always 0 in Pineview */
 553                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 554                                 break;
 555                         for (clock.n = limit->n.min;
 556                              clock.n <= limit->n.max; clock.n++) {
 557                                 for (clock.p1 = limit->p1.min;
 558                                         clock.p1 <= limit->p1.max; clock.p1++) {
 559                                         int this_err;
 560
 561                                         intel_clock(dev, refclk, &clock);
 562                                         if (!intel_PLL_is_valid(dev, limit,
 563                                                                 &clock))
 564                                                 continue;
 565
 566                                         this_err = abs(clock.dot - target);
 567                                         if (this_err < err) {
 568                                                 *best_clock = clock;
 569                                                 err = this_err;
 570                                         }
 571                                 }
 572                         }
 573                 }
 574         }
 575
 576         return (err != target);
 577 }
 578
 579 static bool
 580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 581                         int target, int refclk, intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct drm_i915_private *dev_priv = dev->dev_private;
 585         intel_clock_t clock;
 586         int max_n;
 587         bool found;
 588         /* approximately equals target * 0.00585 */
 589         int err_most = (target >> 8) + (target >> 9);
 590         found = false;
 591
 592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 593                 int lvds_reg;
 594
 595                 if (HAS_PCH_SPLIT(dev))
 596                         lvds_reg = PCH_LVDS;
 597                 else
 598                         lvds_reg = LVDS;
 599                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 600                     LVDS_CLKB_POWER_UP)
 601                         clock.p2 = limit->p2.p2_fast;
 602                 else
 603                         clock.p2 = limit->p2.p2_slow;
 604         } else {
 605                 if (target < limit->p2.dot_limit)
 606                         clock.p2 = limit->p2.p2_slow;
 607                 else
 608                         clock.p2 = limit->p2.p2_fast;
 609         }
 610
 611         memset(best_clock, 0, sizeof(*best_clock));
 612         max_n = limit->n.max;
 613         /* based on hardware requirement, prefer smaller n to precision */
 614         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 615                 /* based on hardware requirement, prefere larger m1,m2 */
 616                 for (clock.m1 = limit->m1.max;
 617                      clock.m1 >= limit->m1.min; clock.m1--) {
 618                         for (clock.m2 = limit->m2.max;
 619                              clock.m2 >= limit->m2.min; clock.m2--) {
 620                                 for (clock.p1 = limit->p1.max;
 621                                      clock.p1 >= limit->p1.min; clock.p1--) {
 622                                         int this_err;
 623
 624                                         intel_clock(dev, refclk, &clock);
 625                                         if (!intel_PLL_is_valid(dev, limit,
 626                                                                 &clock))
 627                                                 continue;
 628
 629                                         this_err = abs(clock.dot - target);
 630                                         if (this_err < err_most) {
 631                                                 *best_clock = clock;
 632                                                 err_most = this_err;
 633                                                 max_n = clock.n;
 634                                                 found = true;
 635                                         }
 636                                 }
 637                         }
 638                 }
 639         }
 640         return found;
 641 }
 642
 643 static bool
 644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 645                            int target, int refclk, intel_clock_t *best_clock)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         intel_clock_t clock;
 649
 650         if (target < 200000) {
 651                 clock.n = 1;
 652                 clock.p1 = 2;
 653                 clock.p2 = 10;
 654                 clock.m1 = 12;
 655                 clock.m2 = 9;
 656         } else {
 657                 clock.n = 2;
 658                 clock.p1 = 1;
 659                 clock.p2 = 10;
 660                 clock.m1 = 14;
 661                 clock.m2 = 8;
 662         }
 663         intel_clock(dev, refclk, &clock);
 664         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 665         return true;
 666 }
 667
 668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 669 static bool
 670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 671                       int target, int refclk, intel_clock_t *best_clock)
 672 {
 673         intel_clock_t clock;
 674         if (target < 200000) {
 675                 clock.p1 = 2;
 676                 clock.p2 = 10;
 677                 clock.n = 2;
 678                 clock.m1 = 23;
 679                 clock.m2 = 8;
 680         } else {
 681                 clock.p1 = 1;
 682                 clock.p2 = 10;
 683                 clock.n = 1;
 684                 clock.m1 = 14;
 685                 clock.m2 = 2;
 686         }
 687         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 688         clock.p = (clock.p1 * clock.p2);
 689         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 690         clock.vco = 0;
 691         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 692         return true;
 693 }
 694
 695 /**
 696  * intel_wait_for_vblank - wait for vblank on a given pipe
 697  * @dev: drm device
 698  * @pipe: pipe to wait for
 699  *
 700  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 701  * mode setting code.
 702  */
 703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 704 {
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         int pipestat_reg = PIPESTAT(pipe);
 707
 708         /* Clear existing vblank status. Note this will clear any other
 709          * sticky status fields as well.
 710          *
 711          * This races with i915_driver_irq_handler() with the result
 712          * that either function could miss a vblank event.  Here it is not
 713          * fatal, as we will either wait upon the next vblank interrupt or
 714          * timeout.  Generally speaking intel_wait_for_vblank() is only
 715          * called during modeset at which time the GPU should be idle and
 716          * should *not* be performing page flips and thus not waiting on
 717          * vblanks...
 718          * Currently, the result of us stealing a vblank from the irq
 719          * handler is that a single frame will be skipped during swapbuffers.
 720          */
 721         I915_WRITE(pipestat_reg,
 722                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 723
 724         /* Wait for vblank interrupt bit to set */
 725         if (wait_for(I915_READ(pipestat_reg) &
 726                      PIPE_VBLANK_INTERRUPT_STATUS,
 727                      50))
 728                 DRM_DEBUG_KMS("vblank wait timed out\n");
 729 }
 730
 731 /*
 732  * intel_wait_for_pipe_off - wait for pipe to turn off
 733  * @dev: drm device
 734  * @pipe: pipe to wait for
 735  *
 736  * After disabling a pipe, we can't wait for vblank in the usual way,
 737  * spinning on the vblank interrupt status bit, since we won't actually
 738  * see an interrupt when the pipe is disabled.
 739  *
 740  * On Gen4 and above:
 741  *   wait for the pipe register state bit to turn off
 742  *
 743  * Otherwise:
 744  *   wait for the display line value to settle (it usually
 745  *   ends up stopping at the start of the next frame).
 746  *
 747  */
 748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 749 {
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751
 752         if (INTEL_INFO(dev)->gen >= 4) {
 753                 int reg = PIPECONF(pipe);
 754
 755                 /* Wait for the Pipe State to go off */
 756                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 757                              100))
 758                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 759         } else {
 760                 u32 last_line;
 761                 int reg = PIPEDSL(pipe);
 762                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 763
 764                 /* Wait for the display line to settle */
 765                 do {
 766                         last_line = I915_READ(reg) & DSL_LINEMASK;
 767                         mdelay(5);
 768                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 769                          time_after(timeout, jiffies));
 770                 if (time_after(jiffies, timeout))
 771                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 772         }
 773 }
 774
 775 static const char *state_string(bool enabled)
 776 {
 777         return enabled ? "on" : "off";
 778 }
 779
 780 /* Only for pre-ILK configs */
 781 static void assert_pll(struct drm_i915_private *dev_priv,
 782                        enum pipe pipe, bool state)
 783 {
 784         int reg;
 785         u32 val;
 786         bool cur_state;
 787
 788         reg = DPLL(pipe);
 789         val = I915_READ(reg);
 790         cur_state = !!(val & DPLL_VCO_ENABLE);
 791         WARN(cur_state != state,
 792              "PLL state assertion failure (expected %s, current %s)\n",
 793              state_string(state), state_string(cur_state));
 794 }
 795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 797
 798 /* For ILK+ */
 799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 800                            enum pipe pipe, bool state)
 801 {
 802         int reg;
 803         u32 val;
 804         bool cur_state;
 805
 806         if (HAS_PCH_CPT(dev_priv->dev)) {
 807                 u32 pch_dpll;
 808
 809                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 810
 811                 /* Make sure the selected PLL is enabled to the transcoder */
 812                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 813                      "transcoder %d PLL not enabled\n", pipe);
 814
 815                 /* Convert the transcoder pipe number to a pll pipe number */
 816                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 817         }
 818
 819         reg = PCH_DPLL(pipe);
 820         val = I915_READ(reg);
 821         cur_state = !!(val & DPLL_VCO_ENABLE);
 822         WARN(cur_state != state,
 823              "PCH PLL state assertion failure (expected %s, current %s)\n",
 824              state_string(state), state_string(cur_state));
 825 }
 826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 828
 829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 830                           enum pipe pipe, bool state)
 831 {
 832         int reg;
 833         u32 val;
 834         bool cur_state;
 835
 836         reg = FDI_TX_CTL(pipe);
 837         val = I915_READ(reg);
 838         cur_state = !!(val & FDI_TX_ENABLE);
 839         WARN(cur_state != state,
 840              "FDI TX state assertion failure (expected %s, current %s)\n",
 841              state_string(state), state_string(cur_state));
 842 }
 843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 845
 846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 847                           enum pipe pipe, bool state)
 848 {
 849         int reg;
 850         u32 val;
 851         bool cur_state;
 852
 853         reg = FDI_RX_CTL(pipe);
 854         val = I915_READ(reg);
 855         cur_state = !!(val & FDI_RX_ENABLE);
 856         WARN(cur_state != state,
 857              "FDI RX state assertion failure (expected %s, current %s)\n",
 858              state_string(state), state_string(cur_state));
 859 }
 860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 862
 863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         /* ILK FDI PLL is always enabled */
 870         if (dev_priv->info->gen == 5)
 871                 return;
 872
 873         reg = FDI_TX_CTL(pipe);
 874         val = I915_READ(reg);
 875         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 876 }
 877
 878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 879                                       enum pipe pipe)
 880 {
 881         int reg;
 882         u32 val;
 883
 884         reg = FDI_RX_CTL(pipe);
 885         val = I915_READ(reg);
 886         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 887 }
 888
 889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 890                                   enum pipe pipe)
 891 {
 892         int pp_reg, lvds_reg;
 893         u32 val;
 894         enum pipe panel_pipe = PIPE_A;
 895         bool locked = true;
 896
 897         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 898                 pp_reg = PCH_PP_CONTROL;
 899                 lvds_reg = PCH_LVDS;
 900         } else {
 901                 pp_reg = PP_CONTROL;
 902                 lvds_reg = LVDS;
 903         }
 904
 905         val = I915_READ(pp_reg);
 906         if (!(val & PANEL_POWER_ON) ||
 907             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 908                 locked = false;
 909
 910         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 911                 panel_pipe = PIPE_B;
 912
 913         WARN(panel_pipe == pipe && locked,
 914              "panel assertion failure, pipe %c regs locked\n",
 915              pipe_name(pipe));
 916 }
 917
 918 static void assert_pipe(struct drm_i915_private *dev_priv,
 919                         enum pipe pipe, bool state)
 920 {
 921         int reg;
 922         u32 val;
 923         bool cur_state;
 924
 925         reg = PIPECONF(pipe);
 926         val = I915_READ(reg);
 927         cur_state = !!(val & PIPECONF_ENABLE);
 928         WARN(cur_state != state,
 929              "pipe %c assertion failure (expected %s, current %s)\n",
 930              pipe_name(pipe), state_string(state), state_string(cur_state));
 931 }
 932 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 933 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 934
 935 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 936                                  enum plane plane)
 937 {
 938         int reg;
 939         u32 val;
 940
 941         reg = DSPCNTR(plane);
 942         val = I915_READ(reg);
 943         WARN(!(val & DISPLAY_PLANE_ENABLE),
 944              "plane %c assertion failure, should be active but is disabled\n",
 945              plane_name(plane));
 946 }
 947
 948 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 949                                    enum pipe pipe)
 950 {
 951         int reg, i;
 952         u32 val;
 953         int cur_pipe;
 954
 955         /* Planes are fixed to pipes on ILK+ */
 956         if (HAS_PCH_SPLIT(dev_priv->dev))
 957                 return;
 958
 959         /* Need to check both planes against the pipe */
 960         for (i = 0; i < 2; i++) {
 961                 reg = DSPCNTR(i);
 962                 val = I915_READ(reg);
 963                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 964                         DISPPLANE_SEL_PIPE_SHIFT;
 965                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 966                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 967                      plane_name(i), pipe_name(pipe));
 968         }
 969 }
 970
 971 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 972 {
 973         u32 val;
 974         bool enabled;
 975
 976         val = I915_READ(PCH_DREF_CONTROL);
 977         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 978                             DREF_SUPERSPREAD_SOURCE_MASK));
 979         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 980 }
 981
 982 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 983                                        enum pipe pipe)
 984 {
 985         int reg;
 986         u32 val;
 987         bool enabled;
 988
 989         reg = TRANSCONF(pipe);
 990         val = I915_READ(reg);
 991         enabled = !!(val & TRANS_ENABLE);
 992         WARN(enabled,
 993              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 994              pipe_name(pipe));
 995 }
 996
 997 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 998                             enum pipe pipe, u32 port_sel, u32 val)
 999 {
1000         if ((val & DP_PORT_EN) == 0)
1001                 return false;
1002
1003         if (HAS_PCH_CPT(dev_priv->dev)) {
1004                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007                         return false;
1008         } else {
1009                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010                         return false;
1011         }
1012         return true;
1013 }
1014
1015 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016                               enum pipe pipe, u32 val)
1017 {
1018         if ((val & PORT_ENABLE) == 0)
1019                 return false;
1020
1021         if (HAS_PCH_CPT(dev_priv->dev)) {
1022                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023                         return false;
1024         } else {
1025                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026                         return false;
1027         }
1028         return true;
1029 }
1030
1031 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032                               enum pipe pipe, u32 val)
1033 {
1034         if ((val & LVDS_PORT_EN) == 0)
1035                 return false;
1036
1037         if (HAS_PCH_CPT(dev_priv->dev)) {
1038                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039                         return false;
1040         } else {
1041                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042                         return false;
1043         }
1044         return true;
1045 }
1046
1047 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048                               enum pipe pipe, u32 val)
1049 {
1050         if ((val & ADPA_DAC_ENABLE) == 0)
1051                 return false;
1052         if (HAS_PCH_CPT(dev_priv->dev)) {
1053                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054                         return false;
1055         } else {
1056                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057                         return false;
1058         }
1059         return true;
1060 }
1061
1062 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1063                                    enum pipe pipe, int reg, u32 port_sel)
1064 {
1065         u32 val = I915_READ(reg);
1066         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1067              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1068              reg, pipe_name(pipe));
1069 }
1070
1071 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072                                      enum pipe pipe, int reg)
1073 {
1074         u32 val = I915_READ(reg);
1075         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1076              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1077              reg, pipe_name(pipe));
1078 }
1079
1080 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081                                       enum pipe pipe)
1082 {
1083         int reg;
1084         u32 val;
1085
1086         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1089
1090         reg = PCH_ADPA;
1091         val = I915_READ(reg);
1092         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1093              "PCH VGA enabled on transcoder %c, should be disabled\n",
1094              pipe_name(pipe));
1095
1096         reg = PCH_LVDS;
1097         val = I915_READ(reg);
1098         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1099              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1100              pipe_name(pipe));
1101
1102         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105 }
1106
1107 /**
1108  * intel_enable_pll - enable a PLL
1109  * @dev_priv: i915 private structure
1110  * @pipe: pipe PLL to enable
1111  *
1112  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1113  * make sure the PLL reg is writable first though, since the panel write
1114  * protect mechanism may be enabled.
1115  *
1116  * Note!  This is for pre-ILK only.
1117  */
1118 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119 {
1120         int reg;
1121         u32 val;
1122
1123         /* No really, not for ILK+ */
1124         BUG_ON(dev_priv->info->gen >= 5);
1125
1126         /* PLL is protected by panel, make sure we can write it */
1127         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128                 assert_panel_unlocked(dev_priv, pipe);
1129
1130         reg = DPLL(pipe);
1131         val = I915_READ(reg);
1132         val |= DPLL_VCO_ENABLE;
1133
1134         /* We do this three times for luck */
1135         I915_WRITE(reg, val);
1136         POSTING_READ(reg);
1137         udelay(150); /* wait for warmup */
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(150); /* wait for warmup */
1141         I915_WRITE(reg, val);
1142         POSTING_READ(reg);
1143         udelay(150); /* wait for warmup */
1144 }
1145
1146 /**
1147  * intel_disable_pll - disable a PLL
1148  * @dev_priv: i915 private structure
1149  * @pipe: pipe PLL to disable
1150  *
1151  * Disable the PLL for @pipe, making sure the pipe is off first.
1152  *
1153  * Note!  This is for pre-ILK only.
1154  */
1155 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157         int reg;
1158         u32 val;
1159
1160         /* Don't disable pipe A or pipe A PLLs if needed */
1161         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162                 return;
1163
1164         /* Make sure the pipe isn't still relying on us */
1165         assert_pipe_disabled(dev_priv, pipe);
1166
1167         reg = DPLL(pipe);
1168         val = I915_READ(reg);
1169         val &= ~DPLL_VCO_ENABLE;
1170         I915_WRITE(reg, val);
1171         POSTING_READ(reg);
1172 }
1173
1174 /**
1175  * intel_enable_pch_pll - enable PCH PLL
1176  * @dev_priv: i915 private structure
1177  * @pipe: pipe PLL to enable
1178  *
1179  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180  * drives the transcoder clock.
1181  */
1182 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183                                  enum pipe pipe)
1184 {
1185         int reg;
1186         u32 val;
1187
1188         if (pipe > 1)
1189                 return;
1190
1191         /* PCH only available on ILK+ */
1192         BUG_ON(dev_priv->info->gen < 5);
1193
1194         /* PCH refclock must be enabled first */
1195         assert_pch_refclk_enabled(dev_priv);
1196
1197         reg = PCH_DPLL(pipe);
1198         val = I915_READ(reg);
1199         val |= DPLL_VCO_ENABLE;
1200         I915_WRITE(reg, val);
1201         POSTING_READ(reg);
1202         udelay(200);
1203 }
1204
1205 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206                                   enum pipe pipe)
1207 {
1208         int reg;
1209         u32 val;
1210
1211         if (pipe > 1)
1212                 return;
1213
1214         /* PCH only available on ILK+ */
1215         BUG_ON(dev_priv->info->gen < 5);
1216
1217         /* Make sure transcoder isn't still depending on us */
1218         assert_transcoder_disabled(dev_priv, pipe);
1219
1220         reg = PCH_DPLL(pipe);
1221         val = I915_READ(reg);
1222         val &= ~DPLL_VCO_ENABLE;
1223         I915_WRITE(reg, val);
1224         POSTING_READ(reg);
1225         udelay(200);
1226 }
1227
1228 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229                                     enum pipe pipe)
1230 {
1231         int reg;
1232         u32 val;
1233
1234         /* PCH only available on ILK+ */
1235         BUG_ON(dev_priv->info->gen < 5);
1236
1237         /* Make sure PCH DPLL is enabled */
1238         assert_pch_pll_enabled(dev_priv, pipe);
1239
1240         /* FDI must be feeding us bits for PCH ports */
1241         assert_fdi_tx_enabled(dev_priv, pipe);
1242         assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244         reg = TRANSCONF(pipe);
1245         val = I915_READ(reg);
1246
1247         if (HAS_PCH_IBX(dev_priv->dev)) {
1248                 /*
1249                  * make the BPC in transcoder be consistent with
1250                  * that in pipeconf reg.
1251                  */
1252                 val &= ~PIPE_BPC_MASK;
1253                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254         }
1255         I915_WRITE(reg, val | TRANS_ENABLE);
1256         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258 }
1259
1260 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261                                      enum pipe pipe)
1262 {
1263         int reg;
1264         u32 val;
1265
1266         /* FDI relies on the transcoder */
1267         assert_fdi_tx_disabled(dev_priv, pipe);
1268         assert_fdi_rx_disabled(dev_priv, pipe);
1269
1270         /* Ports must be off as well */
1271         assert_pch_ports_disabled(dev_priv, pipe);
1272
1273         reg = TRANSCONF(pipe);
1274         val = I915_READ(reg);
1275         val &= ~TRANS_ENABLE;
1276         I915_WRITE(reg, val);
1277         /* wait for PCH transcoder off, transcoder state */
1278         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1280 }
1281
1282 /**
1283  * intel_enable_pipe - enable a pipe, asserting requirements
1284  * @dev_priv: i915 private structure
1285  * @pipe: pipe to enable
1286  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1287  *
1288  * Enable @pipe, making sure that various hardware specific requirements
1289  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290  *
1291  * @pipe should be %PIPE_A or %PIPE_B.
1292  *
1293  * Will wait until the pipe is actually running (i.e. first vblank) before
1294  * returning.
1295  */
1296 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297                               bool pch_port)
1298 {
1299         int reg;
1300         u32 val;
1301
1302         /*
1303          * A pipe without a PLL won't actually be able to drive bits from
1304          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1305          * need the check.
1306          */
1307         if (!HAS_PCH_SPLIT(dev_priv->dev))
1308                 assert_pll_enabled(dev_priv, pipe);
1309         else {
1310                 if (pch_port) {
1311                         /* if driving the PCH, we need FDI enabled */
1312                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314                 }
1315                 /* FIXME: assert CPU port conditions for SNB+ */
1316         }
1317
1318         reg = PIPECONF(pipe);
1319         val = I915_READ(reg);
1320         if (val & PIPECONF_ENABLE)
1321                 return;
1322
1323         I915_WRITE(reg, val | PIPECONF_ENABLE);
1324         intel_wait_for_vblank(dev_priv->dev, pipe);
1325 }
1326
1327 /**
1328  * intel_disable_pipe - disable a pipe, asserting requirements
1329  * @dev_priv: i915 private structure
1330  * @pipe: pipe to disable
1331  *
1332  * Disable @pipe, making sure that various hardware specific requirements
1333  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334  *
1335  * @pipe should be %PIPE_A or %PIPE_B.
1336  *
1337  * Will wait until the pipe has shut down before returning.
1338  */
1339 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340                                enum pipe pipe)
1341 {
1342         int reg;
1343         u32 val;
1344
1345         /*
1346          * Make sure planes won't keep trying to pump pixels to us,
1347          * or we might hang the display.
1348          */
1349         assert_planes_disabled(dev_priv, pipe);
1350
1351         /* Don't disable pipe A or pipe A PLLs if needed */
1352         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353                 return;
1354
1355         reg = PIPECONF(pipe);
1356         val = I915_READ(reg);
1357         if ((val & PIPECONF_ENABLE) == 0)
1358                 return;
1359
1360         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1361         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362 }
1363
1364 /*
1365  * Plane regs are double buffered, going from enabled->disabled needs a
1366  * trigger in order to latch.  The display address reg provides this.
1367  */
1368 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369                                       enum plane plane)
1370 {
1371         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373 }
1374
1375 /**
1376  * intel_enable_plane - enable a display plane on a given pipe
1377  * @dev_priv: i915 private structure
1378  * @plane: plane to enable
1379  * @pipe: pipe being fed
1380  *
1381  * Enable @plane on @pipe, making sure that @pipe is running first.
1382  */
1383 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384                                enum plane plane, enum pipe pipe)
1385 {
1386         int reg;
1387         u32 val;
1388
1389         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390         assert_pipe_enabled(dev_priv, pipe);
1391
1392         reg = DSPCNTR(plane);
1393         val = I915_READ(reg);
1394         if (val & DISPLAY_PLANE_ENABLE)
1395                 return;
1396
1397         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1398         intel_flush_display_plane(dev_priv, plane);
1399         intel_wait_for_vblank(dev_priv->dev, pipe);
1400 }
1401
1402 /**
1403  * intel_disable_plane - disable a display plane
1404  * @dev_priv: i915 private structure
1405  * @plane: plane to disable
1406  * @pipe: pipe consuming the data
1407  *
1408  * Disable @plane; should be an independent operation.
1409  */
1410 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411                                 enum plane plane, enum pipe pipe)
1412 {
1413         int reg;
1414         u32 val;
1415
1416         reg = DSPCNTR(plane);
1417         val = I915_READ(reg);
1418         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419                 return;
1420
1421         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1422         intel_flush_display_plane(dev_priv, plane);
1423         intel_wait_for_vblank(dev_priv->dev, pipe);
1424 }
1425
1426 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1427                            enum pipe pipe, int reg, u32 port_sel)
1428 {
1429         u32 val = I915_READ(reg);
1430         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1431                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1432                 I915_WRITE(reg, val & ~DP_PORT_EN);
1433         }
1434 }
1435
1436 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437                              enum pipe pipe, int reg)
1438 {
1439         u32 val = I915_READ(reg);
1440         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1441                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442                               reg, pipe);
1443                 I915_WRITE(reg, val & ~PORT_ENABLE);
1444         }
1445 }
1446
1447 /* Disable any ports connected to this transcoder */
1448 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449                                     enum pipe pipe)
1450 {
1451         u32 reg, val;
1452
1453         val = I915_READ(PCH_PP_CONTROL);
1454         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
1456         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1459
1460         reg = PCH_ADPA;
1461         val = I915_READ(reg);
1462         if (adpa_pipe_enabled(dev_priv, val, pipe))
1463                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465         reg = PCH_LVDS;
1466         val = I915_READ(reg);
1467         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1469                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470                 POSTING_READ(reg);
1471                 udelay(100);
1472         }
1473
1474         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476         disable_pch_hdmi(dev_priv, pipe, HDMID);
1477 }
1478
1479 static void i8xx_disable_fbc(struct drm_device *dev)
1480 {
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         u32 fbc_ctl;
1483
1484         /* Disable compression */
1485         fbc_ctl = I915_READ(FBC_CONTROL);
1486         if ((fbc_ctl & FBC_CTL_EN) == 0)
1487                 return;
1488
1489         fbc_ctl &= ~FBC_CTL_EN;
1490         I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492         /* Wait for compressing bit to clear */
1493         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494                 DRM_DEBUG_KMS("FBC idle timed out\n");
1495                 return;
1496         }
1497
1498         DRM_DEBUG_KMS("disabled FBC\n");
1499 }
1500
1501 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502 {
1503         struct drm_device *dev = crtc->dev;
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         struct drm_framebuffer *fb = crtc->fb;
1506         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1507         struct drm_i915_gem_object *obj = intel_fb->obj;
1508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1509         int cfb_pitch;
1510         int plane, i;
1511         u32 fbc_ctl, fbc_ctl2;
1512
1513         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514         if (fb->pitch < cfb_pitch)
1515                 cfb_pitch = fb->pitch;
1516
1517         /* FBC_CTL wants 64B units */
1518         cfb_pitch = (cfb_pitch / 64) - 1;
1519         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1520
1521         /* Clear old tags */
1522         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523                 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525         /* Set it up... */
1526         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527         fbc_ctl2 |= plane;
1528         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531         /* enable it... */
1532         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1533         if (IS_I945GM(dev))
1534                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1535         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1536         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1537         fbc_ctl |= obj->fence_reg;
1538         I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
1540         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541                       cfb_pitch, crtc->y, intel_crtc->plane);
1542 }
1543
1544 static bool i8xx_fbc_enabled(struct drm_device *dev)
1545 {
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549 }
1550
1551 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1560         unsigned long stall_watermark = 200;
1561         u32 dpfc_ctl;
1562
1563         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1564         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1565         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1566
1567         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572         /* enable it... */
1573         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
1575         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1576 }
1577
1578 static void g4x_disable_fbc(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         u32 dpfc_ctl;
1582
1583         /* Disable compression */
1584         dpfc_ctl = I915_READ(DPFC_CONTROL);
1585         if (dpfc_ctl & DPFC_CTL_EN) {
1586                 dpfc_ctl &= ~DPFC_CTL_EN;
1587                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1588
1589                 DRM_DEBUG_KMS("disabled FBC\n");
1590         }
1591 }
1592
1593 static bool g4x_fbc_enabled(struct drm_device *dev)
1594 {
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598 }
1599
1600 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601 {
1602         struct drm_i915_private *dev_priv = dev->dev_private;
1603         u32 blt_ecoskpd;
1604
1605         /* Make sure blitter notifies FBC of writes */
1606         gen6_gt_force_wake_get(dev_priv);
1607         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609                 GEN6_BLITTER_LOCK_SHIFT;
1610         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614                          GEN6_BLITTER_LOCK_SHIFT);
1615         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1617         gen6_gt_force_wake_put(dev_priv);
1618 }
1619
1620 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621 {
1622         struct drm_device *dev = crtc->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         struct drm_framebuffer *fb = crtc->fb;
1625         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1626         struct drm_i915_gem_object *obj = intel_fb->obj;
1627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1628         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1629         unsigned long stall_watermark = 200;
1630         u32 dpfc_ctl;
1631
1632         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1633         dpfc_ctl &= DPFC_RESERVED;
1634         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1635         /* Set persistent mode for front-buffer rendering, ala X. */
1636         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1637         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1638         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1639
1640         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1644         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1645         /* enable it... */
1646         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1647
1648         if (IS_GEN6(dev)) {
1649                 I915_WRITE(SNB_DPFC_CTL_SA,
1650                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1651                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1652                 sandybridge_blit_fbc_update(dev);
1653         }
1654
1655         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656 }
1657
1658 static void ironlake_disable_fbc(struct drm_device *dev)
1659 {
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         u32 dpfc_ctl;
1662
1663         /* Disable compression */
1664         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1665         if (dpfc_ctl & DPFC_CTL_EN) {
1666                 dpfc_ctl &= ~DPFC_CTL_EN;
1667                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1668
1669                 DRM_DEBUG_KMS("disabled FBC\n");
1670         }
1671 }
1672
1673 static bool ironlake_fbc_enabled(struct drm_device *dev)
1674 {
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678 }
1679
1680 bool intel_fbc_enabled(struct drm_device *dev)
1681 {
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684         if (!dev_priv->display.fbc_enabled)
1685                 return false;
1686
1687         return dev_priv->display.fbc_enabled(dev);
1688 }
1689
1690 static void intel_fbc_work_fn(struct work_struct *__work)
1691 {
1692         struct intel_fbc_work *work =
1693                 container_of(to_delayed_work(__work),
1694                              struct intel_fbc_work, work);
1695         struct drm_device *dev = work->crtc->dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698         mutex_lock(&dev->struct_mutex);
1699         if (work == dev_priv->fbc_work) {
1700                 /* Double check that we haven't switched fb without cancelling
1701                  * the prior work.
1702                  */
1703                 if (work->crtc->fb == work->fb) {
1704                         dev_priv->display.enable_fbc(work->crtc,
1705                                                      work->interval);
1706
1707                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1709                         dev_priv->cfb_y = work->crtc->y;
1710                 }
1711
1712                 dev_priv->fbc_work = NULL;
1713         }
1714         mutex_unlock(&dev->struct_mutex);
1715
1716         kfree(work);
1717 }
1718
1719 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720 {
1721         if (dev_priv->fbc_work == NULL)
1722                 return;
1723
1724         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726         /* Synchronisation is provided by struct_mutex and checking of
1727          * dev_priv->fbc_work, so we can perform the cancellation
1728          * entirely asynchronously.
1729          */
1730         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731                 /* tasklet was killed before being run, clean up */
1732                 kfree(dev_priv->fbc_work);
1733
1734         /* Mark the work as no longer wanted so that if it does
1735          * wake-up (because the work was already running and waiting
1736          * for our mutex), it will discover that is no longer
1737          * necessary to run.
1738          */
1739         dev_priv->fbc_work = NULL;
1740 }
1741
1742 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1743 {
1744         struct intel_fbc_work *work;
1745         struct drm_device *dev = crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         if (!dev_priv->display.enable_fbc)
1749                 return;
1750
1751         intel_cancel_fbc_work(dev_priv);
1752
1753         work = kzalloc(sizeof *work, GFP_KERNEL);
1754         if (work == NULL) {
1755                 dev_priv->display.enable_fbc(crtc, interval);
1756                 return;
1757         }
1758
1759         work->crtc = crtc;
1760         work->fb = crtc->fb;
1761         work->interval = interval;
1762         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764         dev_priv->fbc_work = work;
1765
1766         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768         /* Delay the actual enabling to let pageflipping cease and the
1769          * display to settle before starting the compression. Note that
1770          * this delay also serves a second purpose: it allows for a
1771          * vblank to pass after disabling the FBC before we attempt
1772          * to modify the control registers.
1773          *
1774          * A more complicated solution would involve tracking vblanks
1775          * following the termination of the page-flipping sequence
1776          * and indeed performing the enable as a co-routine and not
1777          * waiting synchronously upon the vblank.
1778          */
1779         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1780 }
1781
1782 void intel_disable_fbc(struct drm_device *dev)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785
1786         intel_cancel_fbc_work(dev_priv);
1787
1788         if (!dev_priv->display.disable_fbc)
1789                 return;
1790
1791         dev_priv->display.disable_fbc(dev);
1792         dev_priv->cfb_plane = -1;
1793 }
1794
1795 /**
1796  * intel_update_fbc - enable/disable FBC as needed
1797  * @dev: the drm_device
1798  *
1799  * Set up the framebuffer compression hardware at mode set time.  We
1800  * enable it if possible:
1801  *   - plane A only (on pre-965)
1802  *   - no pixel mulitply/line duplication
1803  *   - no alpha buffer discard
1804  *   - no dual wide
1805  *   - framebuffer <= 2048 in width, 1536 in height
1806  *
1807  * We can't assume that any compression will take place (worst case),
1808  * so the compressed buffer has to be the same size as the uncompressed
1809  * one.  It also must reside (along with the line length buffer) in
1810  * stolen memory.
1811  *
1812  * We need to enable/disable FBC on a global basis.
1813  */
1814 static void intel_update_fbc(struct drm_device *dev)
1815 {
1816         struct drm_i915_private *dev_priv = dev->dev_private;
1817         struct drm_crtc *crtc = NULL, *tmp_crtc;
1818         struct intel_crtc *intel_crtc;
1819         struct drm_framebuffer *fb;
1820         struct intel_framebuffer *intel_fb;
1821         struct drm_i915_gem_object *obj;
1822         int enable_fbc;
1823
1824         DRM_DEBUG_KMS("\n");
1825
1826         if (!i915_powersave)
1827                 return;
1828
1829         if (!I915_HAS_FBC(dev))
1830                 return;
1831
1832         /*
1833          * If FBC is already on, we just have to verify that we can
1834          * keep it that way...
1835          * Need to disable if:
1836          *   - more than one pipe is active
1837          *   - changing FBC params (stride, fence, mode)
1838          *   - new fb is too large to fit in compressed buffer
1839          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1840          */
1841         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1842                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1843                         if (crtc) {
1844                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846                                 goto out_disable;
1847                         }
1848                         crtc = tmp_crtc;
1849                 }
1850         }
1851
1852         if (!crtc || crtc->fb == NULL) {
1853                 DRM_DEBUG_KMS("no output, disabling\n");
1854                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1855                 goto out_disable;
1856         }
1857
1858         intel_crtc = to_intel_crtc(crtc);
1859         fb = crtc->fb;
1860         intel_fb = to_intel_framebuffer(fb);
1861         obj = intel_fb->obj;
1862
1863         enable_fbc = i915_enable_fbc;
1864         if (enable_fbc < 0) {
1865                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866                 enable_fbc = 1;
1867                 if (INTEL_INFO(dev)->gen <= 6)
1868                         enable_fbc = 0;
1869         }
1870         if (!enable_fbc) {
1871                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1872                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873                 goto out_disable;
1874         }
1875         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1876                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1877                               "compression\n");
1878                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1879                 goto out_disable;
1880         }
1881         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1883                 DRM_DEBUG_KMS("mode incompatible with compression, "
1884                               "disabling\n");
1885                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1886                 goto out_disable;
1887         }
1888         if ((crtc->mode.hdisplay > 2048) ||
1889             (crtc->mode.vdisplay > 1536)) {
1890                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1891                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1892                 goto out_disable;
1893         }
1894         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1895                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1896                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1897                 goto out_disable;
1898         }
1899
1900         /* The use of a CPU fence is mandatory in order to detect writes
1901          * by the CPU to the scanout and trigger updates to the FBC.
1902          */
1903         if (obj->tiling_mode != I915_TILING_X ||
1904             obj->fence_reg == I915_FENCE_REG_NONE) {
1905                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1906                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1907                 goto out_disable;
1908         }
1909
1910         /* If the kernel debugger is active, always disable compression */
1911         if (in_dbg_master())
1912                 goto out_disable;
1913
1914         /* If the scanout has not changed, don't modify the FBC settings.
1915          * Note that we make the fundamental assumption that the fb->obj
1916          * cannot be unpinned (and have its GTT offset and fence revoked)
1917          * without first being decoupled from the scanout and FBC disabled.
1918          */
1919         if (dev_priv->cfb_plane == intel_crtc->plane &&
1920             dev_priv->cfb_fb == fb->base.id &&
1921             dev_priv->cfb_y == crtc->y)
1922                 return;
1923
1924         if (intel_fbc_enabled(dev)) {
1925                 /* We update FBC along two paths, after changing fb/crtc
1926                  * configuration (modeswitching) and after page-flipping
1927                  * finishes. For the latter, we know that not only did
1928                  * we disable the FBC at the start of the page-flip
1929                  * sequence, but also more than one vblank has passed.
1930                  *
1931                  * For the former case of modeswitching, it is possible
1932                  * to switch between two FBC valid configurations
1933                  * instantaneously so we do need to disable the FBC
1934                  * before we can modify its control registers. We also
1935                  * have to wait for the next vblank for that to take
1936                  * effect. However, since we delay enabling FBC we can
1937                  * assume that a vblank has passed since disabling and
1938                  * that we can safely alter the registers in the deferred
1939                  * callback.
1940                  *
1941                  * In the scenario that we go from a valid to invalid
1942                  * and then back to valid FBC configuration we have
1943                  * no strict enforcement that a vblank occurred since
1944                  * disabling the FBC. However, along all current pipe
1945                  * disabling paths we do need to wait for a vblank at
1946                  * some point. And we wait before enabling FBC anyway.
1947                  */
1948                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949                 intel_disable_fbc(dev);
1950         }
1951
1952         intel_enable_fbc(crtc, 500);
1953         return;
1954
1955 out_disable:
1956         /* Multiple disables should be harmless */
1957         if (intel_fbc_enabled(dev)) {
1958                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1959                 intel_disable_fbc(dev);
1960         }
1961 }
1962
1963 int
1964 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1965                            struct drm_i915_gem_object *obj,
1966                            struct intel_ring_buffer *pipelined)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         u32 alignment;
1970         int ret;
1971
1972         switch (obj->tiling_mode) {
1973         case I915_TILING_NONE:
1974                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975                         alignment = 128 * 1024;
1976                 else if (INTEL_INFO(dev)->gen >= 4)
1977                         alignment = 4 * 1024;
1978                 else
1979                         alignment = 64 * 1024;
1980                 break;
1981         case I915_TILING_X:
1982                 /* pin() will align the object as required by fence */
1983                 alignment = 0;
1984                 break;
1985         case I915_TILING_Y:
1986                 /* FIXME: Is this true? */
1987                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988                 return -EINVAL;
1989         default:
1990                 BUG();
1991         }
1992
1993         dev_priv->mm.interruptible = false;
1994         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1995         if (ret)
1996                 goto err_interruptible;
1997
1998         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999          * fence, whereas 965+ only requires a fence if using
2000          * framebuffer compression.  For simplicity, we always install
2001          * a fence as the cost is not that onerous.
2002          */
2003         if (obj->tiling_mode != I915_TILING_NONE) {
2004                 ret = i915_gem_object_get_fence(obj, pipelined);
2005                 if (ret)
2006                         goto err_unpin;
2007         }
2008
2009         dev_priv->mm.interruptible = true;
2010         return 0;
2011
2012 err_unpin:
2013         i915_gem_object_unpin(obj);
2014 err_interruptible:
2015         dev_priv->mm.interruptible = true;
2016         return ret;
2017 }
2018
2019 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020                              int x, int y)
2021 {
2022         struct drm_device *dev = crtc->dev;
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025         struct intel_framebuffer *intel_fb;
2026         struct drm_i915_gem_object *obj;
2027         int plane = intel_crtc->plane;
2028         unsigned long Start, Offset;
2029         u32 dspcntr;
2030         u32 reg;
2031
2032         switch (plane) {
2033         case 0:
2034         case 1:
2035                 break;
2036         default:
2037                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038                 return -EINVAL;
2039         }
2040
2041         intel_fb = to_intel_framebuffer(fb);
2042         obj = intel_fb->obj;
2043
2044         reg = DSPCNTR(plane);
2045         dspcntr = I915_READ(reg);
2046         /* Mask out pixel format bits in case we change it */
2047         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048         switch (fb->bits_per_pixel) {
2049         case 8:
2050                 dspcntr |= DISPPLANE_8BPP;
2051                 break;
2052         case 16:
2053                 if (fb->depth == 15)
2054                         dspcntr |= DISPPLANE_15_16BPP;
2055                 else
2056                         dspcntr |= DISPPLANE_16BPP;
2057                 break;
2058         case 24:
2059         case 32:
2060                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061                 break;
2062         default:
2063                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2064                 return -EINVAL;
2065         }
2066         if (INTEL_INFO(dev)->gen >= 4) {
2067                 if (obj->tiling_mode != I915_TILING_NONE)
2068                         dspcntr |= DISPPLANE_TILED;
2069                 else
2070                         dspcntr &= ~DISPPLANE_TILED;
2071         }
2072
2073         I915_WRITE(reg, dspcntr);
2074
2075         Start = obj->gtt_offset;
2076         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
2078         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079                       Start, Offset, x, y, fb->pitch);
2080         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2081         if (INTEL_INFO(dev)->gen >= 4) {
2082                 I915_WRITE(DSPSURF(plane), Start);
2083                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084                 I915_WRITE(DSPADDR(plane), Offset);
2085         } else
2086                 I915_WRITE(DSPADDR(plane), Start + Offset);
2087         POSTING_READ(reg);
2088
2089         return 0;
2090 }
2091
2092 static int ironlake_update_plane(struct drm_crtc *crtc,
2093                                  struct drm_framebuffer *fb, int x, int y)
2094 {
2095         struct drm_device *dev = crtc->dev;
2096         struct drm_i915_private *dev_priv = dev->dev_private;
2097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098         struct intel_framebuffer *intel_fb;
2099         struct drm_i915_gem_object *obj;
2100         int plane = intel_crtc->plane;
2101         unsigned long Start, Offset;
2102         u32 dspcntr;
2103         u32 reg;
2104
2105         switch (plane) {
2106         case 0:
2107         case 1:
2108         case 2:
2109                 break;
2110         default:
2111                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112                 return -EINVAL;
2113         }
2114
2115         intel_fb = to_intel_framebuffer(fb);
2116         obj = intel_fb->obj;
2117
2118         reg = DSPCNTR(plane);
2119         dspcntr = I915_READ(reg);
2120         /* Mask out pixel format bits in case we change it */
2121         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122         switch (fb->bits_per_pixel) {
2123         case 8:
2124                 dspcntr |= DISPPLANE_8BPP;
2125                 break;
2126         case 16:
2127                 if (fb->depth != 16)
2128                         return -EINVAL;
2129
2130                 dspcntr |= DISPPLANE_16BPP;
2131                 break;
2132         case 24:
2133         case 32:
2134                 if (fb->depth == 24)
2135                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136                 else if (fb->depth == 30)
2137                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138                 else
2139                         return -EINVAL;
2140                 break;
2141         default:
2142                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143                 return -EINVAL;
2144         }
2145
2146         if (obj->tiling_mode != I915_TILING_NONE)
2147                 dspcntr |= DISPPLANE_TILED;
2148         else
2149                 dspcntr &= ~DISPPLANE_TILED;
2150
2151         /* must disable */
2152         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154         I915_WRITE(reg, dspcntr);
2155
2156         Start = obj->gtt_offset;
2157         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160                       Start, Offset, x, y, fb->pitch);
2161         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162         I915_WRITE(DSPSURF(plane), Start);
2163         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164         I915_WRITE(DSPADDR(plane), Offset);
2165         POSTING_READ(reg);
2166
2167         return 0;
2168 }
2169
2170 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 static int
2172 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173                            int x, int y, enum mode_set_atomic state)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         int ret;
2178
2179         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180         if (ret)
2181                 return ret;
2182
2183         intel_update_fbc(dev);
2184         intel_increase_pllclock(crtc);
2185
2186         return 0;
2187 }
2188
2189 static int
2190 intel_finish_fb(struct drm_framebuffer *old_fb)
2191 {
2192         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2193         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194         bool was_interruptible = dev_priv->mm.interruptible;
2195         int ret;
2196
2197         wait_event(dev_priv->pending_flip_queue,
2198                    atomic_read(&dev_priv->mm.wedged) ||
2199                    atomic_read(&obj->pending_flip) == 0);
2200
2201         /* Big Hammer, we also need to ensure that any pending
2202          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2203          * current scanout is retired before unpinning the old
2204          * framebuffer.
2205          *
2206          * This should only fail upon a hung GPU, in which case we
2207          * can safely continue.
2208          */
2209         dev_priv->mm.interruptible = false;
2210         ret = i915_gem_object_finish_gpu(obj);
2211         dev_priv->mm.interruptible = was_interruptible;
2212
2213         return ret;
2214 }
2215
2216 static int
2217 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2218                     struct drm_framebuffer *old_fb)
2219 {
2220         struct drm_device *dev = crtc->dev;
2221         struct drm_i915_master_private *master_priv;
2222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2223         int ret;
2224
2225         /* no fb bound */
2226         if (!crtc->fb) {
2227                 DRM_ERROR("No FB bound\n");
2228                 return 0;
2229         }
2230
2231         switch (intel_crtc->plane) {
2232         case 0:
2233         case 1:
2234                 break;
2235         case 2:
2236                 if (IS_IVYBRIDGE(dev))
2237                         break;
2238                 /* fall through otherwise */
2239         default:
2240                 DRM_ERROR("no plane for crtc\n");
2241                 return -EINVAL;
2242         }
2243
2244         mutex_lock(&dev->struct_mutex);
2245         ret = intel_pin_and_fence_fb_obj(dev,
2246                                          to_intel_framebuffer(crtc->fb)->obj,
2247                                          NULL);
2248         if (ret != 0) {
2249                 mutex_unlock(&dev->struct_mutex);
2250                 DRM_ERROR("pin & fence failed\n");
2251                 return ret;
2252         }
2253
2254         if (old_fb)
2255                 intel_finish_fb(old_fb);
2256
2257         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2258                                          LEAVE_ATOMIC_MODE_SET);
2259         if (ret) {
2260                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2261                 mutex_unlock(&dev->struct_mutex);
2262                 DRM_ERROR("failed to update base address\n");
2263                 return ret;
2264         }
2265
2266         if (old_fb) {
2267                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2268                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2269         }
2270
2271         mutex_unlock(&dev->struct_mutex);
2272
2273         if (!dev->primary->master)
2274                 return 0;
2275
2276         master_priv = dev->primary->master->driver_priv;
2277         if (!master_priv->sarea_priv)
2278                 return 0;
2279
2280         if (intel_crtc->pipe) {
2281                 master_priv->sarea_priv->pipeB_x = x;
2282                 master_priv->sarea_priv->pipeB_y = y;
2283         } else {
2284                 master_priv->sarea_priv->pipeA_x = x;
2285                 master_priv->sarea_priv->pipeA_y = y;
2286         }
2287
2288         return 0;
2289 }
2290
2291 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2292 {
2293         struct drm_device *dev = crtc->dev;
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         u32 dpa_ctl;
2296
2297         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2298         dpa_ctl = I915_READ(DP_A);
2299         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2300
2301         if (clock < 200000) {
2302                 u32 temp;
2303                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2304                 /* workaround for 160Mhz:
2305                    1) program 0x4600c bits 15:0 = 0x8124
2306                    2) program 0x46010 bit 0 = 1
2307                    3) program 0x46034 bit 24 = 1
2308                    4) program 0x64000 bit 14 = 1
2309                    */
2310                 temp = I915_READ(0x4600c);
2311                 temp &= 0xffff0000;
2312                 I915_WRITE(0x4600c, temp | 0x8124);
2313
2314                 temp = I915_READ(0x46010);
2315                 I915_WRITE(0x46010, temp | 1);
2316
2317                 temp = I915_READ(0x46034);
2318                 I915_WRITE(0x46034, temp | (1 << 24));
2319         } else {
2320                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2321         }
2322         I915_WRITE(DP_A, dpa_ctl);
2323
2324         POSTING_READ(DP_A);
2325         udelay(500);
2326 }
2327
2328 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2329 {
2330         struct drm_device *dev = crtc->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2333         int pipe = intel_crtc->pipe;
2334         u32 reg, temp;
2335
2336         /* enable normal train */
2337         reg = FDI_TX_CTL(pipe);
2338         temp = I915_READ(reg);
2339         if (IS_IVYBRIDGE(dev)) {
2340                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2341                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2342         } else {
2343                 temp &= ~FDI_LINK_TRAIN_NONE;
2344                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         }
2346         I915_WRITE(reg, temp);
2347
2348         reg = FDI_RX_CTL(pipe);
2349         temp = I915_READ(reg);
2350         if (HAS_PCH_CPT(dev)) {
2351                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2352                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2353         } else {
2354                 temp &= ~FDI_LINK_TRAIN_NONE;
2355                 temp |= FDI_LINK_TRAIN_NONE;
2356         }
2357         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2358
2359         /* wait one idle pattern time */
2360         POSTING_READ(reg);
2361         udelay(1000);
2362
2363         /* IVB wants error correction enabled */
2364         if (IS_IVYBRIDGE(dev))
2365                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2366                            FDI_FE_ERRC_ENABLE);
2367 }
2368
2369 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2370 {
2371         struct drm_i915_private *dev_priv = dev->dev_private;
2372         u32 flags = I915_READ(SOUTH_CHICKEN1);
2373
2374         flags |= FDI_PHASE_SYNC_OVR(pipe);
2375         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2376         flags |= FDI_PHASE_SYNC_EN(pipe);
2377         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2378         POSTING_READ(SOUTH_CHICKEN1);
2379 }
2380
2381 /* The FDI link training functions for ILK/Ibexpeak. */
2382 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2383 {
2384         struct drm_device *dev = crtc->dev;
2385         struct drm_i915_private *dev_priv = dev->dev_private;
2386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2387         int pipe = intel_crtc->pipe;
2388         int plane = intel_crtc->plane;
2389         u32 reg, temp, tries;
2390
2391         /* FDI needs bits from pipe & plane first */
2392         assert_pipe_enabled(dev_priv, pipe);
2393         assert_plane_enabled(dev_priv, plane);
2394
2395         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2396            for train result */
2397         reg = FDI_RX_IMR(pipe);
2398         temp = I915_READ(reg);
2399         temp &= ~FDI_RX_SYMBOL_LOCK;
2400         temp &= ~FDI_RX_BIT_LOCK;
2401         I915_WRITE(reg, temp);
2402         I915_READ(reg);
2403         udelay(150);
2404
2405         /* enable CPU FDI TX and PCH FDI RX */
2406         reg = FDI_TX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         temp &= ~(7 << 19);
2409         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2410         temp &= ~FDI_LINK_TRAIN_NONE;
2411         temp |= FDI_LINK_TRAIN_PATTERN_1;
2412         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2413
2414         reg = FDI_RX_CTL(pipe);
2415         temp = I915_READ(reg);
2416         temp &= ~FDI_LINK_TRAIN_NONE;
2417         temp |= FDI_LINK_TRAIN_PATTERN_1;
2418         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2419
2420         POSTING_READ(reg);
2421         udelay(150);
2422
2423         /* Ironlake workaround, enable clock pointer after FDI enable*/
2424         if (HAS_PCH_IBX(dev)) {
2425                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2426                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2427                            FDI_RX_PHASE_SYNC_POINTER_EN);
2428         }
2429
2430         reg = FDI_RX_IIR(pipe);
2431         for (tries = 0; tries < 5; tries++) {
2432                 temp = I915_READ(reg);
2433                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2434
2435                 if ((temp & FDI_RX_BIT_LOCK)) {
2436                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2437                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2438                         break;
2439                 }
2440         }
2441         if (tries == 5)
2442                 DRM_ERROR("FDI train 1 fail!\n");
2443
2444         /* Train 2 */
2445         reg = FDI_TX_CTL(pipe);
2446         temp = I915_READ(reg);
2447         temp &= ~FDI_LINK_TRAIN_NONE;
2448         temp |= FDI_LINK_TRAIN_PATTERN_2;
2449         I915_WRITE(reg, temp);
2450
2451         reg = FDI_RX_CTL(pipe);
2452         temp = I915_READ(reg);
2453         temp &= ~FDI_LINK_TRAIN_NONE;
2454         temp |= FDI_LINK_TRAIN_PATTERN_2;
2455         I915_WRITE(reg, temp);
2456
2457         POSTING_READ(reg);
2458         udelay(150);
2459
2460         reg = FDI_RX_IIR(pipe);
2461         for (tries = 0; tries < 5; tries++) {
2462                 temp = I915_READ(reg);
2463                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464
2465                 if (temp & FDI_RX_SYMBOL_LOCK) {
2466                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2467                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2468                         break;
2469                 }
2470         }
2471         if (tries == 5)
2472                 DRM_ERROR("FDI train 2 fail!\n");
2473
2474         DRM_DEBUG_KMS("FDI train done\n");
2475
2476 }
2477
2478 static const int snb_b_fdi_train_param[] = {
2479         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2480         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2481         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2482         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2483 };
2484
2485 /* The FDI link training functions for SNB/Cougarpoint. */
2486 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2487 {
2488         struct drm_device *dev = crtc->dev;
2489         struct drm_i915_private *dev_priv = dev->dev_private;
2490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2491         int pipe = intel_crtc->pipe;
2492         u32 reg, temp, i;
2493
2494         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2495            for train result */
2496         reg = FDI_RX_IMR(pipe);
2497         temp = I915_READ(reg);
2498         temp &= ~FDI_RX_SYMBOL_LOCK;
2499         temp &= ~FDI_RX_BIT_LOCK;
2500         I915_WRITE(reg, temp);
2501
2502         POSTING_READ(reg);
2503         udelay(150);
2504
2505         /* enable CPU FDI TX and PCH FDI RX */
2506         reg = FDI_TX_CTL(pipe);
2507         temp = I915_READ(reg);
2508         temp &= ~(7 << 19);
2509         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2510         temp &= ~FDI_LINK_TRAIN_NONE;
2511         temp |= FDI_LINK_TRAIN_PATTERN_1;
2512         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2513         /* SNB-B */
2514         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2515         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2516
2517         reg = FDI_RX_CTL(pipe);
2518         temp = I915_READ(reg);
2519         if (HAS_PCH_CPT(dev)) {
2520                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2521                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2522         } else {
2523                 temp &= ~FDI_LINK_TRAIN_NONE;
2524                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2525         }
2526         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2527
2528         POSTING_READ(reg);
2529         udelay(150);
2530
2531         if (HAS_PCH_CPT(dev))
2532                 cpt_phase_pointer_enable(dev, pipe);
2533
2534         for (i = 0; i < 4; i++) {
2535                 reg = FDI_TX_CTL(pipe);
2536                 temp = I915_READ(reg);
2537                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538                 temp |= snb_b_fdi_train_param[i];
2539                 I915_WRITE(reg, temp);
2540
2541                 POSTING_READ(reg);
2542                 udelay(500);
2543
2544                 reg = FDI_RX_IIR(pipe);
2545                 temp = I915_READ(reg);
2546                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547
2548                 if (temp & FDI_RX_BIT_LOCK) {
2549                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2550                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2551                         break;
2552                 }
2553         }
2554         if (i == 4)
2555                 DRM_ERROR("FDI train 1 fail!\n");
2556
2557         /* Train 2 */
2558         reg = FDI_TX_CTL(pipe);
2559         temp = I915_READ(reg);
2560         temp &= ~FDI_LINK_TRAIN_NONE;
2561         temp |= FDI_LINK_TRAIN_PATTERN_2;
2562         if (IS_GEN6(dev)) {
2563                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564                 /* SNB-B */
2565                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2566         }
2567         I915_WRITE(reg, temp);
2568
2569         reg = FDI_RX_CTL(pipe);
2570         temp = I915_READ(reg);
2571         if (HAS_PCH_CPT(dev)) {
2572                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2574         } else {
2575                 temp &= ~FDI_LINK_TRAIN_NONE;
2576                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2577         }
2578         I915_WRITE(reg, temp);
2579
2580         POSTING_READ(reg);
2581         udelay(150);
2582
2583         for (i = 0; i < 4; i++) {
2584                 reg = FDI_TX_CTL(pipe);
2585                 temp = I915_READ(reg);
2586                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587                 temp |= snb_b_fdi_train_param[i];
2588                 I915_WRITE(reg, temp);
2589
2590                 POSTING_READ(reg);
2591                 udelay(500);
2592
2593                 reg = FDI_RX_IIR(pipe);
2594                 temp = I915_READ(reg);
2595                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2596
2597                 if (temp & FDI_RX_SYMBOL_LOCK) {
2598                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2599                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2600                         break;
2601                 }
2602         }
2603         if (i == 4)
2604                 DRM_ERROR("FDI train 2 fail!\n");
2605
2606         DRM_DEBUG_KMS("FDI train done.\n");
2607 }
2608
2609 /* Manual link training for Ivy Bridge A0 parts */
2610 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2611 {
2612         struct drm_device *dev = crtc->dev;
2613         struct drm_i915_private *dev_priv = dev->dev_private;
2614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615         int pipe = intel_crtc->pipe;
2616         u32 reg, temp, i;
2617
2618         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2619            for train result */
2620         reg = FDI_RX_IMR(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~FDI_RX_SYMBOL_LOCK;
2623         temp &= ~FDI_RX_BIT_LOCK;
2624         I915_WRITE(reg, temp);
2625
2626         POSTING_READ(reg);
2627         udelay(150);
2628
2629         /* enable CPU FDI TX and PCH FDI RX */
2630         reg = FDI_TX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         temp &= ~(7 << 19);
2633         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2634         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2635         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2636         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2638         temp |= FDI_COMPOSITE_SYNC;
2639         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2640
2641         reg = FDI_RX_CTL(pipe);
2642         temp = I915_READ(reg);
2643         temp &= ~FDI_LINK_TRAIN_AUTO;
2644         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2645         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2646         temp |= FDI_COMPOSITE_SYNC;
2647         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2648
2649         POSTING_READ(reg);
2650         udelay(150);
2651
2652         if (HAS_PCH_CPT(dev))
2653                 cpt_phase_pointer_enable(dev, pipe);
2654
2655         for (i = 0; i < 4; i++) {
2656                 reg = FDI_TX_CTL(pipe);
2657                 temp = I915_READ(reg);
2658                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2659                 temp |= snb_b_fdi_train_param[i];
2660                 I915_WRITE(reg, temp);
2661
2662                 POSTING_READ(reg);
2663                 udelay(500);
2664
2665                 reg = FDI_RX_IIR(pipe);
2666                 temp = I915_READ(reg);
2667                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2668
2669                 if (temp & FDI_RX_BIT_LOCK ||
2670                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2671                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2672                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2673                         break;
2674                 }
2675         }
2676         if (i == 4)
2677                 DRM_ERROR("FDI train 1 fail!\n");
2678
2679         /* Train 2 */
2680         reg = FDI_TX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2683         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2684         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2686         I915_WRITE(reg, temp);
2687
2688         reg = FDI_RX_CTL(pipe);
2689         temp = I915_READ(reg);
2690         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2691         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2692         I915_WRITE(reg, temp);
2693
2694         POSTING_READ(reg);
2695         udelay(150);
2696
2697         for (i = 0; i < 4; i++) {
2698                 reg = FDI_TX_CTL(pipe);
2699                 temp = I915_READ(reg);
2700                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701                 temp |= snb_b_fdi_train_param[i];
2702                 I915_WRITE(reg, temp);
2703
2704                 POSTING_READ(reg);
2705                 udelay(500);
2706
2707                 reg = FDI_RX_IIR(pipe);
2708                 temp = I915_READ(reg);
2709                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711                 if (temp & FDI_RX_SYMBOL_LOCK) {
2712                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2714                         break;
2715                 }
2716         }
2717         if (i == 4)
2718                 DRM_ERROR("FDI train 2 fail!\n");
2719
2720         DRM_DEBUG_KMS("FDI train done.\n");
2721 }
2722
2723 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2724 {
2725         struct drm_device *dev = crtc->dev;
2726         struct drm_i915_private *dev_priv = dev->dev_private;
2727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2728         int pipe = intel_crtc->pipe;
2729         u32 reg, temp;
2730
2731         /* Write the TU size bits so error detection works */
2732         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2733                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2734
2735         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2736         reg = FDI_RX_CTL(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~((0x7 << 19) | (0x7 << 16));
2739         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2740         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2741         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2742
2743         POSTING_READ(reg);
2744         udelay(200);
2745
2746         /* Switch from Rawclk to PCDclk */
2747         temp = I915_READ(reg);
2748         I915_WRITE(reg, temp | FDI_PCDCLK);
2749
2750         POSTING_READ(reg);
2751         udelay(200);
2752
2753         /* Enable CPU FDI TX PLL, always on for Ironlake */
2754         reg = FDI_TX_CTL(pipe);
2755         temp = I915_READ(reg);
2756         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2757                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2758
2759                 POSTING_READ(reg);
2760                 udelay(100);
2761         }
2762 }
2763
2764 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2765 {
2766         struct drm_i915_private *dev_priv = dev->dev_private;
2767         u32 flags = I915_READ(SOUTH_CHICKEN1);
2768
2769         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2770         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2771         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2772         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2773         POSTING_READ(SOUTH_CHICKEN1);
2774 }
2775 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2776 {
2777         struct drm_device *dev = crtc->dev;
2778         struct drm_i915_private *dev_priv = dev->dev_private;
2779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780         int pipe = intel_crtc->pipe;
2781         u32 reg, temp;
2782
2783         /* disable CPU FDI tx and PCH FDI rx */
2784         reg = FDI_TX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2787         POSTING_READ(reg);
2788
2789         reg = FDI_RX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         temp &= ~(0x7 << 16);
2792         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2793         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2794
2795         POSTING_READ(reg);
2796         udelay(100);
2797
2798         /* Ironlake workaround, disable clock pointer after downing FDI */
2799         if (HAS_PCH_IBX(dev)) {
2800                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2801                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2802                            I915_READ(FDI_RX_CHICKEN(pipe) &
2803                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2804         } else if (HAS_PCH_CPT(dev)) {
2805                 cpt_phase_pointer_disable(dev, pipe);
2806         }
2807
2808         /* still set train pattern 1 */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         temp &= ~FDI_LINK_TRAIN_NONE;
2812         temp |= FDI_LINK_TRAIN_PATTERN_1;
2813         I915_WRITE(reg, temp);
2814
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         if (HAS_PCH_CPT(dev)) {
2818                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2820         } else {
2821                 temp &= ~FDI_LINK_TRAIN_NONE;
2822                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2823         }
2824         /* BPC in FDI rx is consistent with that in PIPECONF */
2825         temp &= ~(0x07 << 16);
2826         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2827         I915_WRITE(reg, temp);
2828
2829         POSTING_READ(reg);
2830         udelay(100);
2831 }
2832
2833 /*
2834  * When we disable a pipe, we need to clear any pending scanline wait events
2835  * to avoid hanging the ring, which we assume we are waiting on.
2836  */
2837 static void intel_clear_scanline_wait(struct drm_device *dev)
2838 {
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840         struct intel_ring_buffer *ring;
2841         u32 tmp;
2842
2843         if (IS_GEN2(dev))
2844                 /* Can't break the hang on i8xx */
2845                 return;
2846
2847         ring = LP_RING(dev_priv);
2848         tmp = I915_READ_CTL(ring);
2849         if (tmp & RING_WAIT)
2850                 I915_WRITE_CTL(ring, tmp);
2851 }
2852
2853 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2854 {
2855         struct drm_i915_gem_object *obj;
2856         struct drm_i915_private *dev_priv;
2857
2858         if (crtc->fb == NULL)
2859                 return;
2860
2861         obj = to_intel_framebuffer(crtc->fb)->obj;
2862         dev_priv = crtc->dev->dev_private;
2863         wait_event(dev_priv->pending_flip_queue,
2864                    atomic_read(&obj->pending_flip) == 0);
2865 }
2866
2867 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2868 {
2869         struct drm_device *dev = crtc->dev;
2870         struct drm_mode_config *mode_config = &dev->mode_config;
2871         struct intel_encoder *encoder;
2872
2873         /*
2874          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2875          * must be driven by its own crtc; no sharing is possible.
2876          */
2877         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2878                 if (encoder->base.crtc != crtc)
2879                         continue;
2880
2881                 switch (encoder->type) {
2882                 case INTEL_OUTPUT_EDP:
2883                         if (!intel_encoder_is_pch_edp(&encoder->base))
2884                                 return false;
2885                         continue;
2886                 }
2887         }
2888
2889         return true;
2890 }
2891
2892 /*
2893  * Enable PCH resources required for PCH ports:
2894  *   - PCH PLLs
2895  *   - FDI training & RX/TX
2896  *   - update transcoder timings
2897  *   - DP transcoding bits
2898  *   - transcoder
2899  */
2900 static void ironlake_pch_enable(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905         int pipe = intel_crtc->pipe;
2906         u32 reg, temp, transc_sel;
2907
2908         /* For PCH output, training FDI link */
2909         dev_priv->display.fdi_link_train(crtc);
2910
2911         intel_enable_pch_pll(dev_priv, pipe);
2912
2913         if (HAS_PCH_CPT(dev)) {
2914                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2915                         TRANSC_DPLLB_SEL;
2916
2917                 /* Be sure PCH DPLL SEL is set */
2918                 temp = I915_READ(PCH_DPLL_SEL);
2919                 if (pipe == 0) {
2920                         temp &= ~(TRANSA_DPLLB_SEL);
2921                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2922                 } else if (pipe == 1) {
2923                         temp &= ~(TRANSB_DPLLB_SEL);
2924                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2925                 } else if (pipe == 2) {
2926                         temp &= ~(TRANSC_DPLLB_SEL);
2927                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2928                 }
2929                 I915_WRITE(PCH_DPLL_SEL, temp);
2930         }
2931
2932         /* set transcoder timing, panel must allow it */
2933         assert_panel_unlocked(dev_priv, pipe);
2934         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2935         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2936         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2937
2938         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2939         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2940         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2941
2942         intel_fdi_normal_train(crtc);
2943
2944         /* For PCH DP, enable TRANS_DP_CTL */
2945         if (HAS_PCH_CPT(dev) &&
2946             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2947              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2948                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2949                 reg = TRANS_DP_CTL(pipe);
2950                 temp = I915_READ(reg);
2951                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2952                           TRANS_DP_SYNC_MASK |
2953                           TRANS_DP_BPC_MASK);
2954                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2955                          TRANS_DP_ENH_FRAMING);
2956                 temp |= bpc << 9; /* same format but at 11:9 */
2957
2958                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2959                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2960                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2961                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2962
2963                 switch (intel_trans_dp_port_sel(crtc)) {
2964                 case PCH_DP_B:
2965                         temp |= TRANS_DP_PORT_SEL_B;
2966                         break;
2967                 case PCH_DP_C:
2968                         temp |= TRANS_DP_PORT_SEL_C;
2969                         break;
2970                 case PCH_DP_D:
2971                         temp |= TRANS_DP_PORT_SEL_D;
2972                         break;
2973                 default:
2974                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2975                         temp |= TRANS_DP_PORT_SEL_B;
2976                         break;
2977                 }
2978
2979                 I915_WRITE(reg, temp);
2980         }
2981
2982         intel_enable_transcoder(dev_priv, pipe);
2983 }
2984
2985 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2986 {
2987         struct drm_i915_private *dev_priv = dev->dev_private;
2988         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2989         u32 temp;
2990
2991         temp = I915_READ(dslreg);
2992         udelay(500);
2993         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2994                 /* Without this, mode sets may fail silently on FDI */
2995                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2996                 udelay(250);
2997                 I915_WRITE(tc2reg, 0);
2998                 if (wait_for(I915_READ(dslreg) != temp, 5))
2999                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3000         }
3001 }
3002
3003 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3004 {
3005         struct drm_device *dev = crtc->dev;
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008         int pipe = intel_crtc->pipe;
3009         int plane = intel_crtc->plane;
3010         u32 temp;
3011         bool is_pch_port;
3012
3013         if (intel_crtc->active)
3014                 return;
3015
3016         intel_crtc->active = true;
3017         intel_update_watermarks(dev);
3018
3019         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3020                 temp = I915_READ(PCH_LVDS);
3021                 if ((temp & LVDS_PORT_EN) == 0)
3022                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3023         }
3024
3025         is_pch_port = intel_crtc_driving_pch(crtc);
3026
3027         if (is_pch_port)
3028                 ironlake_fdi_pll_enable(crtc);
3029         else
3030                 ironlake_fdi_disable(crtc);
3031
3032         /* Enable panel fitting for LVDS */
3033         if (dev_priv->pch_pf_size &&
3034             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3035                 /* Force use of hard-coded filter coefficients
3036                  * as some pre-programmed values are broken,
3037                  * e.g. x201.
3038                  */
3039                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3040                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3041                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3042         }
3043
3044         /*
3045          * On ILK+ LUT must be loaded before the pipe is running but with
3046          * clocks enabled
3047          */
3048         intel_crtc_load_lut(crtc);
3049
3050         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3051         intel_enable_plane(dev_priv, plane, pipe);
3052
3053         if (is_pch_port)
3054                 ironlake_pch_enable(crtc);
3055
3056         mutex_lock(&dev->struct_mutex);
3057         intel_update_fbc(dev);
3058         mutex_unlock(&dev->struct_mutex);
3059
3060         intel_crtc_update_cursor(crtc, true);
3061 }
3062
3063 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3064 {
3065         struct drm_device *dev = crtc->dev;
3066         struct drm_i915_private *dev_priv = dev->dev_private;
3067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3068         int pipe = intel_crtc->pipe;
3069         int plane = intel_crtc->plane;
3070         u32 reg, temp;
3071
3072         if (!intel_crtc->active)
3073                 return;
3074
3075         intel_crtc_wait_for_pending_flips(crtc);
3076         drm_vblank_off(dev, pipe);
3077         intel_crtc_update_cursor(crtc, false);
3078
3079         intel_disable_plane(dev_priv, plane, pipe);
3080
3081         if (dev_priv->cfb_plane == plane)
3082                 intel_disable_fbc(dev);
3083
3084         intel_disable_pipe(dev_priv, pipe);
3085
3086         /* Disable PF */
3087         I915_WRITE(PF_CTL(pipe), 0);
3088         I915_WRITE(PF_WIN_SZ(pipe), 0);
3089
3090         ironlake_fdi_disable(crtc);
3091
3092         /* This is a horrible layering violation; we should be doing this in
3093          * the connector/encoder ->prepare instead, but we don't always have
3094          * enough information there about the config to know whether it will
3095          * actually be necessary or just cause undesired flicker.
3096          */
3097         intel_disable_pch_ports(dev_priv, pipe);
3098
3099         intel_disable_transcoder(dev_priv, pipe);
3100
3101         if (HAS_PCH_CPT(dev)) {
3102                 /* disable TRANS_DP_CTL */
3103                 reg = TRANS_DP_CTL(pipe);
3104                 temp = I915_READ(reg);
3105                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3106                 temp |= TRANS_DP_PORT_SEL_NONE;
3107                 I915_WRITE(reg, temp);
3108
3109                 /* disable DPLL_SEL */
3110                 temp = I915_READ(PCH_DPLL_SEL);
3111                 switch (pipe) {
3112                 case 0:
3113                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3114                         break;
3115                 case 1:
3116                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3117                         break;
3118                 case 2:
3119                         /* C shares PLL A or B */
3120                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3121                         break;
3122                 default:
3123                         BUG(); /* wtf */
3124                 }
3125                 I915_WRITE(PCH_DPLL_SEL, temp);
3126         }
3127
3128         /* disable PCH DPLL */
3129         if (!intel_crtc->no_pll)
3130                 intel_disable_pch_pll(dev_priv, pipe);
3131
3132         /* Switch from PCDclk to Rawclk */
3133         reg = FDI_RX_CTL(pipe);
3134         temp = I915_READ(reg);
3135         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3136
3137         /* Disable CPU FDI TX PLL */
3138         reg = FDI_TX_CTL(pipe);
3139         temp = I915_READ(reg);
3140         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3141
3142         POSTING_READ(reg);
3143         udelay(100);
3144
3145         reg = FDI_RX_CTL(pipe);
3146         temp = I915_READ(reg);
3147         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3148
3149         /* Wait for the clocks to turn off. */
3150         POSTING_READ(reg);
3151         udelay(100);
3152
3153         intel_crtc->active = false;
3154         intel_update_watermarks(dev);
3155
3156         mutex_lock(&dev->struct_mutex);
3157         intel_update_fbc(dev);
3158         intel_clear_scanline_wait(dev);
3159         mutex_unlock(&dev->struct_mutex);
3160 }
3161
3162 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3163 {
3164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165         int pipe = intel_crtc->pipe;
3166         int plane = intel_crtc->plane;
3167
3168         /* XXX: When our outputs are all unaware of DPMS modes other than off
3169          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3170          */
3171         switch (mode) {
3172         case DRM_MODE_DPMS_ON:
3173         case DRM_MODE_DPMS_STANDBY:
3174         case DRM_MODE_DPMS_SUSPEND:
3175                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3176                 ironlake_crtc_enable(crtc);
3177                 break;
3178
3179         case DRM_MODE_DPMS_OFF:
3180                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3181                 ironlake_crtc_disable(crtc);
3182                 break;
3183         }
3184 }
3185
3186 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3187 {
3188         if (!enable && intel_crtc->overlay) {
3189                 struct drm_device *dev = intel_crtc->base.dev;
3190                 struct drm_i915_private *dev_priv = dev->dev_private;
3191
3192                 mutex_lock(&dev->struct_mutex);
3193                 dev_priv->mm.interruptible = false;
3194                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3195                 dev_priv->mm.interruptible = true;
3196                 mutex_unlock(&dev->struct_mutex);
3197         }
3198
3199         /* Let userspace switch the overlay on again. In most cases userspace
3200          * has to recompute where to put it anyway.
3201          */
3202 }
3203
3204 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3205 {
3206         struct drm_device *dev = crtc->dev;
3207         struct drm_i915_private *dev_priv = dev->dev_private;
3208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3209         int pipe = intel_crtc->pipe;
3210         int plane = intel_crtc->plane;
3211
3212         if (intel_crtc->active)
3213                 return;
3214
3215         intel_crtc->active = true;
3216         intel_update_watermarks(dev);
3217
3218         intel_enable_pll(dev_priv, pipe);
3219         intel_enable_pipe(dev_priv, pipe, false);
3220         intel_enable_plane(dev_priv, plane, pipe);
3221
3222         intel_crtc_load_lut(crtc);
3223         intel_update_fbc(dev);
3224
3225         /* Give the overlay scaler a chance to enable if it's on this pipe */
3226         intel_crtc_dpms_overlay(intel_crtc, true);
3227         intel_crtc_update_cursor(crtc, true);
3228 }
3229
3230 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3231 {
3232         struct drm_device *dev = crtc->dev;
3233         struct drm_i915_private *dev_priv = dev->dev_private;
3234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3235         int pipe = intel_crtc->pipe;
3236         int plane = intel_crtc->plane;
3237
3238         if (!intel_crtc->active)
3239                 return;
3240
3241         /* Give the overlay scaler a chance to disable if it's on this pipe */
3242         intel_crtc_wait_for_pending_flips(crtc);
3243         drm_vblank_off(dev, pipe);
3244         intel_crtc_dpms_overlay(intel_crtc, false);
3245         intel_crtc_update_cursor(crtc, false);
3246
3247         if (dev_priv->cfb_plane == plane)
3248                 intel_disable_fbc(dev);
3249
3250         intel_disable_plane(dev_priv, plane, pipe);
3251         intel_disable_pipe(dev_priv, pipe);
3252         intel_disable_pll(dev_priv, pipe);
3253
3254         intel_crtc->active = false;
3255         intel_update_fbc(dev);
3256         intel_update_watermarks(dev);
3257         intel_clear_scanline_wait(dev);
3258 }
3259
3260 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3261 {
3262         /* XXX: When our outputs are all unaware of DPMS modes other than off
3263          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3264          */
3265         switch (mode) {
3266         case DRM_MODE_DPMS_ON:
3267         case DRM_MODE_DPMS_STANDBY:
3268         case DRM_MODE_DPMS_SUSPEND:
3269                 i9xx_crtc_enable(crtc);
3270                 break;
3271         case DRM_MODE_DPMS_OFF:
3272                 i9xx_crtc_disable(crtc);
3273                 break;
3274         }
3275 }
3276
3277 /**
3278  * Sets the power management mode of the pipe and plane.
3279  */
3280 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3281 {
3282         struct drm_device *dev = crtc->dev;
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         struct drm_i915_master_private *master_priv;
3285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286         int pipe = intel_crtc->pipe;
3287         bool enabled;
3288
3289         if (intel_crtc->dpms_mode == mode)
3290                 return;
3291
3292         intel_crtc->dpms_mode = mode;
3293
3294         dev_priv->display.dpms(crtc, mode);
3295
3296         if (!dev->primary->master)
3297                 return;
3298
3299         master_priv = dev->primary->master->driver_priv;
3300         if (!master_priv->sarea_priv)
3301                 return;
3302
3303         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3304
3305         switch (pipe) {
3306         case 0:
3307                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3308                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3309                 break;
3310         case 1:
3311                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3312                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3313                 break;
3314         default:
3315                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3316                 break;
3317         }
3318 }
3319
3320 static void intel_crtc_disable(struct drm_crtc *crtc)
3321 {
3322         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3323         struct drm_device *dev = crtc->dev;
3324
3325         /* Flush any pending WAITs before we disable the pipe. Note that
3326          * we need to drop the struct_mutex in order to acquire it again
3327          * during the lowlevel dpms routines around a couple of the
3328          * operations. It does not look trivial nor desirable to move
3329          * that locking higher. So instead we leave a window for the
3330          * submission of further commands on the fb before we can actually
3331          * disable it. This race with userspace exists anyway, and we can
3332          * only rely on the pipe being disabled by userspace after it
3333          * receives the hotplug notification and has flushed any pending
3334          * batches.
3335          */
3336         if (crtc->fb) {
3337                 mutex_lock(&dev->struct_mutex);
3338                 intel_finish_fb(crtc->fb);
3339                 mutex_unlock(&dev->struct_mutex);
3340         }
3341
3342         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3343
3344         if (crtc->fb) {
3345                 mutex_lock(&dev->struct_mutex);
3346                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3347                 mutex_unlock(&dev->struct_mutex);
3348         }
3349 }
3350
3351 /* Prepare for a mode set.
3352  *
3353  * Note we could be a lot smarter here.  We need to figure out which outputs
3354  * will be enabled, which disabled (in short, how the config will changes)
3355  * and perform the minimum necessary steps to accomplish that, e.g. updating
3356  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3357  * panel fitting is in the proper state, etc.
3358  */
3359 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3360 {
3361         i9xx_crtc_disable(crtc);
3362 }
3363
3364 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3365 {
3366         i9xx_crtc_enable(crtc);
3367 }
3368
3369 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3370 {
3371         ironlake_crtc_disable(crtc);
3372 }
3373
3374 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3375 {
3376         ironlake_crtc_enable(crtc);
3377 }
3378
3379 void intel_encoder_prepare(struct drm_encoder *encoder)
3380 {
3381         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3382         /* lvds has its own version of prepare see intel_lvds_prepare */
3383         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3384 }
3385
3386 void intel_encoder_commit(struct drm_encoder *encoder)
3387 {
3388         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3389         struct drm_device *dev = encoder->dev;
3390         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3391         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3392
3393         /* lvds has its own version of commit see intel_lvds_commit */
3394         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3395
3396         if (HAS_PCH_CPT(dev))
3397                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3398 }
3399
3400 void intel_encoder_destroy(struct drm_encoder *encoder)
3401 {
3402         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3403
3404         drm_encoder_cleanup(encoder);
3405         kfree(intel_encoder);
3406 }
3407
3408 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3409                                   struct drm_display_mode *mode,
3410                                   struct drm_display_mode *adjusted_mode)
3411 {
3412         struct drm_device *dev = crtc->dev;
3413
3414         if (HAS_PCH_SPLIT(dev)) {
3415                 /* FDI link clock is fixed at 2.7G */
3416                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3417                         return false;
3418         }
3419
3420         /* XXX some encoders set the crtcinfo, others don't.
3421          * Obviously we need some form of conflict resolution here...
3422          */
3423         if (adjusted_mode->crtc_htotal == 0)
3424                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3425
3426         return true;
3427 }
3428
3429 static int i945_get_display_clock_speed(struct drm_device *dev)
3430 {
3431         return 400000;
3432 }
3433
3434 static int i915_get_display_clock_speed(struct drm_device *dev)
3435 {
3436         return 333000;
3437 }
3438
3439 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3440 {
3441         return 200000;
3442 }
3443
3444 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3445 {
3446         u16 gcfgc = 0;
3447
3448         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3449
3450         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3451                 return 133000;
3452         else {
3453                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3454                 case GC_DISPLAY_CLOCK_333_MHZ:
3455                         return 333000;
3456                 default:
3457                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3458                         return 190000;
3459                 }
3460         }
3461 }
3462
3463 static int i865_get_display_clock_speed(struct drm_device *dev)
3464 {
3465         return 266000;
3466 }
3467
3468 static int i855_get_display_clock_speed(struct drm_device *dev)
3469 {
3470         u16 hpllcc = 0;
3471         /* Assume that the hardware is in the high speed state.  This
3472          * should be the default.
3473          */
3474         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3475         case GC_CLOCK_133_200:
3476         case GC_CLOCK_100_200:
3477                 return 200000;
3478         case GC_CLOCK_166_250:
3479                 return 250000;
3480         case GC_CLOCK_100_133:
3481                 return 133000;
3482         }
3483
3484         /* Shouldn't happen */
3485         return 0;
3486 }
3487
3488 static int i830_get_display_clock_speed(struct drm_device *dev)
3489 {
3490         return 133000;
3491 }
3492
3493 struct fdi_m_n {
3494         u32        tu;
3495         u32        gmch_m;
3496         u32        gmch_n;
3497         u32        link_m;
3498         u32        link_n;
3499 };
3500
3501 static void
3502 fdi_reduce_ratio(u32 *num, u32 *den)
3503 {
3504         while (*num > 0xffffff || *den > 0xffffff) {
3505                 *num >>= 1;
3506                 *den >>= 1;
3507         }
3508 }
3509
3510 static void
3511 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3512                      int link_clock, struct fdi_m_n *m_n)
3513 {
3514         m_n->tu = 64; /* default size */
3515
3516         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3517         m_n->gmch_m = bits_per_pixel * pixel_clock;
3518         m_n->gmch_n = link_clock * nlanes * 8;
3519         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3520
3521         m_n->link_m = pixel_clock;
3522         m_n->link_n = link_clock;
3523         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3524 }
3525
3526
3527 struct intel_watermark_params {
3528         unsigned long fifo_size;
3529         unsigned long max_wm;
3530         unsigned long default_wm;
3531         unsigned long guard_size;
3532         unsigned long cacheline_size;
3533 };
3534
3535 /* Pineview has different values for various configs */
3536 static const struct intel_watermark_params pineview_display_wm = {
3537         PINEVIEW_DISPLAY_FIFO,
3538         PINEVIEW_MAX_WM,
3539         PINEVIEW_DFT_WM,
3540         PINEVIEW_GUARD_WM,
3541         PINEVIEW_FIFO_LINE_SIZE
3542 };
3543 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3544         PINEVIEW_DISPLAY_FIFO,
3545         PINEVIEW_MAX_WM,
3546         PINEVIEW_DFT_HPLLOFF_WM,
3547         PINEVIEW_GUARD_WM,
3548         PINEVIEW_FIFO_LINE_SIZE
3549 };
3550 static const struct intel_watermark_params pineview_cursor_wm = {
3551         PINEVIEW_CURSOR_FIFO,
3552         PINEVIEW_CURSOR_MAX_WM,
3553         PINEVIEW_CURSOR_DFT_WM,
3554         PINEVIEW_CURSOR_GUARD_WM,
3555         PINEVIEW_FIFO_LINE_SIZE,
3556 };
3557 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3558         PINEVIEW_CURSOR_FIFO,
3559         PINEVIEW_CURSOR_MAX_WM,
3560         PINEVIEW_CURSOR_DFT_WM,
3561         PINEVIEW_CURSOR_GUARD_WM,
3562         PINEVIEW_FIFO_LINE_SIZE
3563 };
3564 static const struct intel_watermark_params g4x_wm_info = {
3565         G4X_FIFO_SIZE,
3566         G4X_MAX_WM,
3567         G4X_MAX_WM,
3568         2,
3569         G4X_FIFO_LINE_SIZE,
3570 };
3571 static const struct intel_watermark_params g4x_cursor_wm_info = {
3572         I965_CURSOR_FIFO,
3573         I965_CURSOR_MAX_WM,
3574         I965_CURSOR_DFT_WM,
3575         2,
3576         G4X_FIFO_LINE_SIZE,
3577 };
3578 static const struct intel_watermark_params i965_cursor_wm_info = {
3579         I965_CURSOR_FIFO,
3580         I965_CURSOR_MAX_WM,
3581         I965_CURSOR_DFT_WM,
3582         2,
3583         I915_FIFO_LINE_SIZE,
3584 };
3585 static const struct intel_watermark_params i945_wm_info = {
3586         I945_FIFO_SIZE,
3587         I915_MAX_WM,
3588         1,
3589         2,
3590         I915_FIFO_LINE_SIZE
3591 };
3592 static const struct intel_watermark_params i915_wm_info = {
3593         I915_FIFO_SIZE,
3594         I915_MAX_WM,
3595         1,
3596         2,
3597         I915_FIFO_LINE_SIZE
3598 };
3599 static const struct intel_watermark_params i855_wm_info = {
3600         I855GM_FIFO_SIZE,
3601         I915_MAX_WM,
3602         1,
3603         2,
3604         I830_FIFO_LINE_SIZE
3605 };
3606 static const struct intel_watermark_params i830_wm_info = {
3607         I830_FIFO_SIZE,
3608         I915_MAX_WM,
3609         1,
3610         2,
3611         I830_FIFO_LINE_SIZE
3612 };
3613
3614 static const struct intel_watermark_params ironlake_display_wm_info = {
3615         ILK_DISPLAY_FIFO,
3616         ILK_DISPLAY_MAXWM,
3617         ILK_DISPLAY_DFTWM,
3618         2,
3619         ILK_FIFO_LINE_SIZE
3620 };
3621 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3622         ILK_CURSOR_FIFO,
3623         ILK_CURSOR_MAXWM,
3624         ILK_CURSOR_DFTWM,
3625         2,
3626         ILK_FIFO_LINE_SIZE
3627 };
3628 static const struct intel_watermark_params ironlake_display_srwm_info = {
3629         ILK_DISPLAY_SR_FIFO,
3630         ILK_DISPLAY_MAX_SRWM,
3631         ILK_DISPLAY_DFT_SRWM,
3632         2,
3633         ILK_FIFO_LINE_SIZE
3634 };
3635 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3636         ILK_CURSOR_SR_FIFO,
3637         ILK_CURSOR_MAX_SRWM,
3638         ILK_CURSOR_DFT_SRWM,
3639         2,
3640         ILK_FIFO_LINE_SIZE
3641 };
3642
3643 static const struct intel_watermark_params sandybridge_display_wm_info = {
3644         SNB_DISPLAY_FIFO,
3645         SNB_DISPLAY_MAXWM,
3646         SNB_DISPLAY_DFTWM,
3647         2,
3648         SNB_FIFO_LINE_SIZE
3649 };
3650 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3651         SNB_CURSOR_FIFO,
3652         SNB_CURSOR_MAXWM,
3653         SNB_CURSOR_DFTWM,
3654         2,
3655         SNB_FIFO_LINE_SIZE
3656 };
3657 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3658         SNB_DISPLAY_SR_FIFO,
3659         SNB_DISPLAY_MAX_SRWM,
3660         SNB_DISPLAY_DFT_SRWM,
3661         2,
3662         SNB_FIFO_LINE_SIZE
3663 };
3664 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3665         SNB_CURSOR_SR_FIFO,
3666         SNB_CURSOR_MAX_SRWM,
3667         SNB_CURSOR_DFT_SRWM,
3668         2,
3669         SNB_FIFO_LINE_SIZE
3670 };
3671
3672
3673 /**
3674  * intel_calculate_wm - calculate watermark level
3675  * @clock_in_khz: pixel clock
3676  * @wm: chip FIFO params
3677  * @pixel_size: display pixel size
3678  * @latency_ns: memory latency for the platform
3679  *
3680  * Calculate the watermark level (the level at which the display plane will
3681  * start fetching from memory again).  Each chip has a different display
3682  * FIFO size and allocation, so the caller needs to figure that out and pass
3683  * in the correct intel_watermark_params structure.
3684  *
3685  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3686  * on the pixel size.  When it reaches the watermark level, it'll start
3687  * fetching FIFO line sized based chunks from memory until the FIFO fills
3688  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3689  * will occur, and a display engine hang could result.
3690  */
3691 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3692                                         const struct intel_watermark_params *wm,
3693                                         int fifo_size,
3694                                         int pixel_size,
3695                                         unsigned long latency_ns)
3696 {
3697         long entries_required, wm_size;
3698
3699         /*
3700          * Note: we need to make sure we don't overflow for various clock &
3701          * latency values.
3702          * clocks go from a few thousand to several hundred thousand.
3703          * latency is usually a few thousand
3704          */
3705         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3706                 1000;
3707         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3708
3709         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3710
3711         wm_size = fifo_size - (entries_required + wm->guard_size);
3712
3713         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3714
3715         /* Don't promote wm_size to unsigned... */
3716         if (wm_size > (long)wm->max_wm)
3717                 wm_size = wm->max_wm;
3718         if (wm_size <= 0)
3719                 wm_size = wm->default_wm;
3720         return wm_size;
3721 }
3722
3723 struct cxsr_latency {
3724         int is_desktop;
3725         int is_ddr3;
3726         unsigned long fsb_freq;
3727         unsigned long mem_freq;
3728         unsigned long display_sr;
3729         unsigned long display_hpll_disable;
3730         unsigned long cursor_sr;
3731         unsigned long cursor_hpll_disable;
3732 };
3733
3734 static const struct cxsr_latency cxsr_latency_table[] = {
3735         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3736         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3737         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3738         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3739         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3740
3741         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3742         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3743         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3744         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3745         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3746
3747         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3748         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3749         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3750         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3751         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3752
3753         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3754         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3755         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3756         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3757         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3758
3759         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3760         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3761         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3762         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3763         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3764
3765         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3766         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3767         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3768         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3769         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3770 };
3771
3772 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3773                                                          int is_ddr3,
3774                                                          int fsb,
3775                                                          int mem)
3776 {
3777         const struct cxsr_latency *latency;
3778         int i;
3779
3780         if (fsb == 0 || mem == 0)
3781                 return NULL;
3782
3783         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3784                 latency = &cxsr_latency_table[i];
3785                 if (is_desktop == latency->is_desktop &&
3786                     is_ddr3 == latency->is_ddr3 &&
3787                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3788                         return latency;
3789         }
3790
3791         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3792
3793         return NULL;
3794 }
3795
3796 static void pineview_disable_cxsr(struct drm_device *dev)
3797 {
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799
3800         /* deactivate cxsr */
3801         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3802 }
3803
3804 /*
3805  * Latency for FIFO fetches is dependent on several factors:
3806  *   - memory configuration (speed, channels)
3807  *   - chipset
3808  *   - current MCH state
3809  * It can be fairly high in some situations, so here we assume a fairly
3810  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3811  * set this value too high, the FIFO will fetch frequently to stay full)
3812  * and power consumption (set it too low to save power and we might see
3813  * FIFO underruns and display "flicker").
3814  *
3815  * A value of 5us seems to be a good balance; safe for very low end
3816  * platforms but not overly aggressive on lower latency configs.
3817  */
3818 static const int latency_ns = 5000;
3819
3820 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3821 {
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         uint32_t dsparb = I915_READ(DSPARB);
3824         int size;
3825
3826         size = dsparb & 0x7f;
3827         if (plane)
3828                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3829
3830         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3831                       plane ? "B" : "A", size);
3832
3833         return size;
3834 }
3835
3836 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3837 {
3838         struct drm_i915_private *dev_priv = dev->dev_private;
3839         uint32_t dsparb = I915_READ(DSPARB);
3840         int size;
3841
3842         size = dsparb & 0x1ff;
3843         if (plane)
3844                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3845         size >>= 1; /* Convert to cachelines */
3846
3847         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3848                       plane ? "B" : "A", size);
3849
3850         return size;
3851 }
3852
3853 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3854 {
3855         struct drm_i915_private *dev_priv = dev->dev_private;
3856         uint32_t dsparb = I915_READ(DSPARB);
3857         int size;
3858
3859         size = dsparb & 0x7f;
3860         size >>= 2; /* Convert to cachelines */
3861
3862         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3863                       plane ? "B" : "A",
3864                       size);
3865
3866         return size;
3867 }
3868
3869 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3870 {
3871         struct drm_i915_private *dev_priv = dev->dev_private;
3872         uint32_t dsparb = I915_READ(DSPARB);
3873         int size;
3874
3875         size = dsparb & 0x7f;
3876         size >>= 1; /* Convert to cachelines */
3877
3878         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3879                       plane ? "B" : "A", size);
3880
3881         return size;
3882 }
3883
3884 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3885 {
3886         struct drm_crtc *crtc, *enabled = NULL;
3887
3888         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3889                 if (crtc->enabled && crtc->fb) {
3890                         if (enabled)
3891                                 return NULL;
3892                         enabled = crtc;
3893                 }
3894         }
3895
3896         return enabled;
3897 }
3898
3899 static void pineview_update_wm(struct drm_device *dev)
3900 {
3901         struct drm_i915_private *dev_priv = dev->dev_private;
3902         struct drm_crtc *crtc;
3903         const struct cxsr_latency *latency;
3904         u32 reg;
3905         unsigned long wm;
3906
3907         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3908                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3909         if (!latency) {
3910                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3911                 pineview_disable_cxsr(dev);
3912                 return;
3913         }
3914
3915         crtc = single_enabled_crtc(dev);
3916         if (crtc) {
3917                 int clock = crtc->mode.clock;
3918                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3919
3920                 /* Display SR */
3921                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3922                                         pineview_display_wm.fifo_size,
3923                                         pixel_size, latency->display_sr);
3924                 reg = I915_READ(DSPFW1);
3925                 reg &= ~DSPFW_SR_MASK;
3926                 reg |= wm << DSPFW_SR_SHIFT;
3927                 I915_WRITE(DSPFW1, reg);
3928                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3929
3930                 /* cursor SR */
3931                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3932                                         pineview_display_wm.fifo_size,
3933                                         pixel_size, latency->cursor_sr);
3934                 reg = I915_READ(DSPFW3);
3935                 reg &= ~DSPFW_CURSOR_SR_MASK;
3936                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3937                 I915_WRITE(DSPFW3, reg);
3938
3939                 /* Display HPLL off SR */
3940                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3941                                         pineview_display_hplloff_wm.fifo_size,
3942                                         pixel_size, latency->display_hpll_disable);
3943                 reg = I915_READ(DSPFW3);
3944                 reg &= ~DSPFW_HPLL_SR_MASK;
3945                 reg |= wm & DSPFW_HPLL_SR_MASK;
3946                 I915_WRITE(DSPFW3, reg);
3947
3948                 /* cursor HPLL off SR */
3949                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3950                                         pineview_display_hplloff_wm.fifo_size,
3951                                         pixel_size, latency->cursor_hpll_disable);
3952                 reg = I915_READ(DSPFW3);
3953                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3954                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3955                 I915_WRITE(DSPFW3, reg);
3956                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3957
3958                 /* activate cxsr */
3959                 I915_WRITE(DSPFW3,
3960                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3961                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3962         } else {
3963                 pineview_disable_cxsr(dev);
3964                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3965         }
3966 }
3967
3968 static bool g4x_compute_wm0(struct drm_device *dev,
3969                             int plane,
3970                             const struct intel_watermark_params *display,
3971                             int display_latency_ns,
3972                             const struct intel_watermark_params *cursor,
3973                             int cursor_latency_ns,
3974                             int *plane_wm,
3975                             int *cursor_wm)
3976 {
3977         struct drm_crtc *crtc;
3978         int htotal, hdisplay, clock, pixel_size;
3979         int line_time_us, line_count;
3980         int entries, tlb_miss;
3981
3982         crtc = intel_get_crtc_for_plane(dev, plane);
3983         if (crtc->fb == NULL || !crtc->enabled) {
3984                 *cursor_wm = cursor->guard_size;
3985                 *plane_wm = display->guard_size;
3986                 return false;
3987         }
3988
3989         htotal = crtc->mode.htotal;
3990         hdisplay = crtc->mode.hdisplay;
3991         clock = crtc->mode.clock;
3992         pixel_size = crtc->fb->bits_per_pixel / 8;
3993
3994         /* Use the small buffer method to calculate plane watermark */
3995         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3996         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3997         if (tlb_miss > 0)
3998                 entries += tlb_miss;
3999         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4000         *plane_wm = entries + display->guard_size;
4001         if (*plane_wm > (int)display->max_wm)
4002                 *plane_wm = display->max_wm;
4003
4004         /* Use the large buffer method to calculate cursor watermark */
4005         line_time_us = ((htotal * 1000) / clock);
4006         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4007         entries = line_count * 64 * pixel_size;
4008         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4009         if (tlb_miss > 0)
4010                 entries += tlb_miss;
4011         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4012         *cursor_wm = entries + cursor->guard_size;
4013         if (*cursor_wm > (int)cursor->max_wm)
4014                 *cursor_wm = (int)cursor->max_wm;
4015
4016         return true;
4017 }
4018
4019 /*
4020  * Check the wm result.
4021  *
4022  * If any calculated watermark values is larger than the maximum value that
4023  * can be programmed into the associated watermark register, that watermark
4024  * must be disabled.
4025  */
4026 static bool g4x_check_srwm(struct drm_device *dev,
4027                            int display_wm, int cursor_wm,
4028                            const struct intel_watermark_params *display,
4029                            const struct intel_watermark_params *cursor)
4030 {
4031         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4032                       display_wm, cursor_wm);
4033
4034         if (display_wm > display->max_wm) {
4035                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4036                               display_wm, display->max_wm);
4037                 return false;
4038         }
4039
4040         if (cursor_wm > cursor->max_wm) {
4041                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4042                               cursor_wm, cursor->max_wm);
4043                 return false;
4044         }
4045
4046         if (!(display_wm || cursor_wm)) {
4047                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4048                 return false;
4049         }
4050
4051         return true;
4052 }
4053
4054 static bool g4x_compute_srwm(struct drm_device *dev,
4055                              int plane,
4056                              int latency_ns,
4057                              const struct intel_watermark_params *display,
4058                              const struct intel_watermark_params *cursor,
4059                              int *display_wm, int *cursor_wm)
4060 {
4061         struct drm_crtc *crtc;
4062         int hdisplay, htotal, pixel_size, clock;
4063         unsigned long line_time_us;
4064         int line_count, line_size;
4065         int small, large;
4066         int entries;
4067
4068         if (!latency_ns) {
4069                 *display_wm = *cursor_wm = 0;
4070                 return false;
4071         }
4072
4073         crtc = intel_get_crtc_for_plane(dev, plane);
4074         hdisplay = crtc->mode.hdisplay;
4075         htotal = crtc->mode.htotal;
4076         clock = crtc->mode.clock;
4077         pixel_size = crtc->fb->bits_per_pixel / 8;
4078
4079         line_time_us = (htotal * 1000) / clock;
4080         line_count = (latency_ns / line_time_us + 1000) / 1000;
4081         line_size = hdisplay * pixel_size;
4082
4083         /* Use the minimum of the small and large buffer method for primary */
4084         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4085         large = line_count * line_size;
4086
4087         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4088         *display_wm = entries + display->guard_size;
4089
4090         /* calculate the self-refresh watermark for display cursor */
4091         entries = line_count * pixel_size * 64;
4092         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4093         *cursor_wm = entries + cursor->guard_size;
4094
4095         return g4x_check_srwm(dev,
4096                               *display_wm, *cursor_wm,
4097                               display, cursor);
4098 }
4099
4100 #define single_plane_enabled(mask) is_power_of_2(mask)
4101
4102 static void g4x_update_wm(struct drm_device *dev)
4103 {
4104         static const int sr_latency_ns = 12000;
4105         struct drm_i915_private *dev_priv = dev->dev_private;
4106         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4107         int plane_sr, cursor_sr;
4108         unsigned int enabled = 0;
4109
4110         if (g4x_compute_wm0(dev, 0,
4111                             &g4x_wm_info, latency_ns,
4112                             &g4x_cursor_wm_info, latency_ns,
4113                             &planea_wm, &cursora_wm))
4114                 enabled |= 1;
4115
4116         if (g4x_compute_wm0(dev, 1,
4117                             &g4x_wm_info, latency_ns,
4118                             &g4x_cursor_wm_info, latency_ns,
4119                             &planeb_wm, &cursorb_wm))
4120                 enabled |= 2;
4121
4122         plane_sr = cursor_sr = 0;
4123         if (single_plane_enabled(enabled) &&
4124             g4x_compute_srwm(dev, ffs(enabled) - 1,
4125                              sr_latency_ns,
4126                              &g4x_wm_info,
4127                              &g4x_cursor_wm_info,
4128                              &plane_sr, &cursor_sr))
4129                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4130         else
4131                 I915_WRITE(FW_BLC_SELF,
4132                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4133
4134         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4135                       planea_wm, cursora_wm,
4136                       planeb_wm, cursorb_wm,
4137                       plane_sr, cursor_sr);
4138
4139         I915_WRITE(DSPFW1,
4140                    (plane_sr << DSPFW_SR_SHIFT) |
4141                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4142                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4143                    planea_wm);
4144         I915_WRITE(DSPFW2,
4145                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4146                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4147         /* HPLL off in SR has some issues on G4x... disable it */
4148         I915_WRITE(DSPFW3,
4149                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4150                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4151 }
4152
4153 static void i965_update_wm(struct drm_device *dev)
4154 {
4155         struct drm_i915_private *dev_priv = dev->dev_private;
4156         struct drm_crtc *crtc;
4157         int srwm = 1;
4158         int cursor_sr = 16;
4159
4160         /* Calc sr entries for one plane configs */
4161         crtc = single_enabled_crtc(dev);
4162         if (crtc) {
4163                 /* self-refresh has much higher latency */
4164                 static const int sr_latency_ns = 12000;
4165                 int clock = crtc->mode.clock;
4166                 int htotal = crtc->mode.htotal;
4167                 int hdisplay = crtc->mode.hdisplay;
4168                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4169                 unsigned long line_time_us;
4170                 int entries;
4171
4172                 line_time_us = ((htotal * 1000) / clock);
4173
4174                 /* Use ns/us then divide to preserve precision */
4175                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4176                         pixel_size * hdisplay;
4177                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4178                 srwm = I965_FIFO_SIZE - entries;
4179                 if (srwm < 0)
4180                         srwm = 1;
4181                 srwm &= 0x1ff;
4182                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4183                               entries, srwm);
4184
4185                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4186                         pixel_size * 64;
4187                 entries = DIV_ROUND_UP(entries,
4188                                           i965_cursor_wm_info.cacheline_size);
4189                 cursor_sr = i965_cursor_wm_info.fifo_size -
4190                         (entries + i965_cursor_wm_info.guard_size);
4191
4192                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4193                         cursor_sr = i965_cursor_wm_info.max_wm;
4194
4195                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4196                               "cursor %d\n", srwm, cursor_sr);
4197
4198                 if (IS_CRESTLINE(dev))
4199                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4200         } else {
4201                 /* Turn off self refresh if both pipes are enabled */
4202                 if (IS_CRESTLINE(dev))
4203                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4204                                    & ~FW_BLC_SELF_EN);
4205         }
4206
4207         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4208                       srwm);
4209
4210         /* 965 has limitations... */
4211         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4212                    (8 << 16) | (8 << 8) | (8 << 0));
4213         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4214         /* update cursor SR watermark */
4215         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4216 }
4217
4218 static void i9xx_update_wm(struct drm_device *dev)
4219 {
4220         struct drm_i915_private *dev_priv = dev->dev_private;
4221         const struct intel_watermark_params *wm_info;
4222         uint32_t fwater_lo;
4223         uint32_t fwater_hi;
4224         int cwm, srwm = 1;
4225         int fifo_size;
4226         int planea_wm, planeb_wm;
4227         struct drm_crtc *crtc, *enabled = NULL;
4228
4229         if (IS_I945GM(dev))
4230                 wm_info = &i945_wm_info;
4231         else if (!IS_GEN2(dev))
4232                 wm_info = &i915_wm_info;
4233         else
4234                 wm_info = &i855_wm_info;
4235
4236         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4237         crtc = intel_get_crtc_for_plane(dev, 0);
4238         if (crtc->enabled && crtc->fb) {
4239                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4240                                                wm_info, fifo_size,
4241                                                crtc->fb->bits_per_pixel / 8,
4242                                                latency_ns);
4243                 enabled = crtc;
4244         } else
4245                 planea_wm = fifo_size - wm_info->guard_size;
4246
4247         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4248         crtc = intel_get_crtc_for_plane(dev, 1);
4249         if (crtc->enabled && crtc->fb) {
4250                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4251                                                wm_info, fifo_size,
4252                                                crtc->fb->bits_per_pixel / 8,
4253                                                latency_ns);
4254                 if (enabled == NULL)
4255                         enabled = crtc;
4256                 else
4257                         enabled = NULL;
4258         } else
4259                 planeb_wm = fifo_size - wm_info->guard_size;
4260
4261         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4262
4263         /*
4264          * Overlay gets an aggressive default since video jitter is bad.
4265          */
4266         cwm = 2;
4267
4268         /* Play safe and disable self-refresh before adjusting watermarks. */
4269         if (IS_I945G(dev) || IS_I945GM(dev))
4270                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4271         else if (IS_I915GM(dev))
4272                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4273
4274         /* Calc sr entries for one plane configs */
4275         if (HAS_FW_BLC(dev) && enabled) {
4276                 /* self-refresh has much higher latency */
4277                 static const int sr_latency_ns = 6000;
4278                 int clock = enabled->mode.clock;
4279                 int htotal = enabled->mode.htotal;
4280                 int hdisplay = enabled->mode.hdisplay;
4281                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4282                 unsigned long line_time_us;
4283                 int entries;
4284
4285                 line_time_us = (htotal * 1000) / clock;
4286
4287                 /* Use ns/us then divide to preserve precision */
4288                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4289                         pixel_size * hdisplay;
4290                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4291                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4292                 srwm = wm_info->fifo_size - entries;
4293                 if (srwm < 0)
4294                         srwm = 1;
4295
4296                 if (IS_I945G(dev) || IS_I945GM(dev))
4297                         I915_WRITE(FW_BLC_SELF,
4298                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4299                 else if (IS_I915GM(dev))
4300                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4301         }
4302
4303         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4304                       planea_wm, planeb_wm, cwm, srwm);
4305
4306         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4307         fwater_hi = (cwm & 0x1f);
4308
4309         /* Set request length to 8 cachelines per fetch */
4310         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4311         fwater_hi = fwater_hi | (1 << 8);
4312
4313         I915_WRITE(FW_BLC, fwater_lo);
4314         I915_WRITE(FW_BLC2, fwater_hi);
4315
4316         if (HAS_FW_BLC(dev)) {
4317                 if (enabled) {
4318                         if (IS_I945G(dev) || IS_I945GM(dev))
4319                                 I915_WRITE(FW_BLC_SELF,
4320                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4321                         else if (IS_I915GM(dev))
4322                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4323                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4324                 } else
4325                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4326         }
4327 }
4328
4329 static void i830_update_wm(struct drm_device *dev)
4330 {
4331         struct drm_i915_private *dev_priv = dev->dev_private;
4332         struct drm_crtc *crtc;
4333         uint32_t fwater_lo;
4334         int planea_wm;
4335
4336         crtc = single_enabled_crtc(dev);
4337         if (crtc == NULL)
4338                 return;
4339
4340         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4341                                        dev_priv->display.get_fifo_size(dev, 0),
4342                                        crtc->fb->bits_per_pixel / 8,
4343                                        latency_ns);
4344         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4345         fwater_lo |= (3<<8) | planea_wm;
4346
4347         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4348
4349         I915_WRITE(FW_BLC, fwater_lo);
4350 }
4351
4352 #define ILK_LP0_PLANE_LATENCY           700
4353 #define ILK_LP0_CURSOR_LATENCY          1300
4354
4355 /*
4356  * Check the wm result.
4357  *
4358  * If any calculated watermark values is larger than the maximum value that
4359  * can be programmed into the associated watermark register, that watermark
4360  * must be disabled.
4361  */
4362 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4363                                 int fbc_wm, int display_wm, int cursor_wm,
4364                                 const struct intel_watermark_params *display,
4365                                 const struct intel_watermark_params *cursor)
4366 {
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368
4369         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4370                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4371
4372         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4373                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4374                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4375
4376                 /* fbc has it's own way to disable FBC WM */
4377                 I915_WRITE(DISP_ARB_CTL,
4378                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4379                 return false;
4380         }
4381
4382         if (display_wm > display->max_wm) {
4383                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4384                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4385                 return false;
4386         }
4387
4388         if (cursor_wm > cursor->max_wm) {
4389                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4390                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4391                 return false;
4392         }
4393
4394         if (!(fbc_wm || display_wm || cursor_wm)) {
4395                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4396                 return false;
4397         }
4398
4399         return true;
4400 }
4401
4402 /*
4403  * Compute watermark values of WM[1-3],
4404  */
4405 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4406                                   int latency_ns,
4407                                   const struct intel_watermark_params *display,
4408                                   const struct intel_watermark_params *cursor,
4409                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4410 {
4411         struct drm_crtc *crtc;
4412         unsigned long line_time_us;
4413         int hdisplay, htotal, pixel_size, clock;
4414         int line_count, line_size;
4415         int small, large;
4416         int entries;
4417
4418         if (!latency_ns) {
4419                 *fbc_wm = *display_wm = *cursor_wm = 0;
4420                 return false;
4421         }
4422
4423         crtc = intel_get_crtc_for_plane(dev, plane);
4424         hdisplay = crtc->mode.hdisplay;
4425         htotal = crtc->mode.htotal;
4426         clock = crtc->mode.clock;
4427         pixel_size = crtc->fb->bits_per_pixel / 8;
4428
4429         line_time_us = (htotal * 1000) / clock;
4430         line_count = (latency_ns / line_time_us + 1000) / 1000;
4431         line_size = hdisplay * pixel_size;
4432
4433         /* Use the minimum of the small and large buffer method for primary */
4434         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4435         large = line_count * line_size;
4436
4437         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4438         *display_wm = entries + display->guard_size;
4439
4440         /*
4441          * Spec says:
4442          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4443          */
4444         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4445
4446         /* calculate the self-refresh watermark for display cursor */
4447         entries = line_count * pixel_size * 64;
4448         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4449         *cursor_wm = entries + cursor->guard_size;
4450
4451         return ironlake_check_srwm(dev, level,
4452                                    *fbc_wm, *display_wm, *cursor_wm,
4453                                    display, cursor);
4454 }
4455
4456 static void ironlake_update_wm(struct drm_device *dev)
4457 {
4458         struct drm_i915_private *dev_priv = dev->dev_private;
4459         int fbc_wm, plane_wm, cursor_wm;
4460         unsigned int enabled;
4461
4462         enabled = 0;
4463         if (g4x_compute_wm0(dev, 0,
4464                             &ironlake_display_wm_info,
4465                             ILK_LP0_PLANE_LATENCY,
4466                             &ironlake_cursor_wm_info,
4467                             ILK_LP0_CURSOR_LATENCY,
4468                             &plane_wm, &cursor_wm)) {
4469                 I915_WRITE(WM0_PIPEA_ILK,
4470                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4471                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4472                               " plane %d, " "cursor: %d\n",
4473                               plane_wm, cursor_wm);
4474                 enabled |= 1;
4475         }
4476
4477         if (g4x_compute_wm0(dev, 1,
4478                             &ironlake_display_wm_info,
4479                             ILK_LP0_PLANE_LATENCY,
4480                             &ironlake_cursor_wm_info,
4481                             ILK_LP0_CURSOR_LATENCY,
4482                             &plane_wm, &cursor_wm)) {
4483                 I915_WRITE(WM0_PIPEB_ILK,
4484                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4485                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4486                               " plane %d, cursor: %d\n",
4487                               plane_wm, cursor_wm);
4488                 enabled |= 2;
4489         }
4490
4491         /*
4492          * Calculate and update the self-refresh watermark only when one
4493          * display plane is used.
4494          */
4495         I915_WRITE(WM3_LP_ILK, 0);
4496         I915_WRITE(WM2_LP_ILK, 0);
4497         I915_WRITE(WM1_LP_ILK, 0);
4498
4499         if (!single_plane_enabled(enabled))
4500                 return;
4501         enabled = ffs(enabled) - 1;
4502
4503         /* WM1 */
4504         if (!ironlake_compute_srwm(dev, 1, enabled,
4505                                    ILK_READ_WM1_LATENCY() * 500,
4506                                    &ironlake_display_srwm_info,
4507                                    &ironlake_cursor_srwm_info,
4508                                    &fbc_wm, &plane_wm, &cursor_wm))
4509                 return;
4510
4511         I915_WRITE(WM1_LP_ILK,
4512                    WM1_LP_SR_EN |
4513                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4514                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4515                    (plane_wm << WM1_LP_SR_SHIFT) |
4516                    cursor_wm);
4517
4518         /* WM2 */
4519         if (!ironlake_compute_srwm(dev, 2, enabled,
4520                                    ILK_READ_WM2_LATENCY() * 500,
4521                                    &ironlake_display_srwm_info,
4522                                    &ironlake_cursor_srwm_info,
4523                                    &fbc_wm, &plane_wm, &cursor_wm))
4524                 return;
4525
4526         I915_WRITE(WM2_LP_ILK,
4527                    WM2_LP_EN |
4528                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4529                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4530                    (plane_wm << WM1_LP_SR_SHIFT) |
4531                    cursor_wm);
4532
4533         /*
4534          * WM3 is unsupported on ILK, probably because we don't have latency
4535          * data for that power state
4536          */
4537 }
4538
4539 static void sandybridge_update_wm(struct drm_device *dev)
4540 {
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4543         int fbc_wm, plane_wm, cursor_wm;
4544         unsigned int enabled;
4545
4546         enabled = 0;
4547         if (g4x_compute_wm0(dev, 0,
4548                             &sandybridge_display_wm_info, latency,
4549                             &sandybridge_cursor_wm_info, latency,
4550                             &plane_wm, &cursor_wm)) {
4551                 I915_WRITE(WM0_PIPEA_ILK,
4552                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4553                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4554                               " plane %d, " "cursor: %d\n",
4555                               plane_wm, cursor_wm);
4556                 enabled |= 1;
4557         }
4558
4559         if (g4x_compute_wm0(dev, 1,
4560                             &sandybridge_display_wm_info, latency,
4561                             &sandybridge_cursor_wm_info, latency,
4562                             &plane_wm, &cursor_wm)) {
4563                 I915_WRITE(WM0_PIPEB_ILK,
4564                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4565                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4566                               " plane %d, cursor: %d\n",
4567                               plane_wm, cursor_wm);
4568                 enabled |= 2;
4569         }
4570
4571         /* IVB has 3 pipes */
4572         if (IS_IVYBRIDGE(dev) &&
4573             g4x_compute_wm0(dev, 2,
4574                             &sandybridge_display_wm_info, latency,
4575                             &sandybridge_cursor_wm_info, latency,
4576                             &plane_wm, &cursor_wm)) {
4577                 I915_WRITE(WM0_PIPEC_IVB,
4578                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4579                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4580                               " plane %d, cursor: %d\n",
4581                               plane_wm, cursor_wm);
4582                 enabled |= 3;
4583         }
4584
4585         /*
4586          * Calculate and update the self-refresh watermark only when one
4587          * display plane is used.
4588          *
4589          * SNB support 3 levels of watermark.
4590          *
4591          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4592          * and disabled in the descending order
4593          *
4594          */
4595         I915_WRITE(WM3_LP_ILK, 0);
4596         I915_WRITE(WM2_LP_ILK, 0);
4597         I915_WRITE(WM1_LP_ILK, 0);
4598
4599         if (!single_plane_enabled(enabled))
4600                 return;
4601         enabled = ffs(enabled) - 1;
4602
4603         /* WM1 */
4604         if (!ironlake_compute_srwm(dev, 1, enabled,
4605                                    SNB_READ_WM1_LATENCY() * 500,
4606                                    &sandybridge_display_srwm_info,
4607                                    &sandybridge_cursor_srwm_info,
4608                                    &fbc_wm, &plane_wm, &cursor_wm))
4609                 return;
4610
4611         I915_WRITE(WM1_LP_ILK,
4612                    WM1_LP_SR_EN |
4613                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4614                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4615                    (plane_wm << WM1_LP_SR_SHIFT) |
4616                    cursor_wm);
4617
4618         /* WM2 */
4619         if (!ironlake_compute_srwm(dev, 2, enabled,
4620                                    SNB_READ_WM2_LATENCY() * 500,
4621                                    &sandybridge_display_srwm_info,
4622                                    &sandybridge_cursor_srwm_info,
4623                                    &fbc_wm, &plane_wm, &cursor_wm))
4624                 return;
4625
4626         I915_WRITE(WM2_LP_ILK,
4627                    WM2_LP_EN |
4628                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4629                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4630                    (plane_wm << WM1_LP_SR_SHIFT) |
4631                    cursor_wm);
4632
4633         /* WM3 */
4634         if (!ironlake_compute_srwm(dev, 3, enabled,
4635                                    SNB_READ_WM3_LATENCY() * 500,
4636                                    &sandybridge_display_srwm_info,
4637                                    &sandybridge_cursor_srwm_info,
4638                                    &fbc_wm, &plane_wm, &cursor_wm))
4639                 return;
4640
4641         I915_WRITE(WM3_LP_ILK,
4642                    WM3_LP_EN |
4643                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4644                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4645                    (plane_wm << WM1_LP_SR_SHIFT) |
4646                    cursor_wm);
4647 }
4648
4649 /**
4650  * intel_update_watermarks - update FIFO watermark values based on current modes
4651  *
4652  * Calculate watermark values for the various WM regs based on current mode
4653  * and plane configuration.
4654  *
4655  * There are several cases to deal with here:
4656  *   - normal (i.e. non-self-refresh)
4657  *   - self-refresh (SR) mode
4658  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4659  *   - lines are small relative to FIFO size (buffer can hold more than 2
4660  *     lines), so need to account for TLB latency
4661  *
4662  *   The normal calculation is:
4663  *     watermark = dotclock * bytes per pixel * latency
4664  *   where latency is platform & configuration dependent (we assume pessimal
4665  *   values here).
4666  *
4667  *   The SR calculation is:
4668  *     watermark = (trunc(latency/line time)+1) * surface width *
4669  *       bytes per pixel
4670  *   where
4671  *     line time = htotal / dotclock
4672  *     surface width = hdisplay for normal plane and 64 for cursor
4673  *   and latency is assumed to be high, as above.
4674  *
4675  * The final value programmed to the register should always be rounded up,
4676  * and include an extra 2 entries to account for clock crossings.
4677  *
4678  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4679  * to set the non-SR watermarks to 8.
4680  */
4681 static void intel_update_watermarks(struct drm_device *dev)
4682 {
4683         struct drm_i915_private *dev_priv = dev->dev_private;
4684
4685         if (dev_priv->display.update_wm)
4686                 dev_priv->display.update_wm(dev);
4687 }
4688
4689 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4690 {
4691         if (i915_panel_use_ssc >= 0)
4692                 return i915_panel_use_ssc != 0;
4693         return dev_priv->lvds_use_ssc
4694                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4695 }
4696
4697 /**
4698  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4699  * @crtc: CRTC structure
4700  * @mode: requested mode
4701  *
4702  * A pipe may be connected to one or more outputs.  Based on the depth of the
4703  * attached framebuffer, choose a good color depth to use on the pipe.
4704  *
4705  * If possible, match the pipe depth to the fb depth.  In some cases, this
4706  * isn't ideal, because the connected output supports a lesser or restricted
4707  * set of depths.  Resolve that here:
4708  *    LVDS typically supports only 6bpc, so clamp down in that case
4709  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4710  *    Displays may support a restricted set as well, check EDID and clamp as
4711  *      appropriate.
4712  *    DP may want to dither down to 6bpc to fit larger modes
4713  *
4714  * RETURNS:
4715  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4716  * true if they don't match).
4717  */
4718 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4719                                          unsigned int *pipe_bpp,
4720                                          struct drm_display_mode *mode)
4721 {
4722         struct drm_device *dev = crtc->dev;
4723         struct drm_i915_private *dev_priv = dev->dev_private;
4724         struct drm_encoder *encoder;
4725         struct drm_connector *connector;
4726         unsigned int display_bpc = UINT_MAX, bpc;
4727
4728         /* Walk the encoders & connectors on this crtc, get min bpc */
4729         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4730                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4731
4732                 if (encoder->crtc != crtc)
4733                         continue;
4734
4735                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4736                         unsigned int lvds_bpc;
4737
4738                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4739                             LVDS_A3_POWER_UP)
4740                                 lvds_bpc = 8;
4741                         else
4742                                 lvds_bpc = 6;
4743
4744                         if (lvds_bpc < display_bpc) {
4745                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4746                                 display_bpc = lvds_bpc;
4747                         }
4748                         continue;
4749                 }
4750
4751                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4752                         /* Use VBT settings if we have an eDP panel */
4753                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4754
4755                         if (edp_bpc < display_bpc) {
4756                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4757                                 display_bpc = edp_bpc;
4758                         }
4759                         continue;
4760                 }
4761
4762                 /* Not one of the known troublemakers, check the EDID */
4763                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4764                                     head) {
4765                         if (connector->encoder != encoder)
4766                                 continue;
4767
4768                         /* Don't use an invalid EDID bpc value */
4769                         if (connector->display_info.bpc &&
4770                             connector->display_info.bpc < display_bpc) {
4771                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4772                                 display_bpc = connector->display_info.bpc;
4773                         }
4774                 }
4775
4776                 /*
4777                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4778                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4779                  */
4780                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4781                         if (display_bpc > 8 && display_bpc < 12) {
4782                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4783                                 display_bpc = 12;
4784                         } else {
4785                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4786                                 display_bpc = 8;
4787                         }
4788                 }
4789         }
4790
4791         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4792                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4793                 display_bpc = 6;
4794         }
4795
4796         /*
4797          * We could just drive the pipe at the highest bpc all the time and
4798          * enable dithering as needed, but that costs bandwidth.  So choose
4799          * the minimum value that expresses the full color range of the fb but
4800          * also stays within the max display bpc discovered above.
4801          */
4802
4803         switch (crtc->fb->depth) {
4804         case 8:
4805                 bpc = 8; /* since we go through a colormap */
4806                 break;
4807         case 15:
4808         case 16:
4809                 bpc = 6; /* min is 18bpp */
4810                 break;
4811         case 24:
4812                 bpc = 8;
4813                 break;
4814         case 30:
4815                 bpc = 10;
4816                 break;
4817         case 48:
4818                 bpc = 12;
4819                 break;
4820         default:
4821                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4822                 bpc = min((unsigned int)8, display_bpc);
4823                 break;
4824         }
4825
4826         display_bpc = min(display_bpc, bpc);
4827
4828         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4829                       bpc, display_bpc);
4830
4831         *pipe_bpp = display_bpc * 3;
4832
4833         return display_bpc != bpc;
4834 }
4835
4836 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4837                               struct drm_display_mode *mode,
4838                               struct drm_display_mode *adjusted_mode,
4839                               int x, int y,
4840                               struct drm_framebuffer *old_fb)
4841 {
4842         struct drm_device *dev = crtc->dev;
4843         struct drm_i915_private *dev_priv = dev->dev_private;
4844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4845         int pipe = intel_crtc->pipe;
4846         int plane = intel_crtc->plane;
4847         int refclk, num_connectors = 0;
4848         intel_clock_t clock, reduced_clock;
4849         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4850         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4851         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4852         struct drm_mode_config *mode_config = &dev->mode_config;
4853         struct intel_encoder *encoder;
4854         const intel_limit_t *limit;
4855         int ret;
4856         u32 temp;
4857         u32 lvds_sync = 0;
4858
4859         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4860                 if (encoder->base.crtc != crtc)
4861                         continue;
4862
4863                 switch (encoder->type) {
4864                 case INTEL_OUTPUT_LVDS:
4865                         is_lvds = true;
4866                         break;
4867                 case INTEL_OUTPUT_SDVO:
4868                 case INTEL_OUTPUT_HDMI:
4869                         is_sdvo = true;
4870                         if (encoder->needs_tv_clock)
4871                                 is_tv = true;
4872                         break;
4873                 case INTEL_OUTPUT_DVO:
4874                         is_dvo = true;
4875                         break;
4876                 case INTEL_OUTPUT_TVOUT:
4877                         is_tv = true;
4878                         break;
4879                 case INTEL_OUTPUT_ANALOG:
4880                         is_crt = true;
4881                         break;
4882                 case INTEL_OUTPUT_DISPLAYPORT:
4883                         is_dp = true;
4884                         break;
4885                 }
4886
4887                 num_connectors++;
4888         }
4889
4890         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4891                 refclk = dev_priv->lvds_ssc_freq * 1000;
4892                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4893                               refclk / 1000);
4894         } else if (!IS_GEN2(dev)) {
4895                 refclk = 96000;
4896         } else {
4897                 refclk = 48000;
4898         }
4899
4900         /*
4901          * Returns a set of divisors for the desired target clock with the given
4902          * refclk, or FALSE.  The returned values represent the clock equation:
4903          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4904          */
4905         limit = intel_limit(crtc, refclk);
4906         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4907         if (!ok) {
4908                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4909                 return -EINVAL;
4910         }
4911
4912         /* Ensure that the cursor is valid for the new mode before changing... */
4913         intel_crtc_update_cursor(crtc, true);
4914
4915         if (is_lvds && dev_priv->lvds_downclock_avail) {
4916                 has_reduced_clock = limit->find_pll(limit, crtc,
4917                                                     dev_priv->lvds_downclock,
4918                                                     refclk,
4919                                                     &reduced_clock);
4920                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4921                         /*
4922                          * If the different P is found, it means that we can't
4923                          * switch the display clock by using the FP0/FP1.
4924                          * In such case we will disable the LVDS downclock
4925                          * feature.
4926                          */
4927                         DRM_DEBUG_KMS("Different P is found for "
4928                                       "LVDS clock/downclock\n");
4929                         has_reduced_clock = 0;
4930                 }
4931         }
4932         /* SDVO TV has fixed PLL values depend on its clock range,
4933            this mirrors vbios setting. */
4934         if (is_sdvo && is_tv) {
4935                 if (adjusted_mode->clock >= 100000
4936                     && adjusted_mode->clock < 140500) {
4937                         clock.p1 = 2;
4938                         clock.p2 = 10;
4939                         clock.n = 3;
4940                         clock.m1 = 16;
4941                         clock.m2 = 8;
4942                 } else if (adjusted_mode->clock >= 140500
4943                            && adjusted_mode->clock <= 200000) {
4944                         clock.p1 = 1;
4945                         clock.p2 = 10;
4946                         clock.n = 6;
4947                         clock.m1 = 12;
4948                         clock.m2 = 8;
4949                 }
4950         }
4951
4952         if (IS_PINEVIEW(dev)) {
4953                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4954                 if (has_reduced_clock)
4955                         fp2 = (1 << reduced_clock.n) << 16 |
4956                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4957         } else {
4958                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4959                 if (has_reduced_clock)
4960                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4961                                 reduced_clock.m2;
4962         }
4963
4964         dpll = DPLL_VGA_MODE_DIS;
4965
4966         if (!IS_GEN2(dev)) {
4967                 if (is_lvds)
4968                         dpll |= DPLLB_MODE_LVDS;
4969                 else
4970                         dpll |= DPLLB_MODE_DAC_SERIAL;
4971                 if (is_sdvo) {
4972                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4973                         if (pixel_multiplier > 1) {
4974                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4975                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4976                         }
4977                         dpll |= DPLL_DVO_HIGH_SPEED;
4978                 }
4979                 if (is_dp)
4980                         dpll |= DPLL_DVO_HIGH_SPEED;
4981
4982                 /* compute bitmask from p1 value */
4983                 if (IS_PINEVIEW(dev))
4984                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4985                 else {
4986                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4987                         if (IS_G4X(dev) && has_reduced_clock)
4988                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4989                 }
4990                 switch (clock.p2) {
4991                 case 5:
4992                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4993                         break;
4994                 case 7:
4995                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4996                         break;
4997                 case 10:
4998                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4999                         break;
5000                 case 14:
5001                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5002                         break;
5003                 }
5004                 if (INTEL_INFO(dev)->gen >= 4)
5005                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5006         } else {
5007                 if (is_lvds) {
5008                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5009                 } else {
5010                         if (clock.p1 == 2)
5011                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5012                         else
5013                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5014                         if (clock.p2 == 4)
5015                                 dpll |= PLL_P2_DIVIDE_BY_4;
5016                 }
5017         }
5018
5019         if (is_sdvo && is_tv)
5020                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5021         else if (is_tv)
5022                 /* XXX: just matching BIOS for now */
5023                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5024                 dpll |= 3;
5025         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5026                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5027         else
5028                 dpll |= PLL_REF_INPUT_DREFCLK;
5029
5030         /* setup pipeconf */
5031         pipeconf = I915_READ(PIPECONF(pipe));
5032
5033         /* Set up the display plane register */
5034         dspcntr = DISPPLANE_GAMMA_ENABLE;
5035
5036         /* Ironlake's plane is forced to pipe, bit 24 is to
5037            enable color space conversion */
5038         if (pipe == 0)
5039                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5040         else
5041                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5042
5043         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5044                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5045                  * core speed.
5046                  *
5047                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5048                  * pipe == 0 check?
5049                  */
5050                 if (mode->clock >
5051                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5052                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5053                 else
5054                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5055         }
5056
5057         /* default to 8bpc */
5058         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5059         if (is_dp) {
5060                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5061                         pipeconf |= PIPECONF_BPP_6 |
5062                                     PIPECONF_DITHER_EN |
5063                                     PIPECONF_DITHER_TYPE_SP;
5064                 }
5065         }
5066
5067         dpll |= DPLL_VCO_ENABLE;
5068
5069         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5070         drm_mode_debug_printmodeline(mode);
5071
5072         I915_WRITE(FP0(pipe), fp);
5073         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5074
5075         POSTING_READ(DPLL(pipe));
5076         udelay(150);
5077
5078         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5079          * This is an exception to the general rule that mode_set doesn't turn
5080          * things on.
5081          */
5082         if (is_lvds) {
5083                 temp = I915_READ(LVDS);
5084                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5085                 if (pipe == 1) {
5086                         temp |= LVDS_PIPEB_SELECT;
5087                 } else {
5088                         temp &= ~LVDS_PIPEB_SELECT;
5089                 }
5090                 /* set the corresponsding LVDS_BORDER bit */
5091                 temp |= dev_priv->lvds_border_bits;
5092                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5093                  * set the DPLLs for dual-channel mode or not.
5094                  */
5095                 if (clock.p2 == 7)
5096                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5097                 else
5098                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5099
5100                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5101                  * appropriately here, but we need to look more thoroughly into how
5102                  * panels behave in the two modes.
5103                  */
5104                 /* set the dithering flag on LVDS as needed */
5105                 if (INTEL_INFO(dev)->gen >= 4) {
5106                         if (dev_priv->lvds_dither)
5107                                 temp |= LVDS_ENABLE_DITHER;
5108                         else
5109                                 temp &= ~LVDS_ENABLE_DITHER;
5110                 }
5111                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5112                         lvds_sync |= LVDS_HSYNC_POLARITY;
5113                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5114                         lvds_sync |= LVDS_VSYNC_POLARITY;
5115                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5116                     != lvds_sync) {
5117                         char flags[2] = "-+";
5118                         DRM_INFO("Changing LVDS panel from "
5119                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5120                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5121                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5122                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5123                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5124                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5125                         temp |= lvds_sync;
5126                 }
5127                 I915_WRITE(LVDS, temp);
5128         }
5129
5130         if (is_dp) {
5131                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5132         }
5133
5134         I915_WRITE(DPLL(pipe), dpll);
5135
5136         /* Wait for the clocks to stabilize. */
5137         POSTING_READ(DPLL(pipe));
5138         udelay(150);
5139
5140         if (INTEL_INFO(dev)->gen >= 4) {
5141                 temp = 0;
5142                 if (is_sdvo) {
5143                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5144                         if (temp > 1)
5145                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5146                         else
5147                                 temp = 0;
5148                 }
5149                 I915_WRITE(DPLL_MD(pipe), temp);
5150         } else {
5151                 /* The pixel multiplier can only be updated once the
5152                  * DPLL is enabled and the clocks are stable.
5153                  *
5154                  * So write it again.
5155                  */
5156                 I915_WRITE(DPLL(pipe), dpll);
5157         }
5158
5159         intel_crtc->lowfreq_avail = false;
5160         if (is_lvds && has_reduced_clock && i915_powersave) {
5161                 I915_WRITE(FP1(pipe), fp2);
5162                 intel_crtc->lowfreq_avail = true;
5163                 if (HAS_PIPE_CXSR(dev)) {
5164                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5165                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5166                 }
5167         } else {
5168                 I915_WRITE(FP1(pipe), fp);
5169                 if (HAS_PIPE_CXSR(dev)) {
5170                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5171                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5172                 }
5173         }
5174
5175         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5176                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5177                 /* the chip adds 2 halflines automatically */
5178                 adjusted_mode->crtc_vdisplay -= 1;
5179                 adjusted_mode->crtc_vtotal -= 1;
5180                 adjusted_mode->crtc_vblank_start -= 1;
5181                 adjusted_mode->crtc_vblank_end -= 1;
5182                 adjusted_mode->crtc_vsync_end -= 1;
5183                 adjusted_mode->crtc_vsync_start -= 1;
5184         } else
5185                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5186
5187         I915_WRITE(HTOTAL(pipe),
5188                    (adjusted_mode->crtc_hdisplay - 1) |
5189                    ((adjusted_mode->crtc_htotal - 1) << 16));
5190         I915_WRITE(HBLANK(pipe),
5191                    (adjusted_mode->crtc_hblank_start - 1) |
5192                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5193         I915_WRITE(HSYNC(pipe),
5194                    (adjusted_mode->crtc_hsync_start - 1) |
5195                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5196
5197         I915_WRITE(VTOTAL(pipe),
5198                    (adjusted_mode->crtc_vdisplay - 1) |
5199                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5200         I915_WRITE(VBLANK(pipe),
5201                    (adjusted_mode->crtc_vblank_start - 1) |
5202                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5203         I915_WRITE(VSYNC(pipe),
5204                    (adjusted_mode->crtc_vsync_start - 1) |
5205                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5206
5207         /* pipesrc and dspsize control the size that is scaled from,
5208          * which should always be the user's requested size.
5209          */
5210         I915_WRITE(DSPSIZE(plane),
5211                    ((mode->vdisplay - 1) << 16) |
5212                    (mode->hdisplay - 1));
5213         I915_WRITE(DSPPOS(plane), 0);
5214         I915_WRITE(PIPESRC(pipe),
5215                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5216
5217         I915_WRITE(PIPECONF(pipe), pipeconf);
5218         POSTING_READ(PIPECONF(pipe));
5219         intel_enable_pipe(dev_priv, pipe, false);
5220
5221         intel_wait_for_vblank(dev, pipe);
5222
5223         I915_WRITE(DSPCNTR(plane), dspcntr);
5224         POSTING_READ(DSPCNTR(plane));
5225         intel_enable_plane(dev_priv, plane, pipe);
5226
5227         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5228
5229         intel_update_watermarks(dev);
5230
5231         return ret;
5232 }
5233
5234 /*
5235  * Initialize reference clocks when the driver loads
5236  */
5237 void ironlake_init_pch_refclk(struct drm_device *dev)
5238 {
5239         struct drm_i915_private *dev_priv = dev->dev_private;
5240         struct drm_mode_config *mode_config = &dev->mode_config;
5241         struct intel_encoder *encoder;
5242         u32 temp;
5243         bool has_lvds = false;
5244         bool has_cpu_edp = false;
5245         bool has_pch_edp = false;
5246         bool has_panel = false;
5247         bool has_ck505 = false;
5248         bool can_ssc = false;
5249
5250         /* We need to take the global config into account */
5251         list_for_each_entry(encoder, &mode_config->encoder_list,
5252                             base.head) {
5253                 switch (encoder->type) {
5254                 case INTEL_OUTPUT_LVDS:
5255                         has_panel = true;
5256                         has_lvds = true;
5257                         break;
5258                 case INTEL_OUTPUT_EDP:
5259                         has_panel = true;
5260                         if (intel_encoder_is_pch_edp(&encoder->base))
5261                                 has_pch_edp = true;
5262                         else
5263                                 has_cpu_edp = true;
5264                         break;
5265                 }
5266         }
5267
5268         if (HAS_PCH_IBX(dev)) {
5269                 has_ck505 = dev_priv->display_clock_mode;
5270                 can_ssc = has_ck505;
5271         } else {
5272                 has_ck505 = false;
5273                 can_ssc = true;
5274         }
5275
5276         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5277                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5278                       has_ck505);
5279
5280         /* Ironlake: try to setup display ref clock before DPLL
5281          * enabling. This is only under driver's control after
5282          * PCH B stepping, previous chipset stepping should be
5283          * ignoring this setting.
5284          */
5285         temp = I915_READ(PCH_DREF_CONTROL);
5286         /* Always enable nonspread source */
5287         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5288
5289         if (has_ck505)
5290                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5291         else
5292                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5293
5294         if (has_panel) {
5295                 temp &= ~DREF_SSC_SOURCE_MASK;
5296                 temp |= DREF_SSC_SOURCE_ENABLE;
5297
5298                 /* SSC must be turned on before enabling the CPU output  */
5299                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5300                         DRM_DEBUG_KMS("Using SSC on panel\n");
5301                         temp |= DREF_SSC1_ENABLE;
5302                 }
5303
5304                 /* Get SSC going before enabling the outputs */
5305                 I915_WRITE(PCH_DREF_CONTROL, temp);
5306                 POSTING_READ(PCH_DREF_CONTROL);
5307                 udelay(200);
5308
5309                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5310
5311                 /* Enable CPU source on CPU attached eDP */
5312                 if (has_cpu_edp) {
5313                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5314                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5315                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5316                         }
5317                         else
5318                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5319                 } else
5320                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5321
5322                 I915_WRITE(PCH_DREF_CONTROL, temp);
5323                 POSTING_READ(PCH_DREF_CONTROL);
5324                 udelay(200);
5325         } else {
5326                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5327
5328                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5329
5330                 /* Turn off CPU output */
5331                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5332
5333                 I915_WRITE(PCH_DREF_CONTROL, temp);
5334                 POSTING_READ(PCH_DREF_CONTROL);
5335                 udelay(200);
5336
5337                 /* Turn off the SSC source */
5338                 temp &= ~DREF_SSC_SOURCE_MASK;
5339                 temp |= DREF_SSC_SOURCE_DISABLE;
5340
5341                 /* Turn off SSC1 */
5342                 temp &= ~ DREF_SSC1_ENABLE;
5343
5344                 I915_WRITE(PCH_DREF_CONTROL, temp);
5345                 POSTING_READ(PCH_DREF_CONTROL);
5346                 udelay(200);
5347         }
5348 }
5349
5350 static int ironlake_get_refclk(struct drm_crtc *crtc)
5351 {
5352         struct drm_device *dev = crtc->dev;
5353         struct drm_i915_private *dev_priv = dev->dev_private;
5354         struct intel_encoder *encoder;
5355         struct drm_mode_config *mode_config = &dev->mode_config;
5356         struct intel_encoder *edp_encoder = NULL;
5357         int num_connectors = 0;
5358         bool is_lvds = false;
5359
5360         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5361                 if (encoder->base.crtc != crtc)
5362                         continue;
5363
5364                 switch (encoder->type) {
5365                 case INTEL_OUTPUT_LVDS:
5366                         is_lvds = true;
5367                         break;
5368                 case INTEL_OUTPUT_EDP:
5369                         edp_encoder = encoder;
5370                         break;
5371                 }
5372                 num_connectors++;
5373         }
5374
5375         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5376                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5377                               dev_priv->lvds_ssc_freq);
5378                 return dev_priv->lvds_ssc_freq * 1000;
5379         }
5380
5381         return 120000;
5382 }
5383
5384 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5385                                   struct drm_display_mode *mode,
5386                                   struct drm_display_mode *adjusted_mode,
5387                                   int x, int y,
5388                                   struct drm_framebuffer *old_fb)
5389 {
5390         struct drm_device *dev = crtc->dev;
5391         struct drm_i915_private *dev_priv = dev->dev_private;
5392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5393         int pipe = intel_crtc->pipe;
5394         int plane = intel_crtc->plane;
5395         int refclk, num_connectors = 0;
5396         intel_clock_t clock, reduced_clock;
5397         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5398         bool ok, has_reduced_clock = false, is_sdvo = false;
5399         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5400         struct intel_encoder *has_edp_encoder = NULL;
5401         struct drm_mode_config *mode_config = &dev->mode_config;
5402         struct intel_encoder *encoder;
5403         const intel_limit_t *limit;
5404         int ret;
5405         struct fdi_m_n m_n = {0};
5406         u32 temp;
5407         u32 lvds_sync = 0;
5408         int target_clock, pixel_multiplier, lane, link_bw, factor;
5409         unsigned int pipe_bpp;
5410         bool dither;
5411
5412         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5413                 if (encoder->base.crtc != crtc)
5414                         continue;
5415
5416                 switch (encoder->type) {
5417                 case INTEL_OUTPUT_LVDS:
5418                         is_lvds = true;
5419                         break;
5420                 case INTEL_OUTPUT_SDVO:
5421                 case INTEL_OUTPUT_HDMI:
5422                         is_sdvo = true;
5423                         if (encoder->needs_tv_clock)
5424                                 is_tv = true;
5425                         break;
5426                 case INTEL_OUTPUT_TVOUT:
5427                         is_tv = true;
5428                         break;
5429                 case INTEL_OUTPUT_ANALOG:
5430                         is_crt = true;
5431                         break;
5432                 case INTEL_OUTPUT_DISPLAYPORT:
5433                         is_dp = true;
5434                         break;
5435                 case INTEL_OUTPUT_EDP:
5436                         has_edp_encoder = encoder;
5437                         break;
5438                 }
5439
5440                 num_connectors++;
5441         }
5442
5443         refclk = ironlake_get_refclk(crtc);
5444
5445         /*
5446          * Returns a set of divisors for the desired target clock with the given
5447          * refclk, or FALSE.  The returned values represent the clock equation:
5448          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5449          */
5450         limit = intel_limit(crtc, refclk);
5451         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5452         if (!ok) {
5453                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5454                 return -EINVAL;
5455         }
5456
5457         /* Ensure that the cursor is valid for the new mode before changing... */
5458         intel_crtc_update_cursor(crtc, true);
5459
5460         if (is_lvds && dev_priv->lvds_downclock_avail) {
5461                 has_reduced_clock = limit->find_pll(limit, crtc,
5462                                                     dev_priv->lvds_downclock,
5463                                                     refclk,
5464                                                     &reduced_clock);
5465                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5466                         /*
5467                          * If the different P is found, it means that we can't
5468                          * switch the display clock by using the FP0/FP1.
5469                          * In such case we will disable the LVDS downclock
5470                          * feature.
5471                          */
5472                         DRM_DEBUG_KMS("Different P is found for "
5473                                       "LVDS clock/downclock\n");
5474                         has_reduced_clock = 0;
5475                 }
5476         }
5477         /* SDVO TV has fixed PLL values depend on its clock range,
5478            this mirrors vbios setting. */
5479         if (is_sdvo && is_tv) {
5480                 if (adjusted_mode->clock >= 100000
5481                     && adjusted_mode->clock < 140500) {
5482                         clock.p1 = 2;
5483                         clock.p2 = 10;
5484                         clock.n = 3;
5485                         clock.m1 = 16;
5486                         clock.m2 = 8;
5487                 } else if (adjusted_mode->clock >= 140500
5488                            && adjusted_mode->clock <= 200000) {
5489                         clock.p1 = 1;
5490                         clock.p2 = 10;
5491                         clock.n = 6;
5492                         clock.m1 = 12;
5493                         clock.m2 = 8;
5494                 }
5495         }
5496
5497         /* FDI link */
5498         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5499         lane = 0;
5500         /* CPU eDP doesn't require FDI link, so just set DP M/N
5501            according to current link config */
5502         if (has_edp_encoder &&
5503             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5504                 target_clock = mode->clock;
5505                 intel_edp_link_config(has_edp_encoder,
5506                                       &lane, &link_bw);
5507         } else {
5508                 /* [e]DP over FDI requires target mode clock
5509                    instead of link clock */
5510                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5511                         target_clock = mode->clock;
5512                 else
5513                         target_clock = adjusted_mode->clock;
5514
5515                 /* FDI is a binary signal running at ~2.7GHz, encoding
5516                  * each output octet as 10 bits. The actual frequency
5517                  * is stored as a divider into a 100MHz clock, and the
5518                  * mode pixel clock is stored in units of 1KHz.
5519                  * Hence the bw of each lane in terms of the mode signal
5520                  * is:
5521                  */
5522                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5523         }
5524
5525         /* determine panel color depth */
5526         temp = I915_READ(PIPECONF(pipe));
5527         temp &= ~PIPE_BPC_MASK;
5528         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5529         switch (pipe_bpp) {
5530         case 18:
5531                 temp |= PIPE_6BPC;
5532                 break;
5533         case 24:
5534                 temp |= PIPE_8BPC;
5535                 break;
5536         case 30:
5537                 temp |= PIPE_10BPC;
5538                 break;
5539         case 36:
5540                 temp |= PIPE_12BPC;
5541                 break;
5542         default:
5543                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5544                         pipe_bpp);
5545                 temp |= PIPE_8BPC;
5546                 pipe_bpp = 24;
5547                 break;
5548         }
5549
5550         intel_crtc->bpp = pipe_bpp;
5551         I915_WRITE(PIPECONF(pipe), temp);
5552
5553         if (!lane) {
5554                 /*
5555                  * Account for spread spectrum to avoid
5556                  * oversubscribing the link. Max center spread
5557                  * is 2.5%; use 5% for safety's sake.
5558                  */
5559                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5560                 lane = bps / (link_bw * 8) + 1;
5561         }
5562
5563         intel_crtc->fdi_lanes = lane;
5564
5565         if (pixel_multiplier > 1)
5566                 link_bw *= pixel_multiplier;
5567         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5568                              &m_n);
5569
5570         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5571         if (has_reduced_clock)
5572                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5573                         reduced_clock.m2;
5574
5575         /* Enable autotuning of the PLL clock (if permissible) */
5576         factor = 21;
5577         if (is_lvds) {
5578                 if ((intel_panel_use_ssc(dev_priv) &&
5579                      dev_priv->lvds_ssc_freq == 100) ||
5580                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5581                         factor = 25;
5582         } else if (is_sdvo && is_tv)
5583                 factor = 20;
5584
5585         if (clock.m < factor * clock.n)
5586                 fp |= FP_CB_TUNE;
5587
5588         dpll = 0;
5589
5590         if (is_lvds)
5591                 dpll |= DPLLB_MODE_LVDS;
5592         else
5593                 dpll |= DPLLB_MODE_DAC_SERIAL;
5594         if (is_sdvo) {
5595                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5596                 if (pixel_multiplier > 1) {
5597                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5598                 }
5599                 dpll |= DPLL_DVO_HIGH_SPEED;
5600         }
5601         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5602                 dpll |= DPLL_DVO_HIGH_SPEED;
5603
5604         /* compute bitmask from p1 value */
5605         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5606         /* also FPA1 */
5607         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5608
5609         switch (clock.p2) {
5610         case 5:
5611                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5612                 break;
5613         case 7:
5614                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5615                 break;
5616         case 10:
5617                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5618                 break;
5619         case 14:
5620                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5621                 break;
5622         }
5623
5624         if (is_sdvo && is_tv)
5625                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5626         else if (is_tv)
5627                 /* XXX: just matching BIOS for now */
5628                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5629                 dpll |= 3;
5630         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5631                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5632         else
5633                 dpll |= PLL_REF_INPUT_DREFCLK;
5634
5635         /* setup pipeconf */
5636         pipeconf = I915_READ(PIPECONF(pipe));
5637
5638         /* Set up the display plane register */
5639         dspcntr = DISPPLANE_GAMMA_ENABLE;
5640
5641         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5642         drm_mode_debug_printmodeline(mode);
5643
5644         /* PCH eDP needs FDI, but CPU eDP does not */
5645         if (!intel_crtc->no_pll) {
5646                 if (!has_edp_encoder ||
5647                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5648                         I915_WRITE(PCH_FP0(pipe), fp);
5649                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5650
5651                         POSTING_READ(PCH_DPLL(pipe));
5652                         udelay(150);
5653                 }
5654         } else {
5655                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5656                     fp == I915_READ(PCH_FP0(0))) {
5657                         intel_crtc->use_pll_a = true;
5658                         DRM_DEBUG_KMS("using pipe a dpll\n");
5659                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5660                            fp == I915_READ(PCH_FP0(1))) {
5661                         intel_crtc->use_pll_a = false;
5662                         DRM_DEBUG_KMS("using pipe b dpll\n");
5663                 } else {
5664                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5665                         return -EINVAL;
5666                 }
5667         }
5668
5669         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5670          * This is an exception to the general rule that mode_set doesn't turn
5671          * things on.
5672          */
5673         if (is_lvds) {
5674                 temp = I915_READ(PCH_LVDS);
5675                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5676                 if (HAS_PCH_CPT(dev)) {
5677                         temp &= ~PORT_TRANS_SEL_MASK;
5678                         temp |= PORT_TRANS_SEL_CPT(pipe);
5679                 } else {
5680                         if (pipe == 1)
5681                                 temp |= LVDS_PIPEB_SELECT;
5682                         else
5683                                 temp &= ~LVDS_PIPEB_SELECT;
5684                 }
5685
5686                 /* set the corresponsding LVDS_BORDER bit */
5687                 temp |= dev_priv->lvds_border_bits;
5688                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5689                  * set the DPLLs for dual-channel mode or not.
5690                  */
5691                 if (clock.p2 == 7)
5692                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5693                 else
5694                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5695
5696                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5697                  * appropriately here, but we need to look more thoroughly into how
5698                  * panels behave in the two modes.
5699                  */
5700                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5701                         lvds_sync |= LVDS_HSYNC_POLARITY;
5702                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5703                         lvds_sync |= LVDS_VSYNC_POLARITY;
5704                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5705                     != lvds_sync) {
5706                         char flags[2] = "-+";
5707                         DRM_INFO("Changing LVDS panel from "
5708                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5709                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5710                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5711                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5712                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5713                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5714                         temp |= lvds_sync;
5715                 }
5716                 I915_WRITE(PCH_LVDS, temp);
5717         }
5718
5719         pipeconf &= ~PIPECONF_DITHER_EN;
5720         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5721         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5722                 pipeconf |= PIPECONF_DITHER_EN;
5723                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5724         }
5725         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5726                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5727         } else {
5728                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5729                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5730                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5731                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5732                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5733         }
5734
5735         if (!intel_crtc->no_pll &&
5736             (!has_edp_encoder ||
5737              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5738                 I915_WRITE(PCH_DPLL(pipe), dpll);
5739
5740                 /* Wait for the clocks to stabilize. */
5741                 POSTING_READ(PCH_DPLL(pipe));
5742                 udelay(150);
5743
5744                 /* The pixel multiplier can only be updated once the
5745                  * DPLL is enabled and the clocks are stable.
5746                  *
5747                  * So write it again.
5748                  */
5749                 I915_WRITE(PCH_DPLL(pipe), dpll);
5750         }
5751
5752         intel_crtc->lowfreq_avail = false;
5753         if (!intel_crtc->no_pll) {
5754                 if (is_lvds && has_reduced_clock && i915_powersave) {
5755                         I915_WRITE(PCH_FP1(pipe), fp2);
5756                         intel_crtc->lowfreq_avail = true;
5757                         if (HAS_PIPE_CXSR(dev)) {
5758                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5759                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5760                         }
5761                 } else {
5762                         I915_WRITE(PCH_FP1(pipe), fp);
5763                         if (HAS_PIPE_CXSR(dev)) {
5764                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5765                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5766                         }
5767                 }
5768         }
5769
5770         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5771                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5772                 /* the chip adds 2 halflines automatically */
5773                 adjusted_mode->crtc_vdisplay -= 1;
5774                 adjusted_mode->crtc_vtotal -= 1;
5775                 adjusted_mode->crtc_vblank_start -= 1;
5776                 adjusted_mode->crtc_vblank_end -= 1;
5777                 adjusted_mode->crtc_vsync_end -= 1;
5778                 adjusted_mode->crtc_vsync_start -= 1;
5779         } else
5780                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5781
5782         I915_WRITE(HTOTAL(pipe),
5783                    (adjusted_mode->crtc_hdisplay - 1) |
5784                    ((adjusted_mode->crtc_htotal - 1) << 16));
5785         I915_WRITE(HBLANK(pipe),
5786                    (adjusted_mode->crtc_hblank_start - 1) |
5787                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5788         I915_WRITE(HSYNC(pipe),
5789                    (adjusted_mode->crtc_hsync_start - 1) |
5790                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5791
5792         I915_WRITE(VTOTAL(pipe),
5793                    (adjusted_mode->crtc_vdisplay - 1) |
5794                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5795         I915_WRITE(VBLANK(pipe),
5796                    (adjusted_mode->crtc_vblank_start - 1) |
5797                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5798         I915_WRITE(VSYNC(pipe),
5799                    (adjusted_mode->crtc_vsync_start - 1) |
5800                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5801
5802         /* pipesrc controls the size that is scaled from, which should
5803          * always be the user's requested size.
5804          */
5805         I915_WRITE(PIPESRC(pipe),
5806                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5807
5808         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5809         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5810         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5811         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5812
5813         if (has_edp_encoder &&
5814             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5815                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5816         }
5817
5818         I915_WRITE(PIPECONF(pipe), pipeconf);
5819         POSTING_READ(PIPECONF(pipe));
5820
5821         intel_wait_for_vblank(dev, pipe);
5822
5823         if (IS_GEN5(dev)) {
5824                 /* enable address swizzle for tiling buffer */
5825                 temp = I915_READ(DISP_ARB_CTL);
5826                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5827         }
5828
5829         I915_WRITE(DSPCNTR(plane), dspcntr);
5830         POSTING_READ(DSPCNTR(plane));
5831
5832         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5833
5834         intel_update_watermarks(dev);
5835
5836         return ret;
5837 }
5838
5839 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5840                                struct drm_display_mode *mode,
5841                                struct drm_display_mode *adjusted_mode,
5842                                int x, int y,
5843                                struct drm_framebuffer *old_fb)
5844 {
5845         struct drm_device *dev = crtc->dev;
5846         struct drm_i915_private *dev_priv = dev->dev_private;
5847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5848         int pipe = intel_crtc->pipe;
5849         int ret;
5850
5851         drm_vblank_pre_modeset(dev, pipe);
5852
5853         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5854                                               x, y, old_fb);
5855
5856         drm_vblank_post_modeset(dev, pipe);
5857
5858         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5859
5860         return ret;
5861 }
5862
5863 static void g4x_write_eld(struct drm_connector *connector,
5864                           struct drm_crtc *crtc)
5865 {
5866         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5867         uint8_t *eld = connector->eld;
5868         uint32_t eldv;
5869         uint32_t len;
5870         uint32_t i;
5871
5872         i = I915_READ(G4X_AUD_VID_DID);
5873
5874         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5875                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5876         else
5877                 eldv = G4X_ELDV_DEVCTG;
5878
5879         i = I915_READ(G4X_AUD_CNTL_ST);
5880         i &= ~(eldv | G4X_ELD_ADDR);
5881         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5882         I915_WRITE(G4X_AUD_CNTL_ST, i);
5883
5884         if (!eld[0])
5885                 return;
5886
5887         len = min_t(uint8_t, eld[2], len);
5888         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5889         for (i = 0; i < len; i++)
5890                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5891
5892         i = I915_READ(G4X_AUD_CNTL_ST);
5893         i |= eldv;
5894         I915_WRITE(G4X_AUD_CNTL_ST, i);
5895 }
5896
5897 static void ironlake_write_eld(struct drm_connector *connector,
5898                                      struct drm_crtc *crtc)
5899 {
5900         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5901         uint8_t *eld = connector->eld;
5902         uint32_t eldv;
5903         uint32_t i;
5904         int len;
5905         int hdmiw_hdmiedid;
5906         int aud_cntl_st;
5907         int aud_cntrl_st2;
5908
5909         if (HAS_PCH_IBX(connector->dev)) {
5910                 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5911                 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5912                 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5913         } else {
5914                 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5915                 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5916                 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5917         }
5918
5919         i = to_intel_crtc(crtc)->pipe;
5920         hdmiw_hdmiedid += i * 0x100;
5921         aud_cntl_st += i * 0x100;
5922
5923         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5924
5925         i = I915_READ(aud_cntl_st);
5926         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5927         if (!i) {
5928                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5929                 /* operate blindly on all ports */
5930                 eldv = GEN5_ELD_VALIDB;
5931                 eldv |= GEN5_ELD_VALIDB << 4;
5932                 eldv |= GEN5_ELD_VALIDB << 8;
5933         } else {
5934                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5935                 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5936         }
5937
5938         i = I915_READ(aud_cntrl_st2);
5939         i &= ~eldv;
5940         I915_WRITE(aud_cntrl_st2, i);
5941
5942         if (!eld[0])
5943                 return;
5944
5945         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5946                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5947                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5948         }
5949
5950         i = I915_READ(aud_cntl_st);
5951         i &= ~GEN5_ELD_ADDRESS;
5952         I915_WRITE(aud_cntl_st, i);
5953
5954         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5955         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5956         for (i = 0; i < len; i++)
5957                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5958
5959         i = I915_READ(aud_cntrl_st2);
5960         i |= eldv;
5961         I915_WRITE(aud_cntrl_st2, i);
5962 }
5963
5964 void intel_write_eld(struct drm_encoder *encoder,
5965                      struct drm_display_mode *mode)
5966 {
5967         struct drm_crtc *crtc = encoder->crtc;
5968         struct drm_connector *connector;
5969         struct drm_device *dev = encoder->dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971
5972         connector = drm_select_eld(encoder, mode);
5973         if (!connector)
5974                 return;
5975
5976         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5977                          connector->base.id,
5978                          drm_get_connector_name(connector),
5979                          connector->encoder->base.id,
5980                          drm_get_encoder_name(connector->encoder));
5981
5982         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5983
5984         if (dev_priv->display.write_eld)
5985                 dev_priv->display.write_eld(connector, crtc);
5986 }
5987
5988 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5989 void intel_crtc_load_lut(struct drm_crtc *crtc)
5990 {
5991         struct drm_device *dev = crtc->dev;
5992         struct drm_i915_private *dev_priv = dev->dev_private;
5993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994         int palreg = PALETTE(intel_crtc->pipe);
5995         int i;
5996
5997         /* The clocks have to be on to load the palette. */
5998         if (!crtc->enabled || !intel_crtc->active)
5999                 return;
6000
6001         /* use legacy palette for Ironlake */
6002         if (HAS_PCH_SPLIT(dev))
6003                 palreg = LGC_PALETTE(intel_crtc->pipe);
6004
6005         for (i = 0; i < 256; i++) {
6006                 I915_WRITE(palreg + 4 * i,
6007                            (intel_crtc->lut_r[i] << 16) |
6008                            (intel_crtc->lut_g[i] << 8) |
6009                            intel_crtc->lut_b[i]);
6010         }
6011 }
6012
6013 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6014 {
6015         struct drm_device *dev = crtc->dev;
6016         struct drm_i915_private *dev_priv = dev->dev_private;
6017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6018         bool visible = base != 0;
6019         u32 cntl;
6020
6021         if (intel_crtc->cursor_visible == visible)
6022                 return;
6023
6024         cntl = I915_READ(_CURACNTR);
6025         if (visible) {
6026                 /* On these chipsets we can only modify the base whilst
6027                  * the cursor is disabled.
6028                  */
6029                 I915_WRITE(_CURABASE, base);
6030
6031                 cntl &= ~(CURSOR_FORMAT_MASK);
6032                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6033                 cntl |= CURSOR_ENABLE |
6034                         CURSOR_GAMMA_ENABLE |
6035                         CURSOR_FORMAT_ARGB;
6036         } else
6037                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6038         I915_WRITE(_CURACNTR, cntl);
6039
6040         intel_crtc->cursor_visible = visible;
6041 }
6042
6043 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6044 {
6045         struct drm_device *dev = crtc->dev;
6046         struct drm_i915_private *dev_priv = dev->dev_private;
6047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6048         int pipe = intel_crtc->pipe;
6049         bool visible = base != 0;
6050
6051         if (intel_crtc->cursor_visible != visible) {
6052                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6053                 if (base) {
6054                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6055                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6056                         cntl |= pipe << 28; /* Connect to correct pipe */
6057                 } else {
6058                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6059                         cntl |= CURSOR_MODE_DISABLE;
6060                 }
6061                 I915_WRITE(CURCNTR(pipe), cntl);
6062
6063                 intel_crtc->cursor_visible = visible;
6064         }
6065         /* and commit changes on next vblank */
6066         I915_WRITE(CURBASE(pipe), base);
6067 }
6068
6069 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6070 {
6071         struct drm_device *dev = crtc->dev;
6072         struct drm_i915_private *dev_priv = dev->dev_private;
6073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6074         int pipe = intel_crtc->pipe;
6075         bool visible = base != 0;
6076
6077         if (intel_crtc->cursor_visible != visible) {
6078                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6079                 if (base) {
6080                         cntl &= ~CURSOR_MODE;
6081                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6082                 } else {
6083                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6084                         cntl |= CURSOR_MODE_DISABLE;
6085                 }
6086                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6087
6088                 intel_crtc->cursor_visible = visible;
6089         }
6090         /* and commit changes on next vblank */
6091         I915_WRITE(CURBASE_IVB(pipe), base);
6092 }
6093
6094 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6095 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6096                                      bool on)
6097 {
6098         struct drm_device *dev = crtc->dev;
6099         struct drm_i915_private *dev_priv = dev->dev_private;
6100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6101         int pipe = intel_crtc->pipe;
6102         int x = intel_crtc->cursor_x;
6103         int y = intel_crtc->cursor_y;
6104         u32 base, pos;
6105         bool visible;
6106
6107         pos = 0;
6108
6109         if (on && crtc->enabled && crtc->fb) {
6110                 base = intel_crtc->cursor_addr;
6111                 if (x > (int) crtc->fb->width)
6112                         base = 0;
6113
6114                 if (y > (int) crtc->fb->height)
6115                         base = 0;
6116         } else
6117                 base = 0;
6118
6119         if (x < 0) {
6120                 if (x + intel_crtc->cursor_width < 0)
6121                         base = 0;
6122
6123                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6124                 x = -x;
6125         }
6126         pos |= x << CURSOR_X_SHIFT;
6127
6128         if (y < 0) {
6129                 if (y + intel_crtc->cursor_height < 0)
6130                         base = 0;
6131
6132                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6133                 y = -y;
6134         }
6135         pos |= y << CURSOR_Y_SHIFT;
6136
6137         visible = base != 0;
6138         if (!visible && !intel_crtc->cursor_visible)
6139                 return;
6140
6141         if (IS_IVYBRIDGE(dev)) {
6142                 I915_WRITE(CURPOS_IVB(pipe), pos);
6143                 ivb_update_cursor(crtc, base);
6144         } else {
6145                 I915_WRITE(CURPOS(pipe), pos);
6146                 if (IS_845G(dev) || IS_I865G(dev))
6147                         i845_update_cursor(crtc, base);
6148                 else
6149                         i9xx_update_cursor(crtc, base);
6150         }
6151
6152         if (visible)
6153                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6154 }
6155
6156 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6157                                  struct drm_file *file,
6158                                  uint32_t handle,
6159                                  uint32_t width, uint32_t height)
6160 {
6161         struct drm_device *dev = crtc->dev;
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164         struct drm_i915_gem_object *obj;
6165         uint32_t addr;
6166         int ret;
6167
6168         DRM_DEBUG_KMS("\n");
6169
6170         /* if we want to turn off the cursor ignore width and height */
6171         if (!handle) {
6172                 DRM_DEBUG_KMS("cursor off\n");
6173                 addr = 0;
6174                 obj = NULL;
6175                 mutex_lock(&dev->struct_mutex);
6176                 goto finish;
6177         }
6178
6179         /* Currently we only support 64x64 cursors */
6180         if (width != 64 || height != 64) {
6181                 DRM_ERROR("we currently only support 64x64 cursors\n");
6182                 return -EINVAL;
6183         }
6184
6185         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6186         if (&obj->base == NULL)
6187                 return -ENOENT;
6188
6189         if (obj->base.size < width * height * 4) {
6190                 DRM_ERROR("buffer is to small\n");
6191                 ret = -ENOMEM;
6192                 goto fail;
6193         }
6194
6195         /* we only need to pin inside GTT if cursor is non-phy */
6196         mutex_lock(&dev->struct_mutex);
6197         if (!dev_priv->info->cursor_needs_physical) {
6198                 if (obj->tiling_mode) {
6199                         DRM_ERROR("cursor cannot be tiled\n");
6200                         ret = -EINVAL;
6201                         goto fail_locked;
6202                 }
6203
6204                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6205                 if (ret) {
6206                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6207                         goto fail_locked;
6208                 }
6209
6210                 ret = i915_gem_object_put_fence(obj);
6211                 if (ret) {
6212                         DRM_ERROR("failed to release fence for cursor");
6213                         goto fail_unpin;
6214                 }
6215
6216                 addr = obj->gtt_offset;
6217         } else {
6218                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6219                 ret = i915_gem_attach_phys_object(dev, obj,
6220                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6221                                                   align);
6222                 if (ret) {
6223                         DRM_ERROR("failed to attach phys object\n");
6224                         goto fail_locked;
6225                 }
6226                 addr = obj->phys_obj->handle->busaddr;
6227         }
6228
6229         if (IS_GEN2(dev))
6230                 I915_WRITE(CURSIZE, (height << 12) | width);
6231
6232  finish:
6233         if (intel_crtc->cursor_bo) {
6234                 if (dev_priv->info->cursor_needs_physical) {
6235                         if (intel_crtc->cursor_bo != obj)
6236                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6237                 } else
6238                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6239                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6240         }
6241
6242         mutex_unlock(&dev->struct_mutex);
6243
6244         intel_crtc->cursor_addr = addr;
6245         intel_crtc->cursor_bo = obj;
6246         intel_crtc->cursor_width = width;
6247         intel_crtc->cursor_height = height;
6248
6249         intel_crtc_update_cursor(crtc, true);
6250
6251         return 0;
6252 fail_unpin:
6253         i915_gem_object_unpin(obj);
6254 fail_locked:
6255         mutex_unlock(&dev->struct_mutex);
6256 fail:
6257         drm_gem_object_unreference_unlocked(&obj->base);
6258         return ret;
6259 }
6260
6261 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6262 {
6263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264
6265         intel_crtc->cursor_x = x;
6266         intel_crtc->cursor_y = y;
6267
6268         intel_crtc_update_cursor(crtc, true);
6269
6270         return 0;
6271 }
6272
6273 /** Sets the color ramps on behalf of RandR */
6274 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6275                                  u16 blue, int regno)
6276 {
6277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6278
6279         intel_crtc->lut_r[regno] = red >> 8;
6280         intel_crtc->lut_g[regno] = green >> 8;
6281         intel_crtc->lut_b[regno] = blue >> 8;
6282 }
6283
6284 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6285                              u16 *blue, int regno)
6286 {
6287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6288
6289         *red = intel_crtc->lut_r[regno] << 8;
6290         *green = intel_crtc->lut_g[regno] << 8;
6291         *blue = intel_crtc->lut_b[regno] << 8;
6292 }
6293
6294 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6295                                  u16 *blue, uint32_t start, uint32_t size)
6296 {
6297         int end = (start + size > 256) ? 256 : start + size, i;
6298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299
6300         for (i = start; i < end; i++) {
6301                 intel_crtc->lut_r[i] = red[i] >> 8;
6302                 intel_crtc->lut_g[i] = green[i] >> 8;
6303                 intel_crtc->lut_b[i] = blue[i] >> 8;
6304         }
6305
6306         intel_crtc_load_lut(crtc);
6307 }
6308
6309 /**
6310  * Get a pipe with a simple mode set on it for doing load-based monitor
6311  * detection.
6312  *
6313  * It will be up to the load-detect code to adjust the pipe as appropriate for
6314  * its requirements.  The pipe will be connected to no other encoders.
6315  *
6316  * Currently this code will only succeed if there is a pipe with no encoders
6317  * configured for it.  In the future, it could choose to temporarily disable
6318  * some outputs to free up a pipe for its use.
6319  *
6320  * \return crtc, or NULL if no pipes are available.
6321  */
6322
6323 /* VESA 640x480x72Hz mode to set on the pipe */
6324 static struct drm_display_mode load_detect_mode = {
6325         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6326                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6327 };
6328
6329 static struct drm_framebuffer *
6330 intel_framebuffer_create(struct drm_device *dev,
6331                          struct drm_mode_fb_cmd *mode_cmd,
6332                          struct drm_i915_gem_object *obj)
6333 {
6334         struct intel_framebuffer *intel_fb;
6335         int ret;
6336
6337         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6338         if (!intel_fb) {
6339                 drm_gem_object_unreference_unlocked(&obj->base);
6340                 return ERR_PTR(-ENOMEM);
6341         }
6342
6343         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6344         if (ret) {
6345                 drm_gem_object_unreference_unlocked(&obj->base);
6346                 kfree(intel_fb);
6347                 return ERR_PTR(ret);
6348         }
6349
6350         return &intel_fb->base;
6351 }
6352
6353 static u32
6354 intel_framebuffer_pitch_for_width(int width, int bpp)
6355 {
6356         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6357         return ALIGN(pitch, 64);
6358 }
6359
6360 static u32
6361 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6362 {
6363         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6364         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6365 }
6366
6367 static struct drm_framebuffer *
6368 intel_framebuffer_create_for_mode(struct drm_device *dev,
6369                                   struct drm_display_mode *mode,
6370                                   int depth, int bpp)
6371 {
6372         struct drm_i915_gem_object *obj;
6373         struct drm_mode_fb_cmd mode_cmd;
6374
6375         obj = i915_gem_alloc_object(dev,
6376                                     intel_framebuffer_size_for_mode(mode, bpp));
6377         if (obj == NULL)
6378                 return ERR_PTR(-ENOMEM);
6379
6380         mode_cmd.width = mode->hdisplay;
6381         mode_cmd.height = mode->vdisplay;
6382         mode_cmd.depth = depth;
6383         mode_cmd.bpp = bpp;
6384         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6385
6386         return intel_framebuffer_create(dev, &mode_cmd, obj);
6387 }
6388
6389 static struct drm_framebuffer *
6390 mode_fits_in_fbdev(struct drm_device *dev,
6391                    struct drm_display_mode *mode)
6392 {
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         struct drm_i915_gem_object *obj;
6395         struct drm_framebuffer *fb;
6396
6397         if (dev_priv->fbdev == NULL)
6398                 return NULL;
6399
6400         obj = dev_priv->fbdev->ifb.obj;
6401         if (obj == NULL)
6402                 return NULL;
6403
6404         fb = &dev_priv->fbdev->ifb.base;
6405         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6406                                                           fb->bits_per_pixel))
6407                 return NULL;
6408
6409         if (obj->base.size < mode->vdisplay * fb->pitch)
6410                 return NULL;
6411
6412         return fb;
6413 }
6414
6415 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6416                                 struct drm_connector *connector,
6417                                 struct drm_display_mode *mode,
6418                                 struct intel_load_detect_pipe *old)
6419 {
6420         struct intel_crtc *intel_crtc;
6421         struct drm_crtc *possible_crtc;
6422         struct drm_encoder *encoder = &intel_encoder->base;
6423         struct drm_crtc *crtc = NULL;
6424         struct drm_device *dev = encoder->dev;
6425         struct drm_framebuffer *old_fb;
6426         int i = -1;
6427
6428         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6429                       connector->base.id, drm_get_connector_name(connector),
6430                       encoder->base.id, drm_get_encoder_name(encoder));
6431
6432         /*
6433          * Algorithm gets a little messy:
6434          *
6435          *   - if the connector already has an assigned crtc, use it (but make
6436          *     sure it's on first)
6437          *
6438          *   - try to find the first unused crtc that can drive this connector,
6439          *     and use that if we find one
6440          */
6441
6442         /* See if we already have a CRTC for this connector */
6443         if (encoder->crtc) {
6444                 crtc = encoder->crtc;
6445
6446                 intel_crtc = to_intel_crtc(crtc);
6447                 old->dpms_mode = intel_crtc->dpms_mode;
6448                 old->load_detect_temp = false;
6449
6450                 /* Make sure the crtc and connector are running */
6451                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6452                         struct drm_encoder_helper_funcs *encoder_funcs;
6453                         struct drm_crtc_helper_funcs *crtc_funcs;
6454
6455                         crtc_funcs = crtc->helper_private;
6456                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6457
6458                         encoder_funcs = encoder->helper_private;
6459                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6460                 }
6461
6462                 return true;
6463         }
6464
6465         /* Find an unused one (if possible) */
6466         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6467                 i++;
6468                 if (!(encoder->possible_crtcs & (1 << i)))
6469                         continue;
6470                 if (!possible_crtc->enabled) {
6471                         crtc = possible_crtc;
6472                         break;
6473                 }
6474         }
6475
6476         /*
6477          * If we didn't find an unused CRTC, don't use any.
6478          */
6479         if (!crtc) {
6480                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6481                 return false;
6482         }
6483
6484         encoder->crtc = crtc;
6485         connector->encoder = encoder;
6486
6487         intel_crtc = to_intel_crtc(crtc);
6488         old->dpms_mode = intel_crtc->dpms_mode;
6489         old->load_detect_temp = true;
6490         old->release_fb = NULL;
6491
6492         if (!mode)
6493                 mode = &load_detect_mode;
6494
6495         old_fb = crtc->fb;
6496
6497         /* We need a framebuffer large enough to accommodate all accesses
6498          * that the plane may generate whilst we perform load detection.
6499          * We can not rely on the fbcon either being present (we get called
6500          * during its initialisation to detect all boot displays, or it may
6501          * not even exist) or that it is large enough to satisfy the
6502          * requested mode.
6503          */
6504         crtc->fb = mode_fits_in_fbdev(dev, mode);
6505         if (crtc->fb == NULL) {
6506                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6507                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6508                 old->release_fb = crtc->fb;
6509         } else
6510                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6511         if (IS_ERR(crtc->fb)) {
6512                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6513                 crtc->fb = old_fb;
6514                 return false;
6515         }
6516
6517         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6518                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6519                 if (old->release_fb)
6520                         old->release_fb->funcs->destroy(old->release_fb);
6521                 crtc->fb = old_fb;
6522                 return false;
6523         }
6524
6525         /* let the connector get through one full cycle before testing */
6526         intel_wait_for_vblank(dev, intel_crtc->pipe);
6527
6528         return true;
6529 }
6530
6531 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6532                                     struct drm_connector *connector,
6533                                     struct intel_load_detect_pipe *old)
6534 {
6535         struct drm_encoder *encoder = &intel_encoder->base;
6536         struct drm_device *dev = encoder->dev;
6537         struct drm_crtc *crtc = encoder->crtc;
6538         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6539         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6540
6541         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6542                       connector->base.id, drm_get_connector_name(connector),
6543                       encoder->base.id, drm_get_encoder_name(encoder));
6544
6545         if (old->load_detect_temp) {
6546                 connector->encoder = NULL;
6547                 drm_helper_disable_unused_functions(dev);
6548
6549                 if (old->release_fb)
6550                         old->release_fb->funcs->destroy(old->release_fb);
6551
6552                 return;
6553         }
6554
6555         /* Switch crtc and encoder back off if necessary */
6556         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6557                 encoder_funcs->dpms(encoder, old->dpms_mode);
6558                 crtc_funcs->dpms(crtc, old->dpms_mode);
6559         }
6560 }
6561
6562 /* Returns the clock of the currently programmed mode of the given pipe. */
6563 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6564 {
6565         struct drm_i915_private *dev_priv = dev->dev_private;
6566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6567         int pipe = intel_crtc->pipe;
6568         u32 dpll = I915_READ(DPLL(pipe));
6569         u32 fp;
6570         intel_clock_t clock;
6571
6572         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6573                 fp = I915_READ(FP0(pipe));
6574         else
6575                 fp = I915_READ(FP1(pipe));
6576
6577         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6578         if (IS_PINEVIEW(dev)) {
6579                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6580                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6581         } else {
6582                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6583                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6584         }
6585
6586         if (!IS_GEN2(dev)) {
6587                 if (IS_PINEVIEW(dev))
6588                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6589                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6590                 else
6591                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6592                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6593
6594                 switch (dpll & DPLL_MODE_MASK) {
6595                 case DPLLB_MODE_DAC_SERIAL:
6596                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6597                                 5 : 10;
6598                         break;
6599                 case DPLLB_MODE_LVDS:
6600                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6601                                 7 : 14;
6602                         break;
6603                 default:
6604                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6605                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6606                         return 0;
6607                 }
6608
6609                 /* XXX: Handle the 100Mhz refclk */
6610                 intel_clock(dev, 96000, &clock);
6611         } else {
6612                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6613
6614                 if (is_lvds) {
6615                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6616                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6617                         clock.p2 = 14;
6618
6619                         if ((dpll & PLL_REF_INPUT_MASK) ==
6620                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6621                                 /* XXX: might not be 66MHz */
6622                                 intel_clock(dev, 66000, &clock);
6623                         } else
6624                                 intel_clock(dev, 48000, &clock);
6625                 } else {
6626                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6627                                 clock.p1 = 2;
6628                         else {
6629                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6630                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6631                         }
6632                         if (dpll & PLL_P2_DIVIDE_BY_4)
6633                                 clock.p2 = 4;
6634                         else
6635                                 clock.p2 = 2;
6636
6637                         intel_clock(dev, 48000, &clock);
6638                 }
6639         }
6640
6641         /* XXX: It would be nice to validate the clocks, but we can't reuse
6642          * i830PllIsValid() because it relies on the xf86_config connector
6643          * configuration being accurate, which it isn't necessarily.
6644          */
6645
6646         return clock.dot;
6647 }
6648
6649 /** Returns the currently programmed mode of the given pipe. */
6650 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6651                                              struct drm_crtc *crtc)
6652 {
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6655         int pipe = intel_crtc->pipe;
6656         struct drm_display_mode *mode;
6657         int htot = I915_READ(HTOTAL(pipe));
6658         int hsync = I915_READ(HSYNC(pipe));
6659         int vtot = I915_READ(VTOTAL(pipe));
6660         int vsync = I915_READ(VSYNC(pipe));
6661
6662         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6663         if (!mode)
6664                 return NULL;
6665
6666         mode->clock = intel_crtc_clock_get(dev, crtc);
6667         mode->hdisplay = (htot & 0xffff) + 1;
6668         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6669         mode->hsync_start = (hsync & 0xffff) + 1;
6670         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6671         mode->vdisplay = (vtot & 0xffff) + 1;
6672         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6673         mode->vsync_start = (vsync & 0xffff) + 1;
6674         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6675
6676         drm_mode_set_name(mode);
6677         drm_mode_set_crtcinfo(mode, 0);
6678
6679         return mode;
6680 }
6681
6682 #define GPU_IDLE_TIMEOUT 500 /* ms */
6683
6684 /* When this timer fires, we've been idle for awhile */
6685 static void intel_gpu_idle_timer(unsigned long arg)
6686 {
6687         struct drm_device *dev = (struct drm_device *)arg;
6688         drm_i915_private_t *dev_priv = dev->dev_private;
6689
6690         if (!list_empty(&dev_priv->mm.active_list)) {
6691                 /* Still processing requests, so just re-arm the timer. */
6692                 mod_timer(&dev_priv->idle_timer, jiffies +
6693                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6694                 return;
6695         }
6696
6697         dev_priv->busy = false;
6698         queue_work(dev_priv->wq, &dev_priv->idle_work);
6699 }
6700
6701 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6702
6703 static void intel_crtc_idle_timer(unsigned long arg)
6704 {
6705         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6706         struct drm_crtc *crtc = &intel_crtc->base;
6707         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6708         struct intel_framebuffer *intel_fb;
6709
6710         intel_fb = to_intel_framebuffer(crtc->fb);
6711         if (intel_fb && intel_fb->obj->active) {
6712                 /* The framebuffer is still being accessed by the GPU. */
6713                 mod_timer(&intel_crtc->idle_timer, jiffies +
6714                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6715                 return;
6716         }
6717
6718         intel_crtc->busy = false;
6719         queue_work(dev_priv->wq, &dev_priv->idle_work);
6720 }
6721
6722 static void intel_increase_pllclock(struct drm_crtc *crtc)
6723 {
6724         struct drm_device *dev = crtc->dev;
6725         drm_i915_private_t *dev_priv = dev->dev_private;
6726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6727         int pipe = intel_crtc->pipe;
6728         int dpll_reg = DPLL(pipe);
6729         int dpll;
6730
6731         if (HAS_PCH_SPLIT(dev))
6732                 return;
6733
6734         if (!dev_priv->lvds_downclock_avail)
6735                 return;
6736
6737         dpll = I915_READ(dpll_reg);
6738         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6739                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6740
6741                 /* Unlock panel regs */
6742                 I915_WRITE(PP_CONTROL,
6743                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6744
6745                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6746                 I915_WRITE(dpll_reg, dpll);
6747                 intel_wait_for_vblank(dev, pipe);
6748
6749                 dpll = I915_READ(dpll_reg);
6750                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6751                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6752
6753                 /* ...and lock them again */
6754                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6755         }
6756
6757         /* Schedule downclock */
6758         mod_timer(&intel_crtc->idle_timer, jiffies +
6759                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6760 }
6761
6762 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6763 {
6764         struct drm_device *dev = crtc->dev;
6765         drm_i915_private_t *dev_priv = dev->dev_private;
6766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6767         int pipe = intel_crtc->pipe;
6768         int dpll_reg = DPLL(pipe);
6769         int dpll = I915_READ(dpll_reg);
6770
6771         if (HAS_PCH_SPLIT(dev))
6772                 return;
6773
6774         if (!dev_priv->lvds_downclock_avail)
6775                 return;
6776
6777         /*
6778          * Since this is called by a timer, we should never get here in
6779          * the manual case.
6780          */
6781         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6782                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6783
6784                 /* Unlock panel regs */
6785                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6786                            PANEL_UNLOCK_REGS);
6787
6788                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6789                 I915_WRITE(dpll_reg, dpll);
6790                 intel_wait_for_vblank(dev, pipe);
6791                 dpll = I915_READ(dpll_reg);
6792                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6793                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6794
6795                 /* ...and lock them again */
6796                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6797         }
6798
6799 }
6800
6801 /**
6802  * intel_idle_update - adjust clocks for idleness
6803  * @work: work struct
6804  *
6805  * Either the GPU or display (or both) went idle.  Check the busy status
6806  * here and adjust the CRTC and GPU clocks as necessary.
6807  */
6808 static void intel_idle_update(struct work_struct *work)
6809 {
6810         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6811                                                     idle_work);
6812         struct drm_device *dev = dev_priv->dev;
6813         struct drm_crtc *crtc;
6814         struct intel_crtc *intel_crtc;
6815
6816         if (!i915_powersave)
6817                 return;
6818
6819         mutex_lock(&dev->struct_mutex);
6820
6821         i915_update_gfx_val(dev_priv);
6822
6823         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6824                 /* Skip inactive CRTCs */
6825                 if (!crtc->fb)
6826                         continue;
6827
6828                 intel_crtc = to_intel_crtc(crtc);
6829                 if (!intel_crtc->busy)
6830                         intel_decrease_pllclock(crtc);
6831         }
6832
6833
6834         mutex_unlock(&dev->struct_mutex);
6835 }
6836
6837 /**
6838  * intel_mark_busy - mark the GPU and possibly the display busy
6839  * @dev: drm device
6840  * @obj: object we're operating on
6841  *
6842  * Callers can use this function to indicate that the GPU is busy processing
6843  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6844  * buffer), we'll also mark the display as busy, so we know to increase its
6845  * clock frequency.
6846  */
6847 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6848 {
6849         drm_i915_private_t *dev_priv = dev->dev_private;
6850         struct drm_crtc *crtc = NULL;
6851         struct intel_framebuffer *intel_fb;
6852         struct intel_crtc *intel_crtc;
6853
6854         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6855                 return;
6856
6857         if (!dev_priv->busy)
6858                 dev_priv->busy = true;
6859         else
6860                 mod_timer(&dev_priv->idle_timer, jiffies +
6861                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6862
6863         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6864                 if (!crtc->fb)
6865                         continue;
6866
6867                 intel_crtc = to_intel_crtc(crtc);
6868                 intel_fb = to_intel_framebuffer(crtc->fb);
6869                 if (intel_fb->obj == obj) {
6870                         if (!intel_crtc->busy) {
6871                                 /* Non-busy -> busy, upclock */
6872                                 intel_increase_pllclock(crtc);
6873                                 intel_crtc->busy = true;
6874                         } else {
6875                                 /* Busy -> busy, put off timer */
6876                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6877                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6878                         }
6879                 }
6880         }
6881 }
6882
6883 static void intel_crtc_destroy(struct drm_crtc *crtc)
6884 {
6885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6886         struct drm_device *dev = crtc->dev;
6887         struct intel_unpin_work *work;
6888         unsigned long flags;
6889
6890         spin_lock_irqsave(&dev->event_lock, flags);
6891         work = intel_crtc->unpin_work;
6892         intel_crtc->unpin_work = NULL;
6893         spin_unlock_irqrestore(&dev->event_lock, flags);
6894
6895         if (work) {
6896                 cancel_work_sync(&work->work);
6897                 kfree(work);
6898         }
6899
6900         drm_crtc_cleanup(crtc);
6901
6902         kfree(intel_crtc);
6903 }
6904
6905 static void intel_unpin_work_fn(struct work_struct *__work)
6906 {
6907         struct intel_unpin_work *work =
6908                 container_of(__work, struct intel_unpin_work, work);
6909
6910         mutex_lock(&work->dev->struct_mutex);
6911         i915_gem_object_unpin(work->old_fb_obj);
6912         drm_gem_object_unreference(&work->pending_flip_obj->base);
6913         drm_gem_object_unreference(&work->old_fb_obj->base);
6914
6915         intel_update_fbc(work->dev);
6916         mutex_unlock(&work->dev->struct_mutex);
6917         kfree(work);
6918 }
6919
6920 static void do_intel_finish_page_flip(struct drm_device *dev,
6921                                       struct drm_crtc *crtc)
6922 {
6923         drm_i915_private_t *dev_priv = dev->dev_private;
6924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6925         struct intel_unpin_work *work;
6926         struct drm_i915_gem_object *obj;
6927         struct drm_pending_vblank_event *e;
6928         struct timeval tnow, tvbl;
6929         unsigned long flags;
6930
6931         /* Ignore early vblank irqs */
6932         if (intel_crtc == NULL)
6933                 return;
6934
6935         do_gettimeofday(&tnow);
6936
6937         spin_lock_irqsave(&dev->event_lock, flags);
6938         work = intel_crtc->unpin_work;
6939         if (work == NULL || !work->pending) {
6940                 spin_unlock_irqrestore(&dev->event_lock, flags);
6941                 return;
6942         }
6943
6944         intel_crtc->unpin_work = NULL;
6945
6946         if (work->event) {
6947                 e = work->event;
6948                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6949
6950                 /* Called before vblank count and timestamps have
6951                  * been updated for the vblank interval of flip
6952                  * completion? Need to increment vblank count and
6953                  * add one videorefresh duration to returned timestamp
6954                  * to account for this. We assume this happened if we
6955                  * get called over 0.9 frame durations after the last
6956                  * timestamped vblank.
6957                  *
6958                  * This calculation can not be used with vrefresh rates
6959                  * below 5Hz (10Hz to be on the safe side) without
6960                  * promoting to 64 integers.
6961                  */
6962                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6963                     9 * crtc->framedur_ns) {
6964                         e->event.sequence++;
6965                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6966                                              crtc->framedur_ns);
6967                 }
6968
6969                 e->event.tv_sec = tvbl.tv_sec;
6970                 e->event.tv_usec = tvbl.tv_usec;
6971
6972                 list_add_tail(&e->base.link,
6973                               &e->base.file_priv->event_list);
6974                 wake_up_interruptible(&e->base.file_priv->event_wait);
6975         }
6976
6977         drm_vblank_put(dev, intel_crtc->pipe);
6978
6979         spin_unlock_irqrestore(&dev->event_lock, flags);
6980
6981         obj = work->old_fb_obj;
6982
6983         atomic_clear_mask(1 << intel_crtc->plane,
6984                           &obj->pending_flip.counter);
6985         if (atomic_read(&obj->pending_flip) == 0)
6986                 wake_up(&dev_priv->pending_flip_queue);
6987
6988         schedule_work(&work->work);
6989
6990         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6991 }
6992
6993 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6994 {
6995         drm_i915_private_t *dev_priv = dev->dev_private;
6996         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6997
6998         do_intel_finish_page_flip(dev, crtc);
6999 }
7000
7001 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7002 {
7003         drm_i915_private_t *dev_priv = dev->dev_private;
7004         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7005
7006         do_intel_finish_page_flip(dev, crtc);
7007 }
7008
7009 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7010 {
7011         drm_i915_private_t *dev_priv = dev->dev_private;
7012         struct intel_crtc *intel_crtc =
7013                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7014         unsigned long flags;
7015
7016         spin_lock_irqsave(&dev->event_lock, flags);
7017         if (intel_crtc->unpin_work) {
7018                 if ((++intel_crtc->unpin_work->pending) > 1)
7019                         DRM_ERROR("Prepared flip multiple times\n");
7020         } else {
7021                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7022         }
7023         spin_unlock_irqrestore(&dev->event_lock, flags);
7024 }
7025
7026 static int intel_gen2_queue_flip(struct drm_device *dev,
7027                                  struct drm_crtc *crtc,
7028                                  struct drm_framebuffer *fb,
7029                                  struct drm_i915_gem_object *obj)
7030 {
7031         struct drm_i915_private *dev_priv = dev->dev_private;
7032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7033         unsigned long offset;
7034         u32 flip_mask;
7035         int ret;
7036
7037         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7038         if (ret)
7039                 goto err;
7040
7041         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7042         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7043
7044         ret = BEGIN_LP_RING(6);
7045         if (ret)
7046                 goto err_unpin;
7047
7048         /* Can't queue multiple flips, so wait for the previous
7049          * one to finish before executing the next.
7050          */
7051         if (intel_crtc->plane)
7052                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7053         else
7054                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7055         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7056         OUT_RING(MI_NOOP);
7057         OUT_RING(MI_DISPLAY_FLIP |
7058                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7059         OUT_RING(fb->pitch);
7060         OUT_RING(obj->gtt_offset + offset);
7061         OUT_RING(MI_NOOP);
7062         ADVANCE_LP_RING();
7063         return 0;
7064
7065 err_unpin:
7066         i915_gem_object_unpin(obj);
7067 err:
7068         return ret;
7069 }
7070
7071 static int intel_gen3_queue_flip(struct drm_device *dev,
7072                                  struct drm_crtc *crtc,
7073                                  struct drm_framebuffer *fb,
7074                                  struct drm_i915_gem_object *obj)
7075 {
7076         struct drm_i915_private *dev_priv = dev->dev_private;
7077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7078         unsigned long offset;
7079         u32 flip_mask;
7080         int ret;
7081
7082         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7083         if (ret)
7084                 goto err;
7085
7086         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7087         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7088
7089         ret = BEGIN_LP_RING(6);
7090         if (ret)
7091                 goto err_unpin;
7092
7093         if (intel_crtc->plane)
7094                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7095         else
7096                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7097         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7098         OUT_RING(MI_NOOP);
7099         OUT_RING(MI_DISPLAY_FLIP_I915 |
7100                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7101         OUT_RING(fb->pitch);
7102         OUT_RING(obj->gtt_offset + offset);
7103         OUT_RING(MI_NOOP);
7104
7105         ADVANCE_LP_RING();
7106         return 0;
7107
7108 err_unpin:
7109         i915_gem_object_unpin(obj);
7110 err:
7111         return ret;
7112 }
7113
7114 static int intel_gen4_queue_flip(struct drm_device *dev,
7115                                  struct drm_crtc *crtc,
7116                                  struct drm_framebuffer *fb,
7117                                  struct drm_i915_gem_object *obj)
7118 {
7119         struct drm_i915_private *dev_priv = dev->dev_private;
7120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7121         uint32_t pf, pipesrc;
7122         int ret;
7123
7124         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7125         if (ret)
7126                 goto err;
7127
7128         ret = BEGIN_LP_RING(4);
7129         if (ret)
7130                 goto err_unpin;
7131
7132         /* i965+ uses the linear or tiled offsets from the
7133          * Display Registers (which do not change across a page-flip)
7134          * so we need only reprogram the base address.
7135          */
7136         OUT_RING(MI_DISPLAY_FLIP |
7137                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7138         OUT_RING(fb->pitch);
7139         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7140
7141         /* XXX Enabling the panel-fitter across page-flip is so far
7142          * untested on non-native modes, so ignore it for now.
7143          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7144          */
7145         pf = 0;
7146         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7147         OUT_RING(pf | pipesrc);
7148         ADVANCE_LP_RING();
7149         return 0;
7150
7151 err_unpin:
7152         i915_gem_object_unpin(obj);
7153 err:
7154         return ret;
7155 }
7156
7157 static int intel_gen6_queue_flip(struct drm_device *dev,
7158                                  struct drm_crtc *crtc,
7159                                  struct drm_framebuffer *fb,
7160                                  struct drm_i915_gem_object *obj)
7161 {
7162         struct drm_i915_private *dev_priv = dev->dev_private;
7163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7164         uint32_t pf, pipesrc;
7165         int ret;
7166
7167         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7168         if (ret)
7169                 goto err;
7170
7171         ret = BEGIN_LP_RING(4);
7172         if (ret)
7173                 goto err_unpin;
7174
7175         OUT_RING(MI_DISPLAY_FLIP |
7176                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7177         OUT_RING(fb->pitch | obj->tiling_mode);
7178         OUT_RING(obj->gtt_offset);
7179
7180         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7181         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7182         OUT_RING(pf | pipesrc);
7183         ADVANCE_LP_RING();
7184         return 0;
7185
7186 err_unpin:
7187         i915_gem_object_unpin(obj);
7188 err:
7189         return ret;
7190 }
7191
7192 /*
7193  * On gen7 we currently use the blit ring because (in early silicon at least)
7194  * the render ring doesn't give us interrpts for page flip completion, which
7195  * means clients will hang after the first flip is queued.  Fortunately the
7196  * blit ring generates interrupts properly, so use it instead.
7197  */
7198 static int intel_gen7_queue_flip(struct drm_device *dev,
7199                                  struct drm_crtc *crtc,
7200                                  struct drm_framebuffer *fb,
7201                                  struct drm_i915_gem_object *obj)
7202 {
7203         struct drm_i915_private *dev_priv = dev->dev_private;
7204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7205         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7206         uint32_t plane_bit = 0;
7207         int ret;
7208
7209         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7210         if (ret)
7211                 goto err;
7212
7213         switch(intel_crtc->plane) {
7214         case PLANE_A:
7215                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7216                 break;
7217         case PLANE_B:
7218                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7219                 break;
7220         case PLANE_C:
7221                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7222                 break;
7223         default:
7224                 WARN_ONCE(1, "unknown plane in flip command\n");
7225                 ret = -ENODEV;
7226                 goto err;
7227         }
7228
7229         ret = intel_ring_begin(ring, 4);
7230         if (ret)
7231                 goto err_unpin;
7232
7233         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7234         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7235         intel_ring_emit(ring, (obj->gtt_offset));
7236         intel_ring_emit(ring, (MI_NOOP));
7237         intel_ring_advance(ring);
7238         return 0;
7239
7240 err_unpin:
7241         i915_gem_object_unpin(obj);
7242 err:
7243         return ret;
7244 }
7245
7246 static int intel_default_queue_flip(struct drm_device *dev,
7247                                     struct drm_crtc *crtc,
7248                                     struct drm_framebuffer *fb,
7249                                     struct drm_i915_gem_object *obj)
7250 {
7251         return -ENODEV;
7252 }
7253
7254 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7255                                 struct drm_framebuffer *fb,
7256                                 struct drm_pending_vblank_event *event)
7257 {
7258         struct drm_device *dev = crtc->dev;
7259         struct drm_i915_private *dev_priv = dev->dev_private;
7260         struct intel_framebuffer *intel_fb;
7261         struct drm_i915_gem_object *obj;
7262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7263         struct intel_unpin_work *work;
7264         unsigned long flags;
7265         int ret;
7266
7267         work = kzalloc(sizeof *work, GFP_KERNEL);
7268         if (work == NULL)
7269                 return -ENOMEM;
7270
7271         work->event = event;
7272         work->dev = crtc->dev;
7273         intel_fb = to_intel_framebuffer(crtc->fb);
7274         work->old_fb_obj = intel_fb->obj;
7275         INIT_WORK(&work->work, intel_unpin_work_fn);
7276
7277         ret = drm_vblank_get(dev, intel_crtc->pipe);
7278         if (ret)
7279                 goto free_work;
7280
7281         /* We borrow the event spin lock for protecting unpin_work */
7282         spin_lock_irqsave(&dev->event_lock, flags);
7283         if (intel_crtc->unpin_work) {
7284                 spin_unlock_irqrestore(&dev->event_lock, flags);
7285                 kfree(work);
7286                 drm_vblank_put(dev, intel_crtc->pipe);
7287
7288                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7289                 return -EBUSY;
7290         }
7291         intel_crtc->unpin_work = work;
7292         spin_unlock_irqrestore(&dev->event_lock, flags);
7293
7294         intel_fb = to_intel_framebuffer(fb);
7295         obj = intel_fb->obj;
7296
7297         mutex_lock(&dev->struct_mutex);
7298
7299         /* Reference the objects for the scheduled work. */
7300         drm_gem_object_reference(&work->old_fb_obj->base);
7301         drm_gem_object_reference(&obj->base);
7302
7303         crtc->fb = fb;
7304
7305         work->pending_flip_obj = obj;
7306
7307         work->enable_stall_check = true;
7308
7309         /* Block clients from rendering to the new back buffer until
7310          * the flip occurs and the object is no longer visible.
7311          */
7312         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7313
7314         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7315         if (ret)
7316                 goto cleanup_pending;
7317
7318         intel_disable_fbc(dev);
7319         mutex_unlock(&dev->struct_mutex);
7320
7321         trace_i915_flip_request(intel_crtc->plane, obj);
7322
7323         return 0;
7324
7325 cleanup_pending:
7326         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7327         drm_gem_object_unreference(&work->old_fb_obj->base);
7328         drm_gem_object_unreference(&obj->base);
7329         mutex_unlock(&dev->struct_mutex);
7330
7331         spin_lock_irqsave(&dev->event_lock, flags);
7332         intel_crtc->unpin_work = NULL;
7333         spin_unlock_irqrestore(&dev->event_lock, flags);
7334
7335         drm_vblank_put(dev, intel_crtc->pipe);
7336 free_work:
7337         kfree(work);
7338
7339         return ret;
7340 }
7341
7342 static void intel_sanitize_modesetting(struct drm_device *dev,
7343                                        int pipe, int plane)
7344 {
7345         struct drm_i915_private *dev_priv = dev->dev_private;
7346         u32 reg, val;
7347         int i;
7348
7349         /* Clear any frame start delays used for debugging left by the BIOS */
7350         for_each_pipe(i) {
7351                 reg = PIPECONF(i);
7352                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7353         }
7354
7355         if (HAS_PCH_SPLIT(dev))
7356                 return;
7357
7358         /* Who knows what state these registers were left in by the BIOS or
7359          * grub?
7360          *
7361          * If we leave the registers in a conflicting state (e.g. with the
7362          * display plane reading from the other pipe than the one we intend
7363          * to use) then when we attempt to teardown the active mode, we will
7364          * not disable the pipes and planes in the correct order -- leaving
7365          * a plane reading from a disabled pipe and possibly leading to
7366          * undefined behaviour.
7367          */
7368
7369         reg = DSPCNTR(plane);
7370         val = I915_READ(reg);
7371
7372         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7373                 return;
7374         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7375                 return;
7376
7377         /* This display plane is active and attached to the other CPU pipe. */
7378         pipe = !pipe;
7379
7380         /* Disable the plane and wait for it to stop reading from the pipe. */
7381         intel_disable_plane(dev_priv, plane, pipe);
7382         intel_disable_pipe(dev_priv, pipe);
7383 }
7384
7385 static void intel_crtc_reset(struct drm_crtc *crtc)
7386 {
7387         struct drm_device *dev = crtc->dev;
7388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7389
7390         /* Reset flags back to the 'unknown' status so that they
7391          * will be correctly set on the initial modeset.
7392          */
7393         intel_crtc->dpms_mode = -1;
7394
7395         /* We need to fix up any BIOS configuration that conflicts with
7396          * our expectations.
7397          */
7398         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7399 }
7400
7401 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7402         .dpms = intel_crtc_dpms,
7403         .mode_fixup = intel_crtc_mode_fixup,
7404         .mode_set = intel_crtc_mode_set,
7405         .mode_set_base = intel_pipe_set_base,
7406         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7407         .load_lut = intel_crtc_load_lut,
7408         .disable = intel_crtc_disable,
7409 };
7410
7411 static const struct drm_crtc_funcs intel_crtc_funcs = {
7412         .reset = intel_crtc_reset,
7413         .cursor_set = intel_crtc_cursor_set,
7414         .cursor_move = intel_crtc_cursor_move,
7415         .gamma_set = intel_crtc_gamma_set,
7416         .set_config = drm_crtc_helper_set_config,
7417         .destroy = intel_crtc_destroy,
7418         .page_flip = intel_crtc_page_flip,
7419 };
7420
7421 static void intel_crtc_init(struct drm_device *dev, int pipe)
7422 {
7423         drm_i915_private_t *dev_priv = dev->dev_private;
7424         struct intel_crtc *intel_crtc;
7425         int i;
7426
7427         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7428         if (intel_crtc == NULL)
7429                 return;
7430
7431         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7432
7433         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7434         for (i = 0; i < 256; i++) {
7435                 intel_crtc->lut_r[i] = i;
7436                 intel_crtc->lut_g[i] = i;
7437                 intel_crtc->lut_b[i] = i;
7438         }
7439
7440         /* Swap pipes & planes for FBC on pre-965 */
7441         intel_crtc->pipe = pipe;
7442         intel_crtc->plane = pipe;
7443         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7444                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7445                 intel_crtc->plane = !pipe;
7446         }
7447
7448         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7449                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7450         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7451         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7452
7453         intel_crtc_reset(&intel_crtc->base);
7454         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7455         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7456
7457         if (HAS_PCH_SPLIT(dev)) {
7458                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7459                         intel_crtc->no_pll = true;
7460                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7461                 intel_helper_funcs.commit = ironlake_crtc_commit;
7462         } else {
7463                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7464                 intel_helper_funcs.commit = i9xx_crtc_commit;
7465         }
7466
7467         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7468
7469         intel_crtc->busy = false;
7470
7471         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7472                     (unsigned long)intel_crtc);
7473 }
7474
7475 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7476                                 struct drm_file *file)
7477 {
7478         drm_i915_private_t *dev_priv = dev->dev_private;
7479         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7480         struct drm_mode_object *drmmode_obj;
7481         struct intel_crtc *crtc;
7482
7483         if (!dev_priv) {
7484                 DRM_ERROR("called with no initialization\n");
7485                 return -EINVAL;
7486         }
7487
7488         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7489                         DRM_MODE_OBJECT_CRTC);
7490
7491         if (!drmmode_obj) {
7492                 DRM_ERROR("no such CRTC id\n");
7493                 return -EINVAL;
7494         }
7495
7496         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7497         pipe_from_crtc_id->pipe = crtc->pipe;
7498
7499         return 0;
7500 }
7501
7502 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7503 {
7504         struct intel_encoder *encoder;
7505         int index_mask = 0;
7506         int entry = 0;
7507
7508         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7509                 if (type_mask & encoder->clone_mask)
7510                         index_mask |= (1 << entry);
7511                 entry++;
7512         }
7513
7514         return index_mask;
7515 }
7516
7517 static bool has_edp_a(struct drm_device *dev)
7518 {
7519         struct drm_i915_private *dev_priv = dev->dev_private;
7520
7521         if (!IS_MOBILE(dev))
7522                 return false;
7523
7524         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7525                 return false;
7526
7527         if (IS_GEN5(dev) &&
7528             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7529                 return false;
7530
7531         return true;
7532 }
7533
7534 static void intel_setup_outputs(struct drm_device *dev)
7535 {
7536         struct drm_i915_private *dev_priv = dev->dev_private;
7537         struct intel_encoder *encoder;
7538         bool dpd_is_edp = false;
7539         bool has_lvds = false;
7540
7541         if (IS_MOBILE(dev) && !IS_I830(dev))
7542                 has_lvds = intel_lvds_init(dev);
7543         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7544                 /* disable the panel fitter on everything but LVDS */
7545                 I915_WRITE(PFIT_CONTROL, 0);
7546         }
7547
7548         if (HAS_PCH_SPLIT(dev)) {
7549                 dpd_is_edp = intel_dpd_is_edp(dev);
7550
7551                 if (has_edp_a(dev))
7552                         intel_dp_init(dev, DP_A);
7553
7554                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7555                         intel_dp_init(dev, PCH_DP_D);
7556         }
7557
7558         intel_crt_init(dev);
7559
7560         if (HAS_PCH_SPLIT(dev)) {
7561                 int found;
7562
7563                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7564                         /* PCH SDVOB multiplex with HDMIB */
7565                         found = intel_sdvo_init(dev, PCH_SDVOB);
7566                         if (!found)
7567                                 intel_hdmi_init(dev, HDMIB);
7568                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7569                                 intel_dp_init(dev, PCH_DP_B);
7570                 }
7571
7572                 if (I915_READ(HDMIC) & PORT_DETECTED)
7573                         intel_hdmi_init(dev, HDMIC);
7574
7575                 if (I915_READ(HDMID) & PORT_DETECTED)
7576                         intel_hdmi_init(dev, HDMID);
7577
7578                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7579                         intel_dp_init(dev, PCH_DP_C);
7580
7581                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7582                         intel_dp_init(dev, PCH_DP_D);
7583
7584         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7585                 bool found = false;
7586
7587                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7588                         DRM_DEBUG_KMS("probing SDVOB\n");
7589                         found = intel_sdvo_init(dev, SDVOB);
7590                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7591                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7592                                 intel_hdmi_init(dev, SDVOB);
7593                         }
7594
7595                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7596                                 DRM_DEBUG_KMS("probing DP_B\n");
7597                                 intel_dp_init(dev, DP_B);
7598                         }
7599                 }
7600
7601                 /* Before G4X SDVOC doesn't have its own detect register */
7602
7603                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7604                         DRM_DEBUG_KMS("probing SDVOC\n");
7605                         found = intel_sdvo_init(dev, SDVOC);
7606                 }
7607
7608                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7609
7610                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7611                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7612                                 intel_hdmi_init(dev, SDVOC);
7613                         }
7614                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7615                                 DRM_DEBUG_KMS("probing DP_C\n");
7616                                 intel_dp_init(dev, DP_C);
7617                         }
7618                 }
7619
7620                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7621                     (I915_READ(DP_D) & DP_DETECTED)) {
7622                         DRM_DEBUG_KMS("probing DP_D\n");
7623                         intel_dp_init(dev, DP_D);
7624                 }
7625         } else if (IS_GEN2(dev))
7626                 intel_dvo_init(dev);
7627
7628         if (SUPPORTS_TV(dev))
7629                 intel_tv_init(dev);
7630
7631         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7632                 encoder->base.possible_crtcs = encoder->crtc_mask;
7633                 encoder->base.possible_clones =
7634                         intel_encoder_clones(dev, encoder->clone_mask);
7635         }
7636
7637         /* disable all the possible outputs/crtcs before entering KMS mode */
7638         drm_helper_disable_unused_functions(dev);
7639
7640         if (HAS_PCH_SPLIT(dev))
7641                 ironlake_init_pch_refclk(dev);
7642 }
7643
7644 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7645 {
7646         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7647
7648         drm_framebuffer_cleanup(fb);
7649         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7650
7651         kfree(intel_fb);
7652 }
7653
7654 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7655                                                 struct drm_file *file,
7656                                                 unsigned int *handle)
7657 {
7658         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7659         struct drm_i915_gem_object *obj = intel_fb->obj;
7660
7661         return drm_gem_handle_create(file, &obj->base, handle);
7662 }
7663
7664 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7665         .destroy = intel_user_framebuffer_destroy,
7666         .create_handle = intel_user_framebuffer_create_handle,
7667 };
7668
7669 int intel_framebuffer_init(struct drm_device *dev,
7670                            struct intel_framebuffer *intel_fb,
7671                            struct drm_mode_fb_cmd *mode_cmd,
7672                            struct drm_i915_gem_object *obj)
7673 {
7674         int ret;
7675
7676         if (obj->tiling_mode == I915_TILING_Y)
7677                 return -EINVAL;
7678
7679         if (mode_cmd->pitch & 63)
7680                 return -EINVAL;
7681
7682         switch (mode_cmd->bpp) {
7683         case 8:
7684         case 16:
7685                 /* Only pre-ILK can handle 5:5:5 */
7686                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7687                         return -EINVAL;
7688                 break;
7689
7690         case 24:
7691         case 32:
7692                 break;
7693         default:
7694                 return -EINVAL;
7695         }
7696
7697         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7698         if (ret) {
7699                 DRM_ERROR("framebuffer init failed %d\n", ret);
7700                 return ret;
7701         }
7702
7703         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7704         intel_fb->obj = obj;
7705         return 0;
7706 }
7707
7708 static struct drm_framebuffer *
7709 intel_user_framebuffer_create(struct drm_device *dev,
7710                               struct drm_file *filp,
7711                               struct drm_mode_fb_cmd *mode_cmd)
7712 {
7713         struct drm_i915_gem_object *obj;
7714
7715         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7716         if (&obj->base == NULL)
7717                 return ERR_PTR(-ENOENT);
7718
7719         return intel_framebuffer_create(dev, mode_cmd, obj);
7720 }
7721
7722 static const struct drm_mode_config_funcs intel_mode_funcs = {
7723         .fb_create = intel_user_framebuffer_create,
7724         .output_poll_changed = intel_fb_output_poll_changed,
7725 };
7726
7727 static struct drm_i915_gem_object *
7728 intel_alloc_context_page(struct drm_device *dev)
7729 {
7730         struct drm_i915_gem_object *ctx;
7731         int ret;
7732
7733         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7734
7735         ctx = i915_gem_alloc_object(dev, 4096);
7736         if (!ctx) {
7737                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7738                 return NULL;
7739         }
7740
7741         ret = i915_gem_object_pin(ctx, 4096, true);
7742         if (ret) {
7743                 DRM_ERROR("failed to pin power context: %d\n", ret);
7744                 goto err_unref;
7745         }
7746
7747         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7748         if (ret) {
7749                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7750                 goto err_unpin;
7751         }
7752
7753         return ctx;
7754
7755 err_unpin:
7756         i915_gem_object_unpin(ctx);
7757 err_unref:
7758         drm_gem_object_unreference(&ctx->base);
7759         mutex_unlock(&dev->struct_mutex);
7760         return NULL;
7761 }
7762
7763 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7764 {
7765         struct drm_i915_private *dev_priv = dev->dev_private;
7766         u16 rgvswctl;
7767
7768         rgvswctl = I915_READ16(MEMSWCTL);
7769         if (rgvswctl & MEMCTL_CMD_STS) {
7770                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7771                 return false; /* still busy with another command */
7772         }
7773
7774         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7775                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7776         I915_WRITE16(MEMSWCTL, rgvswctl);
7777         POSTING_READ16(MEMSWCTL);
7778
7779         rgvswctl |= MEMCTL_CMD_STS;
7780         I915_WRITE16(MEMSWCTL, rgvswctl);
7781
7782         return true;
7783 }
7784
7785 void ironlake_enable_drps(struct drm_device *dev)
7786 {
7787         struct drm_i915_private *dev_priv = dev->dev_private;
7788         u32 rgvmodectl = I915_READ(MEMMODECTL);
7789         u8 fmax, fmin, fstart, vstart;
7790
7791         /* Enable temp reporting */
7792         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7793         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7794
7795         /* 100ms RC evaluation intervals */
7796         I915_WRITE(RCUPEI, 100000);
7797         I915_WRITE(RCDNEI, 100000);
7798
7799         /* Set max/min thresholds to 90ms and 80ms respectively */
7800         I915_WRITE(RCBMAXAVG, 90000);
7801         I915_WRITE(RCBMINAVG, 80000);
7802
7803         I915_WRITE(MEMIHYST, 1);
7804
7805         /* Set up min, max, and cur for interrupt handling */
7806         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7807         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7808         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7809                 MEMMODE_FSTART_SHIFT;
7810
7811         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7812                 PXVFREQ_PX_SHIFT;
7813
7814         dev_priv->fmax = fmax; /* IPS callback will increase this */
7815         dev_priv->fstart = fstart;
7816
7817         dev_priv->max_delay = fstart;
7818         dev_priv->min_delay = fmin;
7819         dev_priv->cur_delay = fstart;
7820
7821         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7822                          fmax, fmin, fstart);
7823
7824         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7825
7826         /*
7827          * Interrupts will be enabled in ironlake_irq_postinstall
7828          */
7829
7830         I915_WRITE(VIDSTART, vstart);
7831         POSTING_READ(VIDSTART);
7832
7833         rgvmodectl |= MEMMODE_SWMODE_EN;
7834         I915_WRITE(MEMMODECTL, rgvmodectl);
7835
7836         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7837                 DRM_ERROR("stuck trying to change perf mode\n");
7838         msleep(1);
7839
7840         ironlake_set_drps(dev, fstart);
7841
7842         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7843                 I915_READ(0x112e0);
7844         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7845         dev_priv->last_count2 = I915_READ(0x112f4);
7846         getrawmonotonic(&dev_priv->last_time2);
7847 }
7848
7849 void ironlake_disable_drps(struct drm_device *dev)
7850 {
7851         struct drm_i915_private *dev_priv = dev->dev_private;
7852         u16 rgvswctl = I915_READ16(MEMSWCTL);
7853
7854         /* Ack interrupts, disable EFC interrupt */
7855         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7856         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7857         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7858         I915_WRITE(DEIIR, DE_PCU_EVENT);
7859         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7860
7861         /* Go back to the starting frequency */
7862         ironlake_set_drps(dev, dev_priv->fstart);
7863         msleep(1);
7864         rgvswctl |= MEMCTL_CMD_STS;
7865         I915_WRITE(MEMSWCTL, rgvswctl);
7866         msleep(1);
7867
7868 }
7869
7870 void gen6_set_rps(struct drm_device *dev, u8 val)
7871 {
7872         struct drm_i915_private *dev_priv = dev->dev_private;
7873         u32 swreq;
7874
7875         swreq = (val & 0x3ff) << 25;
7876         I915_WRITE(GEN6_RPNSWREQ, swreq);
7877 }
7878
7879 void gen6_disable_rps(struct drm_device *dev)
7880 {
7881         struct drm_i915_private *dev_priv = dev->dev_private;
7882
7883         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7884         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7885         I915_WRITE(GEN6_PMIER, 0);
7886         /* Complete PM interrupt masking here doesn't race with the rps work
7887          * item again unmasking PM interrupts because that is using a different
7888          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7889          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7890
7891         spin_lock_irq(&dev_priv->rps_lock);
7892         dev_priv->pm_iir = 0;
7893         spin_unlock_irq(&dev_priv->rps_lock);
7894
7895         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7896 }
7897
7898 static unsigned long intel_pxfreq(u32 vidfreq)
7899 {
7900         unsigned long freq;
7901         int div = (vidfreq & 0x3f0000) >> 16;
7902         int post = (vidfreq & 0x3000) >> 12;
7903         int pre = (vidfreq & 0x7);
7904
7905         if (!pre)
7906                 return 0;
7907
7908         freq = ((div * 133333) / ((1<<post) * pre));
7909
7910         return freq;
7911 }
7912
7913 void intel_init_emon(struct drm_device *dev)
7914 {
7915         struct drm_i915_private *dev_priv = dev->dev_private;
7916         u32 lcfuse;
7917         u8 pxw[16];
7918         int i;
7919
7920         /* Disable to program */
7921         I915_WRITE(ECR, 0);
7922         POSTING_READ(ECR);
7923
7924         /* Program energy weights for various events */
7925         I915_WRITE(SDEW, 0x15040d00);
7926         I915_WRITE(CSIEW0, 0x007f0000);
7927         I915_WRITE(CSIEW1, 0x1e220004);
7928         I915_WRITE(CSIEW2, 0x04000004);
7929
7930         for (i = 0; i < 5; i++)
7931                 I915_WRITE(PEW + (i * 4), 0);
7932         for (i = 0; i < 3; i++)
7933                 I915_WRITE(DEW + (i * 4), 0);
7934
7935         /* Program P-state weights to account for frequency power adjustment */
7936         for (i = 0; i < 16; i++) {
7937                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7938                 unsigned long freq = intel_pxfreq(pxvidfreq);
7939                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7940                         PXVFREQ_PX_SHIFT;
7941                 unsigned long val;
7942
7943                 val = vid * vid;
7944                 val *= (freq / 1000);
7945                 val *= 255;
7946                 val /= (127*127*900);
7947                 if (val > 0xff)
7948                         DRM_ERROR("bad pxval: %ld\n", val);
7949                 pxw[i] = val;
7950         }
7951         /* Render standby states get 0 weight */
7952         pxw[14] = 0;
7953         pxw[15] = 0;
7954
7955         for (i = 0; i < 4; i++) {
7956                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7957                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7958                 I915_WRITE(PXW + (i * 4), val);
7959         }
7960
7961         /* Adjust magic regs to magic values (more experimental results) */
7962         I915_WRITE(OGW0, 0);
7963         I915_WRITE(OGW1, 0);
7964         I915_WRITE(EG0, 0x00007f00);
7965         I915_WRITE(EG1, 0x0000000e);
7966         I915_WRITE(EG2, 0x000e0000);
7967         I915_WRITE(EG3, 0x68000300);
7968         I915_WRITE(EG4, 0x42000000);
7969         I915_WRITE(EG5, 0x00140031);
7970         I915_WRITE(EG6, 0);
7971         I915_WRITE(EG7, 0);
7972
7973         for (i = 0; i < 8; i++)
7974                 I915_WRITE(PXWL + (i * 4), 0);
7975
7976         /* Enable PMON + select events */
7977         I915_WRITE(ECR, 0x80000019);
7978
7979         lcfuse = I915_READ(LCFUSE02);
7980
7981         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7982 }
7983
7984 static bool intel_enable_rc6(struct drm_device *dev)
7985 {
7986         /*
7987          * Respect the kernel parameter if it is set
7988          */
7989         if (i915_enable_rc6 >= 0)
7990                 return i915_enable_rc6;
7991
7992         /*
7993          * Disable RC6 on Ironlake
7994          */
7995         if (INTEL_INFO(dev)->gen == 5)
7996                 return 0;
7997
7998         /*
7999          * Disable rc6 on Sandybridge
8000          */
8001         if (INTEL_INFO(dev)->gen == 6) {
8002                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8003                 return 0;
8004         }
8005         DRM_DEBUG_DRIVER("RC6 enabled\n");
8006         return 1;
8007 }
8008
8009 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8010 {
8011         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8012         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8013         u32 pcu_mbox, rc6_mask = 0;
8014         int cur_freq, min_freq, max_freq;
8015         int i;
8016
8017         /* Here begins a magic sequence of register writes to enable
8018          * auto-downclocking.
8019          *
8020          * Perhaps there might be some value in exposing these to
8021          * userspace...
8022          */
8023         I915_WRITE(GEN6_RC_STATE, 0);
8024         mutex_lock(&dev_priv->dev->struct_mutex);
8025         gen6_gt_force_wake_get(dev_priv);
8026
8027         /* disable the counters and set deterministic thresholds */
8028         I915_WRITE(GEN6_RC_CONTROL, 0);
8029
8030         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8031         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8032         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8033         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8034         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8035
8036         for (i = 0; i < I915_NUM_RINGS; i++)
8037                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8038
8039         I915_WRITE(GEN6_RC_SLEEP, 0);
8040         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8041         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8042         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8043         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8044
8045         if (intel_enable_rc6(dev_priv->dev))
8046                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8047                         ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
8048
8049         I915_WRITE(GEN6_RC_CONTROL,
8050                    rc6_mask |
8051                    GEN6_RC_CTL_EI_MODE(1) |
8052                    GEN6_RC_CTL_HW_ENABLE);
8053
8054         I915_WRITE(GEN6_RPNSWREQ,
8055                    GEN6_FREQUENCY(10) |
8056                    GEN6_OFFSET(0) |
8057                    GEN6_AGGRESSIVE_TURBO);
8058         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8059                    GEN6_FREQUENCY(12));
8060
8061         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8062         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8063                    18 << 24 |
8064                    6 << 16);
8065         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8066         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8067         I915_WRITE(GEN6_RP_UP_EI, 100000);
8068         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8069         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8070         I915_WRITE(GEN6_RP_CONTROL,
8071                    GEN6_RP_MEDIA_TURBO |
8072                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
8073                    GEN6_RP_MEDIA_IS_GFX |
8074                    GEN6_RP_ENABLE |
8075                    GEN6_RP_UP_BUSY_AVG |
8076                    GEN6_RP_DOWN_IDLE_CONT);
8077
8078         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8079                      500))
8080                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8081
8082         I915_WRITE(GEN6_PCODE_DATA, 0);
8083         I915_WRITE(GEN6_PCODE_MAILBOX,
8084                    GEN6_PCODE_READY |
8085                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8086         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8087                      500))
8088                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8089
8090         min_freq = (rp_state_cap & 0xff0000) >> 16;
8091         max_freq = rp_state_cap & 0xff;
8092         cur_freq = (gt_perf_status & 0xff00) >> 8;
8093
8094         /* Check for overclock support */
8095         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8096                      500))
8097                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8098         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8099         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8100         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8101                      500))
8102                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8103         if (pcu_mbox & (1<<31)) { /* OC supported */
8104                 max_freq = pcu_mbox & 0xff;
8105                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8106         }
8107
8108         /* In units of 100MHz */
8109         dev_priv->max_delay = max_freq;
8110         dev_priv->min_delay = min_freq;
8111         dev_priv->cur_delay = cur_freq;
8112
8113         /* requires MSI enabled */
8114         I915_WRITE(GEN6_PMIER,
8115                    GEN6_PM_MBOX_EVENT |
8116                    GEN6_PM_THERMAL_EVENT |
8117                    GEN6_PM_RP_DOWN_TIMEOUT |
8118                    GEN6_PM_RP_UP_THRESHOLD |
8119                    GEN6_PM_RP_DOWN_THRESHOLD |
8120                    GEN6_PM_RP_UP_EI_EXPIRED |
8121                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8122         spin_lock_irq(&dev_priv->rps_lock);
8123         WARN_ON(dev_priv->pm_iir != 0);
8124         I915_WRITE(GEN6_PMIMR, 0);
8125         spin_unlock_irq(&dev_priv->rps_lock);
8126         /* enable all PM interrupts */
8127         I915_WRITE(GEN6_PMINTRMSK, 0);
8128
8129         gen6_gt_force_wake_put(dev_priv);
8130         mutex_unlock(&dev_priv->dev->struct_mutex);
8131 }
8132
8133 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8134 {
8135         int min_freq = 15;
8136         int gpu_freq, ia_freq, max_ia_freq;
8137         int scaling_factor = 180;
8138
8139         max_ia_freq = cpufreq_quick_get_max(0);
8140         /*
8141          * Default to measured freq if none found, PCU will ensure we don't go
8142          * over
8143          */
8144         if (!max_ia_freq)
8145                 max_ia_freq = tsc_khz;
8146
8147         /* Convert from kHz to MHz */
8148         max_ia_freq /= 1000;
8149
8150         mutex_lock(&dev_priv->dev->struct_mutex);
8151
8152         /*
8153          * For each potential GPU frequency, load a ring frequency we'd like
8154          * to use for memory access.  We do this by specifying the IA frequency
8155          * the PCU should use as a reference to determine the ring frequency.
8156          */
8157         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8158              gpu_freq--) {
8159                 int diff = dev_priv->max_delay - gpu_freq;
8160
8161                 /*
8162                  * For GPU frequencies less than 750MHz, just use the lowest
8163                  * ring freq.
8164                  */
8165                 if (gpu_freq < min_freq)
8166                         ia_freq = 800;
8167                 else
8168                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8169                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8170
8171                 I915_WRITE(GEN6_PCODE_DATA,
8172                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8173                            gpu_freq);
8174                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8175                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8176                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8177                               GEN6_PCODE_READY) == 0, 10)) {
8178                         DRM_ERROR("pcode write of freq table timed out\n");
8179                         continue;
8180                 }
8181         }
8182
8183         mutex_unlock(&dev_priv->dev->struct_mutex);
8184 }
8185
8186 static void ironlake_init_clock_gating(struct drm_device *dev)
8187 {
8188         struct drm_i915_private *dev_priv = dev->dev_private;
8189         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8190
8191         /* Required for FBC */
8192         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8193                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8194                 DPFDUNIT_CLOCK_GATE_DISABLE;
8195         /* Required for CxSR */
8196         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8197
8198         I915_WRITE(PCH_3DCGDIS0,
8199                    MARIUNIT_CLOCK_GATE_DISABLE |
8200                    SVSMUNIT_CLOCK_GATE_DISABLE);
8201         I915_WRITE(PCH_3DCGDIS1,
8202                    VFMUNIT_CLOCK_GATE_DISABLE);
8203
8204         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8205
8206         /*
8207          * According to the spec the following bits should be set in
8208          * order to enable memory self-refresh
8209          * The bit 22/21 of 0x42004
8210          * The bit 5 of 0x42020
8211          * The bit 15 of 0x45000
8212          */
8213         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8214                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8215                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8216         I915_WRITE(ILK_DSPCLK_GATE,
8217                    (I915_READ(ILK_DSPCLK_GATE) |
8218                     ILK_DPARB_CLK_GATE));
8219         I915_WRITE(DISP_ARB_CTL,
8220                    (I915_READ(DISP_ARB_CTL) |
8221                     DISP_FBC_WM_DIS));
8222         I915_WRITE(WM3_LP_ILK, 0);
8223         I915_WRITE(WM2_LP_ILK, 0);
8224         I915_WRITE(WM1_LP_ILK, 0);
8225
8226         /*
8227          * Based on the document from hardware guys the following bits
8228          * should be set unconditionally in order to enable FBC.
8229          * The bit 22 of 0x42000
8230          * The bit 22 of 0x42004
8231          * The bit 7,8,9 of 0x42020.
8232          */
8233         if (IS_IRONLAKE_M(dev)) {
8234                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8235                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8236                            ILK_FBCQ_DIS);
8237                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8238                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8239                            ILK_DPARB_GATE);
8240                 I915_WRITE(ILK_DSPCLK_GATE,
8241                            I915_READ(ILK_DSPCLK_GATE) |
8242                            ILK_DPFC_DIS1 |
8243                            ILK_DPFC_DIS2 |
8244                            ILK_CLK_FBC);
8245         }
8246
8247         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8248                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8249                    ILK_ELPIN_409_SELECT);
8250         I915_WRITE(_3D_CHICKEN2,
8251                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8252                    _3D_CHICKEN2_WM_READ_PIPELINED);
8253 }
8254
8255 static void gen6_init_clock_gating(struct drm_device *dev)
8256 {
8257         struct drm_i915_private *dev_priv = dev->dev_private;
8258         int pipe;
8259         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8260
8261         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8262
8263         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8264                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8265                    ILK_ELPIN_409_SELECT);
8266
8267         I915_WRITE(WM3_LP_ILK, 0);
8268         I915_WRITE(WM2_LP_ILK, 0);
8269         I915_WRITE(WM1_LP_ILK, 0);
8270
8271         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8272          * gating disable must be set.  Failure to set it results in
8273          * flickering pixels due to Z write ordering failures after
8274          * some amount of runtime in the Mesa "fire" demo, and Unigine
8275          * Sanctuary and Tropics, and apparently anything else with
8276          * alpha test or pixel discard.
8277          *
8278          * According to the spec, bit 11 (RCCUNIT) must also be set,
8279          * but we didn't debug actual testcases to find it out.
8280          */
8281         I915_WRITE(GEN6_UCGCTL2,
8282                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8283                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8284
8285         /*
8286          * According to the spec the following bits should be
8287          * set in order to enable memory self-refresh and fbc:
8288          * The bit21 and bit22 of 0x42000
8289          * The bit21 and bit22 of 0x42004
8290          * The bit5 and bit7 of 0x42020
8291          * The bit14 of 0x70180
8292          * The bit14 of 0x71180
8293          */
8294         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8295                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8296                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8297         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8298                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8299                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8300         I915_WRITE(ILK_DSPCLK_GATE,
8301                    I915_READ(ILK_DSPCLK_GATE) |
8302                    ILK_DPARB_CLK_GATE  |
8303                    ILK_DPFD_CLK_GATE);
8304
8305         for_each_pipe(pipe) {
8306                 I915_WRITE(DSPCNTR(pipe),
8307                            I915_READ(DSPCNTR(pipe)) |
8308                            DISPPLANE_TRICKLE_FEED_DISABLE);
8309                 intel_flush_display_plane(dev_priv, pipe);
8310         }
8311 }
8312
8313 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8314 {
8315         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8316
8317         reg &= ~GEN7_FF_SCHED_MASK;
8318         reg |= GEN7_FF_TS_SCHED_HW;
8319         reg |= GEN7_FF_VS_SCHED_HW;
8320         reg |= GEN7_FF_DS_SCHED_HW;
8321
8322         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8323 }
8324
8325 static void ivybridge_init_clock_gating(struct drm_device *dev)
8326 {
8327         struct drm_i915_private *dev_priv = dev->dev_private;
8328         int pipe;
8329         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8330
8331         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8332
8333         I915_WRITE(WM3_LP_ILK, 0);
8334         I915_WRITE(WM2_LP_ILK, 0);
8335         I915_WRITE(WM1_LP_ILK, 0);
8336
8337         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8338          * This implements the WaDisableRCZUnitClockGating workaround.
8339          */
8340         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8341
8342         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8343
8344         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8345         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8346                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8347
8348         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8349         I915_WRITE(GEN7_L3CNTLREG1,
8350                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8351         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8352                         GEN7_WA_L3_CHICKEN_MODE);
8353
8354         /* This is required by WaCatErrorRejectionIssue */
8355         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8356                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8357                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8358
8359         for_each_pipe(pipe) {
8360                 I915_WRITE(DSPCNTR(pipe),
8361                            I915_READ(DSPCNTR(pipe)) |
8362                            DISPPLANE_TRICKLE_FEED_DISABLE);
8363                 intel_flush_display_plane(dev_priv, pipe);
8364         }
8365
8366         gen7_setup_fixed_func_scheduler(dev_priv);
8367 }
8368
8369 static void g4x_init_clock_gating(struct drm_device *dev)
8370 {
8371         struct drm_i915_private *dev_priv = dev->dev_private;
8372         uint32_t dspclk_gate;
8373
8374         I915_WRITE(RENCLK_GATE_D1, 0);
8375         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8376                    GS_UNIT_CLOCK_GATE_DISABLE |
8377                    CL_UNIT_CLOCK_GATE_DISABLE);
8378         I915_WRITE(RAMCLK_GATE_D, 0);
8379         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8380                 OVRUNIT_CLOCK_GATE_DISABLE |
8381                 OVCUNIT_CLOCK_GATE_DISABLE;
8382         if (IS_GM45(dev))
8383                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8384         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8385 }
8386
8387 static void crestline_init_clock_gating(struct drm_device *dev)
8388 {
8389         struct drm_i915_private *dev_priv = dev->dev_private;
8390
8391         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8392         I915_WRITE(RENCLK_GATE_D2, 0);
8393         I915_WRITE(DSPCLK_GATE_D, 0);
8394         I915_WRITE(RAMCLK_GATE_D, 0);
8395         I915_WRITE16(DEUC, 0);
8396 }
8397
8398 static void broadwater_init_clock_gating(struct drm_device *dev)
8399 {
8400         struct drm_i915_private *dev_priv = dev->dev_private;
8401
8402         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8403                    I965_RCC_CLOCK_GATE_DISABLE |
8404                    I965_RCPB_CLOCK_GATE_DISABLE |
8405                    I965_ISC_CLOCK_GATE_DISABLE |
8406                    I965_FBC_CLOCK_GATE_DISABLE);
8407         I915_WRITE(RENCLK_GATE_D2, 0);
8408 }
8409
8410 static void gen3_init_clock_gating(struct drm_device *dev)
8411 {
8412         struct drm_i915_private *dev_priv = dev->dev_private;
8413         u32 dstate = I915_READ(D_STATE);
8414
8415         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8416                 DSTATE_DOT_CLOCK_GATING;
8417         I915_WRITE(D_STATE, dstate);
8418 }
8419
8420 static void i85x_init_clock_gating(struct drm_device *dev)
8421 {
8422         struct drm_i915_private *dev_priv = dev->dev_private;
8423
8424         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8425 }
8426
8427 static void i830_init_clock_gating(struct drm_device *dev)
8428 {
8429         struct drm_i915_private *dev_priv = dev->dev_private;
8430
8431         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8432 }
8433
8434 static void ibx_init_clock_gating(struct drm_device *dev)
8435 {
8436         struct drm_i915_private *dev_priv = dev->dev_private;
8437
8438         /*
8439          * On Ibex Peak and Cougar Point, we need to disable clock
8440          * gating for the panel power sequencer or it will fail to
8441          * start up when no ports are active.
8442          */
8443         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8444 }
8445
8446 static void cpt_init_clock_gating(struct drm_device *dev)
8447 {
8448         struct drm_i915_private *dev_priv = dev->dev_private;
8449         int pipe;
8450
8451         /*
8452          * On Ibex Peak and Cougar Point, we need to disable clock
8453          * gating for the panel power sequencer or it will fail to
8454          * start up when no ports are active.
8455          */
8456         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8457         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8458                    DPLS_EDP_PPS_FIX_DIS);
8459         /* Without this, mode sets may fail silently on FDI */
8460         for_each_pipe(pipe)
8461                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8462 }
8463
8464 static void ironlake_teardown_rc6(struct drm_device *dev)
8465 {
8466         struct drm_i915_private *dev_priv = dev->dev_private;
8467
8468         if (dev_priv->renderctx) {
8469                 i915_gem_object_unpin(dev_priv->renderctx);
8470                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8471                 dev_priv->renderctx = NULL;
8472         }
8473
8474         if (dev_priv->pwrctx) {
8475                 i915_gem_object_unpin(dev_priv->pwrctx);
8476                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8477                 dev_priv->pwrctx = NULL;
8478         }
8479 }
8480
8481 static void ironlake_disable_rc6(struct drm_device *dev)
8482 {
8483         struct drm_i915_private *dev_priv = dev->dev_private;
8484
8485         if (I915_READ(PWRCTXA)) {
8486                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8487                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8488                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8489                          50);
8490
8491                 I915_WRITE(PWRCTXA, 0);
8492                 POSTING_READ(PWRCTXA);
8493
8494                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8495                 POSTING_READ(RSTDBYCTL);
8496         }
8497
8498         ironlake_teardown_rc6(dev);
8499 }
8500
8501 static int ironlake_setup_rc6(struct drm_device *dev)
8502 {
8503         struct drm_i915_private *dev_priv = dev->dev_private;
8504
8505         if (dev_priv->renderctx == NULL)
8506                 dev_priv->renderctx = intel_alloc_context_page(dev);
8507         if (!dev_priv->renderctx)
8508                 return -ENOMEM;
8509
8510         if (dev_priv->pwrctx == NULL)
8511                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8512         if (!dev_priv->pwrctx) {
8513                 ironlake_teardown_rc6(dev);
8514                 return -ENOMEM;
8515         }
8516
8517         return 0;
8518 }
8519
8520 void ironlake_enable_rc6(struct drm_device *dev)
8521 {
8522         struct drm_i915_private *dev_priv = dev->dev_private;
8523         int ret;
8524
8525         /* rc6 disabled by default due to repeated reports of hanging during
8526          * boot and resume.
8527          */
8528         if (!intel_enable_rc6(dev))
8529                 return;
8530
8531         mutex_lock(&dev->struct_mutex);
8532         ret = ironlake_setup_rc6(dev);
8533         if (ret) {
8534                 mutex_unlock(&dev->struct_mutex);
8535                 return;
8536         }
8537
8538         /*
8539          * GPU can automatically power down the render unit if given a page
8540          * to save state.
8541          */
8542         ret = BEGIN_LP_RING(6);
8543         if (ret) {
8544                 ironlake_teardown_rc6(dev);
8545                 mutex_unlock(&dev->struct_mutex);
8546                 return;
8547         }
8548
8549         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8550         OUT_RING(MI_SET_CONTEXT);
8551         OUT_RING(dev_priv->renderctx->gtt_offset |
8552                  MI_MM_SPACE_GTT |
8553                  MI_SAVE_EXT_STATE_EN |
8554                  MI_RESTORE_EXT_STATE_EN |
8555                  MI_RESTORE_INHIBIT);
8556         OUT_RING(MI_SUSPEND_FLUSH);
8557         OUT_RING(MI_NOOP);
8558         OUT_RING(MI_FLUSH);
8559         ADVANCE_LP_RING();
8560
8561         /*
8562          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8563          * does an implicit flush, combined with MI_FLUSH above, it should be
8564          * safe to assume that renderctx is valid
8565          */
8566         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8567         if (ret) {
8568                 DRM_ERROR("failed to enable ironlake power power savings\n");
8569                 ironlake_teardown_rc6(dev);
8570                 mutex_unlock(&dev->struct_mutex);
8571                 return;
8572         }
8573
8574         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8575         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8576         mutex_unlock(&dev->struct_mutex);
8577 }
8578
8579 void intel_init_clock_gating(struct drm_device *dev)
8580 {
8581         struct drm_i915_private *dev_priv = dev->dev_private;
8582
8583         dev_priv->display.init_clock_gating(dev);
8584
8585         if (dev_priv->display.init_pch_clock_gating)
8586                 dev_priv->display.init_pch_clock_gating(dev);
8587 }
8588
8589 /* Set up chip specific display functions */
8590 static void intel_init_display(struct drm_device *dev)
8591 {
8592         struct drm_i915_private *dev_priv = dev->dev_private;
8593
8594         /* We always want a DPMS function */
8595         if (HAS_PCH_SPLIT(dev)) {
8596                 dev_priv->display.dpms = ironlake_crtc_dpms;
8597                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8598                 dev_priv->display.update_plane = ironlake_update_plane;
8599         } else {
8600                 dev_priv->display.dpms = i9xx_crtc_dpms;
8601                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8602                 dev_priv->display.update_plane = i9xx_update_plane;
8603         }
8604
8605         if (I915_HAS_FBC(dev)) {
8606                 if (HAS_PCH_SPLIT(dev)) {
8607                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8608                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8609                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8610                 } else if (IS_GM45(dev)) {
8611                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8612                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8613                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8614                 } else if (IS_CRESTLINE(dev)) {
8615                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8616                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8617                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8618                 }
8619                 /* 855GM needs testing */
8620         }
8621
8622         /* Returns the core display clock speed */
8623         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8624                 dev_priv->display.get_display_clock_speed =
8625                         i945_get_display_clock_speed;
8626         else if (IS_I915G(dev))
8627                 dev_priv->display.get_display_clock_speed =
8628                         i915_get_display_clock_speed;
8629         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8630                 dev_priv->display.get_display_clock_speed =
8631                         i9xx_misc_get_display_clock_speed;
8632         else if (IS_I915GM(dev))
8633                 dev_priv->display.get_display_clock_speed =
8634                         i915gm_get_display_clock_speed;
8635         else if (IS_I865G(dev))
8636                 dev_priv->display.get_display_clock_speed =
8637                         i865_get_display_clock_speed;
8638         else if (IS_I85X(dev))
8639                 dev_priv->display.get_display_clock_speed =
8640                         i855_get_display_clock_speed;
8641         else /* 852, 830 */
8642                 dev_priv->display.get_display_clock_speed =
8643                         i830_get_display_clock_speed;
8644
8645         /* For FIFO watermark updates */
8646         if (HAS_PCH_SPLIT(dev)) {
8647                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8648                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8649
8650                 /* IVB configs may use multi-threaded forcewake */
8651                 if (IS_IVYBRIDGE(dev)) {
8652                         u32     ecobus;
8653
8654                         mutex_lock(&dev->struct_mutex);
8655                         __gen6_gt_force_wake_mt_get(dev_priv);
8656                         ecobus = I915_READ(ECOBUS);
8657                         __gen6_gt_force_wake_mt_put(dev_priv);
8658                         mutex_unlock(&dev->struct_mutex);
8659
8660                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8661                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8662                                 dev_priv->display.force_wake_get =
8663                                         __gen6_gt_force_wake_mt_get;
8664                                 dev_priv->display.force_wake_put =
8665                                         __gen6_gt_force_wake_mt_put;
8666                         }
8667                 }
8668
8669                 if (HAS_PCH_IBX(dev))
8670                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8671                 else if (HAS_PCH_CPT(dev))
8672                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8673
8674                 if (IS_GEN5(dev)) {
8675                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8676                                 dev_priv->display.update_wm = ironlake_update_wm;
8677                         else {
8678                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8679                                               "Disable CxSR\n");
8680                                 dev_priv->display.update_wm = NULL;
8681                         }
8682                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8683                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8684                         dev_priv->display.write_eld = ironlake_write_eld;
8685                 } else if (IS_GEN6(dev)) {
8686                         if (SNB_READ_WM0_LATENCY()) {
8687                                 dev_priv->display.update_wm = sandybridge_update_wm;
8688                         } else {
8689                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8690                                               "Disable CxSR\n");
8691                                 dev_priv->display.update_wm = NULL;
8692                         }
8693                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8694                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8695                         dev_priv->display.write_eld = ironlake_write_eld;
8696                 } else if (IS_IVYBRIDGE(dev)) {
8697                         /* FIXME: detect B0+ stepping and use auto training */
8698                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8699                         if (SNB_READ_WM0_LATENCY()) {
8700                                 dev_priv->display.update_wm = sandybridge_update_wm;
8701                         } else {
8702                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8703                                               "Disable CxSR\n");
8704                                 dev_priv->display.update_wm = NULL;
8705                         }
8706                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8707                         dev_priv->display.write_eld = ironlake_write_eld;
8708                 } else
8709                         dev_priv->display.update_wm = NULL;
8710         } else if (IS_PINEVIEW(dev)) {
8711                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8712                                             dev_priv->is_ddr3,
8713                                             dev_priv->fsb_freq,
8714                                             dev_priv->mem_freq)) {
8715                         DRM_INFO("failed to find known CxSR latency "
8716                                  "(found ddr%s fsb freq %d, mem freq %d), "
8717                                  "disabling CxSR\n",
8718                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8719                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8720                         /* Disable CxSR and never update its watermark again */
8721                         pineview_disable_cxsr(dev);
8722                         dev_priv->display.update_wm = NULL;
8723                 } else
8724                         dev_priv->display.update_wm = pineview_update_wm;
8725                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8726         } else if (IS_G4X(dev)) {
8727                 dev_priv->display.write_eld = g4x_write_eld;
8728                 dev_priv->display.update_wm = g4x_update_wm;
8729                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8730         } else if (IS_GEN4(dev)) {
8731                 dev_priv->display.update_wm = i965_update_wm;
8732                 if (IS_CRESTLINE(dev))
8733                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8734                 else if (IS_BROADWATER(dev))
8735                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8736         } else if (IS_GEN3(dev)) {
8737                 dev_priv->display.update_wm = i9xx_update_wm;
8738                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8739                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8740         } else if (IS_I865G(dev)) {
8741                 dev_priv->display.update_wm = i830_update_wm;
8742                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8743                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8744         } else if (IS_I85X(dev)) {
8745                 dev_priv->display.update_wm = i9xx_update_wm;
8746                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8747                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8748         } else {
8749                 dev_priv->display.update_wm = i830_update_wm;
8750                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8751                 if (IS_845G(dev))
8752                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8753                 else
8754                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8755         }
8756
8757         /* Default just returns -ENODEV to indicate unsupported */
8758         dev_priv->display.queue_flip = intel_default_queue_flip;
8759
8760         switch (INTEL_INFO(dev)->gen) {
8761         case 2:
8762                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8763                 break;
8764
8765         case 3:
8766                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8767                 break;
8768
8769         case 4:
8770         case 5:
8771                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8772                 break;
8773
8774         case 6:
8775                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8776                 break;
8777         case 7:
8778                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8779                 break;
8780         }
8781 }
8782
8783 /*
8784  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8785  * resume, or other times.  This quirk makes sure that's the case for
8786  * affected systems.
8787  */
8788 static void quirk_pipea_force(struct drm_device *dev)
8789 {
8790         struct drm_i915_private *dev_priv = dev->dev_private;
8791
8792         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8793         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8794 }
8795
8796 /*
8797  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8798  */
8799 static void quirk_ssc_force_disable(struct drm_device *dev)
8800 {
8801         struct drm_i915_private *dev_priv = dev->dev_private;
8802         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8803 }
8804
8805 struct intel_quirk {
8806         int device;
8807         int subsystem_vendor;
8808         int subsystem_device;
8809         void (*hook)(struct drm_device *dev);
8810 };
8811
8812 struct intel_quirk intel_quirks[] = {
8813         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8814         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8815         /* HP Mini needs pipe A force quirk (LP: #322104) */
8816         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8817
8818         /* Thinkpad R31 needs pipe A force quirk */
8819         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8820         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8821         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8822
8823         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8824         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8825         /* ThinkPad X40 needs pipe A force quirk */
8826
8827         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8828         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8829
8830         /* 855 & before need to leave pipe A & dpll A up */
8831         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8832         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8833
8834         /* Lenovo U160 cannot use SSC on LVDS */
8835         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8836
8837         /* Sony Vaio Y cannot use SSC on LVDS */
8838         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8839 };
8840
8841 static void intel_init_quirks(struct drm_device *dev)
8842 {
8843         struct pci_dev *d = dev->pdev;
8844         int i;
8845
8846         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8847                 struct intel_quirk *q = &intel_quirks[i];
8848
8849                 if (d->device == q->device &&
8850                     (d->subsystem_vendor == q->subsystem_vendor ||
8851                      q->subsystem_vendor == PCI_ANY_ID) &&
8852                     (d->subsystem_device == q->subsystem_device ||
8853                      q->subsystem_device == PCI_ANY_ID))
8854                         q->hook(dev);
8855         }
8856 }
8857
8858 /* Disable the VGA plane that we never use */
8859 static void i915_disable_vga(struct drm_device *dev)
8860 {
8861         struct drm_i915_private *dev_priv = dev->dev_private;
8862         u8 sr1;
8863         u32 vga_reg;
8864
8865         if (HAS_PCH_SPLIT(dev))
8866                 vga_reg = CPU_VGACNTRL;
8867         else
8868                 vga_reg = VGACNTRL;
8869
8870         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8871         outb(1, VGA_SR_INDEX);
8872         sr1 = inb(VGA_SR_DATA);
8873         outb(sr1 | 1<<5, VGA_SR_DATA);
8874         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8875         udelay(300);
8876
8877         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8878         POSTING_READ(vga_reg);
8879 }
8880
8881 void intel_modeset_init(struct drm_device *dev)
8882 {
8883         struct drm_i915_private *dev_priv = dev->dev_private;
8884         int i;
8885
8886         drm_mode_config_init(dev);
8887
8888         dev->mode_config.min_width = 0;
8889         dev->mode_config.min_height = 0;
8890
8891         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8892
8893         intel_init_quirks(dev);
8894
8895         intel_init_display(dev);
8896
8897         if (IS_GEN2(dev)) {
8898                 dev->mode_config.max_width = 2048;
8899                 dev->mode_config.max_height = 2048;
8900         } else if (IS_GEN3(dev)) {
8901                 dev->mode_config.max_width = 4096;
8902                 dev->mode_config.max_height = 4096;
8903         } else {
8904                 dev->mode_config.max_width = 8192;
8905                 dev->mode_config.max_height = 8192;
8906         }
8907         dev->mode_config.fb_base = dev->agp->base;
8908
8909         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8910                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8911
8912         for (i = 0; i < dev_priv->num_pipe; i++) {
8913                 intel_crtc_init(dev, i);
8914         }
8915
8916         /* Just disable it once at startup */
8917         i915_disable_vga(dev);
8918         intel_setup_outputs(dev);
8919
8920         intel_init_clock_gating(dev);
8921
8922         if (IS_IRONLAKE_M(dev)) {
8923                 ironlake_enable_drps(dev);
8924                 intel_init_emon(dev);
8925         }
8926
8927         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8928                 gen6_enable_rps(dev_priv);
8929                 gen6_update_ring_freq(dev_priv);
8930         }
8931
8932         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8933         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8934                     (unsigned long)dev);
8935 }
8936
8937 void intel_modeset_gem_init(struct drm_device *dev)
8938 {
8939         if (IS_IRONLAKE_M(dev))
8940                 ironlake_enable_rc6(dev);
8941
8942         intel_setup_overlay(dev);
8943 }
8944
8945 void intel_modeset_cleanup(struct drm_device *dev)
8946 {
8947         struct drm_i915_private *dev_priv = dev->dev_private;
8948         struct drm_crtc *crtc;
8949         struct intel_crtc *intel_crtc;
8950
8951         drm_kms_helper_poll_fini(dev);
8952         mutex_lock(&dev->struct_mutex);
8953
8954         intel_unregister_dsm_handler();
8955
8956
8957         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8958                 /* Skip inactive CRTCs */
8959                 if (!crtc->fb)
8960                         continue;
8961
8962                 intel_crtc = to_intel_crtc(crtc);
8963                 intel_increase_pllclock(crtc);
8964         }
8965
8966         intel_disable_fbc(dev);
8967
8968         if (IS_IRONLAKE_M(dev))
8969                 ironlake_disable_drps(dev);
8970         if (IS_GEN6(dev) || IS_GEN7(dev))
8971                 gen6_disable_rps(dev);
8972
8973         if (IS_IRONLAKE_M(dev))
8974                 ironlake_disable_rc6(dev);
8975
8976         mutex_unlock(&dev->struct_mutex);
8977
8978         /* Disable the irq before mode object teardown, for the irq might
8979          * enqueue unpin/hotplug work. */
8980         drm_irq_uninstall(dev);
8981         cancel_work_sync(&dev_priv->hotplug_work);
8982         cancel_work_sync(&dev_priv->rps_work);
8983
8984         /* flush any delayed tasks or pending work */
8985         flush_scheduled_work();
8986
8987         /* Shut off idle work before the crtcs get freed. */
8988         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8989                 intel_crtc = to_intel_crtc(crtc);
8990                 del_timer_sync(&intel_crtc->idle_timer);
8991         }
8992         del_timer_sync(&dev_priv->idle_timer);
8993         cancel_work_sync(&dev_priv->idle_work);
8994
8995         drm_mode_config_cleanup(dev);
8996 }
8997
8998 /*
8999  * Return which encoder is currently attached for connector.
9000  */
9001 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9002 {
9003         return &intel_attached_encoder(connector)->base;
9004 }
9005
9006 void intel_connector_attach_encoder(struct intel_connector *connector,
9007                                     struct intel_encoder *encoder)
9008 {
9009         connector->encoder = encoder;
9010         drm_mode_connector_attach_encoder(&connector->base,
9011                                           &encoder->base);
9012 }
9013
9014 /*
9015  * set vga decode state - true == enable VGA decode
9016  */
9017 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9018 {
9019         struct drm_i915_private *dev_priv = dev->dev_private;
9020         u16 gmch_ctrl;
9021
9022         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9023         if (state)
9024                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9025         else
9026                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9027         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9028         return 0;
9029 }
9030
9031 #ifdef CONFIG_DEBUG_FS
9032 #include <linux/seq_file.h>
9033
9034 struct intel_display_error_state {
9035         struct intel_cursor_error_state {
9036                 u32 control;
9037                 u32 position;
9038                 u32 base;
9039                 u32 size;
9040         } cursor[2];
9041
9042         struct intel_pipe_error_state {
9043                 u32 conf;
9044                 u32 source;
9045
9046                 u32 htotal;
9047                 u32 hblank;
9048                 u32 hsync;
9049                 u32 vtotal;
9050                 u32 vblank;
9051                 u32 vsync;
9052         } pipe[2];
9053
9054         struct intel_plane_error_state {
9055                 u32 control;
9056                 u32 stride;
9057                 u32 size;
9058                 u32 pos;
9059                 u32 addr;
9060                 u32 surface;
9061                 u32 tile_offset;
9062         } plane[2];
9063 };
9064
9065 struct intel_display_error_state *
9066 intel_display_capture_error_state(struct drm_device *dev)
9067 {
9068         drm_i915_private_t *dev_priv = dev->dev_private;
9069         struct intel_display_error_state *error;
9070         int i;
9071
9072         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9073         if (error == NULL)
9074                 return NULL;
9075
9076         for (i = 0; i < 2; i++) {
9077                 error->cursor[i].control = I915_READ(CURCNTR(i));
9078                 error->cursor[i].position = I915_READ(CURPOS(i));
9079                 error->cursor[i].base = I915_READ(CURBASE(i));
9080
9081                 error->plane[i].control = I915_READ(DSPCNTR(i));
9082                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9083                 error->plane[i].size = I915_READ(DSPSIZE(i));
9084                 error->plane[i].pos = I915_READ(DSPPOS(i));
9085                 error->plane[i].addr = I915_READ(DSPADDR(i));
9086                 if (INTEL_INFO(dev)->gen >= 4) {
9087                         error->plane[i].surface = I915_READ(DSPSURF(i));
9088                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9089                 }
9090
9091                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9092                 error->pipe[i].source = I915_READ(PIPESRC(i));
9093                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9094                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9095                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9096                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9097                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9098                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9099         }
9100
9101         return error;
9102 }
9103
9104 void
9105 intel_display_print_error_state(struct seq_file *m,
9106                                 struct drm_device *dev,
9107                                 struct intel_display_error_state *error)
9108 {
9109         int i;
9110
9111         for (i = 0; i < 2; i++) {
9112                 seq_printf(m, "Pipe [%d]:\n", i);
9113                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9114                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9115                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9116                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9117                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9118                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9119                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9120                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9121
9122                 seq_printf(m, "Plane [%d]:\n", i);
9123                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9124                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9125                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9126                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9127                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9128                 if (INTEL_INFO(dev)->gen >= 4) {
9129                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9130                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9131                 }
9132
9133                 seq_printf(m, "Cursor [%d]:\n", i);
9134                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9135                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9136                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9137         }
9138 }
9139 #endif