drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *best_clock);
  90
  91 static bool
  92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  93                       int target, int refclk, intel_clock_t *best_clock);
  94 static bool
  95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  96                            int target, int refclk, intel_clock_t *best_clock);
  97
  98 static inline u32 /* units of 100MHz */
  99 intel_fdi_link_freq(struct drm_device *dev)
 100 {
 101         if (IS_GEN5(dev)) {
 102                 struct drm_i915_private *dev_priv = dev->dev_private;
 103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 104         } else
 105                 return 27;
 106 }
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 2 },
 119         .find_pll = intel_find_best_PLL,
 120 };
 121
 122 static const intel_limit_t intel_limits_i8xx_lvds = {
 123         .dot = { .min = 25000, .max = 350000 },
 124         .vco = { .min = 930000, .max = 1400000 },
 125         .n = { .min = 3, .max = 16 },
 126         .m = { .min = 96, .max = 140 },
 127         .m1 = { .min = 18, .max = 26 },
 128         .m2 = { .min = 6, .max = 16 },
 129         .p = { .min = 4, .max = 128 },
 130         .p1 = { .min = 1, .max = 6 },
 131         .p2 = { .dot_limit = 165000,
 132                 .p2_slow = 14, .p2_fast = 7 },
 133         .find_pll = intel_find_best_PLL,
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 8, .max = 18 },
 142         .m2 = { .min = 3, .max = 7 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147         .find_pll = intel_find_best_PLL,
 148 };
 149
 150 static const intel_limit_t intel_limits_i9xx_lvds = {
 151         .dot = { .min = 20000, .max = 400000 },
 152         .vco = { .min = 1400000, .max = 2800000 },
 153         .n = { .min = 1, .max = 6 },
 154         .m = { .min = 70, .max = 120 },
 155         .m1 = { .min = 10, .max = 22 },
 156         .m2 = { .min = 5, .max = 9 },
 157         .p = { .min = 7, .max = 98 },
 158         .p1 = { .min = 1, .max = 8 },
 159         .p2 = { .dot_limit = 112000,
 160                 .p2_slow = 14, .p2_fast = 7 },
 161         .find_pll = intel_find_best_PLL,
 162 };
 163
 164
 165 static const intel_limit_t intel_limits_g4x_sdvo = {
 166         .dot = { .min = 25000, .max = 270000 },
 167         .vco = { .min = 1750000, .max = 3500000},
 168         .n = { .min = 1, .max = 4 },
 169         .m = { .min = 104, .max = 138 },
 170         .m1 = { .min = 17, .max = 23 },
 171         .m2 = { .min = 5, .max = 11 },
 172         .p = { .min = 10, .max = 30 },
 173         .p1 = { .min = 1, .max = 3},
 174         .p2 = { .dot_limit = 270000,
 175                 .p2_slow = 10,
 176                 .p2_fast = 10
 177         },
 178         .find_pll = intel_g4x_find_best_PLL,
 179 };
 180
 181 static const intel_limit_t intel_limits_g4x_hdmi = {
 182         .dot = { .min = 22000, .max = 400000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 16, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8},
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192         .find_pll = intel_g4x_find_best_PLL,
 193 };
 194
 195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 196         .dot = { .min = 20000, .max = 115000 },
 197         .vco = { .min = 1750000, .max = 3500000 },
 198         .n = { .min = 1, .max = 3 },
 199         .m = { .min = 104, .max = 138 },
 200         .m1 = { .min = 17, .max = 23 },
 201         .m2 = { .min = 5, .max = 11 },
 202         .p = { .min = 28, .max = 112 },
 203         .p1 = { .min = 2, .max = 8 },
 204         .p2 = { .dot_limit = 0,
 205                 .p2_slow = 14, .p2_fast = 14
 206         },
 207         .find_pll = intel_g4x_find_best_PLL,
 208 };
 209
 210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 211         .dot = { .min = 80000, .max = 224000 },
 212         .vco = { .min = 1750000, .max = 3500000 },
 213         .n = { .min = 1, .max = 3 },
 214         .m = { .min = 104, .max = 138 },
 215         .m1 = { .min = 17, .max = 23 },
 216         .m2 = { .min = 5, .max = 11 },
 217         .p = { .min = 14, .max = 42 },
 218         .p1 = { .min = 2, .max = 6 },
 219         .p2 = { .dot_limit = 0,
 220                 .p2_slow = 7, .p2_fast = 7
 221         },
 222         .find_pll = intel_g4x_find_best_PLL,
 223 };
 224
 225 static const intel_limit_t intel_limits_g4x_display_port = {
 226         .dot = { .min = 161670, .max = 227000 },
 227         .vco = { .min = 1750000, .max = 3500000},
 228         .n = { .min = 1, .max = 2 },
 229         .m = { .min = 97, .max = 108 },
 230         .m1 = { .min = 0x10, .max = 0x12 },
 231         .m2 = { .min = 0x05, .max = 0x06 },
 232         .p = { .min = 10, .max = 20 },
 233         .p1 = { .min = 1, .max = 2},
 234         .p2 = { .dot_limit = 0,
 235                 .p2_slow = 10, .p2_fast = 10 },
 236         .find_pll = intel_find_pll_g4x_dp,
 237 };
 238
 239 static const intel_limit_t intel_limits_pineview_sdvo = {
 240         .dot = { .min = 20000, .max = 400000},
 241         .vco = { .min = 1700000, .max = 3500000 },
 242         /* Pineview's Ncounter is a ring counter */
 243         .n = { .min = 3, .max = 6 },
 244         .m = { .min = 2, .max = 256 },
 245         /* Pineview only has one combined m divider, which we treat as m2. */
 246         .m1 = { .min = 0, .max = 0 },
 247         .m2 = { .min = 0, .max = 254 },
 248         .p = { .min = 5, .max = 80 },
 249         .p1 = { .min = 1, .max = 8 },
 250         .p2 = { .dot_limit = 200000,
 251                 .p2_slow = 10, .p2_fast = 5 },
 252         .find_pll = intel_find_best_PLL,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         .n = { .min = 3, .max = 6 },
 259         .m = { .min = 2, .max = 256 },
 260         .m1 = { .min = 0, .max = 0 },
 261         .m2 = { .min = 0, .max = 254 },
 262         .p = { .min = 7, .max = 112 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 14 },
 266         .find_pll = intel_find_best_PLL,
 267 };
 268
 269 /* Ironlake / Sandybridge
 270  *
 271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 272  * the range value for them is (actual_value - 2).
 273  */
 274 static const intel_limit_t intel_limits_ironlake_dac = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 5 },
 278         .m = { .min = 79, .max = 127 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285         .find_pll = intel_g4x_find_best_PLL,
 286 };
 287
 288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 1760000, .max = 3510000 },
 291         .n = { .min = 1, .max = 3 },
 292         .m = { .min = 79, .max = 118 },
 293         .m1 = { .min = 12, .max = 22 },
 294         .m2 = { .min = 5, .max = 9 },
 295         .p = { .min = 28, .max = 112 },
 296         .p1 = { .min = 2, .max = 8 },
 297         .p2 = { .dot_limit = 225000,
 298                 .p2_slow = 14, .p2_fast = 14 },
 299         .find_pll = intel_g4x_find_best_PLL,
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 127 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 56 },
 310         .p1 = { .min = 2, .max = 8 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313         .find_pll = intel_g4x_find_best_PLL,
 314 };
 315
 316 /* LVDS 100mhz refclk limits. */
 317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 2 },
 321         .m = { .min = 79, .max = 126 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328         .find_pll = intel_g4x_find_best_PLL,
 329 };
 330
 331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 332         .dot = { .min = 25000, .max = 350000 },
 333         .vco = { .min = 1760000, .max = 3510000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 79, .max = 126 },
 336         .m1 = { .min = 12, .max = 22 },
 337         .m2 = { .min = 5, .max = 9 },
 338         .p = { .min = 14, .max = 42 },
 339         .p1 = { .min = 2, .max = 6 },
 340         .p2 = { .dot_limit = 225000,
 341                 .p2_slow = 7, .p2_fast = 7 },
 342         .find_pll = intel_g4x_find_best_PLL,
 343 };
 344
 345 static const intel_limit_t intel_limits_ironlake_display_port = {
 346         .dot = { .min = 25000, .max = 350000 },
 347         .vco = { .min = 1760000, .max = 3510000},
 348         .n = { .min = 1, .max = 2 },
 349         .m = { .min = 81, .max = 90 },
 350         .m1 = { .min = 12, .max = 22 },
 351         .m2 = { .min = 5, .max = 9 },
 352         .p = { .min = 10, .max = 20 },
 353         .p1 = { .min = 1, .max = 2},
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 10, .p2_fast = 10 },
 356         .find_pll = intel_find_pll_ironlake_dp,
 357 };
 358
 359 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 360                               unsigned int reg)
 361 {
 362         unsigned int val;
 363
 364         if (dev_priv->lvds_val)
 365                 val = dev_priv->lvds_val;
 366         else {
 367                 /* BIOS should set the proper LVDS register value at boot, but
 368                  * in reality, it doesn't set the value when the lid is closed;
 369                  * we need to check "the value to be set" in VBT when LVDS
 370                  * register is uninitialized.
 371                  */
 372                 val = I915_READ(reg);
 373                 if (!(val & ~LVDS_DETECTED))
 374                         val = dev_priv->bios_lvds_val;
 375                 dev_priv->lvds_val = val;
 376         }
 377         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 378 }
 379
 380 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 381                                                 int refclk)
 382 {
 383         struct drm_device *dev = crtc->dev;
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         const intel_limit_t *limit;
 386
 387         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 388                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 389                         /* LVDS dual channel */
 390                         if (refclk == 100000)
 391                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 392                         else
 393                                 limit = &intel_limits_ironlake_dual_lvds;
 394                 } else {
 395                         if (refclk == 100000)
 396                                 limit = &intel_limits_ironlake_single_lvds_100m;
 397                         else
 398                                 limit = &intel_limits_ironlake_single_lvds;
 399                 }
 400         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 401                         HAS_eDP)
 402                 limit = &intel_limits_ironlake_display_port;
 403         else
 404                 limit = &intel_limits_ironlake_dac;
 405
 406         return limit;
 407 }
 408
 409 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 410 {
 411         struct drm_device *dev = crtc->dev;
 412         struct drm_i915_private *dev_priv = dev->dev_private;
 413         const intel_limit_t *limit;
 414
 415         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 416                 if (is_dual_link_lvds(dev_priv, LVDS))
 417                         /* LVDS with dual channel */
 418                         limit = &intel_limits_g4x_dual_channel_lvds;
 419                 else
 420                         /* LVDS with dual channel */
 421                         limit = &intel_limits_g4x_single_channel_lvds;
 422         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 423                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 424                 limit = &intel_limits_g4x_hdmi;
 425         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 426                 limit = &intel_limits_g4x_sdvo;
 427         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 428                 limit = &intel_limits_g4x_display_port;
 429         } else /* The option is for other outputs */
 430                 limit = &intel_limits_i9xx_sdvo;
 431
 432         return limit;
 433 }
 434
 435 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 436 {
 437         struct drm_device *dev = crtc->dev;
 438         const intel_limit_t *limit;
 439
 440         if (HAS_PCH_SPLIT(dev))
 441                 limit = intel_ironlake_limit(crtc, refclk);
 442         else if (IS_G4X(dev)) {
 443                 limit = intel_g4x_limit(crtc);
 444         } else if (IS_PINEVIEW(dev)) {
 445                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 446                         limit = &intel_limits_pineview_lvds;
 447                 else
 448                         limit = &intel_limits_pineview_sdvo;
 449         } else if (!IS_GEN2(dev)) {
 450                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 451                         limit = &intel_limits_i9xx_lvds;
 452                 else
 453                         limit = &intel_limits_i9xx_sdvo;
 454         } else {
 455                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 456                         limit = &intel_limits_i8xx_lvds;
 457                 else
 458                         limit = &intel_limits_i8xx_dvo;
 459         }
 460         return limit;
 461 }
 462
 463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 464 static void pineview_clock(int refclk, intel_clock_t *clock)
 465 {
 466         clock->m = clock->m2 + 2;
 467         clock->p = clock->p1 * clock->p2;
 468         clock->vco = refclk * clock->m / clock->n;
 469         clock->dot = clock->vco / clock->p;
 470 }
 471
 472 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 473 {
 474         if (IS_PINEVIEW(dev)) {
 475                 pineview_clock(refclk, clock);
 476                 return;
 477         }
 478         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 479         clock->p = clock->p1 * clock->p2;
 480         clock->vco = refclk * clock->m / (clock->n + 2);
 481         clock->dot = clock->vco / clock->p;
 482 }
 483
 484 /**
 485  * Returns whether any output on the specified pipe is of the specified type
 486  */
 487 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 488 {
 489         struct drm_device *dev = crtc->dev;
 490         struct drm_mode_config *mode_config = &dev->mode_config;
 491         struct intel_encoder *encoder;
 492
 493         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 494                 if (encoder->base.crtc == crtc && encoder->type == type)
 495                         return true;
 496
 497         return false;
 498 }
 499
 500 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 501 /**
 502  * Returns whether the given set of divisors are valid for a given refclk with
 503  * the given connectors.
 504  */
 505
 506 static bool intel_PLL_is_valid(struct drm_device *dev,
 507                                const intel_limit_t *limit,
 508                                const intel_clock_t *clock)
 509 {
 510         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 511                 INTELPllInvalid("p1 out of range\n");
 512         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 513                 INTELPllInvalid("p out of range\n");
 514         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 515                 INTELPllInvalid("m2 out of range\n");
 516         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 517                 INTELPllInvalid("m1 out of range\n");
 518         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 519                 INTELPllInvalid("m1 <= m2\n");
 520         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 521                 INTELPllInvalid("m out of range\n");
 522         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 523                 INTELPllInvalid("n out of range\n");
 524         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 525                 INTELPllInvalid("vco out of range\n");
 526         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 527          * connector, etc., rather than just a single range.
 528          */
 529         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 530                 INTELPllInvalid("dot out of range\n");
 531
 532         return true;
 533 }
 534
 535 static bool
 536 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 537                     int target, int refclk, intel_clock_t *best_clock)
 538
 539 {
 540         struct drm_device *dev = crtc->dev;
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         intel_clock_t clock;
 543         int err = target;
 544
 545         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 546             (I915_READ(LVDS)) != 0) {
 547                 /*
 548                  * For LVDS, if the panel is on, just rely on its current
 549                  * settings for dual-channel.  We haven't figured out how to
 550                  * reliably set up different single/dual channel state, if we
 551                  * even can.
 552                  */
 553                 if (is_dual_link_lvds(dev_priv, LVDS))
 554                         clock.p2 = limit->p2.p2_fast;
 555                 else
 556                         clock.p2 = limit->p2.p2_slow;
 557         } else {
 558                 if (target < limit->p2.dot_limit)
 559                         clock.p2 = limit->p2.p2_slow;
 560                 else
 561                         clock.p2 = limit->p2.p2_fast;
 562         }
 563
 564         memset(best_clock, 0, sizeof(*best_clock));
 565
 566         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 567              clock.m1++) {
 568                 for (clock.m2 = limit->m2.min;
 569                      clock.m2 <= limit->m2.max; clock.m2++) {
 570                         /* m1 is always 0 in Pineview */
 571                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 572                                 break;
 573                         for (clock.n = limit->n.min;
 574                              clock.n <= limit->n.max; clock.n++) {
 575                                 for (clock.p1 = limit->p1.min;
 576                                         clock.p1 <= limit->p1.max; clock.p1++) {
 577                                         int this_err;
 578
 579                                         intel_clock(dev, refclk, &clock);
 580                                         if (!intel_PLL_is_valid(dev, limit,
 581                                                                 &clock))
 582                                                 continue;
 583
 584                                         this_err = abs(clock.dot - target);
 585                                         if (this_err < err) {
 586                                                 *best_clock = clock;
 587                                                 err = this_err;
 588                                         }
 589                                 }
 590                         }
 591                 }
 592         }
 593
 594         return (err != target);
 595 }
 596
 597 static bool
 598 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 599                         int target, int refclk, intel_clock_t *best_clock)
 600 {
 601         struct drm_device *dev = crtc->dev;
 602         struct drm_i915_private *dev_priv = dev->dev_private;
 603         intel_clock_t clock;
 604         int max_n;
 605         bool found;
 606         /* approximately equals target * 0.00585 */
 607         int err_most = (target >> 8) + (target >> 9);
 608         found = false;
 609
 610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 int lvds_reg;
 612
 613                 if (HAS_PCH_SPLIT(dev))
 614                         lvds_reg = PCH_LVDS;
 615                 else
 616                         lvds_reg = LVDS;
 617                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 618                     LVDS_CLKB_POWER_UP)
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630         max_n = limit->n.max;
 631         /* based on hardware requirement, prefer smaller n to precision */
 632         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 633                 /* based on hardware requirement, prefere larger m1,m2 */
 634                 for (clock.m1 = limit->m1.max;
 635                      clock.m1 >= limit->m1.min; clock.m1--) {
 636                         for (clock.m2 = limit->m2.max;
 637                              clock.m2 >= limit->m2.min; clock.m2--) {
 638                                 for (clock.p1 = limit->p1.max;
 639                                      clock.p1 >= limit->p1.min; clock.p1--) {
 640                                         int this_err;
 641
 642                                         intel_clock(dev, refclk, &clock);
 643                                         if (!intel_PLL_is_valid(dev, limit,
 644                                                                 &clock))
 645                                                 continue;
 646
 647                                         this_err = abs(clock.dot - target);
 648                                         if (this_err < err_most) {
 649                                                 *best_clock = clock;
 650                                                 err_most = this_err;
 651                                                 max_n = clock.n;
 652                                                 found = true;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658         return found;
 659 }
 660
 661 static bool
 662 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 663                            int target, int refclk, intel_clock_t *best_clock)
 664 {
 665         struct drm_device *dev = crtc->dev;
 666         intel_clock_t clock;
 667
 668         if (target < 200000) {
 669                 clock.n = 1;
 670                 clock.p1 = 2;
 671                 clock.p2 = 10;
 672                 clock.m1 = 12;
 673                 clock.m2 = 9;
 674         } else {
 675                 clock.n = 2;
 676                 clock.p1 = 1;
 677                 clock.p2 = 10;
 678                 clock.m1 = 14;
 679                 clock.m2 = 8;
 680         }
 681         intel_clock(dev, refclk, &clock);
 682         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 683         return true;
 684 }
 685
 686 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 687 static bool
 688 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 689                       int target, int refclk, intel_clock_t *best_clock)
 690 {
 691         intel_clock_t clock;
 692         if (target < 200000) {
 693                 clock.p1 = 2;
 694                 clock.p2 = 10;
 695                 clock.n = 2;
 696                 clock.m1 = 23;
 697                 clock.m2 = 8;
 698         } else {
 699                 clock.p1 = 1;
 700                 clock.p2 = 10;
 701                 clock.n = 1;
 702                 clock.m1 = 14;
 703                 clock.m2 = 2;
 704         }
 705         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 706         clock.p = (clock.p1 * clock.p2);
 707         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 708         clock.vco = 0;
 709         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 710         return true;
 711 }
 712
 713 /**
 714  * intel_wait_for_vblank - wait for vblank on a given pipe
 715  * @dev: drm device
 716  * @pipe: pipe to wait for
 717  *
 718  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 719  * mode setting code.
 720  */
 721 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 722 {
 723         struct drm_i915_private *dev_priv = dev->dev_private;
 724         int pipestat_reg = PIPESTAT(pipe);
 725
 726         /* Clear existing vblank status. Note this will clear any other
 727          * sticky status fields as well.
 728          *
 729          * This races with i915_driver_irq_handler() with the result
 730          * that either function could miss a vblank event.  Here it is not
 731          * fatal, as we will either wait upon the next vblank interrupt or
 732          * timeout.  Generally speaking intel_wait_for_vblank() is only
 733          * called during modeset at which time the GPU should be idle and
 734          * should *not* be performing page flips and thus not waiting on
 735          * vblanks...
 736          * Currently, the result of us stealing a vblank from the irq
 737          * handler is that a single frame will be skipped during swapbuffers.
 738          */
 739         I915_WRITE(pipestat_reg,
 740                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 741
 742         /* Wait for vblank interrupt bit to set */
 743         if (wait_for(I915_READ(pipestat_reg) &
 744                      PIPE_VBLANK_INTERRUPT_STATUS,
 745                      50))
 746                 DRM_DEBUG_KMS("vblank wait timed out\n");
 747 }
 748
 749 /*
 750  * intel_wait_for_pipe_off - wait for pipe to turn off
 751  * @dev: drm device
 752  * @pipe: pipe to wait for
 753  *
 754  * After disabling a pipe, we can't wait for vblank in the usual way,
 755  * spinning on the vblank interrupt status bit, since we won't actually
 756  * see an interrupt when the pipe is disabled.
 757  *
 758  * On Gen4 and above:
 759  *   wait for the pipe register state bit to turn off
 760  *
 761  * Otherwise:
 762  *   wait for the display line value to settle (it usually
 763  *   ends up stopping at the start of the next frame).
 764  *
 765  */
 766 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 767 {
 768         struct drm_i915_private *dev_priv = dev->dev_private;
 769
 770         if (INTEL_INFO(dev)->gen >= 4) {
 771                 int reg = PIPECONF(pipe);
 772
 773                 /* Wait for the Pipe State to go off */
 774                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 775                              100))
 776                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 777         } else {
 778                 u32 last_line;
 779                 int reg = PIPEDSL(pipe);
 780                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 781
 782                 /* Wait for the display line to settle */
 783                 do {
 784                         last_line = I915_READ(reg) & DSL_LINEMASK;
 785                         mdelay(5);
 786                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 787                          time_after(timeout, jiffies));
 788                 if (time_after(jiffies, timeout))
 789                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 790         }
 791 }
 792
 793 static const char *state_string(bool enabled)
 794 {
 795         return enabled ? "on" : "off";
 796 }
 797
 798 /* Only for pre-ILK configs */
 799 static void assert_pll(struct drm_i915_private *dev_priv,
 800                        enum pipe pipe, bool state)
 801 {
 802         int reg;
 803         u32 val;
 804         bool cur_state;
 805
 806         reg = DPLL(pipe);
 807         val = I915_READ(reg);
 808         cur_state = !!(val & DPLL_VCO_ENABLE);
 809         WARN(cur_state != state,
 810              "PLL state assertion failure (expected %s, current %s)\n",
 811              state_string(state), state_string(cur_state));
 812 }
 813 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 814 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 815
 816 /* For ILK+ */
 817 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 818                            enum pipe pipe, bool state)
 819 {
 820         int reg;
 821         u32 val;
 822         bool cur_state;
 823
 824         if (HAS_PCH_CPT(dev_priv->dev)) {
 825                 u32 pch_dpll;
 826
 827                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 828
 829                 /* Make sure the selected PLL is enabled to the transcoder */
 830                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 831                      "transcoder %d PLL not enabled\n", pipe);
 832
 833                 /* Convert the transcoder pipe number to a pll pipe number */
 834                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 835         }
 836
 837         reg = PCH_DPLL(pipe);
 838         val = I915_READ(reg);
 839         cur_state = !!(val & DPLL_VCO_ENABLE);
 840         WARN(cur_state != state,
 841              "PCH PLL state assertion failure (expected %s, current %s)\n",
 842              state_string(state), state_string(cur_state));
 843 }
 844 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 845 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 846
 847 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 848                           enum pipe pipe, bool state)
 849 {
 850         int reg;
 851         u32 val;
 852         bool cur_state;
 853
 854         reg = FDI_TX_CTL(pipe);
 855         val = I915_READ(reg);
 856         cur_state = !!(val & FDI_TX_ENABLE);
 857         WARN(cur_state != state,
 858              "FDI TX state assertion failure (expected %s, current %s)\n",
 859              state_string(state), state_string(cur_state));
 860 }
 861 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 862 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 863
 864 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 865                           enum pipe pipe, bool state)
 866 {
 867         int reg;
 868         u32 val;
 869         bool cur_state;
 870
 871         reg = FDI_RX_CTL(pipe);
 872         val = I915_READ(reg);
 873         cur_state = !!(val & FDI_RX_ENABLE);
 874         WARN(cur_state != state,
 875              "FDI RX state assertion failure (expected %s, current %s)\n",
 876              state_string(state), state_string(cur_state));
 877 }
 878 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 879 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 880
 881 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 882                                       enum pipe pipe)
 883 {
 884         int reg;
 885         u32 val;
 886
 887         /* ILK FDI PLL is always enabled */
 888         if (dev_priv->info->gen == 5)
 889                 return;
 890
 891         reg = FDI_TX_CTL(pipe);
 892         val = I915_READ(reg);
 893         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 894 }
 895
 896 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 897                                       enum pipe pipe)
 898 {
 899         int reg;
 900         u32 val;
 901
 902         reg = FDI_RX_CTL(pipe);
 903         val = I915_READ(reg);
 904         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 905 }
 906
 907 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 908                                   enum pipe pipe)
 909 {
 910         int pp_reg, lvds_reg;
 911         u32 val;
 912         enum pipe panel_pipe = PIPE_A;
 913         bool locked = true;
 914
 915         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 916                 pp_reg = PCH_PP_CONTROL;
 917                 lvds_reg = PCH_LVDS;
 918         } else {
 919                 pp_reg = PP_CONTROL;
 920                 lvds_reg = LVDS;
 921         }
 922
 923         val = I915_READ(pp_reg);
 924         if (!(val & PANEL_POWER_ON) ||
 925             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 926                 locked = false;
 927
 928         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 929                 panel_pipe = PIPE_B;
 930
 931         WARN(panel_pipe == pipe && locked,
 932              "panel assertion failure, pipe %c regs locked\n",
 933              pipe_name(pipe));
 934 }
 935
 936 static void assert_pipe(struct drm_i915_private *dev_priv,
 937                         enum pipe pipe, bool state)
 938 {
 939         int reg;
 940         u32 val;
 941         bool cur_state;
 942
 943         reg = PIPECONF(pipe);
 944         val = I915_READ(reg);
 945         cur_state = !!(val & PIPECONF_ENABLE);
 946         WARN(cur_state != state,
 947              "pipe %c assertion failure (expected %s, current %s)\n",
 948              pipe_name(pipe), state_string(state), state_string(cur_state));
 949 }
 950 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 951 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 952
 953 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 954                                  enum plane plane)
 955 {
 956         int reg;
 957         u32 val;
 958
 959         reg = DSPCNTR(plane);
 960         val = I915_READ(reg);
 961         WARN(!(val & DISPLAY_PLANE_ENABLE),
 962              "plane %c assertion failure, should be active but is disabled\n",
 963              plane_name(plane));
 964 }
 965
 966 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 967                                    enum pipe pipe)
 968 {
 969         int reg, i;
 970         u32 val;
 971         int cur_pipe;
 972
 973         /* Planes are fixed to pipes on ILK+ */
 974         if (HAS_PCH_SPLIT(dev_priv->dev))
 975                 return;
 976
 977         /* Need to check both planes against the pipe */
 978         for (i = 0; i < 2; i++) {
 979                 reg = DSPCNTR(i);
 980                 val = I915_READ(reg);
 981                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 982                         DISPPLANE_SEL_PIPE_SHIFT;
 983                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 984                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 985                      plane_name(i), pipe_name(pipe));
 986         }
 987 }
 988
 989 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 990 {
 991         u32 val;
 992         bool enabled;
 993
 994         val = I915_READ(PCH_DREF_CONTROL);
 995         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 996                             DREF_SUPERSPREAD_SOURCE_MASK));
 997         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 998 }
 999
1000 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1001                                        enum pipe pipe)
1002 {
1003         int reg;
1004         u32 val;
1005         bool enabled;
1006
1007         reg = TRANSCONF(pipe);
1008         val = I915_READ(reg);
1009         enabled = !!(val & TRANS_ENABLE);
1010         WARN(enabled,
1011              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1012              pipe_name(pipe));
1013 }
1014
1015 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1016                             enum pipe pipe, u32 port_sel, u32 val)
1017 {
1018         if ((val & DP_PORT_EN) == 0)
1019                 return false;
1020
1021         if (HAS_PCH_CPT(dev_priv->dev)) {
1022                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1023                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1024                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1025                         return false;
1026         } else {
1027                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1028                         return false;
1029         }
1030         return true;
1031 }
1032
1033 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1034                               enum pipe pipe, u32 val)
1035 {
1036         if ((val & PORT_ENABLE) == 0)
1037                 return false;
1038
1039         if (HAS_PCH_CPT(dev_priv->dev)) {
1040                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1041                         return false;
1042         } else {
1043                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1044                         return false;
1045         }
1046         return true;
1047 }
1048
1049 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1050                               enum pipe pipe, u32 val)
1051 {
1052         if ((val & LVDS_PORT_EN) == 0)
1053                 return false;
1054
1055         if (HAS_PCH_CPT(dev_priv->dev)) {
1056                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1057                         return false;
1058         } else {
1059                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1060                         return false;
1061         }
1062         return true;
1063 }
1064
1065 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1066                               enum pipe pipe, u32 val)
1067 {
1068         if ((val & ADPA_DAC_ENABLE) == 0)
1069                 return false;
1070         if (HAS_PCH_CPT(dev_priv->dev)) {
1071                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1072                         return false;
1073         } else {
1074                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1075                         return false;
1076         }
1077         return true;
1078 }
1079
1080 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1081                                    enum pipe pipe, int reg, u32 port_sel)
1082 {
1083         u32 val = I915_READ(reg);
1084         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1085              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1086              reg, pipe_name(pipe));
1087 }
1088
1089 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1090                                      enum pipe pipe, int reg)
1091 {
1092         u32 val = I915_READ(reg);
1093         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1094              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1095              reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1099                                       enum pipe pipe)
1100 {
1101         int reg;
1102         u32 val;
1103
1104         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1105         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1106         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1107
1108         reg = PCH_ADPA;
1109         val = I915_READ(reg);
1110         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1111              "PCH VGA enabled on transcoder %c, should be disabled\n",
1112              pipe_name(pipe));
1113
1114         reg = PCH_LVDS;
1115         val = I915_READ(reg);
1116         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1117              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1118              pipe_name(pipe));
1119
1120         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1121         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1122         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1123 }
1124
1125 /**
1126  * intel_enable_pll - enable a PLL
1127  * @dev_priv: i915 private structure
1128  * @pipe: pipe PLL to enable
1129  *
1130  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1131  * make sure the PLL reg is writable first though, since the panel write
1132  * protect mechanism may be enabled.
1133  *
1134  * Note!  This is for pre-ILK only.
1135  */
1136 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1137 {
1138         int reg;
1139         u32 val;
1140
1141         /* No really, not for ILK+ */
1142         BUG_ON(dev_priv->info->gen >= 5);
1143
1144         /* PLL is protected by panel, make sure we can write it */
1145         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1146                 assert_panel_unlocked(dev_priv, pipe);
1147
1148         reg = DPLL(pipe);
1149         val = I915_READ(reg);
1150         val |= DPLL_VCO_ENABLE;
1151
1152         /* We do this three times for luck */
1153         I915_WRITE(reg, val);
1154         POSTING_READ(reg);
1155         udelay(150); /* wait for warmup */
1156         I915_WRITE(reg, val);
1157         POSTING_READ(reg);
1158         udelay(150); /* wait for warmup */
1159         I915_WRITE(reg, val);
1160         POSTING_READ(reg);
1161         udelay(150); /* wait for warmup */
1162 }
1163
1164 /**
1165  * intel_disable_pll - disable a PLL
1166  * @dev_priv: i915 private structure
1167  * @pipe: pipe PLL to disable
1168  *
1169  * Disable the PLL for @pipe, making sure the pipe is off first.
1170  *
1171  * Note!  This is for pre-ILK only.
1172  */
1173 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1174 {
1175         int reg;
1176         u32 val;
1177
1178         /* Don't disable pipe A or pipe A PLLs if needed */
1179         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1180                 return;
1181
1182         /* Make sure the pipe isn't still relying on us */
1183         assert_pipe_disabled(dev_priv, pipe);
1184
1185         reg = DPLL(pipe);
1186         val = I915_READ(reg);
1187         val &= ~DPLL_VCO_ENABLE;
1188         I915_WRITE(reg, val);
1189         POSTING_READ(reg);
1190 }
1191
1192 /**
1193  * intel_enable_pch_pll - enable PCH PLL
1194  * @dev_priv: i915 private structure
1195  * @pipe: pipe PLL to enable
1196  *
1197  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1198  * drives the transcoder clock.
1199  */
1200 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1201                                  enum pipe pipe)
1202 {
1203         int reg;
1204         u32 val;
1205
1206         if (pipe > 1)
1207                 return;
1208
1209         /* PCH only available on ILK+ */
1210         BUG_ON(dev_priv->info->gen < 5);
1211
1212         /* PCH refclock must be enabled first */
1213         assert_pch_refclk_enabled(dev_priv);
1214
1215         reg = PCH_DPLL(pipe);
1216         val = I915_READ(reg);
1217         val |= DPLL_VCO_ENABLE;
1218         I915_WRITE(reg, val);
1219         POSTING_READ(reg);
1220         udelay(200);
1221 }
1222
1223 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1224                                   enum pipe pipe)
1225 {
1226         int reg;
1227         u32 val;
1228
1229         if (pipe > 1)
1230                 return;
1231
1232         /* PCH only available on ILK+ */
1233         BUG_ON(dev_priv->info->gen < 5);
1234
1235         /* Make sure transcoder isn't still depending on us */
1236         assert_transcoder_disabled(dev_priv, pipe);
1237
1238         reg = PCH_DPLL(pipe);
1239         val = I915_READ(reg);
1240         val &= ~DPLL_VCO_ENABLE;
1241         I915_WRITE(reg, val);
1242         POSTING_READ(reg);
1243         udelay(200);
1244 }
1245
1246 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1247                                     enum pipe pipe)
1248 {
1249         int reg;
1250         u32 val;
1251
1252         /* PCH only available on ILK+ */
1253         BUG_ON(dev_priv->info->gen < 5);
1254
1255         /* Make sure PCH DPLL is enabled */
1256         assert_pch_pll_enabled(dev_priv, pipe);
1257
1258         /* FDI must be feeding us bits for PCH ports */
1259         assert_fdi_tx_enabled(dev_priv, pipe);
1260         assert_fdi_rx_enabled(dev_priv, pipe);
1261
1262         reg = TRANSCONF(pipe);
1263         val = I915_READ(reg);
1264
1265         if (HAS_PCH_IBX(dev_priv->dev)) {
1266                 /*
1267                  * make the BPC in transcoder be consistent with
1268                  * that in pipeconf reg.
1269                  */
1270                 val &= ~PIPE_BPC_MASK;
1271                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1272         }
1273         I915_WRITE(reg, val | TRANS_ENABLE);
1274         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1275                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1276 }
1277
1278 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1279                                      enum pipe pipe)
1280 {
1281         int reg;
1282         u32 val;
1283
1284         /* FDI relies on the transcoder */
1285         assert_fdi_tx_disabled(dev_priv, pipe);
1286         assert_fdi_rx_disabled(dev_priv, pipe);
1287
1288         /* Ports must be off as well */
1289         assert_pch_ports_disabled(dev_priv, pipe);
1290
1291         reg = TRANSCONF(pipe);
1292         val = I915_READ(reg);
1293         val &= ~TRANS_ENABLE;
1294         I915_WRITE(reg, val);
1295         /* wait for PCH transcoder off, transcoder state */
1296         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1297                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1298 }
1299
1300 /**
1301  * intel_enable_pipe - enable a pipe, asserting requirements
1302  * @dev_priv: i915 private structure
1303  * @pipe: pipe to enable
1304  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1305  *
1306  * Enable @pipe, making sure that various hardware specific requirements
1307  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1308  *
1309  * @pipe should be %PIPE_A or %PIPE_B.
1310  *
1311  * Will wait until the pipe is actually running (i.e. first vblank) before
1312  * returning.
1313  */
1314 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1315                               bool pch_port)
1316 {
1317         int reg;
1318         u32 val;
1319
1320         /*
1321          * A pipe without a PLL won't actually be able to drive bits from
1322          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1323          * need the check.
1324          */
1325         if (!HAS_PCH_SPLIT(dev_priv->dev))
1326                 assert_pll_enabled(dev_priv, pipe);
1327         else {
1328                 if (pch_port) {
1329                         /* if driving the PCH, we need FDI enabled */
1330                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1331                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1332                 }
1333                 /* FIXME: assert CPU port conditions for SNB+ */
1334         }
1335
1336         reg = PIPECONF(pipe);
1337         val = I915_READ(reg);
1338         if (val & PIPECONF_ENABLE)
1339                 return;
1340
1341         I915_WRITE(reg, val | PIPECONF_ENABLE);
1342         intel_wait_for_vblank(dev_priv->dev, pipe);
1343 }
1344
1345 /**
1346  * intel_disable_pipe - disable a pipe, asserting requirements
1347  * @dev_priv: i915 private structure
1348  * @pipe: pipe to disable
1349  *
1350  * Disable @pipe, making sure that various hardware specific requirements
1351  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1352  *
1353  * @pipe should be %PIPE_A or %PIPE_B.
1354  *
1355  * Will wait until the pipe has shut down before returning.
1356  */
1357 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1358                                enum pipe pipe)
1359 {
1360         int reg;
1361         u32 val;
1362
1363         /*
1364          * Make sure planes won't keep trying to pump pixels to us,
1365          * or we might hang the display.
1366          */
1367         assert_planes_disabled(dev_priv, pipe);
1368
1369         /* Don't disable pipe A or pipe A PLLs if needed */
1370         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1371                 return;
1372
1373         reg = PIPECONF(pipe);
1374         val = I915_READ(reg);
1375         if ((val & PIPECONF_ENABLE) == 0)
1376                 return;
1377
1378         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1379         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1380 }
1381
1382 /*
1383  * Plane regs are double buffered, going from enabled->disabled needs a
1384  * trigger in order to latch.  The display address reg provides this.
1385  */
1386 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1387                                       enum plane plane)
1388 {
1389         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1390         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1391 }
1392
1393 /**
1394  * intel_enable_plane - enable a display plane on a given pipe
1395  * @dev_priv: i915 private structure
1396  * @plane: plane to enable
1397  * @pipe: pipe being fed
1398  *
1399  * Enable @plane on @pipe, making sure that @pipe is running first.
1400  */
1401 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1402                                enum plane plane, enum pipe pipe)
1403 {
1404         int reg;
1405         u32 val;
1406
1407         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1408         assert_pipe_enabled(dev_priv, pipe);
1409
1410         reg = DSPCNTR(plane);
1411         val = I915_READ(reg);
1412         if (val & DISPLAY_PLANE_ENABLE)
1413                 return;
1414
1415         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1416         intel_flush_display_plane(dev_priv, plane);
1417         intel_wait_for_vblank(dev_priv->dev, pipe);
1418 }
1419
1420 /**
1421  * intel_disable_plane - disable a display plane
1422  * @dev_priv: i915 private structure
1423  * @plane: plane to disable
1424  * @pipe: pipe consuming the data
1425  *
1426  * Disable @plane; should be an independent operation.
1427  */
1428 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1429                                 enum plane plane, enum pipe pipe)
1430 {
1431         int reg;
1432         u32 val;
1433
1434         reg = DSPCNTR(plane);
1435         val = I915_READ(reg);
1436         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1437                 return;
1438
1439         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1440         intel_flush_display_plane(dev_priv, plane);
1441         intel_wait_for_vblank(dev_priv->dev, pipe);
1442 }
1443
1444 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1445                            enum pipe pipe, int reg, u32 port_sel)
1446 {
1447         u32 val = I915_READ(reg);
1448         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1449                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1450                 I915_WRITE(reg, val & ~DP_PORT_EN);
1451         }
1452 }
1453
1454 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1455                              enum pipe pipe, int reg)
1456 {
1457         u32 val = I915_READ(reg);
1458         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1459                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1460                               reg, pipe);
1461                 I915_WRITE(reg, val & ~PORT_ENABLE);
1462         }
1463 }
1464
1465 /* Disable any ports connected to this transcoder */
1466 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1467                                     enum pipe pipe)
1468 {
1469         u32 reg, val;
1470
1471         val = I915_READ(PCH_PP_CONTROL);
1472         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1473
1474         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         reg = PCH_ADPA;
1479         val = I915_READ(reg);
1480         if (adpa_pipe_enabled(dev_priv, pipe, val))
1481                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1482
1483         reg = PCH_LVDS;
1484         val = I915_READ(reg);
1485         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1486                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1487                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1488                 POSTING_READ(reg);
1489                 udelay(100);
1490         }
1491
1492         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1493         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1494         disable_pch_hdmi(dev_priv, pipe, HDMID);
1495 }
1496
1497 static void i8xx_disable_fbc(struct drm_device *dev)
1498 {
1499         struct drm_i915_private *dev_priv = dev->dev_private;
1500         u32 fbc_ctl;
1501
1502         /* Disable compression */
1503         fbc_ctl = I915_READ(FBC_CONTROL);
1504         if ((fbc_ctl & FBC_CTL_EN) == 0)
1505                 return;
1506
1507         fbc_ctl &= ~FBC_CTL_EN;
1508         I915_WRITE(FBC_CONTROL, fbc_ctl);
1509
1510         /* Wait for compressing bit to clear */
1511         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1512                 DRM_DEBUG_KMS("FBC idle timed out\n");
1513                 return;
1514         }
1515
1516         DRM_DEBUG_KMS("disabled FBC\n");
1517 }
1518
1519 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1520 {
1521         struct drm_device *dev = crtc->dev;
1522         struct drm_i915_private *dev_priv = dev->dev_private;
1523         struct drm_framebuffer *fb = crtc->fb;
1524         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1525         struct drm_i915_gem_object *obj = intel_fb->obj;
1526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1527         int cfb_pitch;
1528         int plane, i;
1529         u32 fbc_ctl, fbc_ctl2;
1530
1531         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1532         if (fb->pitch < cfb_pitch)
1533                 cfb_pitch = fb->pitch;
1534
1535         /* FBC_CTL wants 64B units */
1536         cfb_pitch = (cfb_pitch / 64) - 1;
1537         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1538
1539         /* Clear old tags */
1540         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1541                 I915_WRITE(FBC_TAG + (i * 4), 0);
1542
1543         /* Set it up... */
1544         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1545         fbc_ctl2 |= plane;
1546         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1547         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1548
1549         /* enable it... */
1550         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1551         if (IS_I945GM(dev))
1552                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1553         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1554         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1555         fbc_ctl |= obj->fence_reg;
1556         I915_WRITE(FBC_CONTROL, fbc_ctl);
1557
1558         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1559                       cfb_pitch, crtc->y, intel_crtc->plane);
1560 }
1561
1562 static bool i8xx_fbc_enabled(struct drm_device *dev)
1563 {
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565
1566         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1567 }
1568
1569 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1570 {
1571         struct drm_device *dev = crtc->dev;
1572         struct drm_i915_private *dev_priv = dev->dev_private;
1573         struct drm_framebuffer *fb = crtc->fb;
1574         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1575         struct drm_i915_gem_object *obj = intel_fb->obj;
1576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1577         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1578         unsigned long stall_watermark = 200;
1579         u32 dpfc_ctl;
1580
1581         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1582         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1583         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1584
1585         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1586                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1587                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1588         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1589
1590         /* enable it... */
1591         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1592
1593         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1594 }
1595
1596 static void g4x_disable_fbc(struct drm_device *dev)
1597 {
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         u32 dpfc_ctl;
1600
1601         /* Disable compression */
1602         dpfc_ctl = I915_READ(DPFC_CONTROL);
1603         if (dpfc_ctl & DPFC_CTL_EN) {
1604                 dpfc_ctl &= ~DPFC_CTL_EN;
1605                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1606
1607                 DRM_DEBUG_KMS("disabled FBC\n");
1608         }
1609 }
1610
1611 static bool g4x_fbc_enabled(struct drm_device *dev)
1612 {
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1616 }
1617
1618 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1619 {
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         u32 blt_ecoskpd;
1622
1623         /* Make sure blitter notifies FBC of writes */
1624         gen6_gt_force_wake_get(dev_priv);
1625         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1626         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1627                 GEN6_BLITTER_LOCK_SHIFT;
1628         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1629         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1630         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1631         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1632                          GEN6_BLITTER_LOCK_SHIFT);
1633         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1634         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1635         gen6_gt_force_wake_put(dev_priv);
1636 }
1637
1638 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1639 {
1640         struct drm_device *dev = crtc->dev;
1641         struct drm_i915_private *dev_priv = dev->dev_private;
1642         struct drm_framebuffer *fb = crtc->fb;
1643         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1644         struct drm_i915_gem_object *obj = intel_fb->obj;
1645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1646         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1647         unsigned long stall_watermark = 200;
1648         u32 dpfc_ctl;
1649
1650         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1651         dpfc_ctl &= DPFC_RESERVED;
1652         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1653         /* Set persistent mode for front-buffer rendering, ala X. */
1654         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1655         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1656         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1657
1658         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1659                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1660                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1661         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1662         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1663         /* enable it... */
1664         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1665
1666         if (IS_GEN6(dev)) {
1667                 I915_WRITE(SNB_DPFC_CTL_SA,
1668                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1669                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1670                 sandybridge_blit_fbc_update(dev);
1671         }
1672
1673         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1674 }
1675
1676 static void ironlake_disable_fbc(struct drm_device *dev)
1677 {
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         u32 dpfc_ctl;
1680
1681         /* Disable compression */
1682         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683         if (dpfc_ctl & DPFC_CTL_EN) {
1684                 dpfc_ctl &= ~DPFC_CTL_EN;
1685                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1686
1687                 DRM_DEBUG_KMS("disabled FBC\n");
1688         }
1689 }
1690
1691 static bool ironlake_fbc_enabled(struct drm_device *dev)
1692 {
1693         struct drm_i915_private *dev_priv = dev->dev_private;
1694
1695         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1696 }
1697
1698 bool intel_fbc_enabled(struct drm_device *dev)
1699 {
1700         struct drm_i915_private *dev_priv = dev->dev_private;
1701
1702         if (!dev_priv->display.fbc_enabled)
1703                 return false;
1704
1705         return dev_priv->display.fbc_enabled(dev);
1706 }
1707
1708 static void intel_fbc_work_fn(struct work_struct *__work)
1709 {
1710         struct intel_fbc_work *work =
1711                 container_of(to_delayed_work(__work),
1712                              struct intel_fbc_work, work);
1713         struct drm_device *dev = work->crtc->dev;
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715
1716         mutex_lock(&dev->struct_mutex);
1717         if (work == dev_priv->fbc_work) {
1718                 /* Double check that we haven't switched fb without cancelling
1719                  * the prior work.
1720                  */
1721                 if (work->crtc->fb == work->fb) {
1722                         dev_priv->display.enable_fbc(work->crtc,
1723                                                      work->interval);
1724
1725                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1726                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1727                         dev_priv->cfb_y = work->crtc->y;
1728                 }
1729
1730                 dev_priv->fbc_work = NULL;
1731         }
1732         mutex_unlock(&dev->struct_mutex);
1733
1734         kfree(work);
1735 }
1736
1737 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1738 {
1739         if (dev_priv->fbc_work == NULL)
1740                 return;
1741
1742         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1743
1744         /* Synchronisation is provided by struct_mutex and checking of
1745          * dev_priv->fbc_work, so we can perform the cancellation
1746          * entirely asynchronously.
1747          */
1748         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1749                 /* tasklet was killed before being run, clean up */
1750                 kfree(dev_priv->fbc_work);
1751
1752         /* Mark the work as no longer wanted so that if it does
1753          * wake-up (because the work was already running and waiting
1754          * for our mutex), it will discover that is no longer
1755          * necessary to run.
1756          */
1757         dev_priv->fbc_work = NULL;
1758 }
1759
1760 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1761 {
1762         struct intel_fbc_work *work;
1763         struct drm_device *dev = crtc->dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765
1766         if (!dev_priv->display.enable_fbc)
1767                 return;
1768
1769         intel_cancel_fbc_work(dev_priv);
1770
1771         work = kzalloc(sizeof *work, GFP_KERNEL);
1772         if (work == NULL) {
1773                 dev_priv->display.enable_fbc(crtc, interval);
1774                 return;
1775         }
1776
1777         work->crtc = crtc;
1778         work->fb = crtc->fb;
1779         work->interval = interval;
1780         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1781
1782         dev_priv->fbc_work = work;
1783
1784         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1785
1786         /* Delay the actual enabling to let pageflipping cease and the
1787          * display to settle before starting the compression. Note that
1788          * this delay also serves a second purpose: it allows for a
1789          * vblank to pass after disabling the FBC before we attempt
1790          * to modify the control registers.
1791          *
1792          * A more complicated solution would involve tracking vblanks
1793          * following the termination of the page-flipping sequence
1794          * and indeed performing the enable as a co-routine and not
1795          * waiting synchronously upon the vblank.
1796          */
1797         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1798 }
1799
1800 void intel_disable_fbc(struct drm_device *dev)
1801 {
1802         struct drm_i915_private *dev_priv = dev->dev_private;
1803
1804         intel_cancel_fbc_work(dev_priv);
1805
1806         if (!dev_priv->display.disable_fbc)
1807                 return;
1808
1809         dev_priv->display.disable_fbc(dev);
1810         dev_priv->cfb_plane = -1;
1811 }
1812
1813 /**
1814  * intel_update_fbc - enable/disable FBC as needed
1815  * @dev: the drm_device
1816  *
1817  * Set up the framebuffer compression hardware at mode set time.  We
1818  * enable it if possible:
1819  *   - plane A only (on pre-965)
1820  *   - no pixel mulitply/line duplication
1821  *   - no alpha buffer discard
1822  *   - no dual wide
1823  *   - framebuffer <= 2048 in width, 1536 in height
1824  *
1825  * We can't assume that any compression will take place (worst case),
1826  * so the compressed buffer has to be the same size as the uncompressed
1827  * one.  It also must reside (along with the line length buffer) in
1828  * stolen memory.
1829  *
1830  * We need to enable/disable FBC on a global basis.
1831  */
1832 static void intel_update_fbc(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         struct drm_crtc *crtc = NULL, *tmp_crtc;
1836         struct intel_crtc *intel_crtc;
1837         struct drm_framebuffer *fb;
1838         struct intel_framebuffer *intel_fb;
1839         struct drm_i915_gem_object *obj;
1840         int enable_fbc;
1841
1842         DRM_DEBUG_KMS("\n");
1843
1844         if (!i915_powersave)
1845                 return;
1846
1847         if (!I915_HAS_FBC(dev))
1848                 return;
1849
1850         /*
1851          * If FBC is already on, we just have to verify that we can
1852          * keep it that way...
1853          * Need to disable if:
1854          *   - more than one pipe is active
1855          *   - changing FBC params (stride, fence, mode)
1856          *   - new fb is too large to fit in compressed buffer
1857          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1858          */
1859         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1860                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1861                         if (crtc) {
1862                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1863                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1864                                 goto out_disable;
1865                         }
1866                         crtc = tmp_crtc;
1867                 }
1868         }
1869
1870         if (!crtc || crtc->fb == NULL) {
1871                 DRM_DEBUG_KMS("no output, disabling\n");
1872                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1873                 goto out_disable;
1874         }
1875
1876         intel_crtc = to_intel_crtc(crtc);
1877         fb = crtc->fb;
1878         intel_fb = to_intel_framebuffer(fb);
1879         obj = intel_fb->obj;
1880
1881         enable_fbc = i915_enable_fbc;
1882         if (enable_fbc < 0) {
1883                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1884                 enable_fbc = 1;
1885                 if (INTEL_INFO(dev)->gen <= 6)
1886                         enable_fbc = 0;
1887         }
1888         if (!enable_fbc) {
1889                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1890                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1891                 goto out_disable;
1892         }
1893         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1894                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1895                               "compression\n");
1896                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1897                 goto out_disable;
1898         }
1899         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1900             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1901                 DRM_DEBUG_KMS("mode incompatible with compression, "
1902                               "disabling\n");
1903                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1904                 goto out_disable;
1905         }
1906         if ((crtc->mode.hdisplay > 2048) ||
1907             (crtc->mode.vdisplay > 1536)) {
1908                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1909                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1910                 goto out_disable;
1911         }
1912         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1913                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1914                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1915                 goto out_disable;
1916         }
1917
1918         /* The use of a CPU fence is mandatory in order to detect writes
1919          * by the CPU to the scanout and trigger updates to the FBC.
1920          */
1921         if (obj->tiling_mode != I915_TILING_X ||
1922             obj->fence_reg == I915_FENCE_REG_NONE) {
1923                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1924                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1925                 goto out_disable;
1926         }
1927
1928         /* If the kernel debugger is active, always disable compression */
1929         if (in_dbg_master())
1930                 goto out_disable;
1931
1932         /* If the scanout has not changed, don't modify the FBC settings.
1933          * Note that we make the fundamental assumption that the fb->obj
1934          * cannot be unpinned (and have its GTT offset and fence revoked)
1935          * without first being decoupled from the scanout and FBC disabled.
1936          */
1937         if (dev_priv->cfb_plane == intel_crtc->plane &&
1938             dev_priv->cfb_fb == fb->base.id &&
1939             dev_priv->cfb_y == crtc->y)
1940                 return;
1941
1942         if (intel_fbc_enabled(dev)) {
1943                 /* We update FBC along two paths, after changing fb/crtc
1944                  * configuration (modeswitching) and after page-flipping
1945                  * finishes. For the latter, we know that not only did
1946                  * we disable the FBC at the start of the page-flip
1947                  * sequence, but also more than one vblank has passed.
1948                  *
1949                  * For the former case of modeswitching, it is possible
1950                  * to switch between two FBC valid configurations
1951                  * instantaneously so we do need to disable the FBC
1952                  * before we can modify its control registers. We also
1953                  * have to wait for the next vblank for that to take
1954                  * effect. However, since we delay enabling FBC we can
1955                  * assume that a vblank has passed since disabling and
1956                  * that we can safely alter the registers in the deferred
1957                  * callback.
1958                  *
1959                  * In the scenario that we go from a valid to invalid
1960                  * and then back to valid FBC configuration we have
1961                  * no strict enforcement that a vblank occurred since
1962                  * disabling the FBC. However, along all current pipe
1963                  * disabling paths we do need to wait for a vblank at
1964                  * some point. And we wait before enabling FBC anyway.
1965                  */
1966                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1967                 intel_disable_fbc(dev);
1968         }
1969
1970         intel_enable_fbc(crtc, 500);
1971         return;
1972
1973 out_disable:
1974         /* Multiple disables should be harmless */
1975         if (intel_fbc_enabled(dev)) {
1976                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1977                 intel_disable_fbc(dev);
1978         }
1979 }
1980
1981 int
1982 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1983                            struct drm_i915_gem_object *obj,
1984                            struct intel_ring_buffer *pipelined)
1985 {
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         u32 alignment;
1988         int ret;
1989
1990         switch (obj->tiling_mode) {
1991         case I915_TILING_NONE:
1992                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1993                         alignment = 128 * 1024;
1994                 else if (INTEL_INFO(dev)->gen >= 4)
1995                         alignment = 4 * 1024;
1996                 else
1997                         alignment = 64 * 1024;
1998                 break;
1999         case I915_TILING_X:
2000                 /* pin() will align the object as required by fence */
2001                 alignment = 0;
2002                 break;
2003         case I915_TILING_Y:
2004                 /* FIXME: Is this true? */
2005                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2006                 return -EINVAL;
2007         default:
2008                 BUG();
2009         }
2010
2011         dev_priv->mm.interruptible = false;
2012         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2013         if (ret)
2014                 goto err_interruptible;
2015
2016         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2017          * fence, whereas 965+ only requires a fence if using
2018          * framebuffer compression.  For simplicity, we always install
2019          * a fence as the cost is not that onerous.
2020          */
2021         if (obj->tiling_mode != I915_TILING_NONE) {
2022                 ret = i915_gem_object_get_fence(obj, pipelined);
2023                 if (ret)
2024                         goto err_unpin;
2025         }
2026
2027         dev_priv->mm.interruptible = true;
2028         return 0;
2029
2030 err_unpin:
2031         i915_gem_object_unpin(obj);
2032 err_interruptible:
2033         dev_priv->mm.interruptible = true;
2034         return ret;
2035 }
2036
2037 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2038                              int x, int y)
2039 {
2040         struct drm_device *dev = crtc->dev;
2041         struct drm_i915_private *dev_priv = dev->dev_private;
2042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2043         struct intel_framebuffer *intel_fb;
2044         struct drm_i915_gem_object *obj;
2045         int plane = intel_crtc->plane;
2046         unsigned long Start, Offset;
2047         u32 dspcntr;
2048         u32 reg;
2049
2050         switch (plane) {
2051         case 0:
2052         case 1:
2053                 break;
2054         default:
2055                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056                 return -EINVAL;
2057         }
2058
2059         intel_fb = to_intel_framebuffer(fb);
2060         obj = intel_fb->obj;
2061
2062         reg = DSPCNTR(plane);
2063         dspcntr = I915_READ(reg);
2064         /* Mask out pixel format bits in case we change it */
2065         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2066         switch (fb->bits_per_pixel) {
2067         case 8:
2068                 dspcntr |= DISPPLANE_8BPP;
2069                 break;
2070         case 16:
2071                 if (fb->depth == 15)
2072                         dspcntr |= DISPPLANE_15_16BPP;
2073                 else
2074                         dspcntr |= DISPPLANE_16BPP;
2075                 break;
2076         case 24:
2077         case 32:
2078                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2079                 break;
2080         default:
2081                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2082                 return -EINVAL;
2083         }
2084         if (INTEL_INFO(dev)->gen >= 4) {
2085                 if (obj->tiling_mode != I915_TILING_NONE)
2086                         dspcntr |= DISPPLANE_TILED;
2087                 else
2088                         dspcntr &= ~DISPPLANE_TILED;
2089         }
2090
2091         I915_WRITE(reg, dspcntr);
2092
2093         Start = obj->gtt_offset;
2094         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2095
2096         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2097                       Start, Offset, x, y, fb->pitch);
2098         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2099         if (INTEL_INFO(dev)->gen >= 4) {
2100                 I915_WRITE(DSPSURF(plane), Start);
2101                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2102                 I915_WRITE(DSPADDR(plane), Offset);
2103         } else
2104                 I915_WRITE(DSPADDR(plane), Start + Offset);
2105         POSTING_READ(reg);
2106
2107         return 0;
2108 }
2109
2110 static int ironlake_update_plane(struct drm_crtc *crtc,
2111                                  struct drm_framebuffer *fb, int x, int y)
2112 {
2113         struct drm_device *dev = crtc->dev;
2114         struct drm_i915_private *dev_priv = dev->dev_private;
2115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2116         struct intel_framebuffer *intel_fb;
2117         struct drm_i915_gem_object *obj;
2118         int plane = intel_crtc->plane;
2119         unsigned long Start, Offset;
2120         u32 dspcntr;
2121         u32 reg;
2122
2123         switch (plane) {
2124         case 0:
2125         case 1:
2126         case 2:
2127                 break;
2128         default:
2129                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2130                 return -EINVAL;
2131         }
2132
2133         intel_fb = to_intel_framebuffer(fb);
2134         obj = intel_fb->obj;
2135
2136         reg = DSPCNTR(plane);
2137         dspcntr = I915_READ(reg);
2138         /* Mask out pixel format bits in case we change it */
2139         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2140         switch (fb->bits_per_pixel) {
2141         case 8:
2142                 dspcntr |= DISPPLANE_8BPP;
2143                 break;
2144         case 16:
2145                 if (fb->depth != 16)
2146                         return -EINVAL;
2147
2148                 dspcntr |= DISPPLANE_16BPP;
2149                 break;
2150         case 24:
2151         case 32:
2152                 if (fb->depth == 24)
2153                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2154                 else if (fb->depth == 30)
2155                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2156                 else
2157                         return -EINVAL;
2158                 break;
2159         default:
2160                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2161                 return -EINVAL;
2162         }
2163
2164         if (obj->tiling_mode != I915_TILING_NONE)
2165                 dspcntr |= DISPPLANE_TILED;
2166         else
2167                 dspcntr &= ~DISPPLANE_TILED;
2168
2169         /* must disable */
2170         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2171
2172         I915_WRITE(reg, dspcntr);
2173
2174         Start = obj->gtt_offset;
2175         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2176
2177         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2178                       Start, Offset, x, y, fb->pitch);
2179         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2180         I915_WRITE(DSPSURF(plane), Start);
2181         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2182         I915_WRITE(DSPADDR(plane), Offset);
2183         POSTING_READ(reg);
2184
2185         return 0;
2186 }
2187
2188 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2189 static int
2190 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2191                            int x, int y, enum mode_set_atomic state)
2192 {
2193         struct drm_device *dev = crtc->dev;
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         int ret;
2196
2197         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2198         if (ret)
2199                 return ret;
2200
2201         intel_update_fbc(dev);
2202         intel_increase_pllclock(crtc);
2203
2204         return 0;
2205 }
2206
2207 static int
2208 intel_finish_fb(struct drm_framebuffer *old_fb)
2209 {
2210         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2211         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212         bool was_interruptible = dev_priv->mm.interruptible;
2213         int ret;
2214
2215         wait_event(dev_priv->pending_flip_queue,
2216                    atomic_read(&dev_priv->mm.wedged) ||
2217                    atomic_read(&obj->pending_flip) == 0);
2218
2219         /* Big Hammer, we also need to ensure that any pending
2220          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2221          * current scanout is retired before unpinning the old
2222          * framebuffer.
2223          *
2224          * This should only fail upon a hung GPU, in which case we
2225          * can safely continue.
2226          */
2227         dev_priv->mm.interruptible = false;
2228         ret = i915_gem_object_finish_gpu(obj);
2229         dev_priv->mm.interruptible = was_interruptible;
2230
2231         return ret;
2232 }
2233
2234 static int
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236                     struct drm_framebuffer *old_fb)
2237 {
2238         struct drm_device *dev = crtc->dev;
2239         struct drm_i915_master_private *master_priv;
2240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241         int ret;
2242
2243         /* no fb bound */
2244         if (!crtc->fb) {
2245                 DRM_ERROR("No FB bound\n");
2246                 return 0;
2247         }
2248
2249         switch (intel_crtc->plane) {
2250         case 0:
2251         case 1:
2252                 break;
2253         case 2:
2254                 if (IS_IVYBRIDGE(dev))
2255                         break;
2256                 /* fall through otherwise */
2257         default:
2258                 DRM_ERROR("no plane for crtc\n");
2259                 return -EINVAL;
2260         }
2261
2262         mutex_lock(&dev->struct_mutex);
2263         ret = intel_pin_and_fence_fb_obj(dev,
2264                                          to_intel_framebuffer(crtc->fb)->obj,
2265                                          NULL);
2266         if (ret != 0) {
2267                 mutex_unlock(&dev->struct_mutex);
2268                 DRM_ERROR("pin & fence failed\n");
2269                 return ret;
2270         }
2271
2272         if (old_fb)
2273                 intel_finish_fb(old_fb);
2274
2275         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2276                                          LEAVE_ATOMIC_MODE_SET);
2277         if (ret) {
2278                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2279                 mutex_unlock(&dev->struct_mutex);
2280                 DRM_ERROR("failed to update base address\n");
2281                 return ret;
2282         }
2283
2284         if (old_fb) {
2285                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2286                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2287         }
2288
2289         mutex_unlock(&dev->struct_mutex);
2290
2291         if (!dev->primary->master)
2292                 return 0;
2293
2294         master_priv = dev->primary->master->driver_priv;
2295         if (!master_priv->sarea_priv)
2296                 return 0;
2297
2298         if (intel_crtc->pipe) {
2299                 master_priv->sarea_priv->pipeB_x = x;
2300                 master_priv->sarea_priv->pipeB_y = y;
2301         } else {
2302                 master_priv->sarea_priv->pipeA_x = x;
2303                 master_priv->sarea_priv->pipeA_y = y;
2304         }
2305
2306         return 0;
2307 }
2308
2309 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2310 {
2311         struct drm_device *dev = crtc->dev;
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         u32 dpa_ctl;
2314
2315         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2316         dpa_ctl = I915_READ(DP_A);
2317         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2318
2319         if (clock < 200000) {
2320                 u32 temp;
2321                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2322                 /* workaround for 160Mhz:
2323                    1) program 0x4600c bits 15:0 = 0x8124
2324                    2) program 0x46010 bit 0 = 1
2325                    3) program 0x46034 bit 24 = 1
2326                    4) program 0x64000 bit 14 = 1
2327                    */
2328                 temp = I915_READ(0x4600c);
2329                 temp &= 0xffff0000;
2330                 I915_WRITE(0x4600c, temp | 0x8124);
2331
2332                 temp = I915_READ(0x46010);
2333                 I915_WRITE(0x46010, temp | 1);
2334
2335                 temp = I915_READ(0x46034);
2336                 I915_WRITE(0x46034, temp | (1 << 24));
2337         } else {
2338                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2339         }
2340         I915_WRITE(DP_A, dpa_ctl);
2341
2342         POSTING_READ(DP_A);
2343         udelay(500);
2344 }
2345
2346 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2347 {
2348         struct drm_device *dev = crtc->dev;
2349         struct drm_i915_private *dev_priv = dev->dev_private;
2350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2351         int pipe = intel_crtc->pipe;
2352         u32 reg, temp;
2353
2354         /* enable normal train */
2355         reg = FDI_TX_CTL(pipe);
2356         temp = I915_READ(reg);
2357         if (IS_IVYBRIDGE(dev)) {
2358                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2359                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2360         } else {
2361                 temp &= ~FDI_LINK_TRAIN_NONE;
2362                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2363         }
2364         I915_WRITE(reg, temp);
2365
2366         reg = FDI_RX_CTL(pipe);
2367         temp = I915_READ(reg);
2368         if (HAS_PCH_CPT(dev)) {
2369                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2370                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2371         } else {
2372                 temp &= ~FDI_LINK_TRAIN_NONE;
2373                 temp |= FDI_LINK_TRAIN_NONE;
2374         }
2375         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2376
2377         /* wait one idle pattern time */
2378         POSTING_READ(reg);
2379         udelay(1000);
2380
2381         /* IVB wants error correction enabled */
2382         if (IS_IVYBRIDGE(dev))
2383                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2384                            FDI_FE_ERRC_ENABLE);
2385 }
2386
2387 /* The FDI link training functions for ILK/Ibexpeak. */
2388 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2389 {
2390         struct drm_device *dev = crtc->dev;
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393         int pipe = intel_crtc->pipe;
2394         int plane = intel_crtc->plane;
2395         u32 reg, temp, tries;
2396
2397         /* FDI needs bits from pipe & plane first */
2398         assert_pipe_enabled(dev_priv, pipe);
2399         assert_plane_enabled(dev_priv, plane);
2400
2401         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2402            for train result */
2403         reg = FDI_RX_IMR(pipe);
2404         temp = I915_READ(reg);
2405         temp &= ~FDI_RX_SYMBOL_LOCK;
2406         temp &= ~FDI_RX_BIT_LOCK;
2407         I915_WRITE(reg, temp);
2408         I915_READ(reg);
2409         udelay(150);
2410
2411         /* enable CPU FDI TX and PCH FDI RX */
2412         reg = FDI_TX_CTL(pipe);
2413         temp = I915_READ(reg);
2414         temp &= ~(7 << 19);
2415         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2416         temp &= ~FDI_LINK_TRAIN_NONE;
2417         temp |= FDI_LINK_TRAIN_PATTERN_1;
2418         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2419
2420         reg = FDI_RX_CTL(pipe);
2421         temp = I915_READ(reg);
2422         temp &= ~FDI_LINK_TRAIN_NONE;
2423         temp |= FDI_LINK_TRAIN_PATTERN_1;
2424         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2425
2426         POSTING_READ(reg);
2427         udelay(150);
2428
2429         /* Ironlake workaround, enable clock pointer after FDI enable*/
2430         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2431         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2432                    FDI_RX_PHASE_SYNC_POINTER_EN);
2433
2434         reg = FDI_RX_IIR(pipe);
2435         for (tries = 0; tries < 5; tries++) {
2436                 temp = I915_READ(reg);
2437                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439                 if ((temp & FDI_RX_BIT_LOCK)) {
2440                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2441                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2442                         break;
2443                 }
2444         }
2445         if (tries == 5)
2446                 DRM_ERROR("FDI train 1 fail!\n");
2447
2448         /* Train 2 */
2449         reg = FDI_TX_CTL(pipe);
2450         temp = I915_READ(reg);
2451         temp &= ~FDI_LINK_TRAIN_NONE;
2452         temp |= FDI_LINK_TRAIN_PATTERN_2;
2453         I915_WRITE(reg, temp);
2454
2455         reg = FDI_RX_CTL(pipe);
2456         temp = I915_READ(reg);
2457         temp &= ~FDI_LINK_TRAIN_NONE;
2458         temp |= FDI_LINK_TRAIN_PATTERN_2;
2459         I915_WRITE(reg, temp);
2460
2461         POSTING_READ(reg);
2462         udelay(150);
2463
2464         reg = FDI_RX_IIR(pipe);
2465         for (tries = 0; tries < 5; tries++) {
2466                 temp = I915_READ(reg);
2467                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468
2469                 if (temp & FDI_RX_SYMBOL_LOCK) {
2470                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2471                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2472                         break;
2473                 }
2474         }
2475         if (tries == 5)
2476                 DRM_ERROR("FDI train 2 fail!\n");
2477
2478         DRM_DEBUG_KMS("FDI train done\n");
2479
2480 }
2481
2482 static const int snb_b_fdi_train_param[] = {
2483         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2484         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2485         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2486         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2487 };
2488
2489 /* The FDI link training functions for SNB/Cougarpoint. */
2490 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2491 {
2492         struct drm_device *dev = crtc->dev;
2493         struct drm_i915_private *dev_priv = dev->dev_private;
2494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2495         int pipe = intel_crtc->pipe;
2496         u32 reg, temp, i;
2497
2498         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2499            for train result */
2500         reg = FDI_RX_IMR(pipe);
2501         temp = I915_READ(reg);
2502         temp &= ~FDI_RX_SYMBOL_LOCK;
2503         temp &= ~FDI_RX_BIT_LOCK;
2504         I915_WRITE(reg, temp);
2505
2506         POSTING_READ(reg);
2507         udelay(150);
2508
2509         /* enable CPU FDI TX and PCH FDI RX */
2510         reg = FDI_TX_CTL(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~(7 << 19);
2513         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2514         temp &= ~FDI_LINK_TRAIN_NONE;
2515         temp |= FDI_LINK_TRAIN_PATTERN_1;
2516         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2517         /* SNB-B */
2518         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2519         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         if (HAS_PCH_CPT(dev)) {
2524                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2525                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2526         } else {
2527                 temp &= ~FDI_LINK_TRAIN_NONE;
2528                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2529         }
2530         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531
2532         POSTING_READ(reg);
2533         udelay(150);
2534
2535         for (i = 0; i < 4; i++) {
2536                 reg = FDI_TX_CTL(pipe);
2537                 temp = I915_READ(reg);
2538                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539                 temp |= snb_b_fdi_train_param[i];
2540                 I915_WRITE(reg, temp);
2541
2542                 POSTING_READ(reg);
2543                 udelay(500);
2544
2545                 reg = FDI_RX_IIR(pipe);
2546                 temp = I915_READ(reg);
2547                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2548
2549                 if (temp & FDI_RX_BIT_LOCK) {
2550                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2551                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2552                         break;
2553                 }
2554         }
2555         if (i == 4)
2556                 DRM_ERROR("FDI train 1 fail!\n");
2557
2558         /* Train 2 */
2559         reg = FDI_TX_CTL(pipe);
2560         temp = I915_READ(reg);
2561         temp &= ~FDI_LINK_TRAIN_NONE;
2562         temp |= FDI_LINK_TRAIN_PATTERN_2;
2563         if (IS_GEN6(dev)) {
2564                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565                 /* SNB-B */
2566                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2567         }
2568         I915_WRITE(reg, temp);
2569
2570         reg = FDI_RX_CTL(pipe);
2571         temp = I915_READ(reg);
2572         if (HAS_PCH_CPT(dev)) {
2573                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2574                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2575         } else {
2576                 temp &= ~FDI_LINK_TRAIN_NONE;
2577                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578         }
2579         I915_WRITE(reg, temp);
2580
2581         POSTING_READ(reg);
2582         udelay(150);
2583
2584         for (i = 0; i < 4; i++) {
2585                 reg = FDI_TX_CTL(pipe);
2586                 temp = I915_READ(reg);
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 temp |= snb_b_fdi_train_param[i];
2589                 I915_WRITE(reg, temp);
2590
2591                 POSTING_READ(reg);
2592                 udelay(500);
2593
2594                 reg = FDI_RX_IIR(pipe);
2595                 temp = I915_READ(reg);
2596                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2597
2598                 if (temp & FDI_RX_SYMBOL_LOCK) {
2599                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2600                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2601                         break;
2602                 }
2603         }
2604         if (i == 4)
2605                 DRM_ERROR("FDI train 2 fail!\n");
2606
2607         DRM_DEBUG_KMS("FDI train done.\n");
2608 }
2609
2610 /* Manual link training for Ivy Bridge A0 parts */
2611 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2612 {
2613         struct drm_device *dev = crtc->dev;
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616         int pipe = intel_crtc->pipe;
2617         u32 reg, temp, i;
2618
2619         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2620            for train result */
2621         reg = FDI_RX_IMR(pipe);
2622         temp = I915_READ(reg);
2623         temp &= ~FDI_RX_SYMBOL_LOCK;
2624         temp &= ~FDI_RX_BIT_LOCK;
2625         I915_WRITE(reg, temp);
2626
2627         POSTING_READ(reg);
2628         udelay(150);
2629
2630         /* enable CPU FDI TX and PCH FDI RX */
2631         reg = FDI_TX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~(7 << 19);
2634         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2635         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2636         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2637         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639         temp |= FDI_COMPOSITE_SYNC;
2640         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~FDI_LINK_TRAIN_AUTO;
2645         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2647         temp |= FDI_COMPOSITE_SYNC;
2648         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2649
2650         POSTING_READ(reg);
2651         udelay(150);
2652
2653         for (i = 0; i < 4; i++) {
2654                 reg = FDI_TX_CTL(pipe);
2655                 temp = I915_READ(reg);
2656                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657                 temp |= snb_b_fdi_train_param[i];
2658                 I915_WRITE(reg, temp);
2659
2660                 POSTING_READ(reg);
2661                 udelay(500);
2662
2663                 reg = FDI_RX_IIR(pipe);
2664                 temp = I915_READ(reg);
2665                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666
2667                 if (temp & FDI_RX_BIT_LOCK ||
2668                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2669                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2670                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2671                         break;
2672                 }
2673         }
2674         if (i == 4)
2675                 DRM_ERROR("FDI train 1 fail!\n");
2676
2677         /* Train 2 */
2678         reg = FDI_TX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2684         I915_WRITE(reg, temp);
2685
2686         reg = FDI_RX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2690         I915_WRITE(reg, temp);
2691
2692         POSTING_READ(reg);
2693         udelay(150);
2694
2695         for (i = 0; i < 4; i++) {
2696                 reg = FDI_TX_CTL(pipe);
2697                 temp = I915_READ(reg);
2698                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699                 temp |= snb_b_fdi_train_param[i];
2700                 I915_WRITE(reg, temp);
2701
2702                 POSTING_READ(reg);
2703                 udelay(500);
2704
2705                 reg = FDI_RX_IIR(pipe);
2706                 temp = I915_READ(reg);
2707                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2708
2709                 if (temp & FDI_RX_SYMBOL_LOCK) {
2710                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2712                         break;
2713                 }
2714         }
2715         if (i == 4)
2716                 DRM_ERROR("FDI train 2 fail!\n");
2717
2718         DRM_DEBUG_KMS("FDI train done.\n");
2719 }
2720
2721 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int pipe = intel_crtc->pipe;
2727         u32 reg, temp;
2728
2729         /* Write the TU size bits so error detection works */
2730         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2731                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2732
2733         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2734         reg = FDI_RX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         temp &= ~((0x7 << 19) | (0x7 << 16));
2737         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2738         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2739         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2740
2741         POSTING_READ(reg);
2742         udelay(200);
2743
2744         /* Switch from Rawclk to PCDclk */
2745         temp = I915_READ(reg);
2746         I915_WRITE(reg, temp | FDI_PCDCLK);
2747
2748         POSTING_READ(reg);
2749         udelay(200);
2750
2751         /* Enable CPU FDI TX PLL, always on for Ironlake */
2752         reg = FDI_TX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2755                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2756
2757                 POSTING_READ(reg);
2758                 udelay(100);
2759         }
2760 }
2761
2762 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2763 {
2764         struct drm_device *dev = crtc->dev;
2765         struct drm_i915_private *dev_priv = dev->dev_private;
2766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2767         int pipe = intel_crtc->pipe;
2768         u32 reg, temp;
2769
2770         /* disable CPU FDI tx and PCH FDI rx */
2771         reg = FDI_TX_CTL(pipe);
2772         temp = I915_READ(reg);
2773         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2774         POSTING_READ(reg);
2775
2776         reg = FDI_RX_CTL(pipe);
2777         temp = I915_READ(reg);
2778         temp &= ~(0x7 << 16);
2779         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2780         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2781
2782         POSTING_READ(reg);
2783         udelay(100);
2784
2785         /* Ironlake workaround, disable clock pointer after downing FDI */
2786         if (HAS_PCH_IBX(dev)) {
2787                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2788                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2789                            I915_READ(FDI_RX_CHICKEN(pipe) &
2790                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2791         }
2792
2793         /* still set train pattern 1 */
2794         reg = FDI_TX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         temp &= ~FDI_LINK_TRAIN_NONE;
2797         temp |= FDI_LINK_TRAIN_PATTERN_1;
2798         I915_WRITE(reg, temp);
2799
2800         reg = FDI_RX_CTL(pipe);
2801         temp = I915_READ(reg);
2802         if (HAS_PCH_CPT(dev)) {
2803                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2804                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2805         } else {
2806                 temp &= ~FDI_LINK_TRAIN_NONE;
2807                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2808         }
2809         /* BPC in FDI rx is consistent with that in PIPECONF */
2810         temp &= ~(0x07 << 16);
2811         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2812         I915_WRITE(reg, temp);
2813
2814         POSTING_READ(reg);
2815         udelay(100);
2816 }
2817
2818 /*
2819  * When we disable a pipe, we need to clear any pending scanline wait events
2820  * to avoid hanging the ring, which we assume we are waiting on.
2821  */
2822 static void intel_clear_scanline_wait(struct drm_device *dev)
2823 {
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         struct intel_ring_buffer *ring;
2826         u32 tmp;
2827
2828         if (IS_GEN2(dev))
2829                 /* Can't break the hang on i8xx */
2830                 return;
2831
2832         ring = LP_RING(dev_priv);
2833         tmp = I915_READ_CTL(ring);
2834         if (tmp & RING_WAIT)
2835                 I915_WRITE_CTL(ring, tmp);
2836 }
2837
2838 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2839 {
2840         struct drm_device *dev = crtc->dev;
2841         struct drm_i915_private *dev_priv = dev->dev_private;
2842         unsigned long flags;
2843         bool pending;
2844
2845         if (atomic_read(&dev_priv->mm.wedged))
2846                 return false;
2847
2848         spin_lock_irqsave(&dev->event_lock, flags);
2849         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2850         spin_unlock_irqrestore(&dev->event_lock, flags);
2851
2852         return pending;
2853 }
2854
2855 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2856 {
2857         struct drm_device *dev = crtc->dev;
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859
2860         if (crtc->fb == NULL)
2861                 return;
2862
2863         wait_event(dev_priv->pending_flip_queue,
2864                    !intel_crtc_has_pending_flip(crtc));
2865
2866         mutex_lock(&dev->struct_mutex);
2867         intel_finish_fb(crtc->fb);
2868         mutex_unlock(&dev->struct_mutex);
2869 }
2870
2871 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2872 {
2873         struct drm_device *dev = crtc->dev;
2874         struct drm_mode_config *mode_config = &dev->mode_config;
2875         struct intel_encoder *encoder;
2876
2877         /*
2878          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2879          * must be driven by its own crtc; no sharing is possible.
2880          */
2881         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2882                 if (encoder->base.crtc != crtc)
2883                         continue;
2884
2885                 switch (encoder->type) {
2886                 case INTEL_OUTPUT_EDP:
2887                         if (!intel_encoder_is_pch_edp(&encoder->base))
2888                                 return false;
2889                         continue;
2890                 }
2891         }
2892
2893         return true;
2894 }
2895
2896 /*
2897  * Enable PCH resources required for PCH ports:
2898  *   - PCH PLLs
2899  *   - FDI training & RX/TX
2900  *   - update transcoder timings
2901  *   - DP transcoding bits
2902  *   - transcoder
2903  */
2904 static void ironlake_pch_enable(struct drm_crtc *crtc)
2905 {
2906         struct drm_device *dev = crtc->dev;
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2909         int pipe = intel_crtc->pipe;
2910         u32 reg, temp, transc_sel;
2911
2912         /* For PCH output, training FDI link */
2913         dev_priv->display.fdi_link_train(crtc);
2914
2915         intel_enable_pch_pll(dev_priv, pipe);
2916
2917         if (HAS_PCH_CPT(dev)) {
2918                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2919                         TRANSC_DPLLB_SEL;
2920
2921                 /* Be sure PCH DPLL SEL is set */
2922                 temp = I915_READ(PCH_DPLL_SEL);
2923                 if (pipe == 0) {
2924                         temp &= ~(TRANSA_DPLLB_SEL);
2925                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2926                 } else if (pipe == 1) {
2927                         temp &= ~(TRANSB_DPLLB_SEL);
2928                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2929                 } else if (pipe == 2) {
2930                         temp &= ~(TRANSC_DPLLB_SEL);
2931                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2932                 }
2933                 I915_WRITE(PCH_DPLL_SEL, temp);
2934         }
2935
2936         /* set transcoder timing, panel must allow it */
2937         assert_panel_unlocked(dev_priv, pipe);
2938         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2939         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2940         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2941
2942         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2943         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2944         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2945
2946         intel_fdi_normal_train(crtc);
2947
2948         /* For PCH DP, enable TRANS_DP_CTL */
2949         if (HAS_PCH_CPT(dev) &&
2950             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2951              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2952                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2953                 reg = TRANS_DP_CTL(pipe);
2954                 temp = I915_READ(reg);
2955                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2956                           TRANS_DP_SYNC_MASK |
2957                           TRANS_DP_BPC_MASK);
2958                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2959                          TRANS_DP_ENH_FRAMING);
2960                 temp |= bpc << 9; /* same format but at 11:9 */
2961
2962                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2963                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2964                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2965                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2966
2967                 switch (intel_trans_dp_port_sel(crtc)) {
2968                 case PCH_DP_B:
2969                         temp |= TRANS_DP_PORT_SEL_B;
2970                         break;
2971                 case PCH_DP_C:
2972                         temp |= TRANS_DP_PORT_SEL_C;
2973                         break;
2974                 case PCH_DP_D:
2975                         temp |= TRANS_DP_PORT_SEL_D;
2976                         break;
2977                 default:
2978                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2979                         temp |= TRANS_DP_PORT_SEL_B;
2980                         break;
2981                 }
2982
2983                 I915_WRITE(reg, temp);
2984         }
2985
2986         intel_enable_transcoder(dev_priv, pipe);
2987 }
2988
2989 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2990 {
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2993         u32 temp;
2994
2995         temp = I915_READ(dslreg);
2996         udelay(500);
2997         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2998                 /* Without this, mode sets may fail silently on FDI */
2999                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3000                 udelay(250);
3001                 I915_WRITE(tc2reg, 0);
3002                 if (wait_for(I915_READ(dslreg) != temp, 5))
3003                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3004         }
3005 }
3006
3007 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3008 {
3009         struct drm_device *dev = crtc->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012         int pipe = intel_crtc->pipe;
3013         int plane = intel_crtc->plane;
3014         u32 temp;
3015         bool is_pch_port;
3016
3017         if (intel_crtc->active)
3018                 return;
3019
3020         intel_crtc->active = true;
3021         intel_update_watermarks(dev);
3022
3023         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3024                 temp = I915_READ(PCH_LVDS);
3025                 if ((temp & LVDS_PORT_EN) == 0)
3026                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3027         }
3028
3029         is_pch_port = intel_crtc_driving_pch(crtc);
3030
3031         if (is_pch_port)
3032                 ironlake_fdi_pll_enable(crtc);
3033         else
3034                 ironlake_fdi_disable(crtc);
3035
3036         /* Enable panel fitting for LVDS */
3037         if (dev_priv->pch_pf_size &&
3038             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3039                 /* Force use of hard-coded filter coefficients
3040                  * as some pre-programmed values are broken,
3041                  * e.g. x201.
3042                  */
3043                 if (IS_IVYBRIDGE(dev))
3044                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3045                                                  PF_PIPE_SEL_IVB(pipe));
3046                 else
3047                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3048                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3049                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3050         }
3051
3052         /*
3053          * On ILK+ LUT must be loaded before the pipe is running but with
3054          * clocks enabled
3055          */
3056         intel_crtc_load_lut(crtc);
3057
3058         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3059         intel_enable_plane(dev_priv, plane, pipe);
3060
3061         if (is_pch_port)
3062                 ironlake_pch_enable(crtc);
3063
3064         mutex_lock(&dev->struct_mutex);
3065         intel_update_fbc(dev);
3066         mutex_unlock(&dev->struct_mutex);
3067
3068         intel_crtc_update_cursor(crtc, true);
3069 }
3070
3071 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3072 {
3073         struct drm_device *dev = crtc->dev;
3074         struct drm_i915_private *dev_priv = dev->dev_private;
3075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076         int pipe = intel_crtc->pipe;
3077         int plane = intel_crtc->plane;
3078         u32 reg, temp;
3079
3080         if (!intel_crtc->active)
3081                 return;
3082
3083         intel_crtc_wait_for_pending_flips(crtc);
3084         drm_vblank_off(dev, pipe);
3085         intel_crtc_update_cursor(crtc, false);
3086
3087         intel_disable_plane(dev_priv, plane, pipe);
3088
3089         if (dev_priv->cfb_plane == plane)
3090                 intel_disable_fbc(dev);
3091
3092         intel_disable_pipe(dev_priv, pipe);
3093
3094         /* Disable PF */
3095         I915_WRITE(PF_CTL(pipe), 0);
3096         I915_WRITE(PF_WIN_SZ(pipe), 0);
3097
3098         ironlake_fdi_disable(crtc);
3099
3100         /* This is a horrible layering violation; we should be doing this in
3101          * the connector/encoder ->prepare instead, but we don't always have
3102          * enough information there about the config to know whether it will
3103          * actually be necessary or just cause undesired flicker.
3104          */
3105         intel_disable_pch_ports(dev_priv, pipe);
3106
3107         intel_disable_transcoder(dev_priv, pipe);
3108
3109         if (HAS_PCH_CPT(dev)) {
3110                 /* disable TRANS_DP_CTL */
3111                 reg = TRANS_DP_CTL(pipe);
3112                 temp = I915_READ(reg);
3113                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3114                 temp |= TRANS_DP_PORT_SEL_NONE;
3115                 I915_WRITE(reg, temp);
3116
3117                 /* disable DPLL_SEL */
3118                 temp = I915_READ(PCH_DPLL_SEL);
3119                 switch (pipe) {
3120                 case 0:
3121                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3122                         break;
3123                 case 1:
3124                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3125                         break;
3126                 case 2:
3127                         /* C shares PLL A or B */
3128                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3129                         break;
3130                 default:
3131                         BUG(); /* wtf */
3132                 }
3133                 I915_WRITE(PCH_DPLL_SEL, temp);
3134         }
3135
3136         /* disable PCH DPLL */
3137         if (!intel_crtc->no_pll)
3138                 intel_disable_pch_pll(dev_priv, pipe);
3139
3140         /* Switch from PCDclk to Rawclk */
3141         reg = FDI_RX_CTL(pipe);
3142         temp = I915_READ(reg);
3143         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3144
3145         /* Disable CPU FDI TX PLL */
3146         reg = FDI_TX_CTL(pipe);
3147         temp = I915_READ(reg);
3148         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(100);
3152
3153         reg = FDI_RX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3156
3157         /* Wait for the clocks to turn off. */
3158         POSTING_READ(reg);
3159         udelay(100);
3160
3161         intel_crtc->active = false;
3162         intel_update_watermarks(dev);
3163
3164         mutex_lock(&dev->struct_mutex);
3165         intel_update_fbc(dev);
3166         intel_clear_scanline_wait(dev);
3167         mutex_unlock(&dev->struct_mutex);
3168 }
3169
3170 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3171 {
3172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173         int pipe = intel_crtc->pipe;
3174         int plane = intel_crtc->plane;
3175
3176         /* XXX: When our outputs are all unaware of DPMS modes other than off
3177          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3178          */
3179         switch (mode) {
3180         case DRM_MODE_DPMS_ON:
3181         case DRM_MODE_DPMS_STANDBY:
3182         case DRM_MODE_DPMS_SUSPEND:
3183                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3184                 ironlake_crtc_enable(crtc);
3185                 break;
3186
3187         case DRM_MODE_DPMS_OFF:
3188                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3189                 ironlake_crtc_disable(crtc);
3190                 break;
3191         }
3192 }
3193
3194 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3195 {
3196         if (!enable && intel_crtc->overlay) {
3197                 struct drm_device *dev = intel_crtc->base.dev;
3198                 struct drm_i915_private *dev_priv = dev->dev_private;
3199
3200                 mutex_lock(&dev->struct_mutex);
3201                 dev_priv->mm.interruptible = false;
3202                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3203                 dev_priv->mm.interruptible = true;
3204                 mutex_unlock(&dev->struct_mutex);
3205         }
3206
3207         /* Let userspace switch the overlay on again. In most cases userspace
3208          * has to recompute where to put it anyway.
3209          */
3210 }
3211
3212 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3213 {
3214         struct drm_device *dev = crtc->dev;
3215         struct drm_i915_private *dev_priv = dev->dev_private;
3216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3217         int pipe = intel_crtc->pipe;
3218         int plane = intel_crtc->plane;
3219
3220         if (intel_crtc->active)
3221                 return;
3222
3223         intel_crtc->active = true;
3224         intel_update_watermarks(dev);
3225
3226         intel_enable_pll(dev_priv, pipe);
3227         intel_enable_pipe(dev_priv, pipe, false);
3228         intel_enable_plane(dev_priv, plane, pipe);
3229
3230         intel_crtc_load_lut(crtc);
3231         intel_update_fbc(dev);
3232
3233         /* Give the overlay scaler a chance to enable if it's on this pipe */
3234         intel_crtc_dpms_overlay(intel_crtc, true);
3235         intel_crtc_update_cursor(crtc, true);
3236 }
3237
3238 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3239 {
3240         struct drm_device *dev = crtc->dev;
3241         struct drm_i915_private *dev_priv = dev->dev_private;
3242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243         int pipe = intel_crtc->pipe;
3244         int plane = intel_crtc->plane;
3245         u32 pctl;
3246
3247         if (!intel_crtc->active)
3248                 return;
3249
3250         /* Give the overlay scaler a chance to disable if it's on this pipe */
3251         intel_crtc_wait_for_pending_flips(crtc);
3252         drm_vblank_off(dev, pipe);
3253         intel_crtc_dpms_overlay(intel_crtc, false);
3254         intel_crtc_update_cursor(crtc, false);
3255
3256         if (dev_priv->cfb_plane == plane)
3257                 intel_disable_fbc(dev);
3258
3259         intel_disable_plane(dev_priv, plane, pipe);
3260         intel_disable_pipe(dev_priv, pipe);
3261
3262         /* Disable pannel fitter if it is on this pipe. */
3263         pctl = I915_READ(PFIT_CONTROL);
3264         if ((pctl & PFIT_ENABLE) &&
3265             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3266                 I915_WRITE(PFIT_CONTROL, 0);
3267
3268         intel_disable_pll(dev_priv, pipe);
3269
3270         intel_crtc->active = false;
3271         intel_update_fbc(dev);
3272         intel_update_watermarks(dev);
3273         intel_clear_scanline_wait(dev);
3274 }
3275
3276 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3277 {
3278         /* XXX: When our outputs are all unaware of DPMS modes other than off
3279          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3280          */
3281         switch (mode) {
3282         case DRM_MODE_DPMS_ON:
3283         case DRM_MODE_DPMS_STANDBY:
3284         case DRM_MODE_DPMS_SUSPEND:
3285                 i9xx_crtc_enable(crtc);
3286                 break;
3287         case DRM_MODE_DPMS_OFF:
3288                 i9xx_crtc_disable(crtc);
3289                 break;
3290         }
3291 }
3292
3293 /**
3294  * Sets the power management mode of the pipe and plane.
3295  */
3296 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3297 {
3298         struct drm_device *dev = crtc->dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         struct drm_i915_master_private *master_priv;
3301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3302         int pipe = intel_crtc->pipe;
3303         bool enabled;
3304
3305         if (intel_crtc->dpms_mode == mode)
3306                 return;
3307
3308         intel_crtc->dpms_mode = mode;
3309
3310         dev_priv->display.dpms(crtc, mode);
3311
3312         if (!dev->primary->master)
3313                 return;
3314
3315         master_priv = dev->primary->master->driver_priv;
3316         if (!master_priv->sarea_priv)
3317                 return;
3318
3319         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3320
3321         switch (pipe) {
3322         case 0:
3323                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3324                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3325                 break;
3326         case 1:
3327                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3328                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3329                 break;
3330         default:
3331                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3332                 break;
3333         }
3334 }
3335
3336 static void intel_crtc_disable(struct drm_crtc *crtc)
3337 {
3338         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3339         struct drm_device *dev = crtc->dev;
3340
3341         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3342
3343         if (crtc->fb) {
3344                 mutex_lock(&dev->struct_mutex);
3345                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3346                 mutex_unlock(&dev->struct_mutex);
3347         }
3348 }
3349
3350 /* Prepare for a mode set.
3351  *
3352  * Note we could be a lot smarter here.  We need to figure out which outputs
3353  * will be enabled, which disabled (in short, how the config will changes)
3354  * and perform the minimum necessary steps to accomplish that, e.g. updating
3355  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3356  * panel fitting is in the proper state, etc.
3357  */
3358 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3359 {
3360         i9xx_crtc_disable(crtc);
3361 }
3362
3363 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3364 {
3365         i9xx_crtc_enable(crtc);
3366 }
3367
3368 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3369 {
3370         ironlake_crtc_disable(crtc);
3371 }
3372
3373 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3374 {
3375         ironlake_crtc_enable(crtc);
3376 }
3377
3378 void intel_encoder_prepare(struct drm_encoder *encoder)
3379 {
3380         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3381         /* lvds has its own version of prepare see intel_lvds_prepare */
3382         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3383 }
3384
3385 void intel_encoder_commit(struct drm_encoder *encoder)
3386 {
3387         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3388         struct drm_device *dev = encoder->dev;
3389         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3390         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3391
3392         /* lvds has its own version of commit see intel_lvds_commit */
3393         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3394
3395         if (HAS_PCH_CPT(dev))
3396                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3397 }
3398
3399 void intel_encoder_destroy(struct drm_encoder *encoder)
3400 {
3401         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3402
3403         drm_encoder_cleanup(encoder);
3404         kfree(intel_encoder);
3405 }
3406
3407 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3408                                   struct drm_display_mode *mode,
3409                                   struct drm_display_mode *adjusted_mode)
3410 {
3411         struct drm_device *dev = crtc->dev;
3412
3413         if (HAS_PCH_SPLIT(dev)) {
3414                 /* FDI link clock is fixed at 2.7G */
3415                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3416                         return false;
3417         }
3418
3419         /* XXX some encoders set the crtcinfo, others don't.
3420          * Obviously we need some form of conflict resolution here...
3421          */
3422         if (adjusted_mode->crtc_htotal == 0)
3423                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3424
3425         return true;
3426 }
3427
3428 static int i945_get_display_clock_speed(struct drm_device *dev)
3429 {
3430         return 400000;
3431 }
3432
3433 static int i915_get_display_clock_speed(struct drm_device *dev)
3434 {
3435         return 333000;
3436 }
3437
3438 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3439 {
3440         return 200000;
3441 }
3442
3443 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3444 {
3445         u16 gcfgc = 0;
3446
3447         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3448
3449         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3450                 return 133000;
3451         else {
3452                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3453                 case GC_DISPLAY_CLOCK_333_MHZ:
3454                         return 333000;
3455                 default:
3456                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3457                         return 190000;
3458                 }
3459         }
3460 }
3461
3462 static int i865_get_display_clock_speed(struct drm_device *dev)
3463 {
3464         return 266000;
3465 }
3466
3467 static int i855_get_display_clock_speed(struct drm_device *dev)
3468 {
3469         u16 hpllcc = 0;
3470         /* Assume that the hardware is in the high speed state.  This
3471          * should be the default.
3472          */
3473         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3474         case GC_CLOCK_133_200:
3475         case GC_CLOCK_100_200:
3476                 return 200000;
3477         case GC_CLOCK_166_250:
3478                 return 250000;
3479         case GC_CLOCK_100_133:
3480                 return 133000;
3481         }
3482
3483         /* Shouldn't happen */
3484         return 0;
3485 }
3486
3487 static int i830_get_display_clock_speed(struct drm_device *dev)
3488 {
3489         return 133000;
3490 }
3491
3492 struct fdi_m_n {
3493         u32        tu;
3494         u32        gmch_m;
3495         u32        gmch_n;
3496         u32        link_m;
3497         u32        link_n;
3498 };
3499
3500 static void
3501 fdi_reduce_ratio(u32 *num, u32 *den)
3502 {
3503         while (*num > 0xffffff || *den > 0xffffff) {
3504                 *num >>= 1;
3505                 *den >>= 1;
3506         }
3507 }
3508
3509 static void
3510 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3511                      int link_clock, struct fdi_m_n *m_n)
3512 {
3513         m_n->tu = 64; /* default size */
3514
3515         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3516         m_n->gmch_m = bits_per_pixel * pixel_clock;
3517         m_n->gmch_n = link_clock * nlanes * 8;
3518         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3519
3520         m_n->link_m = pixel_clock;
3521         m_n->link_n = link_clock;
3522         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3523 }
3524
3525
3526 struct intel_watermark_params {
3527         unsigned long fifo_size;
3528         unsigned long max_wm;
3529         unsigned long default_wm;
3530         unsigned long guard_size;
3531         unsigned long cacheline_size;
3532 };
3533
3534 /* Pineview has different values for various configs */
3535 static const struct intel_watermark_params pineview_display_wm = {
3536         PINEVIEW_DISPLAY_FIFO,
3537         PINEVIEW_MAX_WM,
3538         PINEVIEW_DFT_WM,
3539         PINEVIEW_GUARD_WM,
3540         PINEVIEW_FIFO_LINE_SIZE
3541 };
3542 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3543         PINEVIEW_DISPLAY_FIFO,
3544         PINEVIEW_MAX_WM,
3545         PINEVIEW_DFT_HPLLOFF_WM,
3546         PINEVIEW_GUARD_WM,
3547         PINEVIEW_FIFO_LINE_SIZE
3548 };
3549 static const struct intel_watermark_params pineview_cursor_wm = {
3550         PINEVIEW_CURSOR_FIFO,
3551         PINEVIEW_CURSOR_MAX_WM,
3552         PINEVIEW_CURSOR_DFT_WM,
3553         PINEVIEW_CURSOR_GUARD_WM,
3554         PINEVIEW_FIFO_LINE_SIZE,
3555 };
3556 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3557         PINEVIEW_CURSOR_FIFO,
3558         PINEVIEW_CURSOR_MAX_WM,
3559         PINEVIEW_CURSOR_DFT_WM,
3560         PINEVIEW_CURSOR_GUARD_WM,
3561         PINEVIEW_FIFO_LINE_SIZE
3562 };
3563 static const struct intel_watermark_params g4x_wm_info = {
3564         G4X_FIFO_SIZE,
3565         G4X_MAX_WM,
3566         G4X_MAX_WM,
3567         2,
3568         G4X_FIFO_LINE_SIZE,
3569 };
3570 static const struct intel_watermark_params g4x_cursor_wm_info = {
3571         I965_CURSOR_FIFO,
3572         I965_CURSOR_MAX_WM,
3573         I965_CURSOR_DFT_WM,
3574         2,
3575         G4X_FIFO_LINE_SIZE,
3576 };
3577 static const struct intel_watermark_params i965_cursor_wm_info = {
3578         I965_CURSOR_FIFO,
3579         I965_CURSOR_MAX_WM,
3580         I965_CURSOR_DFT_WM,
3581         2,
3582         I915_FIFO_LINE_SIZE,
3583 };
3584 static const struct intel_watermark_params i945_wm_info = {
3585         I945_FIFO_SIZE,
3586         I915_MAX_WM,
3587         1,
3588         2,
3589         I915_FIFO_LINE_SIZE
3590 };
3591 static const struct intel_watermark_params i915_wm_info = {
3592         I915_FIFO_SIZE,
3593         I915_MAX_WM,
3594         1,
3595         2,
3596         I915_FIFO_LINE_SIZE
3597 };
3598 static const struct intel_watermark_params i855_wm_info = {
3599         I855GM_FIFO_SIZE,
3600         I915_MAX_WM,
3601         1,
3602         2,
3603         I830_FIFO_LINE_SIZE
3604 };
3605 static const struct intel_watermark_params i830_wm_info = {
3606         I830_FIFO_SIZE,
3607         I915_MAX_WM,
3608         1,
3609         2,
3610         I830_FIFO_LINE_SIZE
3611 };
3612
3613 static const struct intel_watermark_params ironlake_display_wm_info = {
3614         ILK_DISPLAY_FIFO,
3615         ILK_DISPLAY_MAXWM,
3616         ILK_DISPLAY_DFTWM,
3617         2,
3618         ILK_FIFO_LINE_SIZE
3619 };
3620 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3621         ILK_CURSOR_FIFO,
3622         ILK_CURSOR_MAXWM,
3623         ILK_CURSOR_DFTWM,
3624         2,
3625         ILK_FIFO_LINE_SIZE
3626 };
3627 static const struct intel_watermark_params ironlake_display_srwm_info = {
3628         ILK_DISPLAY_SR_FIFO,
3629         ILK_DISPLAY_MAX_SRWM,
3630         ILK_DISPLAY_DFT_SRWM,
3631         2,
3632         ILK_FIFO_LINE_SIZE
3633 };
3634 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3635         ILK_CURSOR_SR_FIFO,
3636         ILK_CURSOR_MAX_SRWM,
3637         ILK_CURSOR_DFT_SRWM,
3638         2,
3639         ILK_FIFO_LINE_SIZE
3640 };
3641
3642 static const struct intel_watermark_params sandybridge_display_wm_info = {
3643         SNB_DISPLAY_FIFO,
3644         SNB_DISPLAY_MAXWM,
3645         SNB_DISPLAY_DFTWM,
3646         2,
3647         SNB_FIFO_LINE_SIZE
3648 };
3649 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3650         SNB_CURSOR_FIFO,
3651         SNB_CURSOR_MAXWM,
3652         SNB_CURSOR_DFTWM,
3653         2,
3654         SNB_FIFO_LINE_SIZE
3655 };
3656 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3657         SNB_DISPLAY_SR_FIFO,
3658         SNB_DISPLAY_MAX_SRWM,
3659         SNB_DISPLAY_DFT_SRWM,
3660         2,
3661         SNB_FIFO_LINE_SIZE
3662 };
3663 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3664         SNB_CURSOR_SR_FIFO,
3665         SNB_CURSOR_MAX_SRWM,
3666         SNB_CURSOR_DFT_SRWM,
3667         2,
3668         SNB_FIFO_LINE_SIZE
3669 };
3670
3671
3672 /**
3673  * intel_calculate_wm - calculate watermark level
3674  * @clock_in_khz: pixel clock
3675  * @wm: chip FIFO params
3676  * @pixel_size: display pixel size
3677  * @latency_ns: memory latency for the platform
3678  *
3679  * Calculate the watermark level (the level at which the display plane will
3680  * start fetching from memory again).  Each chip has a different display
3681  * FIFO size and allocation, so the caller needs to figure that out and pass
3682  * in the correct intel_watermark_params structure.
3683  *
3684  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3685  * on the pixel size.  When it reaches the watermark level, it'll start
3686  * fetching FIFO line sized based chunks from memory until the FIFO fills
3687  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3688  * will occur, and a display engine hang could result.
3689  */
3690 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3691                                         const struct intel_watermark_params *wm,
3692                                         int fifo_size,
3693                                         int pixel_size,
3694                                         unsigned long latency_ns)
3695 {
3696         long entries_required, wm_size;
3697
3698         /*
3699          * Note: we need to make sure we don't overflow for various clock &
3700          * latency values.
3701          * clocks go from a few thousand to several hundred thousand.
3702          * latency is usually a few thousand
3703          */
3704         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3705                 1000;
3706         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3707
3708         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3709
3710         wm_size = fifo_size - (entries_required + wm->guard_size);
3711
3712         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3713
3714         /* Don't promote wm_size to unsigned... */
3715         if (wm_size > (long)wm->max_wm)
3716                 wm_size = wm->max_wm;
3717         if (wm_size <= 0)
3718                 wm_size = wm->default_wm;
3719         return wm_size;
3720 }
3721
3722 struct cxsr_latency {
3723         int is_desktop;
3724         int is_ddr3;
3725         unsigned long fsb_freq;
3726         unsigned long mem_freq;
3727         unsigned long display_sr;
3728         unsigned long display_hpll_disable;
3729         unsigned long cursor_sr;
3730         unsigned long cursor_hpll_disable;
3731 };
3732
3733 static const struct cxsr_latency cxsr_latency_table[] = {
3734         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3735         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3736         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3737         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3738         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3739
3740         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3741         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3742         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3743         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3744         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3745
3746         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3747         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3748         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3749         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3750         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3751
3752         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3753         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3754         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3755         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3756         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3757
3758         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3759         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3760         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3761         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3762         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3763
3764         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3765         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3766         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3767         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3768         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3769 };
3770
3771 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3772                                                          int is_ddr3,
3773                                                          int fsb,
3774                                                          int mem)
3775 {
3776         const struct cxsr_latency *latency;
3777         int i;
3778
3779         if (fsb == 0 || mem == 0)
3780                 return NULL;
3781
3782         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3783                 latency = &cxsr_latency_table[i];
3784                 if (is_desktop == latency->is_desktop &&
3785                     is_ddr3 == latency->is_ddr3 &&
3786                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3787                         return latency;
3788         }
3789
3790         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3791
3792         return NULL;
3793 }
3794
3795 static void pineview_disable_cxsr(struct drm_device *dev)
3796 {
3797         struct drm_i915_private *dev_priv = dev->dev_private;
3798
3799         /* deactivate cxsr */
3800         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3801 }
3802
3803 /*
3804  * Latency for FIFO fetches is dependent on several factors:
3805  *   - memory configuration (speed, channels)
3806  *   - chipset
3807  *   - current MCH state
3808  * It can be fairly high in some situations, so here we assume a fairly
3809  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3810  * set this value too high, the FIFO will fetch frequently to stay full)
3811  * and power consumption (set it too low to save power and we might see
3812  * FIFO underruns and display "flicker").
3813  *
3814  * A value of 5us seems to be a good balance; safe for very low end
3815  * platforms but not overly aggressive on lower latency configs.
3816  */
3817 static const int latency_ns = 5000;
3818
3819 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3820 {
3821         struct drm_i915_private *dev_priv = dev->dev_private;
3822         uint32_t dsparb = I915_READ(DSPARB);
3823         int size;
3824
3825         size = dsparb & 0x7f;
3826         if (plane)
3827                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3828
3829         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3830                       plane ? "B" : "A", size);
3831
3832         return size;
3833 }
3834
3835 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3836 {
3837         struct drm_i915_private *dev_priv = dev->dev_private;
3838         uint32_t dsparb = I915_READ(DSPARB);
3839         int size;
3840
3841         size = dsparb & 0x1ff;
3842         if (plane)
3843                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3844         size >>= 1; /* Convert to cachelines */
3845
3846         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3847                       plane ? "B" : "A", size);
3848
3849         return size;
3850 }
3851
3852 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3853 {
3854         struct drm_i915_private *dev_priv = dev->dev_private;
3855         uint32_t dsparb = I915_READ(DSPARB);
3856         int size;
3857
3858         size = dsparb & 0x7f;
3859         size >>= 2; /* Convert to cachelines */
3860
3861         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3862                       plane ? "B" : "A",
3863                       size);
3864
3865         return size;
3866 }
3867
3868 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3869 {
3870         struct drm_i915_private *dev_priv = dev->dev_private;
3871         uint32_t dsparb = I915_READ(DSPARB);
3872         int size;
3873
3874         size = dsparb & 0x7f;
3875         size >>= 1; /* Convert to cachelines */
3876
3877         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3878                       plane ? "B" : "A", size);
3879
3880         return size;
3881 }
3882
3883 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3884 {
3885         struct drm_crtc *crtc, *enabled = NULL;
3886
3887         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3888                 if (crtc->enabled && crtc->fb) {
3889                         if (enabled)
3890                                 return NULL;
3891                         enabled = crtc;
3892                 }
3893         }
3894
3895         return enabled;
3896 }
3897
3898 static void pineview_update_wm(struct drm_device *dev)
3899 {
3900         struct drm_i915_private *dev_priv = dev->dev_private;
3901         struct drm_crtc *crtc;
3902         const struct cxsr_latency *latency;
3903         u32 reg;
3904         unsigned long wm;
3905
3906         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3907                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3908         if (!latency) {
3909                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3910                 pineview_disable_cxsr(dev);
3911                 return;
3912         }
3913
3914         crtc = single_enabled_crtc(dev);
3915         if (crtc) {
3916                 int clock = crtc->mode.clock;
3917                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3918
3919                 /* Display SR */
3920                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3921                                         pineview_display_wm.fifo_size,
3922                                         pixel_size, latency->display_sr);
3923                 reg = I915_READ(DSPFW1);
3924                 reg &= ~DSPFW_SR_MASK;
3925                 reg |= wm << DSPFW_SR_SHIFT;
3926                 I915_WRITE(DSPFW1, reg);
3927                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3928
3929                 /* cursor SR */
3930                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3931                                         pineview_display_wm.fifo_size,
3932                                         pixel_size, latency->cursor_sr);
3933                 reg = I915_READ(DSPFW3);
3934                 reg &= ~DSPFW_CURSOR_SR_MASK;
3935                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3936                 I915_WRITE(DSPFW3, reg);
3937
3938                 /* Display HPLL off SR */
3939                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3940                                         pineview_display_hplloff_wm.fifo_size,
3941                                         pixel_size, latency->display_hpll_disable);
3942                 reg = I915_READ(DSPFW3);
3943                 reg &= ~DSPFW_HPLL_SR_MASK;
3944                 reg |= wm & DSPFW_HPLL_SR_MASK;
3945                 I915_WRITE(DSPFW3, reg);
3946
3947                 /* cursor HPLL off SR */
3948                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3949                                         pineview_display_hplloff_wm.fifo_size,
3950                                         pixel_size, latency->cursor_hpll_disable);
3951                 reg = I915_READ(DSPFW3);
3952                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3953                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3954                 I915_WRITE(DSPFW3, reg);
3955                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3956
3957                 /* activate cxsr */
3958                 I915_WRITE(DSPFW3,
3959                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3960                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3961         } else {
3962                 pineview_disable_cxsr(dev);
3963                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3964         }
3965 }
3966
3967 static bool g4x_compute_wm0(struct drm_device *dev,
3968                             int plane,
3969                             const struct intel_watermark_params *display,
3970                             int display_latency_ns,
3971                             const struct intel_watermark_params *cursor,
3972                             int cursor_latency_ns,
3973                             int *plane_wm,
3974                             int *cursor_wm)
3975 {
3976         struct drm_crtc *crtc;
3977         int htotal, hdisplay, clock, pixel_size;
3978         int line_time_us, line_count;
3979         int entries, tlb_miss;
3980
3981         crtc = intel_get_crtc_for_plane(dev, plane);
3982         if (crtc->fb == NULL || !crtc->enabled) {
3983                 *cursor_wm = cursor->guard_size;
3984                 *plane_wm = display->guard_size;
3985                 return false;
3986         }
3987
3988         htotal = crtc->mode.htotal;
3989         hdisplay = crtc->mode.hdisplay;
3990         clock = crtc->mode.clock;
3991         pixel_size = crtc->fb->bits_per_pixel / 8;
3992
3993         /* Use the small buffer method to calculate plane watermark */
3994         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3995         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3996         if (tlb_miss > 0)
3997                 entries += tlb_miss;
3998         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3999         *plane_wm = entries + display->guard_size;
4000         if (*plane_wm > (int)display->max_wm)
4001                 *plane_wm = display->max_wm;
4002
4003         /* Use the large buffer method to calculate cursor watermark */
4004         line_time_us = ((htotal * 1000) / clock);
4005         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4006         entries = line_count * 64 * pixel_size;
4007         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4008         if (tlb_miss > 0)
4009                 entries += tlb_miss;
4010         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4011         *cursor_wm = entries + cursor->guard_size;
4012         if (*cursor_wm > (int)cursor->max_wm)
4013                 *cursor_wm = (int)cursor->max_wm;
4014
4015         return true;
4016 }
4017
4018 /*
4019  * Check the wm result.
4020  *
4021  * If any calculated watermark values is larger than the maximum value that
4022  * can be programmed into the associated watermark register, that watermark
4023  * must be disabled.
4024  */
4025 static bool g4x_check_srwm(struct drm_device *dev,
4026                            int display_wm, int cursor_wm,
4027                            const struct intel_watermark_params *display,
4028                            const struct intel_watermark_params *cursor)
4029 {
4030         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4031                       display_wm, cursor_wm);
4032
4033         if (display_wm > display->max_wm) {
4034                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4035                               display_wm, display->max_wm);
4036                 return false;
4037         }
4038
4039         if (cursor_wm > cursor->max_wm) {
4040                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4041                               cursor_wm, cursor->max_wm);
4042                 return false;
4043         }
4044
4045         if (!(display_wm || cursor_wm)) {
4046                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4047                 return false;
4048         }
4049
4050         return true;
4051 }
4052
4053 static bool g4x_compute_srwm(struct drm_device *dev,
4054                              int plane,
4055                              int latency_ns,
4056                              const struct intel_watermark_params *display,
4057                              const struct intel_watermark_params *cursor,
4058                              int *display_wm, int *cursor_wm)
4059 {
4060         struct drm_crtc *crtc;
4061         int hdisplay, htotal, pixel_size, clock;
4062         unsigned long line_time_us;
4063         int line_count, line_size;
4064         int small, large;
4065         int entries;
4066
4067         if (!latency_ns) {
4068                 *display_wm = *cursor_wm = 0;
4069                 return false;
4070         }
4071
4072         crtc = intel_get_crtc_for_plane(dev, plane);
4073         hdisplay = crtc->mode.hdisplay;
4074         htotal = crtc->mode.htotal;
4075         clock = crtc->mode.clock;
4076         pixel_size = crtc->fb->bits_per_pixel / 8;
4077
4078         line_time_us = (htotal * 1000) / clock;
4079         line_count = (latency_ns / line_time_us + 1000) / 1000;
4080         line_size = hdisplay * pixel_size;
4081
4082         /* Use the minimum of the small and large buffer method for primary */
4083         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4084         large = line_count * line_size;
4085
4086         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4087         *display_wm = entries + display->guard_size;
4088
4089         /* calculate the self-refresh watermark for display cursor */
4090         entries = line_count * pixel_size * 64;
4091         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4092         *cursor_wm = entries + cursor->guard_size;
4093
4094         return g4x_check_srwm(dev,
4095                               *display_wm, *cursor_wm,
4096                               display, cursor);
4097 }
4098
4099 #define single_plane_enabled(mask) is_power_of_2(mask)
4100
4101 static void g4x_update_wm(struct drm_device *dev)
4102 {
4103         static const int sr_latency_ns = 12000;
4104         struct drm_i915_private *dev_priv = dev->dev_private;
4105         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4106         int plane_sr, cursor_sr;
4107         unsigned int enabled = 0;
4108
4109         if (g4x_compute_wm0(dev, 0,
4110                             &g4x_wm_info, latency_ns,
4111                             &g4x_cursor_wm_info, latency_ns,
4112                             &planea_wm, &cursora_wm))
4113                 enabled |= 1;
4114
4115         if (g4x_compute_wm0(dev, 1,
4116                             &g4x_wm_info, latency_ns,
4117                             &g4x_cursor_wm_info, latency_ns,
4118                             &planeb_wm, &cursorb_wm))
4119                 enabled |= 2;
4120
4121         plane_sr = cursor_sr = 0;
4122         if (single_plane_enabled(enabled) &&
4123             g4x_compute_srwm(dev, ffs(enabled) - 1,
4124                              sr_latency_ns,
4125                              &g4x_wm_info,
4126                              &g4x_cursor_wm_info,
4127                              &plane_sr, &cursor_sr))
4128                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4129         else
4130                 I915_WRITE(FW_BLC_SELF,
4131                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4132
4133         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4134                       planea_wm, cursora_wm,
4135                       planeb_wm, cursorb_wm,
4136                       plane_sr, cursor_sr);
4137
4138         I915_WRITE(DSPFW1,
4139                    (plane_sr << DSPFW_SR_SHIFT) |
4140                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4141                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4142                    planea_wm);
4143         I915_WRITE(DSPFW2,
4144                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4145                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4146         /* HPLL off in SR has some issues on G4x... disable it */
4147         I915_WRITE(DSPFW3,
4148                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4149                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4150 }
4151
4152 static void i965_update_wm(struct drm_device *dev)
4153 {
4154         struct drm_i915_private *dev_priv = dev->dev_private;
4155         struct drm_crtc *crtc;
4156         int srwm = 1;
4157         int cursor_sr = 16;
4158
4159         /* Calc sr entries for one plane configs */
4160         crtc = single_enabled_crtc(dev);
4161         if (crtc) {
4162                 /* self-refresh has much higher latency */
4163                 static const int sr_latency_ns = 12000;
4164                 int clock = crtc->mode.clock;
4165                 int htotal = crtc->mode.htotal;
4166                 int hdisplay = crtc->mode.hdisplay;
4167                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4168                 unsigned long line_time_us;
4169                 int entries;
4170
4171                 line_time_us = ((htotal * 1000) / clock);
4172
4173                 /* Use ns/us then divide to preserve precision */
4174                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4175                         pixel_size * hdisplay;
4176                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4177                 srwm = I965_FIFO_SIZE - entries;
4178                 if (srwm < 0)
4179                         srwm = 1;
4180                 srwm &= 0x1ff;
4181                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4182                               entries, srwm);
4183
4184                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4185                         pixel_size * 64;
4186                 entries = DIV_ROUND_UP(entries,
4187                                           i965_cursor_wm_info.cacheline_size);
4188                 cursor_sr = i965_cursor_wm_info.fifo_size -
4189                         (entries + i965_cursor_wm_info.guard_size);
4190
4191                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4192                         cursor_sr = i965_cursor_wm_info.max_wm;
4193
4194                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4195                               "cursor %d\n", srwm, cursor_sr);
4196
4197                 if (IS_CRESTLINE(dev))
4198                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4199         } else {
4200                 /* Turn off self refresh if both pipes are enabled */
4201                 if (IS_CRESTLINE(dev))
4202                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4203                                    & ~FW_BLC_SELF_EN);
4204         }
4205
4206         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4207                       srwm);
4208
4209         /* 965 has limitations... */
4210         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4211                    (8 << 16) | (8 << 8) | (8 << 0));
4212         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4213         /* update cursor SR watermark */
4214         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4215 }
4216
4217 static void i9xx_update_wm(struct drm_device *dev)
4218 {
4219         struct drm_i915_private *dev_priv = dev->dev_private;
4220         const struct intel_watermark_params *wm_info;
4221         uint32_t fwater_lo;
4222         uint32_t fwater_hi;
4223         int cwm, srwm = 1;
4224         int fifo_size;
4225         int planea_wm, planeb_wm;
4226         struct drm_crtc *crtc, *enabled = NULL;
4227
4228         if (IS_I945GM(dev))
4229                 wm_info = &i945_wm_info;
4230         else if (!IS_GEN2(dev))
4231                 wm_info = &i915_wm_info;
4232         else
4233                 wm_info = &i855_wm_info;
4234
4235         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4236         crtc = intel_get_crtc_for_plane(dev, 0);
4237         if (crtc->enabled && crtc->fb) {
4238                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4239                                                wm_info, fifo_size,
4240                                                crtc->fb->bits_per_pixel / 8,
4241                                                latency_ns);
4242                 enabled = crtc;
4243         } else
4244                 planea_wm = fifo_size - wm_info->guard_size;
4245
4246         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4247         crtc = intel_get_crtc_for_plane(dev, 1);
4248         if (crtc->enabled && crtc->fb) {
4249                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4250                                                wm_info, fifo_size,
4251                                                crtc->fb->bits_per_pixel / 8,
4252                                                latency_ns);
4253                 if (enabled == NULL)
4254                         enabled = crtc;
4255                 else
4256                         enabled = NULL;
4257         } else
4258                 planeb_wm = fifo_size - wm_info->guard_size;
4259
4260         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4261
4262         /*
4263          * Overlay gets an aggressive default since video jitter is bad.
4264          */
4265         cwm = 2;
4266
4267         /* Play safe and disable self-refresh before adjusting watermarks. */
4268         if (IS_I945G(dev) || IS_I945GM(dev))
4269                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4270         else if (IS_I915GM(dev))
4271                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4272
4273         /* Calc sr entries for one plane configs */
4274         if (HAS_FW_BLC(dev) && enabled) {
4275                 /* self-refresh has much higher latency */
4276                 static const int sr_latency_ns = 6000;
4277                 int clock = enabled->mode.clock;
4278                 int htotal = enabled->mode.htotal;
4279                 int hdisplay = enabled->mode.hdisplay;
4280                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4281                 unsigned long line_time_us;
4282                 int entries;
4283
4284                 line_time_us = (htotal * 1000) / clock;
4285
4286                 /* Use ns/us then divide to preserve precision */
4287                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4288                         pixel_size * hdisplay;
4289                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4290                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4291                 srwm = wm_info->fifo_size - entries;
4292                 if (srwm < 0)
4293                         srwm = 1;
4294
4295                 if (IS_I945G(dev) || IS_I945GM(dev))
4296                         I915_WRITE(FW_BLC_SELF,
4297                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4298                 else if (IS_I915GM(dev))
4299                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4300         }
4301
4302         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4303                       planea_wm, planeb_wm, cwm, srwm);
4304
4305         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4306         fwater_hi = (cwm & 0x1f);
4307
4308         /* Set request length to 8 cachelines per fetch */
4309         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4310         fwater_hi = fwater_hi | (1 << 8);
4311
4312         I915_WRITE(FW_BLC, fwater_lo);
4313         I915_WRITE(FW_BLC2, fwater_hi);
4314
4315         if (HAS_FW_BLC(dev)) {
4316                 if (enabled) {
4317                         if (IS_I945G(dev) || IS_I945GM(dev))
4318                                 I915_WRITE(FW_BLC_SELF,
4319                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4320                         else if (IS_I915GM(dev))
4321                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4322                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4323                 } else
4324                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4325         }
4326 }
4327
4328 static void i830_update_wm(struct drm_device *dev)
4329 {
4330         struct drm_i915_private *dev_priv = dev->dev_private;
4331         struct drm_crtc *crtc;
4332         uint32_t fwater_lo;
4333         int planea_wm;
4334
4335         crtc = single_enabled_crtc(dev);
4336         if (crtc == NULL)
4337                 return;
4338
4339         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4340                                        dev_priv->display.get_fifo_size(dev, 0),
4341                                        crtc->fb->bits_per_pixel / 8,
4342                                        latency_ns);
4343         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4344         fwater_lo |= (3<<8) | planea_wm;
4345
4346         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4347
4348         I915_WRITE(FW_BLC, fwater_lo);
4349 }
4350
4351 #define ILK_LP0_PLANE_LATENCY           700
4352 #define ILK_LP0_CURSOR_LATENCY          1300
4353
4354 /*
4355  * Check the wm result.
4356  *
4357  * If any calculated watermark values is larger than the maximum value that
4358  * can be programmed into the associated watermark register, that watermark
4359  * must be disabled.
4360  */
4361 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4362                                 int fbc_wm, int display_wm, int cursor_wm,
4363                                 const struct intel_watermark_params *display,
4364                                 const struct intel_watermark_params *cursor)
4365 {
4366         struct drm_i915_private *dev_priv = dev->dev_private;
4367
4368         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4369                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4370
4371         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4372                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4373                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4374
4375                 /* fbc has it's own way to disable FBC WM */
4376                 I915_WRITE(DISP_ARB_CTL,
4377                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4378                 return false;
4379         }
4380
4381         if (display_wm > display->max_wm) {
4382                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4383                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4384                 return false;
4385         }
4386
4387         if (cursor_wm > cursor->max_wm) {
4388                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4389                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4390                 return false;
4391         }
4392
4393         if (!(fbc_wm || display_wm || cursor_wm)) {
4394                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4395                 return false;
4396         }
4397
4398         return true;
4399 }
4400
4401 /*
4402  * Compute watermark values of WM[1-3],
4403  */
4404 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4405                                   int latency_ns,
4406                                   const struct intel_watermark_params *display,
4407                                   const struct intel_watermark_params *cursor,
4408                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4409 {
4410         struct drm_crtc *crtc;
4411         unsigned long line_time_us;
4412         int hdisplay, htotal, pixel_size, clock;
4413         int line_count, line_size;
4414         int small, large;
4415         int entries;
4416
4417         if (!latency_ns) {
4418                 *fbc_wm = *display_wm = *cursor_wm = 0;
4419                 return false;
4420         }
4421
4422         crtc = intel_get_crtc_for_plane(dev, plane);
4423         hdisplay = crtc->mode.hdisplay;
4424         htotal = crtc->mode.htotal;
4425         clock = crtc->mode.clock;
4426         pixel_size = crtc->fb->bits_per_pixel / 8;
4427
4428         line_time_us = (htotal * 1000) / clock;
4429         line_count = (latency_ns / line_time_us + 1000) / 1000;
4430         line_size = hdisplay * pixel_size;
4431
4432         /* Use the minimum of the small and large buffer method for primary */
4433         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4434         large = line_count * line_size;
4435
4436         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4437         *display_wm = entries + display->guard_size;
4438
4439         /*
4440          * Spec says:
4441          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4442          */
4443         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4444
4445         /* calculate the self-refresh watermark for display cursor */
4446         entries = line_count * pixel_size * 64;
4447         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4448         *cursor_wm = entries + cursor->guard_size;
4449
4450         return ironlake_check_srwm(dev, level,
4451                                    *fbc_wm, *display_wm, *cursor_wm,
4452                                    display, cursor);
4453 }
4454
4455 static void ironlake_update_wm(struct drm_device *dev)
4456 {
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458         int fbc_wm, plane_wm, cursor_wm;
4459         unsigned int enabled;
4460
4461         enabled = 0;
4462         if (g4x_compute_wm0(dev, 0,
4463                             &ironlake_display_wm_info,
4464                             ILK_LP0_PLANE_LATENCY,
4465                             &ironlake_cursor_wm_info,
4466                             ILK_LP0_CURSOR_LATENCY,
4467                             &plane_wm, &cursor_wm)) {
4468                 I915_WRITE(WM0_PIPEA_ILK,
4469                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4470                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4471                               " plane %d, " "cursor: %d\n",
4472                               plane_wm, cursor_wm);
4473                 enabled |= 1;
4474         }
4475
4476         if (g4x_compute_wm0(dev, 1,
4477                             &ironlake_display_wm_info,
4478                             ILK_LP0_PLANE_LATENCY,
4479                             &ironlake_cursor_wm_info,
4480                             ILK_LP0_CURSOR_LATENCY,
4481                             &plane_wm, &cursor_wm)) {
4482                 I915_WRITE(WM0_PIPEB_ILK,
4483                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4484                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4485                               " plane %d, cursor: %d\n",
4486                               plane_wm, cursor_wm);
4487                 enabled |= 2;
4488         }
4489
4490         /*
4491          * Calculate and update the self-refresh watermark only when one
4492          * display plane is used.
4493          */
4494         I915_WRITE(WM3_LP_ILK, 0);
4495         I915_WRITE(WM2_LP_ILK, 0);
4496         I915_WRITE(WM1_LP_ILK, 0);
4497
4498         if (!single_plane_enabled(enabled))
4499                 return;
4500         enabled = ffs(enabled) - 1;
4501
4502         /* WM1 */
4503         if (!ironlake_compute_srwm(dev, 1, enabled,
4504                                    ILK_READ_WM1_LATENCY() * 500,
4505                                    &ironlake_display_srwm_info,
4506                                    &ironlake_cursor_srwm_info,
4507                                    &fbc_wm, &plane_wm, &cursor_wm))
4508                 return;
4509
4510         I915_WRITE(WM1_LP_ILK,
4511                    WM1_LP_SR_EN |
4512                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4513                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4514                    (plane_wm << WM1_LP_SR_SHIFT) |
4515                    cursor_wm);
4516
4517         /* WM2 */
4518         if (!ironlake_compute_srwm(dev, 2, enabled,
4519                                    ILK_READ_WM2_LATENCY() * 500,
4520                                    &ironlake_display_srwm_info,
4521                                    &ironlake_cursor_srwm_info,
4522                                    &fbc_wm, &plane_wm, &cursor_wm))
4523                 return;
4524
4525         I915_WRITE(WM2_LP_ILK,
4526                    WM2_LP_EN |
4527                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4528                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4529                    (plane_wm << WM1_LP_SR_SHIFT) |
4530                    cursor_wm);
4531
4532         /*
4533          * WM3 is unsupported on ILK, probably because we don't have latency
4534          * data for that power state
4535          */
4536 }
4537
4538 static void sandybridge_update_wm(struct drm_device *dev)
4539 {
4540         struct drm_i915_private *dev_priv = dev->dev_private;
4541         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4542         int fbc_wm, plane_wm, cursor_wm;
4543         unsigned int enabled;
4544
4545         enabled = 0;
4546         if (g4x_compute_wm0(dev, 0,
4547                             &sandybridge_display_wm_info, latency,
4548                             &sandybridge_cursor_wm_info, latency,
4549                             &plane_wm, &cursor_wm)) {
4550                 I915_WRITE(WM0_PIPEA_ILK,
4551                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4552                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4553                               " plane %d, " "cursor: %d\n",
4554                               plane_wm, cursor_wm);
4555                 enabled |= 1;
4556         }
4557
4558         if (g4x_compute_wm0(dev, 1,
4559                             &sandybridge_display_wm_info, latency,
4560                             &sandybridge_cursor_wm_info, latency,
4561                             &plane_wm, &cursor_wm)) {
4562                 I915_WRITE(WM0_PIPEB_ILK,
4563                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4564                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4565                               " plane %d, cursor: %d\n",
4566                               plane_wm, cursor_wm);
4567                 enabled |= 2;
4568         }
4569
4570         /* IVB has 3 pipes */
4571         if (IS_IVYBRIDGE(dev) &&
4572             g4x_compute_wm0(dev, 2,
4573                             &sandybridge_display_wm_info, latency,
4574                             &sandybridge_cursor_wm_info, latency,
4575                             &plane_wm, &cursor_wm)) {
4576                 I915_WRITE(WM0_PIPEC_IVB,
4577                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4578                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4579                               " plane %d, cursor: %d\n",
4580                               plane_wm, cursor_wm);
4581                 enabled |= 3;
4582         }
4583
4584         /*
4585          * Calculate and update the self-refresh watermark only when one
4586          * display plane is used.
4587          *
4588          * SNB support 3 levels of watermark.
4589          *
4590          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4591          * and disabled in the descending order
4592          *
4593          */
4594         I915_WRITE(WM3_LP_ILK, 0);
4595         I915_WRITE(WM2_LP_ILK, 0);
4596         I915_WRITE(WM1_LP_ILK, 0);
4597
4598         if (!single_plane_enabled(enabled))
4599                 return;
4600         enabled = ffs(enabled) - 1;
4601
4602         /* WM1 */
4603         if (!ironlake_compute_srwm(dev, 1, enabled,
4604                                    SNB_READ_WM1_LATENCY() * 500,
4605                                    &sandybridge_display_srwm_info,
4606                                    &sandybridge_cursor_srwm_info,
4607                                    &fbc_wm, &plane_wm, &cursor_wm))
4608                 return;
4609
4610         I915_WRITE(WM1_LP_ILK,
4611                    WM1_LP_SR_EN |
4612                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4613                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4614                    (plane_wm << WM1_LP_SR_SHIFT) |
4615                    cursor_wm);
4616
4617         /* WM2 */
4618         if (!ironlake_compute_srwm(dev, 2, enabled,
4619                                    SNB_READ_WM2_LATENCY() * 500,
4620                                    &sandybridge_display_srwm_info,
4621                                    &sandybridge_cursor_srwm_info,
4622                                    &fbc_wm, &plane_wm, &cursor_wm))
4623                 return;
4624
4625         I915_WRITE(WM2_LP_ILK,
4626                    WM2_LP_EN |
4627                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4628                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4629                    (plane_wm << WM1_LP_SR_SHIFT) |
4630                    cursor_wm);
4631
4632         /* WM3 */
4633         if (!ironlake_compute_srwm(dev, 3, enabled,
4634                                    SNB_READ_WM3_LATENCY() * 500,
4635                                    &sandybridge_display_srwm_info,
4636                                    &sandybridge_cursor_srwm_info,
4637                                    &fbc_wm, &plane_wm, &cursor_wm))
4638                 return;
4639
4640         I915_WRITE(WM3_LP_ILK,
4641                    WM3_LP_EN |
4642                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4643                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4644                    (plane_wm << WM1_LP_SR_SHIFT) |
4645                    cursor_wm);
4646 }
4647
4648 /**
4649  * intel_update_watermarks - update FIFO watermark values based on current modes
4650  *
4651  * Calculate watermark values for the various WM regs based on current mode
4652  * and plane configuration.
4653  *
4654  * There are several cases to deal with here:
4655  *   - normal (i.e. non-self-refresh)
4656  *   - self-refresh (SR) mode
4657  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4658  *   - lines are small relative to FIFO size (buffer can hold more than 2
4659  *     lines), so need to account for TLB latency
4660  *
4661  *   The normal calculation is:
4662  *     watermark = dotclock * bytes per pixel * latency
4663  *   where latency is platform & configuration dependent (we assume pessimal
4664  *   values here).
4665  *
4666  *   The SR calculation is:
4667  *     watermark = (trunc(latency/line time)+1) * surface width *
4668  *       bytes per pixel
4669  *   where
4670  *     line time = htotal / dotclock
4671  *     surface width = hdisplay for normal plane and 64 for cursor
4672  *   and latency is assumed to be high, as above.
4673  *
4674  * The final value programmed to the register should always be rounded up,
4675  * and include an extra 2 entries to account for clock crossings.
4676  *
4677  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4678  * to set the non-SR watermarks to 8.
4679  */
4680 static void intel_update_watermarks(struct drm_device *dev)
4681 {
4682         struct drm_i915_private *dev_priv = dev->dev_private;
4683
4684         if (dev_priv->display.update_wm)
4685                 dev_priv->display.update_wm(dev);
4686 }
4687
4688 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4689 {
4690         if (i915_panel_use_ssc >= 0)
4691                 return i915_panel_use_ssc != 0;
4692         return dev_priv->lvds_use_ssc
4693                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4694 }
4695
4696 /**
4697  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4698  * @crtc: CRTC structure
4699  * @mode: requested mode
4700  *
4701  * A pipe may be connected to one or more outputs.  Based on the depth of the
4702  * attached framebuffer, choose a good color depth to use on the pipe.
4703  *
4704  * If possible, match the pipe depth to the fb depth.  In some cases, this
4705  * isn't ideal, because the connected output supports a lesser or restricted
4706  * set of depths.  Resolve that here:
4707  *    LVDS typically supports only 6bpc, so clamp down in that case
4708  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4709  *    Displays may support a restricted set as well, check EDID and clamp as
4710  *      appropriate.
4711  *    DP may want to dither down to 6bpc to fit larger modes
4712  *
4713  * RETURNS:
4714  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4715  * true if they don't match).
4716  */
4717 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4718                                          unsigned int *pipe_bpp,
4719                                          struct drm_display_mode *mode)
4720 {
4721         struct drm_device *dev = crtc->dev;
4722         struct drm_i915_private *dev_priv = dev->dev_private;
4723         struct drm_encoder *encoder;
4724         struct drm_connector *connector;
4725         unsigned int display_bpc = UINT_MAX, bpc;
4726
4727         /* Walk the encoders & connectors on this crtc, get min bpc */
4728         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4729                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4730
4731                 if (encoder->crtc != crtc)
4732                         continue;
4733
4734                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4735                         unsigned int lvds_bpc;
4736
4737                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4738                             LVDS_A3_POWER_UP)
4739                                 lvds_bpc = 8;
4740                         else
4741                                 lvds_bpc = 6;
4742
4743                         if (lvds_bpc < display_bpc) {
4744                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4745                                 display_bpc = lvds_bpc;
4746                         }
4747                         continue;
4748                 }
4749
4750                 /* Not one of the known troublemakers, check the EDID */
4751                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4752                                     head) {
4753                         if (connector->encoder != encoder)
4754                                 continue;
4755
4756                         /* Don't use an invalid EDID bpc value */
4757                         if (connector->display_info.bpc &&
4758                             connector->display_info.bpc < display_bpc) {
4759                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4760                                 display_bpc = connector->display_info.bpc;
4761                         }
4762                 }
4763
4764                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4765                         /* Use VBT settings if we have an eDP panel */
4766                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4767
4768                         if (edp_bpc && edp_bpc < display_bpc) {
4769                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4770                                 display_bpc = edp_bpc;
4771                         }
4772                         continue;
4773                 }
4774
4775                 /*
4776                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4777                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4778                  */
4779                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4780                         if (display_bpc > 8 && display_bpc < 12) {
4781                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4782                                 display_bpc = 12;
4783                         } else {
4784                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4785                                 display_bpc = 8;
4786                         }
4787                 }
4788         }
4789
4790         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4791                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4792                 display_bpc = 6;
4793         }
4794
4795         /*
4796          * We could just drive the pipe at the highest bpc all the time and
4797          * enable dithering as needed, but that costs bandwidth.  So choose
4798          * the minimum value that expresses the full color range of the fb but
4799          * also stays within the max display bpc discovered above.
4800          */
4801
4802         switch (crtc->fb->depth) {
4803         case 8:
4804                 bpc = 8; /* since we go through a colormap */
4805                 break;
4806         case 15:
4807         case 16:
4808                 bpc = 6; /* min is 18bpp */
4809                 break;
4810         case 24:
4811                 bpc = 8;
4812                 break;
4813         case 30:
4814                 bpc = 10;
4815                 break;
4816         case 48:
4817                 bpc = 12;
4818                 break;
4819         default:
4820                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4821                 bpc = min((unsigned int)8, display_bpc);
4822                 break;
4823         }
4824
4825         display_bpc = min(display_bpc, bpc);
4826
4827         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4828                       bpc, display_bpc);
4829
4830         *pipe_bpp = display_bpc * 3;
4831
4832         return display_bpc != bpc;
4833 }
4834
4835 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4836                               struct drm_display_mode *mode,
4837                               struct drm_display_mode *adjusted_mode,
4838                               int x, int y,
4839                               struct drm_framebuffer *old_fb)
4840 {
4841         struct drm_device *dev = crtc->dev;
4842         struct drm_i915_private *dev_priv = dev->dev_private;
4843         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844         int pipe = intel_crtc->pipe;
4845         int plane = intel_crtc->plane;
4846         int refclk, num_connectors = 0;
4847         intel_clock_t clock, reduced_clock;
4848         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4849         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4850         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4851         struct drm_mode_config *mode_config = &dev->mode_config;
4852         struct intel_encoder *encoder;
4853         const intel_limit_t *limit;
4854         int ret;
4855         u32 temp;
4856         u32 lvds_sync = 0;
4857
4858         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4859                 if (encoder->base.crtc != crtc)
4860                         continue;
4861
4862                 switch (encoder->type) {
4863                 case INTEL_OUTPUT_LVDS:
4864                         is_lvds = true;
4865                         break;
4866                 case INTEL_OUTPUT_SDVO:
4867                 case INTEL_OUTPUT_HDMI:
4868                         is_sdvo = true;
4869                         if (encoder->needs_tv_clock)
4870                                 is_tv = true;
4871                         break;
4872                 case INTEL_OUTPUT_DVO:
4873                         is_dvo = true;
4874                         break;
4875                 case INTEL_OUTPUT_TVOUT:
4876                         is_tv = true;
4877                         break;
4878                 case INTEL_OUTPUT_ANALOG:
4879                         is_crt = true;
4880                         break;
4881                 case INTEL_OUTPUT_DISPLAYPORT:
4882                         is_dp = true;
4883                         break;
4884                 }
4885
4886                 num_connectors++;
4887         }
4888
4889         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4890                 refclk = dev_priv->lvds_ssc_freq * 1000;
4891                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4892                               refclk / 1000);
4893         } else if (!IS_GEN2(dev)) {
4894                 refclk = 96000;
4895         } else {
4896                 refclk = 48000;
4897         }
4898
4899         /*
4900          * Returns a set of divisors for the desired target clock with the given
4901          * refclk, or FALSE.  The returned values represent the clock equation:
4902          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4903          */
4904         limit = intel_limit(crtc, refclk);
4905         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4906         if (!ok) {
4907                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4908                 return -EINVAL;
4909         }
4910
4911         /* Ensure that the cursor is valid for the new mode before changing... */
4912         intel_crtc_update_cursor(crtc, true);
4913
4914         if (is_lvds && dev_priv->lvds_downclock_avail) {
4915                 has_reduced_clock = limit->find_pll(limit, crtc,
4916                                                     dev_priv->lvds_downclock,
4917                                                     refclk,
4918                                                     &reduced_clock);
4919                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4920                         /*
4921                          * If the different P is found, it means that we can't
4922                          * switch the display clock by using the FP0/FP1.
4923                          * In such case we will disable the LVDS downclock
4924                          * feature.
4925                          */
4926                         DRM_DEBUG_KMS("Different P is found for "
4927                                       "LVDS clock/downclock\n");
4928                         has_reduced_clock = 0;
4929                 }
4930         }
4931         /* SDVO TV has fixed PLL values depend on its clock range,
4932            this mirrors vbios setting. */
4933         if (is_sdvo && is_tv) {
4934                 if (adjusted_mode->clock >= 100000
4935                     && adjusted_mode->clock < 140500) {
4936                         clock.p1 = 2;
4937                         clock.p2 = 10;
4938                         clock.n = 3;
4939                         clock.m1 = 16;
4940                         clock.m2 = 8;
4941                 } else if (adjusted_mode->clock >= 140500
4942                            && adjusted_mode->clock <= 200000) {
4943                         clock.p1 = 1;
4944                         clock.p2 = 10;
4945                         clock.n = 6;
4946                         clock.m1 = 12;
4947                         clock.m2 = 8;
4948                 }
4949         }
4950
4951         if (IS_PINEVIEW(dev)) {
4952                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4953                 if (has_reduced_clock)
4954                         fp2 = (1 << reduced_clock.n) << 16 |
4955                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4956         } else {
4957                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4958                 if (has_reduced_clock)
4959                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4960                                 reduced_clock.m2;
4961         }
4962
4963         dpll = DPLL_VGA_MODE_DIS;
4964
4965         if (!IS_GEN2(dev)) {
4966                 if (is_lvds)
4967                         dpll |= DPLLB_MODE_LVDS;
4968                 else
4969                         dpll |= DPLLB_MODE_DAC_SERIAL;
4970                 if (is_sdvo) {
4971                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4972                         if (pixel_multiplier > 1) {
4973                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4974                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4975                         }
4976                         dpll |= DPLL_DVO_HIGH_SPEED;
4977                 }
4978                 if (is_dp)
4979                         dpll |= DPLL_DVO_HIGH_SPEED;
4980
4981                 /* compute bitmask from p1 value */
4982                 if (IS_PINEVIEW(dev))
4983                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4984                 else {
4985                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4986                         if (IS_G4X(dev) && has_reduced_clock)
4987                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4988                 }
4989                 switch (clock.p2) {
4990                 case 5:
4991                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4992                         break;
4993                 case 7:
4994                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4995                         break;
4996                 case 10:
4997                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4998                         break;
4999                 case 14:
5000                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5001                         break;
5002                 }
5003                 if (INTEL_INFO(dev)->gen >= 4)
5004                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5005         } else {
5006                 if (is_lvds) {
5007                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5008                 } else {
5009                         if (clock.p1 == 2)
5010                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5011                         else
5012                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5013                         if (clock.p2 == 4)
5014                                 dpll |= PLL_P2_DIVIDE_BY_4;
5015                 }
5016         }
5017
5018         if (is_sdvo && is_tv)
5019                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5020         else if (is_tv)
5021                 /* XXX: just matching BIOS for now */
5022                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5023                 dpll |= 3;
5024         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5025                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5026         else
5027                 dpll |= PLL_REF_INPUT_DREFCLK;
5028
5029         /* setup pipeconf */
5030         pipeconf = I915_READ(PIPECONF(pipe));
5031
5032         /* Set up the display plane register */
5033         dspcntr = DISPPLANE_GAMMA_ENABLE;
5034
5035         /* Ironlake's plane is forced to pipe, bit 24 is to
5036            enable color space conversion */
5037         if (pipe == 0)
5038                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5039         else
5040                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5041
5042         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5043                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5044                  * core speed.
5045                  *
5046                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5047                  * pipe == 0 check?
5048                  */
5049                 if (mode->clock >
5050                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5051                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5052                 else
5053                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5054         }
5055
5056         /* default to 8bpc */
5057         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5058         if (is_dp) {
5059                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5060                         pipeconf |= PIPECONF_BPP_6 |
5061                                     PIPECONF_DITHER_EN |
5062                                     PIPECONF_DITHER_TYPE_SP;
5063                 }
5064         }
5065
5066         dpll |= DPLL_VCO_ENABLE;
5067
5068         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5069         drm_mode_debug_printmodeline(mode);
5070
5071         I915_WRITE(FP0(pipe), fp);
5072         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5073
5074         POSTING_READ(DPLL(pipe));
5075         udelay(150);
5076
5077         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5078          * This is an exception to the general rule that mode_set doesn't turn
5079          * things on.
5080          */
5081         if (is_lvds) {
5082                 temp = I915_READ(LVDS);
5083                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5084                 if (pipe == 1) {
5085                         temp |= LVDS_PIPEB_SELECT;
5086                 } else {
5087                         temp &= ~LVDS_PIPEB_SELECT;
5088                 }
5089                 /* set the corresponsding LVDS_BORDER bit */
5090                 temp |= dev_priv->lvds_border_bits;
5091                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5092                  * set the DPLLs for dual-channel mode or not.
5093                  */
5094                 if (clock.p2 == 7)
5095                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5096                 else
5097                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5098
5099                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5100                  * appropriately here, but we need to look more thoroughly into how
5101                  * panels behave in the two modes.
5102                  */
5103                 /* set the dithering flag on LVDS as needed */
5104                 if (INTEL_INFO(dev)->gen >= 4) {
5105                         if (dev_priv->lvds_dither)
5106                                 temp |= LVDS_ENABLE_DITHER;
5107                         else
5108                                 temp &= ~LVDS_ENABLE_DITHER;
5109                 }
5110                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5111                         lvds_sync |= LVDS_HSYNC_POLARITY;
5112                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5113                         lvds_sync |= LVDS_VSYNC_POLARITY;
5114                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5115                     != lvds_sync) {
5116                         char flags[2] = "-+";
5117                         DRM_INFO("Changing LVDS panel from "
5118                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5119                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5120                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5121                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5122                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5123                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5124                         temp |= lvds_sync;
5125                 }
5126                 I915_WRITE(LVDS, temp);
5127         }
5128
5129         if (is_dp) {
5130                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5131         }
5132
5133         I915_WRITE(DPLL(pipe), dpll);
5134
5135         /* Wait for the clocks to stabilize. */
5136         POSTING_READ(DPLL(pipe));
5137         udelay(150);
5138
5139         if (INTEL_INFO(dev)->gen >= 4) {
5140                 temp = 0;
5141                 if (is_sdvo) {
5142                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5143                         if (temp > 1)
5144                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5145                         else
5146                                 temp = 0;
5147                 }
5148                 I915_WRITE(DPLL_MD(pipe), temp);
5149         } else {
5150                 /* The pixel multiplier can only be updated once the
5151                  * DPLL is enabled and the clocks are stable.
5152                  *
5153                  * So write it again.
5154                  */
5155                 I915_WRITE(DPLL(pipe), dpll);
5156         }
5157
5158         intel_crtc->lowfreq_avail = false;
5159         if (is_lvds && has_reduced_clock && i915_powersave) {
5160                 I915_WRITE(FP1(pipe), fp2);
5161                 intel_crtc->lowfreq_avail = true;
5162                 if (HAS_PIPE_CXSR(dev)) {
5163                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5164                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5165                 }
5166         } else {
5167                 I915_WRITE(FP1(pipe), fp);
5168                 if (HAS_PIPE_CXSR(dev)) {
5169                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5170                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5171                 }
5172         }
5173
5174         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5175                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5176                 /* the chip adds 2 halflines automatically */
5177                 adjusted_mode->crtc_vdisplay -= 1;
5178                 adjusted_mode->crtc_vtotal -= 1;
5179                 adjusted_mode->crtc_vblank_start -= 1;
5180                 adjusted_mode->crtc_vblank_end -= 1;
5181                 adjusted_mode->crtc_vsync_end -= 1;
5182                 adjusted_mode->crtc_vsync_start -= 1;
5183         } else
5184                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5185
5186         I915_WRITE(HTOTAL(pipe),
5187                    (adjusted_mode->crtc_hdisplay - 1) |
5188                    ((adjusted_mode->crtc_htotal - 1) << 16));
5189         I915_WRITE(HBLANK(pipe),
5190                    (adjusted_mode->crtc_hblank_start - 1) |
5191                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5192         I915_WRITE(HSYNC(pipe),
5193                    (adjusted_mode->crtc_hsync_start - 1) |
5194                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5195
5196         I915_WRITE(VTOTAL(pipe),
5197                    (adjusted_mode->crtc_vdisplay - 1) |
5198                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5199         I915_WRITE(VBLANK(pipe),
5200                    (adjusted_mode->crtc_vblank_start - 1) |
5201                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5202         I915_WRITE(VSYNC(pipe),
5203                    (adjusted_mode->crtc_vsync_start - 1) |
5204                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5205
5206         /* pipesrc and dspsize control the size that is scaled from,
5207          * which should always be the user's requested size.
5208          */
5209         I915_WRITE(DSPSIZE(plane),
5210                    ((mode->vdisplay - 1) << 16) |
5211                    (mode->hdisplay - 1));
5212         I915_WRITE(DSPPOS(plane), 0);
5213         I915_WRITE(PIPESRC(pipe),
5214                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5215
5216         I915_WRITE(PIPECONF(pipe), pipeconf);
5217         POSTING_READ(PIPECONF(pipe));
5218         intel_enable_pipe(dev_priv, pipe, false);
5219
5220         intel_wait_for_vblank(dev, pipe);
5221
5222         I915_WRITE(DSPCNTR(plane), dspcntr);
5223         POSTING_READ(DSPCNTR(plane));
5224         intel_enable_plane(dev_priv, plane, pipe);
5225
5226         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5227
5228         intel_update_watermarks(dev);
5229
5230         return ret;
5231 }
5232
5233 /*
5234  * Initialize reference clocks when the driver loads
5235  */
5236 void ironlake_init_pch_refclk(struct drm_device *dev)
5237 {
5238         struct drm_i915_private *dev_priv = dev->dev_private;
5239         struct drm_mode_config *mode_config = &dev->mode_config;
5240         struct intel_encoder *encoder;
5241         u32 temp;
5242         bool has_lvds = false;
5243         bool has_cpu_edp = false;
5244         bool has_pch_edp = false;
5245         bool has_panel = false;
5246         bool has_ck505 = false;
5247         bool can_ssc = false;
5248
5249         /* We need to take the global config into account */
5250         list_for_each_entry(encoder, &mode_config->encoder_list,
5251                             base.head) {
5252                 switch (encoder->type) {
5253                 case INTEL_OUTPUT_LVDS:
5254                         has_panel = true;
5255                         has_lvds = true;
5256                         break;
5257                 case INTEL_OUTPUT_EDP:
5258                         has_panel = true;
5259                         if (intel_encoder_is_pch_edp(&encoder->base))
5260                                 has_pch_edp = true;
5261                         else
5262                                 has_cpu_edp = true;
5263                         break;
5264                 }
5265         }
5266
5267         if (HAS_PCH_IBX(dev)) {
5268                 has_ck505 = dev_priv->display_clock_mode;
5269                 can_ssc = has_ck505;
5270         } else {
5271                 has_ck505 = false;
5272                 can_ssc = true;
5273         }
5274
5275         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5276                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5277                       has_ck505);
5278
5279         /* Ironlake: try to setup display ref clock before DPLL
5280          * enabling. This is only under driver's control after
5281          * PCH B stepping, previous chipset stepping should be
5282          * ignoring this setting.
5283          */
5284         temp = I915_READ(PCH_DREF_CONTROL);
5285         /* Always enable nonspread source */
5286         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5287
5288         if (has_ck505)
5289                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5290         else
5291                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5292
5293         if (has_panel) {
5294                 temp &= ~DREF_SSC_SOURCE_MASK;
5295                 temp |= DREF_SSC_SOURCE_ENABLE;
5296
5297                 /* SSC must be turned on before enabling the CPU output  */
5298                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5299                         DRM_DEBUG_KMS("Using SSC on panel\n");
5300                         temp |= DREF_SSC1_ENABLE;
5301                 }
5302
5303                 /* Get SSC going before enabling the outputs */
5304                 I915_WRITE(PCH_DREF_CONTROL, temp);
5305                 POSTING_READ(PCH_DREF_CONTROL);
5306                 udelay(200);
5307
5308                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5309
5310                 /* Enable CPU source on CPU attached eDP */
5311                 if (has_cpu_edp) {
5312                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5313                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5314                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5315                         }
5316                         else
5317                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5318                 } else
5319                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5320
5321                 I915_WRITE(PCH_DREF_CONTROL, temp);
5322                 POSTING_READ(PCH_DREF_CONTROL);
5323                 udelay(200);
5324         } else {
5325                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5326
5327                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5328
5329                 /* Turn off CPU output */
5330                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5331
5332                 I915_WRITE(PCH_DREF_CONTROL, temp);
5333                 POSTING_READ(PCH_DREF_CONTROL);
5334                 udelay(200);
5335
5336                 /* Turn off the SSC source */
5337                 temp &= ~DREF_SSC_SOURCE_MASK;
5338                 temp |= DREF_SSC_SOURCE_DISABLE;
5339
5340                 /* Turn off SSC1 */
5341                 temp &= ~ DREF_SSC1_ENABLE;
5342
5343                 I915_WRITE(PCH_DREF_CONTROL, temp);
5344                 POSTING_READ(PCH_DREF_CONTROL);
5345                 udelay(200);
5346         }
5347 }
5348
5349 static int ironlake_get_refclk(struct drm_crtc *crtc)
5350 {
5351         struct drm_device *dev = crtc->dev;
5352         struct drm_i915_private *dev_priv = dev->dev_private;
5353         struct intel_encoder *encoder;
5354         struct drm_mode_config *mode_config = &dev->mode_config;
5355         struct intel_encoder *edp_encoder = NULL;
5356         int num_connectors = 0;
5357         bool is_lvds = false;
5358
5359         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5360                 if (encoder->base.crtc != crtc)
5361                         continue;
5362
5363                 switch (encoder->type) {
5364                 case INTEL_OUTPUT_LVDS:
5365                         is_lvds = true;
5366                         break;
5367                 case INTEL_OUTPUT_EDP:
5368                         edp_encoder = encoder;
5369                         break;
5370                 }
5371                 num_connectors++;
5372         }
5373
5374         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5375                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5376                               dev_priv->lvds_ssc_freq);
5377                 return dev_priv->lvds_ssc_freq * 1000;
5378         }
5379
5380         return 120000;
5381 }
5382
5383 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5384                                   struct drm_display_mode *mode,
5385                                   struct drm_display_mode *adjusted_mode,
5386                                   int x, int y,
5387                                   struct drm_framebuffer *old_fb)
5388 {
5389         struct drm_device *dev = crtc->dev;
5390         struct drm_i915_private *dev_priv = dev->dev_private;
5391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5392         int pipe = intel_crtc->pipe;
5393         int plane = intel_crtc->plane;
5394         int refclk, num_connectors = 0;
5395         intel_clock_t clock, reduced_clock;
5396         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5397         bool ok, has_reduced_clock = false, is_sdvo = false;
5398         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5399         struct intel_encoder *has_edp_encoder = NULL;
5400         struct drm_mode_config *mode_config = &dev->mode_config;
5401         struct intel_encoder *encoder;
5402         const intel_limit_t *limit;
5403         int ret;
5404         struct fdi_m_n m_n = {0};
5405         u32 temp;
5406         u32 lvds_sync = 0;
5407         int target_clock, pixel_multiplier, lane, link_bw, factor;
5408         unsigned int pipe_bpp;
5409         bool dither;
5410
5411         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5412                 if (encoder->base.crtc != crtc)
5413                         continue;
5414
5415                 switch (encoder->type) {
5416                 case INTEL_OUTPUT_LVDS:
5417                         is_lvds = true;
5418                         break;
5419                 case INTEL_OUTPUT_SDVO:
5420                 case INTEL_OUTPUT_HDMI:
5421                         is_sdvo = true;
5422                         if (encoder->needs_tv_clock)
5423                                 is_tv = true;
5424                         break;
5425                 case INTEL_OUTPUT_TVOUT:
5426                         is_tv = true;
5427                         break;
5428                 case INTEL_OUTPUT_ANALOG:
5429                         is_crt = true;
5430                         break;
5431                 case INTEL_OUTPUT_DISPLAYPORT:
5432                         is_dp = true;
5433                         break;
5434                 case INTEL_OUTPUT_EDP:
5435                         has_edp_encoder = encoder;
5436                         break;
5437                 }
5438
5439                 num_connectors++;
5440         }
5441
5442         refclk = ironlake_get_refclk(crtc);
5443
5444         /*
5445          * Returns a set of divisors for the desired target clock with the given
5446          * refclk, or FALSE.  The returned values represent the clock equation:
5447          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5448          */
5449         limit = intel_limit(crtc, refclk);
5450         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5451         if (!ok) {
5452                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5453                 return -EINVAL;
5454         }
5455
5456         /* Ensure that the cursor is valid for the new mode before changing... */
5457         intel_crtc_update_cursor(crtc, true);
5458
5459         if (is_lvds && dev_priv->lvds_downclock_avail) {
5460                 has_reduced_clock = limit->find_pll(limit, crtc,
5461                                                     dev_priv->lvds_downclock,
5462                                                     refclk,
5463                                                     &reduced_clock);
5464                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5465                         /*
5466                          * If the different P is found, it means that we can't
5467                          * switch the display clock by using the FP0/FP1.
5468                          * In such case we will disable the LVDS downclock
5469                          * feature.
5470                          */
5471                         DRM_DEBUG_KMS("Different P is found for "
5472                                       "LVDS clock/downclock\n");
5473                         has_reduced_clock = 0;
5474                 }
5475         }
5476         /* SDVO TV has fixed PLL values depend on its clock range,
5477            this mirrors vbios setting. */
5478         if (is_sdvo && is_tv) {
5479                 if (adjusted_mode->clock >= 100000
5480                     && adjusted_mode->clock < 140500) {
5481                         clock.p1 = 2;
5482                         clock.p2 = 10;
5483                         clock.n = 3;
5484                         clock.m1 = 16;
5485                         clock.m2 = 8;
5486                 } else if (adjusted_mode->clock >= 140500
5487                            && adjusted_mode->clock <= 200000) {
5488                         clock.p1 = 1;
5489                         clock.p2 = 10;
5490                         clock.n = 6;
5491                         clock.m1 = 12;
5492                         clock.m2 = 8;
5493                 }
5494         }
5495
5496         /* FDI link */
5497         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5498         lane = 0;
5499         /* CPU eDP doesn't require FDI link, so just set DP M/N
5500            according to current link config */
5501         if (has_edp_encoder &&
5502             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5503                 target_clock = mode->clock;
5504                 intel_edp_link_config(has_edp_encoder,
5505                                       &lane, &link_bw);
5506         } else {
5507                 /* [e]DP over FDI requires target mode clock
5508                    instead of link clock */
5509                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5510                         target_clock = mode->clock;
5511                 else
5512                         target_clock = adjusted_mode->clock;
5513
5514                 /* FDI is a binary signal running at ~2.7GHz, encoding
5515                  * each output octet as 10 bits. The actual frequency
5516                  * is stored as a divider into a 100MHz clock, and the
5517                  * mode pixel clock is stored in units of 1KHz.
5518                  * Hence the bw of each lane in terms of the mode signal
5519                  * is:
5520                  */
5521                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5522         }
5523
5524         /* determine panel color depth */
5525         temp = I915_READ(PIPECONF(pipe));
5526         temp &= ~PIPE_BPC_MASK;
5527         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, adjusted_mode);
5528         switch (pipe_bpp) {
5529         case 18:
5530                 temp |= PIPE_6BPC;
5531                 break;
5532         case 24:
5533                 temp |= PIPE_8BPC;
5534                 break;
5535         case 30:
5536                 temp |= PIPE_10BPC;
5537                 break;
5538         case 36:
5539                 temp |= PIPE_12BPC;
5540                 break;
5541         default:
5542                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5543                         pipe_bpp);
5544                 temp |= PIPE_8BPC;
5545                 pipe_bpp = 24;
5546                 break;
5547         }
5548
5549         intel_crtc->bpp = pipe_bpp;
5550         I915_WRITE(PIPECONF(pipe), temp);
5551
5552         if (!lane) {
5553                 /*
5554                  * Account for spread spectrum to avoid
5555                  * oversubscribing the link. Max center spread
5556                  * is 2.5%; use 5% for safety's sake.
5557                  */
5558                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5559                 lane = bps / (link_bw * 8) + 1;
5560         }
5561
5562         intel_crtc->fdi_lanes = lane;
5563
5564         if (pixel_multiplier > 1)
5565                 link_bw *= pixel_multiplier;
5566         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5567                              &m_n);
5568
5569         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5570         if (has_reduced_clock)
5571                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5572                         reduced_clock.m2;
5573
5574         /* Enable autotuning of the PLL clock (if permissible) */
5575         factor = 21;
5576         if (is_lvds) {
5577                 if ((intel_panel_use_ssc(dev_priv) &&
5578                      dev_priv->lvds_ssc_freq == 100) ||
5579                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5580                         factor = 25;
5581         } else if (is_sdvo && is_tv)
5582                 factor = 20;
5583
5584         if (clock.m < factor * clock.n)
5585                 fp |= FP_CB_TUNE;
5586
5587         dpll = 0;
5588
5589         if (is_lvds)
5590                 dpll |= DPLLB_MODE_LVDS;
5591         else
5592                 dpll |= DPLLB_MODE_DAC_SERIAL;
5593         if (is_sdvo) {
5594                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5595                 if (pixel_multiplier > 1) {
5596                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5597                 }
5598                 dpll |= DPLL_DVO_HIGH_SPEED;
5599         }
5600         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5601                 dpll |= DPLL_DVO_HIGH_SPEED;
5602
5603         /* compute bitmask from p1 value */
5604         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5605         /* also FPA1 */
5606         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5607
5608         switch (clock.p2) {
5609         case 5:
5610                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5611                 break;
5612         case 7:
5613                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5614                 break;
5615         case 10:
5616                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5617                 break;
5618         case 14:
5619                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5620                 break;
5621         }
5622
5623         if (is_sdvo && is_tv)
5624                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5625         else if (is_tv)
5626                 /* XXX: just matching BIOS for now */
5627                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5628                 dpll |= 3;
5629         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5630                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5631         else
5632                 dpll |= PLL_REF_INPUT_DREFCLK;
5633
5634         /* setup pipeconf */
5635         pipeconf = I915_READ(PIPECONF(pipe));
5636
5637         /* Set up the display plane register */
5638         dspcntr = DISPPLANE_GAMMA_ENABLE;
5639
5640         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5641         drm_mode_debug_printmodeline(mode);
5642
5643         /* PCH eDP needs FDI, but CPU eDP does not */
5644         if (!intel_crtc->no_pll) {
5645                 if (!has_edp_encoder ||
5646                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5647                         I915_WRITE(PCH_FP0(pipe), fp);
5648                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5649
5650                         POSTING_READ(PCH_DPLL(pipe));
5651                         udelay(150);
5652                 }
5653         } else {
5654                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5655                     fp == I915_READ(PCH_FP0(0))) {
5656                         intel_crtc->use_pll_a = true;
5657                         DRM_DEBUG_KMS("using pipe a dpll\n");
5658                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5659                            fp == I915_READ(PCH_FP0(1))) {
5660                         intel_crtc->use_pll_a = false;
5661                         DRM_DEBUG_KMS("using pipe b dpll\n");
5662                 } else {
5663                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5664                         return -EINVAL;
5665                 }
5666         }
5667
5668         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5669          * This is an exception to the general rule that mode_set doesn't turn
5670          * things on.
5671          */
5672         if (is_lvds) {
5673                 temp = I915_READ(PCH_LVDS);
5674                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5675                 if (HAS_PCH_CPT(dev)) {
5676                         temp &= ~PORT_TRANS_SEL_MASK;
5677                         temp |= PORT_TRANS_SEL_CPT(pipe);
5678                 } else {
5679                         if (pipe == 1)
5680                                 temp |= LVDS_PIPEB_SELECT;
5681                         else
5682                                 temp &= ~LVDS_PIPEB_SELECT;
5683                 }
5684
5685                 /* set the corresponsding LVDS_BORDER bit */
5686                 temp |= dev_priv->lvds_border_bits;
5687                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5688                  * set the DPLLs for dual-channel mode or not.
5689                  */
5690                 if (clock.p2 == 7)
5691                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5692                 else
5693                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5694
5695                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5696                  * appropriately here, but we need to look more thoroughly into how
5697                  * panels behave in the two modes.
5698                  */
5699                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5700                         lvds_sync |= LVDS_HSYNC_POLARITY;
5701                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5702                         lvds_sync |= LVDS_VSYNC_POLARITY;
5703                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5704                     != lvds_sync) {
5705                         char flags[2] = "-+";
5706                         DRM_INFO("Changing LVDS panel from "
5707                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5708                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5709                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5710                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5711                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5712                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5713                         temp |= lvds_sync;
5714                 }
5715                 I915_WRITE(PCH_LVDS, temp);
5716         }
5717
5718         pipeconf &= ~PIPECONF_DITHER_EN;
5719         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5720         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5721                 pipeconf |= PIPECONF_DITHER_EN;
5722                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5723         }
5724         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5725                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5726         } else {
5727                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5728                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5729                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5730                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5731                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5732         }
5733
5734         if (!intel_crtc->no_pll &&
5735             (!has_edp_encoder ||
5736              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5737                 I915_WRITE(PCH_DPLL(pipe), dpll);
5738
5739                 /* Wait for the clocks to stabilize. */
5740                 POSTING_READ(PCH_DPLL(pipe));
5741                 udelay(150);
5742
5743                 /* The pixel multiplier can only be updated once the
5744                  * DPLL is enabled and the clocks are stable.
5745                  *
5746                  * So write it again.
5747                  */
5748                 I915_WRITE(PCH_DPLL(pipe), dpll);
5749         }
5750
5751         intel_crtc->lowfreq_avail = false;
5752         if (!intel_crtc->no_pll) {
5753                 if (is_lvds && has_reduced_clock && i915_powersave) {
5754                         I915_WRITE(PCH_FP1(pipe), fp2);
5755                         intel_crtc->lowfreq_avail = true;
5756                         if (HAS_PIPE_CXSR(dev)) {
5757                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5758                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5759                         }
5760                 } else {
5761                         I915_WRITE(PCH_FP1(pipe), fp);
5762                         if (HAS_PIPE_CXSR(dev)) {
5763                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5764                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5765                         }
5766                 }
5767         }
5768
5769         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5770                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5771                 /* the chip adds 2 halflines automatically */
5772                 adjusted_mode->crtc_vdisplay -= 1;
5773                 adjusted_mode->crtc_vtotal -= 1;
5774                 adjusted_mode->crtc_vblank_start -= 1;
5775                 adjusted_mode->crtc_vblank_end -= 1;
5776                 adjusted_mode->crtc_vsync_end -= 1;
5777                 adjusted_mode->crtc_vsync_start -= 1;
5778         } else
5779                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5780
5781         I915_WRITE(HTOTAL(pipe),
5782                    (adjusted_mode->crtc_hdisplay - 1) |
5783                    ((adjusted_mode->crtc_htotal - 1) << 16));
5784         I915_WRITE(HBLANK(pipe),
5785                    (adjusted_mode->crtc_hblank_start - 1) |
5786                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5787         I915_WRITE(HSYNC(pipe),
5788                    (adjusted_mode->crtc_hsync_start - 1) |
5789                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5790
5791         I915_WRITE(VTOTAL(pipe),
5792                    (adjusted_mode->crtc_vdisplay - 1) |
5793                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5794         I915_WRITE(VBLANK(pipe),
5795                    (adjusted_mode->crtc_vblank_start - 1) |
5796                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5797         I915_WRITE(VSYNC(pipe),
5798                    (adjusted_mode->crtc_vsync_start - 1) |
5799                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5800
5801         /* pipesrc controls the size that is scaled from, which should
5802          * always be the user's requested size.
5803          */
5804         I915_WRITE(PIPESRC(pipe),
5805                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5806
5807         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5808         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5809         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5810         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5811
5812         if (has_edp_encoder &&
5813             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5814                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5815         }
5816
5817         I915_WRITE(PIPECONF(pipe), pipeconf);
5818         POSTING_READ(PIPECONF(pipe));
5819
5820         intel_wait_for_vblank(dev, pipe);
5821
5822         if (IS_GEN5(dev)) {
5823                 /* enable address swizzle for tiling buffer */
5824                 temp = I915_READ(DISP_ARB_CTL);
5825                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5826         }
5827
5828         I915_WRITE(DSPCNTR(plane), dspcntr);
5829         POSTING_READ(DSPCNTR(plane));
5830
5831         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5832
5833         intel_update_watermarks(dev);
5834
5835         return ret;
5836 }
5837
5838 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5839                                struct drm_display_mode *mode,
5840                                struct drm_display_mode *adjusted_mode,
5841                                int x, int y,
5842                                struct drm_framebuffer *old_fb)
5843 {
5844         struct drm_device *dev = crtc->dev;
5845         struct drm_i915_private *dev_priv = dev->dev_private;
5846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5847         int pipe = intel_crtc->pipe;
5848         int ret;
5849
5850         drm_vblank_pre_modeset(dev, pipe);
5851
5852         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5853                                               x, y, old_fb);
5854
5855         drm_vblank_post_modeset(dev, pipe);
5856
5857         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5858
5859         return ret;
5860 }
5861
5862 static void g4x_write_eld(struct drm_connector *connector,
5863                           struct drm_crtc *crtc)
5864 {
5865         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5866         uint8_t *eld = connector->eld;
5867         uint32_t eldv;
5868         uint32_t len;
5869         uint32_t i;
5870
5871         i = I915_READ(G4X_AUD_VID_DID);
5872
5873         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5874                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5875         else
5876                 eldv = G4X_ELDV_DEVCTG;
5877
5878         i = I915_READ(G4X_AUD_CNTL_ST);
5879         i &= ~(eldv | G4X_ELD_ADDR);
5880         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5881         I915_WRITE(G4X_AUD_CNTL_ST, i);
5882
5883         if (!eld[0])
5884                 return;
5885
5886         len = min_t(uint8_t, eld[2], len);
5887         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5888         for (i = 0; i < len; i++)
5889                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5890
5891         i = I915_READ(G4X_AUD_CNTL_ST);
5892         i |= eldv;
5893         I915_WRITE(G4X_AUD_CNTL_ST, i);
5894 }
5895
5896 static void ironlake_write_eld(struct drm_connector *connector,
5897                                      struct drm_crtc *crtc)
5898 {
5899         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5900         uint8_t *eld = connector->eld;
5901         uint32_t eldv;
5902         uint32_t i;
5903         int len;
5904         int hdmiw_hdmiedid;
5905         int aud_cntl_st;
5906         int aud_cntrl_st2;
5907
5908         if (HAS_PCH_IBX(connector->dev)) {
5909                 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5910                 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5911                 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5912         } else {
5913                 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5914                 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5915                 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5916         }
5917
5918         i = to_intel_crtc(crtc)->pipe;
5919         hdmiw_hdmiedid += i * 0x100;
5920         aud_cntl_st += i * 0x100;
5921
5922         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5923
5924         i = I915_READ(aud_cntl_st);
5925         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5926         if (!i) {
5927                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5928                 /* operate blindly on all ports */
5929                 eldv = GEN5_ELD_VALIDB;
5930                 eldv |= GEN5_ELD_VALIDB << 4;
5931                 eldv |= GEN5_ELD_VALIDB << 8;
5932         } else {
5933                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5934                 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5935         }
5936
5937         i = I915_READ(aud_cntrl_st2);
5938         i &= ~eldv;
5939         I915_WRITE(aud_cntrl_st2, i);
5940
5941         if (!eld[0])
5942                 return;
5943
5944         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5945                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5946                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5947         }
5948
5949         i = I915_READ(aud_cntl_st);
5950         i &= ~GEN5_ELD_ADDRESS;
5951         I915_WRITE(aud_cntl_st, i);
5952
5953         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5954         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5955         for (i = 0; i < len; i++)
5956                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5957
5958         i = I915_READ(aud_cntrl_st2);
5959         i |= eldv;
5960         I915_WRITE(aud_cntrl_st2, i);
5961 }
5962
5963 void intel_write_eld(struct drm_encoder *encoder,
5964                      struct drm_display_mode *mode)
5965 {
5966         struct drm_crtc *crtc = encoder->crtc;
5967         struct drm_connector *connector;
5968         struct drm_device *dev = encoder->dev;
5969         struct drm_i915_private *dev_priv = dev->dev_private;
5970
5971         connector = drm_select_eld(encoder, mode);
5972         if (!connector)
5973                 return;
5974
5975         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5976                          connector->base.id,
5977                          drm_get_connector_name(connector),
5978                          connector->encoder->base.id,
5979                          drm_get_encoder_name(connector->encoder));
5980
5981         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5982
5983         if (dev_priv->display.write_eld)
5984                 dev_priv->display.write_eld(connector, crtc);
5985 }
5986
5987 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5988 void intel_crtc_load_lut(struct drm_crtc *crtc)
5989 {
5990         struct drm_device *dev = crtc->dev;
5991         struct drm_i915_private *dev_priv = dev->dev_private;
5992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5993         int palreg = PALETTE(intel_crtc->pipe);
5994         int i;
5995
5996         /* The clocks have to be on to load the palette. */
5997         if (!crtc->enabled || !intel_crtc->active)
5998                 return;
5999
6000         /* use legacy palette for Ironlake */
6001         if (HAS_PCH_SPLIT(dev))
6002                 palreg = LGC_PALETTE(intel_crtc->pipe);
6003
6004         for (i = 0; i < 256; i++) {
6005                 I915_WRITE(palreg + 4 * i,
6006                            (intel_crtc->lut_r[i] << 16) |
6007                            (intel_crtc->lut_g[i] << 8) |
6008                            intel_crtc->lut_b[i]);
6009         }
6010 }
6011
6012 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6013 {
6014         struct drm_device *dev = crtc->dev;
6015         struct drm_i915_private *dev_priv = dev->dev_private;
6016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6017         bool visible = base != 0;
6018         u32 cntl;
6019
6020         if (intel_crtc->cursor_visible == visible)
6021                 return;
6022
6023         cntl = I915_READ(_CURACNTR);
6024         if (visible) {
6025                 /* On these chipsets we can only modify the base whilst
6026                  * the cursor is disabled.
6027                  */
6028                 I915_WRITE(_CURABASE, base);
6029
6030                 cntl &= ~(CURSOR_FORMAT_MASK);
6031                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6032                 cntl |= CURSOR_ENABLE |
6033                         CURSOR_GAMMA_ENABLE |
6034                         CURSOR_FORMAT_ARGB;
6035         } else
6036                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6037         I915_WRITE(_CURACNTR, cntl);
6038
6039         intel_crtc->cursor_visible = visible;
6040 }
6041
6042 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6043 {
6044         struct drm_device *dev = crtc->dev;
6045         struct drm_i915_private *dev_priv = dev->dev_private;
6046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6047         int pipe = intel_crtc->pipe;
6048         bool visible = base != 0;
6049
6050         if (intel_crtc->cursor_visible != visible) {
6051                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6052                 if (base) {
6053                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6054                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6055                         cntl |= pipe << 28; /* Connect to correct pipe */
6056                 } else {
6057                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6058                         cntl |= CURSOR_MODE_DISABLE;
6059                 }
6060                 I915_WRITE(CURCNTR(pipe), cntl);
6061
6062                 intel_crtc->cursor_visible = visible;
6063         }
6064         /* and commit changes on next vblank */
6065         I915_WRITE(CURBASE(pipe), base);
6066 }
6067
6068 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6069 {
6070         struct drm_device *dev = crtc->dev;
6071         struct drm_i915_private *dev_priv = dev->dev_private;
6072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6073         int pipe = intel_crtc->pipe;
6074         bool visible = base != 0;
6075
6076         if (intel_crtc->cursor_visible != visible) {
6077                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6078                 if (base) {
6079                         cntl &= ~CURSOR_MODE;
6080                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6081                 } else {
6082                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6083                         cntl |= CURSOR_MODE_DISABLE;
6084                 }
6085                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6086
6087                 intel_crtc->cursor_visible = visible;
6088         }
6089         /* and commit changes on next vblank */
6090         I915_WRITE(CURBASE_IVB(pipe), base);
6091 }
6092
6093 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6094 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6095                                      bool on)
6096 {
6097         struct drm_device *dev = crtc->dev;
6098         struct drm_i915_private *dev_priv = dev->dev_private;
6099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6100         int pipe = intel_crtc->pipe;
6101         int x = intel_crtc->cursor_x;
6102         int y = intel_crtc->cursor_y;
6103         u32 base, pos;
6104         bool visible;
6105
6106         pos = 0;
6107
6108         if (on && crtc->enabled && crtc->fb) {
6109                 base = intel_crtc->cursor_addr;
6110                 if (x > (int) crtc->fb->width)
6111                         base = 0;
6112
6113                 if (y > (int) crtc->fb->height)
6114                         base = 0;
6115         } else
6116                 base = 0;
6117
6118         if (x < 0) {
6119                 if (x + intel_crtc->cursor_width < 0)
6120                         base = 0;
6121
6122                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6123                 x = -x;
6124         }
6125         pos |= x << CURSOR_X_SHIFT;
6126
6127         if (y < 0) {
6128                 if (y + intel_crtc->cursor_height < 0)
6129                         base = 0;
6130
6131                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6132                 y = -y;
6133         }
6134         pos |= y << CURSOR_Y_SHIFT;
6135
6136         visible = base != 0;
6137         if (!visible && !intel_crtc->cursor_visible)
6138                 return;
6139
6140         if (IS_IVYBRIDGE(dev)) {
6141                 I915_WRITE(CURPOS_IVB(pipe), pos);
6142                 ivb_update_cursor(crtc, base);
6143         } else {
6144                 I915_WRITE(CURPOS(pipe), pos);
6145                 if (IS_845G(dev) || IS_I865G(dev))
6146                         i845_update_cursor(crtc, base);
6147                 else
6148                         i9xx_update_cursor(crtc, base);
6149         }
6150
6151         if (visible)
6152                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6153 }
6154
6155 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6156                                  struct drm_file *file,
6157                                  uint32_t handle,
6158                                  uint32_t width, uint32_t height)
6159 {
6160         struct drm_device *dev = crtc->dev;
6161         struct drm_i915_private *dev_priv = dev->dev_private;
6162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163         struct drm_i915_gem_object *obj;
6164         uint32_t addr;
6165         int ret;
6166
6167         DRM_DEBUG_KMS("\n");
6168
6169         /* if we want to turn off the cursor ignore width and height */
6170         if (!handle) {
6171                 DRM_DEBUG_KMS("cursor off\n");
6172                 addr = 0;
6173                 obj = NULL;
6174                 mutex_lock(&dev->struct_mutex);
6175                 goto finish;
6176         }
6177
6178         /* Currently we only support 64x64 cursors */
6179         if (width != 64 || height != 64) {
6180                 DRM_ERROR("we currently only support 64x64 cursors\n");
6181                 return -EINVAL;
6182         }
6183
6184         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6185         if (&obj->base == NULL)
6186                 return -ENOENT;
6187
6188         if (obj->base.size < width * height * 4) {
6189                 DRM_ERROR("buffer is to small\n");
6190                 ret = -ENOMEM;
6191                 goto fail;
6192         }
6193
6194         /* we only need to pin inside GTT if cursor is non-phy */
6195         mutex_lock(&dev->struct_mutex);
6196         if (!dev_priv->info->cursor_needs_physical) {
6197                 if (obj->tiling_mode) {
6198                         DRM_ERROR("cursor cannot be tiled\n");
6199                         ret = -EINVAL;
6200                         goto fail_locked;
6201                 }
6202
6203                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6204                 if (ret) {
6205                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6206                         goto fail_locked;
6207                 }
6208
6209                 ret = i915_gem_object_put_fence(obj);
6210                 if (ret) {
6211                         DRM_ERROR("failed to release fence for cursor");
6212                         goto fail_unpin;
6213                 }
6214
6215                 addr = obj->gtt_offset;
6216         } else {
6217                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6218                 ret = i915_gem_attach_phys_object(dev, obj,
6219                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6220                                                   align);
6221                 if (ret) {
6222                         DRM_ERROR("failed to attach phys object\n");
6223                         goto fail_locked;
6224                 }
6225                 addr = obj->phys_obj->handle->busaddr;
6226         }
6227
6228         if (IS_GEN2(dev))
6229                 I915_WRITE(CURSIZE, (height << 12) | width);
6230
6231  finish:
6232         if (intel_crtc->cursor_bo) {
6233                 if (dev_priv->info->cursor_needs_physical) {
6234                         if (intel_crtc->cursor_bo != obj)
6235                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6236                 } else
6237                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6238                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6239         }
6240
6241         mutex_unlock(&dev->struct_mutex);
6242
6243         intel_crtc->cursor_addr = addr;
6244         intel_crtc->cursor_bo = obj;
6245         intel_crtc->cursor_width = width;
6246         intel_crtc->cursor_height = height;
6247
6248         intel_crtc_update_cursor(crtc, true);
6249
6250         return 0;
6251 fail_unpin:
6252         i915_gem_object_unpin(obj);
6253 fail_locked:
6254         mutex_unlock(&dev->struct_mutex);
6255 fail:
6256         drm_gem_object_unreference_unlocked(&obj->base);
6257         return ret;
6258 }
6259
6260 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6261 {
6262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6263
6264         intel_crtc->cursor_x = x;
6265         intel_crtc->cursor_y = y;
6266
6267         intel_crtc_update_cursor(crtc, true);
6268
6269         return 0;
6270 }
6271
6272 /** Sets the color ramps on behalf of RandR */
6273 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6274                                  u16 blue, int regno)
6275 {
6276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6277
6278         intel_crtc->lut_r[regno] = red >> 8;
6279         intel_crtc->lut_g[regno] = green >> 8;
6280         intel_crtc->lut_b[regno] = blue >> 8;
6281 }
6282
6283 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6284                              u16 *blue, int regno)
6285 {
6286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6287
6288         *red = intel_crtc->lut_r[regno] << 8;
6289         *green = intel_crtc->lut_g[regno] << 8;
6290         *blue = intel_crtc->lut_b[regno] << 8;
6291 }
6292
6293 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6294                                  u16 *blue, uint32_t start, uint32_t size)
6295 {
6296         int end = (start + size > 256) ? 256 : start + size, i;
6297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298
6299         for (i = start; i < end; i++) {
6300                 intel_crtc->lut_r[i] = red[i] >> 8;
6301                 intel_crtc->lut_g[i] = green[i] >> 8;
6302                 intel_crtc->lut_b[i] = blue[i] >> 8;
6303         }
6304
6305         intel_crtc_load_lut(crtc);
6306 }
6307
6308 /**
6309  * Get a pipe with a simple mode set on it for doing load-based monitor
6310  * detection.
6311  *
6312  * It will be up to the load-detect code to adjust the pipe as appropriate for
6313  * its requirements.  The pipe will be connected to no other encoders.
6314  *
6315  * Currently this code will only succeed if there is a pipe with no encoders
6316  * configured for it.  In the future, it could choose to temporarily disable
6317  * some outputs to free up a pipe for its use.
6318  *
6319  * \return crtc, or NULL if no pipes are available.
6320  */
6321
6322 /* VESA 640x480x72Hz mode to set on the pipe */
6323 static struct drm_display_mode load_detect_mode = {
6324         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6325                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6326 };
6327
6328 static struct drm_framebuffer *
6329 intel_framebuffer_create(struct drm_device *dev,
6330                          struct drm_mode_fb_cmd *mode_cmd,
6331                          struct drm_i915_gem_object *obj)
6332 {
6333         struct intel_framebuffer *intel_fb;
6334         int ret;
6335
6336         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6337         if (!intel_fb) {
6338                 drm_gem_object_unreference_unlocked(&obj->base);
6339                 return ERR_PTR(-ENOMEM);
6340         }
6341
6342         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6343         if (ret) {
6344                 drm_gem_object_unreference_unlocked(&obj->base);
6345                 kfree(intel_fb);
6346                 return ERR_PTR(ret);
6347         }
6348
6349         return &intel_fb->base;
6350 }
6351
6352 static u32
6353 intel_framebuffer_pitch_for_width(int width, int bpp)
6354 {
6355         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6356         return ALIGN(pitch, 64);
6357 }
6358
6359 static u32
6360 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6361 {
6362         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6363         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6364 }
6365
6366 static struct drm_framebuffer *
6367 intel_framebuffer_create_for_mode(struct drm_device *dev,
6368                                   struct drm_display_mode *mode,
6369                                   int depth, int bpp)
6370 {
6371         struct drm_i915_gem_object *obj;
6372         struct drm_mode_fb_cmd mode_cmd;
6373
6374         obj = i915_gem_alloc_object(dev,
6375                                     intel_framebuffer_size_for_mode(mode, bpp));
6376         if (obj == NULL)
6377                 return ERR_PTR(-ENOMEM);
6378
6379         mode_cmd.width = mode->hdisplay;
6380         mode_cmd.height = mode->vdisplay;
6381         mode_cmd.depth = depth;
6382         mode_cmd.bpp = bpp;
6383         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6384
6385         return intel_framebuffer_create(dev, &mode_cmd, obj);
6386 }
6387
6388 static struct drm_framebuffer *
6389 mode_fits_in_fbdev(struct drm_device *dev,
6390                    struct drm_display_mode *mode)
6391 {
6392         struct drm_i915_private *dev_priv = dev->dev_private;
6393         struct drm_i915_gem_object *obj;
6394         struct drm_framebuffer *fb;
6395
6396         if (dev_priv->fbdev == NULL)
6397                 return NULL;
6398
6399         obj = dev_priv->fbdev->ifb.obj;
6400         if (obj == NULL)
6401                 return NULL;
6402
6403         fb = &dev_priv->fbdev->ifb.base;
6404         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6405                                                           fb->bits_per_pixel))
6406                 return NULL;
6407
6408         if (obj->base.size < mode->vdisplay * fb->pitch)
6409                 return NULL;
6410
6411         return fb;
6412 }
6413
6414 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6415                                 struct drm_connector *connector,
6416                                 struct drm_display_mode *mode,
6417                                 struct intel_load_detect_pipe *old)
6418 {
6419         struct intel_crtc *intel_crtc;
6420         struct drm_crtc *possible_crtc;
6421         struct drm_encoder *encoder = &intel_encoder->base;
6422         struct drm_crtc *crtc = NULL;
6423         struct drm_device *dev = encoder->dev;
6424         struct drm_framebuffer *old_fb;
6425         int i = -1;
6426
6427         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6428                       connector->base.id, drm_get_connector_name(connector),
6429                       encoder->base.id, drm_get_encoder_name(encoder));
6430
6431         /*
6432          * Algorithm gets a little messy:
6433          *
6434          *   - if the connector already has an assigned crtc, use it (but make
6435          *     sure it's on first)
6436          *
6437          *   - try to find the first unused crtc that can drive this connector,
6438          *     and use that if we find one
6439          */
6440
6441         /* See if we already have a CRTC for this connector */
6442         if (encoder->crtc) {
6443                 crtc = encoder->crtc;
6444
6445                 intel_crtc = to_intel_crtc(crtc);
6446                 old->dpms_mode = intel_crtc->dpms_mode;
6447                 old->load_detect_temp = false;
6448
6449                 /* Make sure the crtc and connector are running */
6450                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6451                         struct drm_encoder_helper_funcs *encoder_funcs;
6452                         struct drm_crtc_helper_funcs *crtc_funcs;
6453
6454                         crtc_funcs = crtc->helper_private;
6455                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6456
6457                         encoder_funcs = encoder->helper_private;
6458                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6459                 }
6460
6461                 return true;
6462         }
6463
6464         /* Find an unused one (if possible) */
6465         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6466                 i++;
6467                 if (!(encoder->possible_crtcs & (1 << i)))
6468                         continue;
6469                 if (!possible_crtc->enabled) {
6470                         crtc = possible_crtc;
6471                         break;
6472                 }
6473         }
6474
6475         /*
6476          * If we didn't find an unused CRTC, don't use any.
6477          */
6478         if (!crtc) {
6479                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6480                 return false;
6481         }
6482
6483         encoder->crtc = crtc;
6484         connector->encoder = encoder;
6485
6486         intel_crtc = to_intel_crtc(crtc);
6487         old->dpms_mode = intel_crtc->dpms_mode;
6488         old->load_detect_temp = true;
6489         old->release_fb = NULL;
6490
6491         if (!mode)
6492                 mode = &load_detect_mode;
6493
6494         old_fb = crtc->fb;
6495
6496         /* We need a framebuffer large enough to accommodate all accesses
6497          * that the plane may generate whilst we perform load detection.
6498          * We can not rely on the fbcon either being present (we get called
6499          * during its initialisation to detect all boot displays, or it may
6500          * not even exist) or that it is large enough to satisfy the
6501          * requested mode.
6502          */
6503         crtc->fb = mode_fits_in_fbdev(dev, mode);
6504         if (crtc->fb == NULL) {
6505                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6506                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6507                 old->release_fb = crtc->fb;
6508         } else
6509                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6510         if (IS_ERR(crtc->fb)) {
6511                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6512                 crtc->fb = old_fb;
6513                 return false;
6514         }
6515
6516         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6517                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6518                 if (old->release_fb)
6519                         old->release_fb->funcs->destroy(old->release_fb);
6520                 crtc->fb = old_fb;
6521                 return false;
6522         }
6523
6524         /* let the connector get through one full cycle before testing */
6525         intel_wait_for_vblank(dev, intel_crtc->pipe);
6526
6527         return true;
6528 }
6529
6530 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6531                                     struct drm_connector *connector,
6532                                     struct intel_load_detect_pipe *old)
6533 {
6534         struct drm_encoder *encoder = &intel_encoder->base;
6535         struct drm_device *dev = encoder->dev;
6536         struct drm_crtc *crtc = encoder->crtc;
6537         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6538         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6539
6540         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6541                       connector->base.id, drm_get_connector_name(connector),
6542                       encoder->base.id, drm_get_encoder_name(encoder));
6543
6544         if (old->load_detect_temp) {
6545                 connector->encoder = NULL;
6546                 drm_helper_disable_unused_functions(dev);
6547
6548                 if (old->release_fb)
6549                         old->release_fb->funcs->destroy(old->release_fb);
6550
6551                 return;
6552         }
6553
6554         /* Switch crtc and encoder back off if necessary */
6555         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6556                 encoder_funcs->dpms(encoder, old->dpms_mode);
6557                 crtc_funcs->dpms(crtc, old->dpms_mode);
6558         }
6559 }
6560
6561 /* Returns the clock of the currently programmed mode of the given pipe. */
6562 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6563 {
6564         struct drm_i915_private *dev_priv = dev->dev_private;
6565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6566         int pipe = intel_crtc->pipe;
6567         u32 dpll = I915_READ(DPLL(pipe));
6568         u32 fp;
6569         intel_clock_t clock;
6570
6571         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6572                 fp = I915_READ(FP0(pipe));
6573         else
6574                 fp = I915_READ(FP1(pipe));
6575
6576         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6577         if (IS_PINEVIEW(dev)) {
6578                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6579                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6580         } else {
6581                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6582                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6583         }
6584
6585         if (!IS_GEN2(dev)) {
6586                 if (IS_PINEVIEW(dev))
6587                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6588                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6589                 else
6590                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6591                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6592
6593                 switch (dpll & DPLL_MODE_MASK) {
6594                 case DPLLB_MODE_DAC_SERIAL:
6595                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6596                                 5 : 10;
6597                         break;
6598                 case DPLLB_MODE_LVDS:
6599                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6600                                 7 : 14;
6601                         break;
6602                 default:
6603                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6604                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6605                         return 0;
6606                 }
6607
6608                 /* XXX: Handle the 100Mhz refclk */
6609                 intel_clock(dev, 96000, &clock);
6610         } else {
6611                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6612
6613                 if (is_lvds) {
6614                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6615                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6616                         clock.p2 = 14;
6617
6618                         if ((dpll & PLL_REF_INPUT_MASK) ==
6619                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6620                                 /* XXX: might not be 66MHz */
6621                                 intel_clock(dev, 66000, &clock);
6622                         } else
6623                                 intel_clock(dev, 48000, &clock);
6624                 } else {
6625                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6626                                 clock.p1 = 2;
6627                         else {
6628                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6629                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6630                         }
6631                         if (dpll & PLL_P2_DIVIDE_BY_4)
6632                                 clock.p2 = 4;
6633                         else
6634                                 clock.p2 = 2;
6635
6636                         intel_clock(dev, 48000, &clock);
6637                 }
6638         }
6639
6640         /* XXX: It would be nice to validate the clocks, but we can't reuse
6641          * i830PllIsValid() because it relies on the xf86_config connector
6642          * configuration being accurate, which it isn't necessarily.
6643          */
6644
6645         return clock.dot;
6646 }
6647
6648 /** Returns the currently programmed mode of the given pipe. */
6649 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6650                                              struct drm_crtc *crtc)
6651 {
6652         struct drm_i915_private *dev_priv = dev->dev_private;
6653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654         int pipe = intel_crtc->pipe;
6655         struct drm_display_mode *mode;
6656         int htot = I915_READ(HTOTAL(pipe));
6657         int hsync = I915_READ(HSYNC(pipe));
6658         int vtot = I915_READ(VTOTAL(pipe));
6659         int vsync = I915_READ(VSYNC(pipe));
6660
6661         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6662         if (!mode)
6663                 return NULL;
6664
6665         mode->clock = intel_crtc_clock_get(dev, crtc);
6666         mode->hdisplay = (htot & 0xffff) + 1;
6667         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6668         mode->hsync_start = (hsync & 0xffff) + 1;
6669         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6670         mode->vdisplay = (vtot & 0xffff) + 1;
6671         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6672         mode->vsync_start = (vsync & 0xffff) + 1;
6673         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6674
6675         drm_mode_set_name(mode);
6676         drm_mode_set_crtcinfo(mode, 0);
6677
6678         return mode;
6679 }
6680
6681 #define GPU_IDLE_TIMEOUT 500 /* ms */
6682
6683 /* When this timer fires, we've been idle for awhile */
6684 static void intel_gpu_idle_timer(unsigned long arg)
6685 {
6686         struct drm_device *dev = (struct drm_device *)arg;
6687         drm_i915_private_t *dev_priv = dev->dev_private;
6688
6689         if (!list_empty(&dev_priv->mm.active_list)) {
6690                 /* Still processing requests, so just re-arm the timer. */
6691                 mod_timer(&dev_priv->idle_timer, jiffies +
6692                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6693                 return;
6694         }
6695
6696         dev_priv->busy = false;
6697         queue_work(dev_priv->wq, &dev_priv->idle_work);
6698 }
6699
6700 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6701
6702 static void intel_crtc_idle_timer(unsigned long arg)
6703 {
6704         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6705         struct drm_crtc *crtc = &intel_crtc->base;
6706         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6707         struct intel_framebuffer *intel_fb;
6708
6709         intel_fb = to_intel_framebuffer(crtc->fb);
6710         if (intel_fb && intel_fb->obj->active) {
6711                 /* The framebuffer is still being accessed by the GPU. */
6712                 mod_timer(&intel_crtc->idle_timer, jiffies +
6713                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6714                 return;
6715         }
6716
6717         intel_crtc->busy = false;
6718         queue_work(dev_priv->wq, &dev_priv->idle_work);
6719 }
6720
6721 static void intel_increase_pllclock(struct drm_crtc *crtc)
6722 {
6723         struct drm_device *dev = crtc->dev;
6724         drm_i915_private_t *dev_priv = dev->dev_private;
6725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6726         int pipe = intel_crtc->pipe;
6727         int dpll_reg = DPLL(pipe);
6728         int dpll;
6729
6730         if (HAS_PCH_SPLIT(dev))
6731                 return;
6732
6733         if (!dev_priv->lvds_downclock_avail)
6734                 return;
6735
6736         dpll = I915_READ(dpll_reg);
6737         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6738                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6739
6740                 /* Unlock panel regs */
6741                 I915_WRITE(PP_CONTROL,
6742                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6743
6744                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6745                 I915_WRITE(dpll_reg, dpll);
6746                 intel_wait_for_vblank(dev, pipe);
6747
6748                 dpll = I915_READ(dpll_reg);
6749                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6750                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6751
6752                 /* ...and lock them again */
6753                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6754         }
6755
6756         /* Schedule downclock */
6757         mod_timer(&intel_crtc->idle_timer, jiffies +
6758                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6759 }
6760
6761 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6762 {
6763         struct drm_device *dev = crtc->dev;
6764         drm_i915_private_t *dev_priv = dev->dev_private;
6765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6766         int pipe = intel_crtc->pipe;
6767         int dpll_reg = DPLL(pipe);
6768         int dpll = I915_READ(dpll_reg);
6769
6770         if (HAS_PCH_SPLIT(dev))
6771                 return;
6772
6773         if (!dev_priv->lvds_downclock_avail)
6774                 return;
6775
6776         /*
6777          * Since this is called by a timer, we should never get here in
6778          * the manual case.
6779          */
6780         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6781                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6782
6783                 /* Unlock panel regs */
6784                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6785                            PANEL_UNLOCK_REGS);
6786
6787                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6788                 I915_WRITE(dpll_reg, dpll);
6789                 intel_wait_for_vblank(dev, pipe);
6790                 dpll = I915_READ(dpll_reg);
6791                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6792                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6793
6794                 /* ...and lock them again */
6795                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6796         }
6797
6798 }
6799
6800 /**
6801  * intel_idle_update - adjust clocks for idleness
6802  * @work: work struct
6803  *
6804  * Either the GPU or display (or both) went idle.  Check the busy status
6805  * here and adjust the CRTC and GPU clocks as necessary.
6806  */
6807 static void intel_idle_update(struct work_struct *work)
6808 {
6809         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6810                                                     idle_work);
6811         struct drm_device *dev = dev_priv->dev;
6812         struct drm_crtc *crtc;
6813         struct intel_crtc *intel_crtc;
6814
6815         if (!i915_powersave)
6816                 return;
6817
6818         mutex_lock(&dev->struct_mutex);
6819
6820         i915_update_gfx_val(dev_priv);
6821
6822         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6823                 /* Skip inactive CRTCs */
6824                 if (!crtc->fb)
6825                         continue;
6826
6827                 intel_crtc = to_intel_crtc(crtc);
6828                 if (!intel_crtc->busy)
6829                         intel_decrease_pllclock(crtc);
6830         }
6831
6832
6833         mutex_unlock(&dev->struct_mutex);
6834 }
6835
6836 /**
6837  * intel_mark_busy - mark the GPU and possibly the display busy
6838  * @dev: drm device
6839  * @obj: object we're operating on
6840  *
6841  * Callers can use this function to indicate that the GPU is busy processing
6842  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6843  * buffer), we'll also mark the display as busy, so we know to increase its
6844  * clock frequency.
6845  */
6846 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6847 {
6848         drm_i915_private_t *dev_priv = dev->dev_private;
6849         struct drm_crtc *crtc = NULL;
6850         struct intel_framebuffer *intel_fb;
6851         struct intel_crtc *intel_crtc;
6852
6853         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6854                 return;
6855
6856         if (!dev_priv->busy)
6857                 dev_priv->busy = true;
6858         else
6859                 mod_timer(&dev_priv->idle_timer, jiffies +
6860                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6861
6862         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6863                 if (!crtc->fb)
6864                         continue;
6865
6866                 intel_crtc = to_intel_crtc(crtc);
6867                 intel_fb = to_intel_framebuffer(crtc->fb);
6868                 if (intel_fb->obj == obj) {
6869                         if (!intel_crtc->busy) {
6870                                 /* Non-busy -> busy, upclock */
6871                                 intel_increase_pllclock(crtc);
6872                                 intel_crtc->busy = true;
6873                         } else {
6874                                 /* Busy -> busy, put off timer */
6875                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6876                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6877                         }
6878                 }
6879         }
6880 }
6881
6882 static void intel_crtc_destroy(struct drm_crtc *crtc)
6883 {
6884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885         struct drm_device *dev = crtc->dev;
6886         struct intel_unpin_work *work;
6887         unsigned long flags;
6888
6889         spin_lock_irqsave(&dev->event_lock, flags);
6890         work = intel_crtc->unpin_work;
6891         intel_crtc->unpin_work = NULL;
6892         spin_unlock_irqrestore(&dev->event_lock, flags);
6893
6894         if (work) {
6895                 cancel_work_sync(&work->work);
6896                 kfree(work);
6897         }
6898
6899         drm_crtc_cleanup(crtc);
6900
6901         kfree(intel_crtc);
6902 }
6903
6904 static void intel_unpin_work_fn(struct work_struct *__work)
6905 {
6906         struct intel_unpin_work *work =
6907                 container_of(__work, struct intel_unpin_work, work);
6908
6909         mutex_lock(&work->dev->struct_mutex);
6910         i915_gem_object_unpin(work->old_fb_obj);
6911         drm_gem_object_unreference(&work->pending_flip_obj->base);
6912         drm_gem_object_unreference(&work->old_fb_obj->base);
6913
6914         intel_update_fbc(work->dev);
6915         mutex_unlock(&work->dev->struct_mutex);
6916         kfree(work);
6917 }
6918
6919 static void do_intel_finish_page_flip(struct drm_device *dev,
6920                                       struct drm_crtc *crtc)
6921 {
6922         drm_i915_private_t *dev_priv = dev->dev_private;
6923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924         struct intel_unpin_work *work;
6925         struct drm_i915_gem_object *obj;
6926         struct drm_pending_vblank_event *e;
6927         struct timeval tnow, tvbl;
6928         unsigned long flags;
6929
6930         /* Ignore early vblank irqs */
6931         if (intel_crtc == NULL)
6932                 return;
6933
6934         do_gettimeofday(&tnow);
6935
6936         spin_lock_irqsave(&dev->event_lock, flags);
6937         work = intel_crtc->unpin_work;
6938
6939         /* Ensure we don't miss a work->pending update ... */
6940         smp_rmb();
6941
6942         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6943                 spin_unlock_irqrestore(&dev->event_lock, flags);
6944                 return;
6945         }
6946
6947         /* and that the unpin work is consistent wrt ->pending. */
6948         smp_rmb();
6949
6950         intel_crtc->unpin_work = NULL;
6951
6952         if (work->event) {
6953                 e = work->event;
6954                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6955
6956                 /* Called before vblank count and timestamps have
6957                  * been updated for the vblank interval of flip
6958                  * completion? Need to increment vblank count and
6959                  * add one videorefresh duration to returned timestamp
6960                  * to account for this. We assume this happened if we
6961                  * get called over 0.9 frame durations after the last
6962                  * timestamped vblank.
6963                  *
6964                  * This calculation can not be used with vrefresh rates
6965                  * below 5Hz (10Hz to be on the safe side) without
6966                  * promoting to 64 integers.
6967                  */
6968                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6969                     9 * crtc->framedur_ns) {
6970                         e->event.sequence++;
6971                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6972                                              crtc->framedur_ns);
6973                 }
6974
6975                 e->event.tv_sec = tvbl.tv_sec;
6976                 e->event.tv_usec = tvbl.tv_usec;
6977
6978                 list_add_tail(&e->base.link,
6979                               &e->base.file_priv->event_list);
6980                 wake_up_interruptible(&e->base.file_priv->event_wait);
6981         }
6982
6983         drm_vblank_put(dev, intel_crtc->pipe);
6984
6985         spin_unlock_irqrestore(&dev->event_lock, flags);
6986
6987         obj = work->old_fb_obj;
6988
6989         atomic_clear_mask(1 << intel_crtc->plane,
6990                           &obj->pending_flip.counter);
6991
6992         wake_up(&dev_priv->pending_flip_queue);
6993         schedule_work(&work->work);
6994
6995         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6996 }
6997
6998 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6999 {
7000         drm_i915_private_t *dev_priv = dev->dev_private;
7001         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7002
7003         do_intel_finish_page_flip(dev, crtc);
7004 }
7005
7006 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7007 {
7008         drm_i915_private_t *dev_priv = dev->dev_private;
7009         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7010
7011         do_intel_finish_page_flip(dev, crtc);
7012 }
7013
7014 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7015 {
7016         drm_i915_private_t *dev_priv = dev->dev_private;
7017         struct intel_crtc *intel_crtc =
7018                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7019         unsigned long flags;
7020
7021         /* NB: An MMIO update of the plane base pointer will also
7022          * generate a page-flip completion irq, i.e. every modeset
7023          * is also accompanied by a spurious intel_prepare_page_flip().
7024          */
7025         spin_lock_irqsave(&dev->event_lock, flags);
7026         if (intel_crtc->unpin_work)
7027                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7028         spin_unlock_irqrestore(&dev->event_lock, flags);
7029 }
7030
7031 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7032 {
7033         /* Ensure that the work item is consistent when activating it ... */
7034         smp_wmb();
7035         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7036         /* and that it is marked active as soon as the irq could fire. */
7037         smp_wmb();
7038 }
7039
7040 static int intel_gen2_queue_flip(struct drm_device *dev,
7041                                  struct drm_crtc *crtc,
7042                                  struct drm_framebuffer *fb,
7043                                  struct drm_i915_gem_object *obj)
7044 {
7045         struct drm_i915_private *dev_priv = dev->dev_private;
7046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047         unsigned long offset;
7048         u32 flip_mask;
7049         int ret;
7050
7051         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7052         if (ret)
7053                 goto err;
7054
7055         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7056         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7057
7058         ret = BEGIN_LP_RING(6);
7059         if (ret)
7060                 goto err_unpin;
7061
7062         /* Can't queue multiple flips, so wait for the previous
7063          * one to finish before executing the next.
7064          */
7065         if (intel_crtc->plane)
7066                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7067         else
7068                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7069         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7070         OUT_RING(MI_NOOP);
7071         OUT_RING(MI_DISPLAY_FLIP |
7072                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7073         OUT_RING(fb->pitch);
7074         OUT_RING(obj->gtt_offset + offset);
7075         OUT_RING(MI_NOOP);
7076
7077         intel_mark_page_flip_active(intel_crtc);
7078         ADVANCE_LP_RING();
7079         return 0;
7080
7081 err_unpin:
7082         i915_gem_object_unpin(obj);
7083 err:
7084         return ret;
7085 }
7086
7087 static int intel_gen3_queue_flip(struct drm_device *dev,
7088                                  struct drm_crtc *crtc,
7089                                  struct drm_framebuffer *fb,
7090                                  struct drm_i915_gem_object *obj)
7091 {
7092         struct drm_i915_private *dev_priv = dev->dev_private;
7093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7094         unsigned long offset;
7095         u32 flip_mask;
7096         int ret;
7097
7098         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7099         if (ret)
7100                 goto err;
7101
7102         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7103         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7104
7105         ret = BEGIN_LP_RING(6);
7106         if (ret)
7107                 goto err_unpin;
7108
7109         if (intel_crtc->plane)
7110                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7111         else
7112                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7113         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7114         OUT_RING(MI_NOOP);
7115         OUT_RING(MI_DISPLAY_FLIP_I915 |
7116                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7117         OUT_RING(fb->pitch);
7118         OUT_RING(obj->gtt_offset + offset);
7119         OUT_RING(MI_NOOP);
7120
7121         intel_mark_page_flip_active(intel_crtc);
7122         ADVANCE_LP_RING();
7123         return 0;
7124
7125 err_unpin:
7126         i915_gem_object_unpin(obj);
7127 err:
7128         return ret;
7129 }
7130
7131 static int intel_gen4_queue_flip(struct drm_device *dev,
7132                                  struct drm_crtc *crtc,
7133                                  struct drm_framebuffer *fb,
7134                                  struct drm_i915_gem_object *obj)
7135 {
7136         struct drm_i915_private *dev_priv = dev->dev_private;
7137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138         uint32_t pf, pipesrc;
7139         int ret;
7140
7141         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7142         if (ret)
7143                 goto err;
7144
7145         ret = BEGIN_LP_RING(4);
7146         if (ret)
7147                 goto err_unpin;
7148
7149         /* i965+ uses the linear or tiled offsets from the
7150          * Display Registers (which do not change across a page-flip)
7151          * so we need only reprogram the base address.
7152          */
7153         OUT_RING(MI_DISPLAY_FLIP |
7154                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7155         OUT_RING(fb->pitch);
7156         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7157
7158         /* XXX Enabling the panel-fitter across page-flip is so far
7159          * untested on non-native modes, so ignore it for now.
7160          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7161          */
7162         pf = 0;
7163         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7164         OUT_RING(pf | pipesrc);
7165
7166         intel_mark_page_flip_active(intel_crtc);
7167         ADVANCE_LP_RING();
7168         return 0;
7169
7170 err_unpin:
7171         i915_gem_object_unpin(obj);
7172 err:
7173         return ret;
7174 }
7175
7176 static int intel_gen6_queue_flip(struct drm_device *dev,
7177                                  struct drm_crtc *crtc,
7178                                  struct drm_framebuffer *fb,
7179                                  struct drm_i915_gem_object *obj)
7180 {
7181         struct drm_i915_private *dev_priv = dev->dev_private;
7182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183         uint32_t pf, pipesrc;
7184         int ret;
7185
7186         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7187         if (ret)
7188                 goto err;
7189
7190         ret = BEGIN_LP_RING(4);
7191         if (ret)
7192                 goto err_unpin;
7193
7194         OUT_RING(MI_DISPLAY_FLIP |
7195                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7196         OUT_RING(fb->pitch | obj->tiling_mode);
7197         OUT_RING(obj->gtt_offset);
7198
7199         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7200         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7201         OUT_RING(pf | pipesrc);
7202
7203         intel_mark_page_flip_active(intel_crtc);
7204         ADVANCE_LP_RING();
7205         return 0;
7206
7207 err_unpin:
7208         i915_gem_object_unpin(obj);
7209 err:
7210         return ret;
7211 }
7212
7213 /*
7214  * On gen7 we currently use the blit ring because (in early silicon at least)
7215  * the render ring doesn't give us interrpts for page flip completion, which
7216  * means clients will hang after the first flip is queued.  Fortunately the
7217  * blit ring generates interrupts properly, so use it instead.
7218  */
7219 static int intel_gen7_queue_flip(struct drm_device *dev,
7220                                  struct drm_crtc *crtc,
7221                                  struct drm_framebuffer *fb,
7222                                  struct drm_i915_gem_object *obj)
7223 {
7224         struct drm_i915_private *dev_priv = dev->dev_private;
7225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7226         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7227         uint32_t plane_bit = 0;
7228         int ret;
7229
7230         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7231         if (ret)
7232                 goto err;
7233
7234         switch(intel_crtc->plane) {
7235         case PLANE_A:
7236                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7237                 break;
7238         case PLANE_B:
7239                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7240                 break;
7241         case PLANE_C:
7242                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7243                 break;
7244         default:
7245                 WARN_ONCE(1, "unknown plane in flip command\n");
7246                 ret = -ENODEV;
7247                 goto err_unpin;
7248         }
7249
7250         ret = intel_ring_begin(ring, 4);
7251         if (ret)
7252                 goto err_unpin;
7253
7254         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7255         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7256         intel_ring_emit(ring, (obj->gtt_offset));
7257         intel_ring_emit(ring, (MI_NOOP));
7258
7259         intel_mark_page_flip_active(intel_crtc);
7260         intel_ring_advance(ring);
7261         return 0;
7262
7263 err_unpin:
7264         i915_gem_object_unpin(obj);
7265 err:
7266         return ret;
7267 }
7268
7269 static int intel_default_queue_flip(struct drm_device *dev,
7270                                     struct drm_crtc *crtc,
7271                                     struct drm_framebuffer *fb,
7272                                     struct drm_i915_gem_object *obj)
7273 {
7274         return -ENODEV;
7275 }
7276
7277 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7278                                 struct drm_framebuffer *fb,
7279                                 struct drm_pending_vblank_event *event)
7280 {
7281         struct drm_device *dev = crtc->dev;
7282         struct drm_i915_private *dev_priv = dev->dev_private;
7283         struct drm_framebuffer *old_fb = crtc->fb;
7284         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7286         struct intel_unpin_work *work;
7287         unsigned long flags;
7288         int ret;
7289
7290         work = kzalloc(sizeof *work, GFP_KERNEL);
7291         if (work == NULL)
7292                 return -ENOMEM;
7293
7294         work->event = event;
7295         work->dev = crtc->dev;
7296         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7297         INIT_WORK(&work->work, intel_unpin_work_fn);
7298
7299         ret = drm_vblank_get(dev, intel_crtc->pipe);
7300         if (ret)
7301                 goto free_work;
7302
7303         /* We borrow the event spin lock for protecting unpin_work */
7304         spin_lock_irqsave(&dev->event_lock, flags);
7305         if (intel_crtc->unpin_work) {
7306                 spin_unlock_irqrestore(&dev->event_lock, flags);
7307                 kfree(work);
7308                 drm_vblank_put(dev, intel_crtc->pipe);
7309
7310                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7311                 return -EBUSY;
7312         }
7313         intel_crtc->unpin_work = work;
7314         spin_unlock_irqrestore(&dev->event_lock, flags);
7315
7316         mutex_lock(&dev->struct_mutex);
7317
7318         /* Reference the objects for the scheduled work. */
7319         drm_gem_object_reference(&work->old_fb_obj->base);
7320         drm_gem_object_reference(&obj->base);
7321
7322         crtc->fb = fb;
7323
7324         work->pending_flip_obj = obj;
7325
7326         work->enable_stall_check = true;
7327
7328         /* Block clients from rendering to the new back buffer until
7329          * the flip occurs and the object is no longer visible.
7330          */
7331         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7332
7333         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7334         if (ret)
7335                 goto cleanup_pending;
7336
7337         intel_disable_fbc(dev);
7338         mutex_unlock(&dev->struct_mutex);
7339
7340         trace_i915_flip_request(intel_crtc->plane, obj);
7341
7342         return 0;
7343
7344 cleanup_pending:
7345         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7346         crtc->fb = old_fb;
7347         drm_gem_object_unreference(&work->old_fb_obj->base);
7348         drm_gem_object_unreference(&obj->base);
7349         mutex_unlock(&dev->struct_mutex);
7350
7351         spin_lock_irqsave(&dev->event_lock, flags);
7352         intel_crtc->unpin_work = NULL;
7353         spin_unlock_irqrestore(&dev->event_lock, flags);
7354
7355         drm_vblank_put(dev, intel_crtc->pipe);
7356 free_work:
7357         kfree(work);
7358
7359         return ret;
7360 }
7361
7362 static void intel_sanitize_modesetting(struct drm_device *dev,
7363                                        int pipe, int plane)
7364 {
7365         struct drm_i915_private *dev_priv = dev->dev_private;
7366         u32 reg, val;
7367         int i;
7368
7369         /* Clear any frame start delays used for debugging left by the BIOS */
7370         for_each_pipe(i) {
7371                 reg = PIPECONF(i);
7372                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7373         }
7374
7375         if (HAS_PCH_SPLIT(dev))
7376                 return;
7377
7378         /* Who knows what state these registers were left in by the BIOS or
7379          * grub?
7380          *
7381          * If we leave the registers in a conflicting state (e.g. with the
7382          * display plane reading from the other pipe than the one we intend
7383          * to use) then when we attempt to teardown the active mode, we will
7384          * not disable the pipes and planes in the correct order -- leaving
7385          * a plane reading from a disabled pipe and possibly leading to
7386          * undefined behaviour.
7387          */
7388
7389         reg = DSPCNTR(plane);
7390         val = I915_READ(reg);
7391
7392         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7393                 return;
7394         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7395                 return;
7396
7397         /* This display plane is active and attached to the other CPU pipe. */
7398         pipe = !pipe;
7399
7400         /* Disable the plane and wait for it to stop reading from the pipe. */
7401         intel_disable_plane(dev_priv, plane, pipe);
7402         intel_disable_pipe(dev_priv, pipe);
7403 }
7404
7405 static void intel_crtc_reset(struct drm_crtc *crtc)
7406 {
7407         struct drm_device *dev = crtc->dev;
7408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7409
7410         /* Reset flags back to the 'unknown' status so that they
7411          * will be correctly set on the initial modeset.
7412          */
7413         intel_crtc->dpms_mode = -1;
7414
7415         /* We need to fix up any BIOS configuration that conflicts with
7416          * our expectations.
7417          */
7418         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7419 }
7420
7421 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7422         .dpms = intel_crtc_dpms,
7423         .mode_fixup = intel_crtc_mode_fixup,
7424         .mode_set = intel_crtc_mode_set,
7425         .mode_set_base = intel_pipe_set_base,
7426         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7427         .load_lut = intel_crtc_load_lut,
7428         .disable = intel_crtc_disable,
7429 };
7430
7431 static const struct drm_crtc_funcs intel_crtc_funcs = {
7432         .reset = intel_crtc_reset,
7433         .cursor_set = intel_crtc_cursor_set,
7434         .cursor_move = intel_crtc_cursor_move,
7435         .gamma_set = intel_crtc_gamma_set,
7436         .set_config = drm_crtc_helper_set_config,
7437         .destroy = intel_crtc_destroy,
7438         .page_flip = intel_crtc_page_flip,
7439 };
7440
7441 static void intel_crtc_init(struct drm_device *dev, int pipe)
7442 {
7443         drm_i915_private_t *dev_priv = dev->dev_private;
7444         struct intel_crtc *intel_crtc;
7445         int i;
7446
7447         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7448         if (intel_crtc == NULL)
7449                 return;
7450
7451         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7452
7453         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7454         for (i = 0; i < 256; i++) {
7455                 intel_crtc->lut_r[i] = i;
7456                 intel_crtc->lut_g[i] = i;
7457                 intel_crtc->lut_b[i] = i;
7458         }
7459
7460         /* Swap pipes & planes for FBC on pre-965 */
7461         intel_crtc->pipe = pipe;
7462         intel_crtc->plane = pipe;
7463         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7464                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7465                 intel_crtc->plane = !pipe;
7466         }
7467
7468         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7469                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7470         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7471         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7472
7473         intel_crtc_reset(&intel_crtc->base);
7474         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7475         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7476
7477         if (HAS_PCH_SPLIT(dev)) {
7478                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7479                         intel_crtc->no_pll = true;
7480                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7481                 intel_helper_funcs.commit = ironlake_crtc_commit;
7482         } else {
7483                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7484                 intel_helper_funcs.commit = i9xx_crtc_commit;
7485         }
7486
7487         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7488
7489         intel_crtc->busy = false;
7490
7491         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7492                     (unsigned long)intel_crtc);
7493 }
7494
7495 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7496                                 struct drm_file *file)
7497 {
7498         drm_i915_private_t *dev_priv = dev->dev_private;
7499         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7500         struct drm_mode_object *drmmode_obj;
7501         struct intel_crtc *crtc;
7502
7503         if (!dev_priv) {
7504                 DRM_ERROR("called with no initialization\n");
7505                 return -EINVAL;
7506         }
7507
7508         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7509                         DRM_MODE_OBJECT_CRTC);
7510
7511         if (!drmmode_obj) {
7512                 DRM_ERROR("no such CRTC id\n");
7513                 return -EINVAL;
7514         }
7515
7516         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7517         pipe_from_crtc_id->pipe = crtc->pipe;
7518
7519         return 0;
7520 }
7521
7522 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7523 {
7524         struct intel_encoder *encoder;
7525         int index_mask = 0;
7526         int entry = 0;
7527
7528         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7529                 if (type_mask & encoder->clone_mask)
7530                         index_mask |= (1 << entry);
7531                 entry++;
7532         }
7533
7534         return index_mask;
7535 }
7536
7537 static bool has_edp_a(struct drm_device *dev)
7538 {
7539         struct drm_i915_private *dev_priv = dev->dev_private;
7540
7541         if (!IS_MOBILE(dev))
7542                 return false;
7543
7544         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7545                 return false;
7546
7547         if (IS_GEN5(dev) &&
7548             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7549                 return false;
7550
7551         return true;
7552 }
7553
7554 static void intel_setup_outputs(struct drm_device *dev)
7555 {
7556         struct drm_i915_private *dev_priv = dev->dev_private;
7557         struct intel_encoder *encoder;
7558         bool dpd_is_edp = false;
7559         bool has_lvds = false;
7560
7561         if (IS_MOBILE(dev) && !IS_I830(dev))
7562                 has_lvds = intel_lvds_init(dev);
7563         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7564                 /* disable the panel fitter on everything but LVDS */
7565                 I915_WRITE(PFIT_CONTROL, 0);
7566         }
7567
7568         if (HAS_PCH_SPLIT(dev)) {
7569                 dpd_is_edp = intel_dpd_is_edp(dev);
7570
7571                 if (has_edp_a(dev))
7572                         intel_dp_init(dev, DP_A);
7573
7574                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7575                         intel_dp_init(dev, PCH_DP_D);
7576         }
7577
7578         intel_crt_init(dev);
7579
7580         if (HAS_PCH_SPLIT(dev)) {
7581                 int found;
7582
7583                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7584                         /* PCH SDVOB multiplex with HDMIB */
7585                         found = intel_sdvo_init(dev, PCH_SDVOB);
7586                         if (!found)
7587                                 intel_hdmi_init(dev, HDMIB);
7588                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7589                                 intel_dp_init(dev, PCH_DP_B);
7590                 }
7591
7592                 if (I915_READ(HDMIC) & PORT_DETECTED)
7593                         intel_hdmi_init(dev, HDMIC);
7594
7595                 if (I915_READ(HDMID) & PORT_DETECTED)
7596                         intel_hdmi_init(dev, HDMID);
7597
7598                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7599                         intel_dp_init(dev, PCH_DP_C);
7600
7601                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7602                         intel_dp_init(dev, PCH_DP_D);
7603
7604         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7605                 bool found = false;
7606
7607                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7608                         DRM_DEBUG_KMS("probing SDVOB\n");
7609                         found = intel_sdvo_init(dev, SDVOB);
7610                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7611                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7612                                 intel_hdmi_init(dev, SDVOB);
7613                         }
7614
7615                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7616                                 DRM_DEBUG_KMS("probing DP_B\n");
7617                                 intel_dp_init(dev, DP_B);
7618                         }
7619                 }
7620
7621                 /* Before G4X SDVOC doesn't have its own detect register */
7622
7623                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7624                         DRM_DEBUG_KMS("probing SDVOC\n");
7625                         found = intel_sdvo_init(dev, SDVOC);
7626                 }
7627
7628                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7629
7630                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7631                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7632                                 intel_hdmi_init(dev, SDVOC);
7633                         }
7634                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7635                                 DRM_DEBUG_KMS("probing DP_C\n");
7636                                 intel_dp_init(dev, DP_C);
7637                         }
7638                 }
7639
7640                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7641                     (I915_READ(DP_D) & DP_DETECTED)) {
7642                         DRM_DEBUG_KMS("probing DP_D\n");
7643                         intel_dp_init(dev, DP_D);
7644                 }
7645         } else if (IS_GEN2(dev))
7646                 intel_dvo_init(dev);
7647
7648         if (SUPPORTS_TV(dev))
7649                 intel_tv_init(dev);
7650
7651         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7652                 encoder->base.possible_crtcs = encoder->crtc_mask;
7653                 encoder->base.possible_clones =
7654                         intel_encoder_clones(dev, encoder->clone_mask);
7655         }
7656
7657         /* disable all the possible outputs/crtcs before entering KMS mode */
7658         drm_helper_disable_unused_functions(dev);
7659
7660         if (HAS_PCH_SPLIT(dev))
7661                 ironlake_init_pch_refclk(dev);
7662 }
7663
7664 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7665 {
7666         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7667
7668         drm_framebuffer_cleanup(fb);
7669         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7670
7671         kfree(intel_fb);
7672 }
7673
7674 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7675                                                 struct drm_file *file,
7676                                                 unsigned int *handle)
7677 {
7678         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7679         struct drm_i915_gem_object *obj = intel_fb->obj;
7680
7681         return drm_gem_handle_create(file, &obj->base, handle);
7682 }
7683
7684 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7685         .destroy = intel_user_framebuffer_destroy,
7686         .create_handle = intel_user_framebuffer_create_handle,
7687 };
7688
7689 int intel_framebuffer_init(struct drm_device *dev,
7690                            struct intel_framebuffer *intel_fb,
7691                            struct drm_mode_fb_cmd *mode_cmd,
7692                            struct drm_i915_gem_object *obj)
7693 {
7694         int ret;
7695
7696         if (obj->tiling_mode == I915_TILING_Y)
7697                 return -EINVAL;
7698
7699         if (mode_cmd->pitch & 63)
7700                 return -EINVAL;
7701
7702         switch (mode_cmd->bpp) {
7703         case 8:
7704         case 16:
7705                 /* Only pre-ILK can handle 5:5:5 */
7706                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7707                         return -EINVAL;
7708                 break;
7709
7710         case 24:
7711         case 32:
7712                 break;
7713         default:
7714                 return -EINVAL;
7715         }
7716
7717         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7718         if (ret) {
7719                 DRM_ERROR("framebuffer init failed %d\n", ret);
7720                 return ret;
7721         }
7722
7723         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7724         intel_fb->obj = obj;
7725         return 0;
7726 }
7727
7728 static struct drm_framebuffer *
7729 intel_user_framebuffer_create(struct drm_device *dev,
7730                               struct drm_file *filp,
7731                               struct drm_mode_fb_cmd *mode_cmd)
7732 {
7733         struct drm_i915_gem_object *obj;
7734
7735         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7736         if (&obj->base == NULL)
7737                 return ERR_PTR(-ENOENT);
7738
7739         return intel_framebuffer_create(dev, mode_cmd, obj);
7740 }
7741
7742 static const struct drm_mode_config_funcs intel_mode_funcs = {
7743         .fb_create = intel_user_framebuffer_create,
7744         .output_poll_changed = intel_fb_output_poll_changed,
7745 };
7746
7747 static struct drm_i915_gem_object *
7748 intel_alloc_context_page(struct drm_device *dev)
7749 {
7750         struct drm_i915_gem_object *ctx;
7751         int ret;
7752
7753         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7754
7755         ctx = i915_gem_alloc_object(dev, 4096);
7756         if (!ctx) {
7757                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7758                 return NULL;
7759         }
7760
7761         ret = i915_gem_object_pin(ctx, 4096, true);
7762         if (ret) {
7763                 DRM_ERROR("failed to pin power context: %d\n", ret);
7764                 goto err_unref;
7765         }
7766
7767         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7768         if (ret) {
7769                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7770                 goto err_unpin;
7771         }
7772
7773         return ctx;
7774
7775 err_unpin:
7776         i915_gem_object_unpin(ctx);
7777 err_unref:
7778         drm_gem_object_unreference(&ctx->base);
7779         mutex_unlock(&dev->struct_mutex);
7780         return NULL;
7781 }
7782
7783 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7784 {
7785         struct drm_i915_private *dev_priv = dev->dev_private;
7786         u16 rgvswctl;
7787
7788         rgvswctl = I915_READ16(MEMSWCTL);
7789         if (rgvswctl & MEMCTL_CMD_STS) {
7790                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7791                 return false; /* still busy with another command */
7792         }
7793
7794         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7795                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7796         I915_WRITE16(MEMSWCTL, rgvswctl);
7797         POSTING_READ16(MEMSWCTL);
7798
7799         rgvswctl |= MEMCTL_CMD_STS;
7800         I915_WRITE16(MEMSWCTL, rgvswctl);
7801
7802         return true;
7803 }
7804
7805 void ironlake_enable_drps(struct drm_device *dev)
7806 {
7807         struct drm_i915_private *dev_priv = dev->dev_private;
7808         u32 rgvmodectl = I915_READ(MEMMODECTL);
7809         u8 fmax, fmin, fstart, vstart;
7810
7811         /* Enable temp reporting */
7812         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7813         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7814
7815         /* 100ms RC evaluation intervals */
7816         I915_WRITE(RCUPEI, 100000);
7817         I915_WRITE(RCDNEI, 100000);
7818
7819         /* Set max/min thresholds to 90ms and 80ms respectively */
7820         I915_WRITE(RCBMAXAVG, 90000);
7821         I915_WRITE(RCBMINAVG, 80000);
7822
7823         I915_WRITE(MEMIHYST, 1);
7824
7825         /* Set up min, max, and cur for interrupt handling */
7826         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7827         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7828         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7829                 MEMMODE_FSTART_SHIFT;
7830
7831         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7832                 PXVFREQ_PX_SHIFT;
7833
7834         dev_priv->fmax = fmax; /* IPS callback will increase this */
7835         dev_priv->fstart = fstart;
7836
7837         dev_priv->max_delay = fstart;
7838         dev_priv->min_delay = fmin;
7839         dev_priv->cur_delay = fstart;
7840
7841         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7842                          fmax, fmin, fstart);
7843
7844         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7845
7846         /*
7847          * Interrupts will be enabled in ironlake_irq_postinstall
7848          */
7849
7850         I915_WRITE(VIDSTART, vstart);
7851         POSTING_READ(VIDSTART);
7852
7853         rgvmodectl |= MEMMODE_SWMODE_EN;
7854         I915_WRITE(MEMMODECTL, rgvmodectl);
7855
7856         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7857                 DRM_ERROR("stuck trying to change perf mode\n");
7858         msleep(1);
7859
7860         ironlake_set_drps(dev, fstart);
7861
7862         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7863                 I915_READ(0x112e0);
7864         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7865         dev_priv->last_count2 = I915_READ(0x112f4);
7866         getrawmonotonic(&dev_priv->last_time2);
7867 }
7868
7869 void ironlake_disable_drps(struct drm_device *dev)
7870 {
7871         struct drm_i915_private *dev_priv = dev->dev_private;
7872         u16 rgvswctl = I915_READ16(MEMSWCTL);
7873
7874         /* Ack interrupts, disable EFC interrupt */
7875         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7876         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7877         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7878         I915_WRITE(DEIIR, DE_PCU_EVENT);
7879         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7880
7881         /* Go back to the starting frequency */
7882         ironlake_set_drps(dev, dev_priv->fstart);
7883         msleep(1);
7884         rgvswctl |= MEMCTL_CMD_STS;
7885         I915_WRITE(MEMSWCTL, rgvswctl);
7886         msleep(1);
7887
7888 }
7889
7890 void gen6_set_rps(struct drm_device *dev, u8 val)
7891 {
7892         struct drm_i915_private *dev_priv = dev->dev_private;
7893         u32 swreq;
7894
7895         swreq = (val & 0x3ff) << 25;
7896         I915_WRITE(GEN6_RPNSWREQ, swreq);
7897 }
7898
7899 void gen6_disable_rps(struct drm_device *dev)
7900 {
7901         struct drm_i915_private *dev_priv = dev->dev_private;
7902
7903         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7904         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7905         I915_WRITE(GEN6_PMIER, 0);
7906         /* Complete PM interrupt masking here doesn't race with the rps work
7907          * item again unmasking PM interrupts because that is using a different
7908          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7909          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7910
7911         spin_lock_irq(&dev_priv->rps_lock);
7912         dev_priv->pm_iir = 0;
7913         spin_unlock_irq(&dev_priv->rps_lock);
7914
7915         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7916 }
7917
7918 static unsigned long intel_pxfreq(u32 vidfreq)
7919 {
7920         unsigned long freq;
7921         int div = (vidfreq & 0x3f0000) >> 16;
7922         int post = (vidfreq & 0x3000) >> 12;
7923         int pre = (vidfreq & 0x7);
7924
7925         if (!pre)
7926                 return 0;
7927
7928         freq = ((div * 133333) / ((1<<post) * pre));
7929
7930         return freq;
7931 }
7932
7933 void intel_init_emon(struct drm_device *dev)
7934 {
7935         struct drm_i915_private *dev_priv = dev->dev_private;
7936         u32 lcfuse;
7937         u8 pxw[16];
7938         int i;
7939
7940         /* Disable to program */
7941         I915_WRITE(ECR, 0);
7942         POSTING_READ(ECR);
7943
7944         /* Program energy weights for various events */
7945         I915_WRITE(SDEW, 0x15040d00);
7946         I915_WRITE(CSIEW0, 0x007f0000);
7947         I915_WRITE(CSIEW1, 0x1e220004);
7948         I915_WRITE(CSIEW2, 0x04000004);
7949
7950         for (i = 0; i < 5; i++)
7951                 I915_WRITE(PEW + (i * 4), 0);
7952         for (i = 0; i < 3; i++)
7953                 I915_WRITE(DEW + (i * 4), 0);
7954
7955         /* Program P-state weights to account for frequency power adjustment */
7956         for (i = 0; i < 16; i++) {
7957                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7958                 unsigned long freq = intel_pxfreq(pxvidfreq);
7959                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7960                         PXVFREQ_PX_SHIFT;
7961                 unsigned long val;
7962
7963                 val = vid * vid;
7964                 val *= (freq / 1000);
7965                 val *= 255;
7966                 val /= (127*127*900);
7967                 if (val > 0xff)
7968                         DRM_ERROR("bad pxval: %ld\n", val);
7969                 pxw[i] = val;
7970         }
7971         /* Render standby states get 0 weight */
7972         pxw[14] = 0;
7973         pxw[15] = 0;
7974
7975         for (i = 0; i < 4; i++) {
7976                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7977                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7978                 I915_WRITE(PXW + (i * 4), val);
7979         }
7980
7981         /* Adjust magic regs to magic values (more experimental results) */
7982         I915_WRITE(OGW0, 0);
7983         I915_WRITE(OGW1, 0);
7984         I915_WRITE(EG0, 0x00007f00);
7985         I915_WRITE(EG1, 0x0000000e);
7986         I915_WRITE(EG2, 0x000e0000);
7987         I915_WRITE(EG3, 0x68000300);
7988         I915_WRITE(EG4, 0x42000000);
7989         I915_WRITE(EG5, 0x00140031);
7990         I915_WRITE(EG6, 0);
7991         I915_WRITE(EG7, 0);
7992
7993         for (i = 0; i < 8; i++)
7994                 I915_WRITE(PXWL + (i * 4), 0);
7995
7996         /* Enable PMON + select events */
7997         I915_WRITE(ECR, 0x80000019);
7998
7999         lcfuse = I915_READ(LCFUSE02);
8000
8001         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8002 }
8003
8004 static bool intel_enable_rc6(struct drm_device *dev)
8005 {
8006         /*
8007          * Respect the kernel parameter if it is set
8008          */
8009         if (i915_enable_rc6 >= 0)
8010                 return i915_enable_rc6;
8011
8012         /*
8013          * Disable RC6 on Ironlake
8014          */
8015         if (INTEL_INFO(dev)->gen == 5)
8016                 return 0;
8017
8018         /*
8019          * Disable rc6 on Sandybridge
8020          */
8021         if (INTEL_INFO(dev)->gen == 6) {
8022                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8023                 return 0;
8024         }
8025         DRM_DEBUG_DRIVER("RC6 enabled\n");
8026         return 1;
8027 }
8028
8029 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8030 {
8031         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8032         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8033         u32 pcu_mbox, rc6_mask = 0;
8034         int cur_freq, min_freq, max_freq;
8035         int i;
8036
8037         /* Here begins a magic sequence of register writes to enable
8038          * auto-downclocking.
8039          *
8040          * Perhaps there might be some value in exposing these to
8041          * userspace...
8042          */
8043         I915_WRITE(GEN6_RC_STATE, 0);
8044         mutex_lock(&dev_priv->dev->struct_mutex);
8045         gen6_gt_force_wake_get(dev_priv);
8046
8047         /* disable the counters and set deterministic thresholds */
8048         I915_WRITE(GEN6_RC_CONTROL, 0);
8049
8050         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8051         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8052         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8053         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8054         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8055
8056         for (i = 0; i < I915_NUM_RINGS; i++)
8057                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8058
8059         I915_WRITE(GEN6_RC_SLEEP, 0);
8060         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8061         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8062         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
8063         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8064
8065         if (intel_enable_rc6(dev_priv->dev))
8066                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8067                         ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
8068
8069         I915_WRITE(GEN6_RC_CONTROL,
8070                    rc6_mask |
8071                    GEN6_RC_CTL_EI_MODE(1) |
8072                    GEN6_RC_CTL_HW_ENABLE);
8073
8074         I915_WRITE(GEN6_RPNSWREQ,
8075                    GEN6_FREQUENCY(10) |
8076                    GEN6_OFFSET(0) |
8077                    GEN6_AGGRESSIVE_TURBO);
8078         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8079                    GEN6_FREQUENCY(12));
8080
8081         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8082         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8083                    18 << 24 |
8084                    6 << 16);
8085         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8086         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8087         I915_WRITE(GEN6_RP_UP_EI, 100000);
8088         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8089         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8090         I915_WRITE(GEN6_RP_CONTROL,
8091                    GEN6_RP_MEDIA_TURBO |
8092                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
8093                    GEN6_RP_MEDIA_IS_GFX |
8094                    GEN6_RP_ENABLE |
8095                    GEN6_RP_UP_BUSY_AVG |
8096                    GEN6_RP_DOWN_IDLE_CONT);
8097
8098         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8099                      500))
8100                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8101
8102         I915_WRITE(GEN6_PCODE_DATA, 0);
8103         I915_WRITE(GEN6_PCODE_MAILBOX,
8104                    GEN6_PCODE_READY |
8105                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8106         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8107                      500))
8108                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8109
8110         min_freq = (rp_state_cap & 0xff0000) >> 16;
8111         max_freq = rp_state_cap & 0xff;
8112         cur_freq = (gt_perf_status & 0xff00) >> 8;
8113
8114         /* Check for overclock support */
8115         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8116                      500))
8117                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8118         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8119         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8120         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8121                      500))
8122                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8123         if (pcu_mbox & (1<<31)) { /* OC supported */
8124                 max_freq = pcu_mbox & 0xff;
8125                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8126         }
8127
8128         /* In units of 100MHz */
8129         dev_priv->max_delay = max_freq;
8130         dev_priv->min_delay = min_freq;
8131         dev_priv->cur_delay = cur_freq;
8132
8133         /* requires MSI enabled */
8134         I915_WRITE(GEN6_PMIER,
8135                    GEN6_PM_MBOX_EVENT |
8136                    GEN6_PM_THERMAL_EVENT |
8137                    GEN6_PM_RP_DOWN_TIMEOUT |
8138                    GEN6_PM_RP_UP_THRESHOLD |
8139                    GEN6_PM_RP_DOWN_THRESHOLD |
8140                    GEN6_PM_RP_UP_EI_EXPIRED |
8141                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8142         spin_lock_irq(&dev_priv->rps_lock);
8143         WARN_ON(dev_priv->pm_iir != 0);
8144         I915_WRITE(GEN6_PMIMR, 0);
8145         spin_unlock_irq(&dev_priv->rps_lock);
8146         /* enable all PM interrupts */
8147         I915_WRITE(GEN6_PMINTRMSK, 0);
8148
8149         gen6_gt_force_wake_put(dev_priv);
8150         mutex_unlock(&dev_priv->dev->struct_mutex);
8151 }
8152
8153 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8154 {
8155         int min_freq = 15;
8156         int gpu_freq, ia_freq, max_ia_freq;
8157         int scaling_factor = 180;
8158
8159         max_ia_freq = cpufreq_quick_get_max(0);
8160         /*
8161          * Default to measured freq if none found, PCU will ensure we don't go
8162          * over
8163          */
8164         if (!max_ia_freq)
8165                 max_ia_freq = tsc_khz;
8166
8167         /* Convert from kHz to MHz */
8168         max_ia_freq /= 1000;
8169
8170         mutex_lock(&dev_priv->dev->struct_mutex);
8171
8172         /*
8173          * For each potential GPU frequency, load a ring frequency we'd like
8174          * to use for memory access.  We do this by specifying the IA frequency
8175          * the PCU should use as a reference to determine the ring frequency.
8176          */
8177         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8178              gpu_freq--) {
8179                 int diff = dev_priv->max_delay - gpu_freq;
8180
8181                 /*
8182                  * For GPU frequencies less than 750MHz, just use the lowest
8183                  * ring freq.
8184                  */
8185                 if (gpu_freq < min_freq)
8186                         ia_freq = 800;
8187                 else
8188                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8189                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8190
8191                 I915_WRITE(GEN6_PCODE_DATA,
8192                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8193                            gpu_freq);
8194                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8195                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8196                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8197                               GEN6_PCODE_READY) == 0, 10)) {
8198                         DRM_ERROR("pcode write of freq table timed out\n");
8199                         continue;
8200                 }
8201         }
8202
8203         mutex_unlock(&dev_priv->dev->struct_mutex);
8204 }
8205
8206 static void ironlake_init_clock_gating(struct drm_device *dev)
8207 {
8208         struct drm_i915_private *dev_priv = dev->dev_private;
8209         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8210
8211         /* Required for FBC */
8212         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8213                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8214                 DPFDUNIT_CLOCK_GATE_DISABLE;
8215         /* Required for CxSR */
8216         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8217
8218         I915_WRITE(PCH_3DCGDIS0,
8219                    MARIUNIT_CLOCK_GATE_DISABLE |
8220                    SVSMUNIT_CLOCK_GATE_DISABLE);
8221         I915_WRITE(PCH_3DCGDIS1,
8222                    VFMUNIT_CLOCK_GATE_DISABLE);
8223
8224         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8225
8226         /*
8227          * According to the spec the following bits should be set in
8228          * order to enable memory self-refresh
8229          * The bit 22/21 of 0x42004
8230          * The bit 5 of 0x42020
8231          * The bit 15 of 0x45000
8232          */
8233         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8234                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8235                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8236         I915_WRITE(ILK_DSPCLK_GATE,
8237                    (I915_READ(ILK_DSPCLK_GATE) |
8238                     ILK_DPARB_CLK_GATE));
8239         I915_WRITE(DISP_ARB_CTL,
8240                    (I915_READ(DISP_ARB_CTL) |
8241                     DISP_FBC_WM_DIS));
8242         I915_WRITE(WM3_LP_ILK, 0);
8243         I915_WRITE(WM2_LP_ILK, 0);
8244         I915_WRITE(WM1_LP_ILK, 0);
8245
8246         /*
8247          * Based on the document from hardware guys the following bits
8248          * should be set unconditionally in order to enable FBC.
8249          * The bit 22 of 0x42000
8250          * The bit 22 of 0x42004
8251          * The bit 7,8,9 of 0x42020.
8252          */
8253         if (IS_IRONLAKE_M(dev)) {
8254                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8255                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8256                            ILK_FBCQ_DIS);
8257                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8258                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8259                            ILK_DPARB_GATE);
8260                 I915_WRITE(ILK_DSPCLK_GATE,
8261                            I915_READ(ILK_DSPCLK_GATE) |
8262                            ILK_DPFC_DIS1 |
8263                            ILK_DPFC_DIS2 |
8264                            ILK_CLK_FBC);
8265         }
8266
8267         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8268                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8269                    ILK_ELPIN_409_SELECT);
8270         I915_WRITE(_3D_CHICKEN2,
8271                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8272                    _3D_CHICKEN2_WM_READ_PIPELINED);
8273 }
8274
8275 static void gen6_init_clock_gating(struct drm_device *dev)
8276 {
8277         struct drm_i915_private *dev_priv = dev->dev_private;
8278         int pipe;
8279         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8280
8281         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8282
8283         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8284                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8285                    ILK_ELPIN_409_SELECT);
8286
8287         /* WaDisableHiZPlanesWhenMSAAEnabled */
8288         I915_WRITE(_3D_CHICKEN,
8289                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8290
8291         I915_WRITE(WM3_LP_ILK, 0);
8292         I915_WRITE(WM2_LP_ILK, 0);
8293         I915_WRITE(WM1_LP_ILK, 0);
8294
8295         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8296          * gating disable must be set.  Failure to set it results in
8297          * flickering pixels due to Z write ordering failures after
8298          * some amount of runtime in the Mesa "fire" demo, and Unigine
8299          * Sanctuary and Tropics, and apparently anything else with
8300          * alpha test or pixel discard.
8301          *
8302          * According to the spec, bit 11 (RCCUNIT) must also be set,
8303          * but we didn't debug actual testcases to find it out.
8304          */
8305         I915_WRITE(GEN6_UCGCTL2,
8306                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8307                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8308
8309         /*
8310          * According to the spec the following bits should be
8311          * set in order to enable memory self-refresh and fbc:
8312          * The bit21 and bit22 of 0x42000
8313          * The bit21 and bit22 of 0x42004
8314          * The bit5 and bit7 of 0x42020
8315          * The bit14 of 0x70180
8316          * The bit14 of 0x71180
8317          */
8318         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8319                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8320                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8321         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8322                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8323                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8324         I915_WRITE(ILK_DSPCLK_GATE,
8325                    I915_READ(ILK_DSPCLK_GATE) |
8326                    ILK_DPARB_CLK_GATE  |
8327                    ILK_DPFD_CLK_GATE);
8328
8329         for_each_pipe(pipe) {
8330                 I915_WRITE(DSPCNTR(pipe),
8331                            I915_READ(DSPCNTR(pipe)) |
8332                            DISPPLANE_TRICKLE_FEED_DISABLE);
8333                 intel_flush_display_plane(dev_priv, pipe);
8334         }
8335
8336         /* The default value should be 0x200 according to docs, but the two
8337          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
8338         I915_WRITE(GEN6_GT_MODE, 0xffff << 16);
8339         I915_WRITE(GEN6_GT_MODE, GEN6_GT_MODE_HI << 16 | GEN6_GT_MODE_HI);
8340 }
8341
8342 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8343 {
8344         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8345
8346         reg &= ~GEN7_FF_SCHED_MASK;
8347         reg |= GEN7_FF_TS_SCHED_HW;
8348         reg |= GEN7_FF_VS_SCHED_HW;
8349         reg |= GEN7_FF_DS_SCHED_HW;
8350
8351         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8352 }
8353
8354 static void ivybridge_init_clock_gating(struct drm_device *dev)
8355 {
8356         struct drm_i915_private *dev_priv = dev->dev_private;
8357         int pipe;
8358         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8359
8360         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8361
8362         I915_WRITE(WM3_LP_ILK, 0);
8363         I915_WRITE(WM2_LP_ILK, 0);
8364         I915_WRITE(WM1_LP_ILK, 0);
8365
8366         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8367          * This implements the WaDisableRCZUnitClockGating workaround.
8368          */
8369         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8370
8371         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8372
8373         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8374         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8375                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8376
8377         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8378         I915_WRITE(GEN7_L3CNTLREG1,
8379                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8380         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8381                         GEN7_WA_L3_CHICKEN_MODE);
8382
8383         /* This is required by WaCatErrorRejectionIssue */
8384         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8385                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8386                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8387
8388         for_each_pipe(pipe) {
8389                 I915_WRITE(DSPCNTR(pipe),
8390                            I915_READ(DSPCNTR(pipe)) |
8391                            DISPPLANE_TRICKLE_FEED_DISABLE);
8392                 intel_flush_display_plane(dev_priv, pipe);
8393         }
8394
8395         gen7_setup_fixed_func_scheduler(dev_priv);
8396 }
8397
8398 static void g4x_init_clock_gating(struct drm_device *dev)
8399 {
8400         struct drm_i915_private *dev_priv = dev->dev_private;
8401         uint32_t dspclk_gate;
8402
8403         I915_WRITE(RENCLK_GATE_D1, 0);
8404         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8405                    GS_UNIT_CLOCK_GATE_DISABLE |
8406                    CL_UNIT_CLOCK_GATE_DISABLE);
8407         I915_WRITE(RAMCLK_GATE_D, 0);
8408         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8409                 OVRUNIT_CLOCK_GATE_DISABLE |
8410                 OVCUNIT_CLOCK_GATE_DISABLE;
8411         if (IS_GM45(dev))
8412                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8413         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8414 }
8415
8416 static void crestline_init_clock_gating(struct drm_device *dev)
8417 {
8418         struct drm_i915_private *dev_priv = dev->dev_private;
8419
8420         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8421         I915_WRITE(RENCLK_GATE_D2, 0);
8422         I915_WRITE(DSPCLK_GATE_D, 0);
8423         I915_WRITE(RAMCLK_GATE_D, 0);
8424         I915_WRITE16(DEUC, 0);
8425 }
8426
8427 static void broadwater_init_clock_gating(struct drm_device *dev)
8428 {
8429         struct drm_i915_private *dev_priv = dev->dev_private;
8430
8431         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8432                    I965_RCC_CLOCK_GATE_DISABLE |
8433                    I965_RCPB_CLOCK_GATE_DISABLE |
8434                    I965_ISC_CLOCK_GATE_DISABLE |
8435                    I965_FBC_CLOCK_GATE_DISABLE);
8436         I915_WRITE(RENCLK_GATE_D2, 0);
8437 }
8438
8439 static void gen3_init_clock_gating(struct drm_device *dev)
8440 {
8441         struct drm_i915_private *dev_priv = dev->dev_private;
8442         u32 dstate = I915_READ(D_STATE);
8443
8444         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8445                 DSTATE_DOT_CLOCK_GATING;
8446         I915_WRITE(D_STATE, dstate);
8447 }
8448
8449 static void i85x_init_clock_gating(struct drm_device *dev)
8450 {
8451         struct drm_i915_private *dev_priv = dev->dev_private;
8452
8453         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8454 }
8455
8456 static void i830_init_clock_gating(struct drm_device *dev)
8457 {
8458         struct drm_i915_private *dev_priv = dev->dev_private;
8459
8460         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8461 }
8462
8463 static void ibx_init_clock_gating(struct drm_device *dev)
8464 {
8465         struct drm_i915_private *dev_priv = dev->dev_private;
8466
8467         /*
8468          * On Ibex Peak and Cougar Point, we need to disable clock
8469          * gating for the panel power sequencer or it will fail to
8470          * start up when no ports are active.
8471          */
8472         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8473 }
8474
8475 static void cpt_init_clock_gating(struct drm_device *dev)
8476 {
8477         struct drm_i915_private *dev_priv = dev->dev_private;
8478         int pipe;
8479
8480         /*
8481          * On Ibex Peak and Cougar Point, we need to disable clock
8482          * gating for the panel power sequencer or it will fail to
8483          * start up when no ports are active.
8484          */
8485         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8486         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8487                    DPLS_EDP_PPS_FIX_DIS);
8488         /* Without this, mode sets may fail silently on FDI */
8489         for_each_pipe(pipe)
8490                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8491 }
8492
8493 static void ironlake_teardown_rc6(struct drm_device *dev)
8494 {
8495         struct drm_i915_private *dev_priv = dev->dev_private;
8496
8497         if (dev_priv->renderctx) {
8498                 i915_gem_object_unpin(dev_priv->renderctx);
8499                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8500                 dev_priv->renderctx = NULL;
8501         }
8502
8503         if (dev_priv->pwrctx) {
8504                 i915_gem_object_unpin(dev_priv->pwrctx);
8505                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8506                 dev_priv->pwrctx = NULL;
8507         }
8508 }
8509
8510 static void ironlake_disable_rc6(struct drm_device *dev)
8511 {
8512         struct drm_i915_private *dev_priv = dev->dev_private;
8513
8514         if (I915_READ(PWRCTXA)) {
8515                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8516                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8517                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8518                          50);
8519
8520                 I915_WRITE(PWRCTXA, 0);
8521                 POSTING_READ(PWRCTXA);
8522
8523                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8524                 POSTING_READ(RSTDBYCTL);
8525         }
8526
8527         ironlake_teardown_rc6(dev);
8528 }
8529
8530 static int ironlake_setup_rc6(struct drm_device *dev)
8531 {
8532         struct drm_i915_private *dev_priv = dev->dev_private;
8533
8534         if (dev_priv->renderctx == NULL)
8535                 dev_priv->renderctx = intel_alloc_context_page(dev);
8536         if (!dev_priv->renderctx)
8537                 return -ENOMEM;
8538
8539         if (dev_priv->pwrctx == NULL)
8540                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8541         if (!dev_priv->pwrctx) {
8542                 ironlake_teardown_rc6(dev);
8543                 return -ENOMEM;
8544         }
8545
8546         return 0;
8547 }
8548
8549 void ironlake_enable_rc6(struct drm_device *dev)
8550 {
8551         struct drm_i915_private *dev_priv = dev->dev_private;
8552         int ret;
8553
8554         /* rc6 disabled by default due to repeated reports of hanging during
8555          * boot and resume.
8556          */
8557         if (!intel_enable_rc6(dev))
8558                 return;
8559
8560         mutex_lock(&dev->struct_mutex);
8561         ret = ironlake_setup_rc6(dev);
8562         if (ret) {
8563                 mutex_unlock(&dev->struct_mutex);
8564                 return;
8565         }
8566
8567         /*
8568          * GPU can automatically power down the render unit if given a page
8569          * to save state.
8570          */
8571         ret = BEGIN_LP_RING(6);
8572         if (ret) {
8573                 ironlake_teardown_rc6(dev);
8574                 mutex_unlock(&dev->struct_mutex);
8575                 return;
8576         }
8577
8578         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8579         OUT_RING(MI_SET_CONTEXT);
8580         OUT_RING(dev_priv->renderctx->gtt_offset |
8581                  MI_MM_SPACE_GTT |
8582                  MI_SAVE_EXT_STATE_EN |
8583                  MI_RESTORE_EXT_STATE_EN |
8584                  MI_RESTORE_INHIBIT);
8585         OUT_RING(MI_SUSPEND_FLUSH);
8586         OUT_RING(MI_NOOP);
8587         OUT_RING(MI_FLUSH);
8588         ADVANCE_LP_RING();
8589
8590         /*
8591          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8592          * does an implicit flush, combined with MI_FLUSH above, it should be
8593          * safe to assume that renderctx is valid
8594          */
8595         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8596         if (ret) {
8597                 DRM_ERROR("failed to enable ironlake power power savings\n");
8598                 ironlake_teardown_rc6(dev);
8599                 mutex_unlock(&dev->struct_mutex);
8600                 return;
8601         }
8602
8603         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8604         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8605         mutex_unlock(&dev->struct_mutex);
8606 }
8607
8608 void intel_init_clock_gating(struct drm_device *dev)
8609 {
8610         struct drm_i915_private *dev_priv = dev->dev_private;
8611
8612         dev_priv->display.init_clock_gating(dev);
8613
8614         if (dev_priv->display.init_pch_clock_gating)
8615                 dev_priv->display.init_pch_clock_gating(dev);
8616 }
8617
8618 /* Set up chip specific display functions */
8619 static void intel_init_display(struct drm_device *dev)
8620 {
8621         struct drm_i915_private *dev_priv = dev->dev_private;
8622
8623         /* We always want a DPMS function */
8624         if (HAS_PCH_SPLIT(dev)) {
8625                 dev_priv->display.dpms = ironlake_crtc_dpms;
8626                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8627                 dev_priv->display.update_plane = ironlake_update_plane;
8628         } else {
8629                 dev_priv->display.dpms = i9xx_crtc_dpms;
8630                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8631                 dev_priv->display.update_plane = i9xx_update_plane;
8632         }
8633
8634         if (I915_HAS_FBC(dev)) {
8635                 if (HAS_PCH_SPLIT(dev)) {
8636                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8637                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8638                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8639                 } else if (IS_GM45(dev)) {
8640                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8641                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8642                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8643                 } else if (IS_CRESTLINE(dev)) {
8644                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8645                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8646                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8647                 }
8648                 /* 855GM needs testing */
8649         }
8650
8651         /* Returns the core display clock speed */
8652         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8653                 dev_priv->display.get_display_clock_speed =
8654                         i945_get_display_clock_speed;
8655         else if (IS_I915G(dev))
8656                 dev_priv->display.get_display_clock_speed =
8657                         i915_get_display_clock_speed;
8658         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8659                 dev_priv->display.get_display_clock_speed =
8660                         i9xx_misc_get_display_clock_speed;
8661         else if (IS_I915GM(dev))
8662                 dev_priv->display.get_display_clock_speed =
8663                         i915gm_get_display_clock_speed;
8664         else if (IS_I865G(dev))
8665                 dev_priv->display.get_display_clock_speed =
8666                         i865_get_display_clock_speed;
8667         else if (IS_I85X(dev))
8668                 dev_priv->display.get_display_clock_speed =
8669                         i855_get_display_clock_speed;
8670         else /* 852, 830 */
8671                 dev_priv->display.get_display_clock_speed =
8672                         i830_get_display_clock_speed;
8673
8674         /* For FIFO watermark updates */
8675         if (HAS_PCH_SPLIT(dev)) {
8676                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8677                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8678
8679                 /* IVB configs may use multi-threaded forcewake */
8680                 if (IS_IVYBRIDGE(dev)) {
8681                         u32     ecobus;
8682
8683                         mutex_lock(&dev->struct_mutex);
8684                         __gen6_gt_force_wake_mt_get(dev_priv);
8685                         ecobus = I915_READ(ECOBUS);
8686                         __gen6_gt_force_wake_mt_put(dev_priv);
8687                         mutex_unlock(&dev->struct_mutex);
8688
8689                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8690                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8691                                 dev_priv->display.force_wake_get =
8692                                         __gen6_gt_force_wake_mt_get;
8693                                 dev_priv->display.force_wake_put =
8694                                         __gen6_gt_force_wake_mt_put;
8695                         }
8696                 }
8697
8698                 if (HAS_PCH_IBX(dev))
8699                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8700                 else if (HAS_PCH_CPT(dev))
8701                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8702
8703                 if (IS_GEN5(dev)) {
8704                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8705                                 dev_priv->display.update_wm = ironlake_update_wm;
8706                         else {
8707                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8708                                               "Disable CxSR\n");
8709                                 dev_priv->display.update_wm = NULL;
8710                         }
8711                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8712                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8713                         dev_priv->display.write_eld = ironlake_write_eld;
8714                 } else if (IS_GEN6(dev)) {
8715                         if (SNB_READ_WM0_LATENCY()) {
8716                                 dev_priv->display.update_wm = sandybridge_update_wm;
8717                         } else {
8718                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8719                                               "Disable CxSR\n");
8720                                 dev_priv->display.update_wm = NULL;
8721                         }
8722                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8723                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8724                         dev_priv->display.write_eld = ironlake_write_eld;
8725                 } else if (IS_IVYBRIDGE(dev)) {
8726                         /* FIXME: detect B0+ stepping and use auto training */
8727                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8728                         if (SNB_READ_WM0_LATENCY()) {
8729                                 dev_priv->display.update_wm = sandybridge_update_wm;
8730                         } else {
8731                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8732                                               "Disable CxSR\n");
8733                                 dev_priv->display.update_wm = NULL;
8734                         }
8735                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8736                         dev_priv->display.write_eld = ironlake_write_eld;
8737                 } else
8738                         dev_priv->display.update_wm = NULL;
8739         } else if (IS_PINEVIEW(dev)) {
8740                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8741                                             dev_priv->is_ddr3,
8742                                             dev_priv->fsb_freq,
8743                                             dev_priv->mem_freq)) {
8744                         DRM_INFO("failed to find known CxSR latency "
8745                                  "(found ddr%s fsb freq %d, mem freq %d), "
8746                                  "disabling CxSR\n",
8747                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8748                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8749                         /* Disable CxSR and never update its watermark again */
8750                         pineview_disable_cxsr(dev);
8751                         dev_priv->display.update_wm = NULL;
8752                 } else
8753                         dev_priv->display.update_wm = pineview_update_wm;
8754                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8755         } else if (IS_G4X(dev)) {
8756                 dev_priv->display.write_eld = g4x_write_eld;
8757                 dev_priv->display.update_wm = g4x_update_wm;
8758                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8759         } else if (IS_GEN4(dev)) {
8760                 dev_priv->display.update_wm = i965_update_wm;
8761                 if (IS_CRESTLINE(dev))
8762                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8763                 else if (IS_BROADWATER(dev))
8764                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8765         } else if (IS_GEN3(dev)) {
8766                 dev_priv->display.update_wm = i9xx_update_wm;
8767                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8768                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8769         } else if (IS_I865G(dev)) {
8770                 dev_priv->display.update_wm = i830_update_wm;
8771                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8772                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8773         } else if (IS_I85X(dev)) {
8774                 dev_priv->display.update_wm = i9xx_update_wm;
8775                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8776                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8777         } else {
8778                 dev_priv->display.update_wm = i830_update_wm;
8779                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8780                 if (IS_845G(dev))
8781                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8782                 else
8783                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8784         }
8785
8786         /* Default just returns -ENODEV to indicate unsupported */
8787         dev_priv->display.queue_flip = intel_default_queue_flip;
8788
8789         switch (INTEL_INFO(dev)->gen) {
8790         case 2:
8791                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8792                 break;
8793
8794         case 3:
8795                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8796                 break;
8797
8798         case 4:
8799         case 5:
8800                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8801                 break;
8802
8803         case 6:
8804                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8805                 break;
8806         case 7:
8807                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8808                 break;
8809         }
8810 }
8811
8812 /*
8813  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8814  * resume, or other times.  This quirk makes sure that's the case for
8815  * affected systems.
8816  */
8817 static void quirk_pipea_force(struct drm_device *dev)
8818 {
8819         struct drm_i915_private *dev_priv = dev->dev_private;
8820
8821         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8822         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8823 }
8824
8825 /*
8826  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8827  */
8828 static void quirk_ssc_force_disable(struct drm_device *dev)
8829 {
8830         struct drm_i915_private *dev_priv = dev->dev_private;
8831         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8832 }
8833
8834 /*
8835  * A machine may need to invert the panel backlight brightness value
8836  */
8837 static void quirk_invert_brightness(struct drm_device *dev)
8838 {
8839         struct drm_i915_private *dev_priv = dev->dev_private;
8840         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8841 }
8842
8843 struct intel_quirk {
8844         int device;
8845         int subsystem_vendor;
8846         int subsystem_device;
8847         void (*hook)(struct drm_device *dev);
8848 };
8849
8850 struct intel_quirk intel_quirks[] = {
8851         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8852         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8853         /* HP Mini needs pipe A force quirk (LP: #322104) */
8854         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8855
8856         /* Thinkpad R31 needs pipe A force quirk */
8857         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8858         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8859         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8860
8861         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8862         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8863         /* ThinkPad X40 needs pipe A force quirk */
8864
8865         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8866         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8867
8868         /* 855 & before need to leave pipe A & dpll A up */
8869         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8870         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8871
8872         /* Lenovo U160 cannot use SSC on LVDS */
8873         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8874
8875         /* Sony Vaio Y cannot use SSC on LVDS */
8876         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8877 };
8878
8879 static void intel_init_quirks(struct drm_device *dev)
8880 {
8881         struct pci_dev *d = dev->pdev;
8882         int i;
8883
8884         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8885                 struct intel_quirk *q = &intel_quirks[i];
8886
8887                 if (d->device == q->device &&
8888                     (d->subsystem_vendor == q->subsystem_vendor ||
8889                      q->subsystem_vendor == PCI_ANY_ID) &&
8890                     (d->subsystem_device == q->subsystem_device ||
8891                      q->subsystem_device == PCI_ANY_ID))
8892                         q->hook(dev);
8893         }
8894 }
8895
8896 /* Disable the VGA plane that we never use */
8897 static void i915_disable_vga(struct drm_device *dev)
8898 {
8899         struct drm_i915_private *dev_priv = dev->dev_private;
8900         u8 sr1;
8901         u32 vga_reg;
8902
8903         if (HAS_PCH_SPLIT(dev))
8904                 vga_reg = CPU_VGACNTRL;
8905         else
8906                 vga_reg = VGACNTRL;
8907
8908         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8909         outb(1, VGA_SR_INDEX);
8910         sr1 = inb(VGA_SR_DATA);
8911         outb(sr1 | 1<<5, VGA_SR_DATA);
8912         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8913         udelay(300);
8914
8915         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8916         POSTING_READ(vga_reg);
8917 }
8918
8919 void i915_redisable_vga(struct drm_device *dev)
8920 {
8921         struct drm_i915_private *dev_priv = dev->dev_private;
8922         u32 vga_reg;
8923
8924         if (HAS_PCH_SPLIT(dev))
8925                 vga_reg = CPU_VGACNTRL;
8926         else
8927                 vga_reg = VGACNTRL;
8928
8929         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8930                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8931                 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8932                 POSTING_READ(vga_reg);
8933         }
8934 }
8935
8936 void intel_modeset_init(struct drm_device *dev)
8937 {
8938         struct drm_i915_private *dev_priv = dev->dev_private;
8939         int i;
8940
8941         drm_mode_config_init(dev);
8942
8943         dev->mode_config.min_width = 0;
8944         dev->mode_config.min_height = 0;
8945
8946         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8947
8948         intel_init_quirks(dev);
8949
8950         intel_init_display(dev);
8951
8952         if (IS_GEN2(dev)) {
8953                 dev->mode_config.max_width = 2048;
8954                 dev->mode_config.max_height = 2048;
8955         } else if (IS_GEN3(dev)) {
8956                 dev->mode_config.max_width = 4096;
8957                 dev->mode_config.max_height = 4096;
8958         } else {
8959                 dev->mode_config.max_width = 8192;
8960                 dev->mode_config.max_height = 8192;
8961         }
8962         dev->mode_config.fb_base = dev->agp->base;
8963
8964         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8965                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8966
8967         for (i = 0; i < dev_priv->num_pipe; i++) {
8968                 intel_crtc_init(dev, i);
8969         }
8970
8971         /* Just disable it once at startup */
8972         i915_disable_vga(dev);
8973         intel_setup_outputs(dev);
8974
8975         intel_init_clock_gating(dev);
8976
8977         if (IS_IRONLAKE_M(dev)) {
8978                 ironlake_enable_drps(dev);
8979                 intel_init_emon(dev);
8980         }
8981
8982         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8983                 gen6_enable_rps(dev_priv);
8984                 gen6_update_ring_freq(dev_priv);
8985         }
8986
8987         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8988         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8989                     (unsigned long)dev);
8990 }
8991
8992 void intel_modeset_gem_init(struct drm_device *dev)
8993 {
8994         if (IS_IRONLAKE_M(dev))
8995                 ironlake_enable_rc6(dev);
8996
8997         intel_setup_overlay(dev);
8998 }
8999
9000 void intel_modeset_cleanup(struct drm_device *dev)
9001 {
9002         struct drm_i915_private *dev_priv = dev->dev_private;
9003         struct drm_crtc *crtc;
9004         struct intel_crtc *intel_crtc;
9005
9006         drm_kms_helper_poll_fini(dev);
9007         mutex_lock(&dev->struct_mutex);
9008
9009         intel_unregister_dsm_handler();
9010
9011
9012         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9013                 /* Skip inactive CRTCs */
9014                 if (!crtc->fb)
9015                         continue;
9016
9017                 intel_crtc = to_intel_crtc(crtc);
9018                 intel_increase_pllclock(crtc);
9019         }
9020
9021         intel_disable_fbc(dev);
9022
9023         if (IS_IRONLAKE_M(dev))
9024                 ironlake_disable_drps(dev);
9025         if (IS_GEN6(dev) || IS_GEN7(dev))
9026                 gen6_disable_rps(dev);
9027
9028         if (IS_IRONLAKE_M(dev))
9029                 ironlake_disable_rc6(dev);
9030
9031         mutex_unlock(&dev->struct_mutex);
9032
9033         /* Disable the irq before mode object teardown, for the irq might
9034          * enqueue unpin/hotplug work. */
9035         drm_irq_uninstall(dev);
9036         cancel_work_sync(&dev_priv->hotplug_work);
9037         cancel_work_sync(&dev_priv->rps_work);
9038
9039         /* flush any delayed tasks or pending work */
9040         flush_scheduled_work();
9041
9042         /* Shut off idle work before the crtcs get freed. */
9043         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9044                 intel_crtc = to_intel_crtc(crtc);
9045                 del_timer_sync(&intel_crtc->idle_timer);
9046         }
9047         del_timer_sync(&dev_priv->idle_timer);
9048         cancel_work_sync(&dev_priv->idle_work);
9049
9050         drm_mode_config_cleanup(dev);
9051 }
9052
9053 /*
9054  * Return which encoder is currently attached for connector.
9055  */
9056 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9057 {
9058         return &intel_attached_encoder(connector)->base;
9059 }
9060
9061 void intel_connector_attach_encoder(struct intel_connector *connector,
9062                                     struct intel_encoder *encoder)
9063 {
9064         connector->encoder = encoder;
9065         drm_mode_connector_attach_encoder(&connector->base,
9066                                           &encoder->base);
9067 }
9068
9069 /*
9070  * set vga decode state - true == enable VGA decode
9071  */
9072 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9073 {
9074         struct drm_i915_private *dev_priv = dev->dev_private;
9075         u16 gmch_ctrl;
9076
9077         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9078         if (state)
9079                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9080         else
9081                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9082         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9083         return 0;
9084 }
9085
9086 #ifdef CONFIG_DEBUG_FS
9087 #include <linux/seq_file.h>
9088
9089 struct intel_display_error_state {
9090         struct intel_cursor_error_state {
9091                 u32 control;
9092                 u32 position;
9093                 u32 base;
9094                 u32 size;
9095         } cursor[2];
9096
9097         struct intel_pipe_error_state {
9098                 u32 conf;
9099                 u32 source;
9100
9101                 u32 htotal;
9102                 u32 hblank;
9103                 u32 hsync;
9104                 u32 vtotal;
9105                 u32 vblank;
9106                 u32 vsync;
9107         } pipe[2];
9108
9109         struct intel_plane_error_state {
9110                 u32 control;
9111                 u32 stride;
9112                 u32 size;
9113                 u32 pos;
9114                 u32 addr;
9115                 u32 surface;
9116                 u32 tile_offset;
9117         } plane[2];
9118 };
9119
9120 struct intel_display_error_state *
9121 intel_display_capture_error_state(struct drm_device *dev)
9122 {
9123         drm_i915_private_t *dev_priv = dev->dev_private;
9124         struct intel_display_error_state *error;
9125         int i;
9126
9127         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9128         if (error == NULL)
9129                 return NULL;
9130
9131         for (i = 0; i < 2; i++) {
9132                 error->cursor[i].control = I915_READ(CURCNTR(i));
9133                 error->cursor[i].position = I915_READ(CURPOS(i));
9134                 error->cursor[i].base = I915_READ(CURBASE(i));
9135
9136                 error->plane[i].control = I915_READ(DSPCNTR(i));
9137                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9138                 error->plane[i].size = I915_READ(DSPSIZE(i));
9139                 error->plane[i].pos = I915_READ(DSPPOS(i));
9140                 error->plane[i].addr = I915_READ(DSPADDR(i));
9141                 if (INTEL_INFO(dev)->gen >= 4) {
9142                         error->plane[i].surface = I915_READ(DSPSURF(i));
9143                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9144                 }
9145
9146                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9147                 error->pipe[i].source = I915_READ(PIPESRC(i));
9148                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9149                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9150                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9151                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9152                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9153                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9154         }
9155
9156         return error;
9157 }
9158
9159 void
9160 intel_display_print_error_state(struct seq_file *m,
9161                                 struct drm_device *dev,
9162                                 struct intel_display_error_state *error)
9163 {
9164         int i;
9165
9166         for (i = 0; i < 2; i++) {
9167                 seq_printf(m, "Pipe [%d]:\n", i);
9168                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9169                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9170                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9171                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9172                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9173                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9174                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9175                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9176
9177                 seq_printf(m, "Plane [%d]:\n", i);
9178                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9179                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9180                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9181                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9182                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9183                 if (INTEL_INFO(dev)->gen >= 4) {
9184                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9185                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9186                 }
9187
9188                 seq_printf(m, "Cursor [%d]:\n", i);
9189                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9190                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9191                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9192         }
9193 }
9194 #endif