drm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS
[pandora-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41
42 #include "drm_crtc_helper.h"
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52         /* given values */
53         int n;
54         int m1, m2;
55         int p1, p2;
56         /* derived values */
57         int     dot;
58         int     vco;
59         int     m;
60         int     p;
61 } intel_clock_t;
62
63 typedef struct {
64         int     min, max;
65 } intel_range_t;
66
67 typedef struct {
68         int     dot_limit;
69         int     p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM                  2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
76         intel_p2_t          p2;
77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78                         int, int, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86                     int target, int refclk, intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89                         int target, int refclk, intel_clock_t *best_clock);
90
91 static bool
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93                       int target, int refclk, intel_clock_t *best_clock);
94 static bool
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96                            int target, int refclk, intel_clock_t *best_clock);
97
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
100 {
101         if (IS_GEN5(dev)) {
102                 struct drm_i915_private *dev_priv = dev->dev_private;
103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104         } else
105                 return 27;
106 }
107
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109         .dot = { .min = 25000, .max = 350000 },
110         .vco = { .min = 930000, .max = 1400000 },
111         .n = { .min = 3, .max = 16 },
112         .m = { .min = 96, .max = 140 },
113         .m1 = { .min = 18, .max = 26 },
114         .m2 = { .min = 6, .max = 16 },
115         .p = { .min = 4, .max = 128 },
116         .p1 = { .min = 2, .max = 33 },
117         .p2 = { .dot_limit = 165000,
118                 .p2_slow = 4, .p2_fast = 2 },
119         .find_pll = intel_find_best_PLL,
120 };
121
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123         .dot = { .min = 25000, .max = 350000 },
124         .vco = { .min = 930000, .max = 1400000 },
125         .n = { .min = 3, .max = 16 },
126         .m = { .min = 96, .max = 140 },
127         .m1 = { .min = 18, .max = 26 },
128         .m2 = { .min = 6, .max = 16 },
129         .p = { .min = 4, .max = 128 },
130         .p1 = { .min = 1, .max = 6 },
131         .p2 = { .dot_limit = 165000,
132                 .p2_slow = 14, .p2_fast = 7 },
133         .find_pll = intel_find_best_PLL,
134 };
135
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137         .dot = { .min = 20000, .max = 400000 },
138         .vco = { .min = 1400000, .max = 2800000 },
139         .n = { .min = 1, .max = 6 },
140         .m = { .min = 70, .max = 120 },
141         .m1 = { .min = 10, .max = 22 },
142         .m2 = { .min = 5, .max = 9 },
143         .p = { .min = 5, .max = 80 },
144         .p1 = { .min = 1, .max = 8 },
145         .p2 = { .dot_limit = 200000,
146                 .p2_slow = 10, .p2_fast = 5 },
147         .find_pll = intel_find_best_PLL,
148 };
149
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151         .dot = { .min = 20000, .max = 400000 },
152         .vco = { .min = 1400000, .max = 2800000 },
153         .n = { .min = 1, .max = 6 },
154         .m = { .min = 70, .max = 120 },
155         .m1 = { .min = 10, .max = 22 },
156         .m2 = { .min = 5, .max = 9 },
157         .p = { .min = 7, .max = 98 },
158         .p1 = { .min = 1, .max = 8 },
159         .p2 = { .dot_limit = 112000,
160                 .p2_slow = 14, .p2_fast = 7 },
161         .find_pll = intel_find_best_PLL,
162 };
163
164
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166         .dot = { .min = 25000, .max = 270000 },
167         .vco = { .min = 1750000, .max = 3500000},
168         .n = { .min = 1, .max = 4 },
169         .m = { .min = 104, .max = 138 },
170         .m1 = { .min = 17, .max = 23 },
171         .m2 = { .min = 5, .max = 11 },
172         .p = { .min = 10, .max = 30 },
173         .p1 = { .min = 1, .max = 3},
174         .p2 = { .dot_limit = 270000,
175                 .p2_slow = 10,
176                 .p2_fast = 10
177         },
178         .find_pll = intel_g4x_find_best_PLL,
179 };
180
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182         .dot = { .min = 22000, .max = 400000 },
183         .vco = { .min = 1750000, .max = 3500000},
184         .n = { .min = 1, .max = 4 },
185         .m = { .min = 104, .max = 138 },
186         .m1 = { .min = 16, .max = 23 },
187         .m2 = { .min = 5, .max = 11 },
188         .p = { .min = 5, .max = 80 },
189         .p1 = { .min = 1, .max = 8},
190         .p2 = { .dot_limit = 165000,
191                 .p2_slow = 10, .p2_fast = 5 },
192         .find_pll = intel_g4x_find_best_PLL,
193 };
194
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196         .dot = { .min = 20000, .max = 115000 },
197         .vco = { .min = 1750000, .max = 3500000 },
198         .n = { .min = 1, .max = 3 },
199         .m = { .min = 104, .max = 138 },
200         .m1 = { .min = 17, .max = 23 },
201         .m2 = { .min = 5, .max = 11 },
202         .p = { .min = 28, .max = 112 },
203         .p1 = { .min = 2, .max = 8 },
204         .p2 = { .dot_limit = 0,
205                 .p2_slow = 14, .p2_fast = 14
206         },
207         .find_pll = intel_g4x_find_best_PLL,
208 };
209
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211         .dot = { .min = 80000, .max = 224000 },
212         .vco = { .min = 1750000, .max = 3500000 },
213         .n = { .min = 1, .max = 3 },
214         .m = { .min = 104, .max = 138 },
215         .m1 = { .min = 17, .max = 23 },
216         .m2 = { .min = 5, .max = 11 },
217         .p = { .min = 14, .max = 42 },
218         .p1 = { .min = 2, .max = 6 },
219         .p2 = { .dot_limit = 0,
220                 .p2_slow = 7, .p2_fast = 7
221         },
222         .find_pll = intel_g4x_find_best_PLL,
223 };
224
225 static const intel_limit_t intel_limits_g4x_display_port = {
226         .dot = { .min = 161670, .max = 227000 },
227         .vco = { .min = 1750000, .max = 3500000},
228         .n = { .min = 1, .max = 2 },
229         .m = { .min = 97, .max = 108 },
230         .m1 = { .min = 0x10, .max = 0x12 },
231         .m2 = { .min = 0x05, .max = 0x06 },
232         .p = { .min = 10, .max = 20 },
233         .p1 = { .min = 1, .max = 2},
234         .p2 = { .dot_limit = 0,
235                 .p2_slow = 10, .p2_fast = 10 },
236         .find_pll = intel_find_pll_g4x_dp,
237 };
238
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240         .dot = { .min = 20000, .max = 400000},
241         .vco = { .min = 1700000, .max = 3500000 },
242         /* Pineview's Ncounter is a ring counter */
243         .n = { .min = 3, .max = 6 },
244         .m = { .min = 2, .max = 256 },
245         /* Pineview only has one combined m divider, which we treat as m2. */
246         .m1 = { .min = 0, .max = 0 },
247         .m2 = { .min = 0, .max = 254 },
248         .p = { .min = 5, .max = 80 },
249         .p1 = { .min = 1, .max = 8 },
250         .p2 = { .dot_limit = 200000,
251                 .p2_slow = 10, .p2_fast = 5 },
252         .find_pll = intel_find_best_PLL,
253 };
254
255 static const intel_limit_t intel_limits_pineview_lvds = {
256         .dot = { .min = 20000, .max = 400000 },
257         .vco = { .min = 1700000, .max = 3500000 },
258         .n = { .min = 3, .max = 6 },
259         .m = { .min = 2, .max = 256 },
260         .m1 = { .min = 0, .max = 0 },
261         .m2 = { .min = 0, .max = 254 },
262         .p = { .min = 7, .max = 112 },
263         .p1 = { .min = 1, .max = 8 },
264         .p2 = { .dot_limit = 112000,
265                 .p2_slow = 14, .p2_fast = 14 },
266         .find_pll = intel_find_best_PLL,
267 };
268
269 /* Ironlake / Sandybridge
270  *
271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
272  * the range value for them is (actual_value - 2).
273  */
274 static const intel_limit_t intel_limits_ironlake_dac = {
275         .dot = { .min = 25000, .max = 350000 },
276         .vco = { .min = 1760000, .max = 3510000 },
277         .n = { .min = 1, .max = 5 },
278         .m = { .min = 79, .max = 127 },
279         .m1 = { .min = 12, .max = 22 },
280         .m2 = { .min = 5, .max = 9 },
281         .p = { .min = 5, .max = 80 },
282         .p1 = { .min = 1, .max = 8 },
283         .p2 = { .dot_limit = 225000,
284                 .p2_slow = 10, .p2_fast = 5 },
285         .find_pll = intel_g4x_find_best_PLL,
286 };
287
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289         .dot = { .min = 25000, .max = 350000 },
290         .vco = { .min = 1760000, .max = 3510000 },
291         .n = { .min = 1, .max = 3 },
292         .m = { .min = 79, .max = 118 },
293         .m1 = { .min = 12, .max = 22 },
294         .m2 = { .min = 5, .max = 9 },
295         .p = { .min = 28, .max = 112 },
296         .p1 = { .min = 2, .max = 8 },
297         .p2 = { .dot_limit = 225000,
298                 .p2_slow = 14, .p2_fast = 14 },
299         .find_pll = intel_g4x_find_best_PLL,
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303         .dot = { .min = 25000, .max = 350000 },
304         .vco = { .min = 1760000, .max = 3510000 },
305         .n = { .min = 1, .max = 3 },
306         .m = { .min = 79, .max = 127 },
307         .m1 = { .min = 12, .max = 22 },
308         .m2 = { .min = 5, .max = 9 },
309         .p = { .min = 14, .max = 56 },
310         .p1 = { .min = 2, .max = 8 },
311         .p2 = { .dot_limit = 225000,
312                 .p2_slow = 7, .p2_fast = 7 },
313         .find_pll = intel_g4x_find_best_PLL,
314 };
315
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318         .dot = { .min = 25000, .max = 350000 },
319         .vco = { .min = 1760000, .max = 3510000 },
320         .n = { .min = 1, .max = 2 },
321         .m = { .min = 79, .max = 126 },
322         .m1 = { .min = 12, .max = 22 },
323         .m2 = { .min = 5, .max = 9 },
324         .p = { .min = 28, .max = 112 },
325         .p1 = { .min = 2, .max = 8 },
326         .p2 = { .dot_limit = 225000,
327                 .p2_slow = 14, .p2_fast = 14 },
328         .find_pll = intel_g4x_find_best_PLL,
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332         .dot = { .min = 25000, .max = 350000 },
333         .vco = { .min = 1760000, .max = 3510000 },
334         .n = { .min = 1, .max = 3 },
335         .m = { .min = 79, .max = 126 },
336         .m1 = { .min = 12, .max = 22 },
337         .m2 = { .min = 5, .max = 9 },
338         .p = { .min = 14, .max = 42 },
339         .p1 = { .min = 2, .max = 6 },
340         .p2 = { .dot_limit = 225000,
341                 .p2_slow = 7, .p2_fast = 7 },
342         .find_pll = intel_g4x_find_best_PLL,
343 };
344
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346         .dot = { .min = 25000, .max = 350000 },
347         .vco = { .min = 1760000, .max = 3510000},
348         .n = { .min = 1, .max = 2 },
349         .m = { .min = 81, .max = 90 },
350         .m1 = { .min = 12, .max = 22 },
351         .m2 = { .min = 5, .max = 9 },
352         .p = { .min = 10, .max = 20 },
353         .p1 = { .min = 1, .max = 2},
354         .p2 = { .dot_limit = 0,
355                 .p2_slow = 10, .p2_fast = 10 },
356         .find_pll = intel_find_pll_ironlake_dp,
357 };
358
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360                                                 int refclk)
361 {
362         struct drm_device *dev = crtc->dev;
363         struct drm_i915_private *dev_priv = dev->dev_private;
364         const intel_limit_t *limit;
365
366         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368                     LVDS_CLKB_POWER_UP) {
369                         /* LVDS dual channel */
370                         if (refclk == 100000)
371                                 limit = &intel_limits_ironlake_dual_lvds_100m;
372                         else
373                                 limit = &intel_limits_ironlake_dual_lvds;
374                 } else {
375                         if (refclk == 100000)
376                                 limit = &intel_limits_ironlake_single_lvds_100m;
377                         else
378                                 limit = &intel_limits_ironlake_single_lvds;
379                 }
380         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381                         HAS_eDP)
382                 limit = &intel_limits_ironlake_display_port;
383         else
384                 limit = &intel_limits_ironlake_dac;
385
386         return limit;
387 }
388
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 {
391         struct drm_device *dev = crtc->dev;
392         struct drm_i915_private *dev_priv = dev->dev_private;
393         const intel_limit_t *limit;
394
395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397                     LVDS_CLKB_POWER_UP)
398                         /* LVDS with dual channel */
399                         limit = &intel_limits_g4x_dual_channel_lvds;
400                 else
401                         /* LVDS with dual channel */
402                         limit = &intel_limits_g4x_single_channel_lvds;
403         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405                 limit = &intel_limits_g4x_hdmi;
406         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407                 limit = &intel_limits_g4x_sdvo;
408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409                 limit = &intel_limits_g4x_display_port;
410         } else /* The option is for other outputs */
411                 limit = &intel_limits_i9xx_sdvo;
412
413         return limit;
414 }
415
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 {
418         struct drm_device *dev = crtc->dev;
419         const intel_limit_t *limit;
420
421         if (HAS_PCH_SPLIT(dev))
422                 limit = intel_ironlake_limit(crtc, refclk);
423         else if (IS_G4X(dev)) {
424                 limit = intel_g4x_limit(crtc);
425         } else if (IS_PINEVIEW(dev)) {
426                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427                         limit = &intel_limits_pineview_lvds;
428                 else
429                         limit = &intel_limits_pineview_sdvo;
430         } else if (!IS_GEN2(dev)) {
431                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432                         limit = &intel_limits_i9xx_lvds;
433                 else
434                         limit = &intel_limits_i9xx_sdvo;
435         } else {
436                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437                         limit = &intel_limits_i8xx_lvds;
438                 else
439                         limit = &intel_limits_i8xx_dvo;
440         }
441         return limit;
442 }
443
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
446 {
447         clock->m = clock->m2 + 2;
448         clock->p = clock->p1 * clock->p2;
449         clock->vco = refclk * clock->m / clock->n;
450         clock->dot = clock->vco / clock->p;
451 }
452
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 {
455         if (IS_PINEVIEW(dev)) {
456                 pineview_clock(refclk, clock);
457                 return;
458         }
459         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460         clock->p = clock->p1 * clock->p2;
461         clock->vco = refclk * clock->m / (clock->n + 2);
462         clock->dot = clock->vco / clock->p;
463 }
464
465 /**
466  * Returns whether any output on the specified pipe is of the specified type
467  */
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 {
470         struct drm_device *dev = crtc->dev;
471         struct drm_mode_config *mode_config = &dev->mode_config;
472         struct intel_encoder *encoder;
473
474         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475                 if (encoder->base.crtc == crtc && encoder->type == type)
476                         return true;
477
478         return false;
479 }
480
481 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
482 /**
483  * Returns whether the given set of divisors are valid for a given refclk with
484  * the given connectors.
485  */
486
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488                                const intel_limit_t *limit,
489                                const intel_clock_t *clock)
490 {
491         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
492                 INTELPllInvalid("p1 out of range\n");
493         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
494                 INTELPllInvalid("p out of range\n");
495         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
496                 INTELPllInvalid("m2 out of range\n");
497         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
498                 INTELPllInvalid("m1 out of range\n");
499         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500                 INTELPllInvalid("m1 <= m2\n");
501         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
502                 INTELPllInvalid("m out of range\n");
503         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
504                 INTELPllInvalid("n out of range\n");
505         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506                 INTELPllInvalid("vco out of range\n");
507         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508          * connector, etc., rather than just a single range.
509          */
510         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511                 INTELPllInvalid("dot out of range\n");
512
513         return true;
514 }
515
516 static bool
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518                     int target, int refclk, intel_clock_t *best_clock)
519
520 {
521         struct drm_device *dev = crtc->dev;
522         struct drm_i915_private *dev_priv = dev->dev_private;
523         intel_clock_t clock;
524         int err = target;
525
526         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527             (I915_READ(LVDS)) != 0) {
528                 /*
529                  * For LVDS, if the panel is on, just rely on its current
530                  * settings for dual-channel.  We haven't figured out how to
531                  * reliably set up different single/dual channel state, if we
532                  * even can.
533                  */
534                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535                     LVDS_CLKB_POWER_UP)
536                         clock.p2 = limit->p2.p2_fast;
537                 else
538                         clock.p2 = limit->p2.p2_slow;
539         } else {
540                 if (target < limit->p2.dot_limit)
541                         clock.p2 = limit->p2.p2_slow;
542                 else
543                         clock.p2 = limit->p2.p2_fast;
544         }
545
546         memset(best_clock, 0, sizeof(*best_clock));
547
548         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549              clock.m1++) {
550                 for (clock.m2 = limit->m2.min;
551                      clock.m2 <= limit->m2.max; clock.m2++) {
552                         /* m1 is always 0 in Pineview */
553                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554                                 break;
555                         for (clock.n = limit->n.min;
556                              clock.n <= limit->n.max; clock.n++) {
557                                 for (clock.p1 = limit->p1.min;
558                                         clock.p1 <= limit->p1.max; clock.p1++) {
559                                         int this_err;
560
561                                         intel_clock(dev, refclk, &clock);
562                                         if (!intel_PLL_is_valid(dev, limit,
563                                                                 &clock))
564                                                 continue;
565
566                                         this_err = abs(clock.dot - target);
567                                         if (this_err < err) {
568                                                 *best_clock = clock;
569                                                 err = this_err;
570                                         }
571                                 }
572                         }
573                 }
574         }
575
576         return (err != target);
577 }
578
579 static bool
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581                         int target, int refclk, intel_clock_t *best_clock)
582 {
583         struct drm_device *dev = crtc->dev;
584         struct drm_i915_private *dev_priv = dev->dev_private;
585         intel_clock_t clock;
586         int max_n;
587         bool found;
588         /* approximately equals target * 0.00585 */
589         int err_most = (target >> 8) + (target >> 9);
590         found = false;
591
592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593                 int lvds_reg;
594
595                 if (HAS_PCH_SPLIT(dev))
596                         lvds_reg = PCH_LVDS;
597                 else
598                         lvds_reg = LVDS;
599                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600                     LVDS_CLKB_POWER_UP)
601                         clock.p2 = limit->p2.p2_fast;
602                 else
603                         clock.p2 = limit->p2.p2_slow;
604         } else {
605                 if (target < limit->p2.dot_limit)
606                         clock.p2 = limit->p2.p2_slow;
607                 else
608                         clock.p2 = limit->p2.p2_fast;
609         }
610
611         memset(best_clock, 0, sizeof(*best_clock));
612         max_n = limit->n.max;
613         /* based on hardware requirement, prefer smaller n to precision */
614         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615                 /* based on hardware requirement, prefere larger m1,m2 */
616                 for (clock.m1 = limit->m1.max;
617                      clock.m1 >= limit->m1.min; clock.m1--) {
618                         for (clock.m2 = limit->m2.max;
619                              clock.m2 >= limit->m2.min; clock.m2--) {
620                                 for (clock.p1 = limit->p1.max;
621                                      clock.p1 >= limit->p1.min; clock.p1--) {
622                                         int this_err;
623
624                                         intel_clock(dev, refclk, &clock);
625                                         if (!intel_PLL_is_valid(dev, limit,
626                                                                 &clock))
627                                                 continue;
628
629                                         this_err = abs(clock.dot - target);
630                                         if (this_err < err_most) {
631                                                 *best_clock = clock;
632                                                 err_most = this_err;
633                                                 max_n = clock.n;
634                                                 found = true;
635                                         }
636                                 }
637                         }
638                 }
639         }
640         return found;
641 }
642
643 static bool
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645                            int target, int refclk, intel_clock_t *best_clock)
646 {
647         struct drm_device *dev = crtc->dev;
648         intel_clock_t clock;
649
650         if (target < 200000) {
651                 clock.n = 1;
652                 clock.p1 = 2;
653                 clock.p2 = 10;
654                 clock.m1 = 12;
655                 clock.m2 = 9;
656         } else {
657                 clock.n = 2;
658                 clock.p1 = 1;
659                 clock.p2 = 10;
660                 clock.m1 = 14;
661                 clock.m2 = 8;
662         }
663         intel_clock(dev, refclk, &clock);
664         memcpy(best_clock, &clock, sizeof(intel_clock_t));
665         return true;
666 }
667
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 static bool
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671                       int target, int refclk, intel_clock_t *best_clock)
672 {
673         intel_clock_t clock;
674         if (target < 200000) {
675                 clock.p1 = 2;
676                 clock.p2 = 10;
677                 clock.n = 2;
678                 clock.m1 = 23;
679                 clock.m2 = 8;
680         } else {
681                 clock.p1 = 1;
682                 clock.p2 = 10;
683                 clock.n = 1;
684                 clock.m1 = 14;
685                 clock.m2 = 2;
686         }
687         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688         clock.p = (clock.p1 * clock.p2);
689         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690         clock.vco = 0;
691         memcpy(best_clock, &clock, sizeof(intel_clock_t));
692         return true;
693 }
694
695 /**
696  * intel_wait_for_vblank - wait for vblank on a given pipe
697  * @dev: drm device
698  * @pipe: pipe to wait for
699  *
700  * Wait for vblank to occur on a given pipe.  Needed for various bits of
701  * mode setting code.
702  */
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 {
705         struct drm_i915_private *dev_priv = dev->dev_private;
706         int pipestat_reg = PIPESTAT(pipe);
707
708         /* Clear existing vblank status. Note this will clear any other
709          * sticky status fields as well.
710          *
711          * This races with i915_driver_irq_handler() with the result
712          * that either function could miss a vblank event.  Here it is not
713          * fatal, as we will either wait upon the next vblank interrupt or
714          * timeout.  Generally speaking intel_wait_for_vblank() is only
715          * called during modeset at which time the GPU should be idle and
716          * should *not* be performing page flips and thus not waiting on
717          * vblanks...
718          * Currently, the result of us stealing a vblank from the irq
719          * handler is that a single frame will be skipped during swapbuffers.
720          */
721         I915_WRITE(pipestat_reg,
722                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
724         /* Wait for vblank interrupt bit to set */
725         if (wait_for(I915_READ(pipestat_reg) &
726                      PIPE_VBLANK_INTERRUPT_STATUS,
727                      50))
728                 DRM_DEBUG_KMS("vblank wait timed out\n");
729 }
730
731 /*
732  * intel_wait_for_pipe_off - wait for pipe to turn off
733  * @dev: drm device
734  * @pipe: pipe to wait for
735  *
736  * After disabling a pipe, we can't wait for vblank in the usual way,
737  * spinning on the vblank interrupt status bit, since we won't actually
738  * see an interrupt when the pipe is disabled.
739  *
740  * On Gen4 and above:
741  *   wait for the pipe register state bit to turn off
742  *
743  * Otherwise:
744  *   wait for the display line value to settle (it usually
745  *   ends up stopping at the start of the next frame).
746  *
747  */
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 {
750         struct drm_i915_private *dev_priv = dev->dev_private;
751
752         if (INTEL_INFO(dev)->gen >= 4) {
753                 int reg = PIPECONF(pipe);
754
755                 /* Wait for the Pipe State to go off */
756                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757                              100))
758                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
759         } else {
760                 u32 last_line;
761                 int reg = PIPEDSL(pipe);
762                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764                 /* Wait for the display line to settle */
765                 do {
766                         last_line = I915_READ(reg) & DSL_LINEMASK;
767                         mdelay(5);
768                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769                          time_after(timeout, jiffies));
770                 if (time_after(jiffies, timeout))
771                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
772         }
773 }
774
775 static const char *state_string(bool enabled)
776 {
777         return enabled ? "on" : "off";
778 }
779
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782                        enum pipe pipe, bool state)
783 {
784         int reg;
785         u32 val;
786         bool cur_state;
787
788         reg = DPLL(pipe);
789         val = I915_READ(reg);
790         cur_state = !!(val & DPLL_VCO_ENABLE);
791         WARN(cur_state != state,
792              "PLL state assertion failure (expected %s, current %s)\n",
793              state_string(state), state_string(cur_state));
794 }
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
798 /* For ILK+ */
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800                            enum pipe pipe, bool state)
801 {
802         int reg;
803         u32 val;
804         bool cur_state;
805
806         if (HAS_PCH_CPT(dev_priv->dev)) {
807                 u32 pch_dpll;
808
809                 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811                 /* Make sure the selected PLL is enabled to the transcoder */
812                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813                      "transcoder %d PLL not enabled\n", pipe);
814
815                 /* Convert the transcoder pipe number to a pll pipe number */
816                 pipe = (pch_dpll >> (4 * pipe)) & 1;
817         }
818
819         reg = PCH_DPLL(pipe);
820         val = I915_READ(reg);
821         cur_state = !!(val & DPLL_VCO_ENABLE);
822         WARN(cur_state != state,
823              "PCH PLL state assertion failure (expected %s, current %s)\n",
824              state_string(state), state_string(cur_state));
825 }
826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830                           enum pipe pipe, bool state)
831 {
832         int reg;
833         u32 val;
834         bool cur_state;
835
836         reg = FDI_TX_CTL(pipe);
837         val = I915_READ(reg);
838         cur_state = !!(val & FDI_TX_ENABLE);
839         WARN(cur_state != state,
840              "FDI TX state assertion failure (expected %s, current %s)\n",
841              state_string(state), state_string(cur_state));
842 }
843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847                           enum pipe pipe, bool state)
848 {
849         int reg;
850         u32 val;
851         bool cur_state;
852
853         reg = FDI_RX_CTL(pipe);
854         val = I915_READ(reg);
855         cur_state = !!(val & FDI_RX_ENABLE);
856         WARN(cur_state != state,
857              "FDI RX state assertion failure (expected %s, current %s)\n",
858              state_string(state), state_string(cur_state));
859 }
860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864                                       enum pipe pipe)
865 {
866         int reg;
867         u32 val;
868
869         /* ILK FDI PLL is always enabled */
870         if (dev_priv->info->gen == 5)
871                 return;
872
873         reg = FDI_TX_CTL(pipe);
874         val = I915_READ(reg);
875         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876 }
877
878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879                                       enum pipe pipe)
880 {
881         int reg;
882         u32 val;
883
884         reg = FDI_RX_CTL(pipe);
885         val = I915_READ(reg);
886         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887 }
888
889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890                                   enum pipe pipe)
891 {
892         int pp_reg, lvds_reg;
893         u32 val;
894         enum pipe panel_pipe = PIPE_A;
895         bool locked = true;
896
897         if (HAS_PCH_SPLIT(dev_priv->dev)) {
898                 pp_reg = PCH_PP_CONTROL;
899                 lvds_reg = PCH_LVDS;
900         } else {
901                 pp_reg = PP_CONTROL;
902                 lvds_reg = LVDS;
903         }
904
905         val = I915_READ(pp_reg);
906         if (!(val & PANEL_POWER_ON) ||
907             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908                 locked = false;
909
910         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911                 panel_pipe = PIPE_B;
912
913         WARN(panel_pipe == pipe && locked,
914              "panel assertion failure, pipe %c regs locked\n",
915              pipe_name(pipe));
916 }
917
918 static void assert_pipe(struct drm_i915_private *dev_priv,
919                         enum pipe pipe, bool state)
920 {
921         int reg;
922         u32 val;
923         bool cur_state;
924
925         reg = PIPECONF(pipe);
926         val = I915_READ(reg);
927         cur_state = !!(val & PIPECONF_ENABLE);
928         WARN(cur_state != state,
929              "pipe %c assertion failure (expected %s, current %s)\n",
930              pipe_name(pipe), state_string(state), state_string(cur_state));
931 }
932 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
934
935 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
936                                  enum plane plane)
937 {
938         int reg;
939         u32 val;
940
941         reg = DSPCNTR(plane);
942         val = I915_READ(reg);
943         WARN(!(val & DISPLAY_PLANE_ENABLE),
944              "plane %c assertion failure, should be active but is disabled\n",
945              plane_name(plane));
946 }
947
948 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
949                                    enum pipe pipe)
950 {
951         int reg, i;
952         u32 val;
953         int cur_pipe;
954
955         /* Planes are fixed to pipes on ILK+ */
956         if (HAS_PCH_SPLIT(dev_priv->dev))
957                 return;
958
959         /* Need to check both planes against the pipe */
960         for (i = 0; i < 2; i++) {
961                 reg = DSPCNTR(i);
962                 val = I915_READ(reg);
963                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
964                         DISPPLANE_SEL_PIPE_SHIFT;
965                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
966                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
967                      plane_name(i), pipe_name(pipe));
968         }
969 }
970
971 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
972 {
973         u32 val;
974         bool enabled;
975
976         val = I915_READ(PCH_DREF_CONTROL);
977         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
978                             DREF_SUPERSPREAD_SOURCE_MASK));
979         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
980 }
981
982 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
983                                        enum pipe pipe)
984 {
985         int reg;
986         u32 val;
987         bool enabled;
988
989         reg = TRANSCONF(pipe);
990         val = I915_READ(reg);
991         enabled = !!(val & TRANS_ENABLE);
992         WARN(enabled,
993              "transcoder assertion failed, should be off on pipe %c but is still active\n",
994              pipe_name(pipe));
995 }
996
997 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
998                             enum pipe pipe, u32 port_sel, u32 val)
999 {
1000         if ((val & DP_PORT_EN) == 0)
1001                 return false;
1002
1003         if (HAS_PCH_CPT(dev_priv->dev)) {
1004                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007                         return false;
1008         } else {
1009                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010                         return false;
1011         }
1012         return true;
1013 }
1014
1015 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016                               enum pipe pipe, u32 val)
1017 {
1018         if ((val & PORT_ENABLE) == 0)
1019                 return false;
1020
1021         if (HAS_PCH_CPT(dev_priv->dev)) {
1022                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023                         return false;
1024         } else {
1025                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026                         return false;
1027         }
1028         return true;
1029 }
1030
1031 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032                               enum pipe pipe, u32 val)
1033 {
1034         if ((val & LVDS_PORT_EN) == 0)
1035                 return false;
1036
1037         if (HAS_PCH_CPT(dev_priv->dev)) {
1038                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039                         return false;
1040         } else {
1041                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042                         return false;
1043         }
1044         return true;
1045 }
1046
1047 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048                               enum pipe pipe, u32 val)
1049 {
1050         if ((val & ADPA_DAC_ENABLE) == 0)
1051                 return false;
1052         if (HAS_PCH_CPT(dev_priv->dev)) {
1053                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054                         return false;
1055         } else {
1056                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057                         return false;
1058         }
1059         return true;
1060 }
1061
1062 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1063                                    enum pipe pipe, int reg, u32 port_sel)
1064 {
1065         u32 val = I915_READ(reg);
1066         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1067              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1068              reg, pipe_name(pipe));
1069 }
1070
1071 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072                                      enum pipe pipe, int reg)
1073 {
1074         u32 val = I915_READ(reg);
1075         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1076              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1077              reg, pipe_name(pipe));
1078 }
1079
1080 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081                                       enum pipe pipe)
1082 {
1083         int reg;
1084         u32 val;
1085
1086         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1089
1090         reg = PCH_ADPA;
1091         val = I915_READ(reg);
1092         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1093              "PCH VGA enabled on transcoder %c, should be disabled\n",
1094              pipe_name(pipe));
1095
1096         reg = PCH_LVDS;
1097         val = I915_READ(reg);
1098         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1099              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1100              pipe_name(pipe));
1101
1102         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105 }
1106
1107 /**
1108  * intel_enable_pll - enable a PLL
1109  * @dev_priv: i915 private structure
1110  * @pipe: pipe PLL to enable
1111  *
1112  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1113  * make sure the PLL reg is writable first though, since the panel write
1114  * protect mechanism may be enabled.
1115  *
1116  * Note!  This is for pre-ILK only.
1117  */
1118 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119 {
1120         int reg;
1121         u32 val;
1122
1123         /* No really, not for ILK+ */
1124         BUG_ON(dev_priv->info->gen >= 5);
1125
1126         /* PLL is protected by panel, make sure we can write it */
1127         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128                 assert_panel_unlocked(dev_priv, pipe);
1129
1130         reg = DPLL(pipe);
1131         val = I915_READ(reg);
1132         val |= DPLL_VCO_ENABLE;
1133
1134         /* We do this three times for luck */
1135         I915_WRITE(reg, val);
1136         POSTING_READ(reg);
1137         udelay(150); /* wait for warmup */
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(150); /* wait for warmup */
1141         I915_WRITE(reg, val);
1142         POSTING_READ(reg);
1143         udelay(150); /* wait for warmup */
1144 }
1145
1146 /**
1147  * intel_disable_pll - disable a PLL
1148  * @dev_priv: i915 private structure
1149  * @pipe: pipe PLL to disable
1150  *
1151  * Disable the PLL for @pipe, making sure the pipe is off first.
1152  *
1153  * Note!  This is for pre-ILK only.
1154  */
1155 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157         int reg;
1158         u32 val;
1159
1160         /* Don't disable pipe A or pipe A PLLs if needed */
1161         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162                 return;
1163
1164         /* Make sure the pipe isn't still relying on us */
1165         assert_pipe_disabled(dev_priv, pipe);
1166
1167         reg = DPLL(pipe);
1168         val = I915_READ(reg);
1169         val &= ~DPLL_VCO_ENABLE;
1170         I915_WRITE(reg, val);
1171         POSTING_READ(reg);
1172 }
1173
1174 /**
1175  * intel_enable_pch_pll - enable PCH PLL
1176  * @dev_priv: i915 private structure
1177  * @pipe: pipe PLL to enable
1178  *
1179  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180  * drives the transcoder clock.
1181  */
1182 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183                                  enum pipe pipe)
1184 {
1185         int reg;
1186         u32 val;
1187
1188         if (pipe > 1)
1189                 return;
1190
1191         /* PCH only available on ILK+ */
1192         BUG_ON(dev_priv->info->gen < 5);
1193
1194         /* PCH refclock must be enabled first */
1195         assert_pch_refclk_enabled(dev_priv);
1196
1197         reg = PCH_DPLL(pipe);
1198         val = I915_READ(reg);
1199         val |= DPLL_VCO_ENABLE;
1200         I915_WRITE(reg, val);
1201         POSTING_READ(reg);
1202         udelay(200);
1203 }
1204
1205 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206                                   enum pipe pipe)
1207 {
1208         int reg;
1209         u32 val;
1210
1211         if (pipe > 1)
1212                 return;
1213
1214         /* PCH only available on ILK+ */
1215         BUG_ON(dev_priv->info->gen < 5);
1216
1217         /* Make sure transcoder isn't still depending on us */
1218         assert_transcoder_disabled(dev_priv, pipe);
1219
1220         reg = PCH_DPLL(pipe);
1221         val = I915_READ(reg);
1222         val &= ~DPLL_VCO_ENABLE;
1223         I915_WRITE(reg, val);
1224         POSTING_READ(reg);
1225         udelay(200);
1226 }
1227
1228 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229                                     enum pipe pipe)
1230 {
1231         int reg;
1232         u32 val;
1233
1234         /* PCH only available on ILK+ */
1235         BUG_ON(dev_priv->info->gen < 5);
1236
1237         /* Make sure PCH DPLL is enabled */
1238         assert_pch_pll_enabled(dev_priv, pipe);
1239
1240         /* FDI must be feeding us bits for PCH ports */
1241         assert_fdi_tx_enabled(dev_priv, pipe);
1242         assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244         reg = TRANSCONF(pipe);
1245         val = I915_READ(reg);
1246
1247         if (HAS_PCH_IBX(dev_priv->dev)) {
1248                 /*
1249                  * make the BPC in transcoder be consistent with
1250                  * that in pipeconf reg.
1251                  */
1252                 val &= ~PIPE_BPC_MASK;
1253                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254         }
1255         I915_WRITE(reg, val | TRANS_ENABLE);
1256         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258 }
1259
1260 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261                                      enum pipe pipe)
1262 {
1263         int reg;
1264         u32 val;
1265
1266         /* FDI relies on the transcoder */
1267         assert_fdi_tx_disabled(dev_priv, pipe);
1268         assert_fdi_rx_disabled(dev_priv, pipe);
1269
1270         /* Ports must be off as well */
1271         assert_pch_ports_disabled(dev_priv, pipe);
1272
1273         reg = TRANSCONF(pipe);
1274         val = I915_READ(reg);
1275         val &= ~TRANS_ENABLE;
1276         I915_WRITE(reg, val);
1277         /* wait for PCH transcoder off, transcoder state */
1278         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1280 }
1281
1282 /**
1283  * intel_enable_pipe - enable a pipe, asserting requirements
1284  * @dev_priv: i915 private structure
1285  * @pipe: pipe to enable
1286  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1287  *
1288  * Enable @pipe, making sure that various hardware specific requirements
1289  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290  *
1291  * @pipe should be %PIPE_A or %PIPE_B.
1292  *
1293  * Will wait until the pipe is actually running (i.e. first vblank) before
1294  * returning.
1295  */
1296 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297                               bool pch_port)
1298 {
1299         int reg;
1300         u32 val;
1301
1302         /*
1303          * A pipe without a PLL won't actually be able to drive bits from
1304          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1305          * need the check.
1306          */
1307         if (!HAS_PCH_SPLIT(dev_priv->dev))
1308                 assert_pll_enabled(dev_priv, pipe);
1309         else {
1310                 if (pch_port) {
1311                         /* if driving the PCH, we need FDI enabled */
1312                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314                 }
1315                 /* FIXME: assert CPU port conditions for SNB+ */
1316         }
1317
1318         reg = PIPECONF(pipe);
1319         val = I915_READ(reg);
1320         if (val & PIPECONF_ENABLE)
1321                 return;
1322
1323         I915_WRITE(reg, val | PIPECONF_ENABLE);
1324         intel_wait_for_vblank(dev_priv->dev, pipe);
1325 }
1326
1327 /**
1328  * intel_disable_pipe - disable a pipe, asserting requirements
1329  * @dev_priv: i915 private structure
1330  * @pipe: pipe to disable
1331  *
1332  * Disable @pipe, making sure that various hardware specific requirements
1333  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334  *
1335  * @pipe should be %PIPE_A or %PIPE_B.
1336  *
1337  * Will wait until the pipe has shut down before returning.
1338  */
1339 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340                                enum pipe pipe)
1341 {
1342         int reg;
1343         u32 val;
1344
1345         /*
1346          * Make sure planes won't keep trying to pump pixels to us,
1347          * or we might hang the display.
1348          */
1349         assert_planes_disabled(dev_priv, pipe);
1350
1351         /* Don't disable pipe A or pipe A PLLs if needed */
1352         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353                 return;
1354
1355         reg = PIPECONF(pipe);
1356         val = I915_READ(reg);
1357         if ((val & PIPECONF_ENABLE) == 0)
1358                 return;
1359
1360         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1361         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362 }
1363
1364 /*
1365  * Plane regs are double buffered, going from enabled->disabled needs a
1366  * trigger in order to latch.  The display address reg provides this.
1367  */
1368 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369                                       enum plane plane)
1370 {
1371         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373 }
1374
1375 /**
1376  * intel_enable_plane - enable a display plane on a given pipe
1377  * @dev_priv: i915 private structure
1378  * @plane: plane to enable
1379  * @pipe: pipe being fed
1380  *
1381  * Enable @plane on @pipe, making sure that @pipe is running first.
1382  */
1383 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384                                enum plane plane, enum pipe pipe)
1385 {
1386         int reg;
1387         u32 val;
1388
1389         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390         assert_pipe_enabled(dev_priv, pipe);
1391
1392         reg = DSPCNTR(plane);
1393         val = I915_READ(reg);
1394         if (val & DISPLAY_PLANE_ENABLE)
1395                 return;
1396
1397         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1398         intel_flush_display_plane(dev_priv, plane);
1399         intel_wait_for_vblank(dev_priv->dev, pipe);
1400 }
1401
1402 /**
1403  * intel_disable_plane - disable a display plane
1404  * @dev_priv: i915 private structure
1405  * @plane: plane to disable
1406  * @pipe: pipe consuming the data
1407  *
1408  * Disable @plane; should be an independent operation.
1409  */
1410 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411                                 enum plane plane, enum pipe pipe)
1412 {
1413         int reg;
1414         u32 val;
1415
1416         reg = DSPCNTR(plane);
1417         val = I915_READ(reg);
1418         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419                 return;
1420
1421         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1422         intel_flush_display_plane(dev_priv, plane);
1423         intel_wait_for_vblank(dev_priv->dev, pipe);
1424 }
1425
1426 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1427                            enum pipe pipe, int reg, u32 port_sel)
1428 {
1429         u32 val = I915_READ(reg);
1430         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1431                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1432                 I915_WRITE(reg, val & ~DP_PORT_EN);
1433         }
1434 }
1435
1436 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437                              enum pipe pipe, int reg)
1438 {
1439         u32 val = I915_READ(reg);
1440         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1441                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442                               reg, pipe);
1443                 I915_WRITE(reg, val & ~PORT_ENABLE);
1444         }
1445 }
1446
1447 /* Disable any ports connected to this transcoder */
1448 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449                                     enum pipe pipe)
1450 {
1451         u32 reg, val;
1452
1453         val = I915_READ(PCH_PP_CONTROL);
1454         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
1456         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1459
1460         reg = PCH_ADPA;
1461         val = I915_READ(reg);
1462         if (adpa_pipe_enabled(dev_priv, val, pipe))
1463                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465         reg = PCH_LVDS;
1466         val = I915_READ(reg);
1467         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1469                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470                 POSTING_READ(reg);
1471                 udelay(100);
1472         }
1473
1474         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476         disable_pch_hdmi(dev_priv, pipe, HDMID);
1477 }
1478
1479 static void i8xx_disable_fbc(struct drm_device *dev)
1480 {
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         u32 fbc_ctl;
1483
1484         /* Disable compression */
1485         fbc_ctl = I915_READ(FBC_CONTROL);
1486         if ((fbc_ctl & FBC_CTL_EN) == 0)
1487                 return;
1488
1489         fbc_ctl &= ~FBC_CTL_EN;
1490         I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492         /* Wait for compressing bit to clear */
1493         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494                 DRM_DEBUG_KMS("FBC idle timed out\n");
1495                 return;
1496         }
1497
1498         DRM_DEBUG_KMS("disabled FBC\n");
1499 }
1500
1501 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502 {
1503         struct drm_device *dev = crtc->dev;
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         struct drm_framebuffer *fb = crtc->fb;
1506         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1507         struct drm_i915_gem_object *obj = intel_fb->obj;
1508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1509         int cfb_pitch;
1510         int plane, i;
1511         u32 fbc_ctl, fbc_ctl2;
1512
1513         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514         if (fb->pitch < cfb_pitch)
1515                 cfb_pitch = fb->pitch;
1516
1517         /* FBC_CTL wants 64B units */
1518         cfb_pitch = (cfb_pitch / 64) - 1;
1519         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1520
1521         /* Clear old tags */
1522         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523                 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525         /* Set it up... */
1526         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527         fbc_ctl2 |= plane;
1528         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531         /* enable it... */
1532         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1533         if (IS_I945GM(dev))
1534                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1535         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1536         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1537         fbc_ctl |= obj->fence_reg;
1538         I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
1540         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541                       cfb_pitch, crtc->y, intel_crtc->plane);
1542 }
1543
1544 static bool i8xx_fbc_enabled(struct drm_device *dev)
1545 {
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549 }
1550
1551 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1560         unsigned long stall_watermark = 200;
1561         u32 dpfc_ctl;
1562
1563         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1564         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1565         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1566
1567         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572         /* enable it... */
1573         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
1575         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1576 }
1577
1578 static void g4x_disable_fbc(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         u32 dpfc_ctl;
1582
1583         /* Disable compression */
1584         dpfc_ctl = I915_READ(DPFC_CONTROL);
1585         if (dpfc_ctl & DPFC_CTL_EN) {
1586                 dpfc_ctl &= ~DPFC_CTL_EN;
1587                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1588
1589                 DRM_DEBUG_KMS("disabled FBC\n");
1590         }
1591 }
1592
1593 static bool g4x_fbc_enabled(struct drm_device *dev)
1594 {
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598 }
1599
1600 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601 {
1602         struct drm_i915_private *dev_priv = dev->dev_private;
1603         u32 blt_ecoskpd;
1604
1605         /* Make sure blitter notifies FBC of writes */
1606         gen6_gt_force_wake_get(dev_priv);
1607         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609                 GEN6_BLITTER_LOCK_SHIFT;
1610         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614                          GEN6_BLITTER_LOCK_SHIFT);
1615         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1617         gen6_gt_force_wake_put(dev_priv);
1618 }
1619
1620 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621 {
1622         struct drm_device *dev = crtc->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         struct drm_framebuffer *fb = crtc->fb;
1625         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1626         struct drm_i915_gem_object *obj = intel_fb->obj;
1627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1628         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1629         unsigned long stall_watermark = 200;
1630         u32 dpfc_ctl;
1631
1632         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1633         dpfc_ctl &= DPFC_RESERVED;
1634         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1635         /* Set persistent mode for front-buffer rendering, ala X. */
1636         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1637         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1638         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1639
1640         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1644         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1645         /* enable it... */
1646         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1647
1648         if (IS_GEN6(dev)) {
1649                 I915_WRITE(SNB_DPFC_CTL_SA,
1650                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1651                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1652                 sandybridge_blit_fbc_update(dev);
1653         }
1654
1655         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656 }
1657
1658 static void ironlake_disable_fbc(struct drm_device *dev)
1659 {
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         u32 dpfc_ctl;
1662
1663         /* Disable compression */
1664         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1665         if (dpfc_ctl & DPFC_CTL_EN) {
1666                 dpfc_ctl &= ~DPFC_CTL_EN;
1667                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1668
1669                 DRM_DEBUG_KMS("disabled FBC\n");
1670         }
1671 }
1672
1673 static bool ironlake_fbc_enabled(struct drm_device *dev)
1674 {
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678 }
1679
1680 bool intel_fbc_enabled(struct drm_device *dev)
1681 {
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684         if (!dev_priv->display.fbc_enabled)
1685                 return false;
1686
1687         return dev_priv->display.fbc_enabled(dev);
1688 }
1689
1690 static void intel_fbc_work_fn(struct work_struct *__work)
1691 {
1692         struct intel_fbc_work *work =
1693                 container_of(to_delayed_work(__work),
1694                              struct intel_fbc_work, work);
1695         struct drm_device *dev = work->crtc->dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698         mutex_lock(&dev->struct_mutex);
1699         if (work == dev_priv->fbc_work) {
1700                 /* Double check that we haven't switched fb without cancelling
1701                  * the prior work.
1702                  */
1703                 if (work->crtc->fb == work->fb) {
1704                         dev_priv->display.enable_fbc(work->crtc,
1705                                                      work->interval);
1706
1707                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1709                         dev_priv->cfb_y = work->crtc->y;
1710                 }
1711
1712                 dev_priv->fbc_work = NULL;
1713         }
1714         mutex_unlock(&dev->struct_mutex);
1715
1716         kfree(work);
1717 }
1718
1719 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720 {
1721         if (dev_priv->fbc_work == NULL)
1722                 return;
1723
1724         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726         /* Synchronisation is provided by struct_mutex and checking of
1727          * dev_priv->fbc_work, so we can perform the cancellation
1728          * entirely asynchronously.
1729          */
1730         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731                 /* tasklet was killed before being run, clean up */
1732                 kfree(dev_priv->fbc_work);
1733
1734         /* Mark the work as no longer wanted so that if it does
1735          * wake-up (because the work was already running and waiting
1736          * for our mutex), it will discover that is no longer
1737          * necessary to run.
1738          */
1739         dev_priv->fbc_work = NULL;
1740 }
1741
1742 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1743 {
1744         struct intel_fbc_work *work;
1745         struct drm_device *dev = crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         if (!dev_priv->display.enable_fbc)
1749                 return;
1750
1751         intel_cancel_fbc_work(dev_priv);
1752
1753         work = kzalloc(sizeof *work, GFP_KERNEL);
1754         if (work == NULL) {
1755                 dev_priv->display.enable_fbc(crtc, interval);
1756                 return;
1757         }
1758
1759         work->crtc = crtc;
1760         work->fb = crtc->fb;
1761         work->interval = interval;
1762         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764         dev_priv->fbc_work = work;
1765
1766         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768         /* Delay the actual enabling to let pageflipping cease and the
1769          * display to settle before starting the compression. Note that
1770          * this delay also serves a second purpose: it allows for a
1771          * vblank to pass after disabling the FBC before we attempt
1772          * to modify the control registers.
1773          *
1774          * A more complicated solution would involve tracking vblanks
1775          * following the termination of the page-flipping sequence
1776          * and indeed performing the enable as a co-routine and not
1777          * waiting synchronously upon the vblank.
1778          */
1779         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1780 }
1781
1782 void intel_disable_fbc(struct drm_device *dev)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785
1786         intel_cancel_fbc_work(dev_priv);
1787
1788         if (!dev_priv->display.disable_fbc)
1789                 return;
1790
1791         dev_priv->display.disable_fbc(dev);
1792         dev_priv->cfb_plane = -1;
1793 }
1794
1795 /**
1796  * intel_update_fbc - enable/disable FBC as needed
1797  * @dev: the drm_device
1798  *
1799  * Set up the framebuffer compression hardware at mode set time.  We
1800  * enable it if possible:
1801  *   - plane A only (on pre-965)
1802  *   - no pixel mulitply/line duplication
1803  *   - no alpha buffer discard
1804  *   - no dual wide
1805  *   - framebuffer <= 2048 in width, 1536 in height
1806  *
1807  * We can't assume that any compression will take place (worst case),
1808  * so the compressed buffer has to be the same size as the uncompressed
1809  * one.  It also must reside (along with the line length buffer) in
1810  * stolen memory.
1811  *
1812  * We need to enable/disable FBC on a global basis.
1813  */
1814 static void intel_update_fbc(struct drm_device *dev)
1815 {
1816         struct drm_i915_private *dev_priv = dev->dev_private;
1817         struct drm_crtc *crtc = NULL, *tmp_crtc;
1818         struct intel_crtc *intel_crtc;
1819         struct drm_framebuffer *fb;
1820         struct intel_framebuffer *intel_fb;
1821         struct drm_i915_gem_object *obj;
1822         int enable_fbc;
1823
1824         DRM_DEBUG_KMS("\n");
1825
1826         if (!i915_powersave)
1827                 return;
1828
1829         if (!I915_HAS_FBC(dev))
1830                 return;
1831
1832         /*
1833          * If FBC is already on, we just have to verify that we can
1834          * keep it that way...
1835          * Need to disable if:
1836          *   - more than one pipe is active
1837          *   - changing FBC params (stride, fence, mode)
1838          *   - new fb is too large to fit in compressed buffer
1839          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1840          */
1841         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1842                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1843                         if (crtc) {
1844                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846                                 goto out_disable;
1847                         }
1848                         crtc = tmp_crtc;
1849                 }
1850         }
1851
1852         if (!crtc || crtc->fb == NULL) {
1853                 DRM_DEBUG_KMS("no output, disabling\n");
1854                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1855                 goto out_disable;
1856         }
1857
1858         intel_crtc = to_intel_crtc(crtc);
1859         fb = crtc->fb;
1860         intel_fb = to_intel_framebuffer(fb);
1861         obj = intel_fb->obj;
1862
1863         enable_fbc = i915_enable_fbc;
1864         if (enable_fbc < 0) {
1865                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866                 enable_fbc = 1;
1867                 if (INTEL_INFO(dev)->gen <= 5)
1868                         enable_fbc = 0;
1869         }
1870         if (!enable_fbc) {
1871                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1872                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873                 goto out_disable;
1874         }
1875         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1876                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1877                               "compression\n");
1878                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1879                 goto out_disable;
1880         }
1881         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1883                 DRM_DEBUG_KMS("mode incompatible with compression, "
1884                               "disabling\n");
1885                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1886                 goto out_disable;
1887         }
1888         if ((crtc->mode.hdisplay > 2048) ||
1889             (crtc->mode.vdisplay > 1536)) {
1890                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1891                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1892                 goto out_disable;
1893         }
1894         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1895                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1896                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1897                 goto out_disable;
1898         }
1899
1900         /* The use of a CPU fence is mandatory in order to detect writes
1901          * by the CPU to the scanout and trigger updates to the FBC.
1902          */
1903         if (obj->tiling_mode != I915_TILING_X ||
1904             obj->fence_reg == I915_FENCE_REG_NONE) {
1905                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1906                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1907                 goto out_disable;
1908         }
1909
1910         /* If the kernel debugger is active, always disable compression */
1911         if (in_dbg_master())
1912                 goto out_disable;
1913
1914         /* If the scanout has not changed, don't modify the FBC settings.
1915          * Note that we make the fundamental assumption that the fb->obj
1916          * cannot be unpinned (and have its GTT offset and fence revoked)
1917          * without first being decoupled from the scanout and FBC disabled.
1918          */
1919         if (dev_priv->cfb_plane == intel_crtc->plane &&
1920             dev_priv->cfb_fb == fb->base.id &&
1921             dev_priv->cfb_y == crtc->y)
1922                 return;
1923
1924         if (intel_fbc_enabled(dev)) {
1925                 /* We update FBC along two paths, after changing fb/crtc
1926                  * configuration (modeswitching) and after page-flipping
1927                  * finishes. For the latter, we know that not only did
1928                  * we disable the FBC at the start of the page-flip
1929                  * sequence, but also more than one vblank has passed.
1930                  *
1931                  * For the former case of modeswitching, it is possible
1932                  * to switch between two FBC valid configurations
1933                  * instantaneously so we do need to disable the FBC
1934                  * before we can modify its control registers. We also
1935                  * have to wait for the next vblank for that to take
1936                  * effect. However, since we delay enabling FBC we can
1937                  * assume that a vblank has passed since disabling and
1938                  * that we can safely alter the registers in the deferred
1939                  * callback.
1940                  *
1941                  * In the scenario that we go from a valid to invalid
1942                  * and then back to valid FBC configuration we have
1943                  * no strict enforcement that a vblank occurred since
1944                  * disabling the FBC. However, along all current pipe
1945                  * disabling paths we do need to wait for a vblank at
1946                  * some point. And we wait before enabling FBC anyway.
1947                  */
1948                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949                 intel_disable_fbc(dev);
1950         }
1951
1952         intel_enable_fbc(crtc, 500);
1953         return;
1954
1955 out_disable:
1956         /* Multiple disables should be harmless */
1957         if (intel_fbc_enabled(dev)) {
1958                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1959                 intel_disable_fbc(dev);
1960         }
1961 }
1962
1963 int
1964 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1965                            struct drm_i915_gem_object *obj,
1966                            struct intel_ring_buffer *pipelined)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         u32 alignment;
1970         int ret;
1971
1972         switch (obj->tiling_mode) {
1973         case I915_TILING_NONE:
1974                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975                         alignment = 128 * 1024;
1976                 else if (INTEL_INFO(dev)->gen >= 4)
1977                         alignment = 4 * 1024;
1978                 else
1979                         alignment = 64 * 1024;
1980                 break;
1981         case I915_TILING_X:
1982                 /* pin() will align the object as required by fence */
1983                 alignment = 0;
1984                 break;
1985         case I915_TILING_Y:
1986                 /* FIXME: Is this true? */
1987                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988                 return -EINVAL;
1989         default:
1990                 BUG();
1991         }
1992
1993         dev_priv->mm.interruptible = false;
1994         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1995         if (ret)
1996                 goto err_interruptible;
1997
1998         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999          * fence, whereas 965+ only requires a fence if using
2000          * framebuffer compression.  For simplicity, we always install
2001          * a fence as the cost is not that onerous.
2002          */
2003         if (obj->tiling_mode != I915_TILING_NONE) {
2004                 ret = i915_gem_object_get_fence(obj, pipelined);
2005                 if (ret)
2006                         goto err_unpin;
2007         }
2008
2009         dev_priv->mm.interruptible = true;
2010         return 0;
2011
2012 err_unpin:
2013         i915_gem_object_unpin(obj);
2014 err_interruptible:
2015         dev_priv->mm.interruptible = true;
2016         return ret;
2017 }
2018
2019 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020                              int x, int y)
2021 {
2022         struct drm_device *dev = crtc->dev;
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025         struct intel_framebuffer *intel_fb;
2026         struct drm_i915_gem_object *obj;
2027         int plane = intel_crtc->plane;
2028         unsigned long Start, Offset;
2029         u32 dspcntr;
2030         u32 reg;
2031
2032         switch (plane) {
2033         case 0:
2034         case 1:
2035                 break;
2036         default:
2037                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038                 return -EINVAL;
2039         }
2040
2041         intel_fb = to_intel_framebuffer(fb);
2042         obj = intel_fb->obj;
2043
2044         reg = DSPCNTR(plane);
2045         dspcntr = I915_READ(reg);
2046         /* Mask out pixel format bits in case we change it */
2047         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048         switch (fb->bits_per_pixel) {
2049         case 8:
2050                 dspcntr |= DISPPLANE_8BPP;
2051                 break;
2052         case 16:
2053                 if (fb->depth == 15)
2054                         dspcntr |= DISPPLANE_15_16BPP;
2055                 else
2056                         dspcntr |= DISPPLANE_16BPP;
2057                 break;
2058         case 24:
2059         case 32:
2060                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061                 break;
2062         default:
2063                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2064                 return -EINVAL;
2065         }
2066         if (INTEL_INFO(dev)->gen >= 4) {
2067                 if (obj->tiling_mode != I915_TILING_NONE)
2068                         dspcntr |= DISPPLANE_TILED;
2069                 else
2070                         dspcntr &= ~DISPPLANE_TILED;
2071         }
2072
2073         I915_WRITE(reg, dspcntr);
2074
2075         Start = obj->gtt_offset;
2076         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
2078         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079                       Start, Offset, x, y, fb->pitch);
2080         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2081         if (INTEL_INFO(dev)->gen >= 4) {
2082                 I915_WRITE(DSPSURF(plane), Start);
2083                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084                 I915_WRITE(DSPADDR(plane), Offset);
2085         } else
2086                 I915_WRITE(DSPADDR(plane), Start + Offset);
2087         POSTING_READ(reg);
2088
2089         return 0;
2090 }
2091
2092 static int ironlake_update_plane(struct drm_crtc *crtc,
2093                                  struct drm_framebuffer *fb, int x, int y)
2094 {
2095         struct drm_device *dev = crtc->dev;
2096         struct drm_i915_private *dev_priv = dev->dev_private;
2097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098         struct intel_framebuffer *intel_fb;
2099         struct drm_i915_gem_object *obj;
2100         int plane = intel_crtc->plane;
2101         unsigned long Start, Offset;
2102         u32 dspcntr;
2103         u32 reg;
2104
2105         switch (plane) {
2106         case 0:
2107         case 1:
2108         case 2:
2109                 break;
2110         default:
2111                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112                 return -EINVAL;
2113         }
2114
2115         intel_fb = to_intel_framebuffer(fb);
2116         obj = intel_fb->obj;
2117
2118         reg = DSPCNTR(plane);
2119         dspcntr = I915_READ(reg);
2120         /* Mask out pixel format bits in case we change it */
2121         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122         switch (fb->bits_per_pixel) {
2123         case 8:
2124                 dspcntr |= DISPPLANE_8BPP;
2125                 break;
2126         case 16:
2127                 if (fb->depth != 16)
2128                         return -EINVAL;
2129
2130                 dspcntr |= DISPPLANE_16BPP;
2131                 break;
2132         case 24:
2133         case 32:
2134                 if (fb->depth == 24)
2135                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136                 else if (fb->depth == 30)
2137                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138                 else
2139                         return -EINVAL;
2140                 break;
2141         default:
2142                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143                 return -EINVAL;
2144         }
2145
2146         if (obj->tiling_mode != I915_TILING_NONE)
2147                 dspcntr |= DISPPLANE_TILED;
2148         else
2149                 dspcntr &= ~DISPPLANE_TILED;
2150
2151         /* must disable */
2152         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154         I915_WRITE(reg, dspcntr);
2155
2156         Start = obj->gtt_offset;
2157         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160                       Start, Offset, x, y, fb->pitch);
2161         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162         I915_WRITE(DSPSURF(plane), Start);
2163         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164         I915_WRITE(DSPADDR(plane), Offset);
2165         POSTING_READ(reg);
2166
2167         return 0;
2168 }
2169
2170 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 static int
2172 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173                            int x, int y, enum mode_set_atomic state)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         int ret;
2178
2179         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180         if (ret)
2181                 return ret;
2182
2183         intel_update_fbc(dev);
2184         intel_increase_pllclock(crtc);
2185
2186         return 0;
2187 }
2188
2189 static int
2190 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2191                     struct drm_framebuffer *old_fb)
2192 {
2193         struct drm_device *dev = crtc->dev;
2194         struct drm_i915_master_private *master_priv;
2195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2196         int ret;
2197
2198         /* no fb bound */
2199         if (!crtc->fb) {
2200                 DRM_ERROR("No FB bound\n");
2201                 return 0;
2202         }
2203
2204         switch (intel_crtc->plane) {
2205         case 0:
2206         case 1:
2207                 break;
2208         case 2:
2209                 if (IS_IVYBRIDGE(dev))
2210                         break;
2211                 /* fall through otherwise */
2212         default:
2213                 DRM_ERROR("no plane for crtc\n");
2214                 return -EINVAL;
2215         }
2216
2217         mutex_lock(&dev->struct_mutex);
2218         ret = intel_pin_and_fence_fb_obj(dev,
2219                                          to_intel_framebuffer(crtc->fb)->obj,
2220                                          NULL);
2221         if (ret != 0) {
2222                 mutex_unlock(&dev->struct_mutex);
2223                 DRM_ERROR("pin & fence failed\n");
2224                 return ret;
2225         }
2226
2227         if (old_fb) {
2228                 struct drm_i915_private *dev_priv = dev->dev_private;
2229                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2230
2231                 wait_event(dev_priv->pending_flip_queue,
2232                            atomic_read(&dev_priv->mm.wedged) ||
2233                            atomic_read(&obj->pending_flip) == 0);
2234
2235                 /* Big Hammer, we also need to ensure that any pending
2236                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237                  * current scanout is retired before unpinning the old
2238                  * framebuffer.
2239                  *
2240                  * This should only fail upon a hung GPU, in which case we
2241                  * can safely continue.
2242                  */
2243                 ret = i915_gem_object_finish_gpu(obj);
2244                 (void) ret;
2245         }
2246
2247         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2248                                          LEAVE_ATOMIC_MODE_SET);
2249         if (ret) {
2250                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2251                 mutex_unlock(&dev->struct_mutex);
2252                 DRM_ERROR("failed to update base address\n");
2253                 return ret;
2254         }
2255
2256         if (old_fb) {
2257                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2258                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2259         }
2260
2261         mutex_unlock(&dev->struct_mutex);
2262
2263         if (!dev->primary->master)
2264                 return 0;
2265
2266         master_priv = dev->primary->master->driver_priv;
2267         if (!master_priv->sarea_priv)
2268                 return 0;
2269
2270         if (intel_crtc->pipe) {
2271                 master_priv->sarea_priv->pipeB_x = x;
2272                 master_priv->sarea_priv->pipeB_y = y;
2273         } else {
2274                 master_priv->sarea_priv->pipeA_x = x;
2275                 master_priv->sarea_priv->pipeA_y = y;
2276         }
2277
2278         return 0;
2279 }
2280
2281 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2282 {
2283         struct drm_device *dev = crtc->dev;
2284         struct drm_i915_private *dev_priv = dev->dev_private;
2285         u32 dpa_ctl;
2286
2287         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2288         dpa_ctl = I915_READ(DP_A);
2289         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2290
2291         if (clock < 200000) {
2292                 u32 temp;
2293                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2294                 /* workaround for 160Mhz:
2295                    1) program 0x4600c bits 15:0 = 0x8124
2296                    2) program 0x46010 bit 0 = 1
2297                    3) program 0x46034 bit 24 = 1
2298                    4) program 0x64000 bit 14 = 1
2299                    */
2300                 temp = I915_READ(0x4600c);
2301                 temp &= 0xffff0000;
2302                 I915_WRITE(0x4600c, temp | 0x8124);
2303
2304                 temp = I915_READ(0x46010);
2305                 I915_WRITE(0x46010, temp | 1);
2306
2307                 temp = I915_READ(0x46034);
2308                 I915_WRITE(0x46034, temp | (1 << 24));
2309         } else {
2310                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2311         }
2312         I915_WRITE(DP_A, dpa_ctl);
2313
2314         POSTING_READ(DP_A);
2315         udelay(500);
2316 }
2317
2318 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2319 {
2320         struct drm_device *dev = crtc->dev;
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         u32 reg, temp;
2325
2326         /* enable normal train */
2327         reg = FDI_TX_CTL(pipe);
2328         temp = I915_READ(reg);
2329         if (IS_IVYBRIDGE(dev)) {
2330                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2331                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2332         } else {
2333                 temp &= ~FDI_LINK_TRAIN_NONE;
2334                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2335         }
2336         I915_WRITE(reg, temp);
2337
2338         reg = FDI_RX_CTL(pipe);
2339         temp = I915_READ(reg);
2340         if (HAS_PCH_CPT(dev)) {
2341                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343         } else {
2344                 temp &= ~FDI_LINK_TRAIN_NONE;
2345                 temp |= FDI_LINK_TRAIN_NONE;
2346         }
2347         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349         /* wait one idle pattern time */
2350         POSTING_READ(reg);
2351         udelay(1000);
2352
2353         /* IVB wants error correction enabled */
2354         if (IS_IVYBRIDGE(dev))
2355                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2356                            FDI_FE_ERRC_ENABLE);
2357 }
2358
2359 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2360 {
2361         struct drm_i915_private *dev_priv = dev->dev_private;
2362         u32 flags = I915_READ(SOUTH_CHICKEN1);
2363
2364         flags |= FDI_PHASE_SYNC_OVR(pipe);
2365         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2366         flags |= FDI_PHASE_SYNC_EN(pipe);
2367         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2368         POSTING_READ(SOUTH_CHICKEN1);
2369 }
2370
2371 /* The FDI link training functions for ILK/Ibexpeak. */
2372 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2373 {
2374         struct drm_device *dev = crtc->dev;
2375         struct drm_i915_private *dev_priv = dev->dev_private;
2376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377         int pipe = intel_crtc->pipe;
2378         int plane = intel_crtc->plane;
2379         u32 reg, temp, tries;
2380
2381         /* FDI needs bits from pipe & plane first */
2382         assert_pipe_enabled(dev_priv, pipe);
2383         assert_plane_enabled(dev_priv, plane);
2384
2385         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2386            for train result */
2387         reg = FDI_RX_IMR(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_RX_SYMBOL_LOCK;
2390         temp &= ~FDI_RX_BIT_LOCK;
2391         I915_WRITE(reg, temp);
2392         I915_READ(reg);
2393         udelay(150);
2394
2395         /* enable CPU FDI TX and PCH FDI RX */
2396         reg = FDI_TX_CTL(pipe);
2397         temp = I915_READ(reg);
2398         temp &= ~(7 << 19);
2399         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2400         temp &= ~FDI_LINK_TRAIN_NONE;
2401         temp |= FDI_LINK_TRAIN_PATTERN_1;
2402         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2403
2404         reg = FDI_RX_CTL(pipe);
2405         temp = I915_READ(reg);
2406         temp &= ~FDI_LINK_TRAIN_NONE;
2407         temp |= FDI_LINK_TRAIN_PATTERN_1;
2408         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2409
2410         POSTING_READ(reg);
2411         udelay(150);
2412
2413         /* Ironlake workaround, enable clock pointer after FDI enable*/
2414         if (HAS_PCH_IBX(dev)) {
2415                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2416                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2417                            FDI_RX_PHASE_SYNC_POINTER_EN);
2418         }
2419
2420         reg = FDI_RX_IIR(pipe);
2421         for (tries = 0; tries < 5; tries++) {
2422                 temp = I915_READ(reg);
2423                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425                 if ((temp & FDI_RX_BIT_LOCK)) {
2426                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2427                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2428                         break;
2429                 }
2430         }
2431         if (tries == 5)
2432                 DRM_ERROR("FDI train 1 fail!\n");
2433
2434         /* Train 2 */
2435         reg = FDI_TX_CTL(pipe);
2436         temp = I915_READ(reg);
2437         temp &= ~FDI_LINK_TRAIN_NONE;
2438         temp |= FDI_LINK_TRAIN_PATTERN_2;
2439         I915_WRITE(reg, temp);
2440
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         temp &= ~FDI_LINK_TRAIN_NONE;
2444         temp |= FDI_LINK_TRAIN_PATTERN_2;
2445         I915_WRITE(reg, temp);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if (temp & FDI_RX_SYMBOL_LOCK) {
2456                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2457                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 2 fail!\n");
2463
2464         DRM_DEBUG_KMS("FDI train done\n");
2465
2466 }
2467
2468 static const int snb_b_fdi_train_param[] = {
2469         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473 };
2474
2475 /* The FDI link training functions for SNB/Cougarpoint. */
2476 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477 {
2478         struct drm_device *dev = crtc->dev;
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481         int pipe = intel_crtc->pipe;
2482         u32 reg, temp, i;
2483
2484         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485            for train result */
2486         reg = FDI_RX_IMR(pipe);
2487         temp = I915_READ(reg);
2488         temp &= ~FDI_RX_SYMBOL_LOCK;
2489         temp &= ~FDI_RX_BIT_LOCK;
2490         I915_WRITE(reg, temp);
2491
2492         POSTING_READ(reg);
2493         udelay(150);
2494
2495         /* enable CPU FDI TX and PCH FDI RX */
2496         reg = FDI_TX_CTL(pipe);
2497         temp = I915_READ(reg);
2498         temp &= ~(7 << 19);
2499         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_1;
2502         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503         /* SNB-B */
2504         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2506
2507         reg = FDI_RX_CTL(pipe);
2508         temp = I915_READ(reg);
2509         if (HAS_PCH_CPT(dev)) {
2510                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512         } else {
2513                 temp &= ~FDI_LINK_TRAIN_NONE;
2514                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515         }
2516         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518         POSTING_READ(reg);
2519         udelay(150);
2520
2521         if (HAS_PCH_CPT(dev))
2522                 cpt_phase_pointer_enable(dev, pipe);
2523
2524         for (i = 0; i < 4; i++) {
2525                 reg = FDI_TX_CTL(pipe);
2526                 temp = I915_READ(reg);
2527                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528                 temp |= snb_b_fdi_train_param[i];
2529                 I915_WRITE(reg, temp);
2530
2531                 POSTING_READ(reg);
2532                 udelay(500);
2533
2534                 reg = FDI_RX_IIR(pipe);
2535                 temp = I915_READ(reg);
2536                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538                 if (temp & FDI_RX_BIT_LOCK) {
2539                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2540                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2541                         break;
2542                 }
2543         }
2544         if (i == 4)
2545                 DRM_ERROR("FDI train 1 fail!\n");
2546
2547         /* Train 2 */
2548         reg = FDI_TX_CTL(pipe);
2549         temp = I915_READ(reg);
2550         temp &= ~FDI_LINK_TRAIN_NONE;
2551         temp |= FDI_LINK_TRAIN_PATTERN_2;
2552         if (IS_GEN6(dev)) {
2553                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554                 /* SNB-B */
2555                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556         }
2557         I915_WRITE(reg, temp);
2558
2559         reg = FDI_RX_CTL(pipe);
2560         temp = I915_READ(reg);
2561         if (HAS_PCH_CPT(dev)) {
2562                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564         } else {
2565                 temp &= ~FDI_LINK_TRAIN_NONE;
2566                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567         }
2568         I915_WRITE(reg, temp);
2569
2570         POSTING_READ(reg);
2571         udelay(150);
2572
2573         for (i = 0; i < 4; i++) {
2574                 reg = FDI_TX_CTL(pipe);
2575                 temp = I915_READ(reg);
2576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2577                 temp |= snb_b_fdi_train_param[i];
2578                 I915_WRITE(reg, temp);
2579
2580                 POSTING_READ(reg);
2581                 udelay(500);
2582
2583                 reg = FDI_RX_IIR(pipe);
2584                 temp = I915_READ(reg);
2585                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587                 if (temp & FDI_RX_SYMBOL_LOCK) {
2588                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2589                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2590                         break;
2591                 }
2592         }
2593         if (i == 4)
2594                 DRM_ERROR("FDI train 2 fail!\n");
2595
2596         DRM_DEBUG_KMS("FDI train done.\n");
2597 }
2598
2599 /* Manual link training for Ivy Bridge A0 parts */
2600 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601 {
2602         struct drm_device *dev = crtc->dev;
2603         struct drm_i915_private *dev_priv = dev->dev_private;
2604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605         int pipe = intel_crtc->pipe;
2606         u32 reg, temp, i;
2607
2608         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609            for train result */
2610         reg = FDI_RX_IMR(pipe);
2611         temp = I915_READ(reg);
2612         temp &= ~FDI_RX_SYMBOL_LOCK;
2613         temp &= ~FDI_RX_BIT_LOCK;
2614         I915_WRITE(reg, temp);
2615
2616         POSTING_READ(reg);
2617         udelay(150);
2618
2619         /* enable CPU FDI TX and PCH FDI RX */
2620         reg = FDI_TX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~(7 << 19);
2623         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2624         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2626         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2628         temp |= FDI_COMPOSITE_SYNC;
2629         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630
2631         reg = FDI_RX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_LINK_TRAIN_AUTO;
2634         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636         temp |= FDI_COMPOSITE_SYNC;
2637         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639         POSTING_READ(reg);
2640         udelay(150);
2641
2642         if (HAS_PCH_CPT(dev))
2643                 cpt_phase_pointer_enable(dev, pipe);
2644
2645         for (i = 0; i < 4; i++) {
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 temp |= snb_b_fdi_train_param[i];
2650                 I915_WRITE(reg, temp);
2651
2652                 POSTING_READ(reg);
2653                 udelay(500);
2654
2655                 reg = FDI_RX_IIR(pipe);
2656                 temp = I915_READ(reg);
2657                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659                 if (temp & FDI_RX_BIT_LOCK ||
2660                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2661                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2662                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2663                         break;
2664                 }
2665         }
2666         if (i == 4)
2667                 DRM_ERROR("FDI train 1 fail!\n");
2668
2669         /* Train 2 */
2670         reg = FDI_TX_CTL(pipe);
2671         temp = I915_READ(reg);
2672         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2673         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2674         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676         I915_WRITE(reg, temp);
2677
2678         reg = FDI_RX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682         I915_WRITE(reg, temp);
2683
2684         POSTING_READ(reg);
2685         udelay(150);
2686
2687         for (i = 0; i < 4; i++) {
2688                 reg = FDI_TX_CTL(pipe);
2689                 temp = I915_READ(reg);
2690                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691                 temp |= snb_b_fdi_train_param[i];
2692                 I915_WRITE(reg, temp);
2693
2694                 POSTING_READ(reg);
2695                 udelay(500);
2696
2697                 reg = FDI_RX_IIR(pipe);
2698                 temp = I915_READ(reg);
2699                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701                 if (temp & FDI_RX_SYMBOL_LOCK) {
2702                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2704                         break;
2705                 }
2706         }
2707         if (i == 4)
2708                 DRM_ERROR("FDI train 2 fail!\n");
2709
2710         DRM_DEBUG_KMS("FDI train done.\n");
2711 }
2712
2713 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2714 {
2715         struct drm_device *dev = crtc->dev;
2716         struct drm_i915_private *dev_priv = dev->dev_private;
2717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718         int pipe = intel_crtc->pipe;
2719         u32 reg, temp;
2720
2721         /* Write the TU size bits so error detection works */
2722         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2723                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2724
2725         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2726         reg = FDI_RX_CTL(pipe);
2727         temp = I915_READ(reg);
2728         temp &= ~((0x7 << 19) | (0x7 << 16));
2729         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2730         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2731         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733         POSTING_READ(reg);
2734         udelay(200);
2735
2736         /* Switch from Rawclk to PCDclk */
2737         temp = I915_READ(reg);
2738         I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740         POSTING_READ(reg);
2741         udelay(200);
2742
2743         /* Enable CPU FDI TX PLL, always on for Ironlake */
2744         reg = FDI_TX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749                 POSTING_READ(reg);
2750                 udelay(100);
2751         }
2752 }
2753
2754 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2755 {
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757         u32 flags = I915_READ(SOUTH_CHICKEN1);
2758
2759         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2760         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2761         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2762         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2763         POSTING_READ(SOUTH_CHICKEN1);
2764 }
2765 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2766 {
2767         struct drm_device *dev = crtc->dev;
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770         int pipe = intel_crtc->pipe;
2771         u32 reg, temp;
2772
2773         /* disable CPU FDI tx and PCH FDI rx */
2774         reg = FDI_TX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2777         POSTING_READ(reg);
2778
2779         reg = FDI_RX_CTL(pipe);
2780         temp = I915_READ(reg);
2781         temp &= ~(0x7 << 16);
2782         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2784
2785         POSTING_READ(reg);
2786         udelay(100);
2787
2788         /* Ironlake workaround, disable clock pointer after downing FDI */
2789         if (HAS_PCH_IBX(dev)) {
2790                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2791                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2792                            I915_READ(FDI_RX_CHICKEN(pipe) &
2793                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2794         } else if (HAS_PCH_CPT(dev)) {
2795                 cpt_phase_pointer_disable(dev, pipe);
2796         }
2797
2798         /* still set train pattern 1 */
2799         reg = FDI_TX_CTL(pipe);
2800         temp = I915_READ(reg);
2801         temp &= ~FDI_LINK_TRAIN_NONE;
2802         temp |= FDI_LINK_TRAIN_PATTERN_1;
2803         I915_WRITE(reg, temp);
2804
2805         reg = FDI_RX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         if (HAS_PCH_CPT(dev)) {
2808                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2809                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2810         } else {
2811                 temp &= ~FDI_LINK_TRAIN_NONE;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813         }
2814         /* BPC in FDI rx is consistent with that in PIPECONF */
2815         temp &= ~(0x07 << 16);
2816         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2817         I915_WRITE(reg, temp);
2818
2819         POSTING_READ(reg);
2820         udelay(100);
2821 }
2822
2823 /*
2824  * When we disable a pipe, we need to clear any pending scanline wait events
2825  * to avoid hanging the ring, which we assume we are waiting on.
2826  */
2827 static void intel_clear_scanline_wait(struct drm_device *dev)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         struct intel_ring_buffer *ring;
2831         u32 tmp;
2832
2833         if (IS_GEN2(dev))
2834                 /* Can't break the hang on i8xx */
2835                 return;
2836
2837         ring = LP_RING(dev_priv);
2838         tmp = I915_READ_CTL(ring);
2839         if (tmp & RING_WAIT)
2840                 I915_WRITE_CTL(ring, tmp);
2841 }
2842
2843 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844 {
2845         struct drm_i915_gem_object *obj;
2846         struct drm_i915_private *dev_priv;
2847
2848         if (crtc->fb == NULL)
2849                 return;
2850
2851         obj = to_intel_framebuffer(crtc->fb)->obj;
2852         dev_priv = crtc->dev->dev_private;
2853         wait_event(dev_priv->pending_flip_queue,
2854                    atomic_read(&obj->pending_flip) == 0);
2855 }
2856
2857 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2858 {
2859         struct drm_device *dev = crtc->dev;
2860         struct drm_mode_config *mode_config = &dev->mode_config;
2861         struct intel_encoder *encoder;
2862
2863         /*
2864          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2865          * must be driven by its own crtc; no sharing is possible.
2866          */
2867         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2868                 if (encoder->base.crtc != crtc)
2869                         continue;
2870
2871                 switch (encoder->type) {
2872                 case INTEL_OUTPUT_EDP:
2873                         if (!intel_encoder_is_pch_edp(&encoder->base))
2874                                 return false;
2875                         continue;
2876                 }
2877         }
2878
2879         return true;
2880 }
2881
2882 /*
2883  * Enable PCH resources required for PCH ports:
2884  *   - PCH PLLs
2885  *   - FDI training & RX/TX
2886  *   - update transcoder timings
2887  *   - DP transcoding bits
2888  *   - transcoder
2889  */
2890 static void ironlake_pch_enable(struct drm_crtc *crtc)
2891 {
2892         struct drm_device *dev = crtc->dev;
2893         struct drm_i915_private *dev_priv = dev->dev_private;
2894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895         int pipe = intel_crtc->pipe;
2896         u32 reg, temp, transc_sel;
2897
2898         /* For PCH output, training FDI link */
2899         dev_priv->display.fdi_link_train(crtc);
2900
2901         intel_enable_pch_pll(dev_priv, pipe);
2902
2903         if (HAS_PCH_CPT(dev)) {
2904                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2905                         TRANSC_DPLLB_SEL;
2906
2907                 /* Be sure PCH DPLL SEL is set */
2908                 temp = I915_READ(PCH_DPLL_SEL);
2909                 if (pipe == 0) {
2910                         temp &= ~(TRANSA_DPLLB_SEL);
2911                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2912                 } else if (pipe == 1) {
2913                         temp &= ~(TRANSB_DPLLB_SEL);
2914                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2915                 } else if (pipe == 2) {
2916                         temp &= ~(TRANSC_DPLLB_SEL);
2917                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2918                 }
2919                 I915_WRITE(PCH_DPLL_SEL, temp);
2920         }
2921
2922         /* set transcoder timing, panel must allow it */
2923         assert_panel_unlocked(dev_priv, pipe);
2924         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2925         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2926         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2927
2928         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2929         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2930         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2931
2932         intel_fdi_normal_train(crtc);
2933
2934         /* For PCH DP, enable TRANS_DP_CTL */
2935         if (HAS_PCH_CPT(dev) &&
2936             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2937                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2938                 reg = TRANS_DP_CTL(pipe);
2939                 temp = I915_READ(reg);
2940                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2941                           TRANS_DP_SYNC_MASK |
2942                           TRANS_DP_BPC_MASK);
2943                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2944                          TRANS_DP_ENH_FRAMING);
2945                 temp |= bpc << 9; /* same format but at 11:9 */
2946
2947                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2948                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2949                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2950                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2951
2952                 switch (intel_trans_dp_port_sel(crtc)) {
2953                 case PCH_DP_B:
2954                         temp |= TRANS_DP_PORT_SEL_B;
2955                         break;
2956                 case PCH_DP_C:
2957                         temp |= TRANS_DP_PORT_SEL_C;
2958                         break;
2959                 case PCH_DP_D:
2960                         temp |= TRANS_DP_PORT_SEL_D;
2961                         break;
2962                 default:
2963                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2964                         temp |= TRANS_DP_PORT_SEL_B;
2965                         break;
2966                 }
2967
2968                 I915_WRITE(reg, temp);
2969         }
2970
2971         intel_enable_transcoder(dev_priv, pipe);
2972 }
2973
2974 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2975 {
2976         struct drm_i915_private *dev_priv = dev->dev_private;
2977         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2978         u32 temp;
2979
2980         temp = I915_READ(dslreg);
2981         udelay(500);
2982         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2983                 /* Without this, mode sets may fail silently on FDI */
2984                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2985                 udelay(250);
2986                 I915_WRITE(tc2reg, 0);
2987                 if (wait_for(I915_READ(dslreg) != temp, 5))
2988                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2989         }
2990 }
2991
2992 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2993 {
2994         struct drm_device *dev = crtc->dev;
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2997         int pipe = intel_crtc->pipe;
2998         int plane = intel_crtc->plane;
2999         u32 temp;
3000         bool is_pch_port;
3001
3002         if (intel_crtc->active)
3003                 return;
3004
3005         intel_crtc->active = true;
3006         intel_update_watermarks(dev);
3007
3008         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3009                 temp = I915_READ(PCH_LVDS);
3010                 if ((temp & LVDS_PORT_EN) == 0)
3011                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3012         }
3013
3014         is_pch_port = intel_crtc_driving_pch(crtc);
3015
3016         if (is_pch_port)
3017                 ironlake_fdi_pll_enable(crtc);
3018         else
3019                 ironlake_fdi_disable(crtc);
3020
3021         /* Enable panel fitting for LVDS */
3022         if (dev_priv->pch_pf_size &&
3023             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3024                 /* Force use of hard-coded filter coefficients
3025                  * as some pre-programmed values are broken,
3026                  * e.g. x201.
3027                  */
3028                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3029                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3030                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3031         }
3032
3033         /*
3034          * On ILK+ LUT must be loaded before the pipe is running but with
3035          * clocks enabled
3036          */
3037         intel_crtc_load_lut(crtc);
3038
3039         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3040         intel_enable_plane(dev_priv, plane, pipe);
3041
3042         if (is_pch_port)
3043                 ironlake_pch_enable(crtc);
3044
3045         mutex_lock(&dev->struct_mutex);
3046         intel_update_fbc(dev);
3047         mutex_unlock(&dev->struct_mutex);
3048
3049         intel_crtc_update_cursor(crtc, true);
3050 }
3051
3052 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3053 {
3054         struct drm_device *dev = crtc->dev;
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057         int pipe = intel_crtc->pipe;
3058         int plane = intel_crtc->plane;
3059         u32 reg, temp;
3060
3061         if (!intel_crtc->active)
3062                 return;
3063
3064         intel_crtc_wait_for_pending_flips(crtc);
3065         drm_vblank_off(dev, pipe);
3066         intel_crtc_update_cursor(crtc, false);
3067
3068         intel_disable_plane(dev_priv, plane, pipe);
3069
3070         if (dev_priv->cfb_plane == plane)
3071                 intel_disable_fbc(dev);
30