drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include "drmP.h"
  29 #include "intel_drv.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "intel_dp.h"
  33
  34 #include "drm_crtc_helper.h"
  35
  36 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  37
  38 typedef struct {
  39     /* given values */
  40     int n;
  41     int m1, m2;
  42     int p1, p2;
  43     /* derived values */
  44     int dot;
  45     int vco;
  46     int m;
  47     int p;
  48 } intel_clock_t;
  49
  50 typedef struct {
  51     int min, max;
  52 } intel_range_t;
  53
  54 typedef struct {
  55     int dot_limit;
  56     int p2_slow, p2_fast;
  57 } intel_p2_t;
  58
  59 #define INTEL_P2_NUM                  2
  60 typedef struct intel_limit intel_limit_t;
  61 struct intel_limit {
  62     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  63     intel_p2_t      p2;
  64     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  65                       int, int, intel_clock_t *);
  66 };
  67
  68 #define I8XX_DOT_MIN              25000
  69 #define I8XX_DOT_MAX             350000
  70 #define I8XX_VCO_MIN             930000
  71 #define I8XX_VCO_MAX            1400000
  72 #define I8XX_N_MIN                    3
  73 #define I8XX_N_MAX                   16
  74 #define I8XX_M_MIN                   96
  75 #define I8XX_M_MAX                  140
  76 #define I8XX_M1_MIN                  18
  77 #define I8XX_M1_MAX                  26
  78 #define I8XX_M2_MIN                   6
  79 #define I8XX_M2_MAX                  16
  80 #define I8XX_P_MIN                    4
  81 #define I8XX_P_MAX                  128
  82 #define I8XX_P1_MIN                   2
  83 #define I8XX_P1_MAX                  33
  84 #define I8XX_P1_LVDS_MIN              1
  85 #define I8XX_P1_LVDS_MAX              6
  86 #define I8XX_P2_SLOW                  4
  87 #define I8XX_P2_FAST                  2
  88 #define I8XX_P2_LVDS_SLOW             14
  89 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  90 #define I8XX_P2_SLOW_LIMIT       165000
  91
  92 #define I9XX_DOT_MIN              20000
  93 #define I9XX_DOT_MAX             400000
  94 #define I9XX_VCO_MIN            1400000
  95 #define I9XX_VCO_MAX            2800000
  96 #define IGD_VCO_MIN             1700000
  97 #define IGD_VCO_MAX             3500000
  98 #define I9XX_N_MIN                    1
  99 #define I9XX_N_MAX                    6
 100 /* IGD's Ncounter is a ring counter */
 101 #define IGD_N_MIN                     3
 102 #define IGD_N_MAX                     6
 103 #define I9XX_M_MIN                   70
 104 #define I9XX_M_MAX                  120
 105 #define IGD_M_MIN                     2
 106 #define IGD_M_MAX                   256
 107 #define I9XX_M1_MIN                  10
 108 #define I9XX_M1_MAX                  22
 109 #define I9XX_M2_MIN                   5
 110 #define I9XX_M2_MAX                   9
 111 /* IGD M1 is reserved, and must be 0 */
 112 #define IGD_M1_MIN                    0
 113 #define IGD_M1_MAX                    0
 114 #define IGD_M2_MIN                    0
 115 #define IGD_M2_MAX                    254
 116 #define I9XX_P_SDVO_DAC_MIN           5
 117 #define I9XX_P_SDVO_DAC_MAX          80
 118 #define I9XX_P_LVDS_MIN               7
 119 #define I9XX_P_LVDS_MAX              98
 120 #define IGD_P_LVDS_MIN                7
 121 #define IGD_P_LVDS_MAX               112
 122 #define I9XX_P1_MIN                   1
 123 #define I9XX_P1_MAX                   8
 124 #define I9XX_P2_SDVO_DAC_SLOW                10
 125 #define I9XX_P2_SDVO_DAC_FAST                 5
 126 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 127 #define I9XX_P2_LVDS_SLOW                    14
 128 #define I9XX_P2_LVDS_FAST                     7
 129 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 130
 131 /*The parameter is for SDVO on G4x platform*/
 132 #define G4X_DOT_SDVO_MIN           25000
 133 #define G4X_DOT_SDVO_MAX           270000
 134 #define G4X_VCO_MIN                1750000
 135 #define G4X_VCO_MAX                3500000
 136 #define G4X_N_SDVO_MIN             1
 137 #define G4X_N_SDVO_MAX             4
 138 #define G4X_M_SDVO_MIN             104
 139 #define G4X_M_SDVO_MAX             138
 140 #define G4X_M1_SDVO_MIN            17
 141 #define G4X_M1_SDVO_MAX            23
 142 #define G4X_M2_SDVO_MIN            5
 143 #define G4X_M2_SDVO_MAX            11
 144 #define G4X_P_SDVO_MIN             10
 145 #define G4X_P_SDVO_MAX             30
 146 #define G4X_P1_SDVO_MIN            1
 147 #define G4X_P1_SDVO_MAX            3
 148 #define G4X_P2_SDVO_SLOW           10
 149 #define G4X_P2_SDVO_FAST           10
 150 #define G4X_P2_SDVO_LIMIT          270000
 151
 152 /*The parameter is for HDMI_DAC on G4x platform*/
 153 #define G4X_DOT_HDMI_DAC_MIN           22000
 154 #define G4X_DOT_HDMI_DAC_MAX           400000
 155 #define G4X_N_HDMI_DAC_MIN             1
 156 #define G4X_N_HDMI_DAC_MAX             4
 157 #define G4X_M_HDMI_DAC_MIN             104
 158 #define G4X_M_HDMI_DAC_MAX             138
 159 #define G4X_M1_HDMI_DAC_MIN            16
 160 #define G4X_M1_HDMI_DAC_MAX            23
 161 #define G4X_M2_HDMI_DAC_MIN            5
 162 #define G4X_M2_HDMI_DAC_MAX            11
 163 #define G4X_P_HDMI_DAC_MIN             5
 164 #define G4X_P_HDMI_DAC_MAX             80
 165 #define G4X_P1_HDMI_DAC_MIN            1
 166 #define G4X_P1_HDMI_DAC_MAX            8
 167 #define G4X_P2_HDMI_DAC_SLOW           10
 168 #define G4X_P2_HDMI_DAC_FAST           5
 169 #define G4X_P2_HDMI_DAC_LIMIT          165000
 170
 171 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 172 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 173 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 174 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 175 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 176 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 177 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 178 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 179 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 180 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 181 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 182 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 183 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 184 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 185 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 186 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 187 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 188 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 189
 190 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 191 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 192 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 193 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 194 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 195 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 196 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 197 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 198 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 199 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 200 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 201 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 202 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 203 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 204 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 205 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 206 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 207 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 208
 209 /*The parameter is for DISPLAY PORT on G4x platform*/
 210 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 211 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 212 #define G4X_N_DISPLAY_PORT_MIN             1
 213 #define G4X_N_DISPLAY_PORT_MAX             2
 214 #define G4X_M_DISPLAY_PORT_MIN             97
 215 #define G4X_M_DISPLAY_PORT_MAX             108
 216 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 217 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 218 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 219 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 220 #define G4X_P_DISPLAY_PORT_MIN             10
 221 #define G4X_P_DISPLAY_PORT_MAX             20
 222 #define G4X_P1_DISPLAY_PORT_MIN            1
 223 #define G4X_P1_DISPLAY_PORT_MAX            2
 224 #define G4X_P2_DISPLAY_PORT_SLOW           10
 225 #define G4X_P2_DISPLAY_PORT_FAST           10
 226 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 227
 228 /* IGDNG */
 229 /* as we calculate clock using (register_value + 2) for
 230    N/M1/M2, so here the range value for them is (actual_value-2).
 231  */
 232 #define IGDNG_DOT_MIN         25000
 233 #define IGDNG_DOT_MAX         350000
 234 #define IGDNG_VCO_MIN         1760000
 235 #define IGDNG_VCO_MAX         3510000
 236 #define IGDNG_N_MIN           1
 237 #define IGDNG_N_MAX           5
 238 #define IGDNG_M_MIN           79
 239 #define IGDNG_M_MAX           118
 240 #define IGDNG_M1_MIN          12
 241 #define IGDNG_M1_MAX          23
 242 #define IGDNG_M2_MIN          5
 243 #define IGDNG_M2_MAX          9
 244 #define IGDNG_P_SDVO_DAC_MIN  5
 245 #define IGDNG_P_SDVO_DAC_MAX  80
 246 #define IGDNG_P_LVDS_MIN      28
 247 #define IGDNG_P_LVDS_MAX      112
 248 #define IGDNG_P1_MIN          1
 249 #define IGDNG_P1_MAX          8
 250 #define IGDNG_P2_SDVO_DAC_SLOW 10
 251 #define IGDNG_P2_SDVO_DAC_FAST 5
 252 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 253 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 254 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 255
 256 static bool
 257 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 258                     int target, int refclk, intel_clock_t *best_clock);
 259 static bool
 260 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 261                         int target, int refclk, intel_clock_t *best_clock);
 262 static bool
 263 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 264                         int target, int refclk, intel_clock_t *best_clock);
 265
 266 static bool
 267 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 268                       int target, int refclk, intel_clock_t *best_clock);
 269
 270 static const intel_limit_t intel_limits_i8xx_dvo = {
 271         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 272         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 273         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 274         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 275         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 276         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 277         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 278         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 279         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 280                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 281         .find_pll = intel_find_best_PLL,
 282 };
 283
 284 static const intel_limit_t intel_limits_i8xx_lvds = {
 285         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 286         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 287         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 288         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 289         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 290         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 291         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 292         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 293         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 294                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 295         .find_pll = intel_find_best_PLL,
 296 };
 297
 298 static const intel_limit_t intel_limits_i9xx_sdvo = {
 299         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 300         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 301         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 302         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 303         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 304         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 305         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 306         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 307         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 308                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 309         .find_pll = intel_find_best_PLL,
 310 };
 311
 312 static const intel_limit_t intel_limits_i9xx_lvds = {
 313         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 314         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 315         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 316         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 317         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 318         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 319         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 320         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 321         /* The single-channel range is 25-112Mhz, and dual-channel
 322          * is 80-224Mhz.  Prefer single channel as much as possible.
 323          */
 324         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 326         .find_pll = intel_find_best_PLL,
 327 };
 328
 329     /* below parameter and function is for G4X Chipset Family*/
 330 static const intel_limit_t intel_limits_g4x_sdvo = {
 331         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 332         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 333         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 334         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 335         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 336         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 337         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 338         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 339         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 340                  .p2_slow = G4X_P2_SDVO_SLOW,
 341                  .p2_fast = G4X_P2_SDVO_FAST
 342         },
 343         .find_pll = intel_g4x_find_best_PLL,
 344 };
 345
 346 static const intel_limit_t intel_limits_g4x_hdmi = {
 347         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 348         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 349         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 350         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 351         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 352         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 353         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 354         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 355         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 356                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 357                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 358         },
 359         .find_pll = intel_g4x_find_best_PLL,
 360 };
 361
 362 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 363         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 364                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 365         .vco = { .min = G4X_VCO_MIN,
 366                  .max = G4X_VCO_MAX },
 367         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 368                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 369         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 370                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 371         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 372                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 373         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 374                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 375         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 376                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 377         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 378                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 379         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 380                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 381                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 382         },
 383         .find_pll = intel_g4x_find_best_PLL,
 384 };
 385
 386 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 387         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 388                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 389         .vco = { .min = G4X_VCO_MIN,
 390                  .max = G4X_VCO_MAX },
 391         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 392                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 393         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 394                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 395         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 396                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 397         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 398                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 399         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 400                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 401         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 402                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 403         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 404                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 405                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 406         },
 407         .find_pll = intel_g4x_find_best_PLL,
 408 };
 409
 410 static const intel_limit_t intel_limits_g4x_display_port = {
 411         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 412                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 413         .vco = { .min = G4X_VCO_MIN,
 414                  .max = G4X_VCO_MAX},
 415         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 416                  .max = G4X_N_DISPLAY_PORT_MAX },
 417         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 418                  .max = G4X_M_DISPLAY_PORT_MAX },
 419         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 420                  .max = G4X_M1_DISPLAY_PORT_MAX },
 421         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 422                  .max = G4X_M2_DISPLAY_PORT_MAX },
 423         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 424                  .max = G4X_P_DISPLAY_PORT_MAX },
 425         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 426                  .max = G4X_P1_DISPLAY_PORT_MAX},
 427         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 428                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 429                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 430         .find_pll = intel_find_pll_g4x_dp,
 431 };
 432
 433 static const intel_limit_t intel_limits_igd_sdvo = {
 434         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 435         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 436         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 437         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 438         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 439         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 440         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 441         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 442         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 443                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 444         .find_pll = intel_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_igd_lvds = {
 448         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 449         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 450         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 451         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 452         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 453         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 454         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 455         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 456         /* IGD only supports single-channel mode. */
 457         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 458                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 459         .find_pll = intel_find_best_PLL,
 460 };
 461
 462 static const intel_limit_t intel_limits_igdng_sdvo = {
 463         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 464         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 465         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 466         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 467         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 468         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 469         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 470         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 471         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 472                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 473                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 474         .find_pll = intel_igdng_find_best_PLL,
 475 };
 476
 477 static const intel_limit_t intel_limits_igdng_lvds = {
 478         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 479         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 480         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 481         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 482         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 483         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 484         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 485         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 486         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 487                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 488                  .p2_fast = IGDNG_P2_LVDS_FAST },
 489         .find_pll = intel_igdng_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 493 {
 494         const intel_limit_t *limit;
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 496                 limit = &intel_limits_igdng_lvds;
 497         else
 498                 limit = &intel_limits_igdng_sdvo;
 499
 500         return limit;
 501 }
 502
 503 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         const intel_limit_t *limit;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 511                     LVDS_CLKB_POWER_UP)
 512                         /* LVDS with dual channel */
 513                         limit = &intel_limits_g4x_dual_channel_lvds;
 514                 else
 515                         /* LVDS with dual channel */
 516                         limit = &intel_limits_g4x_single_channel_lvds;
 517         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 518                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 519                 limit = &intel_limits_g4x_hdmi;
 520         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 521                 limit = &intel_limits_g4x_sdvo;
 522         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 523                 limit = &intel_limits_g4x_display_port;
 524         } else /* The option is for other outputs */
 525                 limit = &intel_limits_i9xx_sdvo;
 526
 527         return limit;
 528 }
 529
 530 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 531 {
 532         struct drm_device *dev = crtc->dev;
 533         const intel_limit_t *limit;
 534
 535         if (IS_IGDNG(dev))
 536                 limit = intel_igdng_limit(crtc);
 537         else if (IS_G4X(dev)) {
 538                 limit = intel_g4x_limit(crtc);
 539         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 540                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 541                         limit = &intel_limits_i9xx_lvds;
 542                 else
 543                         limit = &intel_limits_i9xx_sdvo;
 544         } else if (IS_IGD(dev)) {
 545                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 546                         limit = &intel_limits_igd_lvds;
 547                 else
 548                         limit = &intel_limits_igd_sdvo;
 549         } else {
 550                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 551                         limit = &intel_limits_i8xx_lvds;
 552                 else
 553                         limit = &intel_limits_i8xx_dvo;
 554         }
 555         return limit;
 556 }
 557
 558 /* m1 is reserved as 0 in IGD, n is a ring counter */
 559 static void igd_clock(int refclk, intel_clock_t *clock)
 560 {
 561         clock->m = clock->m2 + 2;
 562         clock->p = clock->p1 * clock->p2;
 563         clock->vco = refclk * clock->m / clock->n;
 564         clock->dot = clock->vco / clock->p;
 565 }
 566
 567 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 568 {
 569         if (IS_IGD(dev)) {
 570                 igd_clock(refclk, clock);
 571                 return;
 572         }
 573         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 574         clock->p = clock->p1 * clock->p2;
 575         clock->vco = refclk * clock->m / (clock->n + 2);
 576         clock->dot = clock->vco / clock->p;
 577 }
 578
 579 /**
 580  * Returns whether any output on the specified pipe is of the specified type
 581  */
 582 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 583 {
 584     struct drm_device *dev = crtc->dev;
 585     struct drm_mode_config *mode_config = &dev->mode_config;
 586     struct drm_connector *l_entry;
 587
 588     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 589             if (l_entry->encoder &&
 590                 l_entry->encoder->crtc == crtc) {
 591                     struct intel_output *intel_output = to_intel_output(l_entry);
 592                     if (intel_output->type == type)
 593                             return true;
 594             }
 595     }
 596     return false;
 597 }
 598
 599 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 600 /**
 601  * Returns whether the given set of divisors are valid for a given refclk with
 602  * the given connectors.
 603  */
 604
 605 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 606 {
 607         const intel_limit_t *limit = intel_limit (crtc);
 608         struct drm_device *dev = crtc->dev;
 609
 610         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 611                 INTELPllInvalid ("p1 out of range\n");
 612         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 613                 INTELPllInvalid ("p out of range\n");
 614         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 615                 INTELPllInvalid ("m2 out of range\n");
 616         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 617                 INTELPllInvalid ("m1 out of range\n");
 618         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 619                 INTELPllInvalid ("m1 <= m2\n");
 620         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 621                 INTELPllInvalid ("m out of range\n");
 622         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 623                 INTELPllInvalid ("n out of range\n");
 624         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 625                 INTELPllInvalid ("vco out of range\n");
 626         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 627          * connector, etc., rather than just a single range.
 628          */
 629         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 630                 INTELPllInvalid ("dot out of range\n");
 631
 632         return true;
 633 }
 634
 635 static bool
 636 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 637                     int target, int refclk, intel_clock_t *best_clock)
 638
 639 {
 640         struct drm_device *dev = crtc->dev;
 641         struct drm_i915_private *dev_priv = dev->dev_private;
 642         intel_clock_t clock;
 643         int err = target;
 644
 645         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 646             (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
 647                 /*
 648                  * For LVDS, if the panel is on, just rely on its current
 649                  * settings for dual-channel.  We haven't figured out how to
 650                  * reliably set up different single/dual channel state, if we
 651                  * even can.
 652                  */
 653                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP)
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset (best_clock, 0, sizeof (*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 668                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 669                         /* m1 is always 0 in IGD */
 670                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 671                                 break;
 672                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 673                              clock.n++) {
 674                                 for (clock.p1 = limit->p1.min;
 675                                      clock.p1 <= limit->p1.max; clock.p1++) {
 676                                         int this_err;
 677
 678                                         intel_clock(dev, refclk, &clock);
 679
 680                                         if (!intel_PLL_is_valid(crtc, &clock))
 681                                                 continue;
 682
 683                                         this_err = abs(clock.dot - target);
 684                                         if (this_err < err) {
 685                                                 *best_clock = clock;
 686                                                 err = this_err;
 687                                         }
 688                                 }
 689                         }
 690                 }
 691         }
 692
 693         return (err != target);
 694 }
 695
 696 static bool
 697 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 698                         int target, int refclk, intel_clock_t *best_clock)
 699 {
 700         struct drm_device *dev = crtc->dev;
 701         struct drm_i915_private *dev_priv = dev->dev_private;
 702         intel_clock_t clock;
 703         int max_n;
 704         bool found;
 705         /* approximately equals target * 0.00488 */
 706         int err_most = (target >> 8) + (target >> 10);
 707         found = false;
 708
 709         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 710                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 711                     LVDS_CLKB_POWER_UP)
 712                         clock.p2 = limit->p2.p2_fast;
 713                 else
 714                         clock.p2 = limit->p2.p2_slow;
 715         } else {
 716                 if (target < limit->p2.dot_limit)
 717                         clock.p2 = limit->p2.p2_slow;
 718                 else
 719                         clock.p2 = limit->p2.p2_fast;
 720         }
 721
 722         memset(best_clock, 0, sizeof(*best_clock));
 723         max_n = limit->n.max;
 724         /* based on hardware requriment prefer smaller n to precision */
 725         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 726                 /* based on hardware requirment prefere larger m1,m2, p1 */
 727                 for (clock.m1 = limit->m1.max;
 728                      clock.m1 >= limit->m1.min; clock.m1--) {
 729                         for (clock.m2 = limit->m2.max;
 730                              clock.m2 >= limit->m2.min; clock.m2--) {
 731                                 for (clock.p1 = limit->p1.max;
 732                                      clock.p1 >= limit->p1.min; clock.p1--) {
 733                                         int this_err;
 734
 735                                         intel_clock(dev, refclk, &clock);
 736                                         if (!intel_PLL_is_valid(crtc, &clock))
 737                                                 continue;
 738                                         this_err = abs(clock.dot - target) ;
 739                                         if (this_err < err_most) {
 740                                                 *best_clock = clock;
 741                                                 err_most = this_err;
 742                                                 max_n = clock.n;
 743                                                 found = true;
 744                                         }
 745                                 }
 746                         }
 747                 }
 748         }
 749         return found;
 750 }
 751
 752 static bool
 753 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 754                         int target, int refclk, intel_clock_t *best_clock)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_i915_private *dev_priv = dev->dev_private;
 758         intel_clock_t clock;
 759         int max_n;
 760         bool found;
 761         int err_most = 47;
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 766                     LVDS_CLKB_POWER_UP)
 767                         clock.p2 = limit->p2.p2_fast;
 768                 else
 769                         clock.p2 = limit->p2.p2_slow;
 770         } else {
 771                 if (target < limit->p2.dot_limit)
 772                         clock.p2 = limit->p2.p2_slow;
 773                 else
 774                         clock.p2 = limit->p2.p2_fast;
 775         }
 776
 777         memset(best_clock, 0, sizeof(*best_clock));
 778         max_n = limit->n.max;
 779         /* based on hardware requriment prefer smaller n to precision */
 780         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 781                 /* based on hardware requirment prefere larger m1,m2, p1 */
 782                 for (clock.m1 = limit->m1.max;
 783                      clock.m1 >= limit->m1.min; clock.m1--) {
 784                         for (clock.m2 = limit->m2.max;
 785                              clock.m2 >= limit->m2.min; clock.m2--) {
 786                                 for (clock.p1 = limit->p1.max;
 787                                      clock.p1 >= limit->p1.min; clock.p1--) {
 788                                         int this_err;
 789
 790                                         intel_clock(dev, refclk, &clock);
 791                                         if (!intel_PLL_is_valid(crtc, &clock))
 792                                                 continue;
 793                                         this_err = abs((10000 - (target*10000/clock.dot)));
 794                                         if (this_err < err_most) {
 795                                                 *best_clock = clock;
 796                                                 err_most = this_err;
 797                                                 max_n = clock.n;
 798                                                 found = true;
 799                                                 /* found on first matching */
 800                                                 goto out;
 801                                         }
 802                                 }
 803                         }
 804                 }
 805         }
 806 out:
 807         return found;
 808 }
 809
 810 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 811 static bool
 812 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 813                       int target, int refclk, intel_clock_t *best_clock)
 814 {
 815     intel_clock_t clock;
 816     if (target < 200000) {
 817         clock.dot = 161670;
 818         clock.p = 20;
 819         clock.p1 = 2;
 820         clock.p2 = 10;
 821         clock.n = 0x01;
 822         clock.m = 97;
 823         clock.m1 = 0x10;
 824         clock.m2 = 0x05;
 825     } else {
 826         clock.dot = 270000;
 827         clock.p = 10;
 828         clock.p1 = 1;
 829         clock.p2 = 10;
 830         clock.n = 0x02;
 831         clock.m = 108;
 832         clock.m1 = 0x12;
 833         clock.m2 = 0x06;
 834     }
 835     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 836     return true;
 837 }
 838
 839 void
 840 intel_wait_for_vblank(struct drm_device *dev)
 841 {
 842         /* Wait for 20ms, i.e. one cycle at 50hz. */
 843         mdelay(20);
 844 }
 845
 846 static int
 847 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 848                     struct drm_framebuffer *old_fb)
 849 {
 850         struct drm_device *dev = crtc->dev;
 851         struct drm_i915_private *dev_priv = dev->dev_private;
 852         struct drm_i915_master_private *master_priv;
 853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 854         struct intel_framebuffer *intel_fb;
 855         struct drm_i915_gem_object *obj_priv;
 856         struct drm_gem_object *obj;
 857         int pipe = intel_crtc->pipe;
 858         unsigned long Start, Offset;
 859         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 860         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 861         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 862         int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
 863         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 864         u32 dspcntr, alignment;
 865         int ret;
 866
 867         /* no fb bound */
 868         if (!crtc->fb) {
 869                 DRM_DEBUG("No FB bound\n");
 870                 return 0;
 871         }
 872
 873         switch (pipe) {
 874         case 0:
 875         case 1:
 876                 break;
 877         default:
 878                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 879                 return -EINVAL;
 880         }
 881
 882         intel_fb = to_intel_framebuffer(crtc->fb);
 883         obj = intel_fb->obj;
 884         obj_priv = obj->driver_private;
 885
 886         switch (obj_priv->tiling_mode) {
 887         case I915_TILING_NONE:
 888                 alignment = 64 * 1024;
 889                 break;
 890         case I915_TILING_X:
 891                 /* pin() will align the object as required by fence */
 892                 alignment = 0;
 893                 break;
 894         case I915_TILING_Y:
 895                 /* FIXME: Is this true? */
 896                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 897                 return -EINVAL;
 898         default:
 899                 BUG();
 900         }
 901
 902         mutex_lock(&dev->struct_mutex);
 903         ret = i915_gem_object_pin(obj, alignment);
 904         if (ret != 0) {
 905                 mutex_unlock(&dev->struct_mutex);
 906                 return ret;
 907         }
 908
 909         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 910         if (ret != 0) {
 911                 i915_gem_object_unpin(obj);
 912                 mutex_unlock(&dev->struct_mutex);
 913                 return ret;
 914         }
 915
 916         /* Pre-i965 needs to install a fence for tiled scan-out */
 917         if (!IS_I965G(dev) &&
 918             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 919             obj_priv->tiling_mode != I915_TILING_NONE) {
 920                 ret = i915_gem_object_get_fence_reg(obj);
 921                 if (ret != 0) {
 922                         i915_gem_object_unpin(obj);
 923                         mutex_unlock(&dev->struct_mutex);
 924                         return ret;
 925                 }
 926         }
 927
 928         dspcntr = I915_READ(dspcntr_reg);
 929         /* Mask out pixel format bits in case we change it */
 930         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 931         switch (crtc->fb->bits_per_pixel) {
 932         case 8:
 933                 dspcntr |= DISPPLANE_8BPP;
 934                 break;
 935         case 16:
 936                 if (crtc->fb->depth == 15)
 937                         dspcntr |= DISPPLANE_15_16BPP;
 938                 else
 939                         dspcntr |= DISPPLANE_16BPP;
 940                 break;
 941         case 24:
 942         case 32:
 943                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 944                 break;
 945         default:
 946                 DRM_ERROR("Unknown color depth\n");
 947                 i915_gem_object_unpin(obj);
 948                 mutex_unlock(&dev->struct_mutex);
 949                 return -EINVAL;
 950         }
 951         if (IS_I965G(dev)) {
 952                 if (obj_priv->tiling_mode != I915_TILING_NONE)
 953                         dspcntr |= DISPPLANE_TILED;
 954                 else
 955                         dspcntr &= ~DISPPLANE_TILED;
 956         }
 957
 958         I915_WRITE(dspcntr_reg, dspcntr);
 959
 960         Start = obj_priv->gtt_offset;
 961         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 962
 963         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 964         I915_WRITE(dspstride, crtc->fb->pitch);
 965         if (IS_I965G(dev)) {
 966                 I915_WRITE(dspbase, Offset);
 967                 I915_READ(dspbase);
 968                 I915_WRITE(dspsurf, Start);
 969                 I915_READ(dspsurf);
 970                 I915_WRITE(dsptileoff, (y << 16) | x);
 971         } else {
 972                 I915_WRITE(dspbase, Start + Offset);
 973                 I915_READ(dspbase);
 974         }
 975
 976         intel_wait_for_vblank(dev);
 977
 978         if (old_fb) {
 979                 intel_fb = to_intel_framebuffer(old_fb);
 980                 i915_gem_object_unpin(intel_fb->obj);
 981         }
 982         mutex_unlock(&dev->struct_mutex);
 983
 984         if (!dev->primary->master)
 985                 return 0;
 986
 987         master_priv = dev->primary->master->driver_priv;
 988         if (!master_priv->sarea_priv)
 989                 return 0;
 990
 991         if (pipe) {
 992                 master_priv->sarea_priv->pipeB_x = x;
 993                 master_priv->sarea_priv->pipeB_y = y;
 994         } else {
 995                 master_priv->sarea_priv->pipeA_x = x;
 996                 master_priv->sarea_priv->pipeA_y = y;
 997         }
 998
 999         return 0;
1000 }
1001
1002 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1003 {
1004         struct drm_device *dev = crtc->dev;
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007         int pipe = intel_crtc->pipe;
1008         int plane = intel_crtc->pipe;
1009         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1010         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1011         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1012         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1013         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1014         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1015         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1016         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1017         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1018         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1019         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1020         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1021         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1022         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1023         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1024         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1025         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1026         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1027         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1028         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1029         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1030         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1031         u32 temp;
1032         int tries = 5, j;
1033
1034         /* XXX: When our outputs are all unaware of DPMS modes other than off
1035          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1036          */
1037         switch (mode) {
1038         case DRM_MODE_DPMS_ON:
1039         case DRM_MODE_DPMS_STANDBY:
1040         case DRM_MODE_DPMS_SUSPEND:
1041                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1042                 /* enable PCH DPLL */
1043                 temp = I915_READ(pch_dpll_reg);
1044                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1045                         I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1046                         I915_READ(pch_dpll_reg);
1047                 }
1048
1049                 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1050                 temp = I915_READ(fdi_rx_reg);
1051                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1052                                 FDI_SEL_PCDCLK |
1053                                 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1054                 I915_READ(fdi_rx_reg);
1055                 udelay(200);
1056
1057                 /* Enable CPU FDI TX PLL, always on for IGDNG */
1058                 temp = I915_READ(fdi_tx_reg);
1059                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1060                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1061                         I915_READ(fdi_tx_reg);
1062                         udelay(100);
1063                 }
1064
1065                 /* Enable CPU pipe */
1066                 temp = I915_READ(pipeconf_reg);
1067                 if ((temp & PIPEACONF_ENABLE) == 0) {
1068                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1069                         I915_READ(pipeconf_reg);
1070                         udelay(100);
1071                 }
1072
1073                 /* configure and enable CPU plane */
1074                 temp = I915_READ(dspcntr_reg);
1075                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1076                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1077                         /* Flush the plane changes */
1078                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1079                 }
1080
1081                 /* enable CPU FDI TX and PCH FDI RX */
1082                 temp = I915_READ(fdi_tx_reg);
1083                 temp |= FDI_TX_ENABLE;
1084                 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1085                 temp &= ~FDI_LINK_TRAIN_NONE;
1086                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1087                 I915_WRITE(fdi_tx_reg, temp);
1088                 I915_READ(fdi_tx_reg);
1089
1090                 temp = I915_READ(fdi_rx_reg);
1091                 temp &= ~FDI_LINK_TRAIN_NONE;
1092                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1093                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1094                 I915_READ(fdi_rx_reg);
1095
1096                 udelay(150);
1097
1098                 /* Train FDI. */
1099                 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1100                    for train result */
1101                 temp = I915_READ(fdi_rx_imr_reg);
1102                 temp &= ~FDI_RX_SYMBOL_LOCK;
1103                 temp &= ~FDI_RX_BIT_LOCK;
1104                 I915_WRITE(fdi_rx_imr_reg, temp);
1105                 I915_READ(fdi_rx_imr_reg);
1106                 udelay(150);
1107
1108                 temp = I915_READ(fdi_rx_iir_reg);
1109                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1110
1111                 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1112                         for (j = 0; j < tries; j++) {
1113                                 temp = I915_READ(fdi_rx_iir_reg);
1114                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1115                                 if (temp & FDI_RX_BIT_LOCK)
1116                                         break;
1117                                 udelay(200);
1118                         }
1119                         if (j != tries)
1120                                 I915_WRITE(fdi_rx_iir_reg,
1121                                                 temp | FDI_RX_BIT_LOCK);
1122                         else
1123                                 DRM_DEBUG("train 1 fail\n");
1124                 } else {
1125                         I915_WRITE(fdi_rx_iir_reg,
1126                                         temp | FDI_RX_BIT_LOCK);
1127                         DRM_DEBUG("train 1 ok 2!\n");
1128                 }
1129                 temp = I915_READ(fdi_tx_reg);
1130                 temp &= ~FDI_LINK_TRAIN_NONE;
1131                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1132                 I915_WRITE(fdi_tx_reg, temp);
1133
1134                 temp = I915_READ(fdi_rx_reg);
1135                 temp &= ~FDI_LINK_TRAIN_NONE;
1136                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1137                 I915_WRITE(fdi_rx_reg, temp);
1138
1139                 udelay(150);
1140
1141                 temp = I915_READ(fdi_rx_iir_reg);
1142                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1143
1144                 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1145                         for (j = 0; j < tries; j++) {
1146                                 temp = I915_READ(fdi_rx_iir_reg);
1147                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1148                                 if (temp & FDI_RX_SYMBOL_LOCK)
1149                                         break;
1150                                 udelay(200);
1151                         }
1152                         if (j != tries) {
1153                                 I915_WRITE(fdi_rx_iir_reg,
1154                                                 temp | FDI_RX_SYMBOL_LOCK);
1155                                 DRM_DEBUG("train 2 ok 1!\n");
1156                         } else
1157                                 DRM_DEBUG("train 2 fail\n");
1158                 } else {
1159                         I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1160                         DRM_DEBUG("train 2 ok 2!\n");
1161                 }
1162                 DRM_DEBUG("train done\n");
1163
1164                 /* set transcoder timing */
1165                 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1166                 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1167                 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1168
1169                 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1170                 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1171                 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1172
1173                 /* enable PCH transcoder */
1174                 temp = I915_READ(transconf_reg);
1175                 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1176                 I915_READ(transconf_reg);
1177
1178                 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1179                         ;
1180
1181                 /* enable normal */
1182
1183                 temp = I915_READ(fdi_tx_reg);
1184                 temp &= ~FDI_LINK_TRAIN_NONE;
1185                 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1186                                 FDI_TX_ENHANCE_FRAME_ENABLE);
1187                 I915_READ(fdi_tx_reg);
1188
1189                 temp = I915_READ(fdi_rx_reg);
1190                 temp &= ~FDI_LINK_TRAIN_NONE;
1191                 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1192                                 FDI_RX_ENHANCE_FRAME_ENABLE);
1193                 I915_READ(fdi_rx_reg);
1194
1195                 /* wait one idle pattern time */
1196                 udelay(100);
1197
1198                 intel_crtc_load_lut(crtc);
1199
1200         break;
1201         case DRM_MODE_DPMS_OFF:
1202                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1203
1204                 /* Disable the VGA plane that we never use */
1205                 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1206
1207                 /* Disable display plane */
1208                 temp = I915_READ(dspcntr_reg);
1209                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1210                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1211                         /* Flush the plane changes */
1212                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1213                         I915_READ(dspbase_reg);
1214                 }
1215
1216                 /* disable cpu pipe, disable after all planes disabled */
1217                 temp = I915_READ(pipeconf_reg);
1218                 if ((temp & PIPEACONF_ENABLE) != 0) {
1219                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1220                         I915_READ(pipeconf_reg);
1221                         /* wait for cpu pipe off, pipe state */
1222                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1223                                 ;
1224                 } else
1225                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1226
1227                 /* IGDNG-A : disable cpu panel fitter ? */
1228                 temp = I915_READ(pf_ctl_reg);
1229                 if ((temp & PF_ENABLE) != 0) {
1230                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1231                         I915_READ(pf_ctl_reg);
1232                 }
1233
1234                 /* disable CPU FDI tx and PCH FDI rx */
1235                 temp = I915_READ(fdi_tx_reg);
1236                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1237                 I915_READ(fdi_tx_reg);
1238
1239                 temp = I915_READ(fdi_rx_reg);
1240                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1241                 I915_READ(fdi_rx_reg);
1242
1243                 /* still set train pattern 1 */
1244                 temp = I915_READ(fdi_tx_reg);
1245                 temp &= ~FDI_LINK_TRAIN_NONE;
1246                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1247                 I915_WRITE(fdi_tx_reg, temp);
1248
1249                 temp = I915_READ(fdi_rx_reg);
1250                 temp &= ~FDI_LINK_TRAIN_NONE;
1251                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1252                 I915_WRITE(fdi_rx_reg, temp);
1253
1254                 /* disable PCH transcoder */
1255                 temp = I915_READ(transconf_reg);
1256                 if ((temp & TRANS_ENABLE) != 0) {
1257                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1258                         I915_READ(transconf_reg);
1259                         /* wait for PCH transcoder off, transcoder state */
1260                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1261                                 ;
1262                 }
1263
1264                 /* disable PCH DPLL */
1265                 temp = I915_READ(pch_dpll_reg);
1266                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1267                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1268                         I915_READ(pch_dpll_reg);
1269                 }
1270
1271                 temp = I915_READ(fdi_rx_reg);
1272                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1273                         temp &= ~FDI_SEL_PCDCLK;
1274                         temp &= ~FDI_RX_PLL_ENABLE;
1275                         I915_WRITE(fdi_rx_reg, temp);
1276                         I915_READ(fdi_rx_reg);
1277                 }
1278
1279                 /* Wait for the clocks to turn off. */
1280                 udelay(150);
1281                 break;
1282         }
1283 }
1284
1285 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1286 {
1287         struct drm_device *dev = crtc->dev;
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1290         int pipe = intel_crtc->pipe;
1291         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1292         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1293         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1294         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1295         u32 temp;
1296
1297         /* XXX: When our outputs are all unaware of DPMS modes other than off
1298          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1299          */
1300         switch (mode) {
1301         case DRM_MODE_DPMS_ON:
1302         case DRM_MODE_DPMS_STANDBY:
1303         case DRM_MODE_DPMS_SUSPEND:
1304                 /* Enable the DPLL */
1305                 temp = I915_READ(dpll_reg);
1306                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1307                         I915_WRITE(dpll_reg, temp);
1308                         I915_READ(dpll_reg);
1309                         /* Wait for the clocks to stabilize. */
1310                         udelay(150);
1311                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1312                         I915_READ(dpll_reg);
1313                         /* Wait for the clocks to stabilize. */
1314                         udelay(150);
1315                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1316                         I915_READ(dpll_reg);
1317                         /* Wait for the clocks to stabilize. */
1318                         udelay(150);
1319                 }
1320
1321                 /* Enable the pipe */
1322                 temp = I915_READ(pipeconf_reg);
1323                 if ((temp & PIPEACONF_ENABLE) == 0)
1324                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1325
1326                 /* Enable the plane */
1327                 temp = I915_READ(dspcntr_reg);
1328                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1329                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1330                         /* Flush the plane changes */
1331                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1332                 }
1333
1334                 intel_crtc_load_lut(crtc);
1335
1336                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1337                 //intel_crtc_dpms_video(crtc, true); TODO
1338         break;
1339         case DRM_MODE_DPMS_OFF:
1340                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1341                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1342
1343                 /* Disable the VGA plane that we never use */
1344                 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1345
1346                 /* Disable display plane */
1347                 temp = I915_READ(dspcntr_reg);
1348                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1349                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1350                         /* Flush the plane changes */
1351                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1352                         I915_READ(dspbase_reg);
1353                 }
1354
1355                 if (!IS_I9XX(dev)) {
1356                         /* Wait for vblank for the disable to take effect */
1357                         intel_wait_for_vblank(dev);
1358                 }
1359
1360                 /* Next, disable display pipes */
1361                 temp = I915_READ(pipeconf_reg);
1362                 if ((temp & PIPEACONF_ENABLE) != 0) {
1363                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1364                         I915_READ(pipeconf_reg);
1365                 }
1366
1367                 /* Wait for vblank for the disable to take effect. */
1368                 intel_wait_for_vblank(dev);
1369
1370                 temp = I915_READ(dpll_reg);
1371                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1372                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1373                         I915_READ(dpll_reg);
1374                 }
1375
1376                 /* Wait for the clocks to turn off. */
1377                 udelay(150);
1378                 break;
1379         }
1380 }
1381
1382 /**
1383  * Sets the power management mode of the pipe and plane.
1384  *
1385  * This code should probably grow support for turning the cursor off and back
1386  * on appropriately at the same time as we're turning the pipe off/on.
1387  */
1388 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1389 {
1390         struct drm_device *dev = crtc->dev;
1391         struct drm_i915_master_private *master_priv;
1392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1393         int pipe = intel_crtc->pipe;
1394         bool enabled;
1395
1396         if (IS_IGDNG(dev))
1397                 igdng_crtc_dpms(crtc, mode);
1398         else
1399                 i9xx_crtc_dpms(crtc, mode);
1400
1401         if (!dev->primary->master)
1402                 return;
1403
1404         master_priv = dev->primary->master->driver_priv;
1405         if (!master_priv->sarea_priv)
1406                 return;
1407
1408         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1409
1410         switch (pipe) {
1411         case 0:
1412                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1413                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1414                 break;
1415         case 1:
1416                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1417                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1418                 break;
1419         default:
1420                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1421                 break;
1422         }
1423
1424         intel_crtc->dpms_mode = mode;
1425 }
1426
1427 static void intel_crtc_prepare (struct drm_crtc *crtc)
1428 {
1429         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1430         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1431 }
1432
1433 static void intel_crtc_commit (struct drm_crtc *crtc)
1434 {
1435         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1436         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1437 }
1438
1439 void intel_encoder_prepare (struct drm_encoder *encoder)
1440 {
1441         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1442         /* lvds has its own version of prepare see intel_lvds_prepare */
1443         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1444 }
1445
1446 void intel_encoder_commit (struct drm_encoder *encoder)
1447 {
1448         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1449         /* lvds has its own version of commit see intel_lvds_commit */
1450         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1451 }
1452
1453 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1454                                   struct drm_display_mode *mode,
1455                                   struct drm_display_mode *adjusted_mode)
1456 {
1457         struct drm_device *dev = crtc->dev;
1458         if (IS_IGDNG(dev)) {
1459                 /* FDI link clock is fixed at 2.7G */
1460                 if (mode->clock * 3 > 27000 * 4)
1461                         return MODE_CLOCK_HIGH;
1462         }
1463         return true;
1464 }
1465
1466
1467 /** Returns the core display clock speed for i830 - i945 */
1468 static int intel_get_core_clock_speed(struct drm_device *dev)
1469 {
1470
1471         /* Core clock values taken from the published datasheets.
1472          * The 830 may go up to 166 Mhz, which we should check.
1473          */
1474         if (IS_I945G(dev))
1475                 return 400000;
1476         else if (IS_I915G(dev))
1477                 return 333000;
1478         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1479                 return 200000;
1480         else if (IS_I915GM(dev)) {
1481                 u16 gcfgc = 0;
1482
1483                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1484
1485                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1486                         return 133000;
1487                 else {
1488                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1489                         case GC_DISPLAY_CLOCK_333_MHZ:
1490                                 return 333000;
1491                         default:
1492                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1493                                 return 190000;
1494                         }
1495                 }
1496         } else if (IS_I865G(dev))
1497                 return 266000;
1498         else if (IS_I855(dev)) {
1499                 u16 hpllcc = 0;
1500                 /* Assume that the hardware is in the high speed state.  This
1501                  * should be the default.
1502                  */
1503                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1504                 case GC_CLOCK_133_200:
1505                 case GC_CLOCK_100_200:
1506                         return 200000;
1507                 case GC_CLOCK_166_250:
1508                         return 250000;
1509                 case GC_CLOCK_100_133:
1510                         return 133000;
1511                 }
1512         } else /* 852, 830 */
1513                 return 133000;
1514
1515         return 0; /* Silence gcc warning */
1516 }
1517
1518
1519 /**
1520  * Return the pipe currently connected to the panel fitter,
1521  * or -1 if the panel fitter is not present or not in use
1522  */
1523 static int intel_panel_fitter_pipe (struct drm_device *dev)
1524 {
1525         struct drm_i915_private *dev_priv = dev->dev_private;
1526         u32  pfit_control;
1527
1528         /* i830 doesn't have a panel fitter */
1529         if (IS_I830(dev))
1530                 return -1;
1531
1532         pfit_control = I915_READ(PFIT_CONTROL);
1533
1534         /* See if the panel fitter is in use */
1535         if ((pfit_control & PFIT_ENABLE) == 0)
1536                 return -1;
1537
1538         /* 965 can place panel fitter on either pipe */
1539         if (IS_I965G(dev))
1540                 return (pfit_control >> 29) & 0x3;
1541
1542         /* older chips can only use pipe 1 */
1543         return 1;
1544 }
1545
1546 struct fdi_m_n {
1547         u32        tu;
1548         u32        gmch_m;
1549         u32        gmch_n;
1550         u32        link_m;
1551         u32        link_n;
1552 };
1553
1554 static void
1555 fdi_reduce_ratio(u32 *num, u32 *den)
1556 {
1557         while (*num > 0xffffff || *den > 0xffffff) {
1558                 *num >>= 1;
1559                 *den >>= 1;
1560         }
1561 }
1562
1563 #define DATA_N 0x800000
1564 #define LINK_N 0x80000
1565
1566 static void
1567 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1568                 int pixel_clock, int link_clock,
1569                 struct fdi_m_n *m_n)
1570 {
1571         u64 temp;
1572
1573         m_n->tu = 64; /* default size */
1574
1575         temp = (u64) DATA_N * pixel_clock;
1576         temp = div_u64(temp, link_clock);
1577         m_n->gmch_m = (temp * bytes_per_pixel) / nlanes;
1578         m_n->gmch_n = DATA_N;
1579         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1580
1581         temp = (u64) LINK_N * pixel_clock;
1582         m_n->link_m = div_u64(temp, link_clock);
1583         m_n->link_n = LINK_N;
1584         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1585 }
1586
1587
1588 static int intel_crtc_mode_set(struct drm_crtc *crtc,
1589                                struct drm_display_mode *mode,
1590                                struct drm_display_mode *adjusted_mode,
1591                                int x, int y,
1592                                struct drm_framebuffer *old_fb)
1593 {
1594         struct drm_device *dev = crtc->dev;
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1597         int pipe = intel_crtc->pipe;
1598         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
1599         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1600         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
1601         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1602         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1603         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1604         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1605         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1606         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1607         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1608         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1609         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
1610         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
1611         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
1612         int refclk, num_outputs = 0;
1613         intel_clock_t clock;
1614         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
1615         bool ok, is_sdvo = false, is_dvo = false;
1616         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
1617         struct drm_mode_config *mode_config = &dev->mode_config;
1618         struct drm_connector *connector;
1619         const intel_limit_t *limit;
1620         int ret;
1621         struct fdi_m_n m_n = {0};
1622         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
1623         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
1624         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
1625         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
1626         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
1627         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1628         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1629         int lvds_reg = LVDS;
1630         u32 temp;
1631         int sdvo_pixel_multiply;
1632
1633         drm_vblank_pre_modeset(dev, pipe);
1634
1635         list_for_each_entry(connector, &mode_config->connector_list, head) {
1636                 struct intel_output *intel_output = to_intel_output(connector);
1637
1638                 if (!connector->encoder || connector->encoder->crtc != crtc)
1639                         continue;
1640
1641                 switch (intel_output->type) {
1642                 case INTEL_OUTPUT_LVDS:
1643                         is_lvds = true;
1644                         break;
1645                 case INTEL_OUTPUT_SDVO:
1646                 case INTEL_OUTPUT_HDMI:
1647                         is_sdvo = true;
1648                         if (intel_output->needs_tv_clock)
1649                                 is_tv = true;
1650                         break;
1651                 case INTEL_OUTPUT_DVO:
1652                         is_dvo = true;
1653                         break;
1654                 case INTEL_OUTPUT_TVOUT:
1655                         is_tv = true;
1656                         break;
1657                 case INTEL_OUTPUT_ANALOG:
1658                         is_crt = true;
1659                         break;
1660                 case INTEL_OUTPUT_DISPLAYPORT:
1661                         is_dp = true;
1662                         break;
1663                 }
1664
1665                 num_outputs++;
1666         }
1667
1668         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
1669                 refclk = dev_priv->lvds_ssc_freq * 1000;
1670                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1671         } else if (IS_I9XX(dev)) {
1672                 refclk = 96000;
1673                 if (IS_IGDNG(dev))
1674                         refclk = 120000; /* 120Mhz refclk */
1675         } else {
1676                 refclk = 48000;
1677         }
1678
1679
1680         /*
1681          * Returns a set of divisors for the desired target clock with the given
1682          * refclk, or FALSE.  The returned values represent the clock equation:
1683          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1684          */
1685         limit = intel_limit(crtc);
1686         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1687         if (!ok) {
1688                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1689                 drm_vblank_post_modeset(dev, pipe);
1690                 return -EINVAL;
1691         }
1692
1693         /* SDVO TV has fixed PLL values depend on its clock range,
1694            this mirrors vbios setting. */
1695         if (is_sdvo && is_tv) {
1696                 if (adjusted_mode->clock >= 100000
1697                                 && adjusted_mode->clock < 140500) {
1698                         clock.p1 = 2;
1699                         clock.p2 = 10;
1700                         clock.n = 3;
1701                         clock.m1 = 16;
1702                         clock.m2 = 8;
1703                 } else if (adjusted_mode->clock >= 140500
1704                                 && adjusted_mode->clock <= 200000) {
1705                         clock.p1 = 1;
1706                         clock.p2 = 10;
1707                         clock.n = 6;
1708                         clock.m1 = 12;
1709                         clock.m2 = 8;
1710                 }
1711         }
1712
1713         /* FDI link */
1714         if (IS_IGDNG(dev))
1715                 igdng_compute_m_n(3, 4, /* lane num 4 */
1716                                 adjusted_mode->clock,
1717                                 270000, /* lane clock */
1718                                 &m_n);
1719
1720         if (IS_IGD(dev))
1721                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1722         else
1723                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1724
1725         if (!IS_IGDNG(dev))
1726                 dpll = DPLL_VGA_MODE_DIS;
1727
1728         if (IS_I9XX(dev)) {
1729                 if (is_lvds)
1730                         dpll |= DPLLB_MODE_LVDS;
1731                 else
1732                         dpll |= DPLLB_MODE_DAC_SERIAL;
1733                 if (is_sdvo) {
1734                         dpll |= DPLL_DVO_HIGH_SPEED;
1735                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1736                         if (IS_I945G(dev) || IS_I945GM(dev))
1737                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1738                         else if (IS_IGDNG(dev))
1739                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1740                 }
1741                 if (is_dp)
1742                         dpll |= DPLL_DVO_HIGH_SPEED;
1743
1744                 /* compute bitmask from p1 value */
1745                 if (IS_IGD(dev))
1746                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1747                 else {
1748                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1749                         /* also FPA1 */
1750                         if (IS_IGDNG(dev))
1751                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1752                 }
1753                 switch (clock.p2) {
1754                 case 5:
1755                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1756                         break;
1757                 case 7:
1758                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1759                         break;
1760                 case 10:
1761                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1762                         break;
1763                 case 14:
1764                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1765                         break;
1766                 }
1767                 if (IS_I965G(dev) && !IS_IGDNG(dev))
1768                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1769         } else {
1770                 if (is_lvds) {
1771                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1772                 } else {
1773                         if (clock.p1 == 2)
1774                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
1775                         else
1776                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1777                         if (clock.p2 == 4)
1778                                 dpll |= PLL_P2_DIVIDE_BY_4;
1779                 }
1780         }
1781
1782         if (is_sdvo && is_tv)
1783                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1784         else if (is_tv)
1785                 /* XXX: just matching BIOS for now */
1786                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1787                 dpll |= 3;
1788         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
1789                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1790         else
1791                 dpll |= PLL_REF_INPUT_DREFCLK;
1792
1793         /* setup pipeconf */
1794         pipeconf = I915_READ(pipeconf_reg);
1795
1796         /* Set up the display plane register */
1797         dspcntr = DISPPLANE_GAMMA_ENABLE;
1798
1799         /* IGDNG's plane is forced to pipe, bit 24 is to
1800            enable color space conversion */
1801         if (!IS_IGDNG(dev)) {
1802                 if (pipe == 0)
1803                         dspcntr |= DISPPLANE_SEL_PIPE_A;
1804                 else
1805                         dspcntr |= DISPPLANE_SEL_PIPE_B;
1806         }
1807
1808         if (pipe == 0 && !IS_I965G(dev)) {
1809                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1810                  * core speed.
1811                  *
1812                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1813                  * pipe == 0 check?
1814                  */
1815                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
1816                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
1817                 else
1818                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
1819         }
1820
1821         dspcntr |= DISPLAY_PLANE_ENABLE;
1822         pipeconf |= PIPEACONF_ENABLE;
1823         dpll |= DPLL_VCO_ENABLE;
1824
1825
1826         /* Disable the panel fitter if it was on our pipe */
1827         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
1828                 I915_WRITE(PFIT_CONTROL, 0);
1829
1830         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1831         drm_mode_debug_printmodeline(mode);
1832
1833         /* assign to IGDNG registers */
1834         if (IS_IGDNG(dev)) {
1835                 fp_reg = pch_fp_reg;
1836                 dpll_reg = pch_dpll_reg;
1837         }
1838
1839         if (dpll & DPLL_VCO_ENABLE) {
1840                 I915_WRITE(fp_reg, fp);
1841                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1842                 I915_READ(dpll_reg);
1843                 udelay(150);
1844         }
1845
1846         if (IS_IGDNG(dev)) {
1847                 /* enable PCH clock reference source */
1848                 /* XXX need to change the setting for other outputs */
1849                 u32 temp;
1850                 temp = I915_READ(PCH_DREF_CONTROL);
1851                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
1852                 temp |= DREF_NONSPREAD_CK505_ENABLE;
1853                 temp &= ~DREF_SSC_SOURCE_MASK;
1854                 temp |= DREF_SSC_SOURCE_ENABLE;
1855                 temp &= ~DREF_SSC1_ENABLE;
1856                 /* if no eDP, disable source output to CPU */
1857                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
1858                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
1859                 I915_WRITE(PCH_DREF_CONTROL, temp);
1860         }
1861
1862         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1863          * This is an exception to the general rule that mode_set doesn't turn
1864          * things on.
1865          */
1866         if (is_lvds) {
1867                 u32 lvds;
1868
1869                 if (IS_IGDNG(dev))
1870                         lvds_reg = PCH_LVDS;
1871
1872                 lvds = I915_READ(lvds_reg);
1873                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1874                 /* Set the B0-B3 data pairs corresponding to whether we're going to
1875                  * set the DPLLs for dual-channel mode or not.
1876                  */
1877                 if (clock.p2 == 7)
1878                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1879                 else
1880                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1881
1882                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1883                  * appropriately here, but we need to look more thoroughly into how
1884                  * panels behave in the two modes.
1885                  */
1886
1887                 I915_WRITE(lvds_reg, lvds);
1888                 I915_READ(lvds_reg);
1889         }
1890         if (is_dp)
1891                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
1892
1893         I915_WRITE(fp_reg, fp);
1894         I915_WRITE(dpll_reg, dpll);
1895         I915_READ(dpll_reg);
1896         /* Wait for the clocks to stabilize. */
1897         udelay(150);
1898
1899         if (IS_I965G(dev) && !IS_IGDNG(dev)) {
1900                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1901                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1902                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1903         } else {
1904                 /* write it again -- the BIOS does, after all */
1905                 I915_WRITE(dpll_reg, dpll);
1906         }
1907         I915_READ(dpll_reg);
1908         /* Wait for the clocks to stabilize. */
1909         udelay(150);
1910
1911         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1912                    ((adjusted_mode->crtc_htotal - 1) << 16));
1913         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1914                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
1915         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1916                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
1917         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1918                    ((adjusted_mode->crtc_vtotal - 1) << 16));
1919         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1920                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
1921         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1922                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
1923         /* pipesrc and dspsize control the size that is scaled from, which should
1924          * always be the user's requested size.
1925          */
1926         if (!IS_IGDNG(dev)) {
1927                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
1928                                 (mode->hdisplay - 1));
1929                 I915_WRITE(dsppos_reg, 0);
1930         }
1931         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1932
1933         if (IS_IGDNG(dev)) {
1934                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
1935                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
1936                 I915_WRITE(link_m1_reg, m_n.link_m);
1937                 I915_WRITE(link_n1_reg, m_n.link_n);
1938
1939                  /* enable FDI RX PLL too */
1940                 temp = I915_READ(fdi_rx_reg);
1941                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1942                 udelay(200);
1943         }
1944
1945         I915_WRITE(pipeconf_reg, pipeconf);
1946         I915_READ(pipeconf_reg);
1947
1948         intel_wait_for_vblank(dev);
1949
1950         I915_WRITE(dspcntr_reg, dspcntr);
1951
1952         /* Flush the plane changes */
1953         ret = intel_pipe_set_base(crtc, x, y, old_fb);
1954         drm_vblank_post_modeset(dev, pipe);
1955
1956         return ret;
1957 }
1958
1959 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1960 void intel_crtc_load_lut(struct drm_crtc *crtc)
1961 {
1962         struct drm_device *dev = crtc->dev;
1963         struct drm_i915_private *dev_priv = dev->dev_private;
1964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
1966         int i;
1967
1968         /* The clocks have to be on to load the palette. */
1969         if (!crtc->enabled)
1970                 return;
1971
1972         /* use legacy palette for IGDNG */
1973         if (IS_IGDNG(dev))
1974                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
1975                                                    LGC_PALETTE_B;
1976
1977         for (i = 0; i < 256; i++) {
1978                 I915_WRITE(palreg + 4 * i,
1979                            (intel_crtc->lut_r[i] << 16) |
1980                            (intel_crtc->lut_g[i] << 8) |
1981                            intel_crtc->lut_b[i]);
1982         }
1983 }
1984
1985 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1986                                  struct drm_file *file_priv,
1987                                  uint32_t handle,
1988                                  uint32_t width, uint32_t height)
1989 {
1990         struct drm_device *dev = crtc->dev;
1991         struct drm_i915_private *dev_priv = dev->dev_private;
1992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1993         struct drm_gem_object *bo;
1994         struct drm_i915_gem_object *obj_priv;
1995         int pipe = intel_crtc->pipe;
1996         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1997         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1998         uint32_t temp = I915_READ(control);
1999         size_t addr;
2000         int ret;
2001
2002         DRM_DEBUG("\n");
2003
2004         /* if we want to turn off the cursor ignore width and height */
2005         if (!handle) {
2006                 DRM_DEBUG("cursor off\n");
2007                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2008                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2009                         temp |= CURSOR_MODE_DISABLE;
2010                 } else {
2011                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2012                 }
2013                 addr = 0;
2014                 bo = NULL;
2015                 mutex_lock(&dev->struct_mutex);
2016                 goto finish;
2017         }
2018
2019         /* Currently we only support 64x64 cursors */
2020         if (width != 64 || height != 64) {
2021                 DRM_ERROR("we currently only support 64x64 cursors\n");
2022                 return -EINVAL;
2023         }
2024
2025         bo = drm_gem_object_lookup(dev, file_priv, handle);
2026         if (!bo)
2027                 return -ENOENT;
2028
2029         obj_priv = bo->driver_private;
2030
2031         if (bo->size < width * height * 4) {
2032                 DRM_ERROR("buffer is to small\n");
2033                 ret = -ENOMEM;
2034                 goto fail;
2035         }
2036
2037         /* we only need to pin inside GTT if cursor is non-phy */
2038         mutex_lock(&dev->struct_mutex);
2039         if (!dev_priv->cursor_needs_physical) {
2040                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2041                 if (ret) {
2042                         DRM_ERROR("failed to pin cursor bo\n");
2043                         goto fail_locked;
2044                 }
2045                 addr = obj_priv->gtt_offset;
2046         } else {
2047                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2048                 if (ret) {
2049                         DRM_ERROR("failed to attach phys object\n");
2050                         goto fail_locked;
2051                 }
2052                 addr = obj_priv->phys_obj->handle->busaddr;
2053         }
2054
2055         if (!IS_I9XX(dev))
2056                 I915_WRITE(CURSIZE, (height << 12) | width);
2057
2058         /* Hooray for CUR*CNTR differences */
2059         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2060                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2061                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2062                 temp |= (pipe << 28); /* Connect to correct pipe */
2063         } else {
2064                 temp &= ~(CURSOR_FORMAT_MASK);
2065                 temp |= CURSOR_ENABLE;
2066                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2067         }
2068
2069  finish:
2070         I915_WRITE(control, temp);
2071         I915_WRITE(base, addr);
2072
2073         if (intel_crtc->cursor_bo) {
2074                 if (dev_priv->cursor_needs_physical) {
2075                         if (intel_crtc->cursor_bo != bo)
2076                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2077                 } else
2078                         i915_gem_object_unpin(intel_crtc->cursor_bo);
2079                 drm_gem_object_unreference(intel_crtc->cursor_bo);
2080         }
2081         mutex_unlock(&dev->struct_mutex);
2082
2083         intel_crtc->cursor_addr = addr;
2084         intel_crtc->cursor_bo = bo;
2085
2086         return 0;
2087 fail:
2088         mutex_lock(&dev->struct_mutex);
2089 fail_locked:
2090         drm_gem_object_unreference(bo);
2091         mutex_unlock(&dev->struct_mutex);
2092         return ret;
2093 }
2094
2095 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2096 {
2097         struct drm_device *dev = crtc->dev;
2098         struct drm_i915_private *dev_priv = dev->dev_private;
2099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2100         int pipe = intel_crtc->pipe;
2101         uint32_t temp = 0;
2102         uint32_t adder;
2103
2104         if (x < 0) {
2105                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2106                 x = -x;
2107         }
2108         if (y < 0) {
2109                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2110                 y = -y;
2111         }
2112
2113         temp |= x << CURSOR_X_SHIFT;
2114         temp |= y << CURSOR_Y_SHIFT;
2115
2116         adder = intel_crtc->cursor_addr;
2117         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2118         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2119
2120         return 0;
2121 }
2122
2123 /** Sets the color ramps on behalf of RandR */
2124 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2125                                  u16 blue, int regno)
2126 {
2127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2128
2129         intel_crtc->lut_r[regno] = red >> 8;
2130         intel_crtc->lut_g[regno] = green >> 8;
2131         intel_crtc->lut_b[regno] = blue >> 8;
2132 }
2133
2134 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2135                                  u16 *blue, uint32_t size)
2136 {
2137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2138         int i;
2139
2140         if (size != 256)
2141                 return;
2142
2143         for (i = 0; i < 256; i++) {
2144                 intel_crtc->lut_r[i] = red[i] >> 8;
2145                 intel_crtc->lut_g[i] = green[i] >> 8;
2146                 intel_crtc->lut_b[i] = blue[i] >> 8;
2147         }
2148
2149         intel_crtc_load_lut(crtc);
2150 }
2151
2152 /**
2153  * Get a pipe with a simple mode set on it for doing load-based monitor
2154  * detection.
2155  *
2156  * It will be up to the load-detect code to adjust the pipe as appropriate for
2157  * its requirements.  The pipe will be connected to no other outputs.
2158  *
2159  * Currently this code will only succeed if there is a pipe with no outputs
2160  * configured for it.  In the future, it could choose to temporarily disable
2161  * some outputs to free up a pipe for its use.
2162  *
2163  * \return crtc, or NULL if no pipes are available.
2164  */
2165
2166 /* VESA 640x480x72Hz mode to set on the pipe */
2167 static struct drm_display_mode load_detect_mode = {
2168         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2169                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2170 };
2171
2172 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2173                                             struct drm_display_mode *mode,
2174                                             int *dpms_mode)
2175 {
2176         struct intel_crtc *intel_crtc;
2177         struct drm_crtc *possible_crtc;
2178         struct drm_crtc *supported_crtc =NULL;
2179         struct drm_encoder *encoder = &intel_output->enc;
2180         struct drm_crtc *crtc = NULL;
2181         struct drm_device *dev = encoder->dev;
2182         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2183         struct drm_crtc_helper_funcs *crtc_funcs;
2184         int i = -1;
2185
2186         /*
2187          * Algorithm gets a little messy:
2188          *   - if the connector already has an assigned crtc, use it (but make
2189          *     sure it's on first)
2190          *   - try to find the first unused crtc that can drive this connector,
2191          *     and use that if we find one
2192          *   - if there are no unused crtcs available, try to use the first
2193          *     one we found that supports the connector
2194          */
2195
2196         /* See if we already have a CRTC for this connector */
2197         if (encoder->crtc) {
2198                 crtc = encoder->crtc;
2199                 /* Make sure the crtc and connector are running */
2200                 intel_crtc = to_intel_crtc(crtc);
2201                 *dpms_mode = intel_crtc->dpms_mode;
2202                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2203                         crtc_funcs = crtc->helper_private;
2204                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2205                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2206                 }
2207                 return crtc;
2208         }
2209
2210         /* Find an unused one (if possible) */
2211         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2212                 i++;
2213                 if (!(encoder->possible_crtcs & (1 << i)))
2214                         continue;
2215                 if (!possible_crtc->enabled) {
2216                         crtc = possible_crtc;
2217                         break;
2218                 }
2219                 if (!supported_crtc)
2220                         supported_crtc = possible_crtc;
2221         }
2222
2223         /*
2224          * If we didn't find an unused CRTC, don't use any.
2225          */
2226         if (!crtc) {
2227                 return NULL;
2228         }
2229
2230         encoder->crtc = crtc;
2231         intel_output->base.encoder = encoder;
2232         intel_output->load_detect_temp = true;
2233
2234         intel_crtc = to_intel_crtc(crtc);
2235         *dpms_mode = intel_crtc->dpms_mode;
2236
2237         if (!crtc->enabled) {
2238                 if (!mode)
2239                         mode = &load_detect_mode;
2240                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2241         } else {
2242                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2243                         crtc_funcs = crtc->helper_private;
2244                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2245                 }
2246
2247                 /* Add this connector to the crtc */
2248                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2249                 encoder_funcs->commit(encoder);
2250         }
2251         /* let the connector get through one full cycle before testing */
2252         intel_wait_for_vblank(dev);
2253
2254         return crtc;
2255 }
2256
2257 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2258 {
2259         struct drm_encoder *encoder = &intel_output->enc;
2260         struct drm_device *dev = encoder->dev;
2261         struct drm_crtc *crtc = encoder->crtc;
2262         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2263         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2264
2265         if (intel_output->load_detect_temp) {
2266                 encoder->crtc = NULL;
2267                 intel_output->base.encoder = NULL;
2268                 intel_output->load_detect_temp = false;
2269                 crtc->enabled = drm_helper_crtc_in_use(crtc);
2270                 drm_helper_disable_unused_functions(dev);
2271         }
2272
2273         /* Switch crtc and output back off if necessary */
2274         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2275                 if (encoder->crtc == crtc)
2276                         encoder_funcs->dpms(encoder, dpms_mode);
2277                 crtc_funcs->dpms(crtc, dpms_mode);
2278         }
2279 }
2280
2281 /* Returns the clock of the currently programmed mode of the given pipe. */
2282 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2283 {
2284         struct drm_i915_private *dev_priv = dev->dev_private;
2285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2286         int pipe = intel_crtc->pipe;
2287         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2288         u32 fp;
2289         intel_clock_t clock;
2290
2291         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2292                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2293         else
2294                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2295
2296         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2297         if (IS_IGD(dev)) {
2298                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2299                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2300         } else {
2301                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2302                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2303         }
2304
2305         if (IS_I9XX(dev)) {
2306                 if (IS_IGD(dev))
2307                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2308                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2309                 else
2310                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2311                                DPLL_FPA01_P1_POST_DIV_SHIFT);
2312
2313                 switch (dpll & DPLL_MODE_MASK) {
2314                 case DPLLB_MODE_DAC_SERIAL:
2315                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2316                                 5 : 10;
2317                         break;
2318                 case DPLLB_MODE_LVDS:
2319                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2320                                 7 : 14;
2321                         break;
2322                 default:
2323                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2324                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
2325                         return 0;
2326                 }
2327
2328                 /* XXX: Handle the 100Mhz refclk */
2329                 intel_clock(dev, 96000, &clock);
2330         } else {
2331                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2332
2333                 if (is_lvds) {
2334                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2335                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
2336                         clock.p2 = 14;
2337
2338                         if ((dpll & PLL_REF_INPUT_MASK) ==
2339                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2340                                 /* XXX: might not be 66MHz */
2341                                 intel_clock(dev, 66000, &clock);
2342                         } else
2343                                 intel_clock(dev, 48000, &clock);
2344                 } else {
2345                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
2346                                 clock.p1 = 2;
2347                         else {
2348                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2349                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2350                         }
2351                         if (dpll & PLL_P2_DIVIDE_BY_4)
2352                                 clock.p2 = 4;
2353                         else
2354                                 clock.p2 = 2;
2355
2356                         intel_clock(dev, 48000, &clock);
2357                 }
2358         }
2359
2360         /* XXX: It would be nice to validate the clocks, but we can't reuse
2361          * i830PllIsValid() because it relies on the xf86_config connector
2362          * configuration being accurate, which it isn't necessarily.
2363          */
2364
2365         return clock.dot;
2366 }
2367
2368 /** Returns the currently programmed mode of the given pipe. */
2369 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2370                                              struct drm_crtc *crtc)
2371 {
2372         struct drm_i915_private *dev_priv = dev->dev_private;
2373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2374         int pipe = intel_crtc->pipe;
2375         struct drm_display_mode *mode;
2376         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2377         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2378         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2379         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2380
2381         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2382         if (!mode)
2383                 return NULL;
2384
2385         mode->clock = intel_crtc_clock_get(dev, crtc);
2386         mode->hdisplay = (htot & 0xffff) + 1;
2387         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2388         mode->hsync_start = (hsync & 0xffff) + 1;
2389         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2390         mode->vdisplay = (vtot & 0xffff) + 1;
2391         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2392         mode->vsync_start = (vsync & 0xffff) + 1;
2393         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2394
2395         drm_mode_set_name(mode);
2396         drm_mode_set_crtcinfo(mode, 0);
2397
2398         return mode;
2399 }
2400
2401 static void intel_crtc_destroy(struct drm_crtc *crtc)
2402 {
2403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2404
2405         if (intel_crtc->mode_set.mode)
2406                 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
2407         drm_crtc_cleanup(crtc);
2408         kfree(intel_crtc);
2409 }
2410
2411 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2412         .dpms = intel_crtc_dpms,
2413         .mode_fixup = intel_crtc_mode_fixup,
2414         .mode_set = intel_crtc_mode_set,
2415         .mode_set_base = intel_pipe_set_base,
2416         .prepare = intel_crtc_prepare,
2417         .commit = intel_crtc_commit,
2418 };
2419
2420 static const struct drm_crtc_funcs intel_crtc_funcs = {
2421         .cursor_set = intel_crtc_cursor_set,
2422         .cursor_move = intel_crtc_cursor_move,
2423         .gamma_set = intel_crtc_gamma_set,
2424         .set_config = drm_crtc_helper_set_config,
2425         .destroy = intel_crtc_destroy,
2426 };
2427
2428
2429 static void intel_crtc_init(struct drm_device *dev, int pipe)
2430 {
2431         struct intel_crtc *intel_crtc;
2432         int i;
2433
2434         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2435         if (intel_crtc == NULL)
2436                 return;
2437
2438         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2439
2440         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2441         intel_crtc->pipe = pipe;
2442         for (i = 0; i < 256; i++) {
2443                 intel_crtc->lut_r[i] = i;
2444                 intel_crtc->lut_g[i] = i;
2445                 intel_crtc->lut_b[i] = i;
2446         }
2447
2448         intel_crtc->cursor_addr = 0;
2449         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2450         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2451
2452         intel_crtc->mode_set.crtc = &intel_crtc->base;
2453         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2454         intel_crtc->mode_set.num_connectors = 0;
2455
2456         if (i915_fbpercrtc) {
2457
2458
2459
2460         }
2461 }
2462
2463 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2464                                 struct drm_file *file_priv)
2465 {
2466         drm_i915_private_t *dev_priv = dev->dev_private;
2467         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2468         struct drm_crtc *crtc = NULL;
2469         int pipe = -1;
2470
2471         if (!dev_priv) {
2472                 DRM_ERROR("called with no initialization\n");
2473                 return -EINVAL;
2474         }
2475
2476         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2477                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2478                 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2479                         pipe = intel_crtc->pipe;
2480                         break;
2481                 }
2482         }
2483
2484         if (pipe == -1) {
2485                 DRM_ERROR("no such CRTC id\n");
2486                 return -EINVAL;
2487         }
2488
2489         pipe_from_crtc_id->pipe = pipe;
2490
2491        return 0;
2492 }
2493
2494 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
2495 {
2496         struct drm_crtc *crtc = NULL;
2497
2498         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2499                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500                 if (intel_crtc->pipe == pipe)
2501                         break;
2502         }
2503         return crtc;
2504 }
2505
2506 static int intel_connector_clones(struct drm_device *dev, int type_mask)
2507 {
2508         int index_mask = 0;
2509         struct drm_connector *connector;
2510         int entry = 0;
2511
2512         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2513                 struct intel_output *intel_output = to_intel_output(connector);
2514                 if (type_mask & (1 << intel_output->type))
2515                         index_mask |= (1 << entry);
2516                 entry++;
2517         }
2518         return index_mask;
2519 }
2520
2521
2522 static void intel_setup_outputs(struct drm_device *dev)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         struct drm_connector *connector;
2526
2527         intel_crt_init(dev);
2528
2529         /* Set up integrated LVDS */
2530         if (IS_MOBILE(dev) && !IS_I830(dev))
2531                 intel_lvds_init(dev);
2532
2533         if (IS_IGDNG(dev)) {
2534                 int found;
2535
2536                 if (I915_READ(HDMIB) & PORT_DETECTED) {
2537                         /* check SDVOB */
2538                         /* found = intel_sdvo_init(dev, HDMIB); */
2539                         found = 0;
2540                         if (!found)
2541                                 intel_hdmi_init(dev, HDMIB);
2542                 }
2543
2544                 if (I915_READ(HDMIC) & PORT_DETECTED)
2545                         intel_hdmi_init(dev, HDMIC);
2546
2547                 if (I915_READ(HDMID) & PORT_DETECTED)
2548                         intel_hdmi_init(dev, HDMID);
2549
2550         } else if (IS_I9XX(dev)) {
2551                 int found;
2552                 u32 reg;
2553
2554                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
2555                         found = intel_sdvo_init(dev, SDVOB);
2556                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2557                                 intel_hdmi_init(dev, SDVOB);
2558                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
2559                                 intel_dp_init(dev, DP_B);
2560                 }
2561
2562                 /* Before G4X SDVOC doesn't have its own detect register */
2563                 if (IS_G4X(dev))
2564                         reg = SDVOC;
2565                 else
2566                         reg = SDVOB;
2567
2568                 if (I915_READ(reg) & SDVO_DETECTED) {
2569                         found = intel_sdvo_init(dev, SDVOC);
2570                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2571                                 intel_hdmi_init(dev, SDVOC);
2572                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
2573                                 intel_dp_init(dev, DP_C);
2574                 }
2575                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
2576                         intel_dp_init(dev, DP_D);
2577         } else
2578                 intel_dvo_init(dev);
2579
2580         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
2581                 intel_tv_init(dev);
2582
2583         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2584                 struct intel_output *intel_output = to_intel_output(connector);
2585                 struct drm_encoder *encoder = &intel_output->enc;
2586                 int crtc_mask = 0, clone_mask = 0;
2587
2588                 /* valid crtcs */
2589                 switch(intel_output->type) {
2590                 case INTEL_OUTPUT_HDMI:
2591                         crtc_mask = ((1 << 0)|
2592                                      (1 << 1));
2593                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
2594                         break;
2595                 case INTEL_OUTPUT_DVO:
2596                 case INTEL_OUTPUT_SDVO:
2597                         crtc_mask = ((1 << 0)|
2598                                      (1 << 1));
2599                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
2600                                       (1 << INTEL_OUTPUT_DVO) |
2601                                       (1 << INTEL_OUTPUT_SDVO));
2602                         break;
2603                 case INTEL_OUTPUT_ANALOG:
2604                         crtc_mask = ((1 << 0)|
2605                                      (1 << 1));
2606                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
2607                                       (1 << INTEL_OUTPUT_DVO) |
2608                                       (1 << INTEL_OUTPUT_SDVO));
2609                         break;
2610                 case INTEL_OUTPUT_LVDS:
2611                         crtc_mask = (1 << 1);
2612                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
2613                         break;
2614                 case INTEL_OUTPUT_TVOUT:
2615                         crtc_mask = ((1 << 0) |
2616                                      (1 << 1));
2617                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
2618                         break;
2619                 case INTEL_OUTPUT_DISPLAYPORT:
2620                         crtc_mask = ((1 << 0) |
2621                                      (1 << 1));
2622                         clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
2623                         break;
2624                 }
2625                 encoder->possible_crtcs = crtc_mask;
2626                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
2627         }
2628 }
2629
2630 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
2631 {
2632         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2633         struct drm_device *dev = fb->dev;
2634
2635         if (fb->fbdev)
2636                 intelfb_remove(dev, fb);
2637
2638         drm_framebuffer_cleanup(fb);
2639         mutex_lock(&dev->struct_mutex);
2640         drm_gem_object_unreference(intel_fb->obj);
2641         mutex_unlock(&dev->struct_mutex);
2642
2643         kfree(intel_fb);
2644 }
2645
2646 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
2647                                                 struct drm_file *file_priv,
2648                                                 unsigned int *handle)
2649 {
2650         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2651         struct drm_gem_object *object = intel_fb->obj;
2652
2653         return drm_gem_handle_create(file_priv, object, handle);
2654 }
2655
2656 static const struct drm_framebuffer_funcs intel_fb_funcs = {
2657         .destroy = intel_user_framebuffer_destroy,
2658         .create_handle = intel_user_framebuffer_create_handle,
2659 };
2660
2661 int intel_framebuffer_create(struct drm_device *dev,
2662                              struct drm_mode_fb_cmd *mode_cmd,
2663                              struct drm_framebuffer **fb,
2664                              struct drm_gem_object *obj)
2665 {
2666         struct intel_framebuffer *intel_fb;
2667         int ret;
2668
2669         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2670         if (!intel_fb)
2671                 return -ENOMEM;
2672
2673         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
2674         if (ret) {
2675                 DRM_ERROR("framebuffer init failed %d\n", ret);
2676                 return ret;
2677         }
2678
2679         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
2680
2681         intel_fb->obj = obj;
2682
2683         *fb = &intel_fb->base;
2684
2685         return 0;
2686 }
2687
2688
2689 static struct drm_framebuffer *
2690 intel_user_framebuffer_create(struct drm_device *dev,
2691                               struct drm_file *filp,
2692                               struct drm_mode_fb_cmd *mode_cmd)
2693 {
2694         struct drm_gem_object *obj;
2695         struct drm_framebuffer *fb;
2696         int ret;
2697
2698         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
2699         if (!obj)
2700                 return NULL;
2701
2702         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
2703         if (ret) {
2704                 mutex_lock(&dev->struct_mutex);
2705                 drm_gem_object_unreference(obj);
2706                 mutex_unlock(&dev->struct_mutex);
2707                 return NULL;
2708         }
2709
2710         return fb;
2711 }
2712
2713 static const struct drm_mode_config_funcs intel_mode_funcs = {
2714         .fb_create = intel_user_framebuffer_create,
2715         .fb_changed = intelfb_probe,
2716 };
2717
2718 void intel_modeset_init(struct drm_device *dev)
2719 {
2720         int num_pipe;
2721         int i;
2722
2723         drm_mode_config_init(dev);
2724
2725         dev->mode_config.min_width = 0;
2726         dev->mode_config.min_height = 0;
2727
2728         dev->mode_config.funcs = (void *)&intel_mode_funcs;
2729
2730         if (IS_I965G(dev)) {
2731                 dev->mode_config.max_width = 8192;
2732                 dev->mode_config.max_height = 8192;
2733         } else {
2734                 dev->mode_config.max_width = 2048;
2735                 dev->mode_config.max_height = 2048;
2736         }
2737
2738         /* set memory base */
2739         if (IS_I9XX(dev))
2740                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
2741         else
2742                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
2743
2744         if (IS_MOBILE(dev) || IS_I9XX(dev))
2745                 num_pipe = 2;
2746         else
2747                 num_pipe = 1;
2748         DRM_DEBUG("%d display pipe%s available.\n",
2749                   num_pipe, num_pipe > 1 ? "s" : "");
2750
2751         for (i = 0; i < num_pipe; i++) {
2752                 intel_crtc_init(dev, i);
2753         }
2754
2755         intel_setup_outputs(dev);
2756 }
2757
2758 void intel_modeset_cleanup(struct drm_device *dev)
2759 {
2760         drm_mode_config_cleanup(dev);
2761 }
2762
2763
2764 /* current intel driver doesn't take advantage of encoders
2765    always give back the encoder for the connector
2766 */
2767 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
2768 {
2769         struct intel_output *intel_output = to_intel_output(connector);
2770
2771         return &intel_output->enc;
2772 }