2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
119 .find_pll = intel_find_best_PLL,
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
133 .find_pll = intel_find_best_PLL,
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
147 .find_pll = intel_find_best_PLL,
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
161 .find_pll = intel_find_best_PLL,
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
178 .find_pll = intel_g4x_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
192 .find_pll = intel_g4x_find_best_PLL,
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
207 .find_pll = intel_g4x_find_best_PLL,
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
222 .find_pll = intel_g4x_find_best_PLL,
225 static const intel_limit_t intel_limits_g4x_display_port = {
226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
235 .p2_slow = 10, .p2_fast = 10 },
236 .find_pll = intel_find_pll_g4x_dp,
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
242 /* Pineview's Ncounter is a ring counter */
243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
245 /* Pineview only has one combined m divider, which we treat as m2. */
246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 .find_pll = intel_find_best_PLL,
255 static const intel_limit_t intel_limits_pineview_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
266 .find_pll = intel_find_best_PLL,
269 /* Ironlake / Sandybridge
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
274 static const intel_limit_t intel_limits_ironlake_dac = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
285 .find_pll = intel_g4x_find_best_PLL,
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
299 .find_pll = intel_g4x_find_best_PLL,
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 .find_pll = intel_g4x_find_best_PLL,
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 .find_pll = intel_g4x_find_best_PLL,
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
339 .p1 = { .min = 2, .max = 6 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 .find_pll = intel_g4x_find_best_PLL,
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 10, .p2_fast = 10 },
356 .find_pll = intel_find_pll_ironlake_dp,
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 const intel_limit_t *limit;
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
370 if (refclk == 100000)
371 limit = &intel_limits_ironlake_dual_lvds_100m;
373 limit = &intel_limits_ironlake_dual_lvds;
375 if (refclk == 100000)
376 limit = &intel_limits_ironlake_single_lvds_100m;
378 limit = &intel_limits_ironlake_single_lvds;
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
382 limit = &intel_limits_ironlake_display_port;
384 limit = &intel_limits_ironlake_dac;
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
398 /* LVDS with dual channel */
399 limit = &intel_limits_g4x_dual_channel_lvds;
401 /* LVDS with dual channel */
402 limit = &intel_limits_g4x_single_channel_lvds;
403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405 limit = &intel_limits_g4x_hdmi;
406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407 limit = &intel_limits_g4x_sdvo;
408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409 limit = &intel_limits_g4x_display_port;
410 } else /* The option is for other outputs */
411 limit = &intel_limits_i9xx_sdvo;
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
421 if (HAS_PCH_SPLIT(dev))
422 limit = intel_ironlake_limit(crtc, refclk);
423 else if (IS_G4X(dev)) {
424 limit = intel_g4x_limit(crtc);
425 } else if (IS_PINEVIEW(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_pineview_lvds;
429 limit = &intel_limits_pineview_sdvo;
430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
434 limit = &intel_limits_i9xx_sdvo;
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437 limit = &intel_limits_i8xx_lvds;
439 limit = &intel_limits_i8xx_dvo;
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
466 * Returns whether any output on the specified pipe is of the specified type
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
481 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
492 INTELPllInvalid("p1 out of range\n");
493 if (clock->p < limit->p.min || limit->p.max < clock->p)
494 INTELPllInvalid("p out of range\n");
495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
496 INTELPllInvalid("m2 out of range\n");
497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
498 INTELPllInvalid("m1 out of range\n");
499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500 INTELPllInvalid("m1 <= m2\n");
501 if (clock->m < limit->m.min || limit->m.max < clock->m)
502 INTELPllInvalid("m out of range\n");
503 if (clock->n < limit->n.min || limit->n.max < clock->n)
504 INTELPllInvalid("n out of range\n");
505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506 INTELPllInvalid("vco out of range\n");
507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511 INTELPllInvalid("dot out of range\n");
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527 (I915_READ(LVDS)) != 0) {
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
536 clock.p2 = limit->p2.p2_fast;
538 clock.p2 = limit->p2.p2_slow;
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
543 clock.p2 = limit->p2.p2_fast;
546 memset(best_clock, 0, sizeof(*best_clock));
548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
561 intel_clock(dev, refclk, &clock);
562 if (!intel_PLL_is_valid(dev, limit,
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
576 return (err != target);
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
595 if (HAS_PCH_SPLIT(dev))
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
601 clock.p2 = limit->p2.p2_fast;
603 clock.p2 = limit->p2.p2_slow;
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
608 clock.p2 = limit->p2.p2_fast;
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
613 /* based on hardware requirement, prefer smaller n to precision */
614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615 /* based on hardware requirement, prefere larger m1,m2 */
616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
624 intel_clock(dev, refclk, &clock);
625 if (!intel_PLL_is_valid(dev, limit,
629 this_err = abs(clock.dot - target);
630 if (this_err < err_most) {
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
647 struct drm_device *dev = crtc->dev;
650 if (target < 200000) {
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
674 if (target < 200000) {
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
696 * intel_wait_for_vblank - wait for vblank on a given pipe
698 * @pipe: pipe to wait for
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 int pipestat_reg = PIPESTAT(pipe);
708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
724 /* Wait for vblank interrupt bit to set */
725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
728 DRM_DEBUG_KMS("vblank wait timed out\n");
732 * intel_wait_for_pipe_off - wait for pipe to turn off
734 * @pipe: pipe to wait for
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
741 * wait for the pipe register state bit to turn off
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
750 struct drm_i915_private *dev_priv = dev->dev_private;
752 if (INTEL_INFO(dev)->gen >= 4) {
753 int reg = PIPECONF(pipe);
755 /* Wait for the Pipe State to go off */
756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
761 int reg = PIPEDSL(pipe);
762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
764 /* Wait for the display line to settle */
766 last_line = I915_READ(reg) & DSL_LINEMASK;
768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
775 static const char *state_string(bool enabled)
777 return enabled ? "on" : "off";
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
806 if (HAS_PCH_CPT(dev_priv->dev)) {
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
892 int pp_reg, lvds_reg;
894 enum pipe panel_pipe = PIPE_A;
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
918 void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
930 pipe_name(pipe), state_string(state), state_string(cur_state));
933 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
939 reg = DSPCNTR(plane);
940 val = I915_READ(reg);
941 WARN(!(val & DISPLAY_PLANE_ENABLE),
942 "plane %c assertion failure, should be active but is disabled\n",
946 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
953 /* Planes are fixed to pipes on ILK+ */
954 if (HAS_PCH_SPLIT(dev_priv->dev))
957 /* Need to check both planes against the pipe */
958 for (i = 0; i < 2; i++) {
960 val = I915_READ(reg);
961 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
962 DISPPLANE_SEL_PIPE_SHIFT;
963 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
964 "plane %c assertion failure, should be off on pipe %c but is still active\n",
965 plane_name(i), pipe_name(pipe));
969 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
974 val = I915_READ(PCH_DREF_CONTROL);
975 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
976 DREF_SUPERSPREAD_SOURCE_MASK));
977 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
980 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
987 reg = TRANSCONF(pipe);
988 val = I915_READ(reg);
989 enabled = !!(val & TRANS_ENABLE);
991 "transcoder assertion failed, should be off on pipe %c but is still active\n",
995 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
996 enum pipe pipe, u32 port_sel, u32 val)
998 if ((val & DP_PORT_EN) == 0)
1001 if (HAS_PCH_CPT(dev_priv->dev)) {
1002 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1003 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1004 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007 if ((val & DP_PIPE_MASK) != (pipe << 30))
1013 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1014 enum pipe pipe, u32 val)
1016 if ((val & PORT_ENABLE) == 0)
1019 if (HAS_PCH_CPT(dev_priv->dev)) {
1020 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1029 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1030 enum pipe pipe, u32 val)
1032 if ((val & LVDS_PORT_EN) == 0)
1035 if (HAS_PCH_CPT(dev_priv->dev)) {
1036 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1045 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, u32 val)
1048 if ((val & ADPA_DAC_ENABLE) == 0)
1050 if (HAS_PCH_CPT(dev_priv->dev)) {
1051 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1060 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, int reg, u32 port_sel)
1063 u32 val = I915_READ(reg);
1064 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1065 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1066 reg, pipe_name(pipe));
1069 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1070 enum pipe pipe, int reg)
1072 u32 val = I915_READ(reg);
1073 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1074 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1075 reg, pipe_name(pipe));
1078 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1084 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1085 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1089 val = I915_READ(reg);
1090 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1091 "PCH VGA enabled on transcoder %c, should be disabled\n",
1095 val = I915_READ(reg);
1096 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1097 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1100 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1101 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1106 * intel_enable_pll - enable a PLL
1107 * @dev_priv: i915 private structure
1108 * @pipe: pipe PLL to enable
1110 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1111 * make sure the PLL reg is writable first though, since the panel write
1112 * protect mechanism may be enabled.
1114 * Note! This is for pre-ILK only.
1116 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1121 /* No really, not for ILK+ */
1122 BUG_ON(dev_priv->info->gen >= 5);
1124 /* PLL is protected by panel, make sure we can write it */
1125 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1126 assert_panel_unlocked(dev_priv, pipe);
1129 val = I915_READ(reg);
1130 val |= DPLL_VCO_ENABLE;
1132 /* We do this three times for luck */
1133 I915_WRITE(reg, val);
1135 udelay(150); /* wait for warmup */
1136 I915_WRITE(reg, val);
1138 udelay(150); /* wait for warmup */
1139 I915_WRITE(reg, val);
1141 udelay(150); /* wait for warmup */
1145 * intel_disable_pll - disable a PLL
1146 * @dev_priv: i915 private structure
1147 * @pipe: pipe PLL to disable
1149 * Disable the PLL for @pipe, making sure the pipe is off first.
1151 * Note! This is for pre-ILK only.
1153 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1158 /* Don't disable pipe A or pipe A PLLs if needed */
1159 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162 /* Make sure the pipe isn't still relying on us */
1163 assert_pipe_disabled(dev_priv, pipe);
1166 val = I915_READ(reg);
1167 val &= ~DPLL_VCO_ENABLE;
1168 I915_WRITE(reg, val);
1173 * intel_enable_pch_pll - enable PCH PLL
1174 * @dev_priv: i915 private structure
1175 * @pipe: pipe PLL to enable
1177 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1178 * drives the transcoder clock.
1180 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1189 /* PCH only available on ILK+ */
1190 BUG_ON(dev_priv->info->gen < 5);
1192 /* PCH refclock must be enabled first */
1193 assert_pch_refclk_enabled(dev_priv);
1195 reg = PCH_DPLL(pipe);
1196 val = I915_READ(reg);
1197 val |= DPLL_VCO_ENABLE;
1198 I915_WRITE(reg, val);
1203 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1207 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1208 pll_sel = TRANSC_DPLL_ENABLE;
1213 /* PCH only available on ILK+ */
1214 BUG_ON(dev_priv->info->gen < 5);
1216 /* Make sure transcoder isn't still depending on us */
1217 assert_transcoder_disabled(dev_priv, pipe);
1220 pll_sel |= TRANSC_DPLLA_SEL;
1222 pll_sel |= TRANSC_DPLLB_SEL;
1225 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1228 reg = PCH_DPLL(pipe);
1229 val = I915_READ(reg);
1230 val &= ~DPLL_VCO_ENABLE;
1231 I915_WRITE(reg, val);
1236 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1245 /* Make sure PCH DPLL is enabled */
1246 assert_pch_pll_enabled(dev_priv, pipe);
1248 /* FDI must be feeding us bits for PCH ports */
1249 assert_fdi_tx_enabled(dev_priv, pipe);
1250 assert_fdi_rx_enabled(dev_priv, pipe);
1252 reg = TRANSCONF(pipe);
1253 val = I915_READ(reg);
1255 if (HAS_PCH_IBX(dev_priv->dev)) {
1257 * make the BPC in transcoder be consistent with
1258 * that in pipeconf reg.
1260 val &= ~PIPE_BPC_MASK;
1261 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1263 I915_WRITE(reg, val | TRANS_ENABLE);
1264 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1265 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1268 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1274 /* FDI relies on the transcoder */
1275 assert_fdi_tx_disabled(dev_priv, pipe);
1276 assert_fdi_rx_disabled(dev_priv, pipe);
1278 /* Ports must be off as well */
1279 assert_pch_ports_disabled(dev_priv, pipe);
1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
1283 val &= ~TRANS_ENABLE;
1284 I915_WRITE(reg, val);
1285 /* wait for PCH transcoder off, transcoder state */
1286 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1287 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1291 * intel_enable_pipe - enable a pipe, asserting requirements
1292 * @dev_priv: i915 private structure
1293 * @pipe: pipe to enable
1294 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1296 * Enable @pipe, making sure that various hardware specific requirements
1297 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1299 * @pipe should be %PIPE_A or %PIPE_B.
1301 * Will wait until the pipe is actually running (i.e. first vblank) before
1304 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1311 * A pipe without a PLL won't actually be able to drive bits from
1312 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1315 if (!HAS_PCH_SPLIT(dev_priv->dev))
1316 assert_pll_enabled(dev_priv, pipe);
1319 /* if driving the PCH, we need FDI enabled */
1320 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1321 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1323 /* FIXME: assert CPU port conditions for SNB+ */
1326 reg = PIPECONF(pipe);
1327 val = I915_READ(reg);
1328 if (val & PIPECONF_ENABLE)
1331 I915_WRITE(reg, val | PIPECONF_ENABLE);
1332 intel_wait_for_vblank(dev_priv->dev, pipe);
1336 * intel_disable_pipe - disable a pipe, asserting requirements
1337 * @dev_priv: i915 private structure
1338 * @pipe: pipe to disable
1340 * Disable @pipe, making sure that various hardware specific requirements
1341 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1343 * @pipe should be %PIPE_A or %PIPE_B.
1345 * Will wait until the pipe has shut down before returning.
1347 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1354 * Make sure planes won't keep trying to pump pixels to us,
1355 * or we might hang the display.
1357 assert_planes_disabled(dev_priv, pipe);
1359 /* Don't disable pipe A or pipe A PLLs if needed */
1360 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 reg = PIPECONF(pipe);
1364 val = I915_READ(reg);
1365 if ((val & PIPECONF_ENABLE) == 0)
1368 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1369 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1373 * Plane regs are double buffered, going from enabled->disabled needs a
1374 * trigger in order to latch. The display address reg provides this.
1376 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1379 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1380 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1384 * intel_enable_plane - enable a display plane on a given pipe
1385 * @dev_priv: i915 private structure
1386 * @plane: plane to enable
1387 * @pipe: pipe being fed
1389 * Enable @plane on @pipe, making sure that @pipe is running first.
1391 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1392 enum plane plane, enum pipe pipe)
1397 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1398 assert_pipe_enabled(dev_priv, pipe);
1400 reg = DSPCNTR(plane);
1401 val = I915_READ(reg);
1402 if (val & DISPLAY_PLANE_ENABLE)
1405 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1406 intel_flush_display_plane(dev_priv, plane);
1407 intel_wait_for_vblank(dev_priv->dev, pipe);
1411 * intel_disable_plane - disable a display plane
1412 * @dev_priv: i915 private structure
1413 * @plane: plane to disable
1414 * @pipe: pipe consuming the data
1416 * Disable @plane; should be an independent operation.
1418 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1419 enum plane plane, enum pipe pipe)
1424 reg = DSPCNTR(plane);
1425 val = I915_READ(reg);
1426 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1429 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1430 intel_flush_display_plane(dev_priv, plane);
1431 intel_wait_for_vblank(dev_priv->dev, pipe);
1434 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1435 enum pipe pipe, int reg, u32 port_sel)
1437 u32 val = I915_READ(reg);
1438 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1439 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1440 I915_WRITE(reg, val & ~DP_PORT_EN);
1444 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, int reg)
1447 u32 val = I915_READ(reg);
1448 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1449 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1451 I915_WRITE(reg, val & ~PORT_ENABLE);
1455 /* Disable any ports connected to this transcoder */
1456 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1461 val = I915_READ(PCH_PP_CONTROL);
1462 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1464 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1465 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1466 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469 val = I915_READ(reg);
1470 if (adpa_pipe_enabled(dev_priv, val, pipe))
1471 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1474 val = I915_READ(reg);
1475 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1476 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1477 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1482 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1483 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1484 disable_pch_hdmi(dev_priv, pipe, HDMID);
1487 static void i8xx_disable_fbc(struct drm_device *dev)
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1492 /* Disable compression */
1493 fbc_ctl = I915_READ(FBC_CONTROL);
1494 if ((fbc_ctl & FBC_CTL_EN) == 0)
1497 fbc_ctl &= ~FBC_CTL_EN;
1498 I915_WRITE(FBC_CONTROL, fbc_ctl);
1500 /* Wait for compressing bit to clear */
1501 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1502 DRM_DEBUG_KMS("FBC idle timed out\n");
1506 DRM_DEBUG_KMS("disabled FBC\n");
1509 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1511 struct drm_device *dev = crtc->dev;
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1513 struct drm_framebuffer *fb = crtc->fb;
1514 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1515 struct drm_i915_gem_object *obj = intel_fb->obj;
1516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519 u32 fbc_ctl, fbc_ctl2;
1521 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1522 if (fb->pitches[0] < cfb_pitch)
1523 cfb_pitch = fb->pitches[0];
1525 /* FBC_CTL wants 64B units */
1526 cfb_pitch = (cfb_pitch / 64) - 1;
1527 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1529 /* Clear old tags */
1530 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1531 I915_WRITE(FBC_TAG + (i * 4), 0);
1534 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1536 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1537 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1540 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1542 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1543 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1544 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1545 fbc_ctl |= obj->fence_reg;
1546 I915_WRITE(FBC_CONTROL, fbc_ctl);
1548 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1549 cfb_pitch, crtc->y, intel_crtc->plane);
1552 static bool i8xx_fbc_enabled(struct drm_device *dev)
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1556 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1559 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1561 struct drm_device *dev = crtc->dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 struct drm_framebuffer *fb = crtc->fb;
1564 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1565 struct drm_i915_gem_object *obj = intel_fb->obj;
1566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1567 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1568 unsigned long stall_watermark = 200;
1571 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1572 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1573 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1575 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1576 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1577 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1578 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1581 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1583 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1586 static void g4x_disable_fbc(struct drm_device *dev)
1588 struct drm_i915_private *dev_priv = dev->dev_private;
1591 /* Disable compression */
1592 dpfc_ctl = I915_READ(DPFC_CONTROL);
1593 if (dpfc_ctl & DPFC_CTL_EN) {
1594 dpfc_ctl &= ~DPFC_CTL_EN;
1595 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1597 DRM_DEBUG_KMS("disabled FBC\n");
1601 static bool g4x_fbc_enabled(struct drm_device *dev)
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1605 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1608 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1613 /* Make sure blitter notifies FBC of writes */
1614 gen6_gt_force_wake_get(dev_priv);
1615 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1616 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1617 GEN6_BLITTER_LOCK_SHIFT;
1618 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1619 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1620 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1621 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1622 GEN6_BLITTER_LOCK_SHIFT);
1623 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1624 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1625 gen6_gt_force_wake_put(dev_priv);
1628 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1630 struct drm_device *dev = crtc->dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 struct drm_framebuffer *fb = crtc->fb;
1633 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1634 struct drm_i915_gem_object *obj = intel_fb->obj;
1635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1636 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1637 unsigned long stall_watermark = 200;
1640 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1641 dpfc_ctl &= DPFC_RESERVED;
1642 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1643 /* Set persistent mode for front-buffer rendering, ala X. */
1644 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1645 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1646 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1648 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1649 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1650 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1651 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1652 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1654 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1657 I915_WRITE(SNB_DPFC_CTL_SA,
1658 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1659 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1660 sandybridge_blit_fbc_update(dev);
1663 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1666 static void ironlake_disable_fbc(struct drm_device *dev)
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1671 /* Disable compression */
1672 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1673 if (dpfc_ctl & DPFC_CTL_EN) {
1674 dpfc_ctl &= ~DPFC_CTL_EN;
1675 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1677 DRM_DEBUG_KMS("disabled FBC\n");
1681 static bool ironlake_fbc_enabled(struct drm_device *dev)
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1685 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1688 bool intel_fbc_enabled(struct drm_device *dev)
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1692 if (!dev_priv->display.fbc_enabled)
1695 return dev_priv->display.fbc_enabled(dev);
1698 static void intel_fbc_work_fn(struct work_struct *__work)
1700 struct intel_fbc_work *work =
1701 container_of(to_delayed_work(__work),
1702 struct intel_fbc_work, work);
1703 struct drm_device *dev = work->crtc->dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1706 mutex_lock(&dev->struct_mutex);
1707 if (work == dev_priv->fbc_work) {
1708 /* Double check that we haven't switched fb without cancelling
1711 if (work->crtc->fb == work->fb) {
1712 dev_priv->display.enable_fbc(work->crtc,
1715 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1716 dev_priv->cfb_fb = work->crtc->fb->base.id;
1717 dev_priv->cfb_y = work->crtc->y;
1720 dev_priv->fbc_work = NULL;
1722 mutex_unlock(&dev->struct_mutex);
1727 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1729 if (dev_priv->fbc_work == NULL)
1732 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1734 /* Synchronisation is provided by struct_mutex and checking of
1735 * dev_priv->fbc_work, so we can perform the cancellation
1736 * entirely asynchronously.
1738 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1739 /* tasklet was killed before being run, clean up */
1740 kfree(dev_priv->fbc_work);
1742 /* Mark the work as no longer wanted so that if it does
1743 * wake-up (because the work was already running and waiting
1744 * for our mutex), it will discover that is no longer
1747 dev_priv->fbc_work = NULL;
1750 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1752 struct intel_fbc_work *work;
1753 struct drm_device *dev = crtc->dev;
1754 struct drm_i915_private *dev_priv = dev->dev_private;
1756 if (!dev_priv->display.enable_fbc)
1759 intel_cancel_fbc_work(dev_priv);
1761 work = kzalloc(sizeof *work, GFP_KERNEL);
1763 dev_priv->display.enable_fbc(crtc, interval);
1768 work->fb = crtc->fb;
1769 work->interval = interval;
1770 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1772 dev_priv->fbc_work = work;
1774 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1776 /* Delay the actual enabling to let pageflipping cease and the
1777 * display to settle before starting the compression. Note that
1778 * this delay also serves a second purpose: it allows for a
1779 * vblank to pass after disabling the FBC before we attempt
1780 * to modify the control registers.
1782 * A more complicated solution would involve tracking vblanks
1783 * following the termination of the page-flipping sequence
1784 * and indeed performing the enable as a co-routine and not
1785 * waiting synchronously upon the vblank.
1787 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1790 void intel_disable_fbc(struct drm_device *dev)
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1794 intel_cancel_fbc_work(dev_priv);
1796 if (!dev_priv->display.disable_fbc)
1799 dev_priv->display.disable_fbc(dev);
1800 dev_priv->cfb_plane = -1;
1804 * intel_update_fbc - enable/disable FBC as needed
1805 * @dev: the drm_device
1807 * Set up the framebuffer compression hardware at mode set time. We
1808 * enable it if possible:
1809 * - plane A only (on pre-965)
1810 * - no pixel mulitply/line duplication
1811 * - no alpha buffer discard
1813 * - framebuffer <= 2048 in width, 1536 in height
1815 * We can't assume that any compression will take place (worst case),
1816 * so the compressed buffer has to be the same size as the uncompressed
1817 * one. It also must reside (along with the line length buffer) in
1820 * We need to enable/disable FBC on a global basis.
1822 static void intel_update_fbc(struct drm_device *dev)
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 struct drm_crtc *crtc = NULL, *tmp_crtc;
1826 struct intel_crtc *intel_crtc;
1827 struct drm_framebuffer *fb;
1828 struct intel_framebuffer *intel_fb;
1829 struct drm_i915_gem_object *obj;
1832 DRM_DEBUG_KMS("\n");
1834 if (!i915_powersave)
1837 if (!I915_HAS_FBC(dev))
1841 * If FBC is already on, we just have to verify that we can
1842 * keep it that way...
1843 * Need to disable if:
1844 * - more than one pipe is active
1845 * - changing FBC params (stride, fence, mode)
1846 * - new fb is too large to fit in compressed buffer
1847 * - going to an unsupported config (interlace, pixel multiply, etc.)
1849 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1850 if (tmp_crtc->enabled && tmp_crtc->fb) {
1852 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1853 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1860 if (!crtc || crtc->fb == NULL) {
1861 DRM_DEBUG_KMS("no output, disabling\n");
1862 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1866 intel_crtc = to_intel_crtc(crtc);
1868 intel_fb = to_intel_framebuffer(fb);
1869 obj = intel_fb->obj;
1871 enable_fbc = i915_enable_fbc;
1872 if (enable_fbc < 0) {
1873 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1875 if (INTEL_INFO(dev)->gen <= 5)
1879 DRM_DEBUG_KMS("fbc disabled per module param\n");
1880 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1883 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1884 DRM_DEBUG_KMS("framebuffer too large, disabling "
1886 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1889 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1890 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1891 DRM_DEBUG_KMS("mode incompatible with compression, "
1893 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1896 if ((crtc->mode.hdisplay > 2048) ||
1897 (crtc->mode.vdisplay > 1536)) {
1898 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1899 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1902 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1903 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1904 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1908 /* The use of a CPU fence is mandatory in order to detect writes
1909 * by the CPU to the scanout and trigger updates to the FBC.
1911 if (obj->tiling_mode != I915_TILING_X ||
1912 obj->fence_reg == I915_FENCE_REG_NONE) {
1913 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1914 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1918 /* If the kernel debugger is active, always disable compression */
1919 if (in_dbg_master())
1922 /* If the scanout has not changed, don't modify the FBC settings.
1923 * Note that we make the fundamental assumption that the fb->obj
1924 * cannot be unpinned (and have its GTT offset and fence revoked)
1925 * without first being decoupled from the scanout and FBC disabled.
1927 if (dev_priv->cfb_plane == intel_crtc->plane &&
1928 dev_priv->cfb_fb == fb->base.id &&
1929 dev_priv->cfb_y == crtc->y)
1932 if (intel_fbc_enabled(dev)) {
1933 /* We update FBC along two paths, after changing fb/crtc
1934 * configuration (modeswitching) and after page-flipping
1935 * finishes. For the latter, we know that not only did
1936 * we disable the FBC at the start of the page-flip
1937 * sequence, but also more than one vblank has passed.
1939 * For the former case of modeswitching, it is possible
1940 * to switch between two FBC valid configurations
1941 * instantaneously so we do need to disable the FBC
1942 * before we can modify its control registers. We also
1943 * have to wait for the next vblank for that to take
1944 * effect. However, since we delay enabling FBC we can
1945 * assume that a vblank has passed since disabling and
1946 * that we can safely alter the registers in the deferred
1949 * In the scenario that we go from a valid to invalid
1950 * and then back to valid FBC configuration we have
1951 * no strict enforcement that a vblank occurred since
1952 * disabling the FBC. However, along all current pipe
1953 * disabling paths we do need to wait for a vblank at
1954 * some point. And we wait before enabling FBC anyway.
1956 DRM_DEBUG_KMS("disabling active FBC for update\n");
1957 intel_disable_fbc(dev);
1960 intel_enable_fbc(crtc, 500);
1964 /* Multiple disables should be harmless */
1965 if (intel_fbc_enabled(dev)) {
1966 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1967 intel_disable_fbc(dev);
1972 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1973 struct drm_i915_gem_object *obj,
1974 struct intel_ring_buffer *pipelined)
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1980 switch (obj->tiling_mode) {
1981 case I915_TILING_NONE:
1982 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1983 alignment = 128 * 1024;
1984 else if (INTEL_INFO(dev)->gen >= 4)
1985 alignment = 4 * 1024;
1987 alignment = 64 * 1024;
1990 /* pin() will align the object as required by fence */
1994 /* FIXME: Is this true? */
1995 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2001 dev_priv->mm.interruptible = false;
2002 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2004 goto err_interruptible;
2006 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2007 * fence, whereas 965+ only requires a fence if using
2008 * framebuffer compression. For simplicity, we always install
2009 * a fence as the cost is not that onerous.
2011 if (obj->tiling_mode != I915_TILING_NONE) {
2012 ret = i915_gem_object_get_fence(obj, pipelined);
2017 dev_priv->mm.interruptible = true;
2021 i915_gem_object_unpin(obj);
2023 dev_priv->mm.interruptible = true;
2027 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2030 struct drm_device *dev = crtc->dev;
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2033 struct intel_framebuffer *intel_fb;
2034 struct drm_i915_gem_object *obj;
2035 int plane = intel_crtc->plane;
2036 unsigned long Start, Offset;
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2058 dspcntr |= DISPPLANE_8BPP;
2061 if (fb->depth == 15)
2062 dspcntr |= DISPPLANE_15_16BPP;
2064 dspcntr |= DISPPLANE_16BPP;
2068 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2071 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2074 if (INTEL_INFO(dev)->gen >= 4) {
2075 if (obj->tiling_mode != I915_TILING_NONE)
2076 dspcntr |= DISPPLANE_TILED;
2078 dspcntr &= ~DISPPLANE_TILED;
2081 I915_WRITE(reg, dspcntr);
2083 Start = obj->gtt_offset;
2084 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2086 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2087 Start, Offset, x, y, fb->pitches[0]);
2088 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2089 if (INTEL_INFO(dev)->gen >= 4) {
2090 I915_WRITE(DSPSURF(plane), Start);
2091 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2092 I915_WRITE(DSPADDR(plane), Offset);
2094 I915_WRITE(DSPADDR(plane), Start + Offset);
2100 static int ironlake_update_plane(struct drm_crtc *crtc,
2101 struct drm_framebuffer *fb, int x, int y)
2103 struct drm_device *dev = crtc->dev;
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106 struct intel_framebuffer *intel_fb;
2107 struct drm_i915_gem_object *obj;
2108 int plane = intel_crtc->plane;
2109 unsigned long Start, Offset;
2119 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2123 intel_fb = to_intel_framebuffer(fb);
2124 obj = intel_fb->obj;
2126 reg = DSPCNTR(plane);
2127 dspcntr = I915_READ(reg);
2128 /* Mask out pixel format bits in case we change it */
2129 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2130 switch (fb->bits_per_pixel) {
2132 dspcntr |= DISPPLANE_8BPP;
2135 if (fb->depth != 16)
2138 dspcntr |= DISPPLANE_16BPP;
2142 if (fb->depth == 24)
2143 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2144 else if (fb->depth == 30)
2145 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2150 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2157 dspcntr &= ~DISPPLANE_TILED;
2160 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2162 I915_WRITE(reg, dspcntr);
2164 Start = obj->gtt_offset;
2165 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2167 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2168 Start, Offset, x, y, fb->pitches[0]);
2169 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2170 I915_WRITE(DSPSURF(plane), Start);
2171 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2172 I915_WRITE(DSPADDR(plane), Offset);
2178 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2180 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2181 int x, int y, enum mode_set_atomic state)
2183 struct drm_device *dev = crtc->dev;
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2187 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2191 intel_update_fbc(dev);
2192 intel_increase_pllclock(crtc);
2198 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2199 struct drm_framebuffer *old_fb)
2201 struct drm_device *dev = crtc->dev;
2202 struct drm_i915_master_private *master_priv;
2203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2208 DRM_ERROR("No FB bound\n");
2212 switch (intel_crtc->plane) {
2217 if (IS_IVYBRIDGE(dev))
2219 /* fall through otherwise */
2221 DRM_ERROR("no plane for crtc\n");
2225 mutex_lock(&dev->struct_mutex);
2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
2230 mutex_unlock(&dev->struct_mutex);
2231 DRM_ERROR("pin & fence failed\n");
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2239 wait_event(dev_priv->pending_flip_queue,
2240 atomic_read(&dev_priv->mm.wedged) ||
2241 atomic_read(&obj->pending_flip) == 0);
2243 /* Big Hammer, we also need to ensure that any pending
2244 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2245 * current scanout is retired before unpinning the old
2248 * This should only fail upon a hung GPU, in which case we
2249 * can safely continue.
2251 ret = i915_gem_object_finish_gpu(obj);
2255 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2256 LEAVE_ATOMIC_MODE_SET);
2258 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2259 mutex_unlock(&dev->struct_mutex);
2260 DRM_ERROR("failed to update base address\n");
2265 intel_wait_for_vblank(dev, intel_crtc->pipe);
2266 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2269 mutex_unlock(&dev->struct_mutex);
2271 if (!dev->primary->master)
2274 master_priv = dev->primary->master->driver_priv;
2275 if (!master_priv->sarea_priv)
2278 if (intel_crtc->pipe) {
2279 master_priv->sarea_priv->pipeB_x = x;
2280 master_priv->sarea_priv->pipeB_y = y;
2282 master_priv->sarea_priv->pipeA_x = x;
2283 master_priv->sarea_priv->pipeA_y = y;
2289 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2291 struct drm_device *dev = crtc->dev;
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2295 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2296 dpa_ctl = I915_READ(DP_A);
2297 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2299 if (clock < 200000) {
2301 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2302 /* workaround for 160Mhz:
2303 1) program 0x4600c bits 15:0 = 0x8124
2304 2) program 0x46010 bit 0 = 1
2305 3) program 0x46034 bit 24 = 1
2306 4) program 0x64000 bit 14 = 1
2308 temp = I915_READ(0x4600c);
2310 I915_WRITE(0x4600c, temp | 0x8124);
2312 temp = I915_READ(0x46010);
2313 I915_WRITE(0x46010, temp | 1);
2315 temp = I915_READ(0x46034);
2316 I915_WRITE(0x46034, temp | (1 << 24));
2318 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2320 I915_WRITE(DP_A, dpa_ctl);
2326 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2331 int pipe = intel_crtc->pipe;
2334 /* enable normal train */
2335 reg = FDI_TX_CTL(pipe);
2336 temp = I915_READ(reg);
2337 if (IS_IVYBRIDGE(dev)) {
2338 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2339 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2341 temp &= ~FDI_LINK_TRAIN_NONE;
2342 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2344 I915_WRITE(reg, temp);
2346 reg = FDI_RX_CTL(pipe);
2347 temp = I915_READ(reg);
2348 if (HAS_PCH_CPT(dev)) {
2349 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2350 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_NONE;
2355 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2357 /* wait one idle pattern time */
2361 /* IVB wants error correction enabled */
2362 if (IS_IVYBRIDGE(dev))
2363 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2364 FDI_FE_ERRC_ENABLE);
2367 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2369 struct drm_i915_private *dev_priv = dev->dev_private;
2370 u32 flags = I915_READ(SOUTH_CHICKEN1);
2372 flags |= FDI_PHASE_SYNC_OVR(pipe);
2373 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2374 flags |= FDI_PHASE_SYNC_EN(pipe);
2375 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2376 POSTING_READ(SOUTH_CHICKEN1);
2379 /* The FDI link training functions for ILK/Ibexpeak. */
2380 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2382 struct drm_device *dev = crtc->dev;
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385 int pipe = intel_crtc->pipe;
2386 int plane = intel_crtc->plane;
2387 u32 reg, temp, tries;
2389 /* FDI needs bits from pipe & plane first */
2390 assert_pipe_enabled(dev_priv, pipe);
2391 assert_plane_enabled(dev_priv, plane);
2393 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2395 reg = FDI_RX_IMR(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_RX_SYMBOL_LOCK;
2398 temp &= ~FDI_RX_BIT_LOCK;
2399 I915_WRITE(reg, temp);
2403 /* enable CPU FDI TX and PCH FDI RX */
2404 reg = FDI_TX_CTL(pipe);
2405 temp = I915_READ(reg);
2407 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2408 temp &= ~FDI_LINK_TRAIN_NONE;
2409 temp |= FDI_LINK_TRAIN_PATTERN_1;
2410 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2412 reg = FDI_RX_CTL(pipe);
2413 temp = I915_READ(reg);
2414 temp &= ~FDI_LINK_TRAIN_NONE;
2415 temp |= FDI_LINK_TRAIN_PATTERN_1;
2416 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2421 /* Ironlake workaround, enable clock pointer after FDI enable*/
2422 if (HAS_PCH_IBX(dev)) {
2423 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2424 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2425 FDI_RX_PHASE_SYNC_POINTER_EN);
2428 reg = FDI_RX_IIR(pipe);
2429 for (tries = 0; tries < 5; tries++) {
2430 temp = I915_READ(reg);
2431 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433 if ((temp & FDI_RX_BIT_LOCK)) {
2434 DRM_DEBUG_KMS("FDI train 1 done.\n");
2435 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2440 DRM_ERROR("FDI train 1 fail!\n");
2443 reg = FDI_TX_CTL(pipe);
2444 temp = I915_READ(reg);
2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_2;
2447 I915_WRITE(reg, temp);
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_2;
2453 I915_WRITE(reg, temp);
2458 reg = FDI_RX_IIR(pipe);
2459 for (tries = 0; tries < 5; tries++) {
2460 temp = I915_READ(reg);
2461 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2463 if (temp & FDI_RX_SYMBOL_LOCK) {
2464 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2465 DRM_DEBUG_KMS("FDI train 2 done.\n");
2470 DRM_ERROR("FDI train 2 fail!\n");
2472 DRM_DEBUG_KMS("FDI train done\n");
2476 static const int snb_b_fdi_train_param[] = {
2477 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2478 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2479 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2480 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2483 /* The FDI link training functions for SNB/Cougarpoint. */
2484 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2486 struct drm_device *dev = crtc->dev;
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2489 int pipe = intel_crtc->pipe;
2492 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2494 reg = FDI_RX_IMR(pipe);
2495 temp = I915_READ(reg);
2496 temp &= ~FDI_RX_SYMBOL_LOCK;
2497 temp &= ~FDI_RX_BIT_LOCK;
2498 I915_WRITE(reg, temp);
2503 /* enable CPU FDI TX and PCH FDI RX */
2504 reg = FDI_TX_CTL(pipe);
2505 temp = I915_READ(reg);
2507 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2513 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2515 reg = FDI_RX_CTL(pipe);
2516 temp = I915_READ(reg);
2517 if (HAS_PCH_CPT(dev)) {
2518 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2519 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2521 temp &= ~FDI_LINK_TRAIN_NONE;
2522 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529 if (HAS_PCH_CPT(dev))
2530 cpt_phase_pointer_enable(dev, pipe);
2532 for (i = 0; i < 4; i++) {
2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536 temp |= snb_b_fdi_train_param[i];
2537 I915_WRITE(reg, temp);
2542 reg = FDI_RX_IIR(pipe);
2543 temp = I915_READ(reg);
2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2546 if (temp & FDI_RX_BIT_LOCK) {
2547 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2548 DRM_DEBUG_KMS("FDI train 1 done.\n");
2553 DRM_ERROR("FDI train 1 fail!\n");
2556 reg = FDI_TX_CTL(pipe);
2557 temp = I915_READ(reg);
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2565 I915_WRITE(reg, temp);
2567 reg = FDI_RX_CTL(pipe);
2568 temp = I915_READ(reg);
2569 if (HAS_PCH_CPT(dev)) {
2570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2571 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2573 temp &= ~FDI_LINK_TRAIN_NONE;
2574 temp |= FDI_LINK_TRAIN_PATTERN_2;
2576 I915_WRITE(reg, temp);
2581 for (i = 0; i < 4; i++) {
2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585 temp |= snb_b_fdi_train_param[i];
2586 I915_WRITE(reg, temp);
2591 reg = FDI_RX_IIR(pipe);
2592 temp = I915_READ(reg);
2593 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595 if (temp & FDI_RX_SYMBOL_LOCK) {
2596 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2597 DRM_DEBUG_KMS("FDI train 2 done.\n");
2602 DRM_ERROR("FDI train 2 fail!\n");
2604 DRM_DEBUG_KMS("FDI train done.\n");
2607 /* Manual link training for Ivy Bridge A0 parts */
2608 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2610 struct drm_device *dev = crtc->dev;
2611 struct drm_i915_private *dev_priv = dev->dev_private;
2612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2613 int pipe = intel_crtc->pipe;
2616 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2618 reg = FDI_RX_IMR(pipe);
2619 temp = I915_READ(reg);
2620 temp &= ~FDI_RX_SYMBOL_LOCK;
2621 temp &= ~FDI_RX_BIT_LOCK;
2622 I915_WRITE(reg, temp);
2627 /* enable CPU FDI TX and PCH FDI RX */
2628 reg = FDI_TX_CTL(pipe);
2629 temp = I915_READ(reg);
2631 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2632 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2633 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2634 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2636 temp |= FDI_COMPOSITE_SYNC;
2637 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2639 reg = FDI_RX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_AUTO;
2642 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2643 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2644 temp |= FDI_COMPOSITE_SYNC;
2645 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2650 if (HAS_PCH_CPT(dev))
2651 cpt_phase_pointer_enable(dev, pipe);
2653 for (i = 0; i < 4; i++) {
2654 reg = FDI_TX_CTL(pipe);
2655 temp = I915_READ(reg);
2656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657 temp |= snb_b_fdi_train_param[i];
2658 I915_WRITE(reg, temp);
2663 reg = FDI_RX_IIR(pipe);
2664 temp = I915_READ(reg);
2665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2667 if (temp & FDI_RX_BIT_LOCK ||
2668 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2669 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2670 DRM_DEBUG_KMS("FDI train 1 done.\n");
2675 DRM_ERROR("FDI train 1 fail!\n");
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2684 I915_WRITE(reg, temp);
2686 reg = FDI_RX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2690 I915_WRITE(reg, temp);
2695 for (i = 0; i < 4; i++) {
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
2700 I915_WRITE(reg, temp);
2705 reg = FDI_RX_IIR(pipe);
2706 temp = I915_READ(reg);
2707 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2716 DRM_ERROR("FDI train 2 fail!\n");
2718 DRM_DEBUG_KMS("FDI train done.\n");
2721 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2723 struct drm_device *dev = crtc->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726 int pipe = intel_crtc->pipe;
2729 /* Write the TU size bits so error detection works */
2730 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2731 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2733 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~((0x7 << 19) | (0x7 << 16));
2737 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2738 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2739 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2744 /* Switch from Rawclk to PCDclk */
2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp | FDI_PCDCLK);
2751 /* Enable CPU FDI TX PLL, always on for Ironlake */
2752 reg = FDI_TX_CTL(pipe);
2753 temp = I915_READ(reg);
2754 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2755 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2762 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2765 u32 flags = I915_READ(SOUTH_CHICKEN1);
2767 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2768 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2769 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2770 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2771 POSTING_READ(SOUTH_CHICKEN1);
2773 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778 int pipe = intel_crtc->pipe;
2781 /* disable CPU FDI tx and PCH FDI rx */
2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 temp &= ~(0x7 << 16);
2790 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2791 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2796 /* Ironlake workaround, disable clock pointer after downing FDI */
2797 if (HAS_PCH_IBX(dev)) {
2798 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2799 I915_WRITE(FDI_RX_CHICKEN(pipe),
2800 I915_READ(FDI_RX_CHICKEN(pipe) &
2801 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2802 } else if (HAS_PCH_CPT(dev)) {
2803 cpt_phase_pointer_disable(dev, pipe);
2806 /* still set train pattern 1 */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_NONE;
2810 temp |= FDI_LINK_TRAIN_PATTERN_1;
2811 I915_WRITE(reg, temp);
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 if (HAS_PCH_CPT(dev)) {
2816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2819 temp &= ~FDI_LINK_TRAIN_NONE;
2820 temp |= FDI_LINK_TRAIN_PATTERN_1;
2822 /* BPC in FDI rx is consistent with that in PIPECONF */
2823 temp &= ~(0x07 << 16);
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp);
2832 * When we disable a pipe, we need to clear any pending scanline wait events
2833 * to avoid hanging the ring, which we assume we are waiting on.
2835 static void intel_clear_scanline_wait(struct drm_device *dev)
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 struct intel_ring_buffer *ring;
2842 /* Can't break the hang on i8xx */
2845 ring = LP_RING(dev_priv);
2846 tmp = I915_READ_CTL(ring);
2847 if (tmp & RING_WAIT)
2848 I915_WRITE_CTL(ring, tmp);
2851 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2853 struct drm_i915_gem_object *obj;
2854 struct drm_i915_private *dev_priv;
2856 if (crtc->fb == NULL)
2859 obj = to_intel_framebuffer(crtc->fb)->obj;
2860 dev_priv = crtc->dev->dev_private;
2861 wait_event(dev_priv->pending_flip_queue,
2862 atomic_read(&obj->pending_flip) == 0);
2865 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_mode_config *mode_config = &dev->mode_config;
2869 struct intel_encoder *encoder;
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2875 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2876 if (encoder->base.crtc != crtc)
2879 switch (encoder->type) {
2880 case INTEL_OUTPUT_EDP:
2881 if (!intel_encoder_is_pch_edp(&encoder->base))
2891 * Enable PCH resources required for PCH ports:
2893 * - FDI training & RX/TX
2894 * - update transcoder timings
2895 * - DP transcoding bits
2898 static void ironlake_pch_enable(struct drm_crtc *crtc)
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 int pipe = intel_crtc->pipe;
2904 u32 reg, temp, transc_sel;
2906 /* For PCH output, training FDI link */
2907 dev_priv->display.fdi_link_train(crtc);
2909 intel_enable_pch_pll(dev_priv, pipe);
2911 if (HAS_PCH_CPT(dev)) {
2912 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2915 /* Be sure PCH DPLL SEL is set */
2916 temp = I915_READ(PCH_DPLL_SEL);
2918 temp &= ~(TRANSA_DPLLB_SEL);
2919 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2920 } else if (pipe == 1) {
2921 temp &= ~(TRANSB_DPLLB_SEL);
2922 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2923 } else if (pipe == 2) {
2924 temp &= ~(TRANSC_DPLLB_SEL);
2925 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2927 I915_WRITE(PCH_DPLL_SEL, temp);
2930 /* set transcoder timing, panel must allow it */
2931 assert_panel_unlocked(dev_priv, pipe);
2932 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2933 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2934 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2936 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2937 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2938 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2940 intel_fdi_normal_train(crtc);
2942 /* For PCH DP, enable TRANS_DP_CTL */
2943 if (HAS_PCH_CPT(dev) &&
2944 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2945 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2946 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2947 reg = TRANS_DP_CTL(pipe);
2948 temp = I915_READ(reg);
2949 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2950 TRANS_DP_SYNC_MASK |
2952 temp |= (TRANS_DP_OUTPUT_ENABLE |
2953 TRANS_DP_ENH_FRAMING);
2954 temp |= bpc << 9; /* same format but at 11:9 */
2956 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2957 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2958 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2959 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2961 switch (intel_trans_dp_port_sel(crtc)) {
2963 temp |= TRANS_DP_PORT_SEL_B;
2966 temp |= TRANS_DP_PORT_SEL_C;
2969 temp |= TRANS_DP_PORT_SEL_D;
2972 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2973 temp |= TRANS_DP_PORT_SEL_B;
2977 I915_WRITE(reg, temp);
2980 intel_enable_transcoder(dev_priv, pipe);
2983 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2989 temp = I915_READ(dslreg);
2991 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2992 /* Without this, mode sets may fail silently on FDI */
2993 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2995 I915_WRITE(tc2reg, 0);
2996 if (wait_for(I915_READ(dslreg) != temp, 5))
2997 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3001 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006 int pipe = intel_crtc->pipe;
3007 int plane = intel_crtc->plane;
3011 if (intel_crtc->active)
3014 intel_crtc->active = true;
3015 intel_update_watermarks(dev);
3017 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3018 temp = I915_READ(PCH_LVDS);
3019 if ((temp & LVDS_PORT_EN) == 0)
3020 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3023 is_pch_port = intel_crtc_driving_pch(crtc);
3026 ironlake_fdi_pll_enable(crtc);
3028 ironlake_fdi_disable(crtc);
3030 /* Enable panel fitting for LVDS */
3031 if (dev_priv->pch_pf_size &&
3032 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3033 /* Force use of hard-coded filter coefficients
3034 * as some pre-programmed values are broken,
3037 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3038 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3039 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3043 * On ILK+ LUT must be loaded before the pipe is running but with
3046 intel_crtc_load_lut(crtc);
3048 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3049 intel_enable_plane(dev_priv, plane, pipe);
3052 ironlake_pch_enable(crtc);
3054 mutex_lock(&dev->struct_mutex);
3055 intel_update_fbc(dev);
3056 mutex_unlock(&dev->struct_mutex);
3058 intel_crtc_update_cursor(crtc, true);
3061 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3063 struct drm_device *dev = crtc->dev;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066 int pipe = intel_crtc->pipe;
3067 int plane = intel_crtc->plane;
3070 if (!intel_crtc->active)
3073 intel_crtc_wait_for_pending_flips(crtc);
3074 drm_vblank_off(dev, pipe);
3075 intel_crtc_update_cursor(crtc, false);
3077 intel_disable_plane(dev_priv, plane, pipe);
3079 if (dev_priv->cfb_plane == plane)
3080 intel_disable_fbc(dev);
3082 intel_disable_pipe(dev_priv, pipe);
3085 I915_WRITE(PF_CTL(pipe), 0);
3086 I915_WRITE(PF_WIN_SZ(pipe), 0);
3088 ironlake_fdi_disable(crtc);
3090 /* This is a horrible layering violation; we should be doing this in
3091 * the connector/encoder ->prepare instead, but we don't always have
3092 * enough information there about the config to know whether it will
3093 * actually be necessary or just cause undesired flicker.
3095 intel_disable_pch_ports(dev_priv, pipe);
3097 intel_disable_transcoder(dev_priv, pipe);
3099 if (HAS_PCH_CPT(dev)) {
3100 /* disable TRANS_DP_CTL */
3101 reg = TRANS_DP_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3104 temp |= TRANS_DP_PORT_SEL_NONE;
3105 I915_WRITE(reg, temp);
3107 /* disable DPLL_SEL */
3108 temp = I915_READ(PCH_DPLL_SEL);
3111 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3114 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3117 /* C shares PLL A or B */
3118 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3123 I915_WRITE(PCH_DPLL_SEL, temp);
3126 /* disable PCH DPLL */
3127 if (!intel_crtc->no_pll)
3128 intel_disable_pch_pll(dev_priv, pipe);
3130 /* Switch from PCDclk to Rawclk */
3131 reg = FDI_RX_CTL(pipe);
3132 temp = I915_READ(reg);
3133 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3135 /* Disable CPU FDI TX PLL */
3136 reg = FDI_TX_CTL(pipe);
3137 temp = I915_READ(reg);
3138 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3143 reg = FDI_RX_CTL(pipe);
3144 temp = I915_READ(reg);
3145 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3147 /* Wait for the clocks to turn off. */
3151 intel_crtc->active = false;
3152 intel_update_watermarks(dev);
3154 mutex_lock(&dev->struct_mutex);
3155 intel_update_fbc(dev);
3156 intel_clear_scanline_wait(dev);
3157 mutex_unlock(&dev->struct_mutex);
3160 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163 int pipe = intel_crtc->pipe;
3164 int plane = intel_crtc->plane;
3166 /* XXX: When our outputs are all unaware of DPMS modes other than off
3167 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3170 case DRM_MODE_DPMS_ON:
3171 case DRM_MODE_DPMS_STANDBY:
3172 case DRM_MODE_DPMS_SUSPEND:
3173 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3174 ironlake_crtc_enable(crtc);
3177 case DRM_MODE_DPMS_OFF:
3178 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3179 ironlake_crtc_disable(crtc);
3184 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3186 if (!enable && intel_crtc->overlay) {
3187 struct drm_device *dev = intel_crtc->base.dev;
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3190 mutex_lock(&dev->struct_mutex);
3191 dev_priv->mm.interruptible = false;
3192 (void) intel_overlay_switch_off(intel_crtc->overlay);
3193 dev_priv->mm.interruptible = true;
3194 mutex_unlock(&dev->struct_mutex);
3197 /* Let userspace switch the overlay on again. In most cases userspace
3198 * has to recompute where to put it anyway.
3202 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3204 struct drm_device *dev = crtc->dev;
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207 int pipe = intel_crtc->pipe;
3208 int plane = intel_crtc->plane;
3210 if (intel_crtc->active)
3213 intel_crtc->active = true;
3214 intel_update_watermarks(dev);
3216 intel_enable_pll(dev_priv, pipe);
3217 intel_enable_pipe(dev_priv, pipe, false);
3218 intel_enable_plane(dev_priv, plane, pipe);
3220 intel_crtc_load_lut(crtc);
3221 intel_update_fbc(dev);
3223 /* Give the overlay scaler a chance to enable if it's on this pipe */
3224 intel_crtc_dpms_overlay(intel_crtc, true);
3225 intel_crtc_update_cursor(crtc, true);
3228 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3230 struct drm_device *dev = crtc->dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3233 int pipe = intel_crtc->pipe;
3234 int plane = intel_crtc->plane;
3236 if (!intel_crtc->active)
3239 /* Give the overlay scaler a chance to disable if it's on this pipe */
3240 intel_crtc_wait_for_pending_flips(crtc);
3241 drm_vblank_off(dev, pipe);
3242 intel_crtc_dpms_overlay(intel_crtc, false);
3243 intel_crtc_update_cursor(crtc, false);
3245 if (dev_priv->cfb_plane == plane)
3246 intel_disable_fbc(dev);
3248 intel_disable_plane(dev_priv, plane, pipe);
3249 intel_disable_pipe(dev_priv, pipe);
3250 intel_disable_pll(dev_priv, pipe);
3252 intel_crtc->active = false;
3253 intel_update_fbc(dev);
3254 intel_update_watermarks(dev);
3255 intel_clear_scanline_wait(dev);
3258 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3260 /* XXX: When our outputs are all unaware of DPMS modes other than off
3261 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3264 case DRM_MODE_DPMS_ON:
3265 case DRM_MODE_DPMS_STANDBY:
3266 case DRM_MODE_DPMS_SUSPEND:
3267 i9xx_crtc_enable(crtc);
3269 case DRM_MODE_DPMS_OFF:
3270 i9xx_crtc_disable(crtc);
3276 * Sets the power management mode of the pipe and plane.
3278 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3280 struct drm_device *dev = crtc->dev;
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 struct drm_i915_master_private *master_priv;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 int pipe = intel_crtc->pipe;
3287 if (intel_crtc->dpms_mode == mode)
3290 intel_crtc->dpms_mode = mode;
3292 dev_priv->display.dpms(crtc, mode);
3294 if (!dev->primary->master)
3297 master_priv = dev->primary->master->driver_priv;
3298 if (!master_priv->sarea_priv)
3301 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3305 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3306 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3309 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3310 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3313 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3318 static void intel_crtc_disable(struct drm_crtc *crtc)
3320 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3321 struct drm_device *dev = crtc->dev;
3323 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3326 mutex_lock(&dev->struct_mutex);
3327 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3328 mutex_unlock(&dev->struct_mutex);
3332 /* Prepare for a mode set.
3334 * Note we could be a lot smarter here. We need to figure out which outputs
3335 * will be enabled, which disabled (in short, how the config will changes)
3336 * and perform the minimum necessary steps to accomplish that, e.g. updating
3337 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3338 * panel fitting is in the proper state, etc.
3340 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3342 i9xx_crtc_disable(crtc);
3345 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3347 i9xx_crtc_enable(crtc);
3350 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3352 ironlake_crtc_disable(crtc);
3355 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3357 ironlake_crtc_enable(crtc);
3360 void intel_encoder_prepare(struct drm_encoder *encoder)
3362 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3363 /* lvds has its own version of prepare see intel_lvds_prepare */
3364 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3367 void intel_encoder_commit(struct drm_encoder *encoder)
3369 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3370 struct drm_device *dev = encoder->dev;
3371 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3372 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3374 /* lvds has its own version of commit see intel_lvds_commit */
3375 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3377 if (HAS_PCH_CPT(dev))
3378 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3381 void intel_encoder_destroy(struct drm_encoder *encoder)
3383 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3385 drm_encoder_cleanup(encoder);
3386 kfree(intel_encoder);
3389 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3390 struct drm_display_mode *mode,
3391 struct drm_display_mode *adjusted_mode)
3393 struct drm_device *dev = crtc->dev;
3395 if (HAS_PCH_SPLIT(dev)) {
3396 /* FDI link clock is fixed at 2.7G */
3397 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3401 /* XXX some encoders set the crtcinfo, others don't.
3402 * Obviously we need some form of conflict resolution here...
3404 if (adjusted_mode->crtc_htotal == 0)
3405 drm_mode_set_crtcinfo(adjusted_mode, 0);
3410 static int i945_get_display_clock_speed(struct drm_device *dev)
3415 static int i915_get_display_clock_speed(struct drm_device *dev)
3420 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3425 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3429 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3431 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3434 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3435 case GC_DISPLAY_CLOCK_333_MHZ:
3438 case GC_DISPLAY_CLOCK_190_200_MHZ:
3444 static int i865_get_display_clock_speed(struct drm_device *dev)
3449 static int i855_get_display_clock_speed(struct drm_device *dev)
3452 /* Assume that the hardware is in the high speed state. This
3453 * should be the default.
3455 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3456 case GC_CLOCK_133_200:
3457 case GC_CLOCK_100_200:
3459 case GC_CLOCK_166_250:
3461 case GC_CLOCK_100_133:
3465 /* Shouldn't happen */
3469 static int i830_get_display_clock_speed(struct drm_device *dev)
3483 fdi_reduce_ratio(u32 *num, u32 *den)
3485 while (*num > 0xffffff || *den > 0xffffff) {
3492 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3493 int link_clock, struct fdi_m_n *m_n)
3495 m_n->tu = 64; /* default size */
3497 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3498 m_n->gmch_m = bits_per_pixel * pixel_clock;
3499 m_n->gmch_n = link_clock * nlanes * 8;
3500 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3502 m_n->link_m = pixel_clock;
3503 m_n->link_n = link_clock;
3504 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3508 struct intel_watermark_params {
3509 unsigned long fifo_size;
3510 unsigned long max_wm;
3511 unsigned long default_wm;
3512 unsigned long guard_size;
3513 unsigned long cacheline_size;
3516 /* Pineview has different values for various configs */
3517 static const struct intel_watermark_params pineview_display_wm = {
3518 PINEVIEW_DISPLAY_FIFO,
3522 PINEVIEW_FIFO_LINE_SIZE
3524 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3525 PINEVIEW_DISPLAY_FIFO,
3527 PINEVIEW_DFT_HPLLOFF_WM,
3529 PINEVIEW_FIFO_LINE_SIZE
3531 static const struct intel_watermark_params pineview_cursor_wm = {
3532 PINEVIEW_CURSOR_FIFO,
3533 PINEVIEW_CURSOR_MAX_WM,
3534 PINEVIEW_CURSOR_DFT_WM,
3535 PINEVIEW_CURSOR_GUARD_WM,
3536 PINEVIEW_FIFO_LINE_SIZE,
3538 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3539 PINEVIEW_CURSOR_FIFO,
3540 PINEVIEW_CURSOR_MAX_WM,
3541 PINEVIEW_CURSOR_DFT_WM,
3542 PINEVIEW_CURSOR_GUARD_WM,
3543 PINEVIEW_FIFO_LINE_SIZE
3545 static const struct intel_watermark_params g4x_wm_info = {
3552 static const struct intel_watermark_params g4x_cursor_wm_info = {
3559 static const struct intel_watermark_params i965_cursor_wm_info = {
3564 I915_FIFO_LINE_SIZE,
3566 static const struct intel_watermark_params i945_wm_info = {
3573 static const struct intel_watermark_params i915_wm_info = {
3580 static const struct intel_watermark_params i855_wm_info = {
3587 static const struct intel_watermark_params i830_wm_info = {
3595 static const struct intel_watermark_params ironlake_display_wm_info = {
3602 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3609 static const struct intel_watermark_params ironlake_display_srwm_info = {
3610 ILK_DISPLAY_SR_FIFO,
3611 ILK_DISPLAY_MAX_SRWM,
3612 ILK_DISPLAY_DFT_SRWM,
3616 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3618 ILK_CURSOR_MAX_SRWM,
3619 ILK_CURSOR_DFT_SRWM,
3624 static const struct intel_watermark_params sandybridge_display_wm_info = {
3631 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3638 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3639 SNB_DISPLAY_SR_FIFO,
3640 SNB_DISPLAY_MAX_SRWM,
3641 SNB_DISPLAY_DFT_SRWM,
3645 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3647 SNB_CURSOR_MAX_SRWM,
3648 SNB_CURSOR_DFT_SRWM,
3655 * intel_calculate_wm - calculate watermark level
3656 * @clock_in_khz: pixel clock
3657 * @wm: chip FIFO params
3658 * @pixel_size: display pixel size
3659 * @latency_ns: memory latency for the platform
3661 * Calculate the watermark level (the level at which the display plane will
3662 * start fetching from memory again). Each chip has a different display
3663 * FIFO size and allocation, so the caller needs to figure that out and pass
3664 * in the correct intel_watermark_params structure.
3666 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3667 * on the pixel size. When it reaches the watermark level, it'll start
3668 * fetching FIFO line sized based chunks from memory until the FIFO fills
3669 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3670 * will occur, and a display engine hang could result.
3672 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3673 const struct intel_watermark_params *wm,
3676 unsigned long latency_ns)
3678 long entries_required, wm_size;
3681 * Note: we need to make sure we don't overflow for various clock &
3683 * clocks go from a few thousand to several hundred thousand.
3684 * latency is usually a few thousand
3686 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3688 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3690 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3692 wm_size = fifo_size - (entries_required + wm->guard_size);
3694 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3696 /* Don't promote wm_size to unsigned... */
3697 if (wm_size > (long)wm->max_wm)
3698 wm_size = wm->max_wm;
3700 wm_size = wm->default_wm;
3704 struct cxsr_latency {
3707 unsigned long fsb_freq;
3708 unsigned long mem_freq;
3709 unsigned long display_sr;
3710 unsigned long display_hpll_disable;
3711 unsigned long cursor_sr;
3712 unsigned long cursor_hpll_disable;
3715 static const struct cxsr_latency cxsr_latency_table[] = {
3716 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3717 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3718 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3719 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3720 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3722 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3723 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3724 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3725 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3726 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3728 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3729 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3730 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3731 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3732 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3734 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3735 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3736 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3737 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3738 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3740 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3741 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3742 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3743 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3744 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3746 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3747 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3748 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3749 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3750 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3753 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3758 const struct cxsr_latency *latency;
3761 if (fsb == 0 || mem == 0)
3764 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3765 latency = &cxsr_latency_table[i];
3766 if (is_desktop == latency->is_desktop &&
3767 is_ddr3 == latency->is_ddr3 &&
3768 fsb == latency->fsb_freq && mem == latency->mem_freq)
3772 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3777 static void pineview_disable_cxsr(struct drm_device *dev)
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3781 /* deactivate cxsr */
3782 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3786 * Latency for FIFO fetches is dependent on several factors:
3787 * - memory configuration (speed, channels)
3789 * - current MCH state
3790 * It can be fairly high in some situations, so here we assume a fairly
3791 * pessimal value. It's a tradeoff between extra memory fetches (if we
3792 * set this value too high, the FIFO will fetch frequently to stay full)
3793 * and power consumption (set it too low to save power and we might see
3794 * FIFO underruns and display "flicker").
3796 * A value of 5us seems to be a good balance; safe for very low end
3797 * platforms but not overly aggressive on lower latency configs.
3799 static const int latency_ns = 5000;
3801 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 uint32_t dsparb = I915_READ(DSPARB);
3807 size = dsparb & 0x7f;
3809 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3811 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3812 plane ? "B" : "A", size);
3817 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820 uint32_t dsparb = I915_READ(DSPARB);
3823 size = dsparb & 0x1ff;
3825 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3826 size >>= 1; /* Convert to cachelines */
3828 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3829 plane ? "B" : "A", size);
3834 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 uint32_t dsparb = I915_READ(DSPARB);
3840 size = dsparb & 0x7f;
3841 size >>= 2; /* Convert to cachelines */
3843 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3850 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 uint32_t dsparb = I915_READ(DSPARB);
3856 size = dsparb & 0x7f;
3857 size >>= 1; /* Convert to cachelines */
3859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3860 plane ? "B" : "A", size);
3865 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3867 struct drm_crtc *crtc, *enabled = NULL;
3869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3870 if (crtc->enabled && crtc->fb) {
3880 static void pineview_update_wm(struct drm_device *dev)
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3883 struct drm_crtc *crtc;
3884 const struct cxsr_latency *latency;
3888 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3889 dev_priv->fsb_freq, dev_priv->mem_freq);
3891 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3892 pineview_disable_cxsr(dev);
3896 crtc = single_enabled_crtc(dev);
3898 int clock = crtc->mode.clock;
3899 int pixel_size = crtc->fb->bits_per_pixel / 8;
3902 wm = intel_calculate_wm(clock, &pineview_display_wm,
3903 pineview_display_wm.fifo_size,
3904 pixel_size, latency->display_sr);
3905 reg = I915_READ(DSPFW1);
3906 reg &= ~DSPFW_SR_MASK;
3907 reg |= wm << DSPFW_SR_SHIFT;
3908 I915_WRITE(DSPFW1, reg);
3909 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3912 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3913 pineview_display_wm.fifo_size,
3914 pixel_size, latency->cursor_sr);
3915 reg = I915_READ(DSPFW3);
3916 reg &= ~DSPFW_CURSOR_SR_MASK;
3917 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3918 I915_WRITE(DSPFW3, reg);
3920 /* Display HPLL off SR */
3921 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3922 pineview_display_hplloff_wm.fifo_size,
3923 pixel_size, latency->display_hpll_disable);
3924 reg = I915_READ(DSPFW3);
3925 reg &= ~DSPFW_HPLL_SR_MASK;
3926 reg |= wm & DSPFW_HPLL_SR_MASK;
3927 I915_WRITE(DSPFW3, reg);
3929 /* cursor HPLL off SR */
3930 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3931 pineview_display_hplloff_wm.fifo_size,
3932 pixel_size, latency->cursor_hpll_disable);
3933 reg = I915_READ(DSPFW3);
3934 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3935 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3936 I915_WRITE(DSPFW3, reg);
3937 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3941 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3942 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3944 pineview_disable_cxsr(dev);
3945 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3949 static bool g4x_compute_wm0(struct drm_device *dev,
3951 const struct intel_watermark_params *display,
3952 int display_latency_ns,
3953 const struct intel_watermark_params *cursor,
3954 int cursor_latency_ns,
3958 struct drm_crtc *crtc;
3959 int htotal, hdisplay, clock, pixel_size;
3960 int line_time_us, line_count;
3961 int entries, tlb_miss;
3963 crtc = intel_get_crtc_for_plane(dev, plane);
3964 if (crtc->fb == NULL || !crtc->enabled) {
3965 *cursor_wm = cursor->guard_size;
3966 *plane_wm = display->guard_size;
3970 htotal = crtc->mode.htotal;
3971 hdisplay = crtc->mode.hdisplay;
3972 clock = crtc->mode.clock;
3973 pixel_size = crtc->fb->bits_per_pixel / 8;
3975 /* Use the small buffer method to calculate plane watermark */
3976 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3977 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3979 entries += tlb_miss;
3980 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3981 *plane_wm = entries + display->guard_size;
3982 if (*plane_wm > (int)display->max_wm)
3983 *plane_wm = display->max_wm;
3985 /* Use the large buffer method to calculate cursor watermark */
3986 line_time_us = ((htotal * 1000) / clock);
3987 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3988 entries = line_count * 64 * pixel_size;
3989 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3991 entries += tlb_miss;
3992 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3993 *cursor_wm = entries + cursor->guard_size;
3994 if (*cursor_wm > (int)cursor->max_wm)
3995 *cursor_wm = (int)cursor->max_wm;
4001 * Check the wm result.
4003 * If any calculated watermark values is larger than the maximum value that
4004 * can be programmed into the associated watermark register, that watermark
4007 static bool g4x_check_srwm(struct drm_device *dev,
4008 int display_wm, int cursor_wm,
4009 const struct intel_watermark_params *display,
4010 const struct intel_watermark_params *cursor)
4012 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4013 display_wm, cursor_wm);
4015 if (display_wm > display->max_wm) {
4016 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4017 display_wm, display->max_wm);
4021 if (cursor_wm > cursor->max_wm) {
4022 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4023 cursor_wm, cursor->max_wm);
4027 if (!(display_wm || cursor_wm)) {
4028 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4035 static bool g4x_compute_srwm(struct drm_device *dev,
4038 const struct intel_watermark_params *display,
4039 const struct intel_watermark_params *cursor,
4040 int *display_wm, int *cursor_wm)
4042 struct drm_crtc *crtc;
4043 int hdisplay, htotal, pixel_size, clock;
4044 unsigned long line_time_us;
4045 int line_count, line_size;
4050 *display_wm = *cursor_wm = 0;
4054 crtc = intel_get_crtc_for_plane(dev, plane);
4055 hdisplay = crtc->mode.hdisplay;
4056 htotal = crtc->mode.htotal;
4057 clock = crtc->mode.clock;
4058 pixel_size = crtc->fb->bits_per_pixel / 8;
4060 line_time_us = (htotal * 1000) / clock;
4061 line_count = (latency_ns / line_time_us + 1000) / 1000;
4062 line_size = hdisplay * pixel_size;
4064 /* Use the minimum of the small and large buffer method for primary */
4065 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4066 large = line_count * line_size;
4068 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4069 *display_wm = entries + display->guard_size;
4071 /* calculate the self-refresh watermark for display cursor */
4072 entries = line_count * pixel_size * 64;
4073 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4074 *cursor_wm = entries + cursor->guard_size;
4076 return g4x_check_srwm(dev,
4077 *display_wm, *cursor_wm,
4081 #define single_plane_enabled(mask) is_power_of_2(mask)
4083 static void g4x_update_wm(struct drm_device *dev)
4085 static const int sr_latency_ns = 12000;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4088 int plane_sr, cursor_sr;
4089 unsigned int enabled = 0;
4091 if (g4x_compute_wm0(dev, 0,
4092 &g4x_wm_info, latency_ns,
4093 &g4x_cursor_wm_info, latency_ns,
4094 &planea_wm, &cursora_wm))
4097 if (g4x_compute_wm0(dev, 1,
4098 &g4x_wm_info, latency_ns,
4099 &g4x_cursor_wm_info, latency_ns,
4100 &planeb_wm, &cursorb_wm))
4103 plane_sr = cursor_sr = 0;
4104 if (single_plane_enabled(enabled) &&
4105 g4x_compute_srwm(dev, ffs(enabled) - 1,
4108 &g4x_cursor_wm_info,
4109 &plane_sr, &cursor_sr))
4110 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4112 I915_WRITE(FW_BLC_SELF,
4113 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4115 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4116 planea_wm, cursora_wm,
4117 planeb_wm, cursorb_wm,
4118 plane_sr, cursor_sr);
4121 (plane_sr << DSPFW_SR_SHIFT) |
4122 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4123 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4126 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4127 (cursora_wm << DSPFW_CURSORA_SHIFT));
4128 /* HPLL off in SR has some issues on G4x... disable it */
4130 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4131 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4134 static void i965_update_wm(struct drm_device *dev)
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137 struct drm_crtc *crtc;
4141 /* Calc sr entries for one plane configs */
4142 crtc = single_enabled_crtc(dev);
4144 /* self-refresh has much higher latency */
4145 static const int sr_latency_ns = 12000;
4146 int clock = crtc->mode.clock;
4147 int htotal = crtc->mode.htotal;
4148 int hdisplay = crtc->mode.hdisplay;
4149 int pixel_size = crtc->fb->bits_per_pixel / 8;
4150 unsigned long line_time_us;
4153 line_time_us = ((htotal * 1000) / clock);
4155 /* Use ns/us then divide to preserve precision */
4156 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4157 pixel_size * hdisplay;
4158 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4159 srwm = I965_FIFO_SIZE - entries;
4163 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4166 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4168 entries = DIV_ROUND_UP(entries,
4169 i965_cursor_wm_info.cacheline_size);
4170 cursor_sr = i965_cursor_wm_info.fifo_size -
4171 (entries + i965_cursor_wm_info.guard_size);
4173 if (cursor_sr > i965_cursor_wm_info.max_wm)
4174 cursor_sr = i965_cursor_wm_info.max_wm;
4176 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4177 "cursor %d\n", srwm, cursor_sr);
4179 if (IS_CRESTLINE(dev))
4180 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4182 /* Turn off self refresh if both pipes are enabled */
4183 if (IS_CRESTLINE(dev))
4184 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4188 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4191 /* 965 has limitations... */
4192 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4193 (8 << 16) | (8 << 8) | (8 << 0));
4194 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4195 /* update cursor SR watermark */
4196 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4199 static void i9xx_update_wm(struct drm_device *dev)
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 const struct intel_watermark_params *wm_info;
4207 int planea_wm, planeb_wm;
4208 struct drm_crtc *crtc, *enabled = NULL;
4211 wm_info = &i945_wm_info;
4212 else if (!IS_GEN2(dev))
4213 wm_info = &i915_wm_info;
4215 wm_info = &i855_wm_info;
4217 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4218 crtc = intel_get_crtc_for_plane(dev, 0);
4219 if (crtc->enabled && crtc->fb) {
4220 planea_wm = intel_calculate_wm(crtc->mode.clock,
4222 crtc->fb->bits_per_pixel / 8,
4226 planea_wm = fifo_size - wm_info->guard_size;
4228 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4229 crtc = intel_get_crtc_for_plane(dev, 1);
4230 if (crtc->enabled && crtc->fb) {
4231 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4233 crtc->fb->bits_per_pixel / 8,
4235 if (enabled == NULL)
4240 planeb_wm = fifo_size - wm_info->guard_size;
4242 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4245 * Overlay gets an aggressive default since video jitter is bad.
4249 /* Play safe and disable self-refresh before adjusting watermarks. */
4250 if (IS_I945G(dev) || IS_I945GM(dev))
4251 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4252 else if (IS_I915GM(dev))
4253 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4255 /* Calc sr entries for one plane configs */
4256 if (HAS_FW_BLC(dev) && enabled) {
4257 /* self-refresh has much higher latency */
4258 static const int sr_latency_ns = 6000;
4259 int clock = enabled->mode.clock;
4260 int htotal = enabled->mode.htotal;
4261 int hdisplay = enabled->mode.hdisplay;
4262 int pixel_size = enabled->fb->bits_per_pixel / 8;
4263 unsigned long line_time_us;
4266 line_time_us = (htotal * 1000) / clock;
4268 /* Use ns/us then divide to preserve precision */
4269 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4270 pixel_size * hdisplay;
4271 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4272 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4273 srwm = wm_info->fifo_size - entries;
4277 if (IS_I945G(dev) || IS_I945GM(dev))
4278 I915_WRITE(FW_BLC_SELF,
4279 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4280 else if (IS_I915GM(dev))
4281 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4284 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4285 planea_wm, planeb_wm, cwm, srwm);
4287 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4288 fwater_hi = (cwm & 0x1f);
4290 /* Set request length to 8 cachelines per fetch */
4291 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4292 fwater_hi = fwater_hi | (1 << 8);
4294 I915_WRITE(FW_BLC, fwater_lo);
4295 I915_WRITE(FW_BLC2, fwater_hi);
4297 if (HAS_FW_BLC(dev)) {
4299 if (IS_I945G(dev) || IS_I945GM(dev))
4300 I915_WRITE(FW_BLC_SELF,
4301 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4302 else if (IS_I915GM(dev))
4303 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4304 DRM_DEBUG_KMS("memory self refresh enabled\n");
4306 DRM_DEBUG_KMS("memory self refresh disabled\n");
4310 static void i830_update_wm(struct drm_device *dev)
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct drm_crtc *crtc;
4317 crtc = single_enabled_crtc(dev);
4321 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4322 dev_priv->display.get_fifo_size(dev, 0),
4323 crtc->fb->bits_per_pixel / 8,
4325 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4326 fwater_lo |= (3<<8) | planea_wm;
4328 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4330 I915_WRITE(FW_BLC, fwater_lo);
4333 #define ILK_LP0_PLANE_LATENCY 700
4334 #define ILK_LP0_CURSOR_LATENCY 1300
4337 * Check the wm result.
4339 * If any calculated watermark values is larger than the maximum value that
4340 * can be programmed into the associated watermark register, that watermark
4343 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4344 int fbc_wm, int display_wm, int cursor_wm,
4345 const struct intel_watermark_params *display,
4346 const struct intel_watermark_params *cursor)
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4350 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4351 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4353 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4354 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4355 fbc_wm, SNB_FBC_MAX_SRWM, level);
4357 /* fbc has it's own way to disable FBC WM */
4358 I915_WRITE(DISP_ARB_CTL,
4359 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4363 if (display_wm > display->max_wm) {
4364 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4365 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4369 if (cursor_wm > cursor->max_wm) {
4370 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4371 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4375 if (!(fbc_wm || display_wm || cursor_wm)) {
4376 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4384 * Compute watermark values of WM[1-3],
4386 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4388 const struct intel_watermark_params *display,
4389 const struct intel_watermark_params *cursor,
4390 int *fbc_wm, int *display_wm, int *cursor_wm)
4392 struct drm_crtc *crtc;
4393 unsigned long line_time_us;
4394 int hdisplay, htotal, pixel_size, clock;
4395 int line_count, line_size;
4400 *fbc_wm = *display_wm = *cursor_wm = 0;
4404 crtc = intel_get_crtc_for_plane(dev, plane);
4405 hdisplay = crtc->mode.hdisplay;
4406 htotal = crtc->mode.htotal;
4407 clock = crtc->mode.clock;
4408 pixel_size = crtc->fb->bits_per_pixel / 8;
4410 line_time_us = (htotal * 1000) / clock;
4411 line_count = (latency_ns / line_time_us + 1000) / 1000;
4412 line_size = hdisplay * pixel_size;
4414 /* Use the minimum of the small and large buffer method for primary */
4415 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4416 large = line_count * line_size;
4418 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4419 *display_wm = entries + display->guard_size;
4423 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4425 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4427 /* calculate the self-refresh watermark for display cursor */
4428 entries = line_count * pixel_size * 64;
4429 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4430 *cursor_wm = entries + cursor->guard_size;
4432 return ironlake_check_srwm(dev, level,
4433 *fbc_wm, *display_wm, *cursor_wm,
4437 static void ironlake_update_wm(struct drm_device *dev)
4439 struct drm_i915_private *dev_priv = dev->dev_private;
4440 int fbc_wm, plane_wm, cursor_wm;
4441 unsigned int enabled;
4444 if (g4x_compute_wm0(dev, 0,
4445 &ironlake_display_wm_info,
4446 ILK_LP0_PLANE_LATENCY,
4447 &ironlake_cursor_wm_info,
4448 ILK_LP0_CURSOR_LATENCY,
4449 &plane_wm, &cursor_wm)) {
4450 I915_WRITE(WM0_PIPEA_ILK,
4451 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4452 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4453 " plane %d, " "cursor: %d\n",
4454 plane_wm, cursor_wm);
4458 if (g4x_compute_wm0(dev, 1,
4459 &ironlake_display_wm_info,
4460 ILK_LP0_PLANE_LATENCY,
4461 &ironlake_cursor_wm_info,
4462 ILK_LP0_CURSOR_LATENCY,
4463 &plane_wm, &cursor_wm)) {
4464 I915_WRITE(WM0_PIPEB_ILK,
4465 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4466 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4467 " plane %d, cursor: %d\n",
4468 plane_wm, cursor_wm);
4473 * Calculate and update the self-refresh watermark only when one
4474 * display plane is used.
4476 I915_WRITE(WM3_LP_ILK, 0);
4477 I915_WRITE(WM2_LP_ILK, 0);
4478 I915_WRITE(WM1_LP_ILK, 0);
4480 if (!single_plane_enabled(enabled))
4482 enabled = ffs(enabled) - 1;
4485 if (!ironlake_compute_srwm(dev, 1, enabled,
4486 ILK_READ_WM1_LATENCY() * 500,
4487 &ironlake_display_srwm_info,
4488 &ironlake_cursor_srwm_info,
4489 &fbc_wm, &plane_wm, &cursor_wm))
4492 I915_WRITE(WM1_LP_ILK,
4494 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4495 (fbc_wm << WM1_LP_FBC_SHIFT) |
4496 (plane_wm << WM1_LP_SR_SHIFT) |
4500 if (!ironlake_compute_srwm(dev, 2, enabled,
4501 ILK_READ_WM2_LATENCY() * 500,
4502 &ironlake_display_srwm_info,
4503 &ironlake_cursor_srwm_info,
4504 &fbc_wm, &plane_wm, &cursor_wm))
4507 I915_WRITE(WM2_LP_ILK,
4509 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4510 (fbc_wm << WM1_LP_FBC_SHIFT) |
4511 (plane_wm << WM1_LP_SR_SHIFT) |
4515 * WM3 is unsupported on ILK, probably because we don't have latency
4516 * data for that power state
4520 void sandybridge_update_wm(struct drm_device *dev)
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4524 int fbc_wm, plane_wm, cursor_wm;
4525 unsigned int enabled;
4528 if (g4x_compute_wm0(dev, 0,
4529 &sandybridge_display_wm_info, latency,
4530 &sandybridge_cursor_wm_info, latency,
4531 &plane_wm, &cursor_wm)) {
4532 I915_WRITE(WM0_PIPEA_ILK,
4533 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4534 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4535 " plane %d, " "cursor: %d\n",
4536 plane_wm, cursor_wm);
4540 if (g4x_compute_wm0(dev, 1,
4541 &sandybridge_display_wm_info, latency,
4542 &sandybridge_cursor_wm_info, latency,
4543 &plane_wm, &cursor_wm)) {
4544 I915_WRITE(WM0_PIPEB_ILK,
4545 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547 " plane %d, cursor: %d\n",
4548 plane_wm, cursor_wm);
4552 /* IVB has 3 pipes */
4553 if (IS_IVYBRIDGE(dev) &&
4554 g4x_compute_wm0(dev, 2,
4555 &sandybridge_display_wm_info, latency,
4556 &sandybridge_cursor_wm_info, latency,
4557 &plane_wm, &cursor_wm)) {
4558 I915_WRITE(WM0_PIPEC_IVB,
4559 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4560 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4561 " plane %d, cursor: %d\n",
4562 plane_wm, cursor_wm);
4567 * Calculate and update the self-refresh watermark only when one
4568 * display plane is used.
4570 * SNB support 3 levels of watermark.
4572 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4573 * and disabled in the descending order
4576 I915_WRITE(WM3_LP_ILK, 0);
4577 I915_WRITE(WM2_LP_ILK, 0);
4578 I915_WRITE(WM1_LP_ILK, 0);
4580 if (!single_plane_enabled(enabled) ||
4581 dev_priv->sprite_scaling_enabled)
4583 enabled = ffs(enabled) - 1;
4586 if (!ironlake_compute_srwm(dev, 1, enabled,
4587 SNB_READ_WM1_LATENCY() * 500,
4588 &sandybridge_display_srwm_info,
4589 &sandybridge_cursor_srwm_info,
4590 &fbc_wm, &plane_wm, &cursor_wm))
4593 I915_WRITE(WM1_LP_ILK,
4595 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4596 (fbc_wm << WM1_LP_FBC_SHIFT) |
4597 (plane_wm << WM1_LP_SR_SHIFT) |
4601 if (!ironlake_compute_srwm(dev, 2, enabled,
4602 SNB_READ_WM2_LATENCY() * 500,
4603 &sandybridge_display_srwm_info,
4604 &sandybridge_cursor_srwm_info,
4605 &fbc_wm, &plane_wm, &cursor_wm))
4608 I915_WRITE(WM2_LP_ILK,
4610 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4611 (fbc_wm << WM1_LP_FBC_SHIFT) |
4612 (plane_wm << WM1_LP_SR_SHIFT) |
4616 if (!ironlake_compute_srwm(dev, 3, enabled,
4617 SNB_READ_WM3_LATENCY() * 500,
4618 &sandybridge_display_srwm_info,
4619 &sandybridge_cursor_srwm_info,
4620 &fbc_wm, &plane_wm, &cursor_wm))
4623 I915_WRITE(WM3_LP_ILK,
4625 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4626 (fbc_wm << WM1_LP_FBC_SHIFT) |
4627 (plane_wm << WM1_LP_SR_SHIFT) |
4632 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4633 uint32_t sprite_width, int pixel_size,
4634 const struct intel_watermark_params *display,
4635 int display_latency_ns, int *sprite_wm)
4637 struct drm_crtc *crtc;
4639 int entries, tlb_miss;
4641 crtc = intel_get_crtc_for_plane(dev, plane);
4642 if (crtc->fb == NULL || !crtc->enabled) {
4643 *sprite_wm = display->guard_size;
4647 clock = crtc->mode.clock;
4649 /* Use the small buffer method to calculate the sprite watermark */
4650 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4651 tlb_miss = display->fifo_size*display->cacheline_size -
4654 entries += tlb_miss;
4655 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4656 *sprite_wm = entries + display->guard_size;
4657 if (*sprite_wm > (int)display->max_wm)
4658 *sprite_wm = display->max_wm;
4664 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4665 uint32_t sprite_width, int pixel_size,
4666 const struct intel_watermark_params *display,
4667 int latency_ns, int *sprite_wm)
4669 struct drm_crtc *crtc;
4670 unsigned long line_time_us;
4672 int line_count, line_size;
4681 crtc = intel_get_crtc_for_plane(dev, plane);
4682 clock = crtc->mode.clock;
4684 line_time_us = (sprite_width * 1000) / clock;
4685 line_count = (latency_ns / line_time_us + 1000) / 1000;
4686 line_size = sprite_width * pixel_size;
4688 /* Use the minimum of the small and large buffer method for primary */
4689 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4690 large = line_count * line_size;
4692 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4693 *sprite_wm = entries + display->guard_size;
4695 return *sprite_wm > 0x3ff ? false : true;
4698 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4699 uint32_t sprite_width, int pixel_size)
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4708 reg = WM0_PIPEA_ILK;
4711 reg = WM0_PIPEB_ILK;
4714 reg = WM0_PIPEC_IVB;
4717 return; /* bad pipe */
4720 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4721 &sandybridge_display_wm_info,
4722 latency, &sprite_wm);
4724 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4729 I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4730 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4733 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4735 &sandybridge_display_srwm_info,
4736 SNB_READ_WM1_LATENCY() * 500,
4739 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4743 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4745 /* Only IVB has two more LP watermarks for sprite */
4746 if (!IS_IVYBRIDGE(dev))
4749 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4751 &sandybridge_display_srwm_info,
4752 SNB_READ_WM2_LATENCY() * 500,
4755 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4759 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4761 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4763 &sandybridge_display_srwm_info,
4764 SNB_READ_WM3_LATENCY() * 500,
4767 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4771 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4775 * intel_update_watermarks - update FIFO watermark values based on current modes
4777 * Calculate watermark values for the various WM regs based on current mode
4778 * and plane configuration.
4780 * There are several cases to deal with here:
4781 * - normal (i.e. non-self-refresh)
4782 * - self-refresh (SR) mode
4783 * - lines are large relative to FIFO size (buffer can hold up to 2)
4784 * - lines are small relative to FIFO size (buffer can hold more than 2
4785 * lines), so need to account for TLB latency
4787 * The normal calculation is:
4788 * watermark = dotclock * bytes per pixel * latency
4789 * where latency is platform & configuration dependent (we assume pessimal
4792 * The SR calculation is:
4793 * watermark = (trunc(latency/line time)+1) * surface width *
4796 * line time = htotal / dotclock
4797 * surface width = hdisplay for normal plane and 64 for cursor
4798 * and latency is assumed to be high, as above.
4800 * The final value programmed to the register should always be rounded up,
4801 * and include an extra 2 entries to account for clock crossings.
4803 * We don't use the sprite, so we can ignore that. And on Crestline we have
4804 * to set the non-SR watermarks to 8.
4806 static void intel_update_watermarks(struct drm_device *dev)
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4810 if (dev_priv->display.update_wm)
4811 dev_priv->display.update_wm(dev);
4814 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4815 uint32_t sprite_width, int pixel_size)
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4819 if (dev_priv->display.update_sprite_wm)
4820 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4824 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4826 if (i915_panel_use_ssc >= 0)
4827 return i915_panel_use_ssc != 0;
4828 return dev_priv->lvds_use_ssc
4829 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4833 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4834 * @crtc: CRTC structure
4835 * @mode: requested mode
4837 * A pipe may be connected to one or more outputs. Based on the depth of the
4838 * attached framebuffer, choose a good color depth to use on the pipe.
4840 * If possible, match the pipe depth to the fb depth. In some cases, this
4841 * isn't ideal, because the connected output supports a lesser or restricted
4842 * set of depths. Resolve that here:
4843 * LVDS typically supports only 6bpc, so clamp down in that case
4844 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4845 * Displays may support a restricted set as well, check EDID and clamp as
4847 * DP may want to dither down to 6bpc to fit larger modes
4850 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4851 * true if they don't match).
4853 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4854 unsigned int *pipe_bpp,
4855 struct drm_display_mode *mode)
4857 struct drm_device *dev = crtc->dev;
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 struct drm_encoder *encoder;
4860 struct drm_connector *connector;
4861 unsigned int display_bpc = UINT_MAX, bpc;
4863 /* Walk the encoders & connectors on this crtc, get min bpc */
4864 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4865 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4867 if (encoder->crtc != crtc)
4870 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4871 unsigned int lvds_bpc;
4873 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4879 if (lvds_bpc < display_bpc) {
4880 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4881 display_bpc = lvds_bpc;
4886 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4887 /* Use VBT settings if we have an eDP panel */
4888 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4890 if (edp_bpc < display_bpc) {
4891 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4892 display_bpc = edp_bpc;
4897 /* Not one of the known troublemakers, check the EDID */
4898 list_for_each_entry(connector, &dev->mode_config.connector_list,
4900 if (connector->encoder != encoder)
4903 /* Don't use an invalid EDID bpc value */
4904 if (connector->display_info.bpc &&
4905 connector->display_info.bpc < display_bpc) {
4906 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4907 display_bpc = connector->display_info.bpc;
4912 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4913 * through, clamp it down. (Note: >12bpc will be caught below.)
4915 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4916 if (display_bpc > 8 && display_bpc < 12) {
4917 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4920 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4926 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4927 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4932 * We could just drive the pipe at the highest bpc all the time and
4933 * enable dithering as needed, but that costs bandwidth. So choose
4934 * the minimum value that expresses the full color range of the fb but
4935 * also stays within the max display bpc discovered above.
4938 switch (crtc->fb->depth) {
4940 bpc = 8; /* since we go through a colormap */
4944 bpc = 6; /* min is 18bpp */
4956 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4957 bpc = min((unsigned int)8, display_bpc);
4961 display_bpc = min(display_bpc, bpc);
4963 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4966 *pipe_bpp = display_bpc * 3;
4968 return display_bpc != bpc;
4971 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4972 struct drm_display_mode *mode,
4973 struct drm_display_mode *adjusted_mode,
4975 struct drm_framebuffer *old_fb)
4977 struct drm_device *dev = crtc->dev;
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980 int pipe = intel_crtc->pipe;
4981 int plane = intel_crtc->plane;
4982 int refclk, num_connectors = 0;
4983 intel_clock_t clock, reduced_clock;
4984 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4985 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4986 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4987 struct drm_mode_config *mode_config = &dev->mode_config;
4988 struct intel_encoder *encoder;
4989 const intel_limit_t *limit;
4994 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4995 if (encoder->base.crtc != crtc)
4998 switch (encoder->type) {
4999 case INTEL_OUTPUT_LVDS:
5002 case INTEL_OUTPUT_SDVO:
5003 case INTEL_OUTPUT_HDMI:
5005 if (encoder->needs_tv_clock)
5008 case INTEL_OUTPUT_DVO:
5011 case INTEL_OUTPUT_TVOUT:
5014 case INTEL_OUTPUT_ANALOG:
5017 case INTEL_OUTPUT_DISPLAYPORT:
5025 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5026 refclk = dev_priv->lvds_ssc_freq * 1000;
5027 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5029 } else if (!IS_GEN2(dev)) {
5036 * Returns a set of divisors for the desired target clock with the given
5037 * refclk, or FALSE. The returned values represent the clock equation:
5038 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5040 limit = intel_limit(crtc, refclk);
5041 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5043 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5047 /* Ensure that the cursor is valid for the new mode before changing... */
5048 intel_crtc_update_cursor(crtc, true);
5050 if (is_lvds && dev_priv->lvds_downclock_avail) {
5051 has_reduced_clock = limit->find_pll(limit, crtc,
5052 dev_priv->lvds_downclock,
5055 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5057 * If the different P is found, it means that we can't
5058 * switch the display clock by using the FP0/FP1.
5059 * In such case we will disable the LVDS downclock
5062 DRM_DEBUG_KMS("Different P is found for "
5063 "LVDS clock/downclock\n");
5064 has_reduced_clock = 0;
5067 /* SDVO TV has fixed PLL values depend on its clock range,
5068 this mirrors vbios setting. */
5069 if (is_sdvo && is_tv) {
5070 if (adjusted_mode->clock >= 100000
5071 && adjusted_mode->clock < 140500) {
5077 } else if (adjusted_mode->clock >= 140500
5078 && adjusted_mode->clock <= 200000) {
5087 if (IS_PINEVIEW(dev)) {
5088 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
5089 if (has_reduced_clock)
5090 fp2 = (1 << reduced_clock.n) << 16 |
5091 reduced_clock.m1 << 8 | reduced_clock.m2;
5093 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5094 if (has_reduced_clock)
5095 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5099 dpll = DPLL_VGA_MODE_DIS;
5101 if (!IS_GEN2(dev)) {
5103 dpll |= DPLLB_MODE_LVDS;
5105 dpll |= DPLLB_MODE_DAC_SERIAL;
5107 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5108 if (pixel_multiplier > 1) {
5109 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5110 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5112 dpll |= DPLL_DVO_HIGH_SPEED;
5115 dpll |= DPLL_DVO_HIGH_SPEED;
5117 /* compute bitmask from p1 value */
5118 if (IS_PINEVIEW(dev))
5119 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5121 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5122 if (IS_G4X(dev) && has_reduced_clock)
5123 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5127 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5130 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5133 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5136 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5139 if (INTEL_INFO(dev)->gen >= 4)
5140 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5143 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5146 dpll |= PLL_P1_DIVIDE_BY_TWO;
5148 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5150 dpll |= PLL_P2_DIVIDE_BY_4;
5154 if (is_sdvo && is_tv)
5155 dpll |= PLL_REF_INPUT_TVCLKINBC;
5157 /* XXX: just matching BIOS for now */
5158 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5160 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5161 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5163 dpll |= PLL_REF_INPUT_DREFCLK;
5165 /* setup pipeconf */
5166 pipeconf = I915_READ(PIPECONF(pipe));
5168 /* Set up the display plane register */
5169 dspcntr = DISPPLANE_GAMMA_ENABLE;
5171 /* Ironlake's plane is forced to pipe, bit 24 is to
5172 enable color space conversion */
5174 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5176 dspcntr |= DISPPLANE_SEL_PIPE_B;
5178 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5179 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5182 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5186 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5187 pipeconf |= PIPECONF_DOUBLE_WIDE;
5189 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5192 /* default to 8bpc */
5193 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5195 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5196 pipeconf |= PIPECONF_BPP_6 |
5197 PIPECONF_DITHER_EN |
5198 PIPECONF_DITHER_TYPE_SP;
5202 dpll |= DPLL_VCO_ENABLE;
5204 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5205 drm_mode_debug_printmodeline(mode);
5207 I915_WRITE(FP0(pipe), fp);
5208 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5210 POSTING_READ(DPLL(pipe));
5213 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5214 * This is an exception to the general rule that mode_set doesn't turn
5218 temp = I915_READ(LVDS);
5219 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5221 temp |= LVDS_PIPEB_SELECT;
5223 temp &= ~LVDS_PIPEB_SELECT;
5225 /* set the corresponsding LVDS_BORDER bit */
5226 temp |= dev_priv->lvds_border_bits;
5227 /* Set the B0-B3 data pairs corresponding to whether we're going to
5228 * set the DPLLs for dual-channel mode or not.
5231 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5233 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5235 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5236 * appropriately here, but we need to look more thoroughly into how
5237 * panels behave in the two modes.
5239 /* set the dithering flag on LVDS as needed */
5240 if (INTEL_INFO(dev)->gen >= 4) {
5241 if (dev_priv->lvds_dither)
5242 temp |= LVDS_ENABLE_DITHER;
5244 temp &= ~LVDS_ENABLE_DITHER;
5246 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5247 lvds_sync |= LVDS_HSYNC_POLARITY;
5248 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5249 lvds_sync |= LVDS_VSYNC_POLARITY;
5250 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5252 char flags[2] = "-+";
5253 DRM_INFO("Changing LVDS panel from "
5254 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5255 flags[!(temp & LVDS_HSYNC_POLARITY)],
5256 flags[!(temp & LVDS_VSYNC_POLARITY)],
5257 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5258 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5259 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5262 I915_WRITE(LVDS, temp);
5266 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5269 I915_WRITE(DPLL(pipe), dpll);
5271 /* Wait for the clocks to stabilize. */
5272 POSTING_READ(DPLL(pipe));
5275 if (INTEL_INFO(dev)->gen >= 4) {
5278 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5280 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5284 I915_WRITE(DPLL_MD(pipe), temp);
5286 /* The pixel multiplier can only be updated once the
5287 * DPLL is enabled and the clocks are stable.
5289 * So write it again.
5291 I915_WRITE(DPLL(pipe), dpll);
5294 intel_crtc->lowfreq_avail = false;
5295 if (is_lvds && has_reduced_clock && i915_powersave) {
5296 I915_WRITE(FP1(pipe), fp2);
5297 intel_crtc->lowfreq_avail = true;
5298 if (HAS_PIPE_CXSR(dev)) {
5299 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5300 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5303 I915_WRITE(FP1(pipe), fp);
5304 if (HAS_PIPE_CXSR(dev)) {
5305 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5306 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5310 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5311 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5312 /* the chip adds 2 halflines automatically */
5313 adjusted_mode->crtc_vdisplay -= 1;
5314 adjusted_mode->crtc_vtotal -= 1;
5315 adjusted_mode->crtc_vblank_start -= 1;
5316 adjusted_mode->crtc_vblank_end -= 1;
5317 adjusted_mode->crtc_vsync_end -= 1;
5318 adjusted_mode->crtc_vsync_start -= 1;
5320 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
5322 I915_WRITE(HTOTAL(pipe),
5323 (adjusted_mode->crtc_hdisplay - 1) |
5324 ((adjusted_mode->crtc_htotal - 1) << 16));
5325 I915_WRITE(HBLANK(pipe),
5326 (adjusted_mode->crtc_hblank_start - 1) |
5327 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5328 I915_WRITE(HSYNC(pipe),
5329 (adjusted_mode->crtc_hsync_start - 1) |
5330 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5332 I915_WRITE(VTOTAL(pipe),
5333 (adjusted_mode->crtc_vdisplay - 1) |
5334 ((adjusted_mode->crtc_vtotal - 1) << 16));
5335 I915_WRITE(VBLANK(pipe),
5336 (adjusted_mode->crtc_vblank_start - 1) |
5337 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5338 I915_WRITE(VSYNC(pipe),
5339 (adjusted_mode->crtc_vsync_start - 1) |
5340 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5342 /* pipesrc and dspsize control the size that is scaled from,
5343 * which should always be the user's requested size.
5345 I915_WRITE(DSPSIZE(plane),
5346 ((mode->vdisplay - 1) << 16) |
5347 (mode->hdisplay - 1));
5348 I915_WRITE(DSPPOS(plane), 0);
5349 I915_WRITE(PIPESRC(pipe),
5350 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5352 I915_WRITE(PIPECONF(pipe), pipeconf);
5353 POSTING_READ(PIPECONF(pipe));
5354 intel_enable_pipe(dev_priv, pipe, false);
5356 intel_wait_for_vblank(dev, pipe);
5358 I915_WRITE(DSPCNTR(plane), dspcntr);
5359 POSTING_READ(DSPCNTR(plane));
5360 intel_enable_plane(dev_priv, plane, pipe);
5362 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5364 intel_update_watermarks(dev);
5370 * Initialize reference clocks when the driver loads
5372 void ironlake_init_pch_refclk(struct drm_device *dev)
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct drm_mode_config *mode_config = &dev->mode_config;
5376 struct intel_encoder *encoder;
5378 bool has_lvds = false;
5379 bool has_cpu_edp = false;
5380 bool has_pch_edp = false;
5381 bool has_panel = false;
5382 bool has_ck505 = false;
5383 bool can_ssc = false;
5385 /* We need to take the global config into account */
5386 list_for_each_entry(encoder, &mode_config->encoder_list,
5388 switch (encoder->type) {
5389 case INTEL_OUTPUT_LVDS:
5393 case INTEL_OUTPUT_EDP:
5395 if (intel_encoder_is_pch_edp(&encoder->base))
5403 if (HAS_PCH_IBX(dev)) {
5404 has_ck505 = dev_priv->display_clock_mode;
5405 can_ssc = has_ck505;
5411 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5412 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5415 /* Ironlake: try to setup display ref clock before DPLL
5416 * enabling. This is only under driver's control after
5417 * PCH B stepping, previous chipset stepping should be
5418 * ignoring this setting.
5420 temp = I915_READ(PCH_DREF_CONTROL);
5421 /* Always enable nonspread source */
5422 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5425 temp |= DREF_NONSPREAD_CK505_ENABLE;
5427 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5430 temp &= ~DREF_SSC_SOURCE_MASK;
5431 temp |= DREF_SSC_SOURCE_ENABLE;
5433 /* SSC must be turned on before enabling the CPU output */
5434 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5435 DRM_DEBUG_KMS("Using SSC on panel\n");
5436 temp |= DREF_SSC1_ENABLE;
5439 /* Get SSC going before enabling the outputs */
5440 I915_WRITE(PCH_DREF_CONTROL, temp);
5441 POSTING_READ(PCH_DREF_CONTROL);
5444 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5446 /* Enable CPU source on CPU attached eDP */
5448 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5449 DRM_DEBUG_KMS("Using SSC on eDP\n");
5450 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5453 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5455 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5457 I915_WRITE(PCH_DREF_CONTROL, temp);
5458 POSTING_READ(PCH_DREF_CONTROL);
5461 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5463 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5465 /* Turn off CPU output */
5466 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5468 I915_WRITE(PCH_DREF_CONTROL, temp);
5469 POSTING_READ(PCH_DREF_CONTROL);
5472 /* Turn off the SSC source */
5473 temp &= ~DREF_SSC_SOURCE_MASK;
5474 temp |= DREF_SSC_SOURCE_DISABLE;
5477 temp &= ~ DREF_SSC1_ENABLE;
5479 I915_WRITE(PCH_DREF_CONTROL, temp);
5480 POSTING_READ(PCH_DREF_CONTROL);
5485 static int ironlake_get_refclk(struct drm_crtc *crtc)
5487 struct drm_device *dev = crtc->dev;
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 struct intel_encoder *encoder;
5490 struct drm_mode_config *mode_config = &dev->mode_config;
5491 struct intel_encoder *edp_encoder = NULL;
5492 int num_connectors = 0;
5493 bool is_lvds = false;
5495 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5496 if (encoder->base.crtc != crtc)
5499 switch (encoder->type) {
5500 case INTEL_OUTPUT_LVDS:
5503 case INTEL_OUTPUT_EDP:
5504 edp_encoder = encoder;
5510 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5511 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5512 dev_priv->lvds_ssc_freq);
5513 return dev_priv->lvds_ssc_freq * 1000;
5519 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5520 struct drm_display_mode *mode,
5521 struct drm_display_mode *adjusted_mode,
5523 struct drm_framebuffer *old_fb)
5525 struct drm_device *dev = crtc->dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5528 int pipe = intel_crtc->pipe;
5529 int plane = intel_crtc->plane;
5530 int refclk, num_connectors = 0;
5531 intel_clock_t clock, reduced_clock;
5532 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5533 bool ok, has_reduced_clock = false, is_sdvo = false;
5534 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5535 struct intel_encoder *has_edp_encoder = NULL;
5536 struct drm_mode_config *mode_config = &dev->mode_config;
5537 struct intel_encoder *encoder;
5538 const intel_limit_t *limit;
5540 struct fdi_m_n m_n = {0};
5543 int target_clock, pixel_multiplier, lane, link_bw, factor;
5544 unsigned int pipe_bpp;
5547 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5548 if (encoder->base.crtc != crtc)
5551 switch (encoder->type) {
5552 case INTEL_OUTPUT_LVDS:
5555 case INTEL_OUTPUT_SDVO:
5556 case INTEL_OUTPUT_HDMI:
5558 if (encoder->needs_tv_clock)
5561 case INTEL_OUTPUT_TVOUT:
5564 case INTEL_OUTPUT_ANALOG:
5567 case INTEL_OUTPUT_DISPLAYPORT:
5570 case INTEL_OUTPUT_EDP:
5571 has_edp_encoder = encoder;
5578 refclk = ironlake_get_refclk(crtc);
5581 * Returns a set of divisors for the desired target clock with the given
5582 * refclk, or FALSE. The returned values represent the clock equation:
5583 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5585 limit = intel_limit(crtc, refclk);
5586 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5588 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5592 /* Ensure that the cursor is valid for the new mode before changing... */
5593 intel_crtc_update_cursor(crtc, true);
5595 if (is_lvds && dev_priv->lvds_downclock_avail) {
5596 has_reduced_clock = limit->find_pll(limit, crtc,
5597 dev_priv->lvds_downclock,
5600 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5602 * If the different P is found, it means that we can't
5603 * switch the display clock by using the FP0/FP1.
5604 * In such case we will disable the LVDS downclock
5607 DRM_DEBUG_KMS("Different P is found for "
5608 "LVDS clock/downclock\n");
5609 has_reduced_clock = 0;
5612 /* SDVO TV has fixed PLL values depend on its clock range,
5613 this mirrors vbios setting. */
5614 if (is_sdvo && is_tv) {
5615 if (adjusted_mode->clock >= 100000
5616 && adjusted_mode->clock < 140500) {
5622 } else if (adjusted_mode->clock >= 140500
5623 && adjusted_mode->clock <= 200000) {
5633 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5635 /* CPU eDP doesn't require FDI link, so just set DP M/N
5636 according to current link config */
5637 if (has_edp_encoder &&
5638 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5639 target_clock = mode->clock;
5640 intel_edp_link_config(has_edp_encoder,
5643 /* [e]DP over FDI requires target mode clock
5644 instead of link clock */
5645 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5646 target_clock = mode->clock;
5648 target_clock = adjusted_mode->clock;
5650 /* FDI is a binary signal running at ~2.7GHz, encoding
5651 * each output octet as 10 bits. The actual frequency
5652 * is stored as a divider into a 100MHz clock, and the
5653 * mode pixel clock is stored in units of 1KHz.
5654 * Hence the bw of each lane in terms of the mode signal
5657 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5660 /* determine panel color depth */
5661 temp = I915_READ(PIPECONF(pipe));
5662 temp &= ~PIPE_BPC_MASK;
5663 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5678 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5685 intel_crtc->bpp = pipe_bpp;
5686 I915_WRITE(PIPECONF(pipe), temp);
5690 * Account for spread spectrum to avoid
5691 * oversubscribing the link. Max center spread
5692 * is 2.5%; use 5% for safety's sake.
5694 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5695 lane = bps / (link_bw * 8) + 1;
5698 intel_crtc->fdi_lanes = lane;
5700 if (pixel_multiplier > 1)
5701 link_bw *= pixel_multiplier;
5702 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5705 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5706 if (has_reduced_clock)
5707 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5710 /* Enable autotuning of the PLL clock (if permissible) */
5713 if ((intel_panel_use_ssc(dev_priv) &&
5714 dev_priv->lvds_ssc_freq == 100) ||
5715 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5717 } else if (is_sdvo && is_tv)
5720 if (clock.m < factor * clock.n)
5726 dpll |= DPLLB_MODE_LVDS;
5728 dpll |= DPLLB_MODE_DAC_SERIAL;
5730 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5731 if (pixel_multiplier > 1) {
5732 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5734 dpll |= DPLL_DVO_HIGH_SPEED;
5736 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5737 dpll |= DPLL_DVO_HIGH_SPEED;
5739 /* compute bitmask from p1 value */
5740 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5742 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5746 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5749 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5752 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5755 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5759 if (is_sdvo && is_tv)
5760 dpll |= PLL_REF_INPUT_TVCLKINBC;
5762 /* XXX: just matching BIOS for now */
5763 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5765 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5766 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5768 dpll |= PLL_REF_INPUT_DREFCLK;
5770 /* setup pipeconf */
5771 pipeconf = I915_READ(PIPECONF(pipe));
5773 /* Set up the display plane register */
5774 dspcntr = DISPPLANE_GAMMA_ENABLE;
5776 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5777 drm_mode_debug_printmodeline(mode);
5779 /* PCH eDP needs FDI, but CPU eDP does not */
5780 if (!intel_crtc->no_pll) {
5781 if (!has_edp_encoder ||
5782 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5783 I915_WRITE(PCH_FP0(pipe), fp);
5784 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5786 POSTING_READ(PCH_DPLL(pipe));
5790 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5791 fp == I915_READ(PCH_FP0(0))) {
5792 intel_crtc->use_pll_a = true;
5793 DRM_DEBUG_KMS("using pipe a dpll\n");
5794 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5795 fp == I915_READ(PCH_FP0(1))) {
5796 intel_crtc->use_pll_a = false;
5797 DRM_DEBUG_KMS("using pipe b dpll\n");
5799 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5804 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5805 * This is an exception to the general rule that mode_set doesn't turn
5809 temp = I915_READ(PCH_LVDS);
5810 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5811 if (HAS_PCH_CPT(dev)) {
5812 temp &= ~PORT_TRANS_SEL_MASK;
5813 temp |= PORT_TRANS_SEL_CPT(pipe);
5816 temp |= LVDS_PIPEB_SELECT;
5818 temp &= ~LVDS_PIPEB_SELECT;
5821 /* set the corresponsding LVDS_BORDER bit */
5822 temp |= dev_priv->lvds_border_bits;
5823 /* Set the B0-B3 data pairs corresponding to whether we're going to
5824 * set the DPLLs for dual-channel mode or not.
5827 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5829 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5831 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5832 * appropriately here, but we need to look more thoroughly into how
5833 * panels behave in the two modes.
5835 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5836 lvds_sync |= LVDS_HSYNC_POLARITY;
5837 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5838 lvds_sync |= LVDS_VSYNC_POLARITY;
5839 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5841 char flags[2] = "-+";
5842 DRM_INFO("Changing LVDS panel from "
5843 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5844 flags[!(temp & LVDS_HSYNC_POLARITY)],
5845 flags[!(temp & LVDS_VSYNC_POLARITY)],
5846 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5847 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5848 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5851 I915_WRITE(PCH_LVDS, temp);
5854 pipeconf &= ~PIPECONF_DITHER_EN;
5855 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5856 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5857 pipeconf |= PIPECONF_DITHER_EN;
5858 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5860 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5861 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5863 /* For non-DP output, clear any trans DP clock recovery setting.*/
5864 I915_WRITE(TRANSDATA_M1(pipe), 0);
5865 I915_WRITE(TRANSDATA_N1(pipe), 0);
5866 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5867 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5870 if (!intel_crtc->no_pll &&
5871 (!has_edp_encoder ||
5872 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5873 I915_WRITE(PCH_DPLL(pipe), dpll);
5875 /* Wait for the clocks to stabilize. */
5876 POSTING_READ(PCH_DPLL(pipe));
5879 /* The pixel multiplier can only be updated once the
5880 * DPLL is enabled and the clocks are stable.
5882 * So write it again.
5884 I915_WRITE(PCH_DPLL(pipe), dpll);
5887 intel_crtc->lowfreq_avail = false;
5888 if (!intel_crtc->no_pll) {
5889 if (is_lvds && has_reduced_clock && i915_powersave) {
5890 I915_WRITE(PCH_FP1(pipe), fp2);
5891 intel_crtc->lowfreq_avail = true;
5892 if (HAS_PIPE_CXSR(dev)) {
5893 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5894 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5897 I915_WRITE(PCH_FP1(pipe), fp);
5898 if (HAS_PIPE_CXSR(dev)) {
5899 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5900 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5905 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5906 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5907 /* the chip adds 2 halflines automatically */
5908 adjusted_mode->crtc_vdisplay -= 1;
5909 adjusted_mode->crtc_vtotal -= 1;
5910 adjusted_mode->crtc_vblank_start -= 1;
5911 adjusted_mode->crtc_vblank_end -= 1;
5912 adjusted_mode->crtc_vsync_end -= 1;
5913 adjusted_mode->crtc_vsync_start -= 1;
5915 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5917 I915_WRITE(HTOTAL(pipe),
5918 (adjusted_mode->crtc_hdisplay - 1) |
5919 ((adjusted_mode->crtc_htotal - 1) << 16));
5920 I915_WRITE(HBLANK(pipe),
5921 (adjusted_mode->crtc_hblank_start - 1) |
5922 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5923 I915_WRITE(HSYNC(pipe),
5924 (adjusted_mode->crtc_hsync_start - 1) |
5925 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5927 I915_WRITE(VTOTAL(pipe),
5928 (adjusted_mode->crtc_vdisplay - 1) |
5929 ((adjusted_mode->crtc_vtotal - 1) << 16));
5930 I915_WRITE(VBLANK(pipe),
5931 (adjusted_mode->crtc_vblank_start - 1) |
5932 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5933 I915_WRITE(VSYNC(pipe),
5934 (adjusted_mode->crtc_vsync_start - 1) |
5935 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5937 /* pipesrc controls the size that is scaled from, which should
5938 * always be the user's requested size.
5940 I915_WRITE(PIPESRC(pipe),
5941 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5943 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5944 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5945 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5946 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5948 if (has_edp_encoder &&
5949 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5950 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5953 I915_WRITE(PIPECONF(pipe), pipeconf);
5954 POSTING_READ(PIPECONF(pipe));
5956 intel_wait_for_vblank(dev, pipe);
5959 /* enable address swizzle for tiling buffer */
5960 temp = I915_READ(DISP_ARB_CTL);
5961 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5964 I915_WRITE(DSPCNTR(plane), dspcntr);
5965 POSTING_READ(DSPCNTR(plane));
5967 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5969 intel_update_watermarks(dev);
5974 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5975 struct drm_display_mode *mode,
5976 struct drm_display_mode *adjusted_mode,
5978 struct drm_framebuffer *old_fb)
5980 struct drm_device *dev = crtc->dev;
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5983 int pipe = intel_crtc->pipe;
5986 drm_vblank_pre_modeset(dev, pipe);
5988 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5990 drm_vblank_post_modeset(dev, pipe);
5993 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5995 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6000 static bool intel_eld_uptodate(struct drm_connector *connector,
6001 int reg_eldv, uint32_t bits_eldv,
6002 int reg_elda, uint32_t bits_elda,
6005 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6006 uint8_t *eld = connector->eld;
6009 i = I915_READ(reg_eldv);
6018 i = I915_READ(reg_elda);
6020 I915_WRITE(reg_elda, i);
6022 for (i = 0; i < eld[2]; i++)
6023 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6029 static void g4x_write_eld(struct drm_connector *connector,
6030 struct drm_crtc *crtc)
6032 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6033 uint8_t *eld = connector->eld;
6038 i = I915_READ(G4X_AUD_VID_DID);
6040 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6041 eldv = G4X_ELDV_DEVCL_DEVBLC;
6043 eldv = G4X_ELDV_DEVCTG;
6045 if (intel_eld_uptodate(connector,
6046 G4X_AUD_CNTL_ST, eldv,
6047 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6048 G4X_HDMIW_HDMIEDID))
6051 i = I915_READ(G4X_AUD_CNTL_ST);
6052 i &= ~(eldv | G4X_ELD_ADDR);
6053 len = (i >> 9) & 0x1f; /* ELD buffer size */
6054 I915_WRITE(G4X_AUD_CNTL_ST, i);
6059 len = min_t(uint8_t, eld[2], len);
6060 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6061 for (i = 0; i < len; i++)
6062 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6064 i = I915_READ(G4X_AUD_CNTL_ST);
6066 I915_WRITE(G4X_AUD_CNTL_ST, i);
6069 static void ironlake_write_eld(struct drm_connector *connector,
6070 struct drm_crtc *crtc)
6072 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6073 uint8_t *eld = connector->eld;
6081 if (HAS_PCH_IBX(connector->dev)) {
6082 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6083 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6084 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6086 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6087 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6088 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6091 i = to_intel_crtc(crtc)->pipe;
6092 hdmiw_hdmiedid += i * 0x100;
6093 aud_cntl_st += i * 0x100;
6095 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6097 i = I915_READ(aud_cntl_st);
6098 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6100 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6101 /* operate blindly on all ports */
6102 eldv = IBX_ELD_VALIDB;
6103 eldv |= IBX_ELD_VALIDB << 4;
6104 eldv |= IBX_ELD_VALIDB << 8;
6106 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6107 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6111 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6112 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6115 if (intel_eld_uptodate(connector,
6116 aud_cntrl_st2, eldv,
6117 aud_cntl_st, IBX_ELD_ADDRESS,
6121 i = I915_READ(aud_cntrl_st2);
6123 I915_WRITE(aud_cntrl_st2, i);
6128 i = I915_READ(aud_cntl_st);
6129 i &= ~IBX_ELD_ADDRESS;
6130 I915_WRITE(aud_cntl_st, i);
6132 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6133 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6134 for (i = 0; i < len; i++)
6135 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6137 i = I915_READ(aud_cntrl_st2);
6139 I915_WRITE(aud_cntrl_st2, i);
6142 void intel_write_eld(struct drm_encoder *encoder,
6143 struct drm_display_mode *mode)
6145 struct drm_crtc *crtc = encoder->crtc;
6146 struct drm_connector *connector;
6147 struct drm_device *dev = encoder->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6150 connector = drm_select_eld(encoder, mode);
6154 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6156 drm_get_connector_name(connector),
6157 connector->encoder->base.id,
6158 drm_get_encoder_name(connector->encoder));
6160 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6162 if (dev_priv->display.write_eld)
6163 dev_priv->display.write_eld(connector, crtc);
6166 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6167 void intel_crtc_load_lut(struct drm_crtc *crtc)
6169 struct drm_device *dev = crtc->dev;
6170 struct drm_i915_private *dev_priv = dev->dev_private;
6171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6172 int palreg = PALETTE(intel_crtc->pipe);
6175 /* The clocks have to be on to load the palette. */
6179 /* use legacy palette for Ironlake */
6180 if (HAS_PCH_SPLIT(dev))
6181 palreg = LGC_PALETTE(intel_crtc->pipe);
6183 for (i = 0; i < 256; i++) {
6184 I915_WRITE(palreg + 4 * i,
6185 (intel_crtc->lut_r[i] << 16) |
6186 (intel_crtc->lut_g[i] << 8) |
6187 intel_crtc->lut_b[i]);
6191 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6193 struct drm_device *dev = crtc->dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 bool visible = base != 0;
6199 if (intel_crtc->cursor_visible == visible)
6202 cntl = I915_READ(_CURACNTR);
6204 /* On these chipsets we can only modify the base whilst
6205 * the cursor is disabled.
6207 I915_WRITE(_CURABASE, base);
6209 cntl &= ~(CURSOR_FORMAT_MASK);
6210 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6211 cntl |= CURSOR_ENABLE |
6212 CURSOR_GAMMA_ENABLE |
6215 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6216 I915_WRITE(_CURACNTR, cntl);
6218 intel_crtc->cursor_visible = visible;
6221 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6223 struct drm_device *dev = crtc->dev;
6224 struct drm_i915_private *dev_priv = dev->dev_private;
6225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226 int pipe = intel_crtc->pipe;
6227 bool visible = base != 0;
6229 if (intel_crtc->cursor_visible != visible) {
6230 uint32_t cntl = I915_READ(CURCNTR(pipe));
6232 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6233 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6234 cntl |= pipe << 28; /* Connect to correct pipe */
6236 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6237 cntl |= CURSOR_MODE_DISABLE;
6239 I915_WRITE(CURCNTR(pipe), cntl);
6241 intel_crtc->cursor_visible = visible;
6243 /* and commit changes on next vblank */
6244 I915_WRITE(CURBASE(pipe), base);
6247 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6249 struct drm_device *dev = crtc->dev;
6250 struct drm_i915_private *dev_priv = dev->dev_private;
6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252 int pipe = intel_crtc->pipe;
6253 bool visible = base != 0;
6255 if (intel_crtc->cursor_visible != visible) {
6256 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6258 cntl &= ~CURSOR_MODE;
6259 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6261 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6262 cntl |= CURSOR_MODE_DISABLE;
6264 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6266 intel_crtc->cursor_visible = visible;
6268 /* and commit changes on next vblank */
6269 I915_WRITE(CURBASE_IVB(pipe), base);
6272 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6273 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6276 struct drm_device *dev = crtc->dev;
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279 int pipe = intel_crtc->pipe;
6280 int x = intel_crtc->cursor_x;
6281 int y = intel_crtc->cursor_y;
6287 if (on && crtc->enabled && crtc->fb) {
6288 base = intel_crtc->cursor_addr;
6289 if (x > (int) crtc->fb->width)
6292 if (y > (int) crtc->fb->height)
6298 if (x + intel_crtc->cursor_width < 0)
6301 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6304 pos |= x << CURSOR_X_SHIFT;
6307 if (y + intel_crtc->cursor_height < 0)
6310 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6313 pos |= y << CURSOR_Y_SHIFT;
6315 visible = base != 0;
6316 if (!visible && !intel_crtc->cursor_visible)
6319 if (IS_IVYBRIDGE(dev)) {
6320 I915_WRITE(CURPOS_IVB(pipe), pos);
6321 ivb_update_cursor(crtc, base);
6323 I915_WRITE(CURPOS(pipe), pos);
6324 if (IS_845G(dev) || IS_I865G(dev))
6325 i845_update_cursor(crtc, base);
6327 i9xx_update_cursor(crtc, base);
6331 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6334 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6335 struct drm_file *file,
6337 uint32_t width, uint32_t height)
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342 struct drm_i915_gem_object *obj;
6346 DRM_DEBUG_KMS("\n");
6348 /* if we want to turn off the cursor ignore width and height */
6350 DRM_DEBUG_KMS("cursor off\n");
6353 mutex_lock(&dev->struct_mutex);
6357 /* Currently we only support 64x64 cursors */
6358 if (width != 64 || height != 64) {
6359 DRM_ERROR("we currently only support 64x64 cursors\n");
6363 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6364 if (&obj->base == NULL)
6367 if (obj->base.size < width * height * 4) {
6368 DRM_ERROR("buffer is to small\n");
6373 /* we only need to pin inside GTT if cursor is non-phy */
6374 mutex_lock(&dev->struct_mutex);
6375 if (!dev_priv->info->cursor_needs_physical) {
6376 if (obj->tiling_mode) {
6377 DRM_ERROR("cursor cannot be tiled\n");
6382 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6384 DRM_ERROR("failed to move cursor bo into the GTT\n");
6388 ret = i915_gem_object_put_fence(obj);
6390 DRM_ERROR("failed to release fence for cursor");
6394 addr = obj->gtt_offset;
6396 int align = IS_I830(dev) ? 16 * 1024 : 256;
6397 ret = i915_gem_attach_phys_object(dev, obj,
6398 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6401 DRM_ERROR("failed to attach phys object\n");
6404 addr = obj->phys_obj->handle->busaddr;
6408 I915_WRITE(CURSIZE, (height << 12) | width);
6411 if (intel_crtc->cursor_bo) {
6412 if (dev_priv->info->cursor_needs_physical) {
6413 if (intel_crtc->cursor_bo != obj)
6414 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6416 i915_gem_object_unpin(intel_crtc->cursor_bo);
6417 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6420 mutex_unlock(&dev->struct_mutex);
6422 intel_crtc->cursor_addr = addr;
6423 intel_crtc->cursor_bo = obj;
6424 intel_crtc->cursor_width = width;
6425 intel_crtc->cursor_height = height;
6427 intel_crtc_update_cursor(crtc, true);
6431 i915_gem_object_unpin(obj);
6433 mutex_unlock(&dev->struct_mutex);
6435 drm_gem_object_unreference_unlocked(&obj->base);
6439 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6443 intel_crtc->cursor_x = x;
6444 intel_crtc->cursor_y = y;
6446 intel_crtc_update_cursor(crtc, true);
6451 /** Sets the color ramps on behalf of RandR */
6452 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6453 u16 blue, int regno)
6455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6457 intel_crtc->lut_r[regno] = red >> 8;
6458 intel_crtc->lut_g[regno] = green >> 8;
6459 intel_crtc->lut_b[regno] = blue >> 8;
6462 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6463 u16 *blue, int regno)
6465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6467 *red = intel_crtc->lut_r[regno] << 8;
6468 *green = intel_crtc->lut_g[regno] << 8;
6469 *blue = intel_crtc->lut_b[regno] << 8;
6472 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6473 u16 *blue, uint32_t start, uint32_t size)
6475 int end = (start + size > 256) ? 256 : start + size, i;
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6478 for (i = start; i < end; i++) {
6479 intel_crtc->lut_r[i] = red[i] >> 8;
6480 intel_crtc->lut_g[i] = green[i] >> 8;
6481 intel_crtc->lut_b[i] = blue[i] >> 8;
6484 intel_crtc_load_lut(crtc);
6488 * Get a pipe with a simple mode set on it for doing load-based monitor
6491 * It will be up to the load-detect code to adjust the pipe as appropriate for
6492 * its requirements. The pipe will be connected to no other encoders.
6494 * Currently this code will only succeed if there is a pipe with no encoders
6495 * configured for it. In the future, it could choose to temporarily disable
6496 * some outputs to free up a pipe for its use.
6498 * \return crtc, or NULL if no pipes are available.
6501 /* VESA 640x480x72Hz mode to set on the pipe */
6502 static struct drm_display_mode load_detect_mode = {
6503 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6504 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6507 static struct drm_framebuffer *
6508 intel_framebuffer_create(struct drm_device *dev,
6509 struct drm_mode_fb_cmd2 *mode_cmd,
6510 struct drm_i915_gem_object *obj)
6512 struct intel_framebuffer *intel_fb;
6515 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6517 drm_gem_object_unreference_unlocked(&obj->base);
6518 return ERR_PTR(-ENOMEM);
6521 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6523 drm_gem_object_unreference_unlocked(&obj->base);
6525 return ERR_PTR(ret);
6528 return &intel_fb->base;
6532 intel_framebuffer_pitch_for_width(int width, int bpp)
6534 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6535 return ALIGN(pitch, 64);
6539 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6541 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6542 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6545 static struct drm_framebuffer *
6546 intel_framebuffer_create_for_mode(struct drm_device *dev,
6547 struct drm_display_mode *mode,
6550 struct drm_i915_gem_object *obj;
6551 struct drm_mode_fb_cmd2 mode_cmd;
6553 obj = i915_gem_alloc_object(dev,
6554 intel_framebuffer_size_for_mode(mode, bpp));
6556 return ERR_PTR(-ENOMEM);
6558 mode_cmd.width = mode->hdisplay;
6559 mode_cmd.height = mode->vdisplay;
6560 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6562 mode_cmd.pixel_format = 0;
6564 return intel_framebuffer_create(dev, &mode_cmd, obj);
6567 static struct drm_framebuffer *
6568 mode_fits_in_fbdev(struct drm_device *dev,
6569 struct drm_display_mode *mode)
6571 struct drm_i915_private *dev_priv = dev->dev_private;
6572 struct drm_i915_gem_object *obj;
6573 struct drm_framebuffer *fb;
6575 if (dev_priv->fbdev == NULL)
6578 obj = dev_priv->fbdev->ifb.obj;
6582 fb = &dev_priv->fbdev->ifb.base;
6583 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6584 fb->bits_per_pixel))
6587 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6593 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6594 struct drm_connector *connector,
6595 struct drm_display_mode *mode,
6596 struct intel_load_detect_pipe *old)
6598 struct intel_crtc *intel_crtc;
6599 struct drm_crtc *possible_crtc;
6600 struct drm_encoder *encoder = &intel_encoder->base;
6601 struct drm_crtc *crtc = NULL;
6602 struct drm_device *dev = encoder->dev;
6603 struct drm_framebuffer *old_fb;
6606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6607 connector->base.id, drm_get_connector_name(connector),
6608 encoder->base.id, drm_get_encoder_name(encoder));
6611 * Algorithm gets a little messy:
6613 * - if the connector already has an assigned crtc, use it (but make
6614 * sure it's on first)
6616 * - try to find the first unused crtc that can drive this connector,
6617 * and use that if we find one
6620 /* See if we already have a CRTC for this connector */
6621 if (encoder->crtc) {
6622 crtc = encoder->crtc;
6624 intel_crtc = to_intel_crtc(crtc);
6625 old->dpms_mode = intel_crtc->dpms_mode;
6626 old->load_detect_temp = false;
6628 /* Make sure the crtc and connector are running */
6629 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6630 struct drm_encoder_helper_funcs *encoder_funcs;
6631 struct drm_crtc_helper_funcs *crtc_funcs;
6633 crtc_funcs = crtc->helper_private;
6634 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6636 encoder_funcs = encoder->helper_private;
6637 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6643 /* Find an unused one (if possible) */
6644 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6646 if (!(encoder->possible_crtcs & (1 << i)))
6648 if (!possible_crtc->enabled) {
6649 crtc = possible_crtc;
6655 * If we didn't find an unused CRTC, don't use any.
6658 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6662 encoder->crtc = crtc;
6663 connector->encoder = encoder;
6665 intel_crtc = to_intel_crtc(crtc);
6666 old->dpms_mode = intel_crtc->dpms_mode;
6667 old->load_detect_temp = true;
6668 old->release_fb = NULL;
6671 mode = &load_detect_mode;
6675 /* We need a framebuffer large enough to accommodate all accesses
6676 * that the plane may generate whilst we perform load detection.
6677 * We can not rely on the fbcon either being present (we get called
6678 * during its initialisation to detect all boot displays, or it may
6679 * not even exist) or that it is large enough to satisfy the
6682 crtc->fb = mode_fits_in_fbdev(dev, mode);
6683 if (crtc->fb == NULL) {
6684 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6685 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6686 old->release_fb = crtc->fb;
6688 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6689 if (IS_ERR(crtc->fb)) {
6690 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6695 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6696 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6697 if (old->release_fb)
6698 old->release_fb->funcs->destroy(old->release_fb);
6703 /* let the connector get through one full cycle before testing */
6704 intel_wait_for_vblank(dev, intel_crtc->pipe);
6709 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6710 struct drm_connector *connector,
6711 struct intel_load_detect_pipe *old)
6713 struct drm_encoder *encoder = &intel_encoder->base;
6714 struct drm_device *dev = encoder->dev;
6715 struct drm_crtc *crtc = encoder->crtc;
6716 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6717 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6719 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6720 connector->base.id, drm_get_connector_name(connector),
6721 encoder->base.id, drm_get_encoder_name(encoder));
6723 if (old->load_detect_temp) {
6724 connector->encoder = NULL;
6725 drm_helper_disable_unused_functions(dev);
6727 if (old->release_fb)
6728 old->release_fb->funcs->destroy(old->release_fb);
6733 /* Switch crtc and encoder back off if necessary */
6734 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6735 encoder_funcs->dpms(encoder, old->dpms_mode);
6736 crtc_funcs->dpms(crtc, old->dpms_mode);
6740 /* Returns the clock of the currently programmed mode of the given pipe. */
6741 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6743 struct drm_i915_private *dev_priv = dev->dev_private;
6744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6745 int pipe = intel_crtc->pipe;
6746 u32 dpll = I915_READ(DPLL(pipe));
6748 intel_clock_t clock;
6750 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6751 fp = I915_READ(FP0(pipe));
6753 fp = I915_READ(FP1(pipe));
6755 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6756 if (IS_PINEVIEW(dev)) {
6757 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6758 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6760 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6761 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6764 if (!IS_GEN2(dev)) {
6765 if (IS_PINEVIEW(dev))
6766 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6767 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6769 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6770 DPLL_FPA01_P1_POST_DIV_SHIFT);
6772 switch (dpll & DPLL_MODE_MASK) {
6773 case DPLLB_MODE_DAC_SERIAL:
6774 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6777 case DPLLB_MODE_LVDS:
6778 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6782 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6783 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6787 /* XXX: Handle the 100Mhz refclk */
6788 intel_clock(dev, 96000, &clock);
6790 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6793 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6794 DPLL_FPA01_P1_POST_DIV_SHIFT);
6797 if ((dpll & PLL_REF_INPUT_MASK) ==
6798 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6799 /* XXX: might not be 66MHz */
6800 intel_clock(dev, 66000, &clock);
6802 intel_clock(dev, 48000, &clock);
6804 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6807 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6808 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6810 if (dpll & PLL_P2_DIVIDE_BY_4)
6815 intel_clock(dev, 48000, &clock);
6819 /* XXX: It would be nice to validate the clocks, but we can't reuse
6820 * i830PllIsValid() because it relies on the xf86_config connector
6821 * configuration being accurate, which it isn't necessarily.
6827 /** Returns the currently programmed mode of the given pipe. */
6828 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6829 struct drm_crtc *crtc)
6831 struct drm_i915_private *dev_priv = dev->dev_private;
6832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6833 int pipe = intel_crtc->pipe;
6834 struct drm_display_mode *mode;
6835 int htot = I915_READ(HTOTAL(pipe));
6836 int hsync = I915_READ(HSYNC(pipe));
6837 int vtot = I915_READ(VTOTAL(pipe));
6838 int vsync = I915_READ(VSYNC(pipe));
6840 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6844 mode->clock = intel_crtc_clock_get(dev, crtc);
6845 mode->hdisplay = (htot & 0xffff) + 1;
6846 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6847 mode->hsync_start = (hsync & 0xffff) + 1;
6848 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6849 mode->vdisplay = (vtot & 0xffff) + 1;
6850 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6851 mode->vsync_start = (vsync & 0xffff) + 1;
6852 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6854 drm_mode_set_name(mode);
6855 drm_mode_set_crtcinfo(mode, 0);
6860 #define GPU_IDLE_TIMEOUT 500 /* ms */
6862 /* When this timer fires, we've been idle for awhile */
6863 static void intel_gpu_idle_timer(unsigned long arg)
6865 struct drm_device *dev = (struct drm_device *)arg;
6866 drm_i915_private_t *dev_priv = dev->dev_private;
6868 if (!list_empty(&dev_priv->mm.active_list)) {
6869 /* Still processing requests, so just re-arm the timer. */
6870 mod_timer(&dev_priv->idle_timer, jiffies +
6871 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6875 dev_priv->busy = false;
6876 queue_work(dev_priv->wq, &dev_priv->idle_work);
6879 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6881 static void intel_crtc_idle_timer(unsigned long arg)
6883 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6884 struct drm_crtc *crtc = &intel_crtc->base;
6885 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6886 struct intel_framebuffer *intel_fb;
6888 intel_fb = to_intel_framebuffer(crtc->fb);
6889 if (intel_fb && intel_fb->obj->active) {
6890 /* The framebuffer is still being accessed by the GPU. */
6891 mod_timer(&intel_crtc->idle_timer, jiffies +
6892 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6896 intel_crtc->busy = false;
6897 queue_work(dev_priv->wq, &dev_priv->idle_work);
6900 static void intel_increase_pllclock(struct drm_crtc *crtc)
6902 struct drm_device *dev = crtc->dev;
6903 drm_i915_private_t *dev_priv = dev->dev_private;
6904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6905 int pipe = intel_crtc->pipe;
6906 int dpll_reg = DPLL(pipe);
6909 if (HAS_PCH_SPLIT(dev))
6912 if (!dev_priv->lvds_downclock_avail)
6915 dpll = I915_READ(dpll_reg);
6916 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6917 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6919 /* Unlock panel regs */
6920 I915_WRITE(PP_CONTROL,
6921 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6923 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6924 I915_WRITE(dpll_reg, dpll);
6925 intel_wait_for_vblank(dev, pipe);
6927 dpll = I915_READ(dpll_reg);
6928 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6929 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6931 /* ...and lock them again */
6932 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6935 /* Schedule downclock */
6936 mod_timer(&intel_crtc->idle_timer, jiffies +
6937 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6940 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6942 struct drm_device *dev = crtc->dev;
6943 drm_i915_private_t *dev_priv = dev->dev_private;
6944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6945 int pipe = intel_crtc->pipe;
6946 int dpll_reg = DPLL(pipe);
6947 int dpll = I915_READ(dpll_reg);
6949 if (HAS_PCH_SPLIT(dev))
6952 if (!dev_priv->lvds_downclock_avail)
6956 * Since this is called by a timer, we should never get here in
6959 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6960 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6962 /* Unlock panel regs */
6963 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6966 dpll |= DISPLAY_RATE_SELECT_FPA1;
6967 I915_WRITE(dpll_reg, dpll);
6968 intel_wait_for_vblank(dev, pipe);
6969 dpll = I915_READ(dpll_reg);
6970 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6971 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6973 /* ...and lock them again */
6974 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6980 * intel_idle_update - adjust clocks for idleness
6981 * @work: work struct
6983 * Either the GPU or display (or both) went idle. Check the busy status
6984 * here and adjust the CRTC and GPU clocks as necessary.
6986 static void intel_idle_update(struct work_struct *work)
6988 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6990 struct drm_device *dev = dev_priv->dev;
6991 struct drm_crtc *crtc;
6992 struct intel_crtc *intel_crtc;
6994 if (!i915_powersave)
6997 mutex_lock(&dev->struct_mutex);
6999 i915_update_gfx_val(dev_priv);
7001 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7002 /* Skip inactive CRTCs */
7006 intel_crtc = to_intel_crtc(crtc);
7007 if (!intel_crtc->busy)
7008 intel_decrease_pllclock(crtc);
7012 mutex_unlock(&dev->struct_mutex);
7016 * intel_mark_busy - mark the GPU and possibly the display busy
7018 * @obj: object we're operating on
7020 * Callers can use this function to indicate that the GPU is busy processing
7021 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7022 * buffer), we'll also mark the display as busy, so we know to increase its
7025 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7027 drm_i915_private_t *dev_priv = dev->dev_private;
7028 struct drm_crtc *crtc = NULL;
7029 struct intel_framebuffer *intel_fb;
7030 struct intel_crtc *intel_crtc;
7032 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7035 if (!dev_priv->busy)
7036 dev_priv->busy = true;
7038 mod_timer(&dev_priv->idle_timer, jiffies +
7039 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7041 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7045 intel_crtc = to_intel_crtc(crtc);
7046 intel_fb = to_intel_framebuffer(crtc->fb);
7047 if (intel_fb->obj == obj) {
7048 if (!intel_crtc->busy) {
7049 /* Non-busy -> busy, upclock */
7050 intel_increase_pllclock(crtc);
7051 intel_crtc->busy = true;
7053 /* Busy -> busy, put off timer */
7054 mod_timer(&intel_crtc->idle_timer, jiffies +
7055 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7061 static void intel_crtc_destroy(struct drm_crtc *crtc)
7063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7064 struct drm_device *dev = crtc->dev;
7065 struct intel_unpin_work *work;
7066 unsigned long flags;
7068 spin_lock_irqsave(&dev->event_lock, flags);
7069 work = intel_crtc->unpin_work;
7070 intel_crtc->unpin_work = NULL;
7071 spin_unlock_irqrestore(&dev->event_lock, flags);
7074 cancel_work_sync(&work->work);
7078 drm_crtc_cleanup(crtc);
7083 static void intel_unpin_work_fn(struct work_struct *__work)
7085 struct intel_unpin_work *work =
7086 container_of(__work, struct intel_unpin_work, work);
7088 mutex_lock(&work->dev->struct_mutex);
7089 i915_gem_object_unpin(work->old_fb_obj);
7090 drm_gem_object_unreference(&work->pending_flip_obj->base);
7091 drm_gem_object_unreference(&work->old_fb_obj->base);
7093 intel_update_fbc(work->dev);
7094 mutex_unlock(&work->dev->struct_mutex);
7098 static void do_intel_finish_page_flip(struct drm_device *dev,
7099 struct drm_crtc *crtc)
7101 drm_i915_private_t *dev_priv = dev->dev_private;
7102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7103 struct intel_unpin_work *work;
7104 struct drm_i915_gem_object *obj;
7105 struct drm_pending_vblank_event *e;
7106 struct timeval tnow, tvbl;
7107 unsigned long flags;
7109 /* Ignore early vblank irqs */
7110 if (intel_crtc == NULL)
7113 do_gettimeofday(&tnow);
7115 spin_lock_irqsave(&dev->event_lock, flags);
7116 work = intel_crtc->unpin_work;
7117 if (work == NULL || !work->pending) {
7118 spin_unlock_irqrestore(&dev->event_lock, flags);
7122 intel_crtc->unpin_work = NULL;
7126 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7128 /* Called before vblank count and timestamps have
7129 * been updated for the vblank interval of flip
7130 * completion? Need to increment vblank count and
7131 * add one videorefresh duration to returned timestamp
7132 * to account for this. We assume this happened if we
7133 * get called over 0.9 frame durations after the last
7134 * timestamped vblank.
7136 * This calculation can not be used with vrefresh rates
7137 * below 5Hz (10Hz to be on the safe side) without
7138 * promoting to 64 integers.
7140 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7141 9 * crtc->framedur_ns) {
7142 e->event.sequence++;
7143 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7147 e->event.tv_sec = tvbl.tv_sec;
7148 e->event.tv_usec = tvbl.tv_usec;
7150 list_add_tail(&e->base.link,
7151 &e->base.file_priv->event_list);
7152 wake_up_interruptible(&e->base.file_priv->event_wait);
7155 drm_vblank_put(dev, intel_crtc->pipe);
7157 spin_unlock_irqrestore(&dev->event_lock, flags);
7159 obj = work->old_fb_obj;
7161 atomic_clear_mask(1 << intel_crtc->plane,
7162 &obj->pending_flip.counter);
7163 if (atomic_read(&obj->pending_flip) == 0)
7164 wake_up(&dev_priv->pending_flip_queue);
7166 schedule_work(&work->work);
7168 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7171 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7173 drm_i915_private_t *dev_priv = dev->dev_private;
7174 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7176 do_intel_finish_page_flip(dev, crtc);
7179 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7181 drm_i915_private_t *dev_priv = dev->dev_private;
7182 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7184 do_intel_finish_page_flip(dev, crtc);
7187 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7189 drm_i915_private_t *dev_priv = dev->dev_private;
7190 struct intel_crtc *intel_crtc =
7191 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7192 unsigned long flags;
7194 spin_lock_irqsave(&dev->event_lock, flags);
7195 if (intel_crtc->unpin_work) {
7196 if ((++intel_crtc->unpin_work->pending) > 1)
7197 DRM_ERROR("Prepared flip multiple times\n");
7199 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7201 spin_unlock_irqrestore(&dev->event_lock, flags);
7204 static int intel_gen2_queue_flip(struct drm_device *dev,
7205 struct drm_crtc *crtc,
7206 struct drm_framebuffer *fb,
7207 struct drm_i915_gem_object *obj)
7209 struct drm_i915_private *dev_priv = dev->dev_private;
7210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7211 unsigned long offset;
7215 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7219 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7220 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7222 ret = BEGIN_LP_RING(6);
7226 /* Can't queue multiple flips, so wait for the previous
7227 * one to finish before executing the next.
7229 if (intel_crtc->plane)
7230 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7232 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7233 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7235 OUT_RING(MI_DISPLAY_FLIP |
7236 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7237 OUT_RING(fb->pitches[0]);
7238 OUT_RING(obj->gtt_offset + offset);
7245 static int intel_gen3_queue_flip(struct drm_device *dev,
7246 struct drm_crtc *crtc,
7247 struct drm_framebuffer *fb,
7248 struct drm_i915_gem_object *obj)
7250 struct drm_i915_private *dev_priv = dev->dev_private;
7251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7252 unsigned long offset;
7256 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7260 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7261 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7263 ret = BEGIN_LP_RING(6);
7267 if (intel_crtc->plane)
7268 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7270 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7271 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7273 OUT_RING(MI_DISPLAY_FLIP_I915 |
7274 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7275 OUT_RING(fb->pitches[0]);
7276 OUT_RING(obj->gtt_offset + offset);
7284 static int intel_gen4_queue_flip(struct drm_device *dev,
7285 struct drm_crtc *crtc,
7286 struct drm_framebuffer *fb,
7287 struct drm_i915_gem_object *obj)
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291 uint32_t pf, pipesrc;
7294 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7298 ret = BEGIN_LP_RING(4);
7302 /* i965+ uses the linear or tiled offsets from the
7303 * Display Registers (which do not change across a page-flip)
7304 * so we need only reprogram the base address.
7306 OUT_RING(MI_DISPLAY_FLIP |
7307 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7308 OUT_RING(fb->pitches[0]);
7309 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7311 /* XXX Enabling the panel-fitter across page-flip is so far
7312 * untested on non-native modes, so ignore it for now.
7313 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7316 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7317 OUT_RING(pf | pipesrc);
7323 static int intel_gen6_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7330 uint32_t pf, pipesrc;
7333 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7337 ret = BEGIN_LP_RING(4);
7341 OUT_RING(MI_DISPLAY_FLIP |
7342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7343 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7344 OUT_RING(obj->gtt_offset);
7346 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7347 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7348 OUT_RING(pf | pipesrc);
7355 * On gen7 we currently use the blit ring because (in early silicon at least)
7356 * the render ring doesn't give us interrpts for page flip completion, which
7357 * means clients will hang after the first flip is queued. Fortunately the
7358 * blit ring generates interrupts properly, so use it instead.
7360 static int intel_gen7_queue_flip(struct drm_device *dev,
7361 struct drm_crtc *crtc,
7362 struct drm_framebuffer *fb,
7363 struct drm_i915_gem_object *obj)
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7367 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7370 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7374 ret = intel_ring_begin(ring, 4);
7378 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7379 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7380 intel_ring_emit(ring, (obj->gtt_offset));
7381 intel_ring_emit(ring, (MI_NOOP));
7382 intel_ring_advance(ring);
7387 static int intel_default_queue_flip(struct drm_device *dev,
7388 struct drm_crtc *crtc,
7389 struct drm_framebuffer *fb,
7390 struct drm_i915_gem_object *obj)
7395 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7396 struct drm_framebuffer *fb,
7397 struct drm_pending_vblank_event *event)
7399 struct drm_device *dev = crtc->dev;
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 struct intel_framebuffer *intel_fb;
7402 struct drm_i915_gem_object *obj;
7403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7404 struct intel_unpin_work *work;
7405 unsigned long flags;
7408 work = kzalloc(sizeof *work, GFP_KERNEL);
7412 work->event = event;
7413 work->dev = crtc->dev;
7414 intel_fb = to_intel_framebuffer(crtc->fb);
7415 work->old_fb_obj = intel_fb->obj;
7416 INIT_WORK(&work->work, intel_unpin_work_fn);
7418 ret = drm_vblank_get(dev, intel_crtc->pipe);
7422 /* We borrow the event spin lock for protecting unpin_work */
7423 spin_lock_irqsave(&dev->event_lock, flags);
7424 if (intel_crtc->unpin_work) {
7425 spin_unlock_irqrestore(&dev->event_lock, flags);
7427 drm_vblank_put(dev, intel_crtc->pipe);
7429 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7432 intel_crtc->unpin_work = work;
7433 spin_unlock_irqrestore(&dev->event_lock, flags);
7435 intel_fb = to_intel_framebuffer(fb);
7436 obj = intel_fb->obj;
7438 mutex_lock(&dev->struct_mutex);
7440 /* Reference the objects for the scheduled work. */
7441 drm_gem_object_reference(&work->old_fb_obj->base);
7442 drm_gem_object_reference(&obj->base);
7446 work->pending_flip_obj = obj;
7448 work->enable_stall_check = true;
7450 /* Block clients from rendering to the new back buffer until
7451 * the flip occurs and the object is no longer visible.
7453 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7455 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7457 goto cleanup_pending;
7459 intel_disable_fbc(dev);
7460 mutex_unlock(&dev->struct_mutex);
7462 trace_i915_flip_request(intel_crtc->plane, obj);
7467 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7468 drm_gem_object_unreference(&work->old_fb_obj->base);
7469 drm_gem_object_unreference(&obj->base);
7470 mutex_unlock(&dev->struct_mutex);
7472 spin_lock_irqsave(&dev->event_lock, flags);
7473 intel_crtc->unpin_work = NULL;
7474 spin_unlock_irqrestore(&dev->event_lock, flags);
7476 drm_vblank_put(dev, intel_crtc->pipe);
7483 static void intel_sanitize_modesetting(struct drm_device *dev,
7484 int pipe, int plane)
7486 struct drm_i915_private *dev_priv = dev->dev_private;
7489 if (HAS_PCH_SPLIT(dev))
7492 /* Who knows what state these registers were left in by the BIOS or
7495 * If we leave the registers in a conflicting state (e.g. with the
7496 * display plane reading from the other pipe than the one we intend
7497 * to use) then when we attempt to teardown the active mode, we will
7498 * not disable the pipes and planes in the correct order -- leaving
7499 * a plane reading from a disabled pipe and possibly leading to
7500 * undefined behaviour.
7503 reg = DSPCNTR(plane);
7504 val = I915_READ(reg);
7506 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7508 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7511 /* This display plane is active and attached to the other CPU pipe. */
7514 /* Disable the plane and wait for it to stop reading from the pipe. */
7515 intel_disable_plane(dev_priv, plane, pipe);
7516 intel_disable_pipe(dev_priv, pipe);
7519 static void intel_crtc_reset(struct drm_crtc *crtc)
7521 struct drm_device *dev = crtc->dev;
7522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7524 /* Reset flags back to the 'unknown' status so that they
7525 * will be correctly set on the initial modeset.
7527 intel_crtc->dpms_mode = -1;
7529 /* We need to fix up any BIOS configuration that conflicts with
7532 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7535 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7536 .dpms = intel_crtc_dpms,
7537 .mode_fixup = intel_crtc_mode_fixup,
7538 .mode_set = intel_crtc_mode_set,
7539 .mode_set_base = intel_pipe_set_base,
7540 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7541 .load_lut = intel_crtc_load_lut,
7542 .disable = intel_crtc_disable,
7545 static const struct drm_crtc_funcs intel_crtc_funcs = {
7546 .reset = intel_crtc_reset,
7547 .cursor_set = intel_crtc_cursor_set,
7548 .cursor_move = intel_crtc_cursor_move,
7549 .gamma_set = intel_crtc_gamma_set,
7550 .set_config = drm_crtc_helper_set_config,
7551 .destroy = intel_crtc_destroy,
7552 .page_flip = intel_crtc_page_flip,
7555 static void intel_crtc_init(struct drm_device *dev, int pipe)
7557 drm_i915_private_t *dev_priv = dev->dev_private;
7558 struct intel_crtc *intel_crtc;
7561 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7562 if (intel_crtc == NULL)
7565 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7567 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7568 for (i = 0; i < 256; i++) {
7569 intel_crtc->lut_r[i] = i;
7570 intel_crtc->lut_g[i] = i;
7571 intel_crtc->lut_b[i] = i;
7574 /* Swap pipes & planes for FBC on pre-965 */
7575 intel_crtc->pipe = pipe;
7576 intel_crtc->plane = pipe;
7577 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7578 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7579 intel_crtc->plane = !pipe;
7582 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7583 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7584 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7585 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7587 intel_crtc_reset(&intel_crtc->base);
7588 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7589 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7591 if (HAS_PCH_SPLIT(dev)) {
7592 if (pipe == 2 && IS_IVYBRIDGE(dev))
7593 intel_crtc->no_pll = true;
7594 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7595 intel_helper_funcs.commit = ironlake_crtc_commit;
7597 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7598 intel_helper_funcs.commit = i9xx_crtc_commit;
7601 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7603 intel_crtc->busy = false;
7605 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7606 (unsigned long)intel_crtc);
7609 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7610 struct drm_file *file)
7612 drm_i915_private_t *dev_priv = dev->dev_private;
7613 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7614 struct drm_mode_object *drmmode_obj;
7615 struct intel_crtc *crtc;
7618 DRM_ERROR("called with no initialization\n");
7622 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7623 DRM_MODE_OBJECT_CRTC);
7626 DRM_ERROR("no such CRTC id\n");
7630 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7631 pipe_from_crtc_id->pipe = crtc->pipe;
7636 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7638 struct intel_encoder *encoder;
7642 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7643 if (type_mask & encoder->clone_mask)
7644 index_mask |= (1 << entry);
7651 static bool has_edp_a(struct drm_device *dev)
7653 struct drm_i915_private *dev_priv = dev->dev_private;
7655 if (!IS_MOBILE(dev))
7658 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7662 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7668 static void intel_setup_outputs(struct drm_device *dev)
7670 struct drm_i915_private *dev_priv = dev->dev_private;
7671 struct intel_encoder *encoder;
7672 bool dpd_is_edp = false;
7673 bool has_lvds = false;
7675 if (IS_MOBILE(dev) && !IS_I830(dev))
7676 has_lvds = intel_lvds_init(dev);
7677 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7678 /* disable the panel fitter on everything but LVDS */
7679 I915_WRITE(PFIT_CONTROL, 0);
7682 if (HAS_PCH_SPLIT(dev)) {
7683 dpd_is_edp = intel_dpd_is_edp(dev);
7686 intel_dp_init(dev, DP_A);
7688 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7689 intel_dp_init(dev, PCH_DP_D);
7692 intel_crt_init(dev);
7694 if (HAS_PCH_SPLIT(dev)) {
7697 if (I915_READ(HDMIB) & PORT_DETECTED) {
7698 /* PCH SDVOB multiplex with HDMIB */
7699 found = intel_sdvo_init(dev, PCH_SDVOB);
7701 intel_hdmi_init(dev, HDMIB);
7702 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7703 intel_dp_init(dev, PCH_DP_B);
7706 if (I915_READ(HDMIC) & PORT_DETECTED)
7707 intel_hdmi_init(dev, HDMIC);
7709 if (I915_READ(HDMID) & PORT_DETECTED)
7710 intel_hdmi_init(dev, HDMID);
7712 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7713 intel_dp_init(dev, PCH_DP_C);
7715 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7716 intel_dp_init(dev, PCH_DP_D);
7718 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7721 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7722 DRM_DEBUG_KMS("probing SDVOB\n");
7723 found = intel_sdvo_init(dev, SDVOB);
7724 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7725 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7726 intel_hdmi_init(dev, SDVOB);
7729 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7730 DRM_DEBUG_KMS("probing DP_B\n");
7731 intel_dp_init(dev, DP_B);
7735 /* Before G4X SDVOC doesn't have its own detect register */
7737 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7738 DRM_DEBUG_KMS("probing SDVOC\n");
7739 found = intel_sdvo_init(dev, SDVOC);
7742 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7744 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7745 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7746 intel_hdmi_init(dev, SDVOC);
7748 if (SUPPORTS_INTEGRATED_DP(dev)) {
7749 DRM_DEBUG_KMS("probing DP_C\n");
7750 intel_dp_init(dev, DP_C);
7754 if (SUPPORTS_INTEGRATED_DP(dev) &&
7755 (I915_READ(DP_D) & DP_DETECTED)) {
7756 DRM_DEBUG_KMS("probing DP_D\n");
7757 intel_dp_init(dev, DP_D);
7759 } else if (IS_GEN2(dev))
7760 intel_dvo_init(dev);
7762 if (SUPPORTS_TV(dev))
7765 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7766 encoder->base.possible_crtcs = encoder->crtc_mask;
7767 encoder->base.possible_clones =
7768 intel_encoder_clones(dev, encoder->clone_mask);
7771 /* disable all the possible outputs/crtcs before entering KMS mode */
7772 drm_helper_disable_unused_functions(dev);
7774 if (HAS_PCH_SPLIT(dev))
7775 ironlake_init_pch_refclk(dev);
7778 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7780 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7782 drm_framebuffer_cleanup(fb);
7783 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7788 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7789 struct drm_file *file,
7790 unsigned int *handle)
7792 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7793 struct drm_i915_gem_object *obj = intel_fb->obj;
7795 return drm_gem_handle_create(file, &obj->base, handle);
7798 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7799 .destroy = intel_user_framebuffer_destroy,
7800 .create_handle = intel_user_framebuffer_create_handle,
7803 int intel_framebuffer_init(struct drm_device *dev,
7804 struct intel_framebuffer *intel_fb,
7805 struct drm_mode_fb_cmd2 *mode_cmd,
7806 struct drm_i915_gem_object *obj)
7810 if (obj->tiling_mode == I915_TILING_Y)
7813 if (mode_cmd->pitches[0] & 63)
7816 switch (mode_cmd->pixel_format) {
7817 case DRM_FORMAT_RGB332:
7818 case DRM_FORMAT_RGB565:
7819 case DRM_FORMAT_XRGB8888:
7820 case DRM_FORMAT_ARGB8888:
7821 case DRM_FORMAT_XRGB2101010:
7822 case DRM_FORMAT_ARGB2101010:
7823 /* RGB formats are common across chipsets */
7825 case DRM_FORMAT_YUYV:
7826 case DRM_FORMAT_UYVY:
7827 case DRM_FORMAT_YVYU:
7828 case DRM_FORMAT_VYUY:
7831 DRM_ERROR("unsupported pixel format\n");
7835 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7837 DRM_ERROR("framebuffer init failed %d\n", ret);
7841 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7842 intel_fb->obj = obj;
7846 static struct drm_framebuffer *
7847 intel_user_framebuffer_create(struct drm_device *dev,
7848 struct drm_file *filp,
7849 struct drm_mode_fb_cmd2 *mode_cmd)
7851 struct drm_i915_gem_object *obj;
7853 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7854 mode_cmd->handles[0]));
7855 if (&obj->base == NULL)
7856 return ERR_PTR(-ENOENT);
7858 return intel_framebuffer_create(dev, mode_cmd, obj);
7861 static const struct drm_mode_config_funcs intel_mode_funcs = {
7862 .fb_create = intel_user_framebuffer_create,
7863 .output_poll_changed = intel_fb_output_poll_changed,
7866 static struct drm_i915_gem_object *
7867 intel_alloc_context_page(struct drm_device *dev)
7869 struct drm_i915_gem_object *ctx;
7872 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7874 ctx = i915_gem_alloc_object(dev, 4096);
7876 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7880 ret = i915_gem_object_pin(ctx, 4096, true);
7882 DRM_ERROR("failed to pin power context: %d\n", ret);
7886 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7888 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7895 i915_gem_object_unpin(ctx);
7897 drm_gem_object_unreference(&ctx->base);
7898 mutex_unlock(&dev->struct_mutex);
7902 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7904 struct drm_i915_private *dev_priv = dev->dev_private;
7907 rgvswctl = I915_READ16(MEMSWCTL);
7908 if (rgvswctl & MEMCTL_CMD_STS) {
7909 DRM_DEBUG("gpu busy, RCS change rejected\n");
7910 return false; /* still busy with another command */
7913 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7914 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7915 I915_WRITE16(MEMSWCTL, rgvswctl);
7916 POSTING_READ16(MEMSWCTL);
7918 rgvswctl |= MEMCTL_CMD_STS;
7919 I915_WRITE16(MEMSWCTL, rgvswctl);
7924 void ironlake_enable_drps(struct drm_device *dev)
7926 struct drm_i915_private *dev_priv = dev->dev_private;
7927 u32 rgvmodectl = I915_READ(MEMMODECTL);
7928 u8 fmax, fmin, fstart, vstart;
7930 /* Enable temp reporting */
7931 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7932 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7934 /* 100ms RC evaluation intervals */
7935 I915_WRITE(RCUPEI, 100000);
7936 I915_WRITE(RCDNEI, 100000);
7938 /* Set max/min thresholds to 90ms and 80ms respectively */
7939 I915_WRITE(RCBMAXAVG, 90000);
7940 I915_WRITE(RCBMINAVG, 80000);
7942 I915_WRITE(MEMIHYST, 1);
7944 /* Set up min, max, and cur for interrupt handling */
7945 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7946 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7947 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7948 MEMMODE_FSTART_SHIFT;
7950 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7953 dev_priv->fmax = fmax; /* IPS callback will increase this */
7954 dev_priv->fstart = fstart;
7956 dev_priv->max_delay = fstart;
7957 dev_priv->min_delay = fmin;
7958 dev_priv->cur_delay = fstart;
7960 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7961 fmax, fmin, fstart);
7963 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7966 * Interrupts will be enabled in ironlake_irq_postinstall
7969 I915_WRITE(VIDSTART, vstart);
7970 POSTING_READ(VIDSTART);
7972 rgvmodectl |= MEMMODE_SWMODE_EN;
7973 I915_WRITE(MEMMODECTL, rgvmodectl);
7975 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7976 DRM_ERROR("stuck trying to change perf mode\n");
7979 ironlake_set_drps(dev, fstart);
7981 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7983 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7984 dev_priv->last_count2 = I915_READ(0x112f4);
7985 getrawmonotonic(&dev_priv->last_time2);
7988 void ironlake_disable_drps(struct drm_device *dev)
7990 struct drm_i915_private *dev_priv = dev->dev_private;
7991 u16 rgvswctl = I915_READ16(MEMSWCTL);
7993 /* Ack interrupts, disable EFC interrupt */
7994 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7995 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7996 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7997 I915_WRITE(DEIIR, DE_PCU_EVENT);
7998 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8000 /* Go back to the starting frequency */
8001 ironlake_set_drps(dev, dev_priv->fstart);
8003 rgvswctl |= MEMCTL_CMD_STS;
8004 I915_WRITE(MEMSWCTL, rgvswctl);
8009 void gen6_set_rps(struct drm_device *dev, u8 val)
8011 struct drm_i915_private *dev_priv = dev->dev_private;
8014 swreq = (val & 0x3ff) << 25;
8015 I915_WRITE(GEN6_RPNSWREQ, swreq);
8018 void gen6_disable_rps(struct drm_device *dev)
8020 struct drm_i915_private *dev_priv = dev->dev_private;
8022 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8023 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8024 I915_WRITE(GEN6_PMIER, 0);
8025 /* Complete PM interrupt masking here doesn't race with the rps work
8026 * item again unmasking PM interrupts because that is using a different
8027 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8028 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8030 spin_lock_irq(&dev_priv->rps_lock);
8031 dev_priv->pm_iir = 0;
8032 spin_unlock_irq(&dev_priv->rps_lock);
8034 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8037 static unsigned long intel_pxfreq(u32 vidfreq)
8040 int div = (vidfreq & 0x3f0000) >> 16;
8041 int post = (vidfreq & 0x3000) >> 12;
8042 int pre = (vidfreq & 0x7);
8047 freq = ((div * 133333) / ((1<<post) * pre));
8052 void intel_init_emon(struct drm_device *dev)
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8059 /* Disable to program */
8063 /* Program energy weights for various events */
8064 I915_WRITE(SDEW, 0x15040d00);
8065 I915_WRITE(CSIEW0, 0x007f0000);
8066 I915_WRITE(CSIEW1, 0x1e220004);
8067 I915_WRITE(CSIEW2, 0x04000004);
8069 for (i = 0; i < 5; i++)
8070 I915_WRITE(PEW + (i * 4), 0);
8071 for (i = 0; i < 3; i++)
8072 I915_WRITE(DEW + (i * 4), 0);
8074 /* Program P-state weights to account for frequency power adjustment */
8075 for (i = 0; i < 16; i++) {
8076 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8077 unsigned long freq = intel_pxfreq(pxvidfreq);
8078 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8083 val *= (freq / 1000);
8085 val /= (127*127*900);
8087 DRM_ERROR("bad pxval: %ld\n", val);
8090 /* Render standby states get 0 weight */
8094 for (i = 0; i < 4; i++) {
8095 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8096 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8097 I915_WRITE(PXW + (i * 4), val);
8100 /* Adjust magic regs to magic values (more experimental results) */
8101 I915_WRITE(OGW0, 0);
8102 I915_WRITE(OGW1, 0);
8103 I915_WRITE(EG0, 0x00007f00);
8104 I915_WRITE(EG1, 0x0000000e);
8105 I915_WRITE(EG2, 0x000e0000);
8106 I915_WRITE(EG3, 0x68000300);
8107 I915_WRITE(EG4, 0x42000000);
8108 I915_WRITE(EG5, 0x00140031);
8112 for (i = 0; i < 8; i++)
8113 I915_WRITE(PXWL + (i * 4), 0);
8115 /* Enable PMON + select events */
8116 I915_WRITE(ECR, 0x80000019);
8118 lcfuse = I915_READ(LCFUSE02);
8120 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8123 static bool intel_enable_rc6(struct drm_device *dev)
8126 * Respect the kernel parameter if it is set
8128 if (i915_enable_rc6 >= 0)
8129 return i915_enable_rc6;
8132 * Disable RC6 on Ironlake
8134 if (INTEL_INFO(dev)->gen == 5)
8138 * Disable rc6 on Sandybridge
8140 if (INTEL_INFO(dev)->gen == 6) {
8141 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8144 DRM_DEBUG_DRIVER("RC6 enabled\n");
8148 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8150 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8151 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8152 u32 pcu_mbox, rc6_mask = 0;
8153 int cur_freq, min_freq, max_freq;
8156 /* Here begins a magic sequence of register writes to enable
8157 * auto-downclocking.
8159 * Perhaps there might be some value in exposing these to
8162 I915_WRITE(GEN6_RC_STATE, 0);
8163 mutex_lock(&dev_priv->dev->struct_mutex);
8164 gen6_gt_force_wake_get(dev_priv);
8166 /* disable the counters and set deterministic thresholds */
8167 I915_WRITE(GEN6_RC_CONTROL, 0);
8169 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8170 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8171 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8172 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8173 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8175 for (i = 0; i < I915_NUM_RINGS; i++)
8176 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8178 I915_WRITE(GEN6_RC_SLEEP, 0);
8179 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8180 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8181 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8182 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8184 if (intel_enable_rc6(dev_priv->dev))
8185 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8186 GEN6_RC_CTL_RC6_ENABLE;
8188 I915_WRITE(GEN6_RC_CONTROL,
8190 GEN6_RC_CTL_EI_MODE(1) |
8191 GEN6_RC_CTL_HW_ENABLE);
8193 I915_WRITE(GEN6_RPNSWREQ,
8194 GEN6_FREQUENCY(10) |
8196 GEN6_AGGRESSIVE_TURBO);
8197 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8198 GEN6_FREQUENCY(12));
8200 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8201 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8204 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8205 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8206 I915_WRITE(GEN6_RP_UP_EI, 100000);
8207 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8208 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8209 I915_WRITE(GEN6_RP_CONTROL,
8210 GEN6_RP_MEDIA_TURBO |
8211 GEN6_RP_MEDIA_HW_MODE |
8212 GEN6_RP_MEDIA_IS_GFX |
8214 GEN6_RP_UP_BUSY_AVG |
8215 GEN6_RP_DOWN_IDLE_CONT);
8217 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8219 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8221 I915_WRITE(GEN6_PCODE_DATA, 0);
8222 I915_WRITE(GEN6_PCODE_MAILBOX,
8224 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8225 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8227 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8229 min_freq = (rp_state_cap & 0xff0000) >> 16;
8230 max_freq = rp_state_cap & 0xff;
8231 cur_freq = (gt_perf_status & 0xff00) >> 8;
8233 /* Check for overclock support */
8234 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8236 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8237 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8238 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8239 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8241 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8242 if (pcu_mbox & (1<<31)) { /* OC supported */
8243 max_freq = pcu_mbox & 0xff;
8244 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8247 /* In units of 100MHz */
8248 dev_priv->max_delay = max_freq;
8249 dev_priv->min_delay = min_freq;
8250 dev_priv->cur_delay = cur_freq;
8252 /* requires MSI enabled */
8253 I915_WRITE(GEN6_PMIER,
8254 GEN6_PM_MBOX_EVENT |
8255 GEN6_PM_THERMAL_EVENT |
8256 GEN6_PM_RP_DOWN_TIMEOUT |
8257 GEN6_PM_RP_UP_THRESHOLD |
8258 GEN6_PM_RP_DOWN_THRESHOLD |
8259 GEN6_PM_RP_UP_EI_EXPIRED |
8260 GEN6_PM_RP_DOWN_EI_EXPIRED);
8261 spin_lock_irq(&dev_priv->rps_lock);
8262 WARN_ON(dev_priv->pm_iir != 0);
8263 I915_WRITE(GEN6_PMIMR, 0);
8264 spin_unlock_irq(&dev_priv->rps_lock);
8265 /* enable all PM interrupts */
8266 I915_WRITE(GEN6_PMINTRMSK, 0);
8268 gen6_gt_force_wake_put(dev_priv);
8269 mutex_unlock(&dev_priv->dev->struct_mutex);
8272 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8275 int gpu_freq, ia_freq, max_ia_freq;
8276 int scaling_factor = 180;
8278 max_ia_freq = cpufreq_quick_get_max(0);
8280 * Default to measured freq if none found, PCU will ensure we don't go
8284 max_ia_freq = tsc_khz;
8286 /* Convert from kHz to MHz */
8287 max_ia_freq /= 1000;
8289 mutex_lock(&dev_priv->dev->struct_mutex);
8292 * For each potential GPU frequency, load a ring frequency we'd like
8293 * to use for memory access. We do this by specifying the IA frequency
8294 * the PCU should use as a reference to determine the ring frequency.
8296 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8298 int diff = dev_priv->max_delay - gpu_freq;
8301 * For GPU frequencies less than 750MHz, just use the lowest
8304 if (gpu_freq < min_freq)
8307 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8308 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8310 I915_WRITE(GEN6_PCODE_DATA,
8311 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8313 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8314 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8315 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8316 GEN6_PCODE_READY) == 0, 10)) {
8317 DRM_ERROR("pcode write of freq table timed out\n");
8322 mutex_unlock(&dev_priv->dev->struct_mutex);
8325 static void ironlake_init_clock_gating(struct drm_device *dev)
8327 struct drm_i915_private *dev_priv = dev->dev_private;
8328 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8330 /* Required for FBC */
8331 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8332 DPFCRUNIT_CLOCK_GATE_DISABLE |
8333 DPFDUNIT_CLOCK_GATE_DISABLE;
8334 /* Required for CxSR */
8335 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8337 I915_WRITE(PCH_3DCGDIS0,
8338 MARIUNIT_CLOCK_GATE_DISABLE |
8339 SVSMUNIT_CLOCK_GATE_DISABLE);
8340 I915_WRITE(PCH_3DCGDIS1,
8341 VFMUNIT_CLOCK_GATE_DISABLE);
8343 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8346 * According to the spec the following bits should be set in
8347 * order to enable memory self-refresh
8348 * The bit 22/21 of 0x42004
8349 * The bit 5 of 0x42020
8350 * The bit 15 of 0x45000
8352 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8353 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8354 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8355 I915_WRITE(ILK_DSPCLK_GATE,
8356 (I915_READ(ILK_DSPCLK_GATE) |
8357 ILK_DPARB_CLK_GATE));
8358 I915_WRITE(DISP_ARB_CTL,
8359 (I915_READ(DISP_ARB_CTL) |
8361 I915_WRITE(WM3_LP_ILK, 0);
8362 I915_WRITE(WM2_LP_ILK, 0);
8363 I915_WRITE(WM1_LP_ILK, 0);
8366 * Based on the document from hardware guys the following bits
8367 * should be set unconditionally in order to enable FBC.
8368 * The bit 22 of 0x42000
8369 * The bit 22 of 0x42004
8370 * The bit 7,8,9 of 0x42020.
8372 if (IS_IRONLAKE_M(dev)) {
8373 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8374 I915_READ(ILK_DISPLAY_CHICKEN1) |
8376 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8377 I915_READ(ILK_DISPLAY_CHICKEN2) |
8379 I915_WRITE(ILK_DSPCLK_GATE,
8380 I915_READ(ILK_DSPCLK_GATE) |
8386 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8387 I915_READ(ILK_DISPLAY_CHICKEN2) |
8388 ILK_ELPIN_409_SELECT);
8389 I915_WRITE(_3D_CHICKEN2,
8390 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8391 _3D_CHICKEN2_WM_READ_PIPELINED);
8394 static void gen6_init_clock_gating(struct drm_device *dev)
8396 struct drm_i915_private *dev_priv = dev->dev_private;
8398 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8400 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8402 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8403 I915_READ(ILK_DISPLAY_CHICKEN2) |
8404 ILK_ELPIN_409_SELECT);
8406 I915_WRITE(WM3_LP_ILK, 0);
8407 I915_WRITE(WM2_LP_ILK, 0);
8408 I915_WRITE(WM1_LP_ILK, 0);
8410 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8411 * gating disable must be set. Failure to set it results in
8412 * flickering pixels due to Z write ordering failures after
8413 * some amount of runtime in the Mesa "fire" demo, and Unigine
8414 * Sanctuary and Tropics, and apparently anything else with
8415 * alpha test or pixel discard.
8417 * According to the spec, bit 11 (RCCUNIT) must also be set,
8418 * but we didn't debug actual testcases to find it out.
8420 I915_WRITE(GEN6_UCGCTL2,
8421 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8422 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8425 * According to the spec the following bits should be
8426 * set in order to enable memory self-refresh and fbc:
8427 * The bit21 and bit22 of 0x42000
8428 * The bit21 and bit22 of 0x42004
8429 * The bit5 and bit7 of 0x42020
8430 * The bit14 of 0x70180
8431 * The bit14 of 0x71180
8433 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8434 I915_READ(ILK_DISPLAY_CHICKEN1) |
8435 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8436 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8437 I915_READ(ILK_DISPLAY_CHICKEN2) |
8438 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8439 I915_WRITE(ILK_DSPCLK_GATE,
8440 I915_READ(ILK_DSPCLK_GATE) |
8441 ILK_DPARB_CLK_GATE |
8444 for_each_pipe(pipe) {
8445 I915_WRITE(DSPCNTR(pipe),
8446 I915_READ(DSPCNTR(pipe)) |
8447 DISPPLANE_TRICKLE_FEED_DISABLE);
8448 intel_flush_display_plane(dev_priv, pipe);
8452 static void ivybridge_init_clock_gating(struct drm_device *dev)
8454 struct drm_i915_private *dev_priv = dev->dev_private;
8456 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8458 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8460 I915_WRITE(WM3_LP_ILK, 0);
8461 I915_WRITE(WM2_LP_ILK, 0);
8462 I915_WRITE(WM1_LP_ILK, 0);
8464 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8465 * This implements the WaDisableRCZUnitClockGating workaround.
8467 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8469 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8471 I915_WRITE(IVB_CHICKEN3,
8472 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8473 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8475 for_each_pipe(pipe) {
8476 I915_WRITE(DSPCNTR(pipe),
8477 I915_READ(DSPCNTR(pipe)) |
8478 DISPPLANE_TRICKLE_FEED_DISABLE);
8479 intel_flush_display_plane(dev_priv, pipe);
8483 static void g4x_init_clock_gating(struct drm_device *dev)
8485 struct drm_i915_private *dev_priv = dev->dev_private;
8486 uint32_t dspclk_gate;
8488 I915_WRITE(RENCLK_GATE_D1, 0);
8489 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8490 GS_UNIT_CLOCK_GATE_DISABLE |
8491 CL_UNIT_CLOCK_GATE_DISABLE);
8492 I915_WRITE(RAMCLK_GATE_D, 0);
8493 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8494 OVRUNIT_CLOCK_GATE_DISABLE |
8495 OVCUNIT_CLOCK_GATE_DISABLE;
8497 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8498 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8501 static void crestline_init_clock_gating(struct drm_device *dev)
8503 struct drm_i915_private *dev_priv = dev->dev_private;
8505 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8506 I915_WRITE(RENCLK_GATE_D2, 0);
8507 I915_WRITE(DSPCLK_GATE_D, 0);
8508 I915_WRITE(RAMCLK_GATE_D, 0);
8509 I915_WRITE16(DEUC, 0);
8512 static void broadwater_init_clock_gating(struct drm_device *dev)
8514 struct drm_i915_private *dev_priv = dev->dev_private;
8516 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8517 I965_RCC_CLOCK_GATE_DISABLE |
8518 I965_RCPB_CLOCK_GATE_DISABLE |
8519 I965_ISC_CLOCK_GATE_DISABLE |
8520 I965_FBC_CLOCK_GATE_DISABLE);
8521 I915_WRITE(RENCLK_GATE_D2, 0);
8524 static void gen3_init_clock_gating(struct drm_device *dev)
8526 struct drm_i915_private *dev_priv = dev->dev_private;
8527 u32 dstate = I915_READ(D_STATE);
8529 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8530 DSTATE_DOT_CLOCK_GATING;
8531 I915_WRITE(D_STATE, dstate);
8534 static void i85x_init_clock_gating(struct drm_device *dev)
8536 struct drm_i915_private *dev_priv = dev->dev_private;
8538 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8541 static void i830_init_clock_gating(struct drm_device *dev)
8543 struct drm_i915_private *dev_priv = dev->dev_private;
8545 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8548 static void ibx_init_clock_gating(struct drm_device *dev)
8550 struct drm_i915_private *dev_priv = dev->dev_private;
8553 * On Ibex Peak and Cougar Point, we need to disable clock
8554 * gating for the panel power sequencer or it will fail to
8555 * start up when no ports are active.
8557 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8560 static void cpt_init_clock_gating(struct drm_device *dev)
8562 struct drm_i915_private *dev_priv = dev->dev_private;
8566 * On Ibex Peak and Cougar Point, we need to disable clock
8567 * gating for the panel power sequencer or it will fail to
8568 * start up when no ports are active.
8570 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8571 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8572 DPLS_EDP_PPS_FIX_DIS);
8573 /* Without this, mode sets may fail silently on FDI */
8575 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8578 static void ironlake_teardown_rc6(struct drm_device *dev)
8580 struct drm_i915_private *dev_priv = dev->dev_private;
8582 if (dev_priv->renderctx) {
8583 i915_gem_object_unpin(dev_priv->renderctx);
8584 drm_gem_object_unreference(&dev_priv->renderctx->base);
8585 dev_priv->renderctx = NULL;
8588 if (dev_priv->pwrctx) {
8589 i915_gem_object_unpin(dev_priv->pwrctx);
8590 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8591 dev_priv->pwrctx = NULL;
8595 static void ironlake_disable_rc6(struct drm_device *dev)
8597 struct drm_i915_private *dev_priv = dev->dev_private;
8599 if (I915_READ(PWRCTXA)) {
8600 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8601 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8602 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8605 I915_WRITE(PWRCTXA, 0);
8606 POSTING_READ(PWRCTXA);
8608 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8609 POSTING_READ(RSTDBYCTL);
8612 ironlake_teardown_rc6(dev);
8615 static int ironlake_setup_rc6(struct drm_device *dev)
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8619 if (dev_priv->renderctx == NULL)
8620 dev_priv->renderctx = intel_alloc_context_page(dev);
8621 if (!dev_priv->renderctx)
8624 if (dev_priv->pwrctx == NULL)
8625 dev_priv->pwrctx = intel_alloc_context_page(dev);
8626 if (!dev_priv->pwrctx) {
8627 ironlake_teardown_rc6(dev);
8634 void ironlake_enable_rc6(struct drm_device *dev)
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8639 /* rc6 disabled by default due to repeated reports of hanging during
8642 if (!intel_enable_rc6(dev))
8645 mutex_lock(&dev->struct_mutex);
8646 ret = ironlake_setup_rc6(dev);
8648 mutex_unlock(&dev->struct_mutex);
8653 * GPU can automatically power down the render unit if given a page
8656 ret = BEGIN_LP_RING(6);
8658 ironlake_teardown_rc6(dev);
8659 mutex_unlock(&dev->struct_mutex);
8663 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8664 OUT_RING(MI_SET_CONTEXT);
8665 OUT_RING(dev_priv->renderctx->gtt_offset |
8667 MI_SAVE_EXT_STATE_EN |
8668 MI_RESTORE_EXT_STATE_EN |
8669 MI_RESTORE_INHIBIT);
8670 OUT_RING(MI_SUSPEND_FLUSH);
8676 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8677 * does an implicit flush, combined with MI_FLUSH above, it should be
8678 * safe to assume that renderctx is valid
8680 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8682 DRM_ERROR("failed to enable ironlake power power savings\n");
8683 ironlake_teardown_rc6(dev);
8684 mutex_unlock(&dev->struct_mutex);
8688 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8689 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8690 mutex_unlock(&dev->struct_mutex);
8693 void intel_init_clock_gating(struct drm_device *dev)
8695 struct drm_i915_private *dev_priv = dev->dev_private;
8697 dev_priv->display.init_clock_gating(dev);
8699 if (dev_priv->display.init_pch_clock_gating)
8700 dev_priv->display.init_pch_clock_gating(dev);
8703 /* Set up chip specific display functions */
8704 static void intel_init_display(struct drm_device *dev)
8706 struct drm_i915_private *dev_priv = dev->dev_private;
8708 /* We always want a DPMS function */
8709 if (HAS_PCH_SPLIT(dev)) {
8710 dev_priv->display.dpms = ironlake_crtc_dpms;
8711 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8712 dev_priv->display.update_plane = ironlake_update_plane;
8714 dev_priv->display.dpms = i9xx_crtc_dpms;
8715 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8716 dev_priv->display.update_plane = i9xx_update_plane;
8719 if (I915_HAS_FBC(dev)) {
8720 if (HAS_PCH_SPLIT(dev)) {
8721 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8722 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8723 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8724 } else if (IS_GM45(dev)) {
8725 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8726 dev_priv->display.enable_fbc = g4x_enable_fbc;
8727 dev_priv->display.disable_fbc = g4x_disable_fbc;
8728 } else if (IS_CRESTLINE(dev)) {
8729 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8730 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8731 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8733 /* 855GM needs testing */
8736 /* Returns the core display clock speed */
8737 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8738 dev_priv->display.get_display_clock_speed =
8739 i945_get_display_clock_speed;
8740 else if (IS_I915G(dev))
8741 dev_priv->display.get_display_clock_speed =
8742 i915_get_display_clock_speed;
8743 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8744 dev_priv->display.get_display_clock_speed =
8745 i9xx_misc_get_display_clock_speed;
8746 else if (IS_I915GM(dev))
8747 dev_priv->display.get_display_clock_speed =
8748 i915gm_get_display_clock_speed;
8749 else if (IS_I865G(dev))
8750 dev_priv->display.get_display_clock_speed =
8751 i865_get_display_clock_speed;
8752 else if (IS_I85X(dev))
8753 dev_priv->display.get_display_clock_speed =
8754 i855_get_display_clock_speed;
8756 dev_priv->display.get_display_clock_speed =
8757 i830_get_display_clock_speed;
8759 /* For FIFO watermark updates */
8760 if (HAS_PCH_SPLIT(dev)) {
8761 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8762 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8764 /* IVB configs may use multi-threaded forcewake */
8765 if (IS_IVYBRIDGE(dev)) {
8768 /* A small trick here - if the bios hasn't configured MT forcewake,
8769 * and if the device is in RC6, then force_wake_mt_get will not wake
8770 * the device and the ECOBUS read will return zero. Which will be
8771 * (correctly) interpreted by the test below as MT forcewake being
8774 mutex_lock(&dev->struct_mutex);
8775 __gen6_gt_force_wake_mt_get(dev_priv);
8776 ecobus = I915_READ_NOTRACE(ECOBUS);
8777 __gen6_gt_force_wake_mt_put(dev_priv);
8778 mutex_unlock(&dev->struct_mutex);
8780 if (ecobus & FORCEWAKE_MT_ENABLE) {
8781 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8782 dev_priv->display.force_wake_get =
8783 __gen6_gt_force_wake_mt_get;
8784 dev_priv->display.force_wake_put =
8785 __gen6_gt_force_wake_mt_put;
8789 if (HAS_PCH_IBX(dev))
8790 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8791 else if (HAS_PCH_CPT(dev))
8792 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8795 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8796 dev_priv->display.update_wm = ironlake_update_wm;
8798 DRM_DEBUG_KMS("Failed to get proper latency. "
8800 dev_priv->display.update_wm = NULL;
8802 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8803 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8804 dev_priv->display.write_eld = ironlake_write_eld;
8805 } else if (IS_GEN6(dev)) {
8806 if (SNB_READ_WM0_LATENCY()) {
8807 dev_priv->display.update_wm = sandybridge_update_wm;
8808 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8810 DRM_DEBUG_KMS("Failed to read display plane latency. "
8812 dev_priv->display.update_wm = NULL;
8814 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8815 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8816 dev_priv->display.write_eld = ironlake_write_eld;
8817 } else if (IS_IVYBRIDGE(dev)) {
8818 /* FIXME: detect B0+ stepping and use auto training */
8819 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8820 if (SNB_READ_WM0_LATENCY()) {
8821 dev_priv->display.update_wm = sandybridge_update_wm;
8822 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8824 DRM_DEBUG_KMS("Failed to read display plane latency. "
8826 dev_priv->display.update_wm = NULL;
8828 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8829 dev_priv->display.write_eld = ironlake_write_eld;
8831 dev_priv->display.update_wm = NULL;
8832 } else if (IS_PINEVIEW(dev)) {
8833 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8836 dev_priv->mem_freq)) {
8837 DRM_INFO("failed to find known CxSR latency "
8838 "(found ddr%s fsb freq %d, mem freq %d), "
8840 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8841 dev_priv->fsb_freq, dev_priv->mem_freq);
8842 /* Disable CxSR and never update its watermark again */
8843 pineview_disable_cxsr(dev);
8844 dev_priv->display.update_wm = NULL;
8846 dev_priv->display.update_wm = pineview_update_wm;
8847 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8848 } else if (IS_G4X(dev)) {
8849 dev_priv->display.write_eld = g4x_write_eld;
8850 dev_priv->display.update_wm = g4x_update_wm;
8851 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8852 } else if (IS_GEN4(dev)) {
8853 dev_priv->display.update_wm = i965_update_wm;
8854 if (IS_CRESTLINE(dev))
8855 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8856 else if (IS_BROADWATER(dev))
8857 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8858 } else if (IS_GEN3(dev)) {
8859 dev_priv->display.update_wm = i9xx_update_wm;
8860 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8861 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8862 } else if (IS_I865G(dev)) {
8863 dev_priv->display.update_wm = i830_update_wm;
8864 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8865 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8866 } else if (IS_I85X(dev)) {
8867 dev_priv->display.update_wm = i9xx_update_wm;
8868 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8869 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8871 dev_priv->display.update_wm = i830_update_wm;
8872 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8874 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8876 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8879 /* Default just returns -ENODEV to indicate unsupported */
8880 dev_priv->display.queue_flip = intel_default_queue_flip;
8882 switch (INTEL_INFO(dev)->gen) {
8884 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8888 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8893 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8897 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8900 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8906 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8907 * resume, or other times. This quirk makes sure that's the case for
8910 static void quirk_pipea_force(struct drm_device *dev)
8912 struct drm_i915_private *dev_priv = dev->dev_private;
8914 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8915 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8919 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8921 static void quirk_ssc_force_disable(struct drm_device *dev)
8923 struct drm_i915_private *dev_priv = dev->dev_private;
8924 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8927 struct intel_quirk {
8929 int subsystem_vendor;
8930 int subsystem_device;
8931 void (*hook)(struct drm_device *dev);
8934 struct intel_quirk intel_quirks[] = {
8935 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8936 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8937 /* HP Mini needs pipe A force quirk (LP: #322104) */
8938 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8940 /* Thinkpad R31 needs pipe A force quirk */
8941 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8942 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8943 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8945 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8946 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8947 /* ThinkPad X40 needs pipe A force quirk */
8949 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8950 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8952 /* 855 & before need to leave pipe A & dpll A up */
8953 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8954 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8956 /* Lenovo U160 cannot use SSC on LVDS */
8957 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8959 /* Sony Vaio Y cannot use SSC on LVDS */
8960 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8963 static void intel_init_quirks(struct drm_device *dev)
8965 struct pci_dev *d = dev->pdev;
8968 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8969 struct intel_quirk *q = &intel_quirks[i];
8971 if (d->device == q->device &&
8972 (d->subsystem_vendor == q->subsystem_vendor ||
8973 q->subsystem_vendor == PCI_ANY_ID) &&
8974 (d->subsystem_device == q->subsystem_device ||
8975 q->subsystem_device == PCI_ANY_ID))
8980 /* Disable the VGA plane that we never use */
8981 static void i915_disable_vga(struct drm_device *dev)
8983 struct drm_i915_private *dev_priv = dev->dev_private;
8987 if (HAS_PCH_SPLIT(dev))
8988 vga_reg = CPU_VGACNTRL;
8992 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8993 outb(1, VGA_SR_INDEX);
8994 sr1 = inb(VGA_SR_DATA);
8995 outb(sr1 | 1<<5, VGA_SR_DATA);
8996 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8999 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9000 POSTING_READ(vga_reg);
9003 void intel_modeset_init(struct drm_device *dev)
9005 struct drm_i915_private *dev_priv = dev->dev_private;
9008 drm_mode_config_init(dev);
9010 dev->mode_config.min_width = 0;
9011 dev->mode_config.min_height = 0;
9013 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9015 intel_init_quirks(dev);
9017 intel_init_display(dev);
9020 dev->mode_config.max_width = 2048;
9021 dev->mode_config.max_height = 2048;
9022 } else if (IS_GEN3(dev)) {
9023 dev->mode_config.max_width = 4096;
9024 dev->mode_config.max_height = 4096;
9026 dev->mode_config.max_width = 8192;
9027 dev->mode_config.max_height = 8192;
9029 dev->mode_config.fb_base = dev->agp->base;
9031 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9032 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9034 for (i = 0; i < dev_priv->num_pipe; i++) {
9035 intel_crtc_init(dev, i);
9036 ret = intel_plane_init(dev, i);
9038 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9041 /* Just disable it once at startup */
9042 i915_disable_vga(dev);
9043 intel_setup_outputs(dev);
9045 intel_init_clock_gating(dev);
9047 if (IS_IRONLAKE_M(dev)) {
9048 ironlake_enable_drps(dev);
9049 intel_init_emon(dev);
9052 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9053 gen6_enable_rps(dev_priv);
9054 gen6_update_ring_freq(dev_priv);
9057 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9058 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9059 (unsigned long)dev);
9062 void intel_modeset_gem_init(struct drm_device *dev)
9064 if (IS_IRONLAKE_M(dev))
9065 ironlake_enable_rc6(dev);
9067 intel_setup_overlay(dev);
9070 void intel_modeset_cleanup(struct drm_device *dev)
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 struct drm_crtc *crtc;
9074 struct intel_crtc *intel_crtc;
9076 drm_kms_helper_poll_fini(dev);
9077 mutex_lock(&dev->struct_mutex);
9079 intel_unregister_dsm_handler();
9082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9083 /* Skip inactive CRTCs */
9087 intel_crtc = to_intel_crtc(crtc);
9088 intel_increase_pllclock(crtc);
9091 intel_disable_fbc(dev);
9093 if (IS_IRONLAKE_M(dev))
9094 ironlake_disable_drps(dev);
9095 if (IS_GEN6(dev) || IS_GEN7(dev))
9096 gen6_disable_rps(dev);
9098 if (IS_IRONLAKE_M(dev))
9099 ironlake_disable_rc6(dev);
9101 mutex_unlock(&dev->struct_mutex);
9103 /* Disable the irq before mode object teardown, for the irq might
9104 * enqueue unpin/hotplug work. */
9105 drm_irq_uninstall(dev);
9106 cancel_work_sync(&dev_priv->hotplug_work);
9107 cancel_work_sync(&dev_priv->rps_work);
9109 /* flush any delayed tasks or pending work */
9110 flush_scheduled_work();
9112 /* Shut off idle work before the crtcs get freed. */
9113 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9114 intel_crtc = to_intel_crtc(crtc);
9115 del_timer_sync(&intel_crtc->idle_timer);
9117 del_timer_sync(&dev_priv->idle_timer);
9118 cancel_work_sync(&dev_priv->idle_work);
9120 drm_mode_config_cleanup(dev);
9124 * Return which encoder is currently attached for connector.
9126 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9128 return &intel_attached_encoder(connector)->base;
9131 void intel_connector_attach_encoder(struct intel_connector *connector,
9132 struct intel_encoder *encoder)
9134 connector->encoder = encoder;
9135 drm_mode_connector_attach_encoder(&connector->base,
9140 * set vga decode state - true == enable VGA decode
9142 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9147 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9149 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9151 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9152 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9156 #ifdef CONFIG_DEBUG_FS
9157 #include <linux/seq_file.h>
9159 struct intel_display_error_state {
9160 struct intel_cursor_error_state {
9167 struct intel_pipe_error_state {
9179 struct intel_plane_error_state {
9190 struct intel_display_error_state *
9191 intel_display_capture_error_state(struct drm_device *dev)
9193 drm_i915_private_t *dev_priv = dev->dev_private;
9194 struct intel_display_error_state *error;
9197 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9201 for (i = 0; i < 2; i++) {
9202 error->cursor[i].control = I915_READ(CURCNTR(i));
9203 error->cursor[i].position = I915_READ(CURPOS(i));
9204 error->cursor[i].base = I915_READ(CURBASE(i));
9206 error->plane[i].control = I915_READ(DSPCNTR(i));
9207 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9208 error->plane[i].size = I915_READ(DSPSIZE(i));
9209 error->plane[i].pos = I915_READ(DSPPOS(i));
9210 error->plane[i].addr = I915_READ(DSPADDR(i));
9211 if (INTEL_INFO(dev)->gen >= 4) {
9212 error->plane[i].surface = I915_READ(DSPSURF(i));
9213 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9216 error->pipe[i].conf = I915_READ(PIPECONF(i));
9217 error->pipe[i].source = I915_READ(PIPESRC(i));
9218 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9219 error->pipe[i].hblank = I915_READ(HBLANK(i));
9220 error->pipe[i].hsync = I915_READ(HSYNC(i));
9221 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9222 error->pipe[i].vblank = I915_READ(VBLANK(i));
9223 error->pipe[i].vsync = I915_READ(VSYNC(i));
9230 intel_display_print_error_state(struct seq_file *m,
9231 struct drm_device *dev,
9232 struct intel_display_error_state *error)
9236 for (i = 0; i < 2; i++) {
9237 seq_printf(m, "Pipe [%d]:\n", i);
9238 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9239 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9240 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9241 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9242 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9243 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9244 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9245 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9247 seq_printf(m, "Plane [%d]:\n", i);
9248 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9249 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9250 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9251 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9252 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9253 if (INTEL_INFO(dev)->gen >= 4) {
9254 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9255 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9258 seq_printf(m, "Cursor [%d]:\n", i);
9259 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9260 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9261 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);