drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         WARN(1, "pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         WARN(1, "pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380              && (val & DP_PIPEB_SELECT),
1381              "IBX PCH dp port still using transcoder B\n");
1382 }
1383
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385                                      enum pipe pipe, int reg)
1386 {
1387         u32 val = I915_READ(reg);
1388         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390              reg, pipe_name(pipe));
1391
1392         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393              && (val & SDVO_PIPE_B_SELECT),
1394              "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398                                       enum pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406
1407         reg = PCH_ADPA;
1408         val = I915_READ(reg);
1409         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410              "PCH VGA enabled on transcoder %c, should be disabled\n",
1411              pipe_name(pipe));
1412
1413         reg = PCH_LVDS;
1414         val = I915_READ(reg);
1415         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417              pipe_name(pipe));
1418
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423
1424 /**
1425  * intel_enable_pll - enable a PLL
1426  * @dev_priv: i915 private structure
1427  * @pipe: pipe PLL to enable
1428  *
1429  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1430  * make sure the PLL reg is writable first though, since the panel write
1431  * protect mechanism may be enabled.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  *
1435  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1436  */
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 {
1439         int reg;
1440         u32 val;
1441
1442         /* No really, not for ILK+ */
1443         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444
1445         /* PLL is protected by panel, make sure we can write it */
1446         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447                 assert_panel_unlocked(dev_priv, pipe);
1448
1449         reg = DPLL(pipe);
1450         val = I915_READ(reg);
1451         val |= DPLL_VCO_ENABLE;
1452
1453         /* We do this three times for luck */
1454         I915_WRITE(reg, val);
1455         POSTING_READ(reg);
1456         udelay(150); /* wait for warmup */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463 }
1464
1465 /**
1466  * intel_disable_pll - disable a PLL
1467  * @dev_priv: i915 private structure
1468  * @pipe: pipe PLL to disable
1469  *
1470  * Disable the PLL for @pipe, making sure the pipe is off first.
1471  *
1472  * Note!  This is for pre-ILK only.
1473  */
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475 {
1476         int reg;
1477         u32 val;
1478
1479         /* Don't disable pipe A or pipe A PLLs if needed */
1480         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481                 return;
1482
1483         /* Make sure the pipe isn't still relying on us */
1484         assert_pipe_disabled(dev_priv, pipe);
1485
1486         reg = DPLL(pipe);
1487         val = I915_READ(reg);
1488         val &= ~DPLL_VCO_ENABLE;
1489         I915_WRITE(reg, val);
1490         POSTING_READ(reg);
1491 }
1492
1493 /* SBI access */
1494 static void
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496 {
1497         unsigned long flags;
1498
1499         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1501                                 100)) {
1502                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503                 goto out_unlock;
1504         }
1505
1506         I915_WRITE(SBI_ADDR,
1507                         (reg << 16));
1508         I915_WRITE(SBI_DATA,
1509                         value);
1510         I915_WRITE(SBI_CTL_STAT,
1511                         SBI_BUSY |
1512                         SBI_CTL_OP_CRWR);
1513
1514         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515                                 100)) {
1516                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517                 goto out_unlock;
1518         }
1519
1520 out_unlock:
1521         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522 }
1523
1524 static u32
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526 {
1527         unsigned long flags;
1528         u32 value = 0;
1529
1530         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1532                                 100)) {
1533                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534                 goto out_unlock;
1535         }
1536
1537         I915_WRITE(SBI_ADDR,
1538                         (reg << 16));
1539         I915_WRITE(SBI_CTL_STAT,
1540                         SBI_BUSY |
1541                         SBI_CTL_OP_CRRD);
1542
1543         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544                                 100)) {
1545                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546                 goto out_unlock;
1547         }
1548
1549         value = I915_READ(SBI_DATA);
1550
1551 out_unlock:
1552         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553         return value;
1554 }
1555
1556 /**
1557  * intel_enable_pch_pll - enable PCH PLL
1558  * @dev_priv: i915 private structure
1559  * @pipe: pipe PLL to enable
1560  *
1561  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562  * drives the transcoder clock.
1563  */
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1565 {
1566         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567         struct intel_pch_pll *pll;
1568         int reg;
1569         u32 val;
1570
1571         /* PCH PLLs only available on ILK, SNB and IVB */
1572         BUG_ON(dev_priv->info->gen < 5);
1573         pll = intel_crtc->pch_pll;
1574         if (pll == NULL)
1575                 return;
1576
1577         if (WARN_ON(pll->refcount == 0))
1578                 return;
1579
1580         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581                       pll->pll_reg, pll->active, pll->on,
1582                       intel_crtc->base.base.id);
1583
1584         /* PCH refclock must be enabled first */
1585         assert_pch_refclk_enabled(dev_priv);
1586
1587         if (pll->active++ && pll->on) {
1588                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1589                 return;
1590         }
1591
1592         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594         reg = pll->pll_reg;
1595         val = I915_READ(reg);
1596         val |= DPLL_VCO_ENABLE;
1597         I915_WRITE(reg, val);
1598         POSTING_READ(reg);
1599         udelay(200);
1600
1601         pll->on = true;
1602 }
1603
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1605 {
1606         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1608         int reg;
1609         u32 val;
1610
1611         /* PCH only available on ILK+ */
1612         BUG_ON(dev_priv->info->gen < 5);
1613         if (pll == NULL)
1614                return;
1615
1616         if (WARN_ON(pll->refcount == 0))
1617                 return;
1618
1619         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620                       pll->pll_reg, pll->active, pll->on,
1621                       intel_crtc->base.base.id);
1622
1623         if (WARN_ON(pll->active == 0)) {
1624                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1625                 return;
1626         }
1627
1628         if (--pll->active) {
1629                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1630                 return;
1631         }
1632
1633         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635         /* Make sure transcoder isn't still depending on us */
1636         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637
1638         reg = pll->pll_reg;
1639         val = I915_READ(reg);
1640         val &= ~DPLL_VCO_ENABLE;
1641         I915_WRITE(reg, val);
1642         POSTING_READ(reg);
1643         udelay(200);
1644
1645         pll->on = false;
1646 }
1647
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649                                     enum pipe pipe)
1650 {
1651         int reg;
1652         u32 val, pipeconf_val;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654
1655         /* PCH only available on ILK+ */
1656         BUG_ON(dev_priv->info->gen < 5);
1657
1658         /* Make sure PCH DPLL is enabled */
1659         assert_pch_pll_enabled(dev_priv,
1660                                to_intel_crtc(crtc)->pch_pll,
1661                                to_intel_crtc(crtc));
1662
1663         /* FDI must be feeding us bits for PCH ports */
1664         assert_fdi_tx_enabled(dev_priv, pipe);
1665         assert_fdi_rx_enabled(dev_priv, pipe);
1666
1667         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669                 return;
1670         }
1671         reg = TRANSCONF(pipe);
1672         val = I915_READ(reg);
1673         pipeconf_val = I915_READ(PIPECONF(pipe));
1674
1675         if (HAS_PCH_IBX(dev_priv->dev)) {
1676                 /*
1677                  * make the BPC in transcoder be consistent with
1678                  * that in pipeconf reg.
1679                  */
1680                 val &= ~PIPE_BPC_MASK;
1681                 val |= pipeconf_val & PIPE_BPC_MASK;
1682         }
1683
1684         val &= ~TRANS_INTERLACE_MASK;
1685         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686                 if (HAS_PCH_IBX(dev_priv->dev) &&
1687                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688                         val |= TRANS_LEGACY_INTERLACED_ILK;
1689                 else
1690                         val |= TRANS_INTERLACED;
1691         else
1692                 val |= TRANS_PROGRESSIVE;
1693
1694         I915_WRITE(reg, val | TRANS_ENABLE);
1695         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 }
1698
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700                                      enum pipe pipe)
1701 {
1702         int reg;
1703         u32 val;
1704
1705         /* FDI relies on the transcoder */
1706         assert_fdi_tx_disabled(dev_priv, pipe);
1707         assert_fdi_rx_disabled(dev_priv, pipe);
1708
1709         /* Ports must be off as well */
1710         assert_pch_ports_disabled(dev_priv, pipe);
1711
1712         reg = TRANSCONF(pipe);
1713         val = I915_READ(reg);
1714         val &= ~TRANS_ENABLE;
1715         I915_WRITE(reg, val);
1716         /* wait for PCH transcoder off, transcoder state */
1717         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1719 }
1720
1721 /**
1722  * intel_enable_pipe - enable a pipe, asserting requirements
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe to enable
1725  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1726  *
1727  * Enable @pipe, making sure that various hardware specific requirements
1728  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729  *
1730  * @pipe should be %PIPE_A or %PIPE_B.
1731  *
1732  * Will wait until the pipe is actually running (i.e. first vblank) before
1733  * returning.
1734  */
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736                               bool pch_port)
1737 {
1738         int reg;
1739         u32 val;
1740
1741         /*
1742          * A pipe without a PLL won't actually be able to drive bits from
1743          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1744          * need the check.
1745          */
1746         if (!HAS_PCH_SPLIT(dev_priv->dev))
1747                 assert_pll_enabled(dev_priv, pipe);
1748         else {
1749                 if (pch_port) {
1750                         /* if driving the PCH, we need FDI enabled */
1751                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753                 }
1754                 /* FIXME: assert CPU port conditions for SNB+ */
1755         }
1756
1757         reg = PIPECONF(pipe);
1758         val = I915_READ(reg);
1759         if (val & PIPECONF_ENABLE)
1760                 return;
1761
1762         I915_WRITE(reg, val | PIPECONF_ENABLE);
1763         intel_wait_for_vblank(dev_priv->dev, pipe);
1764 }
1765
1766 /**
1767  * intel_disable_pipe - disable a pipe, asserting requirements
1768  * @dev_priv: i915 private structure
1769  * @pipe: pipe to disable
1770  *
1771  * Disable @pipe, making sure that various hardware specific requirements
1772  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773  *
1774  * @pipe should be %PIPE_A or %PIPE_B.
1775  *
1776  * Will wait until the pipe has shut down before returning.
1777  */
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779                                enum pipe pipe)
1780 {
1781         int reg;
1782         u32 val;
1783
1784         /*
1785          * Make sure planes won't keep trying to pump pixels to us,
1786          * or we might hang the display.
1787          */
1788         assert_planes_disabled(dev_priv, pipe);
1789
1790         /* Don't disable pipe A or pipe A PLLs if needed */
1791         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792                 return;
1793
1794         reg = PIPECONF(pipe);
1795         val = I915_READ(reg);
1796         if ((val & PIPECONF_ENABLE) == 0)
1797                 return;
1798
1799         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801 }
1802
1803 /*
1804  * Plane regs are double buffered, going from enabled->disabled needs a
1805  * trigger in order to latch.  The display address reg provides this.
1806  */
1807 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808                                       enum plane plane)
1809 {
1810         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812 }
1813
1814 /**
1815  * intel_enable_plane - enable a display plane on a given pipe
1816  * @dev_priv: i915 private structure
1817  * @plane: plane to enable
1818  * @pipe: pipe being fed
1819  *
1820  * Enable @plane on @pipe, making sure that @pipe is running first.
1821  */
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823                                enum plane plane, enum pipe pipe)
1824 {
1825         int reg;
1826         u32 val;
1827
1828         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829         assert_pipe_enabled(dev_priv, pipe);
1830
1831         reg = DSPCNTR(plane);
1832         val = I915_READ(reg);
1833         if (val & DISPLAY_PLANE_ENABLE)
1834                 return;
1835
1836         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837         intel_flush_display_plane(dev_priv, plane);
1838         intel_wait_for_vblank(dev_priv->dev, pipe);
1839 }
1840
1841 /**
1842  * intel_disable_plane - disable a display plane
1843  * @dev_priv: i915 private structure
1844  * @plane: plane to disable
1845  * @pipe: pipe consuming the data
1846  *
1847  * Disable @plane; should be an independent operation.
1848  */
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850                                 enum plane plane, enum pipe pipe)
1851 {
1852         int reg;
1853         u32 val;
1854
1855         reg = DSPCNTR(plane);
1856         val = I915_READ(reg);
1857         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858                 return;
1859
1860         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861         intel_flush_display_plane(dev_priv, plane);
1862         intel_wait_for_vblank(dev_priv->dev, pipe);
1863 }
1864
1865 int
1866 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867                            struct drm_i915_gem_object *obj,
1868                            struct intel_ring_buffer *pipelined)
1869 {
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         u32 alignment;
1872         int ret;
1873
1874         switch (obj->tiling_mode) {
1875         case I915_TILING_NONE:
1876                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877                         alignment = 128 * 1024;
1878                 else if (INTEL_INFO(dev)->gen >= 4)
1879                         alignment = 4 * 1024;
1880                 else
1881                         alignment = 64 * 1024;
1882                 break;
1883         case I915_TILING_X:
1884                 /* pin() will align the object as required by fence */
1885                 alignment = 0;
1886                 break;
1887         case I915_TILING_Y:
1888                 /* FIXME: Is this true? */
1889                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890                 return -EINVAL;
1891         default:
1892                 BUG();
1893         }
1894
1895         dev_priv->mm.interruptible = false;
1896         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1897         if (ret)
1898                 goto err_interruptible;
1899
1900         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901          * fence, whereas 965+ only requires a fence if using
1902          * framebuffer compression.  For simplicity, we always install
1903          * a fence as the cost is not that onerous.
1904          */
1905         ret = i915_gem_object_get_fence(obj);
1906         if (ret)
1907                 goto err_unpin;
1908
1909         i915_gem_object_pin_fence(obj);
1910
1911         dev_priv->mm.interruptible = true;
1912         return 0;
1913
1914 err_unpin:
1915         i915_gem_object_unpin(obj);
1916 err_interruptible:
1917         dev_priv->mm.interruptible = true;
1918         return ret;
1919 }
1920
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922 {
1923         i915_gem_object_unpin_fence(obj);
1924         i915_gem_object_unpin(obj);
1925 }
1926
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928  * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930                                                         unsigned int bpp,
1931                                                         unsigned int pitch)
1932 {
1933         int tile_rows, tiles;
1934
1935         tile_rows = *y / 8;
1936         *y %= 8;
1937         tiles = *x / (512/bpp);
1938         *x %= 512/bpp;
1939
1940         return tile_rows * pitch * 8 + tiles * 4096;
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944                              int x, int y)
1945 {
1946         struct drm_device *dev = crtc->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949         struct intel_framebuffer *intel_fb;
1950         struct drm_i915_gem_object *obj;
1951         int plane = intel_crtc->plane;
1952         unsigned long linear_offset;
1953         u32 dspcntr;
1954         u32 reg;
1955
1956         switch (plane) {
1957         case 0:
1958         case 1:
1959                 break;
1960         default:
1961                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962                 return -EINVAL;
1963         }
1964
1965         intel_fb = to_intel_framebuffer(fb);
1966         obj = intel_fb->obj;
1967
1968         reg = DSPCNTR(plane);
1969         dspcntr = I915_READ(reg);
1970         /* Mask out pixel format bits in case we change it */
1971         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972         switch (fb->bits_per_pixel) {
1973         case 8:
1974                 dspcntr |= DISPPLANE_8BPP;
1975                 break;
1976         case 16:
1977                 if (fb->depth == 15)
1978                         dspcntr |= DISPPLANE_15_16BPP;
1979                 else
1980                         dspcntr |= DISPPLANE_16BPP;
1981                 break;
1982         case 24:
1983         case 32:
1984                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985                 break;
1986         default:
1987                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988                 return -EINVAL;
1989         }
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 if (obj->tiling_mode != I915_TILING_NONE)
1992                         dspcntr |= DISPPLANE_TILED;
1993                 else
1994                         dspcntr &= ~DISPPLANE_TILED;
1995         }
1996
1997         I915_WRITE(reg, dspcntr);
1998
1999         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2000
2001         if (INTEL_INFO(dev)->gen >= 4) {
2002                 intel_crtc->dspaddr_offset =
2003                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004                                                            fb->bits_per_pixel / 8,
2005                                                            fb->pitches[0]);
2006                 linear_offset -= intel_crtc->dspaddr_offset;
2007         } else {
2008                 intel_crtc->dspaddr_offset = linear_offset;
2009         }
2010
2011         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014         if (INTEL_INFO(dev)->gen >= 4) {
2015                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2017                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2019         } else
2020                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2021         POSTING_READ(reg);
2022
2023         return 0;
2024 }
2025
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027                                  struct drm_framebuffer *fb, int x, int y)
2028 {
2029         struct drm_device *dev = crtc->dev;
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032         struct intel_framebuffer *intel_fb;
2033         struct drm_i915_gem_object *obj;
2034         int plane = intel_crtc->plane;
2035         unsigned long linear_offset;
2036         u32 dspcntr;
2037         u32 reg;
2038
2039         switch (plane) {
2040         case 0:
2041         case 1:
2042         case 2:
2043                 break;
2044         default:
2045                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046                 return -EINVAL;
2047         }
2048
2049         intel_fb = to_intel_framebuffer(fb);
2050         obj = intel_fb->obj;
2051
2052         reg = DSPCNTR(plane);
2053         dspcntr = I915_READ(reg);
2054         /* Mask out pixel format bits in case we change it */
2055         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056         switch (fb->bits_per_pixel) {
2057         case 8:
2058                 dspcntr |= DISPPLANE_8BPP;
2059                 break;
2060         case 16:
2061                 if (fb->depth != 16)
2062                         return -EINVAL;
2063
2064                 dspcntr |= DISPPLANE_16BPP;
2065                 break;
2066         case 24:
2067         case 32:
2068                 if (fb->depth == 24)
2069                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070                 else if (fb->depth == 30)
2071                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072                 else
2073                         return -EINVAL;
2074                 break;
2075         default:
2076                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077                 return -EINVAL;
2078         }
2079
2080         if (obj->tiling_mode != I915_TILING_NONE)
2081                 dspcntr |= DISPPLANE_TILED;
2082         else
2083                 dspcntr &= ~DISPPLANE_TILED;
2084
2085         /* must disable */
2086         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088         I915_WRITE(reg, dspcntr);
2089
2090         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091         intel_crtc->dspaddr_offset =
2092                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093                                                    fb->bits_per_pixel / 8,
2094                                                    fb->pitches[0]);
2095         linear_offset -= intel_crtc->dspaddr_offset;
2096
2097         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100         I915_MODIFY_DISPBASE(DSPSURF(plane),
2101                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2102         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103         I915_WRITE(DSPLINOFF(plane), linear_offset);
2104         POSTING_READ(reg);
2105
2106         return 0;
2107 }
2108
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2110 static int
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112                            int x, int y, enum mode_set_atomic state)
2113 {
2114         struct drm_device *dev = crtc->dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116
2117         if (dev_priv->display.disable_fbc)
2118                 dev_priv->display.disable_fbc(dev);
2119         intel_increase_pllclock(crtc);
2120
2121         return dev_priv->display.update_plane(crtc, fb, x, y);
2122 }
2123
2124 static int
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2126 {
2127         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129         bool was_interruptible = dev_priv->mm.interruptible;
2130         int ret;
2131
2132         wait_event(dev_priv->pending_flip_queue,
2133                    atomic_read(&dev_priv->mm.wedged) ||
2134                    atomic_read(&obj->pending_flip) == 0);
2135
2136         /* Big Hammer, we also need to ensure that any pending
2137          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138          * current scanout is retired before unpinning the old
2139          * framebuffer.
2140          *
2141          * This should only fail upon a hung GPU, in which case we
2142          * can safely continue.
2143          */
2144         dev_priv->mm.interruptible = false;
2145         ret = i915_gem_object_finish_gpu(obj);
2146         dev_priv->mm.interruptible = was_interruptible;
2147
2148         return ret;
2149 }
2150
2151 static int
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153                     struct drm_framebuffer *fb)
2154 {
2155         struct drm_device *dev = crtc->dev;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         struct drm_i915_master_private *master_priv;
2158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159         struct drm_framebuffer *old_fb;
2160         int ret;
2161
2162         /* no fb bound */
2163         if (!fb) {
2164                 DRM_ERROR("No FB bound\n");
2165                 return 0;
2166         }
2167
2168         if(intel_crtc->plane > dev_priv->num_pipe) {
2169                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170                                 intel_crtc->plane,
2171                                 dev_priv->num_pipe);
2172                 return -EINVAL;
2173         }
2174
2175         mutex_lock(&dev->struct_mutex);
2176         ret = intel_pin_and_fence_fb_obj(dev,
2177                                          to_intel_framebuffer(fb)->obj,
2178                                          NULL);
2179         if (ret != 0) {
2180                 mutex_unlock(&dev->struct_mutex);
2181                 DRM_ERROR("pin & fence failed\n");
2182                 return ret;
2183         }
2184
2185         if (crtc->fb)
2186                 intel_finish_fb(crtc->fb);
2187
2188         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2189         if (ret) {
2190                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191                 mutex_unlock(&dev->struct_mutex);
2192                 DRM_ERROR("failed to update base address\n");
2193                 return ret;
2194         }
2195
2196         old_fb = crtc->fb;
2197         crtc->fb = fb;
2198         crtc->x = x;
2199         crtc->y = y;
2200
2201         if (old_fb) {
2202                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2203                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2204         }
2205
2206         intel_update_fbc(dev);
2207         mutex_unlock(&dev->struct_mutex);
2208
2209         if (!dev->primary->master)
2210                 return 0;
2211
2212         master_priv = dev->primary->master->driver_priv;
2213         if (!master_priv->sarea_priv)
2214                 return 0;
2215
2216         if (intel_crtc->pipe) {
2217                 master_priv->sarea_priv->pipeB_x = x;
2218                 master_priv->sarea_priv->pipeB_y = y;
2219         } else {
2220                 master_priv->sarea_priv->pipeA_x = x;
2221                 master_priv->sarea_priv->pipeA_y = y;
2222         }
2223
2224         return 0;
2225 }
2226
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         u32 dpa_ctl;
2232
2233         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234         dpa_ctl = I915_READ(DP_A);
2235         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237         if (clock < 200000) {
2238                 u32 temp;
2239                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240                 /* workaround for 160Mhz:
2241                    1) program 0x4600c bits 15:0 = 0x8124
2242                    2) program 0x46010 bit 0 = 1
2243                    3) program 0x46034 bit 24 = 1
2244                    4) program 0x64000 bit 14 = 1
2245                    */
2246                 temp = I915_READ(0x4600c);
2247                 temp &= 0xffff0000;
2248                 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250                 temp = I915_READ(0x46010);
2251                 I915_WRITE(0x46010, temp | 1);
2252
2253                 temp = I915_READ(0x46034);
2254                 I915_WRITE(0x46034, temp | (1 << 24));
2255         } else {
2256                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257         }
2258         I915_WRITE(DP_A, dpa_ctl);
2259
2260         POSTING_READ(DP_A);
2261         udelay(500);
2262 }
2263
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269         int pipe = intel_crtc->pipe;
2270         u32 reg, temp;
2271
2272         /* enable normal train */
2273         reg = FDI_TX_CTL(pipe);
2274         temp = I915_READ(reg);
2275         if (IS_IVYBRIDGE(dev)) {
2276                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2278         } else {
2279                 temp &= ~FDI_LINK_TRAIN_NONE;
2280                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2281         }
2282         I915_WRITE(reg, temp);
2283
2284         reg = FDI_RX_CTL(pipe);
2285         temp = I915_READ(reg);
2286         if (HAS_PCH_CPT(dev)) {
2287                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289         } else {
2290                 temp &= ~FDI_LINK_TRAIN_NONE;
2291                 temp |= FDI_LINK_TRAIN_NONE;
2292         }
2293         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295         /* wait one idle pattern time */
2296         POSTING_READ(reg);
2297         udelay(1000);
2298
2299         /* IVB wants error correction enabled */
2300         if (IS_IVYBRIDGE(dev))
2301                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302                            FDI_FE_ERRC_ENABLE);
2303 }
2304
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306 {
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308         u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310         flags |= FDI_PHASE_SYNC_OVR(pipe);
2311         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312         flags |= FDI_PHASE_SYNC_EN(pipe);
2313         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314         POSTING_READ(SOUTH_CHICKEN1);
2315 }
2316
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319 {
2320         struct drm_device *dev = crtc->dev;
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         int plane = intel_crtc->plane;
2325         u32 reg, temp, tries;
2326
2327         /* FDI needs bits from pipe & plane first */
2328         assert_pipe_enabled(dev_priv, pipe);
2329         assert_plane_enabled(dev_priv, plane);
2330
2331         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332            for train result */
2333         reg = FDI_RX_IMR(pipe);
2334         temp = I915_READ(reg);
2335         temp &= ~FDI_RX_SYMBOL_LOCK;
2336         temp &= ~FDI_RX_BIT_LOCK;
2337         I915_WRITE(reg, temp);
2338         I915_READ(reg);
2339         udelay(150);
2340
2341         /* enable CPU FDI TX and PCH FDI RX */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         temp &= ~(7 << 19);
2345         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346         temp &= ~FDI_LINK_TRAIN_NONE;
2347         temp |= FDI_LINK_TRAIN_PATTERN_1;
2348         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2349
2350         reg = FDI_RX_CTL(pipe);
2351         temp = I915_READ(reg);
2352         temp &= ~FDI_LINK_TRAIN_NONE;
2353         temp |= FDI_LINK_TRAIN_PATTERN_1;
2354         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356         POSTING_READ(reg);
2357         udelay(150);
2358
2359         /* Ironlake workaround, enable clock pointer after FDI enable*/
2360         if (HAS_PCH_IBX(dev)) {
2361                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363                            FDI_RX_PHASE_SYNC_POINTER_EN);
2364         }
2365
2366         reg = FDI_RX_IIR(pipe);
2367         for (tries = 0; tries < 5; tries++) {
2368                 temp = I915_READ(reg);
2369                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371                 if ((temp & FDI_RX_BIT_LOCK)) {
2372                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2373                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374                         break;
2375                 }
2376         }
2377         if (tries == 5)
2378                 DRM_ERROR("FDI train 1 fail!\n");
2379
2380         /* Train 2 */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_LINK_TRAIN_NONE;
2384         temp |= FDI_LINK_TRAIN_PATTERN_2;
2385         I915_WRITE(reg, temp);
2386
2387         reg = FDI_RX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_LINK_TRAIN_NONE;
2390         temp |= FDI_LINK_TRAIN_PATTERN_2;
2391         I915_WRITE(reg, temp);
2392
2393         POSTING_READ(reg);
2394         udelay(150);
2395
2396         reg = FDI_RX_IIR(pipe);
2397         for (tries = 0; tries < 5; tries++) {
2398                 temp = I915_READ(reg);
2399                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401                 if (temp & FDI_RX_SYMBOL_LOCK) {
2402                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2404                         break;
2405                 }
2406         }
2407         if (tries == 5)
2408                 DRM_ERROR("FDI train 2 fail!\n");
2409
2410         DRM_DEBUG_KMS("FDI train done\n");
2411
2412 }
2413
2414 static const int snb_b_fdi_train_param[] = {
2415         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419 };
2420
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423 {
2424         struct drm_device *dev = crtc->dev;
2425         struct drm_i915_private *dev_priv = dev->dev_private;
2426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427         int pipe = intel_crtc->pipe;
2428         u32 reg, temp, i, retry;
2429
2430         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431            for train result */
2432         reg = FDI_RX_IMR(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_RX_SYMBOL_LOCK;
2435         temp &= ~FDI_RX_BIT_LOCK;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         /* enable CPU FDI TX and PCH FDI RX */
2442         reg = FDI_TX_CTL(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~(7 << 19);
2445         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446         temp &= ~FDI_LINK_TRAIN_NONE;
2447         temp |= FDI_LINK_TRAIN_PATTERN_1;
2448         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449         /* SNB-B */
2450         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2452
2453         reg = FDI_RX_CTL(pipe);
2454         temp = I915_READ(reg);
2455         if (HAS_PCH_CPT(dev)) {
2456                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458         } else {
2459                 temp &= ~FDI_LINK_TRAIN_NONE;
2460                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461         }
2462         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464         POSTING_READ(reg);
2465         udelay(150);
2466
2467         if (HAS_PCH_CPT(dev))
2468                 cpt_phase_pointer_enable(dev, pipe);
2469
2470         for (i = 0; i < 4; i++) {
2471                 reg = FDI_TX_CTL(pipe);
2472                 temp = I915_READ(reg);
2473                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474                 temp |= snb_b_fdi_train_param[i];
2475                 I915_WRITE(reg, temp);
2476
2477                 POSTING_READ(reg);
2478                 udelay(500);
2479
2480                 for (retry = 0; retry < 5; retry++) {
2481                         reg = FDI_RX_IIR(pipe);
2482                         temp = I915_READ(reg);
2483                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484                         if (temp & FDI_RX_BIT_LOCK) {
2485                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487                                 break;
2488                         }
2489                         udelay(50);
2490                 }
2491                 if (retry < 5)
2492                         break;
2493         }
2494         if (i == 4)
2495                 DRM_ERROR("FDI train 1 fail!\n");
2496
2497         /* Train 2 */
2498         reg = FDI_TX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_2;
2502         if (IS_GEN6(dev)) {
2503                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504                 /* SNB-B */
2505                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506         }
2507         I915_WRITE(reg, temp);
2508
2509         reg = FDI_RX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         if (HAS_PCH_CPT(dev)) {
2512                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514         } else {
2515                 temp &= ~FDI_LINK_TRAIN_NONE;
2516                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517         }
2518         I915_WRITE(reg, temp);
2519
2520         POSTING_READ(reg);
2521         udelay(150);
2522
2523         for (i = 0; i < 4; i++) {
2524                 reg = FDI_TX_CTL(pipe);
2525                 temp = I915_READ(reg);
2526                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527                 temp |= snb_b_fdi_train_param[i];
2528                 I915_WRITE(reg, temp);
2529
2530                 POSTING_READ(reg);
2531                 udelay(500);
2532
2533                 for (retry = 0; retry < 5; retry++) {
2534                         reg = FDI_RX_IIR(pipe);
2535                         temp = I915_READ(reg);
2536                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537                         if (temp & FDI_RX_SYMBOL_LOCK) {
2538                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540                                 break;
2541                         }
2542                         udelay(50);
2543                 }
2544                 if (retry < 5)
2545                         break;
2546         }
2547         if (i == 4)
2548                 DRM_ERROR("FDI train 2 fail!\n");
2549
2550         DRM_DEBUG_KMS("FDI train done.\n");
2551 }
2552
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555 {
2556         struct drm_device *dev = crtc->dev;
2557         struct drm_i915_private *dev_priv = dev->dev_private;
2558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559         int pipe = intel_crtc->pipe;
2560         u32 reg, temp, i;
2561
2562         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563            for train result */
2564         reg = FDI_RX_IMR(pipe);
2565         temp = I915_READ(reg);
2566         temp &= ~FDI_RX_SYMBOL_LOCK;
2567         temp &= ~FDI_RX_BIT_LOCK;
2568         I915_WRITE(reg, temp);
2569
2570         POSTING_READ(reg);
2571         udelay(150);
2572
2573         /* enable CPU FDI TX and PCH FDI RX */
2574         reg = FDI_TX_CTL(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~(7 << 19);
2577         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582         temp |= FDI_COMPOSITE_SYNC;
2583         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585         reg = FDI_RX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~FDI_LINK_TRAIN_AUTO;
2588         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590         temp |= FDI_COMPOSITE_SYNC;
2591         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593         POSTING_READ(reg);
2594         udelay(150);
2595
2596         if (HAS_PCH_CPT(dev))
2597                 cpt_phase_pointer_enable(dev, pipe);
2598
2599         for (i = 0; i < 4; i++) {
2600                 reg = FDI_TX_CTL(pipe);
2601                 temp = I915_READ(reg);
2602                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603                 temp |= snb_b_fdi_train_param[i];
2604                 I915_WRITE(reg, temp);
2605
2606                 POSTING_READ(reg);
2607                 udelay(500);
2608
2609                 reg = FDI_RX_IIR(pipe);
2610                 temp = I915_READ(reg);
2611                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613                 if (temp & FDI_RX_BIT_LOCK ||
2614                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2617                         break;
2618                 }
2619         }
2620         if (i == 4)
2621                 DRM_ERROR("FDI train 1 fail!\n");
2622
2623         /* Train 2 */
2624         reg = FDI_TX_CTL(pipe);
2625         temp = I915_READ(reg);
2626         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630         I915_WRITE(reg, temp);
2631
2632         reg = FDI_RX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636         I915_WRITE(reg, temp);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         for (i = 0; i < 4; i++) {
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 temp |= snb_b_fdi_train_param[i];
2646                 I915_WRITE(reg, temp);
2647
2648                 POSTING_READ(reg);
2649                 udelay(500);
2650
2651                 reg = FDI_RX_IIR(pipe);
2652                 temp = I915_READ(reg);
2653                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655                 if (temp & FDI_RX_SYMBOL_LOCK) {
2656                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 2 fail!\n");
2663
2664         DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2668 {
2669         struct drm_device *dev = intel_crtc->base.dev;
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         int pipe = intel_crtc->pipe;
2672         u32 reg, temp;
2673
2674         /* Write the TU size bits so error detection works */
2675         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2677
2678         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679         reg = FDI_RX_CTL(pipe);
2680         temp = I915_READ(reg);
2681         temp &= ~((0x7 << 19) | (0x7 << 16));
2682         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686         POSTING_READ(reg);
2687         udelay(200);
2688
2689         /* Switch from Rawclk to PCDclk */
2690         temp = I915_READ(reg);
2691         I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693         POSTING_READ(reg);
2694         udelay(200);
2695
2696         /* On Haswell, the PLL configuration for ports and pipes is handled
2697          * separately, as part of DDI setup */
2698         if (!IS_HASWELL(dev)) {
2699                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700                 reg = FDI_TX_CTL(pipe);
2701                 temp = I915_READ(reg);
2702                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2704
2705                         POSTING_READ(reg);
2706                         udelay(100);
2707                 }
2708         }
2709 }
2710
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712 {
2713         struct drm_device *dev = intel_crtc->base.dev;
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* Switch from PCDclk to Rawclk */
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723         /* Disable CPU FDI TX PLL */
2724         reg = FDI_TX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728         POSTING_READ(reg);
2729         udelay(100);
2730
2731         reg = FDI_RX_CTL(pipe);
2732         temp = I915_READ(reg);
2733         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735         /* Wait for the clocks to turn off. */
2736         POSTING_READ(reg);
2737         udelay(100);
2738 }
2739
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741 {
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749         POSTING_READ(SOUTH_CHICKEN1);
2750 }
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756         int pipe = intel_crtc->pipe;
2757         u32 reg, temp;
2758
2759         /* disable CPU FDI tx and PCH FDI rx */
2760         reg = FDI_TX_CTL(pipe);
2761         temp = I915_READ(reg);
2762         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763         POSTING_READ(reg);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~(0x7 << 16);
2768         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771         POSTING_READ(reg);
2772         udelay(100);
2773
2774         /* Ironlake workaround, disable clock pointer after downing FDI */
2775         if (HAS_PCH_IBX(dev)) {
2776                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778                            I915_READ(FDI_RX_CHICKEN(pipe) &
2779                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780         } else if (HAS_PCH_CPT(dev)) {
2781                 cpt_phase_pointer_disable(dev, pipe);
2782         }
2783
2784         /* still set train pattern 1 */
2785         reg = FDI_TX_CTL(pipe);
2786         temp = I915_READ(reg);
2787         temp &= ~FDI_LINK_TRAIN_NONE;
2788         temp |= FDI_LINK_TRAIN_PATTERN_1;
2789         I915_WRITE(reg, temp);
2790
2791         reg = FDI_RX_CTL(pipe);
2792         temp = I915_READ(reg);
2793         if (HAS_PCH_CPT(dev)) {
2794                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796         } else {
2797                 temp &= ~FDI_LINK_TRAIN_NONE;
2798                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         }
2800         /* BPC in FDI rx is consistent with that in PIPECONF */
2801         temp &= ~(0x07 << 16);
2802         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803         I915_WRITE(reg, temp);
2804
2805         POSTING_READ(reg);
2806         udelay(100);
2807 }
2808
2809 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2810 {
2811         struct drm_device *dev = crtc->dev;
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813         unsigned long flags;
2814         bool pending;
2815
2816         if (atomic_read(&dev_priv->mm.wedged))
2817                 return false;
2818
2819         spin_lock_irqsave(&dev->event_lock, flags);
2820         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821         spin_unlock_irqrestore(&dev->event_lock, flags);
2822
2823         return pending;
2824 }
2825
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830
2831         if (crtc->fb == NULL)
2832                 return;
2833
2834         wait_event(dev_priv->pending_flip_queue,
2835                    !intel_crtc_has_pending_flip(crtc));
2836
2837         mutex_lock(&dev->struct_mutex);
2838         intel_finish_fb(crtc->fb);
2839         mutex_unlock(&dev->struct_mutex);
2840 }
2841
2842 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2843 {
2844         struct drm_device *dev = crtc->dev;
2845         struct intel_encoder *intel_encoder;
2846
2847         /*
2848          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2849          * must be driven by its own crtc; no sharing is possible.
2850          */
2851         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2852
2853                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2854                  * CPU handles all others */
2855                 if (IS_HASWELL(dev)) {
2856                         /* It is still unclear how this will work on PPT, so throw up a warning */
2857                         WARN_ON(!HAS_PCH_LPT(dev));
2858
2859                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2860                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2861                                 return true;
2862                         } else {
2863                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2864                                               intel_encoder->type);
2865                                 return false;
2866                         }
2867                 }
2868
2869                 switch (intel_encoder->type) {
2870                 case INTEL_OUTPUT_EDP:
2871                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2872                                 return false;
2873                         continue;
2874                 }
2875         }
2876
2877         return true;
2878 }
2879
2880 /* Program iCLKIP clock to the desired frequency */
2881 static void lpt_program_iclkip(struct drm_crtc *crtc)
2882 {
2883         struct drm_device *dev = crtc->dev;
2884         struct drm_i915_private *dev_priv = dev->dev_private;
2885         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2886         u32 temp;
2887
2888         /* It is necessary to ungate the pixclk gate prior to programming
2889          * the divisors, and gate it back when it is done.
2890          */
2891         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2892
2893         /* Disable SSCCTL */
2894         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2895                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2896                                         SBI_SSCCTL_DISABLE);
2897
2898         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2899         if (crtc->mode.clock == 20000) {
2900                 auxdiv = 1;
2901                 divsel = 0x41;
2902                 phaseinc = 0x20;
2903         } else {
2904                 /* The iCLK virtual clock root frequency is in MHz,
2905                  * but the crtc->mode.clock in in KHz. To get the divisors,
2906                  * it is necessary to divide one by another, so we
2907                  * convert the virtual clock precision to KHz here for higher
2908                  * precision.
2909                  */
2910                 u32 iclk_virtual_root_freq = 172800 * 1000;
2911                 u32 iclk_pi_range = 64;
2912                 u32 desired_divisor, msb_divisor_value, pi_value;
2913
2914                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2915                 msb_divisor_value = desired_divisor / iclk_pi_range;
2916                 pi_value = desired_divisor % iclk_pi_range;
2917
2918                 auxdiv = 0;
2919                 divsel = msb_divisor_value - 2;
2920                 phaseinc = pi_value;
2921         }
2922
2923         /* This should not happen with any sane values */
2924         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2925                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2926         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2927                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2928
2929         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2930                         crtc->mode.clock,
2931                         auxdiv,
2932                         divsel,
2933                         phasedir,
2934                         phaseinc);
2935
2936         /* Program SSCDIVINTPHASE6 */
2937         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2938         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2939         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2940         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2941         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2942         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2943         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2944
2945         intel_sbi_write(dev_priv,
2946                         SBI_SSCDIVINTPHASE6,
2947                         temp);
2948
2949         /* Program SSCAUXDIV */
2950         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2951         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2952         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2953         intel_sbi_write(dev_priv,
2954                         SBI_SSCAUXDIV6,
2955                         temp);
2956
2957
2958         /* Enable modulator and associated divider */
2959         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2960         temp &= ~SBI_SSCCTL_DISABLE;
2961         intel_sbi_write(dev_priv,
2962                         SBI_SSCCTL6,
2963                         temp);
2964
2965         /* Wait for initialization time */
2966         udelay(24);
2967
2968         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2969 }
2970
2971 /*
2972  * Enable PCH resources required for PCH ports:
2973  *   - PCH PLLs
2974  *   - FDI training & RX/TX
2975  *   - update transcoder timings
2976  *   - DP transcoding bits
2977  *   - transcoder
2978  */
2979 static void ironlake_pch_enable(struct drm_crtc *crtc)
2980 {
2981         struct drm_device *dev = crtc->dev;
2982         struct drm_i915_private *dev_priv = dev->dev_private;
2983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984         int pipe = intel_crtc->pipe;
2985         u32 reg, temp;
2986
2987         assert_transcoder_disabled(dev_priv, pipe);
2988
2989         /* For PCH output, training FDI link */
2990         dev_priv->display.fdi_link_train(crtc);
2991
2992         intel_enable_pch_pll(intel_crtc);
2993
2994         if (HAS_PCH_LPT(dev)) {
2995                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2996                 lpt_program_iclkip(crtc);
2997         } else if (HAS_PCH_CPT(dev)) {
2998                 u32 sel;
2999
3000                 temp = I915_READ(PCH_DPLL_SEL);
3001                 switch (pipe) {
3002                 default:
3003                 case 0:
3004                         temp |= TRANSA_DPLL_ENABLE;
3005                         sel = TRANSA_DPLLB_SEL;
3006                         break;
3007                 case 1:
3008                         temp |= TRANSB_DPLL_ENABLE;
3009                         sel = TRANSB_DPLLB_SEL;
3010                         break;
3011                 case 2:
3012                         temp |= TRANSC_DPLL_ENABLE;
3013                         sel = TRANSC_DPLLB_SEL;
3014                         break;
3015                 }
3016                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3017                         temp |= sel;
3018                 else
3019                         temp &= ~sel;
3020                 I915_WRITE(PCH_DPLL_SEL, temp);
3021         }
3022
3023         /* set transcoder timing, panel must allow it */
3024         assert_panel_unlocked(dev_priv, pipe);
3025         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3026         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3027         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3028
3029         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3030         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3031         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3032         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3033
3034         if (!IS_HASWELL(dev))
3035                 intel_fdi_normal_train(crtc);
3036
3037         /* For PCH DP, enable TRANS_DP_CTL */
3038         if (HAS_PCH_CPT(dev) &&
3039             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3040              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3041                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3042                 reg = TRANS_DP_CTL(pipe);
3043                 temp = I915_READ(reg);
3044                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3045                           TRANS_DP_SYNC_MASK |
3046                           TRANS_DP_BPC_MASK);
3047                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3048                          TRANS_DP_ENH_FRAMING);
3049                 temp |= bpc << 9; /* same format but at 11:9 */
3050
3051                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3052                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3053                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3054                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3055
3056                 switch (intel_trans_dp_port_sel(crtc)) {
3057                 case PCH_DP_B:
3058                         temp |= TRANS_DP_PORT_SEL_B;
3059                         break;
3060                 case PCH_DP_C:
3061                         temp |= TRANS_DP_PORT_SEL_C;
3062                         break;
3063                 case PCH_DP_D:
3064                         temp |= TRANS_DP_PORT_SEL_D;
3065                         break;
3066                 default:
3067                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3068                         temp |= TRANS_DP_PORT_SEL_B;
3069                         break;
3070                 }
3071
3072                 I915_WRITE(reg, temp);
3073         }
3074
3075         intel_enable_transcoder(dev_priv, pipe);
3076 }
3077
3078 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3079 {
3080         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3081
3082         if (pll == NULL)
3083                 return;
3084
3085         if (pll->refcount == 0) {
3086                 WARN(1, "bad PCH PLL refcount\n");
3087                 return;
3088         }
3089
3090         --pll->refcount;
3091         intel_crtc->pch_pll = NULL;
3092 }
3093
3094 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3095 {
3096         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3097         struct intel_pch_pll *pll;
3098         int i;
3099
3100         pll = intel_crtc->pch_pll;
3101         if (pll) {
3102                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3103                               intel_crtc->base.base.id, pll->pll_reg);
3104                 goto prepare;
3105         }
3106
3107         if (HAS_PCH_IBX(dev_priv->dev)) {
3108                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3109                 i = intel_crtc->pipe;
3110                 pll = &dev_priv->pch_plls[i];
3111
3112                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3113                               intel_crtc->base.base.id, pll->pll_reg);
3114
3115                 goto found;
3116         }
3117
3118         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119                 pll = &dev_priv->pch_plls[i];
3120
3121                 /* Only want to check enabled timings first */
3122                 if (pll->refcount == 0)
3123                         continue;
3124
3125                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3126                     fp == I915_READ(pll->fp0_reg)) {
3127                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3128                                       intel_crtc->base.base.id,
3129                                       pll->pll_reg, pll->refcount, pll->active);
3130
3131                         goto found;
3132                 }
3133         }
3134
3135         /* Ok no matching timings, maybe there's a free one? */
3136         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3137                 pll = &dev_priv->pch_plls[i];
3138                 if (pll->refcount == 0) {
3139                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3140                                       intel_crtc->base.base.id, pll->pll_reg);
3141                         goto found;
3142                 }
3143         }
3144
3145         return NULL;
3146
3147 found:
3148         intel_crtc->pch_pll = pll;
3149         pll->refcount++;
3150         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3151 prepare: /* separate function? */
3152         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3153
3154         /* Wait for the clocks to stabilize before rewriting the regs */
3155         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3156         POSTING_READ(pll->pll_reg);
3157         udelay(150);
3158
3159         I915_WRITE(pll->fp0_reg, fp);
3160         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3161         pll->on = false;
3162         return pll;
3163 }
3164
3165 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3166 {
3167         struct drm_i915_private *dev_priv = dev->dev_private;
3168         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3169         u32 temp;
3170
3171         temp = I915_READ(dslreg);
3172         udelay(500);
3173         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3174                 /* Without this, mode sets may fail silently on FDI */
3175                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3176                 udelay(250);
3177                 I915_WRITE(tc2reg, 0);
3178                 if (wait_for(I915_READ(dslreg) != temp, 5))
3179                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3180         }
3181 }
3182
3183 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3184 {
3185         struct drm_device *dev = crtc->dev;
3186         struct drm_i915_private *dev_priv = dev->dev_private;
3187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188         struct intel_encoder *encoder;
3189         int pipe = intel_crtc->pipe;
3190         int plane = intel_crtc->plane;
3191         u32 temp;
3192         bool is_pch_port;
3193
3194         WARN_ON(!crtc->enabled);
3195
3196         if (intel_crtc->active)
3197                 return;
3198
3199         intel_crtc->active = true;
3200         intel_update_watermarks(dev);
3201
3202         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3203                 temp = I915_READ(PCH_LVDS);
3204                 if ((temp & LVDS_PORT_EN) == 0)
3205                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3206         }
3207
3208         is_pch_port = intel_crtc_driving_pch(crtc);
3209
3210         if (is_pch_port) {
3211                 ironlake_fdi_pll_enable(intel_crtc);
3212         } else {
3213                 assert_fdi_tx_disabled(dev_priv, pipe);
3214                 assert_fdi_rx_disabled(dev_priv, pipe);
3215         }
3216
3217         for_each_encoder_on_crtc(dev, crtc, encoder)
3218                 if (encoder->pre_enable)
3219                         encoder->pre_enable(encoder);
3220
3221         /* Enable panel fitting for LVDS */
3222         if (dev_priv->pch_pf_size &&
3223             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3224                 /* Force use of hard-coded filter coefficients
3225                  * as some pre-programmed values are broken,
3226                  * e.g. x201.
3227                  */
3228                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3229                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3230                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3231         }
3232
3233         /*
3234          * On ILK+ LUT must be loaded before the pipe is running but with
3235          * clocks enabled
3236          */
3237         intel_crtc_load_lut(crtc);
3238
3239         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3240         intel_enable_plane(dev_priv, plane, pipe);
3241
3242         if (is_pch_port)
3243                 ironlake_pch_enable(crtc);
3244
3245         mutex_lock(&dev->struct_mutex);
3246         intel_update_fbc(dev);
3247         mutex_unlock(&dev->struct_mutex);
3248
3249         intel_crtc_update_cursor(crtc, true);
3250
3251         for_each_encoder_on_crtc(dev, crtc, encoder)
3252                 encoder->enable(encoder);
3253
3254         if (HAS_PCH_CPT(dev))
3255                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3256
3257         /*
3258          * There seems to be a race in PCH platform hw (at least on some
3259          * outputs) where an enabled pipe still completes any pageflip right
3260          * away (as if the pipe is off) instead of waiting for vblank. As soon
3261          * as the first vblank happend, everything works as expected. Hence just
3262          * wait for one vblank before returning to avoid strange things
3263          * happening.
3264          */
3265         intel_wait_for_vblank(dev, intel_crtc->pipe);
3266 }
3267
3268 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3269 {
3270         struct drm_device *dev = crtc->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273         struct intel_encoder *encoder;
3274         int pipe = intel_crtc->pipe;
3275         int plane = intel_crtc->plane;
3276         u32 reg, temp;
3277
3278
3279         if (!intel_crtc->active)
3280                 return;
3281
3282         for_each_encoder_on_crtc(dev, crtc, encoder)
3283                 encoder->disable(encoder);
3284
3285         intel_crtc_wait_for_pending_flips(crtc);
3286         drm_vblank_off(dev, pipe);
3287         intel_crtc_update_cursor(crtc, false);
3288
3289         intel_disable_plane(dev_priv, plane, pipe);
3290
3291         if (dev_priv->cfb_plane == plane)
3292                 intel_disable_fbc(dev);
3293
3294         intel_disable_pipe(dev_priv, pipe);
3295
3296         /* Disable PF */
3297         I915_WRITE(PF_CTL(pipe), 0);
3298         I915_WRITE(PF_WIN_SZ(pipe), 0);
3299
3300         for_each_encoder_on_crtc(dev, crtc, encoder)
3301                 if (encoder->post_disable)
3302                         encoder->post_disable(encoder);
3303
3304         ironlake_fdi_disable(crtc);
3305
3306         intel_disable_transcoder(dev_priv, pipe);
3307
3308         if (HAS_PCH_CPT(dev)) {
3309                 /* disable TRANS_DP_CTL */
3310                 reg = TRANS_DP_CTL(pipe);
3311                 temp = I915_READ(reg);
3312                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3313                 temp |= TRANS_DP_PORT_SEL_NONE;
3314                 I915_WRITE(reg, temp);
3315
3316                 /* disable DPLL_SEL */
3317                 temp = I915_READ(PCH_DPLL_SEL);
3318                 switch (pipe) {
3319                 case 0:
3320                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3321                         break;
3322                 case 1:
3323                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3324                         break;
3325                 case 2:
3326                         /* C shares PLL A or B */
3327                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3328                         break;
3329                 default:
3330                         BUG(); /* wtf */
3331                 }
3332                 I915_WRITE(PCH_DPLL_SEL, temp);
3333         }
3334
3335         /* disable PCH DPLL */
3336         intel_disable_pch_pll(intel_crtc);
3337
3338         ironlake_fdi_pll_disable(intel_crtc);
3339
3340         intel_crtc->active = false;
3341         intel_update_watermarks(dev);
3342
3343         mutex_lock(&dev->struct_mutex);
3344         intel_update_fbc(dev);
3345         mutex_unlock(&dev->struct_mutex);
3346 }
3347
3348 static void ironlake_crtc_off(struct drm_crtc *crtc)
3349 {
3350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351         intel_put_pch_pll(intel_crtc);
3352 }
3353
3354 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3355 {
3356         if (!enable && intel_crtc->overlay) {
3357                 struct drm_device *dev = intel_crtc->base.dev;
3358                 struct drm_i915_private *dev_priv = dev->dev_private;
3359
3360                 mutex_lock(&dev->struct_mutex);
3361                 dev_priv->mm.interruptible = false;
3362                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3363                 dev_priv->mm.interruptible = true;
3364                 mutex_unlock(&dev->struct_mutex);
3365         }
3366
3367         /* Let userspace switch the overlay on again. In most cases userspace
3368          * has to recompute where to put it anyway.
3369          */
3370 }
3371
3372 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3373 {
3374         struct drm_device *dev = crtc->dev;
3375         struct drm_i915_private *dev_priv = dev->dev_private;
3376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377         struct intel_encoder *encoder;
3378         int pipe = intel_crtc->pipe;
3379         int plane = intel_crtc->plane;
3380
3381         WARN_ON(!crtc->enabled);
3382
3383         if (intel_crtc->active)
3384                 return;
3385
3386         intel_crtc->active = true;
3387         intel_update_watermarks(dev);
3388
3389         intel_enable_pll(dev_priv, pipe);
3390         intel_enable_pipe(dev_priv, pipe, false);
3391         intel_enable_plane(dev_priv, plane, pipe);
3392
3393         intel_crtc_load_lut(crtc);
3394         intel_update_fbc(dev);
3395
3396         /* Give the overlay scaler a chance to enable if it's on this pipe */
3397         intel_crtc_dpms_overlay(intel_crtc, true);
3398         intel_crtc_update_cursor(crtc, true);
3399
3400         for_each_encoder_on_crtc(dev, crtc, encoder)
3401                 encoder->enable(encoder);
3402 }
3403
3404 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3405 {
3406         struct drm_device *dev = crtc->dev;
3407         struct drm_i915_private *dev_priv = dev->dev_private;
3408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3409         struct intel_encoder *encoder;
3410         int pipe = intel_crtc->pipe;
3411         int plane = intel_crtc->plane;
3412
3413
3414         if (!intel_crtc->active)
3415                 return;
3416
3417         for_each_encoder_on_crtc(dev, crtc, encoder)
3418                 encoder->disable(encoder);
3419
3420         /* Give the overlay scaler a chance to disable if it's on this pipe */
3421         intel_crtc_wait_for_pending_flips(crtc);
3422         drm_vblank_off(dev, pipe);
3423         intel_crtc_dpms_overlay(intel_crtc, false);
3424         intel_crtc_update_cursor(crtc, false);
3425
3426         if (dev_priv->cfb_plane == plane)
3427                 intel_disable_fbc(dev);
3428
3429         intel_disable_plane(dev_priv, plane, pipe);
3430         intel_disable_pipe(dev_priv, pipe);
3431         intel_disable_pll(dev_priv, pipe);
3432
3433         intel_crtc->active = false;
3434         intel_update_fbc(dev);
3435         intel_update_watermarks(dev);
3436 }
3437
3438 static void i9xx_crtc_off(struct drm_crtc *crtc)
3439 {
3440 }
3441
3442 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3443                                     bool enabled)
3444 {
3445         struct drm_device *dev = crtc->dev;
3446         struct drm_i915_master_private *master_priv;
3447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448         int pipe = intel_crtc->pipe;
3449
3450         if (!dev->primary->master)
3451                 return;
3452
3453         master_priv = dev->primary->master->driver_priv;
3454         if (!master_priv->sarea_priv)
3455                 return;
3456
3457         switch (pipe) {
3458         case 0:
3459                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3460                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3461                 break;
3462         case 1:
3463                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3464                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3465                 break;
3466         default:
3467                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3468                 break;
3469         }
3470 }
3471
3472 /**
3473  * Sets the power management mode of the pipe and plane.
3474  */
3475 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3476 {
3477         struct drm_device *dev = crtc->dev;
3478         struct drm_i915_private *dev_priv = dev->dev_private;
3479         struct intel_encoder *intel_encoder;
3480         bool enable = false;
3481
3482         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3483                 enable |= intel_encoder->connectors_active;
3484
3485         if (enable)
3486                 dev_priv->display.crtc_enable(crtc);
3487         else
3488                 dev_priv->display.crtc_disable(crtc);
3489
3490         intel_crtc_update_sarea(crtc, enable);
3491 }
3492
3493 static void intel_crtc_noop(struct drm_crtc *crtc)
3494 {
3495 }
3496
3497 static void intel_crtc_disable(struct drm_crtc *crtc)
3498 {
3499         struct drm_device *dev = crtc->dev;
3500         struct drm_connector *connector;
3501         struct drm_i915_private *dev_priv = dev->dev_private;
3502
3503         /* crtc should still be enabled when we disable it. */
3504         WARN_ON(!crtc->enabled);
3505
3506         dev_priv->display.crtc_disable(crtc);
3507         intel_crtc_update_sarea(crtc, false);
3508         dev_priv->display.off(crtc);
3509
3510         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3511         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3512
3513         if (crtc->fb) {
3514                 mutex_lock(&dev->struct_mutex);
3515                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3516                 mutex_unlock(&dev->struct_mutex);
3517                 crtc->fb = NULL;
3518         }
3519
3520         /* Update computed state. */
3521         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3522                 if (!connector->encoder || !connector->encoder->crtc)
3523                         continue;
3524
3525                 if (connector->encoder->crtc != crtc)
3526                         continue;
3527
3528                 connector->dpms = DRM_MODE_DPMS_OFF;
3529                 to_intel_encoder(connector->encoder)->connectors_active = false;
3530         }
3531 }
3532
3533 void intel_modeset_disable(struct drm_device *dev)
3534 {
3535         struct drm_crtc *crtc;
3536
3537         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3538                 if (crtc->enabled)
3539                         intel_crtc_disable(crtc);
3540         }
3541 }
3542
3543 void intel_encoder_noop(struct drm_encoder *encoder)
3544 {
3545 }
3546
3547 void intel_encoder_destroy(struct drm_encoder *encoder)
3548 {
3549         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3550
3551         drm_encoder_cleanup(encoder);
3552         kfree(intel_encoder);
3553 }
3554
3555 /* Simple dpms helper for encodres with just one connector, no cloning and only
3556  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3557  * state of the entire output pipe. */
3558 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3559 {
3560         if (mode == DRM_MODE_DPMS_ON) {
3561                 encoder->connectors_active = true;
3562
3563                 intel_crtc_update_dpms(encoder->base.crtc);
3564         } else {
3565                 encoder->connectors_active = false;
3566
3567                 intel_crtc_update_dpms(encoder->base.crtc);
3568         }
3569 }
3570
3571 /* Cross check the actual hw state with our own modeset state tracking (and it's
3572  * internal consistency). */
3573 static void intel_connector_check_state(struct intel_connector *connector)
3574 {
3575         if (connector->get_hw_state(connector)) {
3576                 struct intel_encoder *encoder = connector->encoder;
3577                 struct drm_crtc *crtc;
3578                 bool encoder_enabled;
3579                 enum pipe pipe;
3580
3581                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3582                               connector->base.base.id,
3583                               drm_get_connector_name(&connector->base));
3584
3585                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3586                      "wrong connector dpms state\n");
3587                 WARN(connector->base.encoder != &encoder->base,
3588                      "active connector not linked to encoder\n");
3589                 WARN(!encoder->connectors_active,
3590                      "encoder->connectors_active not set\n");
3591
3592                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3593                 WARN(!encoder_enabled, "encoder not enabled\n");
3594                 if (WARN_ON(!encoder->base.crtc))
3595                         return;
3596
3597                 crtc = encoder->base.crtc;
3598
3599                 WARN(!crtc->enabled, "crtc not enabled\n");
3600                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3601                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3602                      "encoder active on the wrong pipe\n");
3603         }
3604 }
3605
3606 /* Even simpler default implementation, if there's really no special case to
3607  * consider. */
3608 void intel_connector_dpms(struct drm_connector *connector, int mode)
3609 {
3610         struct intel_encoder *encoder = intel_attached_encoder(connector);
3611
3612         /* All the simple cases only support two dpms states. */
3613         if (mode != DRM_MODE_DPMS_ON)
3614                 mode = DRM_MODE_DPMS_OFF;
3615
3616         if (mode == connector->dpms)
3617                 return;
3618
3619         connector->dpms = mode;
3620
3621         /* Only need to change hw state when actually enabled */
3622         if (encoder->base.crtc)
3623                 intel_encoder_dpms(encoder, mode);
3624         else
3625                 WARN_ON(encoder->connectors_active != false);
3626
3627         intel_modeset_check_state(connector->dev);
3628 }
3629
3630 /* Simple connector->get_hw_state implementation for encoders that support only
3631  * one connector and no cloning and hence the encoder state determines the state
3632  * of the connector. */
3633 bool intel_connector_get_hw_state(struct intel_connector *connector)
3634 {
3635         enum pipe pipe = 0;
3636         struct intel_encoder *encoder = connector->encoder;
3637
3638         return encoder->get_hw_state(encoder, &pipe);
3639 }
3640
3641 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3642                                   const struct drm_display_mode *mode,
3643                                   struct drm_display_mode *adjusted_mode)
3644 {
3645         struct drm_device *dev = crtc->dev;
3646
3647         if (HAS_PCH_SPLIT(dev)) {
3648                 /* FDI link clock is fixed at 2.7G */
3649                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3650                         return false;
3651         }
3652
3653         /* All interlaced capable intel hw wants timings in frames. Note though
3654          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3655          * timings, so we need to be careful not to clobber these.*/
3656         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3657                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3658
3659         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3660          * with a hsync front porch of 0.
3661          */
3662         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3663                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3664                 return false;
3665
3666         return true;
3667 }
3668
3669 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3670 {
3671         return 400000; /* FIXME */
3672 }
3673
3674 static int i945_get_display_clock_speed(struct drm_device *dev)
3675 {
3676         return 400000;
3677 }
3678
3679 static int i915_get_display_clock_speed(struct drm_device *dev)
3680 {
3681         return 333000;
3682 }
3683
3684 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3685 {
3686         return 200000;
3687 }
3688
3689 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3690 {
3691         u16 gcfgc = 0;
3692
3693         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3694
3695         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3696                 return 133000;
3697         else {
3698                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3699                 case GC_DISPLAY_CLOCK_333_MHZ:
3700                         return 333000;
3701                 default:
3702                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3703                         return 190000;
3704                 }
3705         }
3706 }
3707
3708 static int i865_get_display_clock_speed(struct drm_device *dev)
3709 {
3710         return 266000;
3711 }
3712
3713 static int i855_get_display_clock_speed(struct drm_device *dev)
3714 {
3715         u16 hpllcc = 0;
3716         /* Assume that the hardware is in the high speed state.  This
3717          * should be the default.
3718          */
3719         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3720         case GC_CLOCK_133_200:
3721         case GC_CLOCK_100_200:
3722                 return 200000;
3723         case GC_CLOCK_166_250:
3724                 return 250000;
3725         case GC_CLOCK_100_133:
3726                 return 133000;
3727         }
3728
3729         /* Shouldn't happen */
3730         return 0;
3731 }
3732
3733 static int i830_get_display_clock_speed(struct drm_device *dev)
3734 {
3735         return 133000;
3736 }
3737
3738 struct fdi_m_n {
3739         u32        tu;
3740         u32        gmch_m;
3741         u32        gmch_n;
3742         u32        link_m;
3743         u32        link_n;
3744 };
3745
3746 static void
3747 fdi_reduce_ratio(u32 *num, u32 *den)
3748 {
3749         while (*num > 0xffffff || *den > 0xffffff) {
3750                 *num >>= 1;
3751                 *den >>= 1;
3752         }
3753 }
3754
3755 static void
3756 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3757                      int link_clock, struct fdi_m_n *m_n)
3758 {
3759         m_n->tu = 64; /* default size */
3760
3761         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3762         m_n->gmch_m = bits_per_pixel * pixel_clock;
3763         m_n->gmch_n = link_clock * nlanes * 8;
3764         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3765
3766         m_n->link_m = pixel_clock;
3767         m_n->link_n = link_clock;
3768         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3769 }
3770
3771 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3772 {
3773         if (i915_panel_use_ssc >= 0)
3774                 return i915_panel_use_ssc != 0;
3775         return dev_priv->lvds_use_ssc
3776                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3777 }
3778
3779 /**
3780  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3781  * @crtc: CRTC structure
3782  * @mode: requested mode
3783  *
3784  * A pipe may be connected to one or more outputs.  Based on the depth of the
3785  * attached framebuffer, choose a good color depth to use on the pipe.
3786  *
3787  * If possible, match the pipe depth to the fb depth.  In some cases, this
3788  * isn't ideal, because the connected output supports a lesser or restricted
3789  * set of depths.  Resolve that here:
3790  *    LVDS typically supports only 6bpc, so clamp down in that case
3791  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3792  *    Displays may support a restricted set as well, check EDID and clamp as
3793  *      appropriate.
3794  *    DP may want to dither down to 6bpc to fit larger modes
3795  *
3796  * RETURNS:
3797  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3798  * true if they don't match).
3799  */
3800 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3801                                          struct drm_framebuffer *fb,
3802                                          unsigned int *pipe_bpp,
3803                                          struct drm_display_mode *mode)
3804 {
3805         struct drm_device *dev = crtc->dev;
3806         struct drm_i915_private *dev_priv = dev->dev_private;
3807         struct drm_connector *connector;
3808         struct intel_encoder *intel_encoder;
3809         unsigned int display_bpc = UINT_MAX, bpc;
3810
3811         /* Walk the encoders & connectors on this crtc, get min bpc */
3812         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3813
3814                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3815                         unsigned int lvds_bpc;
3816
3817                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3818                             LVDS_A3_POWER_UP)
3819                                 lvds_bpc = 8;
3820                         else
3821                                 lvds_bpc = 6;
3822
3823                         if (lvds_bpc < display_bpc) {
3824                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3825                                 display_bpc = lvds_bpc;
3826                         }
3827                         continue;
3828                 }
3829
3830                 /* Not one of the known troublemakers, check the EDID */
3831                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3832                                     head) {
3833                         if (connector->encoder != &intel_encoder->base)
3834                                 continue;
3835
3836                         /* Don't use an invalid EDID bpc value */
3837                         if (connector->display_info.bpc &&
3838                             connector->display_info.bpc < display_bpc) {
3839                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3840                                 display_bpc = connector->display_info.bpc;
3841                         }
3842                 }
3843
3844                 /*
3845                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3846                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3847                  */
3848                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3849                         if (display_bpc > 8 && display_bpc < 12) {
3850                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3851                                 display_bpc = 12;
3852                         } else {
3853                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3854                                 display_bpc = 8;
3855                         }
3856                 }
3857         }
3858
3859         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3860                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3861                 display_bpc = 6;
3862         }
3863
3864         /*
3865          * We could just drive the pipe at the highest bpc all the time and
3866          * enable dithering as needed, but that costs bandwidth.  So choose
3867          * the minimum value that expresses the full color range of the fb but
3868          * also stays within the max display bpc discovered above.
3869          */
3870
3871         switch (fb->depth) {
3872         case 8:
3873                 bpc = 8; /* since we go through a colormap */
3874                 break;
3875         case 15:
3876         case 16:
3877                 bpc = 6; /* min is 18bpp */
3878                 break;
3879         case 24:
3880                 bpc = 8;
3881                 break;
3882         case 30:
3883                 bpc = 10;
3884                 break;
3885         case 48:
3886                 bpc = 12;
3887                 break;
3888         default:
3889                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3890                 bpc = min((unsigned int)8, display_bpc);
3891                 break;
3892         }
3893
3894         display_bpc = min(display_bpc, bpc);
3895
3896         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3897                       bpc, display_bpc);
3898
3899         *pipe_bpp = display_bpc * 3;
3900
3901         return display_bpc != bpc;
3902 }
3903
3904 static int vlv_get_refclk(struct drm_crtc *crtc)
3905 {
3906         struct drm_device *dev = crtc->dev;
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908         int refclk = 27000; /* for DP & HDMI */
3909
3910         return 100000; /* only one validated so far */
3911
3912         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3913                 refclk = 96000;
3914         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3915                 if (intel_panel_use_ssc(dev_priv))
3916                         refclk = 100000;
3917                 else
3918                         refclk = 96000;
3919         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3920                 refclk = 100000;
3921         }
3922
3923         return refclk;
3924 }
3925
3926 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3927 {
3928         struct drm_device *dev = crtc->dev;
3929         struct drm_i915_private *dev_priv = dev->dev_private;
3930         int refclk;
3931
3932         if (IS_VALLEYVIEW(dev)) {
3933                 refclk = vlv_get_refclk(crtc);
3934         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3935             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3936                 refclk = dev_priv->lvds_ssc_freq * 1000;
3937                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3938                               refclk / 1000);
3939         } else if (!IS_GEN2(dev)) {
3940                 refclk = 96000;
3941         } else {
3942                 refclk = 48000;
3943         }
3944
3945         return refclk;
3946 }
3947
3948 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3949                                       intel_clock_t *clock)
3950 {
3951         /* SDVO TV has fixed PLL values depend on its clock range,
3952            this mirrors vbios setting. */
3953         if (adjusted_mode->clock >= 100000
3954             && adjusted_mode->clock < 140500) {
3955                 clock->p1 = 2;
3956                 clock->p2 = 10;
3957                 clock->n = 3;
3958                 clock->m1 = 16;
3959                 clock->m2 = 8;
3960         } else if (adjusted_mode->clock >= 140500
3961                    && adjusted_mode->clock <= 200000) {
3962                 clock->p1 = 1;
3963                 clock->p2 = 10;
3964                 clock->n = 6;
3965                 clock->m1 = 12;
3966                 clock->m2 = 8;
3967         }
3968 }
3969
3970 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3971                                      intel_clock_t *clock,
3972                                      intel_clock_t *reduced_clock)
3973 {
3974         struct drm_device *dev = crtc->dev;
3975         struct drm_i915_private *dev_priv = dev->dev_private;
3976         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3977         int pipe = intel_crtc->pipe;
3978         u32 fp, fp2 = 0;
3979
3980         if (IS_PINEVIEW(dev)) {
3981                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3982                 if (reduced_clock)
3983                         fp2 = (1 << reduced_clock->n) << 16 |
3984                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3985         } else {
3986                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3987                 if (reduced_clock)
3988                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3989                                 reduced_clock->m2;
3990         }
3991
3992         I915_WRITE(FP0(pipe), fp);
3993
3994         intel_crtc->lowfreq_avail = false;
3995         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3996             reduced_clock && i915_powersave) {
3997                 I915_WRITE(FP1(pipe), fp2);
3998                 intel_crtc->lowfreq_avail = true;
3999         } else {
4000                 I915_WRITE(FP1(pipe), fp);
4001         }
4002 }
4003
4004 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4005                               struct drm_display_mode *adjusted_mode)
4006 {
4007         struct drm_device *dev = crtc->dev;
4008         struct drm_i915_private *dev_priv = dev->dev_private;
4009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4010         int pipe = intel_crtc->pipe;
4011         u32 temp;
4012
4013         temp = I915_READ(LVDS);
4014         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4015         if (pipe == 1) {
4016                 temp |= LVDS_PIPEB_SELECT;
4017         } else {
4018                 temp &= ~LVDS_PIPEB_SELECT;
4019         }
4020         /* set the corresponsding LVDS_BORDER bit */
4021         temp |= dev_priv->lvds_border_bits;
4022         /* Set the B0-B3 data pairs corresponding to whether we're going to
4023          * set the DPLLs for dual-channel mode or not.
4024          */
4025         if (clock->p2 == 7)
4026                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4027         else
4028                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4029
4030         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4031          * appropriately here, but we need to look more thoroughly into how
4032          * panels behave in the two modes.
4033          */
4034         /* set the dithering flag on LVDS as needed */
4035         if (INTEL_INFO(dev)->gen >= 4) {
4036                 if (dev_priv->lvds_dither)
4037                         temp |= LVDS_ENABLE_DITHER;
4038                 else
4039                         temp &= ~LVDS_ENABLE_DITHER;
4040         }
4041         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4042         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4043                 temp |= LVDS_HSYNC_POLARITY;
4044         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4045                 temp |= LVDS_VSYNC_POLARITY;
4046         I915_WRITE(LVDS, temp);
4047 }
4048
4049 static void vlv_update_pll(struct drm_crtc *crtc,
4050                            struct drm_display_mode *mode,
4051                            struct drm_display_mode *adjusted_mode,
4052                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4053                            int refclk, int num_connectors)
4054 {
4055         struct drm_device *dev = crtc->dev;
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4058         int pipe = intel_crtc->pipe;
4059         u32 dpll, mdiv, pdiv;
4060         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4061         bool is_hdmi;
4062
4063         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4064
4065         bestn = clock->n;
4066         bestm1 = clock->m1;
4067         bestm2 = clock->m2;
4068         bestp1 = clock->p1;
4069         bestp2 = clock->p2;
4070
4071         /* Enable DPIO clock input */
4072         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4073                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4074         I915_WRITE(DPLL(pipe), dpll);
4075         POSTING_READ(DPLL(pipe));
4076
4077         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4078         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4079         mdiv |= ((bestn << DPIO_N_SHIFT));
4080         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4081         mdiv |= (1 << DPIO_K_SHIFT);
4082         mdiv |= DPIO_ENABLE_CALIBRATION;
4083         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4084
4085         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4086
4087         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4088                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4089                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4090         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4091
4092         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4093
4094         dpll |= DPLL_VCO_ENABLE;
4095         I915_WRITE(DPLL(pipe), dpll);
4096         POSTING_READ(DPLL(pipe));
4097         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4098                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4099
4100         if (is_hdmi) {
4101                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4102
4103                 if (temp > 1)
4104                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4105                 else
4106                         temp = 0;
4107
4108                 I915_WRITE(DPLL_MD(pipe), temp);
4109                 POSTING_READ(DPLL_MD(pipe));
4110         }
4111
4112         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4113 }
4114
4115 static void i9xx_update_pll(struct drm_crtc *crtc,
4116                             struct drm_display_mode *mode,
4117                             struct drm_display_mode *adjusted_mode,
4118                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4119                             int num_connectors)
4120 {
4121         struct drm_device *dev = crtc->dev;
4122         struct drm_i915_private *dev_priv = dev->dev_private;
4123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4124         int pipe = intel_crtc->pipe;
4125         u32 dpll;
4126         bool is_sdvo;
4127
4128         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4129                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4130
4131         dpll = DPLL_VGA_MODE_DIS;
4132
4133         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4134                 dpll |= DPLLB_MODE_LVDS;
4135         else
4136                 dpll |= DPLLB_MODE_DAC_SERIAL;
4137         if (is_sdvo) {
4138                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4139                 if (pixel_multiplier > 1) {
4140                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4141                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4142                 }
4143                 dpll |= DPLL_DVO_HIGH_SPEED;
4144         }
4145         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4146                 dpll |= DPLL_DVO_HIGH_SPEED;
4147
4148         /* compute bitmask from p1 value */
4149         if (IS_PINEVIEW(dev))
4150                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4151         else {
4152                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4153                 if (IS_G4X(dev) && reduced_clock)
4154                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4155         }
4156         switch (clock->p2) {
4157         case 5:
4158                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4159                 break;
4160         case 7:
4161                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4162                 break;
4163         case 10:
4164                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4165                 break;
4166         case 14:
4167                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4168                 break;
4169         }
4170         if (INTEL_INFO(dev)->gen >= 4)
4171                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4172
4173         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4174                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4175         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4176                 /* XXX: just matching BIOS for now */
4177                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4178                 dpll |= 3;
4179         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4180                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4181                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4182         else
4183                 dpll |= PLL_REF_INPUT_DREFCLK;
4184
4185         dpll |= DPLL_VCO_ENABLE;
4186         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4187         POSTING_READ(DPLL(pipe));
4188         udelay(150);
4189
4190         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4191          * This is an exception to the general rule that mode_set doesn't turn
4192          * things on.
4193          */
4194         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4195                 intel_update_lvds(crtc, clock, adjusted_mode);
4196
4197         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4198                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4199
4200         I915_WRITE(DPLL(pipe), dpll);
4201
4202         /* Wait for the clocks to stabilize. */
4203         POSTING_READ(DPLL(pipe));
4204         udelay(150);
4205
4206         if (INTEL_INFO(dev)->gen >= 4) {
4207                 u32 temp = 0;
4208                 if (is_sdvo) {
4209                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4210                         if (temp > 1)
4211                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4212                         else
4213                                 temp = 0;
4214                 }
4215                 I915_WRITE(DPLL_MD(pipe), temp);
4216         } else {
4217                 /* The pixel multiplier can only be updated once the
4218                  * DPLL is enabled and the clocks are stable.
4219                  *
4220                  * So write it again.
4221                  */
4222                 I915_WRITE(DPLL(pipe), dpll);
4223         }
4224 }
4225
4226 static void i8xx_update_pll(struct drm_crtc *crtc,
4227                             struct drm_display_mode *adjusted_mode,
4228                             intel_clock_t *clock,
4229                             int num_connectors)
4230 {
4231         struct drm_device *dev = crtc->dev;
4232         struct drm_i915_private *dev_priv = dev->dev_private;
4233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4234         int pipe = intel_crtc->pipe;
4235         u32 dpll;
4236
4237         dpll = DPLL_VGA_MODE_DIS;
4238
4239         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4240                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4241         } else {
4242                 if (clock->p1 == 2)
4243                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4244                 else
4245                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4246                 if (clock->p2 == 4)
4247                         dpll |= PLL_P2_DIVIDE_BY_4;
4248         }
4249
4250         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4251                 /* XXX: just matching BIOS for now */
4252                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4253                 dpll |= 3;
4254         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4255                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4256                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4257         else
4258                 dpll |= PLL_REF_INPUT_DREFCLK;
4259
4260         dpll |= DPLL_VCO_ENABLE;
4261         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4262         POSTING_READ(DPLL(pipe));
4263         udelay(150);
4264
4265         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4266          * This is an exception to the general rule that mode_set doesn't turn
4267          * things on.
4268          */
4269         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4270                 intel_update_lvds(crtc, clock, adjusted_mode);
4271
4272         I915_WRITE(DPLL(pipe), dpll);
4273
4274         /* Wait for the clocks to stabilize. */
4275         POSTING_READ(DPLL(pipe));
4276         udelay(150);
4277
4278         /* The pixel multiplier can only be updated once the
4279          * DPLL is enabled and the clocks are stable.
4280          *
4281          * So write it again.
4282          */
4283         I915_WRITE(DPLL(pipe), dpll);
4284 }
4285
4286 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4287                               struct drm_display_mode *mode,
4288                               struct drm_display_mode *adjusted_mode,
4289                               int x, int y,
4290                               struct drm_framebuffer *fb)
4291 {
4292         struct drm_device *dev = crtc->dev;
4293         struct drm_i915_private *dev_priv = dev->dev_private;
4294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4295         int pipe = intel_crtc->pipe;
4296         int plane = intel_crtc->plane;
4297         int refclk, num_connectors = 0;
4298         intel_clock_t clock, reduced_clock;
4299         u32 dspcntr, pipeconf, vsyncshift;
4300         bool ok, has_reduced_clock = false, is_sdvo = false;
4301         bool is_lvds = false, is_tv = false, is_dp = false;
4302         struct intel_encoder *encoder;
4303         const intel_limit_t *limit;
4304         int ret;
4305
4306         for_each_encoder_on_crtc(dev, crtc, encoder) {
4307                 switch (encoder->type) {
4308                 case INTEL_OUTPUT_LVDS:
4309                         is_lvds = true;
4310                         break;
4311                 case INTEL_OUTPUT_SDVO:
4312                 case INTEL_OUTPUT_HDMI:
4313                         is_sdvo = true;
4314                         if (encoder->needs_tv_clock)
4315                                 is_tv = true;
4316                         break;
4317                 case INTEL_OUTPUT_TVOUT:
4318                         is_tv = true;
4319                         break;
4320                 case INTEL_OUTPUT_DISPLAYPORT:
4321                         is_dp = true;
4322                         break;
4323                 }
4324
4325                 num_connectors++;
4326         }
4327
4328         refclk = i9xx_get_refclk(crtc, num_connectors);
4329
4330         /*
4331          * Returns a set of divisors for the desired target clock with the given
4332          * refclk, or FALSE.  The returned values represent the clock equation:
4333          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4334          */
4335         limit = intel_limit(crtc, refclk);
4336         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4337                              &clock);
4338         if (!ok) {
4339                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4340                 return -EINVAL;
4341         }
4342
4343         /* Ensure that the cursor is valid for the new mode before changing... */
4344         intel_crtc_update_cursor(crtc, true);
4345
4346         if (is_lvds && dev_priv->lvds_downclock_avail) {
4347                 /*
4348                  * Ensure we match the reduced clock's P to the target clock.
4349                  * If the clocks don't match, we can't switch the display clock
4350                  * by using the FP0/FP1. In such case we will disable the LVDS
4351                  * downclock feature.
4352                 */
4353                 has_reduced_clock = limit->find_pll(limit, crtc,
4354                                                     dev_priv->lvds_downclock,
4355                                                     refclk,
4356                                                     &clock,
4357                                                     &reduced_clock);
4358         }
4359
4360         if (is_sdvo && is_tv)
4361                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4362
4363         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4364                                  &reduced_clock : NULL);
4365
4366         if (IS_GEN2(dev))
4367                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4368         else if (IS_VALLEYVIEW(dev))
4369                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4370                                refclk, num_connectors);
4371         else
4372                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4373                                 has_reduced_clock ? &reduced_clock : NULL,
4374                                 num_connectors);
4375
4376         /* setup pipeconf */
4377         pipeconf = I915_READ(PIPECONF(pipe));
4378
4379         /* Set up the display plane register */
4380         dspcntr = DISPPLANE_GAMMA_ENABLE;
4381
4382         if (pipe == 0)
4383                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4384         else
4385                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4386
4387         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4388                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4389                  * core speed.
4390                  *
4391                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4392                  * pipe == 0 check?
4393                  */
4394                 if (mode->clock >
4395                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4396                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4397                 else
4398                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4399         }
4400
4401         /* default to 8bpc */
4402         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4403         if (is_dp) {
4404                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4405                         pipeconf |= PIPECONF_BPP_6 |
4406                                     PIPECONF_DITHER_EN |
4407                                     PIPECONF_DITHER_TYPE_SP;
4408                 }
4409         }
4410
4411         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4412         drm_mode_debug_printmodeline(mode);
4413
4414         if (HAS_PIPE_CXSR(dev)) {
4415                 if (intel_crtc->lowfreq_avail) {
4416                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4417                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4418                 } else {
4419                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4420                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4421                 }
4422         }
4423
4424         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4425         if (!IS_GEN2(dev) &&
4426             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4427                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4428                 /* the chip adds 2 halflines automatically */
4429                 adjusted_mode->crtc_vtotal -= 1;
4430                 adjusted_mode->crtc_vblank_end -= 1;
4431                 vsyncshift = adjusted_mode->crtc_hsync_start
4432                              - adjusted_mode->crtc_htotal/2;
4433         } else {
4434                 pipeconf |= PIPECONF_PROGRESSIVE;
4435                 vsyncshift = 0;
4436         }
4437
4438         if (!IS_GEN3(dev))
4439                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4440
4441         I915_WRITE(HTOTAL(pipe),
4442                    (adjusted_mode->crtc_hdisplay - 1) |
4443                    ((adjusted_mode->crtc_htotal - 1) << 16));
4444         I915_WRITE(HBLANK(pipe),
4445                    (adjusted_mode->crtc_hblank_start - 1) |
4446                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4447         I915_WRITE(HSYNC(pipe),
4448                    (adjusted_mode->crtc_hsync_start - 1) |
4449                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4450
4451         I915_WRITE(VTOTAL(pipe),
4452                    (adjusted_mode->crtc_vdisplay - 1) |
4453                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4454         I915_WRITE(VBLANK(pipe),
4455                    (adjusted_mode->crtc_vblank_start - 1) |
4456                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4457         I915_WRITE(VSYNC(pipe),
4458                    (adjusted_mode->crtc_vsync_start - 1) |
4459                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4460
4461         /* pipesrc and dspsize control the size that is scaled from,
4462          * which should always be the user's requested size.
4463          */
4464         I915_WRITE(DSPSIZE(plane),
4465                    ((mode->vdisplay - 1) << 16) |
4466                    (mode->hdisplay - 1));
4467         I915_WRITE(DSPPOS(plane), 0);
4468         I915_WRITE(PIPESRC(pipe),
4469                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4470
4471         I915_WRITE(PIPECONF(pipe), pipeconf);
4472         POSTING_READ(PIPECONF(pipe));
4473         intel_enable_pipe(dev_priv, pipe, false);
4474
4475         intel_wait_for_vblank(dev, pipe);
4476
4477         I915_WRITE(DSPCNTR(plane), dspcntr);
4478         POSTING_READ(DSPCNTR(plane));
4479
4480         ret = intel_pipe_set_base(crtc, x, y, fb);
4481
4482         intel_update_watermarks(dev);
4483
4484         return ret;
4485 }
4486
4487 /*
4488  * Initialize reference clocks when the driver loads
4489  */
4490 void ironlake_init_pch_refclk(struct drm_device *dev)
4491 {
4492         struct drm_i915_private *dev_priv = dev->dev_private;
4493         struct drm_mode_config *mode_config = &dev->mode_config;
4494         struct intel_encoder *encoder;
4495         u32 temp;
4496         bool has_lvds = false;
4497         bool has_cpu_edp = false;
4498         bool has_pch_edp = false;
4499         bool has_panel = false;
4500         bool has_ck505 = false;
4501         bool can_ssc = false;
4502
4503         /* We need to take the global config into account */
4504         list_for_each_entry(encoder, &mode_config->encoder_list,
4505                             base.head) {
4506                 switch (encoder->type) {
4507                 case INTEL_OUTPUT_LVDS:
4508                         has_panel = true;
4509                         has_lvds = true;
4510                         break;
4511                 case INTEL_OUTPUT_EDP:
4512                         has_panel = true;
4513                         if (intel_encoder_is_pch_edp(&encoder->base))
4514                                 has_pch_edp = true;
4515                         else
4516                                 has_cpu_edp = true;
4517                         break;
4518                 }
4519         }
4520
4521         if (HAS_PCH_IBX(dev)) {
4522                 has_ck505 = dev_priv->display_clock_mode;
4523                 can_ssc = has_ck505;
4524         } else {
4525                 has_ck505 = false;
4526                 can_ssc = true;
4527         }
4528
4529         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4530                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4531                       has_ck505);
4532
4533         /* Ironlake: try to setup display ref clock before DPLL
4534          * enabling. This is only under driver's control after
4535          * PCH B stepping, previous chipset stepping should be
4536          * ignoring this setting.
4537          */
4538         temp = I915_READ(PCH_DREF_CONTROL);
4539         /* Always enable nonspread source */
4540         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4541
4542         if (has_ck505)
4543                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4544         else
4545                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4546
4547         if (has_panel) {
4548                 temp &= ~DREF_SSC_SOURCE_MASK;
4549                 temp |= DREF_SSC_SOURCE_ENABLE;
4550
4551                 /* SSC must be turned on before enabling the CPU output  */
4552                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4553                         DRM_DEBUG_KMS("Using SSC on panel\n");
4554                         temp |= DREF_SSC1_ENABLE;
4555                 } else
4556                         temp &= ~DREF_SSC1_ENABLE;
4557
4558                 /* Get SSC going before enabling the outputs */
4559                 I915_WRITE(PCH_DREF_CONTROL, temp);
4560                 POSTING_READ(PCH_DREF_CONTROL);
4561                 udelay(200);
4562
4563                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4564
4565                 /* Enable CPU source on CPU attached eDP */
4566                 if (has_cpu_edp) {
4567                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4568                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4569                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4570                         }
4571                         else
4572                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4573                 } else
4574                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4575
4576                 I915_WRITE(PCH_DREF_CONTROL, temp);
4577                 POSTING_READ(PCH_DREF_CONTROL);
4578                 udelay(200);
4579         } else {
4580                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4581
4582                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4583
4584                 /* Turn off CPU output */
4585                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4586
4587                 I915_WRITE(PCH_DREF_CONTROL, temp);
4588                 POSTING_READ(PCH_DREF_CONTROL);
4589                 udelay(200);
4590
4591                 /* Turn off the SSC source */
4592                 temp &= ~DREF_SSC_SOURCE_MASK;
4593                 temp |= DREF_SSC_SOURCE_DISABLE;
4594
4595                 /* Turn off SSC1 */
4596                 temp &= ~ DREF_SSC1_ENABLE;
4597
4598                 I915_WRITE(PCH_DREF_CONTROL, temp);
4599                 POSTING_READ(PCH_DREF_CONTROL);
4600                 udelay(200);
4601         }
4602 }
4603
4604 static int ironlake_get_refclk(struct drm_crtc *crtc)
4605 {
4606         struct drm_device *dev = crtc->dev;
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608         struct intel_encoder *encoder;
4609         struct intel_encoder *edp_encoder = NULL;
4610         int num_connectors = 0;
4611         bool is_lvds = false;
4612
4613         for_each_encoder_on_crtc(dev, crtc, encoder) {
4614                 switch (encoder->type) {
4615                 case INTEL_OUTPUT_LVDS:
4616                         is_lvds = true;
4617                         break;
4618                 case INTEL_OUTPUT_EDP:
4619                         edp_encoder = encoder;
4620                         break;
4621                 }
4622                 num_connectors++;
4623         }
4624
4625         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4626                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4627                               dev_priv->lvds_ssc_freq);
4628                 return dev_priv->lvds_ssc_freq * 1000;
4629         }
4630
4631         return 120000;
4632 }
4633
4634 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4635                                   struct drm_display_mode *adjusted_mode,
4636                                   bool dither)
4637 {
4638         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4640         int pipe = intel_crtc->pipe;
4641         uint32_t val;
4642
4643         val = I915_READ(PIPECONF(pipe));
4644
4645         val &= ~PIPE_BPC_MASK;
4646         switch (intel_crtc->bpp) {
4647         case 18:
4648                 val |= PIPE_6BPC;
4649                 break;
4650         case 24:
4651                 val |= PIPE_8BPC;
4652                 break;
4653         case 30:
4654                 val |= PIPE_10BPC;
4655                 break;
4656         case 36:
4657                 val |= PIPE_12BPC;
4658                 break;
4659         default:
4660                 val |= PIPE_8BPC;
4661                 break;
4662         }
4663
4664         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4665         if (dither)
4666                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4667
4668         val &= ~PIPECONF_INTERLACE_MASK;
4669         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4670                 val |= PIPECONF_INTERLACED_ILK;
4671         else
4672                 val |= PIPECONF_PROGRESSIVE;
4673
4674         I915_WRITE(PIPECONF(pipe), val);
4675         POSTING_READ(PIPECONF(pipe));
4676 }
4677
4678 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4679                                     struct drm_display_mode *adjusted_mode,
4680                                     intel_clock_t *clock,
4681                                     bool *has_reduced_clock,
4682                                     intel_clock_t *reduced_clock)
4683 {
4684         struct drm_device *dev = crtc->dev;
4685         struct drm_i915_private *dev_priv = dev->dev_private;
4686         struct intel_encoder *intel_encoder;
4687         int refclk;
4688         const intel_limit_t *limit;
4689         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4690
4691         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4692                 switch (intel_encoder->type) {
4693                 case INTEL_OUTPUT_LVDS:
4694                         is_lvds = true;
4695                         break;
4696                 case INTEL_OUTPUT_SDVO:
4697                 case INTEL_OUTPUT_HDMI:
4698                         is_sdvo = true;
4699                         if (intel_encoder->needs_tv_clock)
4700                                 is_tv = true;
4701                         break;
4702                 case INTEL_OUTPUT_TVOUT:
4703                         is_tv = true;
4704                         break;
4705                 }
4706         }
4707
4708         refclk = ironlake_get_refclk(crtc);
4709
4710         /*
4711          * Returns a set of divisors for the desired target clock with the given
4712          * refclk, or FALSE.  The returned values represent the clock equation:
4713          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4714          */
4715         limit = intel_limit(crtc, refclk);
4716         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4717                               clock);
4718         if (!ret)
4719                 return false;
4720
4721         if (is_lvds && dev_priv->lvds_downclock_avail) {
4722                 /*
4723                  * Ensure we match the reduced clock's P to the target clock.
4724                  * If the clocks don't match, we can't switch the display clock
4725                  * by using the FP0/FP1. In such case we will disable the LVDS
4726                  * downclock feature.
4727                 */
4728                 *has_reduced_clock = limit->find_pll(limit, crtc,
4729                                                      dev_priv->lvds_downclock,
4730                                                      refclk,
4731                                                      clock,
4732                                                      reduced_clock);
4733         }
4734
4735         if (is_sdvo && is_tv)
4736                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4737
4738         return true;
4739 }
4740
4741 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4742                                   struct drm_display_mode *mode,
4743                                   struct drm_display_mode *adjusted_mode,
4744                                   int x, int y,
4745                                   struct drm_framebuffer *fb)
4746 {
4747         struct drm_device *dev = crtc->dev;
4748         struct drm_i915_private *dev_priv = dev->dev_private;
4749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4750         int pipe = intel_crtc->pipe;
4751         int plane = intel_crtc->plane;
4752         int num_connectors = 0;
4753         intel_clock_t clock, reduced_clock;
4754         u32 dpll, fp = 0, fp2 = 0;
4755         bool ok, has_reduced_clock = false, is_sdvo = false;
4756         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4757         struct intel_encoder *encoder, *edp_encoder = NULL;
4758         int ret;
4759         struct fdi_m_n m_n = {0};
4760         u32 temp;
4761         int target_clock, pixel_multiplier, lane, link_bw, factor;
4762         unsigned int pipe_bpp;
4763         bool dither;
4764         bool is_cpu_edp = false, is_pch_edp = false;
4765
4766         for_each_encoder_on_crtc(dev, crtc, encoder) {
4767                 switch (encoder->type) {
4768                 case INTEL_OUTPUT_LVDS:
4769                         is_lvds = true;
4770                         break;
4771                 case INTEL_OUTPUT_SDVO:
4772                 case INTEL_OUTPUT_HDMI:
4773                         is_sdvo = true;
4774                         if (encoder->needs_tv_clock)
4775                                 is_tv = true;
4776                         break;
4777                 case INTEL_OUTPUT_TVOUT:
4778                         is_tv = true;
4779                         break;
4780                 case INTEL_OUTPUT_ANALOG:
4781                         is_crt = true;
4782                         break;
4783                 case INTEL_OUTPUT_DISPLAYPORT:
4784                         is_dp = true;
4785                         break;
4786                 case INTEL_OUTPUT_EDP:
4787                         is_dp = true;
4788                         if (intel_encoder_is_pch_edp(&encoder->base))
4789                                 is_pch_edp = true;
4790                         else
4791                                 is_cpu_edp = true;
4792                         edp_encoder = encoder;
4793                         break;
4794                 }
4795
4796                 num_connectors++;
4797         }
4798
4799         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
4800                                      &has_reduced_clock, &reduced_clock);
4801         if (!ok) {
4802                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4803                 return -EINVAL;
4804         }
4805
4806         /* Ensure that the cursor is valid for the new mode before changing... */
4807         intel_crtc_update_cursor(crtc, true);
4808
4809         /* FDI link */
4810         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4811         lane = 0;
4812         /* CPU eDP doesn't require FDI link, so just set DP M/N
4813            according to current link config */
4814         if (is_cpu_edp) {
4815                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4816         } else {
4817                 /* FDI is a binary signal running at ~2.7GHz, encoding
4818                  * each output octet as 10 bits. The actual frequency
4819                  * is stored as a divider into a 100MHz clock, and the
4820                  * mode pixel clock is stored in units of 1KHz.
4821                  * Hence the bw of each lane in terms of the mode signal
4822                  * is:
4823                  */
4824                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4825         }
4826
4827         /* [e]DP over FDI requires target mode clock instead of link clock. */
4828         if (edp_encoder)
4829                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4830         else if (is_dp)
4831                 target_clock = mode->clock;
4832         else
4833                 target_clock = adjusted_mode->clock;
4834
4835         /* determine panel color depth */
4836         dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp,
4837                                               adjusted_mode);
4838         if (is_lvds && dev_priv->lvds_dither)
4839                 dither = true;
4840
4841         if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
4842             pipe_bpp != 36) {
4843                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4844                      pipe_bpp);
4845                 pipe_bpp = 24;
4846         }
4847         intel_crtc->bpp = pipe_bpp;
4848
4849         if (!lane) {
4850                 /*
4851                  * Account for spread spectrum to avoid
4852                  * oversubscribing the link. Max center spread
4853                  * is 2.5%; use 5% for safety's sake.
4854                  */
4855                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4856                 lane = bps / (link_bw * 8) + 1;
4857         }
4858
4859         intel_crtc->fdi_lanes = lane;
4860
4861         if (pixel_multiplier > 1)
4862                 link_bw *= pixel_multiplier;
4863         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4864                              &m_n);
4865
4866         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4867         if (has_reduced_clock)
4868                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4869                         reduced_clock.m2;
4870
4871         /* Enable autotuning of the PLL clock (if permissible) */
4872         factor = 21;
4873         if (is_lvds) {
4874                 if ((intel_panel_use_ssc(dev_priv) &&
4875                      dev_priv->lvds_ssc_freq == 100) ||
4876                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4877                         factor = 25;
4878         } else if (is_sdvo && is_tv)
4879                 factor = 20;
4880
4881         if (clock.m < factor * clock.n)
4882                 fp |= FP_CB_TUNE;
4883
4884         dpll = 0;
4885
4886         if (is_lvds)
4887                 dpll |= DPLLB_MODE_LVDS;
4888         else
4889                 dpll |= DPLLB_MODE_DAC_SERIAL;
4890         if (is_sdvo) {
4891                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4892                 if (pixel_multiplier > 1) {
4893                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4894                 }
4895                 dpll |= DPLL_DVO_HIGH_SPEED;
4896         }
4897         if (is_dp && !is_cpu_edp)
4898                 dpll |= DPLL_DVO_HIGH_SPEED;
4899
4900         /* compute bitmask from p1 value */
4901         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4902         /* also FPA1 */
4903         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4904
4905         switch (clock.p2) {
4906         case 5:
4907                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4908                 break;
4909         case 7:
4910                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4911                 break;
4912         case 10:
4913                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4914                 break;
4915         case 14:
4916                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4917                 break;
4918         }
4919
4920         if (is_sdvo && is_tv)
4921                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4922         else if (is_tv)
4923                 /* XXX: just matching BIOS for now */
4924                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4925                 dpll |= 3;
4926         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4927                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4928         else
4929                 dpll |= PLL_REF_INPUT_DREFCLK;
4930
4931         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4932         drm_mode_debug_printmodeline(mode);
4933
4934         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4935          * pre-Haswell/LPT generation */
4936         if (HAS_PCH_LPT(dev)) {
4937                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4938                                 pipe);
4939         } else if (!is_cpu_edp) {
4940                 struct intel_pch_pll *pll;
4941
4942                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4943                 if (pll == NULL) {
4944                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4945                                          pipe);
4946                         return -EINVAL;
4947                 }
4948         } else
4949                 intel_put_pch_pll(intel_crtc);
4950
4951         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4952          * This is an exception to the general rule that mode_set doesn't turn
4953          * things on.
4954          */
4955         if (is_lvds) {
4956                 temp = I915_READ(PCH_LVDS);
4957                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4958                 if (HAS_PCH_CPT(dev)) {
4959                         temp &= ~PORT_TRANS_SEL_MASK;
4960                         temp |= PORT_TRANS_SEL_CPT(pipe);
4961                 } else {
4962                         if (pipe == 1)
4963                                 temp |= LVDS_PIPEB_SELECT;
4964                         else
4965                                 temp &= ~LVDS_PIPEB_SELECT;
4966                 }
4967
4968                 /* set the corresponsding LVDS_BORDER bit */
4969                 temp |= dev_priv->lvds_border_bits;
4970                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4971                  * set the DPLLs for dual-channel mode or not.
4972                  */
4973                 if (clock.p2 == 7)
4974                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4975                 else
4976                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4977
4978                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4979                  * appropriately here, but we need to look more thoroughly into how
4980                  * panels behave in the two modes.
4981                  */
4982                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4983                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4984                         temp |= LVDS_HSYNC_POLARITY;
4985                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4986                         temp |= LVDS_VSYNC_POLARITY;
4987                 I915_WRITE(PCH_LVDS, temp);
4988         }
4989
4990         if (is_dp && !is_cpu_edp) {
4991                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4992         } else {
4993                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4994                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4995                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4996                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4997                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4998         }
4999
5000         if (intel_crtc->pch_pll) {
5001                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5002
5003                 /* Wait for the clocks to stabilize. */
5004                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5005                 udelay(150);
5006
5007                 /* The pixel multiplier can only be updated once the
5008                  * DPLL is enabled and the clocks are stable.
5009                  *
5010                  * So write it again.
5011                  */
5012                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5013         }
5014
5015         intel_crtc->lowfreq_avail = false;
5016         if (intel_crtc->pch_pll) {
5017                 if (is_lvds && has_reduced_clock && i915_powersave) {
5018                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5019                         intel_crtc->lowfreq_avail = true;
5020                 } else {
5021                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5022                 }
5023         }
5024
5025         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5026                 /* the chip adds 2 halflines automatically */
5027                 adjusted_mode->crtc_vtotal -= 1;
5028                 adjusted_mode->crtc_vblank_end -= 1;
5029                 I915_WRITE(VSYNCSHIFT(pipe),
5030                            adjusted_mode->crtc_hsync_start
5031                            - adjusted_mode->crtc_htotal/2);
5032         } else {
5033                 I915_WRITE(VSYNCSHIFT(pipe), 0);
5034         }
5035
5036         I915_WRITE(HTOTAL(pipe),
5037                    (adjusted_mode->crtc_hdisplay - 1) |
5038                    ((adjusted_mode->crtc_htotal - 1) << 16));
5039         I915_WRITE(HBLANK(pipe),
5040                    (adjusted_mode->crtc_hblank_start - 1) |
5041                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5042         I915_WRITE(HSYNC(pipe),
5043                    (adjusted_mode->crtc_hsync_start - 1) |
5044                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5045
5046         I915_WRITE(VTOTAL(pipe),
5047                    (adjusted_mode->crtc_vdisplay - 1) |
5048                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5049         I915_WRITE(VBLANK(pipe),
5050                    (adjusted_mode->crtc_vblank_start - 1) |
5051                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5052         I915_WRITE(VSYNC(pipe),
5053                    (adjusted_mode->crtc_vsync_start - 1) |
5054                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5055
5056         /* pipesrc controls the size that is scaled from, which should
5057          * always be the user's requested size.
5058          */
5059         I915_WRITE(PIPESRC(pipe),
5060                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5061
5062         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5063         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5064         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5065         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5066
5067         if (is_cpu_edp)
5068                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5069
5070         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5071
5072         intel_wait_for_vblank(dev, pipe);
5073
5074         /* Set up the display plane register */
5075         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5076         POSTING_READ(DSPCNTR(plane));
5077
5078         ret = intel_pipe_set_base(crtc, x, y, fb);
5079
5080         intel_update_watermarks(dev);
5081
5082         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5083
5084         return ret;
5085 }
5086
5087 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5088                                struct drm_display_mode *mode,
5089                                struct drm_display_mode *adjusted_mode,
5090                                int x, int y,
5091                                struct drm_framebuffer *fb)
5092 {
5093         struct drm_device *dev = crtc->dev;
5094         struct drm_i915_private *dev_priv = dev->dev_private;
5095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5096         int pipe = intel_crtc->pipe;
5097         int ret;
5098
5099         drm_vblank_pre_modeset(dev, pipe);
5100
5101         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5102                                               x, y, fb);
5103         drm_vblank_post_modeset(dev, pipe);
5104
5105         return ret;
5106 }
5107
5108 static bool intel_eld_uptodate(struct drm_connector *connector,
5109                                int reg_eldv, uint32_t bits_eldv,
5110                                int reg_elda, uint32_t bits_elda,
5111                                int reg_edid)
5112 {
5113         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5114         uint8_t *eld = connector->eld;
5115         uint32_t i;
5116
5117         i = I915_READ(reg_eldv);
5118         i &= bits_eldv;
5119
5120         if (!eld[0])
5121                 return !i;
5122
5123         if (!i)
5124                 return false;
5125
5126         i = I915_READ(reg_elda);
5127         i &= ~bits_elda;
5128         I915_WRITE(reg_elda, i);
5129
5130         for (i = 0; i < eld[2]; i++)
5131                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5132                         return false;
5133
5134         return true;
5135 }
5136
5137 static void g4x_write_eld(struct drm_connector *connector,
5138                           struct drm_crtc *crtc)
5139 {
5140         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5141         uint8_t *eld = connector->eld;
5142         uint32_t eldv;
5143         uint32_t len;
5144         uint32_t i;
5145
5146         i = I915_READ(G4X_AUD_VID_DID);
5147
5148         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5149                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5150         else
5151                 eldv = G4X_ELDV_DEVCTG;
5152
5153         if (intel_eld_uptodate(connector,
5154                                G4X_AUD_CNTL_ST, eldv,
5155                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5156                                G4X_HDMIW_HDMIEDID))
5157                 return;
5158
5159         i = I915_READ(G4X_AUD_CNTL_ST);
5160         i &= ~(eldv | G4X_ELD_ADDR);
5161         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5162         I915_WRITE(G4X_AUD_CNTL_ST, i);
5163
5164         if (!eld[0])
5165                 return;
5166
5167         len = min_t(uint8_t, eld[2], len);
5168         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5169         for (i = 0; i < len; i++)
5170                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5171
5172         i = I915_READ(G4X_AUD_CNTL_ST);
5173         i |= eldv;
5174         I915_WRITE(G4X_AUD_CNTL_ST, i);
5175 }
5176
5177 static void haswell_write_eld(struct drm_connector *connector,
5178                                      struct drm_crtc *crtc)
5179 {
5180         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5181         uint8_t *eld = connector->eld;
5182         struct drm_device *dev = crtc->dev;
5183         uint32_t eldv;
5184         uint32_t i;
5185         int len;
5186         int pipe = to_intel_crtc(crtc)->pipe;
5187         int tmp;
5188
5189         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5190         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5191         int aud_config = HSW_AUD_CFG(pipe);
5192         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5193
5194
5195         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5196
5197         /* Audio output enable */
5198         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5199         tmp = I915_READ(aud_cntrl_st2);
5200         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5201         I915_WRITE(aud_cntrl_st2, tmp);
5202
5203         /* Wait for 1 vertical blank */
5204         intel_wait_for_vblank(dev, pipe);
5205
5206         /* Set ELD valid state */
5207         tmp = I915_READ(aud_cntrl_st2);
5208         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5209         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5210         I915_WRITE(aud_cntrl_st2, tmp);
5211         tmp = I915_READ(aud_cntrl_st2);
5212         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5213
5214         /* Enable HDMI mode */
5215         tmp = I915_READ(aud_config);
5216         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5217         /* clear N_programing_enable and N_value_index */
5218         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5219         I915_WRITE(aud_config, tmp);
5220
5221         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5222
5223         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5224
5225         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5226                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5227                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5228                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5229         } else
5230                 I915_WRITE(aud_config, 0);
5231
5232         if (intel_eld_uptodate(connector,
5233                                aud_cntrl_st2, eldv,
5234                                aud_cntl_st, IBX_ELD_ADDRESS,
5235                                hdmiw_hdmiedid))
5236                 return;
5237
5238         i = I915_READ(aud_cntrl_st2);
5239         i &= ~eldv;
5240         I915_WRITE(aud_cntrl_st2, i);
5241
5242         if (!eld[0])
5243                 return;
5244
5245         i = I915_READ(aud_cntl_st);
5246         i &= ~IBX_ELD_ADDRESS;
5247         I915_WRITE(aud_cntl_st, i);
5248         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5249         DRM_DEBUG_DRIVER("port num:%d\n", i);
5250
5251         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5252         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5253         for (i = 0; i < len; i++)
5254                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5255
5256         i = I915_READ(aud_cntrl_st2);
5257         i |= eldv;
5258         I915_WRITE(aud_cntrl_st2, i);
5259
5260 }
5261
5262 static void ironlake_write_eld(struct drm_connector *connector,
5263                                      struct drm_crtc *crtc)
5264 {
5265         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5266         uint8_t *eld = connector->eld;
5267         uint32_t eldv;
5268         uint32_t i;
5269         int len;
5270         int hdmiw_hdmiedid;
5271         int aud_config;
5272         int aud_cntl_st;
5273         int aud_cntrl_st2;
5274         int pipe = to_intel_crtc(crtc)->pipe;
5275
5276         if (HAS_PCH_IBX(connector->dev)) {
5277                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5278                 aud_config = IBX_AUD_CFG(pipe);
5279                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5280                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5281         } else {
5282                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5283                 aud_config = CPT_AUD_CFG(pipe);
5284                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5285                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5286         }
5287
5288         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5289
5290         i = I915_READ(aud_cntl_st);
5291         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5292         if (!i) {
5293                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5294                 /* operate blindly on all ports */
5295                 eldv = IBX_ELD_VALIDB;
5296                 eldv |= IBX_ELD_VALIDB << 4;
5297                 eldv |= IBX_ELD_VALIDB << 8;
5298         } else {
5299                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5300                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5301         }
5302
5303         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5304                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5305                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5306                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5307         } else
5308                 I915_WRITE(aud_config, 0);
5309
5310         if (intel_eld_uptodate(connector,
5311                                aud_cntrl_st2, eldv,
5312                                aud_cntl_st, IBX_ELD_ADDRESS,
5313                                hdmiw_hdmiedid))
5314                 return;
5315
5316         i = I915_READ(aud_cntrl_st2);
5317         i &= ~eldv;
5318         I915_WRITE(aud_cntrl_st2, i);
5319
5320         if (!eld[0])
5321                 return;
5322
5323         i = I915_READ(aud_cntl_st);
5324         i &= ~IBX_ELD_ADDRESS;
5325         I915_WRITE(aud_cntl_st, i);
5326
5327         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5328         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5329         for (i = 0; i < len; i++)
5330                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5331
5332         i = I915_READ(aud_cntrl_st2);
5333         i |= eldv;
5334         I915_WRITE(aud_cntrl_st2, i);
5335 }
5336
5337 void intel_write_eld(struct drm_encoder *encoder,
5338                      struct drm_display_mode *mode)
5339 {
5340         struct drm_crtc *crtc = encoder->crtc;
5341         struct drm_connector *connector;
5342         struct drm_device *dev = encoder->dev;
5343         struct drm_i915_private *dev_priv = dev->dev_private;
5344
5345         connector = drm_select_eld(encoder, mode);
5346         if (!connector)
5347                 return;
5348
5349         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5350                          connector->base.id,
5351                          drm_get_connector_name(connector),
5352                          connector->encoder->base.id,
5353                          drm_get_encoder_name(connector->encoder));
5354
5355         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5356
5357         if (dev_priv->display.write_eld)
5358                 dev_priv->display.write_eld(connector, crtc);
5359 }
5360
5361 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5362 void intel_crtc_load_lut(struct drm_crtc *crtc)
5363 {
5364         struct drm_device *dev = crtc->dev;
5365         struct drm_i915_private *dev_priv = dev->dev_private;
5366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5367         int palreg = PALETTE(intel_crtc->pipe);
5368         int i;
5369
5370         /* The clocks have to be on to load the palette. */
5371         if (!crtc->enabled || !intel_crtc->active)
5372                 return;
5373
5374         /* use legacy palette for Ironlake */
5375         if (HAS_PCH_SPLIT(dev))
5376                 palreg = LGC_PALETTE(intel_crtc->pipe);
5377
5378         for (i = 0; i < 256; i++) {
5379                 I915_WRITE(palreg + 4 * i,
5380                            (intel_crtc->lut_r[i] << 16) |
5381                            (intel_crtc->lut_g[i] << 8) |
5382                            intel_crtc->lut_b[i]);
5383         }
5384 }
5385
5386 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5387 {
5388         struct drm_device *dev = crtc->dev;
5389         struct drm_i915_private *dev_priv = dev->dev_private;
5390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5391         bool visible = base != 0;
5392         u32 cntl;
5393
5394         if (intel_crtc->cursor_visible == visible)
5395                 return;
5396
5397         cntl = I915_READ(_CURACNTR);
5398         if (visible) {
5399                 /* On these chipsets we can only modify the base whilst
5400                  * the cursor is disabled.
5401                  */
5402                 I915_WRITE(_CURABASE, base);
5403
5404                 cntl &= ~(CURSOR_FORMAT_MASK);
5405                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5406                 cntl |= CURSOR_ENABLE |
5407                         CURSOR_GAMMA_ENABLE |
5408                         CURSOR_FORMAT_ARGB;
5409         } else
5410                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5411         I915_WRITE(_CURACNTR, cntl);
5412
5413         intel_crtc->cursor_visible = visible;
5414 }
5415
5416 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5417 {
5418         struct drm_device *dev = crtc->dev;
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5421         int pipe = intel_crtc->pipe;
5422         bool visible = base != 0;
5423
5424         if (intel_crtc->cursor_visible != visible) {
5425                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5426                 if (base) {
5427                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5428                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5429                         cntl |= pipe << 28; /* Connect to correct pipe */
5430                 } else {
5431                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5432                         cntl |= CURSOR_MODE_DISABLE;
5433                 }
5434                 I915_WRITE(CURCNTR(pipe), cntl);
5435
5436                 intel_crtc->cursor_visible = visible;
5437         }
5438         /* and commit changes on next vblank */
5439         I915_WRITE(CURBASE(pipe), base);
5440 }
5441
5442 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5443 {
5444         struct drm_device *dev = crtc->dev;
5445         struct drm_i915_private *dev_priv = dev->dev_private;
5446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5447         int pipe = intel_crtc->pipe;
5448         bool visible = base != 0;
5449
5450         if (intel_crtc->cursor_visible != visible) {
5451                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5452                 if (base) {
5453                         cntl &= ~CURSOR_MODE;
5454                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5455                 } else {
5456                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5457                         cntl |= CURSOR_MODE_DISABLE;
5458                 }
5459                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5460
5461                 intel_crtc->cursor_visible = visible;
5462         }
5463         /* and commit changes on next vblank */
5464         I915_WRITE(CURBASE_IVB(pipe), base);
5465 }
5466
5467 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5468 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5469                                      bool on)
5470 {
5471         struct drm_device *dev = crtc->dev;
5472         struct drm_i915_private *dev_priv = dev->dev_private;
5473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5474         int pipe = intel_crtc->pipe;
5475         int x = intel_crtc->cursor_x;
5476         int y = intel_crtc->cursor_y;
5477         u32 base, pos;
5478         bool visible;
5479
5480         pos = 0;
5481
5482         if (on && crtc->enabled && crtc->fb) {
5483                 base = intel_crtc->cursor_addr;
5484                 if (x > (int) crtc->fb->width)
5485                         base = 0;
5486
5487                 if (y > (int) crtc->fb->height)
5488                         base = 0;
5489         } else
5490                 base = 0;
5491
5492         if (x < 0) {
5493                 if (x + intel_crtc->cursor_width < 0)
5494                         base = 0;
5495
5496                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5497                 x = -x;
5498         }
5499         pos |= x << CURSOR_X_SHIFT;
5500
5501         if (y < 0) {
5502                 if (y + intel_crtc->cursor_height < 0)
5503                         base = 0;
5504
5505                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5506                 y = -y;
5507         }
5508         pos |= y << CURSOR_Y_SHIFT;
5509
5510         visible = base != 0;
5511         if (!visible && !intel_crtc->cursor_visible)
5512                 return;
5513
5514         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5515                 I915_WRITE(CURPOS_IVB(pipe), pos);
5516                 ivb_update_cursor(crtc, base);
5517         } else {
5518                 I915_WRITE(CURPOS(pipe), pos);
5519                 if (IS_845G(dev) || IS_I865G(dev))
5520                         i845_update_cursor(crtc, base);
5521                 else
5522                         i9xx_update_cursor(crtc, base);
5523         }
5524 }
5525
5526 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5527                                  struct drm_file *file,
5528                                  uint32_t handle,
5529                                  uint32_t width, uint32_t height)
5530 {
5531         struct drm_device *dev = crtc->dev;
5532         struct drm_i915_private *dev_priv = dev->dev_private;
5533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5534         struct drm_i915_gem_object *obj;
5535         uint32_t addr;
5536         int ret;
5537
5538         /* if we want to turn off the cursor ignore width and height */
5539         if (!handle) {
5540                 DRM_DEBUG_KMS("cursor off\n");
5541                 addr = 0;
5542                 obj = NULL;
5543                 mutex_lock(&dev->struct_mutex);
5544                 goto finish;
5545         }
5546
5547         /* Currently we only support 64x64 cursors */
5548         if (width != 64 || height != 64) {
5549                 DRM_ERROR("we currently only support 64x64 cursors\n");
5550                 return -EINVAL;
5551         }
5552
5553         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5554         if (&obj->base == NULL)
5555                 return -ENOENT;
5556
5557         if (obj->base.size < width * height * 4) {
5558                 DRM_ERROR("buffer is to small\n");
5559                 ret = -ENOMEM;
5560                 goto fail;
5561         }
5562
5563         /* we only need to pin inside GTT if cursor is non-phy */
5564         mutex_lock(&dev->struct_mutex);
5565         if (!dev_priv->info->cursor_needs_physical) {
5566                 if (obj->tiling_mode) {
5567                         DRM_ERROR("cursor cannot be tiled\n");
5568                         ret = -EINVAL;
5569                         goto fail_locked;
5570                 }
5571
5572                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5573                 if (ret) {
5574                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5575                         goto fail_locked;
5576                 }
5577
5578                 ret = i915_gem_object_put_fence(obj);
5579                 if (ret) {
5580                         DRM_ERROR("failed to release fence for cursor");
5581                         goto fail_unpin;
5582                 }
5583
5584                 addr = obj->gtt_offset;
5585         } else {
5586                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5587                 ret = i915_gem_attach_phys_object(dev, obj,
5588                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5589                                                   align);
5590                 if (ret) {
5591                         DRM_ERROR("failed to attach phys object\n");
5592                         goto fail_locked;
5593                 }
5594                 addr = obj->phys_obj->handle->busaddr;
5595         }
5596
5597         if (IS_GEN2(dev))
5598                 I915_WRITE(CURSIZE, (height << 12) | width);
5599
5600  finish:
5601         if (intel_crtc->cursor_bo) {
5602                 if (dev_priv->info->cursor_needs_physical) {
5603                         if (intel_crtc->cursor_bo != obj)
5604                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5605                 } else
5606                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5607                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5608         }
5609
5610         mutex_unlock(&dev->struct_mutex);
5611
5612         intel_crtc->cursor_addr = addr;
5613         intel_crtc->cursor_bo = obj;
5614         intel_crtc->cursor_width = width;
5615         intel_crtc->cursor_height = height;
5616
5617         intel_crtc_update_cursor(crtc, true);
5618
5619         return 0;
5620 fail_unpin:
5621         i915_gem_object_unpin(obj);
5622 fail_locked:
5623         mutex_unlock(&dev->struct_mutex);
5624 fail:
5625         drm_gem_object_unreference_unlocked(&obj->base);
5626         return ret;
5627 }
5628
5629 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5630 {
5631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5632
5633         intel_crtc->cursor_x = x;
5634         intel_crtc->cursor_y = y;
5635
5636         intel_crtc_update_cursor(crtc, true);
5637
5638         return 0;
5639 }
5640
5641 /** Sets the color ramps on behalf of RandR */
5642 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5643                                  u16 blue, int regno)
5644 {
5645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5646
5647         intel_crtc->lut_r[regno] = red >> 8;
5648         intel_crtc->lut_g[regno] = green >> 8;
5649         intel_crtc->lut_b[regno] = blue >> 8;
5650 }
5651
5652 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5653                              u16 *blue, int regno)
5654 {
5655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5656
5657         *red = intel_crtc->lut_r[regno] << 8;
5658         *green = intel_crtc->lut_g[regno] << 8;
5659         *blue = intel_crtc->lut_b[regno] << 8;
5660 }
5661
5662 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5663                                  u16 *blue, uint32_t start, uint32_t size)
5664 {
5665         int end = (start + size > 256) ? 256 : start + size, i;
5666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5667
5668         for (i = start; i < end; i++) {
5669                 intel_crtc->lut_r[i] = red[i] >> 8;
5670                 intel_crtc->lut_g[i] = green[i] >> 8;
5671                 intel_crtc->lut_b[i] = blue[i] >> 8;
5672         }
5673
5674         intel_crtc_load_lut(crtc);
5675 }
5676
5677 /**
5678  * Get a pipe with a simple mode set on it for doing load-based monitor
5679  * detection.
5680  *
5681  * It will be up to the load-detect code to adjust the pipe as appropriate for
5682  * its requirements.  The pipe will be connected to no other encoders.
5683  *
5684  * Currently this code will only succeed if there is a pipe with no encoders
5685  * configured for it.  In the future, it could choose to temporarily disable
5686  * some outputs to free up a pipe for its use.
5687  *
5688  * \return crtc, or NULL if no pipes are available.
5689  */
5690
5691 /* VESA 640x480x72Hz mode to set on the pipe */
5692 static struct drm_display_mode load_detect_mode = {
5693         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5694                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5695 };
5696
5697 static struct drm_framebuffer *
5698 intel_framebuffer_create(struct drm_device *dev,
5699                          struct drm_mode_fb_cmd2 *mode_cmd,
5700                          struct drm_i915_gem_object *obj)
5701 {
5702         struct intel_framebuffer *intel_fb;
5703         int ret;
5704
5705         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5706         if (!intel_fb) {
5707                 drm_gem_object_unreference_unlocked(&obj->base);
5708                 return ERR_PTR(-ENOMEM);
5709         }
5710
5711         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5712         if (ret) {
5713                 drm_gem_object_unreference_unlocked(&obj->base);
5714                 kfree(intel_fb);
5715                 return ERR_PTR(ret);
5716         }
5717
5718         return &intel_fb->base;
5719 }
5720
5721 static u32
5722 intel_framebuffer_pitch_for_width(int width, int bpp)
5723 {
5724         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5725         return ALIGN(pitch, 64);
5726 }
5727
5728 static u32
5729 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5730 {
5731         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5732         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5733 }
5734
5735 static struct drm_framebuffer *
5736 intel_framebuffer_create_for_mode(struct drm_device *dev,
5737                                   struct drm_display_mode *mode,
5738                                   int depth, int bpp)
5739 {
5740         struct drm_i915_gem_object *obj;
5741         struct drm_mode_fb_cmd2 mode_cmd;
5742
5743         obj = i915_gem_alloc_object(dev,
5744                                     intel_framebuffer_size_for_mode(mode, bpp));
5745         if (obj == NULL)
5746                 return ERR_PTR(-ENOMEM);
5747
5748         mode_cmd.width = mode->hdisplay;
5749         mode_cmd.height = mode->vdisplay;
5750         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5751                                                                 bpp);
5752         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5753
5754         return intel_framebuffer_create(dev, &mode_cmd, obj);
5755 }
5756
5757 static struct drm_framebuffer *
5758 mode_fits_in_fbdev(struct drm_device *dev,
5759                    struct drm_display_mode *mode)
5760 {
5761         struct drm_i915_private *dev_priv = dev->dev_private;
5762         struct drm_i915_gem_object *obj;
5763         struct drm_framebuffer *fb;
5764
5765         if (dev_priv->fbdev == NULL)
5766                 return NULL;
5767
5768         obj = dev_priv->fbdev->ifb.obj;
5769         if (obj == NULL)
5770                 return NULL;
5771
5772         fb = &dev_priv->fbdev->ifb.base;
5773         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5774                                                                fb->bits_per_pixel))
5775                 return NULL;
5776
5777         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5778                 return NULL;
5779
5780         return fb;
5781 }
5782
5783 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5784                                 struct drm_display_mode *mode,
5785                                 struct intel_load_detect_pipe *old)
5786 {
5787         struct intel_crtc *intel_crtc;
5788         struct intel_encoder *intel_encoder =
5789                 intel_attached_encoder(connector);
5790         struct drm_crtc *possible_crtc;
5791         struct drm_encoder *encoder = &intel_encoder->base;
5792         struct drm_crtc *crtc = NULL;
5793         struct drm_device *dev = encoder->dev;
5794         struct drm_framebuffer *fb;
5795         int i = -1;
5796
5797         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5798                       connector->base.id, drm_get_connector_name(connector),
5799                       encoder->base.id, drm_get_encoder_name(encoder));
5800
5801         /*
5802          * Algorithm gets a little messy:
5803          *
5804          *   - if the connector already has an assigned crtc, use it (but make
5805          *     sure it's on first)
5806          *
5807          *   - try to find the first unused crtc that can drive this connector,
5808          *     and use that if we find one
5809          */
5810
5811         /* See if we already have a CRTC for this connector */
5812         if (encoder->crtc) {
5813                 crtc = encoder->crtc;
5814
5815                 old->dpms_mode = connector->dpms;
5816                 old->load_detect_temp = false;
5817
5818                 /* Make sure the crtc and connector are running */
5819                 if (connector->dpms != DRM_MODE_DPMS_ON)
5820                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5821
5822                 return true;
5823         }
5824
5825         /* Find an unused one (if possible) */
5826         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5827                 i++;
5828                 if (!(encoder->possible_crtcs & (1 << i)))
5829                         continue;
5830                 if (!possible_crtc->enabled) {
5831                         crtc = possible_crtc;
5832                         break;
5833                 }
5834         }
5835
5836         /*
5837          * If we didn't find an unused CRTC, don't use any.
5838          */
5839         if (!crtc) {
5840                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5841                 return false;
5842         }
5843
5844         intel_encoder->new_crtc = to_intel_crtc(crtc);
5845         to_intel_connector(connector)->new_encoder = intel_encoder;
5846
5847         intel_crtc = to_intel_crtc(crtc);
5848         old->dpms_mode = connector->dpms;
5849         old->load_detect_temp = true;
5850         old->release_fb = NULL;
5851
5852         if (!mode)
5853                 mode = &load_detect_mode;
5854
5855         /* We need a framebuffer large enough to accommodate all accesses
5856          * that the plane may generate whilst we perform load detection.
5857          * We can not rely on the fbcon either being present (we get called
5858          * during its initialisation to detect all boot displays, or it may
5859          * not even exist) or that it is large enough to satisfy the
5860          * requested mode.
5861          */
5862         fb = mode_fits_in_fbdev(dev, mode);
5863         if (fb == NULL) {
5864                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5865                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5866                 old->release_fb = fb;
5867         } else
5868                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5869         if (IS_ERR(fb)) {
5870                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5871                 goto fail;
5872         }
5873
5874         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5875                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5876                 if (old->release_fb)
5877                         old->release_fb->funcs->destroy(old->release_fb);
5878                 goto fail;
5879         }
5880
5881         /* let the connector get through one full cycle before testing */
5882         intel_wait_for_vblank(dev, intel_crtc->pipe);
5883
5884         return true;
5885 fail:
5886         connector->encoder = NULL;
5887         encoder->crtc = NULL;
5888         return false;
5889 }
5890
5891 void intel_release_load_detect_pipe(struct drm_connector *connector,
5892                                     struct intel_load_detect_pipe *old)
5893 {
5894         struct intel_encoder *intel_encoder =
5895                 intel_attached_encoder(connector);
5896         struct drm_encoder *encoder = &intel_encoder->base;
5897
5898         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5899                       connector->base.id, drm_get_connector_name(connector),
5900                       encoder->base.id, drm_get_encoder_name(encoder));
5901
5902         if (old->load_detect_temp) {
5903                 struct drm_crtc *crtc = encoder->crtc;
5904
5905                 to_intel_connector(connector)->new_encoder = NULL;
5906                 intel_encoder->new_crtc = NULL;
5907                 intel_set_mode(crtc, NULL, 0, 0, NULL);
5908
5909                 if (old->release_fb)
5910                         old->release_fb->funcs->destroy(old->release_fb);
5911
5912                 return;
5913         }
5914
5915         /* Switch crtc and encoder back off if necessary */
5916         if (old->dpms_mode != DRM_MODE_DPMS_ON)
5917                 connector->funcs->dpms(connector, old->dpms_mode);
5918 }
5919
5920 /* Returns the clock of the currently programmed mode of the given pipe. */
5921 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5922 {
5923         struct drm_i915_private *dev_priv = dev->dev_private;
5924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5925         int pipe = intel_crtc->pipe;
5926         u32 dpll = I915_READ(DPLL(pipe));
5927         u32 fp;
5928         intel_clock_t clock;
5929
5930         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5931                 fp = I915_READ(FP0(pipe));
5932         else
5933                 fp = I915_READ(FP1(pipe));
5934
5935         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5936         if (IS_PINEVIEW(dev)) {
5937                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5938                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5939         } else {
5940                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5941                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5942         }
5943
5944         if (!IS_GEN2(dev)) {
5945                 if (IS_PINEVIEW(dev))
5946                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5947                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5948                 else
5949                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5950                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5951
5952                 switch (dpll & DPLL_MODE_MASK) {
5953                 case DPLLB_MODE_DAC_SERIAL:
5954                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5955                                 5 : 10;
5956                         break;
5957                 case DPLLB_MODE_LVDS:
5958                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5959                                 7 : 14;
5960                         break;
5961                 default:
5962                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5963                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5964                         return 0;
5965                 }
5966
5967                 /* XXX: Handle the 100Mhz refclk */
5968                 intel_clock(dev, 96000, &clock);
5969         } else {
5970                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5971
5972                 if (is_lvds) {
5973                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5974                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5975                         clock.p2 = 14;
5976
5977                         if ((dpll & PLL_REF_INPUT_MASK) ==
5978                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5979                                 /* XXX: might not be 66MHz */
5980                                 intel_clock(dev, 66000, &clock);
5981                         } else
5982                                 intel_clock(dev, 48000, &clock);
5983                 } else {
5984                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5985                                 clock.p1 = 2;
5986                         else {
5987                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5988                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5989                         }
5990                         if (dpll & PLL_P2_DIVIDE_BY_4)
5991                                 clock.p2 = 4;
5992                         else
5993                                 clock.p2 = 2;
5994
5995                         intel_clock(dev, 48000, &clock);
5996                 }
5997         }
5998
5999         /* XXX: It would be nice to validate the clocks, but we can't reuse
6000          * i830PllIsValid() because it relies on the xf86_config connector
6001          * configuration being accurate, which it isn't necessarily.
6002          */
6003
6004         return clock.dot;
6005 }
6006
6007 /** Returns the currently programmed mode of the given pipe. */
6008 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6009                                              struct drm_crtc *crtc)
6010 {
6011         struct drm_i915_private *dev_priv = dev->dev_private;
6012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6013         int pipe = intel_crtc->pipe;
6014         struct drm_display_mode *mode;
6015         int htot = I915_READ(HTOTAL(pipe));
6016         int hsync = I915_READ(HSYNC(pipe));
6017         int vtot = I915_READ(VTOTAL(pipe));
6018         int vsync = I915_READ(VSYNC(pipe));
6019
6020         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6021         if (!mode)
6022                 return NULL;
6023
6024         mode->clock = intel_crtc_clock_get(dev, crtc);
6025         mode->hdisplay = (htot & 0xffff) + 1;
6026         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6027         mode->hsync_start = (hsync & 0xffff) + 1;
6028         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6029         mode->vdisplay = (vtot & 0xffff) + 1;
6030         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6031         mode->vsync_start = (vsync & 0xffff) + 1;
6032         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6033
6034         drm_mode_set_name(mode);
6035
6036         return mode;
6037 }
6038
6039 static void intel_increase_pllclock(struct drm_crtc *crtc)
6040 {
6041         struct drm_device *dev = crtc->dev;
6042         drm_i915_private_t *dev_priv = dev->dev_private;
6043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6044         int pipe = intel_crtc->pipe;
6045         int dpll_reg = DPLL(pipe);
6046         int dpll;
6047
6048         if (HAS_PCH_SPLIT(dev))
6049                 return;
6050
6051         if (!dev_priv->lvds_downclock_avail)
6052                 return;
6053
6054         dpll = I915_READ(dpll_reg);
6055         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6056                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6057
6058                 assert_panel_unlocked(dev_priv, pipe);
6059
6060                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6061                 I915_WRITE(dpll_reg, dpll);
6062                 intel_wait_for_vblank(dev, pipe);
6063
6064                 dpll = I915_READ(dpll_reg);
6065                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6066                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6067         }
6068 }
6069
6070 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6071 {
6072         struct drm_device *dev = crtc->dev;
6073         drm_i915_private_t *dev_priv = dev->dev_private;
6074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075
6076         if (HAS_PCH_SPLIT(dev))
6077                 return;
6078
6079         if (!dev_priv->lvds_downclock_avail)
6080                 return;
6081
6082         /*
6083          * Since this is called by a timer, we should never get here in
6084          * the manual case.
6085          */
6086         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6087                 int pipe = intel_crtc->pipe;
6088                 int dpll_reg = DPLL(pipe);
6089                 int dpll;
6090
6091                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6092
6093                 assert_panel_unlocked(dev_priv, pipe);
6094
6095                 dpll = I915_READ(dpll_reg);
6096                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6097                 I915_WRITE(dpll_reg, dpll);
6098                 intel_wait_for_vblank(dev, pipe);
6099                 dpll = I915_READ(dpll_reg);
6100                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6101                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6102         }
6103
6104 }
6105
6106 void intel_mark_busy(struct drm_device *dev)
6107 {
6108         i915_update_gfx_val(dev->dev_private);
6109 }
6110
6111 void intel_mark_idle(struct drm_device *dev)
6112 {
6113 }
6114
6115 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6116 {
6117         struct drm_device *dev = obj->base.dev;
6118         struct drm_crtc *crtc;
6119
6120         if (!i915_powersave)
6121                 return;
6122
6123         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6124                 if (!crtc->fb)
6125                         continue;
6126
6127                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6128                         intel_increase_pllclock(crtc);
6129         }
6130 }
6131
6132 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6133 {
6134         struct drm_device *dev = obj->base.dev;
6135         struct drm_crtc *crtc;
6136
6137         if (!i915_powersave)
6138                 return;
6139
6140         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6141                 if (!crtc->fb)
6142                         continue;
6143
6144                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6145                         intel_decrease_pllclock(crtc);
6146         }
6147 }
6148
6149 static void intel_crtc_destroy(struct drm_crtc *crtc)
6150 {
6151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152         struct drm_device *dev = crtc->dev;
6153         struct intel_unpin_work *work;
6154         unsigned long flags;
6155
6156         spin_lock_irqsave(&dev->event_lock, flags);
6157         work = intel_crtc->unpin_work;
6158         intel_crtc->unpin_work = NULL;
6159         spin_unlock_irqrestore(&dev->event_lock, flags);
6160
6161         if (work) {
6162                 cancel_work_sync(&work->work);
6163                 kfree(work);
6164         }
6165
6166         drm_crtc_cleanup(crtc);
6167
6168         kfree(intel_crtc);
6169 }
6170
6171 static void intel_unpin_work_fn(struct work_struct *__work)
6172 {
6173         struct intel_unpin_work *work =
6174                 container_of(__work, struct intel_unpin_work, work);
6175
6176         mutex_lock(&work->dev->struct_mutex);
6177         intel_unpin_fb_obj(work->old_fb_obj);
6178         drm_gem_object_unreference(&work->pending_flip_obj->base);
6179         drm_gem_object_unreference(&work->old_fb_obj->base);
6180
6181         intel_update_fbc(work->dev);
6182         mutex_unlock(&work->dev->struct_mutex);
6183         kfree(work);
6184 }
6185
6186 static void do_intel_finish_page_flip(struct drm_device *dev,
6187                                       struct drm_crtc *crtc)
6188 {
6189         drm_i915_private_t *dev_priv = dev->dev_private;
6190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191         struct intel_unpin_work *work;
6192         struct drm_i915_gem_object *obj;
6193         struct drm_pending_vblank_event *e;
6194         struct timeval tvbl;
6195         unsigned long flags;
6196
6197         /* Ignore early vblank irqs */
6198         if (intel_crtc == NULL)
6199                 return;
6200
6201         spin_lock_irqsave(&dev->event_lock, flags);
6202         work = intel_crtc->unpin_work;
6203         if (work == NULL || !work->pending) {
6204                 spin_unlock_irqrestore(&dev->event_lock, flags);
6205                 return;
6206         }
6207
6208         intel_crtc->unpin_work = NULL;
6209
6210         if (work->event) {
6211                 e = work->event;
6212                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6213
6214                 e->event.tv_sec = tvbl.tv_sec;
6215                 e->event.tv_usec = tvbl.tv_usec;
6216
6217                 list_add_tail(&e->base.link,
6218                               &e->base.file_priv->event_list);
6219                 wake_up_interruptible(&e->base.file_priv->event_wait);
6220         }
6221
6222         drm_vblank_put(dev, intel_crtc->pipe);
6223
6224         spin_unlock_irqrestore(&dev->event_lock, flags);
6225
6226         obj = work->old_fb_obj;
6227
6228         atomic_clear_mask(1 << intel_crtc->plane,
6229                           &obj->pending_flip.counter);
6230
6231         wake_up(&dev_priv->pending_flip_queue);
6232         schedule_work(&work->work);
6233
6234         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6235 }
6236
6237 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6238 {
6239         drm_i915_private_t *dev_priv = dev->dev_private;
6240         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6241
6242         do_intel_finish_page_flip(dev, crtc);
6243 }
6244
6245 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6246 {
6247         drm_i915_private_t *dev_priv = dev->dev_private;
6248         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6249
6250         do_intel_finish_page_flip(dev, crtc);
6251 }
6252
6253 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6254 {
6255         drm_i915_private_t *dev_priv = dev->dev_private;
6256         struct intel_crtc *intel_crtc =
6257                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6258         unsigned long flags;
6259
6260         spin_lock_irqsave(&dev->event_lock, flags);
6261         if (intel_crtc->unpin_work) {
6262                 if ((++intel_crtc->unpin_work->pending) > 1)
6263                         DRM_ERROR("Prepared flip multiple times\n");
6264         } else {
6265                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6266         }
6267         spin_unlock_irqrestore(&dev->event_lock, flags);
6268 }
6269
6270 static int intel_gen2_queue_flip(struct drm_device *dev,
6271                                  struct drm_crtc *crtc,
6272                                  struct drm_framebuffer *fb,
6273                                  struct drm_i915_gem_object *obj)
6274 {
6275         struct drm_i915_private *dev_priv = dev->dev_private;
6276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6277         u32 flip_mask;
6278         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6279         int ret;
6280
6281         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6282         if (ret)
6283                 goto err;
6284
6285         ret = intel_ring_begin(ring, 6);
6286         if (ret)
6287                 goto err_unpin;
6288
6289         /* Can't queue multiple flips, so wait for the previous
6290          * one to finish before executing the next.
6291          */
6292         if (intel_crtc->plane)
6293                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6294         else
6295                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6296         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6297         intel_ring_emit(ring, MI_NOOP);
6298         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6299                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6300         intel_ring_emit(ring, fb->pitches[0]);
6301         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6302         intel_ring_emit(ring, 0); /* aux display base address, unused */
6303         intel_ring_advance(ring);
6304         return 0;
6305
6306 err_unpin:
6307         intel_unpin_fb_obj(obj);
6308 err:
6309         return ret;
6310 }
6311
6312 static int intel_gen3_queue_flip(struct drm_device *dev,
6313                                  struct drm_crtc *crtc,
6314                                  struct drm_framebuffer *fb,
6315                                  struct drm_i915_gem_object *obj)
6316 {
6317         struct drm_i915_private *dev_priv = dev->dev_private;
6318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6319         u32 flip_mask;
6320         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6321         int ret;
6322
6323         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6324         if (ret)
6325                 goto err;
6326
6327         ret = intel_ring_begin(ring, 6);
6328         if (ret)
6329                 goto err_unpin;
6330
6331         if (intel_crtc->plane)
6332                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6333         else
6334                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6335         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6336         intel_ring_emit(ring, MI_NOOP);
6337         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6338                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6339         intel_ring_emit(ring, fb->pitches[0]);
6340         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6341         intel_ring_emit(ring, MI_NOOP);
6342
6343         intel_ring_advance(ring);
6344         return 0;
6345
6346 err_unpin:
6347         intel_unpin_fb_obj(obj);
6348 err:
6349         return ret;
6350 }
6351
6352 static int intel_gen4_queue_flip(struct drm_device *dev,
6353                                  struct drm_crtc *crtc,
6354                                  struct drm_framebuffer *fb,
6355                                  struct drm_i915_gem_object *obj)
6356 {
6357         struct drm_i915_private *dev_priv = dev->dev_private;
6358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6359         uint32_t pf, pipesrc;
6360         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6361         int ret;
6362
6363         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6364         if (ret)
6365                 goto err;
6366
6367         ret = intel_ring_begin(ring, 4);
6368         if (ret)
6369                 goto err_unpin;
6370
6371         /* i965+ uses the linear or tiled offsets from the
6372          * Display Registers (which do not change across a page-flip)
6373          * so we need only reprogram the base address.
6374          */
6375         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6376                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6377         intel_ring_emit(ring, fb->pitches[0]);
6378         intel_ring_emit(ring,
6379                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6380                         obj->tiling_mode);
6381
6382         /* XXX Enabling the panel-fitter across page-flip is so far
6383          * untested on non-native modes, so ignore it for now.
6384          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6385          */
6386         pf = 0;
6387         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6388         intel_ring_emit(ring, pf | pipesrc);
6389         intel_ring_advance(ring);
6390         return 0;
6391
6392 err_unpin:
6393         intel_unpin_fb_obj(obj);
6394 err:
6395         return ret;
6396 }
6397
6398 static int intel_gen6_queue_flip(struct drm_device *dev,
6399                                  struct drm_crtc *crtc,
6400                                  struct drm_framebuffer *fb,
6401                                  struct drm_i915_gem_object *obj)
6402 {
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6406         uint32_t pf, pipesrc;
6407         int ret;
6408
6409         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6410         if (ret)
6411                 goto err;
6412
6413         ret = intel_ring_begin(ring, 4);
6414         if (ret)
6415                 goto err_unpin;
6416
6417         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6418                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6419         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6420         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6421
6422         /* Contrary to the suggestions in the documentation,
6423          * "Enable Panel Fitter" does not seem to be required when page
6424          * flipping with a non-native mode, and worse causes a normal
6425          * modeset to fail.
6426          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6427          */
6428         pf = 0;
6429         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6430         intel_ring_emit(ring, pf | pipesrc);
6431         intel_ring_advance(ring);
6432         return 0;
6433
6434 err_unpin:
6435         intel_unpin_fb_obj(obj);
6436 err:
6437         return ret;
6438 }
6439
6440 /*
6441  * On gen7 we currently use the blit ring because (in early silicon at least)
6442  * the render ring doesn't give us interrpts for page flip completion, which
6443  * means clients will hang after the first flip is queued.  Fortunately the
6444  * blit ring generates interrupts properly, so use it instead.
6445  */
6446 static int intel_gen7_queue_flip(struct drm_device *dev,
6447                                  struct drm_crtc *crtc,
6448                                  struct drm_framebuffer *fb,
6449                                  struct drm_i915_gem_object *obj)
6450 {
6451         struct drm_i915_private *dev_priv = dev->dev_private;
6452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6453         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6454         uint32_t plane_bit = 0;
6455         int ret;
6456
6457         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6458         if (ret)
6459                 goto err;
6460
6461         switch(intel_crtc->plane) {
6462         case PLANE_A:
6463                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6464                 break;
6465         case PLANE_B:
6466                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6467                 break;
6468         case PLANE_C:
6469                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6470                 break;
6471         default:
6472                 WARN_ONCE(1, "unknown plane in flip command\n");
6473                 ret = -ENODEV;
6474                 goto err_unpin;
6475         }
6476
6477         ret = intel_ring_begin(ring, 4);
6478         if (ret)
6479                 goto err_unpin;
6480
6481         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6482         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6483         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6484         intel_ring_emit(ring, (MI_NOOP));
6485         intel_ring_advance(ring);
6486         return 0;
6487
6488 err_unpin:
6489         intel_unpin_fb_obj(obj);
6490 err:
6491         return ret;
6492 }
6493
6494 static int intel_default_queue_flip(struct drm_device *dev,
6495                                     struct drm_crtc *crtc,
6496                                     struct drm_framebuffer *fb,
6497                                     struct drm_i915_gem_object *obj)
6498 {
6499         return -ENODEV;
6500 }
6501
6502 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6503                                 struct drm_framebuffer *fb,
6504                                 struct drm_pending_vblank_event *event)
6505 {
6506         struct drm_device *dev = crtc->dev;
6507         struct drm_i915_private *dev_priv = dev->dev_private;
6508         struct intel_framebuffer *intel_fb;
6509         struct drm_i915_gem_object *obj;
6510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6511         struct intel_unpin_work *work;
6512         unsigned long flags;
6513         int ret;
6514
6515         /* Can't change pixel format via MI display flips. */
6516         if (fb->pixel_format != crtc->fb->pixel_format)
6517                 return -EINVAL;
6518
6519         /*
6520          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6521          * Note that pitch changes could also affect these register.
6522          */
6523         if (INTEL_INFO(dev)->gen > 3 &&
6524             (fb->offsets[0] != crtc->fb->offsets[0] ||
6525              fb->pitches[0] != crtc->fb->pitches[0]))
6526                 return -EINVAL;
6527
6528         work = kzalloc(sizeof *work, GFP_KERNEL);
6529         if (work == NULL)
6530                 return -ENOMEM;
6531
6532         work->event = event;
6533         work->dev = crtc->dev;
6534         intel_fb = to_intel_framebuffer(crtc->fb);
6535         work->old_fb_obj = intel_fb->obj;
6536         INIT_WORK(&work->work, intel_unpin_work_fn);
6537
6538         ret = drm_vblank_get(dev, intel_crtc->pipe);
6539         if (ret)
6540                 goto free_work;
6541
6542         /* We borrow the event spin lock for protecting unpin_work */
6543         spin_lock_irqsave(&dev->event_lock, flags);
6544         if (intel_crtc->unpin_work) {
6545                 spin_unlock_irqrestore(&dev->event_lock, flags);
6546                 kfree(work);
6547                 drm_vblank_put(dev, intel_crtc->pipe);
6548
6549                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6550                 return -EBUSY;
6551         }
6552         intel_crtc->unpin_work = work;
6553         spin_unlock_irqrestore(&dev->event_lock, flags);
6554
6555         intel_fb = to_intel_framebuffer(fb);
6556         obj = intel_fb->obj;
6557
6558         ret = i915_mutex_lock_interruptible(dev);
6559         if (ret)
6560                 goto cleanup;
6561
6562         /* Reference the objects for the scheduled work. */
6563         drm_gem_object_reference(&work->old_fb_obj->base);
6564         drm_gem_object_reference(&obj->base);
6565
6566         crtc->fb = fb;
6567
6568         work->pending_flip_obj = obj;
6569
6570         work->enable_stall_check = true;
6571
6572         /* Block clients from rendering to the new back buffer until
6573          * the flip occurs and the object is no longer visible.
6574          */
6575         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6576
6577         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6578         if (ret)
6579                 goto cleanup_pending;
6580
6581         intel_disable_fbc(dev);
6582         intel_mark_fb_busy(obj);
6583         mutex_unlock(&dev->struct_mutex);
6584
6585         trace_i915_flip_request(intel_crtc->plane, obj);
6586
6587         return 0;
6588
6589 cleanup_pending:
6590         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6591         drm_gem_object_unreference(&work->old_fb_obj->base);
6592         drm_gem_object_unreference(&obj->base);
6593         mutex_unlock(&dev->struct_mutex);
6594
6595 cleanup:
6596         spin_lock_irqsave(&dev->event_lock, flags);
6597         intel_crtc->unpin_work = NULL;
6598         spin_unlock_irqrestore(&dev->event_lock, flags);
6599
6600         drm_vblank_put(dev, intel_crtc->pipe);
6601 free_work:
6602         kfree(work);
6603
6604         return ret;
6605 }
6606
6607 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6608         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6609         .load_lut = intel_crtc_load_lut,
6610         .disable = intel_crtc_noop,
6611 };
6612
6613 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6614 {
6615         struct intel_encoder *other_encoder;
6616         struct drm_crtc *crtc = &encoder->new_crtc->base;
6617
6618         if (WARN_ON(!crtc))
6619                 return false;
6620
6621         list_for_each_entry(other_encoder,
6622                             &crtc->dev->mode_config.encoder_list,
6623                             base.head) {
6624
6625                 if (&other_encoder->new_crtc->base != crtc ||
6626                     encoder == other_encoder)
6627                         continue;
6628                 else
6629                         return true;
6630         }
6631
6632         return false;
6633 }
6634
6635 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6636                                   struct drm_crtc *crtc)
6637 {
6638         struct drm_device *dev;
6639         struct drm_crtc *tmp;
6640         int crtc_mask = 1;
6641
6642         WARN(!crtc, "checking null crtc?\n");
6643
6644         dev = crtc->dev;
6645
6646         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6647                 if (tmp == crtc)
6648                         break;
6649                 crtc_mask <<= 1;
6650         }
6651
6652         if (encoder->possible_crtcs & crtc_mask)
6653                 return true;
6654         return false;
6655 }
6656
6657 /**
6658  * intel_modeset_update_staged_output_state
6659  *
6660  * Updates the staged output configuration state, e.g. after we've read out the
6661  * current hw state.
6662  */
6663 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6664 {
6665         struct intel_encoder *encoder;
6666         struct intel_connector *connector;
6667
6668         list_for_each_entry(connector, &dev->mode_config.connector_list,
6669                             base.head) {
6670                 connector->new_encoder =
6671                         to_intel_encoder(connector->base.encoder);
6672         }
6673
6674         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6675                             base.head) {
6676                 encoder->new_crtc =
6677                         to_intel_crtc(encoder->base.crtc);
6678         }
6679 }
6680
6681 /**
6682  * intel_modeset_commit_output_state
6683  *
6684  * This function copies the stage display pipe configuration to the real one.
6685  */
6686 static void intel_modeset_commit_output_state(struct drm_device *dev)
6687 {
6688         struct intel_encoder *encoder;
6689         struct intel_connector *connector;
6690
6691         list_for_each_entry(connector, &dev->mode_config.connector_list,
6692                             base.head) {
6693                 connector->base.encoder = &connector->new_encoder->base;
6694         }
6695
6696         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6697                             base.head) {
6698                 encoder->base.crtc = &encoder->new_crtc->base;
6699         }
6700 }
6701
6702 static struct drm_display_mode *
6703 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6704                             struct drm_display_mode *mode)
6705 {
6706         struct drm_device *dev = crtc->dev;
6707         struct drm_display_mode *adjusted_mode;
6708         struct drm_encoder_helper_funcs *encoder_funcs;
6709         struct intel_encoder *encoder;
6710
6711         adjusted_mode = drm_mode_duplicate(dev, mode);
6712         if (!adjusted_mode)
6713                 return ERR_PTR(-ENOMEM);
6714
6715         /* Pass our mode to the connectors and the CRTC to give them a chance to
6716          * adjust it according to limitations or connector properties, and also
6717          * a chance to reject the mode entirely.
6718          */
6719         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6720                             base.head) {
6721
6722                 if (&encoder->new_crtc->base != crtc)
6723                         continue;
6724                 encoder_funcs = encoder->base.helper_private;
6725                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6726                                                 adjusted_mode))) {
6727                         DRM_DEBUG_KMS("Encoder fixup failed\n");
6728                         goto fail;
6729                 }
6730         }
6731
6732         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6733                 DRM_DEBUG_KMS("CRTC fixup failed\n");
6734                 goto fail;
6735         }
6736         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6737
6738         return adjusted_mode;
6739 fail:
6740         drm_mode_destroy(dev, adjusted_mode);
6741         return ERR_PTR(-EINVAL);
6742 }
6743
6744 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6745  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6746 static void
6747 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6748                              unsigned *prepare_pipes, unsigned *disable_pipes)
6749 {
6750         struct intel_crtc *intel_crtc;
6751         struct drm_device *dev = crtc->dev;
6752         struct intel_encoder *encoder;
6753         struct intel_connector *connector;
6754         struct drm_crtc *tmp_crtc;
6755
6756         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6757
6758         /* Check which crtcs have changed outputs connected to them, these need
6759          * to be part of the prepare_pipes mask. We don't (yet) support global
6760          * modeset across multiple crtcs, so modeset_pipes will only have one
6761          * bit set at most. */
6762         list_for_each_entry(connector, &dev->mode_config.connector_list,
6763                             base.head) {
6764                 if (connector->base.encoder == &connector->new_encoder->base)
6765                         continue;
6766
6767                 if (connector->base.encoder) {
6768                         tmp_crtc = connector->base.encoder->crtc;
6769
6770                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6771                 }
6772
6773                 if (connector->new_encoder)
6774                         *prepare_pipes |=
6775                                 1 << connector->new_encoder->new_crtc->pipe;
6776         }
6777
6778         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6779                             base.head) {
6780                 if (encoder->base.crtc == &encoder->new_crtc->base)
6781                         continue;
6782
6783                 if (encoder->base.crtc) {
6784                         tmp_crtc = encoder->base.crtc;
6785
6786                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6787                 }
6788
6789                 if (encoder->new_crtc)
6790                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6791         }
6792
6793         /* Check for any pipes that will be fully disabled ... */
6794         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6795                             base.head) {
6796                 bool used = false;
6797
6798                 /* Don't try to disable disabled crtcs. */
6799                 if (!intel_crtc->base.enabled)
6800                         continue;
6801
6802                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6803                                     base.head) {
6804                         if (encoder->new_crtc == intel_crtc)
6805                                 used = true;
6806                 }
6807
6808                 if (!used)
6809                         *disable_pipes |= 1 << intel_crtc->pipe;
6810         }
6811
6812
6813         /* set_mode is also used to update properties on life display pipes. */
6814         intel_crtc = to_intel_crtc(crtc);
6815         if (crtc->enabled)
6816                 *prepare_pipes |= 1 << intel_crtc->pipe;
6817
6818         /* We only support modeset on one single crtc, hence we need to do that
6819          * only for the passed in crtc iff we change anything else than just
6820          * disable crtcs.
6821          *
6822          * This is actually not true, to be fully compatible with the old crtc
6823          * helper we automatically disable _any_ output (i.e. doesn't need to be
6824          * connected to the crtc we're modesetting on) if it's disconnected.
6825          * Which is a rather nutty api (since changed the output configuration
6826          * without userspace's explicit request can lead to confusion), but
6827          * alas. Hence we currently need to modeset on all pipes we prepare. */
6828         if (*prepare_pipes)
6829                 *modeset_pipes = *prepare_pipes;
6830
6831         /* ... and mask these out. */
6832         *modeset_pipes &= ~(*disable_pipes);
6833         *prepare_pipes &= ~(*disable_pipes);
6834 }
6835
6836 static bool intel_crtc_in_use(struct drm_crtc *crtc)
6837 {
6838         struct drm_encoder *encoder;
6839         struct drm_device *dev = crtc->dev;
6840
6841         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6842                 if (encoder->crtc == crtc)
6843                         return true;
6844
6845         return false;
6846 }
6847
6848 static void
6849 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6850 {
6851         struct intel_encoder *intel_encoder;
6852         struct intel_crtc *intel_crtc;
6853         struct drm_connector *connector;
6854
6855         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6856                             base.head) {
6857                 if (!intel_encoder->base.crtc)
6858                         continue;
6859
6860                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6861
6862                 if (prepare_pipes & (1 << intel_crtc->pipe))
6863                         intel_encoder->connectors_active = false;
6864         }
6865
6866         intel_modeset_commit_output_state(dev);
6867
6868         /* Update computed state. */
6869         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6870                             base.head) {
6871                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6872         }
6873
6874         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6875                 if (!connector->encoder || !connector->encoder->crtc)
6876                         continue;
6877
6878                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6879
6880                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
6881                         struct drm_property *dpms_property =
6882                                 dev->mode_config.dpms_property;
6883
6884                         connector->dpms = DRM_MODE_DPMS_ON;
6885                         drm_connector_property_set_value(connector,
6886                                                          dpms_property,
6887                                                          DRM_MODE_DPMS_ON);
6888
6889                         intel_encoder = to_intel_encoder(connector->encoder);
6890                         intel_encoder->connectors_active = true;
6891                 }
6892         }
6893
6894 }
6895
6896 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6897         list_for_each_entry((intel_crtc), \
6898                             &(dev)->mode_config.crtc_list, \
6899                             base.head) \
6900                 if (mask & (1 <<(intel_crtc)->pipe)) \
6901
6902 void
6903 intel_modeset_check_state(struct drm_device *dev)
6904 {
6905         struct intel_crtc *crtc;
6906         struct intel_encoder *encoder;
6907         struct intel_connector *connector;
6908
6909         list_for_each_entry(connector, &dev->mode_config.connector_list,
6910                             base.head) {
6911                 /* This also checks the encoder/connector hw state with the
6912                  * ->get_hw_state callbacks. */
6913                 intel_connector_check_state(connector);
6914
6915                 WARN(&connector->new_encoder->base != connector->base.encoder,
6916                      "connector's staged encoder doesn't match current encoder\n");
6917         }
6918
6919         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6920                             base.head) {
6921                 bool enabled = false;
6922                 bool active = false;
6923                 enum pipe pipe, tracked_pipe;
6924
6925                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6926                               encoder->base.base.id,
6927                               drm_get_encoder_name(&encoder->base));
6928
6929                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
6930                      "encoder's stage crtc doesn't match current crtc\n");
6931                 WARN(encoder->connectors_active && !encoder->base.crtc,
6932                      "encoder's active_connectors set, but no crtc\n");
6933
6934                 list_for_each_entry(connector, &dev->mode_config.connector_list,
6935                                     base.head) {
6936                         if (connector->base.encoder != &encoder->base)
6937                                 continue;
6938                         enabled = true;
6939                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
6940                                 active = true;
6941                 }
6942                 WARN(!!encoder->base.crtc != enabled,
6943                      "encoder's enabled state mismatch "
6944                      "(expected %i, found %i)\n",
6945                      !!encoder->base.crtc, enabled);
6946                 WARN(active && !encoder->base.crtc,
6947                      "active encoder with no crtc\n");
6948
6949                 WARN(encoder->connectors_active != active,
6950                      "encoder's computed active state doesn't match tracked active state "
6951                      "(expected %i, found %i)\n", active, encoder->connectors_active);
6952
6953                 active = encoder->get_hw_state(encoder, &pipe);
6954                 WARN(active != encoder->connectors_active,
6955                      "encoder's hw state doesn't match sw tracking "
6956                      "(expected %i, found %i)\n",
6957                      encoder->connectors_active, active);
6958
6959                 if (!encoder->base.crtc)
6960                         continue;
6961
6962                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
6963                 WARN(active && pipe != tracked_pipe,
6964                      "active encoder's pipe doesn't match"
6965                      "(expected %i, found %i)\n",
6966                      tracked_pipe, pipe);
6967
6968         }
6969
6970         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
6971                             base.head) {
6972                 bool enabled = false;
6973                 bool active = false;
6974
6975                 DRM_DEBUG_KMS("[CRTC:%d]\n",
6976                               crtc->base.base.id);
6977
6978                 WARN(crtc->active && !crtc->base.enabled,
6979                      "active crtc, but not enabled in sw tracking\n");
6980
6981                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6982                                     base.head) {
6983                         if (encoder->base.crtc != &crtc->base)
6984                                 continue;
6985                         enabled = true;
6986                         if (encoder->connectors_active)
6987                                 active = true;
6988                 }
6989                 WARN(active != crtc->active,
6990                      "crtc's computed active state doesn't match tracked active state "
6991                      "(expected %i, found %i)\n", active, crtc->active);
6992                 WARN(enabled != crtc->base.enabled,
6993                      "crtc's computed enabled state doesn't match tracked enabled state "
6994                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
6995
6996                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
6997         }
6998 }
6999
7000 bool intel_set_mode(struct drm_crtc *crtc,
7001                     struct drm_display_mode *mode,
7002                     int x, int y, struct drm_framebuffer *fb)
7003 {
7004         struct drm_device *dev = crtc->dev;
7005         drm_i915_private_t *dev_priv = dev->dev_private;
7006         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7007         struct drm_encoder_helper_funcs *encoder_funcs;
7008         struct drm_encoder *encoder;
7009         struct intel_crtc *intel_crtc;
7010         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7011         bool ret = true;
7012
7013         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7014                                      &prepare_pipes, &disable_pipes);
7015
7016         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7017                       modeset_pipes, prepare_pipes, disable_pipes);
7018
7019         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7020                 intel_crtc_disable(&intel_crtc->base);
7021
7022         saved_hwmode = crtc->hwmode;
7023         saved_mode = crtc->mode;
7024
7025         /* Hack: Because we don't (yet) support global modeset on multiple
7026          * crtcs, we don't keep track of the new mode for more than one crtc.
7027          * Hence simply check whether any bit is set in modeset_pipes in all the
7028          * pieces of code that are not yet converted to deal with mutliple crtcs
7029          * changing their mode at the same time. */
7030         adjusted_mode = NULL;
7031         if (modeset_pipes) {
7032                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7033                 if (IS_ERR(adjusted_mode)) {
7034                         return false;
7035                 }
7036         }
7037
7038         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7039                 if (intel_crtc->base.enabled)
7040                         dev_priv->display.crtc_disable(&intel_crtc->base);
7041         }
7042
7043         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7044          * to set it here already despite that we pass it down the callchain.
7045          */
7046         if (modeset_pipes)
7047                 crtc->mode = *mode;
7048
7049         /* Only after disabling all output pipelines that will be changed can we
7050          * update the the output configuration. */
7051         intel_modeset_update_state(dev, prepare_pipes);
7052
7053         /* Set up the DPLL and any encoders state that needs to adjust or depend
7054          * on the DPLL.
7055          */
7056         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7057                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7058                                            mode, adjusted_mode,
7059                                            x, y, fb);
7060                 if (!ret)
7061                     goto done;
7062
7063                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7064
7065                         if (encoder->crtc != &intel_crtc->base)
7066                                 continue;
7067
7068                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7069                                 encoder->base.id, drm_get_encoder_name(encoder),
7070                                 mode->base.id, mode->name);
7071                         encoder_funcs = encoder->helper_private;
7072                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7073                 }
7074         }
7075
7076         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7077         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7078                 dev_priv->display.crtc_enable(&intel_crtc->base);
7079
7080         if (modeset_pipes) {
7081                 /* Store real post-adjustment hardware mode. */
7082                 crtc->hwmode = *adjusted_mode;
7083
7084                 /* Calculate and store various constants which
7085                  * are later needed by vblank and swap-completion
7086                  * timestamping. They are derived from true hwmode.
7087                  */
7088                 drm_calc_timestamping_constants(crtc);
7089         }
7090
7091         /* FIXME: add subpixel order */
7092 done:
7093         drm_mode_destroy(dev, adjusted_mode);
7094         if (!ret && crtc->enabled) {
7095                 crtc->hwmode = saved_hwmode;
7096                 crtc->mode = saved_mode;
7097         } else {
7098                 intel_modeset_check_state(dev);
7099         }
7100
7101         return ret;
7102 }
7103
7104 #undef for_each_intel_crtc_masked
7105
7106 static void intel_set_config_free(struct intel_set_config *config)
7107 {
7108         if (!config)
7109                 return;
7110
7111         kfree(config->save_connector_encoders);
7112         kfree(config->save_encoder_crtcs);
7113         kfree(config);
7114 }
7115
7116 static int intel_set_config_save_state(struct drm_device *dev,
7117                                        struct intel_set_config *config)
7118 {
7119         struct drm_encoder *encoder;
7120         struct drm_connector *connector;
7121         int count;
7122
7123         config->save_encoder_crtcs =
7124                 kcalloc(dev->mode_config.num_encoder,
7125                         sizeof(struct drm_crtc *), GFP_KERNEL);
7126         if (!config->save_encoder_crtcs)
7127                 return -ENOMEM;
7128
7129         config->save_connector_encoders =
7130                 kcalloc(dev->mode_config.num_connector,
7131                         sizeof(struct drm_encoder *), GFP_KERNEL);
7132         if (!config->save_connector_encoders)
7133                 return -ENOMEM;
7134
7135         /* Copy data. Note that driver private data is not affected.
7136          * Should anything bad happen only the expected state is
7137          * restored, not the drivers personal bookkeeping.
7138          */
7139         count = 0;
7140         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7141                 config->save_encoder_crtcs[count++] = encoder->crtc;
7142         }
7143
7144         count = 0;
7145         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7146                 config->save_connector_encoders[count++] = connector->encoder;
7147         }
7148
7149         return 0;
7150 }
7151
7152 static void intel_set_config_restore_state(struct drm_device *dev,
7153                                            struct intel_set_config *config)
7154 {
7155         struct intel_encoder *encoder;
7156         struct intel_connector *connector;
7157         int count;
7158
7159         count = 0;
7160         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7161                 encoder->new_crtc =
7162                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7163         }
7164
7165         count = 0;
7166         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7167                 connector->new_encoder =
7168                         to_intel_encoder(config->save_connector_encoders[count++]);
7169         }
7170 }
7171
7172 static void
7173 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7174                                       struct intel_set_config *config)
7175 {
7176
7177         /* We should be able to check here if the fb has the same properties
7178          * and then just flip_or_move it */
7179         if (set->crtc->fb != set->fb) {
7180                 /* If we have no fb then treat it as a full mode set */
7181                 if (set->crtc->fb == NULL) {
7182                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7183                         config->mode_changed = true;
7184                 } else if (set->fb == NULL) {
7185                         config->mode_changed = true;
7186                 } else if (set->fb->depth != set->crtc->fb->depth) {
7187                         config->mode_changed = true;
7188                 } else if (set->fb->bits_per_pixel !=
7189                            set->crtc->fb->bits_per_pixel) {
7190                         config->mode_changed = true;
7191                 } else
7192                         config->fb_changed = true;
7193         }
7194
7195         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7196                 config->fb_changed = true;
7197
7198         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7199                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7200                 drm_mode_debug_printmodeline(&set->crtc->mode);
7201                 drm_mode_debug_printmodeline(set->mode);
7202                 config->mode_changed = true;
7203         }
7204 }
7205
7206 static int
7207 intel_modeset_stage_output_state(struct drm_device *dev,
7208                                  struct drm_mode_set *set,
7209                                  struct intel_set_config *config)
7210 {
7211         struct drm_crtc *new_crtc;
7212         struct intel_connector *connector;
7213         struct intel_encoder *encoder;
7214         int count, ro;
7215
7216         /* The upper layers ensure that we either disabl a crtc or have a list
7217          * of connectors. For paranoia, double-check this. */
7218         WARN_ON(!set->fb && (set->num_connectors != 0));
7219         WARN_ON(set->fb && (set->num_connectors == 0));
7220
7221         count = 0;
7222         list_for_each_entry(connector, &dev->mode_config.connector_list,
7223                             base.head) {
7224                 /* Otherwise traverse passed in connector list and get encoders
7225                  * for them. */
7226                 for (ro = 0; ro < set->num_connectors; ro++) {
7227                         if (set->connectors[ro] == &connector->base) {
7228                                 connector->new_encoder = connector->encoder;
7229                                 break;
7230                         }
7231                 }
7232
7233                 /* If we disable the crtc, disable all its connectors. Also, if
7234                  * the connector is on the changing crtc but not on the new
7235                  * connector list, disable it. */
7236                 if ((!set->fb || ro == set->num_connectors) &&
7237                     connector->base.encoder &&
7238                     connector->base.encoder->crtc == set->crtc) {
7239                         connector->new_encoder = NULL;
7240
7241                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7242                                 connector->base.base.id,
7243                                 drm_get_connector_name(&connector->base));
7244                 }
7245
7246
7247                 if (&connector->new_encoder->base != connector->base.encoder) {
7248                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7249                         config->mode_changed = true;
7250                 }
7251
7252                 /* Disable all disconnected encoders. */
7253                 if (connector->base.status == connector_status_disconnected)
7254                         connector->new_encoder = NULL;
7255         }
7256         /* connector->new_encoder is now updated for all connectors. */
7257
7258         /* Update crtc of enabled connectors. */
7259         count = 0;
7260         list_for_each_entry(connector, &dev->mode_config.connector_list,
7261                             base.head) {
7262                 if (!connector->new_encoder)
7263                         continue;
7264
7265                 new_crtc = connector->new_encoder->base.crtc;
7266
7267                 for (ro = 0; ro < set->num_connectors; ro++) {
7268                         if (set->connectors[ro] == &connector->base)
7269                                 new_crtc = set->crtc;
7270                 }
7271
7272                 /* Make sure the new CRTC will work with the encoder */
7273                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7274                                            new_crtc)) {
7275                         return -EINVAL;
7276                 }
7277                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7278
7279                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7280                         connector->base.base.id,
7281                         drm_get_connector_name(&connector->base),
7282                         new_crtc->base.id);
7283         }
7284
7285         /* Check for any encoders that needs to be disabled. */
7286         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7287                             base.head) {
7288                 list_for_each_entry(connector,
7289                                     &dev->mode_config.connector_list,
7290                                     base.head) {
7291                         if (connector->new_encoder == encoder) {
7292                                 WARN_ON(!connector->new_encoder->new_crtc);
7293
7294                                 goto next_encoder;
7295                         }
7296                 }
7297                 encoder->new_crtc = NULL;
7298 next_encoder:
7299                 /* Only now check for crtc changes so we don't miss encoders
7300                  * that will be disabled. */
7301                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7302                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7303                         config->mode_changed = true;
7304                 }
7305         }
7306         /* Now we've also updated encoder->new_crtc for all encoders. */
7307
7308         return 0;
7309 }
7310
7311 static int intel_crtc_set_config(struct drm_mode_set *set)
7312 {
7313         struct drm_device *dev;
7314         struct drm_mode_set save_set;
7315         struct intel_set_config *config;
7316         int ret;
7317
7318         BUG_ON(!set);
7319         BUG_ON(!set->crtc);
7320         BUG_ON(!set->crtc->helper_private);
7321
7322         if (!set->mode)
7323                 set->fb = NULL;
7324
7325         /* The fb helper likes to play gross jokes with ->mode_set_config.
7326          * Unfortunately the crtc helper doesn't do much at all for this case,
7327          * so we have to cope with this madness until the fb helper is fixed up. */
7328         if (set->fb && set->num_connectors == 0)
7329                 return 0;
7330
7331         if (set->fb) {
7332                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7333                                 set->crtc->base.id, set->fb->base.id,
7334                                 (int)set->num_connectors, set->x, set->y);
7335         } else {
7336                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7337         }
7338
7339         dev = set->crtc->dev;
7340
7341         ret = -ENOMEM;
7342         config = kzalloc(sizeof(*config), GFP_KERNEL);
7343         if (!config)
7344                 goto out_config;
7345
7346         ret = intel_set_config_save_state(dev, config);
7347         if (ret)
7348                 goto out_config;
7349
7350         save_set.crtc = set->crtc;
7351         save_set.mode = &set->crtc->mode;
7352         save_set.x = set->crtc->x;
7353         save_set.y = set->crtc->y;
7354         save_set.fb = set->crtc->fb;
7355
7356         /* Compute whether we need a full modeset, only an fb base update or no
7357          * change at all. In the future we might also check whether only the
7358          * mode changed, e.g. for LVDS where we only change the panel fitter in
7359          * such cases. */
7360         intel_set_config_compute_mode_changes(set, config);
7361
7362         ret = intel_modeset_stage_output_state(dev, set, config);
7363         if (ret)
7364                 goto fail;
7365
7366         if (config->mode_changed) {
7367                 if (set->mode) {
7368                         DRM_DEBUG_KMS("attempting to set mode from"
7369                                         " userspace\n");
7370                         drm_mode_debug_printmodeline(set->mode);
7371                 }
7372
7373                 if (!intel_set_mode(set->crtc, set->mode,
7374                                     set->x, set->y, set->fb)) {
7375                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7376                                   set->crtc->base.id);
7377                         ret = -EINVAL;
7378                         goto fail;
7379                 }
7380         } else if (config->fb_changed) {
7381                 ret = intel_pipe_set_base(set->crtc,
7382                                           set->x, set->y, set->fb);
7383         }
7384
7385         intel_set_config_free(config);
7386
7387         return 0;
7388
7389 fail:
7390         intel_set_config_restore_state(dev, config);
7391
7392         /* Try to restore the config */
7393         if (config->mode_changed &&
7394             !intel_set_mode(save_set.crtc, save_set.mode,
7395                             save_set.x, save_set.y, save_set.fb))
7396                 DRM_ERROR("failed to restore config after modeset failure\n");
7397
7398 out_config:
7399         intel_set_config_free(config);
7400         return ret;
7401 }
7402
7403 static const struct drm_crtc_funcs intel_crtc_funcs = {
7404         .cursor_set = intel_crtc_cursor_set,
7405         .cursor_move = intel_crtc_cursor_move,
7406         .gamma_set = intel_crtc_gamma_set,
7407         .set_config = intel_crtc_set_config,
7408         .destroy = intel_crtc_destroy,
7409         .page_flip = intel_crtc_page_flip,
7410 };
7411
7412 static void intel_pch_pll_init(struct drm_device *dev)
7413 {
7414         drm_i915_private_t *dev_priv = dev->dev_private;
7415         int i;
7416
7417         if (dev_priv->num_pch_pll == 0) {
7418                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7419                 return;
7420         }
7421
7422         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7423                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7424                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7425                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7426         }
7427 }
7428
7429 static void intel_crtc_init(struct drm_device *dev, int pipe)
7430 {
7431         drm_i915_private_t *dev_priv = dev->dev_private;
7432         struct intel_crtc *intel_crtc;
7433         int i;
7434
7435         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7436         if (intel_crtc == NULL)
7437                 return;
7438
7439         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7440
7441         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7442         for (i = 0; i < 256; i++) {
7443                 intel_crtc->lut_r[i] = i;
7444                 intel_crtc->lut_g[i] = i;
7445                 intel_crtc->lut_b[i] = i;
7446         }
7447
7448         /* Swap pipes & planes for FBC on pre-965 */
7449         intel_crtc->pipe = pipe;
7450         intel_crtc->plane = pipe;
7451         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7452                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7453                 intel_crtc->plane = !pipe;
7454         }
7455
7456         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7457                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7458         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7459         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7460
7461         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7462
7463         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7464 }
7465
7466 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7467                                 struct drm_file *file)
7468 {
7469         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7470         struct drm_mode_object *drmmode_obj;
7471         struct intel_crtc *crtc;
7472
7473         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7474                 return -ENODEV;
7475
7476         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7477                         DRM_MODE_OBJECT_CRTC);
7478
7479         if (!drmmode_obj) {
7480                 DRM_ERROR("no such CRTC id\n");
7481                 return -EINVAL;
7482         }
7483
7484         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7485         pipe_from_crtc_id->pipe = crtc->pipe;
7486
7487         return 0;
7488 }
7489
7490 static int intel_encoder_clones(struct intel_encoder *encoder)
7491 {
7492         struct drm_device *dev = encoder->base.dev;
7493         struct intel_encoder *source_encoder;
7494         int index_mask = 0;
7495         int entry = 0;
7496
7497         list_for_each_entry(source_encoder,
7498                             &dev->mode_config.encoder_list, base.head) {
7499
7500                 if (encoder == source_encoder)
7501                         index_mask |= (1 << entry);
7502
7503                 /* Intel hw has only one MUX where enocoders could be cloned. */
7504                 if (encoder->cloneable && source_encoder->cloneable)
7505                         index_mask |= (1 << entry);
7506
7507                 entry++;
7508         }
7509
7510         return index_mask;
7511 }
7512
7513 static bool has_edp_a(struct drm_device *dev)
7514 {
7515         struct drm_i915_private *dev_priv = dev->dev_private;
7516
7517         if (!IS_MOBILE(dev))
7518                 return false;
7519
7520         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7521                 return false;
7522
7523         if (IS_GEN5(dev) &&
7524             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7525                 return false;
7526
7527         return true;
7528 }
7529
7530 static void intel_setup_outputs(struct drm_device *dev)
7531 {
7532         struct drm_i915_private *dev_priv = dev->dev_private;
7533         struct intel_encoder *encoder;
7534         bool dpd_is_edp = false;
7535         bool has_lvds;
7536
7537         has_lvds = intel_lvds_init(dev);
7538         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7539                 /* disable the panel fitter on everything but LVDS */
7540                 I915_WRITE(PFIT_CONTROL, 0);
7541         }
7542
7543         if (HAS_PCH_SPLIT(dev)) {
7544                 dpd_is_edp = intel_dpd_is_edp(dev);
7545
7546                 if (has_edp_a(dev))
7547                         intel_dp_init(dev, DP_A, PORT_A);
7548
7549                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7550                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7551         }
7552
7553         intel_crt_init(dev);
7554
7555         if (IS_HASWELL(dev)) {
7556                 int found;
7557
7558                 /* Haswell uses DDI functions to detect digital outputs */
7559                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7560                 /* DDI A only supports eDP */
7561                 if (found)
7562                         intel_ddi_init(dev, PORT_A);
7563
7564                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7565                  * register */
7566                 found = I915_READ(SFUSE_STRAP);
7567
7568                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7569                         intel_ddi_init(dev, PORT_B);
7570                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7571                         intel_ddi_init(dev, PORT_C);
7572                 if (found & SFUSE_STRAP_DDID_DETECTED)
7573                         intel_ddi_init(dev, PORT_D);
7574         } else if (HAS_PCH_SPLIT(dev)) {
7575                 int found;
7576
7577                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7578                         /* PCH SDVOB multiplex with HDMIB */
7579                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7580                         if (!found)
7581                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7582                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7583                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7584                 }
7585
7586                 if (I915_READ(HDMIC) & PORT_DETECTED)
7587                         intel_hdmi_init(dev, HDMIC, PORT_C);
7588
7589                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7590                         intel_hdmi_init(dev, HDMID, PORT_D);
7591
7592                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7593                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7594
7595                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7596                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7597         } else if (IS_VALLEYVIEW(dev)) {
7598                 int found;
7599
7600                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7601                         /* SDVOB multiplex with HDMIB */
7602                         found = intel_sdvo_init(dev, SDVOB, true);
7603                         if (!found)
7604                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7605                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7606                                 intel_dp_init(dev, DP_B, PORT_B);
7607                 }
7608
7609                 if (I915_READ(SDVOC) & PORT_DETECTED)
7610                         intel_hdmi_init(dev, SDVOC, PORT_C);
7611
7612                 /* Shares lanes with HDMI on SDVOC */
7613                 if (I915_READ(DP_C) & DP_DETECTED)
7614                         intel_dp_init(dev, DP_C, PORT_C);
7615         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7616                 bool found = false;
7617
7618                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7619                         DRM_DEBUG_KMS("probing SDVOB\n");
7620                         found = intel_sdvo_init(dev, SDVOB, true);
7621                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7622                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7623                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7624                         }
7625
7626                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7627                                 DRM_DEBUG_KMS("probing DP_B\n");
7628                                 intel_dp_init(dev, DP_B, PORT_B);
7629                         }
7630                 }
7631
7632                 /* Before G4X SDVOC doesn't have its own detect register */
7633
7634                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7635                         DRM_DEBUG_KMS("probing SDVOC\n");
7636                         found = intel_sdvo_init(dev, SDVOC, false);
7637                 }
7638
7639                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7640
7641                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7642                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7643                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7644                         }
7645                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7646                                 DRM_DEBUG_KMS("probing DP_C\n");
7647                                 intel_dp_init(dev, DP_C, PORT_C);
7648                         }
7649                 }
7650
7651                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7652                     (I915_READ(DP_D) & DP_DETECTED)) {
7653                         DRM_DEBUG_KMS("probing DP_D\n");
7654                         intel_dp_init(dev, DP_D, PORT_D);
7655                 }
7656         } else if (IS_GEN2(dev))
7657                 intel_dvo_init(dev);
7658
7659         if (SUPPORTS_TV(dev))
7660                 intel_tv_init(dev);
7661
7662         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7663                 encoder->base.possible_crtcs = encoder->crtc_mask;
7664                 encoder->base.possible_clones =
7665                         intel_encoder_clones(encoder);
7666         }
7667
7668         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7669                 ironlake_init_pch_refclk(dev);
7670 }
7671
7672 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7673 {
7674         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7675
7676         drm_framebuffer_cleanup(fb);
7677         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7678
7679         kfree(intel_fb);
7680 }
7681
7682 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7683                                                 struct drm_file *file,
7684                                                 unsigned int *handle)
7685 {
7686         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7687         struct drm_i915_gem_object *obj = intel_fb->obj;
7688
7689         return drm_gem_handle_create(file, &obj->base, handle);
7690 }
7691
7692 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7693         .destroy = intel_user_framebuffer_destroy,
7694         .create_handle = intel_user_framebuffer_create_handle,
7695 };
7696
7697 int intel_framebuffer_init(struct drm_device *dev,
7698                            struct intel_framebuffer *intel_fb,
7699                            struct drm_mode_fb_cmd2 *mode_cmd,
7700                            struct drm_i915_gem_object *obj)
7701 {
7702         int ret;
7703
7704         if (obj->tiling_mode == I915_TILING_Y)
7705                 return -EINVAL;
7706
7707         if (mode_cmd->pitches[0] & 63)
7708                 return -EINVAL;
7709
7710         switch (mode_cmd->pixel_format) {
7711         case DRM_FORMAT_RGB332:
7712         case DRM_FORMAT_RGB565:
7713         case DRM_FORMAT_XRGB8888:
7714         case DRM_FORMAT_XBGR8888:
7715         case DRM_FORMAT_ARGB8888:
7716         case DRM_FORMAT_XRGB2101010:
7717         case DRM_FORMAT_ARGB2101010:
7718                 /* RGB formats are common across chipsets */
7719                 break;
7720         case DRM_FORMAT_YUYV:
7721         case DRM_FORMAT_UYVY:
7722         case DRM_FORMAT_YVYU:
7723         case DRM_FORMAT_VYUY:
7724                 break;
7725         default:
7726                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7727                                 mode_cmd->pixel_format);
7728                 return -EINVAL;
7729         }
7730
7731         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7732         if (ret) {
7733                 DRM_ERROR("framebuffer init failed %d\n", ret);
7734                 return ret;
7735         }
7736
7737         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7738         intel_fb->obj = obj;
7739         return 0;
7740 }
7741
7742 static struct drm_framebuffer *
7743 intel_user_framebuffer_create(struct drm_device *dev,
7744                               struct drm_file *filp,
7745                               struct drm_mode_fb_cmd2 *mode_cmd)
7746 {
7747         struct drm_i915_gem_object *obj;
7748
7749         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7750                                                 mode_cmd->handles[0]));
7751         if (&obj->base == NULL)
7752                 return ERR_PTR(-ENOENT);
7753
7754         return intel_framebuffer_create(dev, mode_cmd, obj);
7755 }
7756
7757 static const struct drm_mode_config_funcs intel_mode_funcs = {
7758         .fb_create = intel_user_framebuffer_create,
7759         .output_poll_changed = intel_fb_output_poll_changed,
7760 };
7761
7762 /* Set up chip specific display functions */
7763 static void intel_init_display(struct drm_device *dev)
7764 {
7765         struct drm_i915_private *dev_priv = dev->dev_private;
7766
7767         /* We always want a DPMS function */
7768         if (HAS_PCH_SPLIT(dev)) {
7769                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7770                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7771                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7772                 dev_priv->display.off = ironlake_crtc_off;
7773                 dev_priv->display.update_plane = ironlake_update_plane;
7774         } else {
7775                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7776                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7777                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7778                 dev_priv->display.off = i9xx_crtc_off;
7779                 dev_priv->display.update_plane = i9xx_update_plane;
7780         }
7781
7782         /* Returns the core display clock speed */
7783         if (IS_VALLEYVIEW(dev))
7784                 dev_priv->display.get_display_clock_speed =
7785                         valleyview_get_display_clock_speed;
7786         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7787                 dev_priv->display.get_display_clock_speed =
7788                         i945_get_display_clock_speed;
7789         else if (IS_I915G(dev))
7790                 dev_priv->display.get_display_clock_speed =
7791                         i915_get_display_clock_speed;
7792         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7793                 dev_priv->display.get_display_clock_speed =
7794                         i9xx_misc_get_display_clock_speed;
7795         else if (IS_I915GM(dev))
7796                 dev_priv->display.get_display_clock_speed =
7797                         i915gm_get_display_clock_speed;
7798         else if (IS_I865G(dev))
7799                 dev_priv->display.get_display_clock_speed =
7800                         i865_get_display_clock_speed;
7801         else if (IS_I85X(dev))
7802                 dev_priv->display.get_display_clock_speed =
7803                         i855_get_display_clock_speed;
7804         else /* 852, 830 */
7805                 dev_priv->display.get_display_clock_speed =
7806                         i830_get_display_clock_speed;
7807
7808         if (HAS_PCH_SPLIT(dev)) {
7809                 if (IS_GEN5(dev)) {
7810                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7811                         dev_priv->display.write_eld = ironlake_write_eld;
7812                 } else if (IS_GEN6(dev)) {
7813                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7814                         dev_priv->display.write_eld = ironlake_write_eld;
7815                 } else if (IS_IVYBRIDGE(dev)) {
7816                         /* FIXME: detect B0+ stepping and use auto training */
7817                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7818                         dev_priv->display.write_eld = ironlake_write_eld;
7819                 } else if (IS_HASWELL(dev)) {
7820                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7821                         dev_priv->display.write_eld = haswell_write_eld;
7822                 } else
7823                         dev_priv->display.update_wm = NULL;
7824         } else if (IS_G4X(dev)) {
7825                 dev_priv->display.write_eld = g4x_write_eld;
7826         }
7827
7828         /* Default just returns -ENODEV to indicate unsupported */
7829         dev_priv->display.queue_flip = intel_default_queue_flip;
7830
7831         switch (INTEL_INFO(dev)->gen) {
7832         case 2:
7833                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7834                 break;
7835
7836         case 3:
7837                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7838                 break;
7839
7840         case 4:
7841         case 5:
7842                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7843                 break;
7844
7845         case 6:
7846                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7847                 break;
7848         case 7:
7849                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7850                 break;
7851         }
7852 }
7853
7854 /*
7855  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7856  * resume, or other times.  This quirk makes sure that's the case for
7857  * affected systems.
7858  */
7859 static void quirk_pipea_force(struct drm_device *dev)
7860 {
7861         struct drm_i915_private *dev_priv = dev->dev_private;
7862
7863         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7864         DRM_INFO("applying pipe a force quirk\n");
7865 }
7866
7867 /*
7868  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7869  */
7870 static void quirk_ssc_force_disable(struct drm_device *dev)
7871 {
7872         struct drm_i915_private *dev_priv = dev->dev_private;
7873         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7874         DRM_INFO("applying lvds SSC disable quirk\n");
7875 }
7876
7877 /*
7878  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7879  * brightness value
7880  */
7881 static void quirk_invert_brightness(struct drm_device *dev)
7882 {
7883         struct drm_i915_private *dev_priv = dev->dev_private;
7884         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7885         DRM_INFO("applying inverted panel brightness quirk\n");
7886 }
7887
7888 struct intel_quirk {
7889         int device;
7890         int subsystem_vendor;
7891         int subsystem_device;
7892         void (*hook)(struct drm_device *dev);
7893 };
7894
7895 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
7896 struct intel_dmi_quirk {
7897         void (*hook)(struct drm_device *dev);
7898         const struct dmi_system_id (*dmi_id_list)[];
7899 };
7900
7901 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
7902 {
7903         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
7904         return 1;
7905 }
7906
7907 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
7908         {
7909                 .dmi_id_list = &(const struct dmi_system_id[]) {
7910                         {
7911                                 .callback = intel_dmi_reverse_brightness,
7912                                 .ident = "NCR Corporation",
7913                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
7914                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
7915                                 },
7916                         },
7917                         { }  /* terminating entry */
7918                 },
7919                 .hook = quirk_invert_brightness,
7920         },
7921 };
7922
7923 static struct intel_quirk intel_quirks[] = {
7924         /* HP Mini needs pipe A force quirk (LP: #322104) */
7925         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7926
7927         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7928         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7929
7930         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7931         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7932
7933         /* 830/845 need to leave pipe A & dpll A up */
7934         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7935         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7936
7937         /* Lenovo U160 cannot use SSC on LVDS */
7938         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7939
7940         /* Sony Vaio Y cannot use SSC on LVDS */
7941         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7942
7943         /* Acer Aspire 5734Z must invert backlight brightness */
7944         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7945 };
7946
7947 static void intel_init_quirks(struct drm_device *dev)
7948 {
7949         struct pci_dev *d = dev->pdev;
7950         int i;
7951
7952         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7953                 struct intel_quirk *q = &intel_quirks[i];
7954
7955                 if (d->device == q->device &&
7956                     (d->subsystem_vendor == q->subsystem_vendor ||
7957                      q->subsystem_vendor == PCI_ANY_ID) &&
7958                     (d->subsystem_device == q->subsystem_device ||
7959                      q->subsystem_device == PCI_ANY_ID))
7960                         q->hook(dev);
7961         }
7962         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
7963                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
7964                         intel_dmi_quirks[i].hook(dev);
7965         }
7966 }
7967
7968 /* Disable the VGA plane that we never use */
7969 static void i915_disable_vga(struct drm_device *dev)
7970 {
7971         struct drm_i915_private *dev_priv = dev->dev_private;
7972         u8 sr1;
7973         u32 vga_reg;
7974
7975         if (HAS_PCH_SPLIT(dev))
7976                 vga_reg = CPU_VGACNTRL;
7977         else
7978                 vga_reg = VGACNTRL;
7979
7980         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7981         outb(SR01, VGA_SR_INDEX);
7982         sr1 = inb(VGA_SR_DATA);
7983         outb(sr1 | 1<<5, VGA_SR_DATA);
7984         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7985         udelay(300);
7986
7987         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7988         POSTING_READ(vga_reg);
7989 }
7990
7991 void intel_modeset_init_hw(struct drm_device *dev)
7992 {
7993         /* We attempt to init the necessary power wells early in the initialization
7994          * time, so the subsystems that expect power to be enabled can work.
7995          */
7996         intel_init_power_wells(dev);
7997
7998         intel_prepare_ddi(dev);
7999
8000         intel_init_clock_gating(dev);
8001
8002         mutex_lock(&dev->struct_mutex);
8003         intel_enable_gt_powersave(dev);
8004         mutex_unlock(&dev->struct_mutex);
8005 }
8006
8007 void intel_modeset_init(struct drm_device *dev)
8008 {
8009         struct drm_i915_private *dev_priv = dev->dev_private;
8010         int i, ret;
8011
8012         drm_mode_config_init(dev);
8013
8014         dev->mode_config.min_width = 0;
8015         dev->mode_config.min_height = 0;
8016
8017         dev->mode_config.preferred_depth = 24;
8018         dev->mode_config.prefer_shadow = 1;
8019
8020         dev->mode_config.funcs = &intel_mode_funcs;
8021
8022         intel_init_quirks(dev);
8023
8024         intel_init_pm(dev);
8025
8026         intel_init_display(dev);
8027
8028         if (IS_GEN2(dev)) {
8029                 dev->mode_config.max_width = 2048;
8030                 dev->mode_config.max_height = 2048;
8031         } else if (IS_GEN3(dev)) {
8032                 dev->mode_config.max_width = 4096;
8033                 dev->mode_config.max_height = 4096;
8034         } else {
8035                 dev->mode_config.max_width = 8192;
8036                 dev->mode_config.max_height = 8192;
8037         }
8038         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8039
8040         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8041                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8042
8043         for (i = 0; i < dev_priv->num_pipe; i++) {
8044                 intel_crtc_init(dev, i);
8045                 ret = intel_plane_init(dev, i);
8046                 if (ret)
8047                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8048         }
8049
8050         intel_pch_pll_init(dev);
8051
8052         /* Just disable it once at startup */
8053         i915_disable_vga(dev);
8054         intel_setup_outputs(dev);
8055 }
8056
8057 static void
8058 intel_connector_break_all_links(struct intel_connector *connector)
8059 {
8060         connector->base.dpms = DRM_MODE_DPMS_OFF;
8061         connector->base.encoder = NULL;
8062         connector->encoder->connectors_active = false;
8063         connector->encoder->base.crtc = NULL;
8064 }
8065
8066 static void intel_enable_pipe_a(struct drm_device *dev)
8067 {
8068         struct intel_connector *connector;
8069         struct drm_connector *crt = NULL;
8070         struct intel_load_detect_pipe load_detect_temp;
8071
8072         /* We can't just switch on the pipe A, we need to set things up with a
8073          * proper mode and output configuration. As a gross hack, enable pipe A
8074          * by enabling the load detect pipe once. */
8075         list_for_each_entry(connector,
8076                             &dev->mode_config.connector_list,
8077                             base.head) {
8078                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8079                         crt = &connector->base;
8080                         break;
8081                 }
8082         }
8083
8084         if (!crt)
8085                 return;
8086
8087         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8088                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8089
8090
8091 }
8092
8093 static bool
8094 intel_check_plane_mapping(struct intel_crtc *crtc)
8095 {
8096         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8097         u32 reg, val;
8098
8099         if (dev_priv->num_pipe == 1)
8100                 return true;
8101
8102         reg = DSPCNTR(!crtc->plane);
8103         val = I915_READ(reg);
8104
8105         if ((val & DISPLAY_PLANE_ENABLE) &&
8106             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8107                 return false;
8108
8109         return true;
8110 }
8111
8112 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8113 {
8114         struct drm_device *dev = crtc->base.dev;
8115         struct drm_i915_private *dev_priv = dev->dev_private;
8116         u32 reg;
8117
8118         /* Clear any frame start delays used for debugging left by the BIOS */
8119         reg = PIPECONF(crtc->pipe);
8120         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8121
8122         /* We need to sanitize the plane -> pipe mapping first because this will
8123          * disable the crtc (and hence change the state) if it is wrong. Note
8124          * that gen4+ has a fixed plane -> pipe mapping.  */
8125         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8126                 struct intel_connector *connector;
8127                 bool plane;
8128
8129                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8130                               crtc->base.base.id);
8131
8132                 /* Pipe has the wrong plane attached and the plane is active.
8133                  * Temporarily change the plane mapping and disable everything
8134                  * ...  */
8135                 plane = crtc->plane;
8136                 crtc->plane = !plane;
8137                 dev_priv->display.crtc_disable(&crtc->base);
8138                 crtc->plane = plane;
8139
8140                 /* ... and break all links. */
8141                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8142                                     base.head) {
8143                         if (connector->encoder->base.crtc != &crtc->base)
8144                                 continue;
8145
8146                         intel_connector_break_all_links(connector);
8147                 }
8148
8149                 WARN_ON(crtc->active);
8150                 crtc->base.enabled = false;
8151         }
8152
8153         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8154             crtc->pipe == PIPE_A && !crtc->active) {
8155                 /* BIOS forgot to enable pipe A, this mostly happens after
8156                  * resume. Force-enable the pipe to fix this, the update_dpms
8157                  * call below we restore the pipe to the right state, but leave
8158                  * the required bits on. */
8159                 intel_enable_pipe_a(dev);
8160         }
8161
8162         /* Adjust the state of the output pipe according to whether we
8163          * have active connectors/encoders. */
8164         intel_crtc_update_dpms(&crtc->base);
8165
8166         if (crtc->active != crtc->base.enabled) {
8167                 struct intel_encoder *encoder;
8168
8169                 /* This can happen either due to bugs in the get_hw_state
8170                  * functions or because the pipe is force-enabled due to the
8171                  * pipe A quirk. */
8172                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8173                               crtc->base.base.id,
8174                               crtc->base.enabled ? "enabled" : "disabled",
8175                               crtc->active ? "enabled" : "disabled");
8176
8177                 crtc->base.enabled = crtc->active;
8178
8179                 /* Because we only establish the connector -> encoder ->
8180                  * crtc links if something is active, this means the
8181                  * crtc is now deactivated. Break the links. connector
8182                  * -> encoder links are only establish when things are
8183                  *  actually up, hence no need to break them. */
8184                 WARN_ON(crtc->active);
8185
8186                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8187                         WARN_ON(encoder->connectors_active);
8188                         encoder->base.crtc = NULL;
8189                 }
8190         }
8191 }
8192
8193 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8194 {
8195         struct intel_connector *connector;
8196         struct drm_device *dev = encoder->base.dev;
8197
8198         /* We need to check both for a crtc link (meaning that the
8199          * encoder is active and trying to read from a pipe) and the
8200          * pipe itself being active. */
8201         bool has_active_crtc = encoder->base.crtc &&
8202                 to_intel_crtc(encoder->base.crtc)->active;
8203
8204         if (encoder->connectors_active && !has_active_crtc) {
8205                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8206                               encoder->base.base.id,
8207                               drm_get_encoder_name(&encoder->base));
8208
8209                 /* Connector is active, but has no active pipe. This is
8210                  * fallout from our resume register restoring. Disable
8211                  * the encoder manually again. */
8212                 if (encoder->base.crtc) {
8213                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8214                                       encoder->base.base.id,
8215                                       drm_get_encoder_name(&encoder->base));
8216                         encoder->disable(encoder);
8217                 }
8218
8219                 /* Inconsistent output/port/pipe state happens presumably due to
8220                  * a bug in one of the get_hw_state functions. Or someplace else
8221                  * in our code, like the register restore mess on resume. Clamp
8222                  * things to off as a safer default. */
8223                 list_for_each_entry(connector,
8224                                     &dev->mode_config.connector_list,
8225                                     base.head) {
8226                         if (connector->encoder != encoder)
8227                                 continue;
8228
8229                         intel_connector_break_all_links(connector);
8230                 }
8231         }
8232         /* Enabled encoders without active connectors will be fixed in
8233          * the crtc fixup. */
8234 }
8235
8236 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8237  * and i915 state tracking structures. */
8238 void intel_modeset_setup_hw_state(struct drm_device *dev)
8239 {
8240         struct drm_i915_private *dev_priv = dev->dev_private;
8241         enum pipe pipe;
8242         u32 tmp;
8243         struct intel_crtc *crtc;
8244         struct intel_encoder *encoder;
8245         struct intel_connector *connector;
8246
8247         for_each_pipe(pipe) {
8248                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8249
8250                 tmp = I915_READ(PIPECONF(pipe));
8251                 if (tmp & PIPECONF_ENABLE)
8252                         crtc->active = true;
8253                 else
8254                         crtc->active = false;
8255
8256                 crtc->base.enabled = crtc->active;
8257
8258                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8259                               crtc->base.base.id,
8260                               crtc->active ? "enabled" : "disabled");
8261         }
8262
8263         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8264                             base.head) {
8265                 pipe = 0;
8266
8267                 if (encoder->get_hw_state(encoder, &pipe)) {
8268                         encoder->base.crtc =
8269                                 dev_priv->pipe_to_crtc_mapping[pipe];
8270                 } else {
8271                         encoder->base.crtc = NULL;
8272                 }
8273
8274                 encoder->connectors_active = false;
8275                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8276                               encoder->base.base.id,
8277                               drm_get_encoder_name(&encoder->base),
8278                               encoder->base.crtc ? "enabled" : "disabled",
8279                               pipe);
8280         }
8281
8282         list_for_each_entry(connector, &dev->mode_config.connector_list,
8283                             base.head) {
8284                 if (connector->get_hw_state(connector)) {
8285                         connector->base.dpms = DRM_MODE_DPMS_ON;
8286                         connector->encoder->connectors_active = true;
8287                         connector->base.encoder = &connector->encoder->base;
8288                 } else {
8289                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8290                         connector->base.encoder = NULL;
8291                 }
8292                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8293                               connector->base.base.id,
8294                               drm_get_connector_name(&connector->base),
8295                               connector->base.encoder ? "enabled" : "disabled");
8296         }
8297
8298         /* HW state is read out, now we need to sanitize this mess. */
8299         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8300                             base.head) {
8301                 intel_sanitize_encoder(encoder);
8302         }
8303
8304         for_each_pipe(pipe) {
8305                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8306                 intel_sanitize_crtc(crtc);
8307         }
8308
8309         intel_modeset_update_staged_output_state(dev);
8310
8311         intel_modeset_check_state(dev);
8312 }
8313
8314 void intel_modeset_gem_init(struct drm_device *dev)
8315 {
8316         intel_modeset_init_hw(dev);
8317
8318         intel_setup_overlay(dev);
8319
8320         intel_modeset_setup_hw_state(dev);
8321 }
8322
8323 void intel_modeset_cleanup(struct drm_device *dev)
8324 {
8325         struct drm_i915_private *dev_priv = dev->dev_private;
8326         struct drm_crtc *crtc;
8327         struct intel_crtc *intel_crtc;
8328
8329         drm_kms_helper_poll_fini(dev);
8330         mutex_lock(&dev->struct_mutex);
8331
8332         intel_unregister_dsm_handler();
8333
8334
8335         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8336                 /* Skip inactive CRTCs */
8337                 if (!crtc->fb)
8338                         continue;
8339
8340                 intel_crtc = to_intel_crtc(crtc);
8341                 intel_increase_pllclock(crtc);
8342         }
8343
8344         intel_disable_fbc(dev);
8345
8346         intel_disable_gt_powersave(dev);
8347
8348         ironlake_teardown_rc6(dev);
8349
8350         if (IS_VALLEYVIEW(dev))
8351                 vlv_init_dpio(dev);
8352
8353         mutex_unlock(&dev->struct_mutex);
8354
8355         /* Disable the irq before mode object teardown, for the irq might
8356          * enqueue unpin/hotplug work. */
8357         drm_irq_uninstall(dev);
8358         cancel_work_sync(&dev_priv->hotplug_work);
8359         cancel_work_sync(&dev_priv->rps.work);
8360
8361         /* flush any delayed tasks or pending work */
8362         flush_scheduled_work();
8363
8364         drm_mode_config_cleanup(dev);
8365 }
8366
8367 /*
8368  * Return which encoder is currently attached for connector.
8369  */
8370 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8371 {
8372         return &intel_attached_encoder(connector)->base;
8373 }
8374
8375 void intel_connector_attach_encoder(struct intel_connector *connector,
8376                                     struct intel_encoder *encoder)
8377 {
8378         connector->encoder = encoder;
8379         drm_mode_connector_attach_encoder(&connector->base,
8380                                           &encoder->base);
8381 }
8382
8383 /*
8384  * set vga decode state - true == enable VGA decode
8385  */
8386 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8387 {
8388         struct drm_i915_private *dev_priv = dev->dev_private;
8389         u16 gmch_ctrl;
8390
8391         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8392         if (state)
8393                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8394         else
8395                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8396         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8397         return 0;
8398 }
8399
8400 #ifdef CONFIG_DEBUG_FS
8401 #include <linux/seq_file.h>
8402
8403 struct intel_display_error_state {
8404         struct intel_cursor_error_state {
8405                 u32 control;
8406                 u32 position;
8407                 u32 base;
8408                 u32 size;
8409         } cursor[I915_MAX_PIPES];
8410
8411         struct intel_pipe_error_state {
8412                 u32 conf;
8413                 u32 source;
8414
8415                 u32 htotal;
8416                 u32 hblank;
8417                 u32 hsync;
8418                 u32 vtotal;
8419                 u32 vblank;
8420                 u32 vsync;
8421         } pipe[I915_MAX_PIPES];
8422
8423         struct intel_plane_error_state {
8424                 u32 control;
8425                 u32 stride;
8426                 u32 size;
8427                 u32 pos;
8428                 u32 addr;
8429                 u32 surface;
8430                 u32 tile_offset;
8431         } plane[I915_MAX_PIPES];
8432 };
8433
8434 struct intel_display_error_state *
8435 intel_display_capture_error_state(struct drm_device *dev)
8436 {
8437         drm_i915_private_t *dev_priv = dev->dev_private;
8438         struct intel_display_error_state *error;
8439         int i;
8440
8441         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8442         if (error == NULL)
8443                 return NULL;
8444
8445         for_each_pipe(i) {
8446                 error->cursor[i].control = I915_READ(CURCNTR(i));
8447                 error->cursor[i].position = I915_READ(CURPOS(i));
8448                 error->cursor[i].base = I915_READ(CURBASE(i));
8449
8450                 error->plane[i].control = I915_READ(DSPCNTR(i));
8451                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8452                 error->plane[i].size = I915_READ(DSPSIZE(i));
8453                 error->plane[i].pos = I915_READ(DSPPOS(i));
8454                 error->plane[i].addr = I915_READ(DSPADDR(i));
8455                 if (INTEL_INFO(dev)->gen >= 4) {
8456                         error->plane[i].surface = I915_READ(DSPSURF(i));
8457                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8458                 }
8459
8460                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8461                 error->pipe[i].source = I915_READ(PIPESRC(i));
8462                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8463                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8464                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8465                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8466                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8467                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8468         }
8469
8470         return error;
8471 }
8472
8473 void
8474 intel_display_print_error_state(struct seq_file *m,
8475                                 struct drm_device *dev,
8476                                 struct intel_display_error_state *error)
8477 {
8478         drm_i915_private_t *dev_priv = dev->dev_private;
8479         int i;
8480
8481         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8482         for_each_pipe(i) {
8483                 seq_printf(m, "Pipe [%d]:\n", i);
8484                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8485                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8486                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8487                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8488                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8489                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8490                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8491                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8492
8493                 seq_printf(m, "Plane [%d]:\n", i);
8494                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8495                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8496                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8497                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8498                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8499                 if (INTEL_INFO(dev)->gen >= 4) {
8500                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8501                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8502                 }
8503
8504                 seq_printf(m, "Cursor [%d]:\n", i);
8505                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8506                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8507                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8508         }
8509 }
8510 #endif