drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 646                                                 int refclk)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         const intel_limit_t *limit;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100000)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100000)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc, refclk);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_device *dev,
 774                                const intel_limit_t *limit,
 775                                const intel_clock_t *clock)
 776 {
 777         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 778                 INTELPllInvalid ("p1 out of range\n");
 779         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 780                 INTELPllInvalid ("p out of range\n");
 781         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 782                 INTELPllInvalid ("m2 out of range\n");
 783         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 784                 INTELPllInvalid ("m1 out of range\n");
 785         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 786                 INTELPllInvalid ("m1 <= m2\n");
 787         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 788                 INTELPllInvalid ("m out of range\n");
 789         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 790                 INTELPllInvalid ("n out of range\n");
 791         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 792                 INTELPllInvalid ("vco out of range\n");
 793         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 794          * connector, etc., rather than just a single range.
 795          */
 796         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 797                 INTELPllInvalid ("dot out of range\n");
 798
 799         return true;
 800 }
 801
 802 static bool
 803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 804                     int target, int refclk, intel_clock_t *best_clock)
 805
 806 {
 807         struct drm_device *dev = crtc->dev;
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         intel_clock_t clock;
 810         int err = target;
 811
 812         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 813             (I915_READ(LVDS)) != 0) {
 814                 /*
 815                  * For LVDS, if the panel is on, just rely on its current
 816                  * settings for dual-channel.  We haven't figured out how to
 817                  * reliably set up different single/dual channel state, if we
 818                  * even can.
 819                  */
 820                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 821                     LVDS_CLKB_POWER_UP)
 822                         clock.p2 = limit->p2.p2_fast;
 823                 else
 824                         clock.p2 = limit->p2.p2_slow;
 825         } else {
 826                 if (target < limit->p2.dot_limit)
 827                         clock.p2 = limit->p2.p2_slow;
 828                 else
 829                         clock.p2 = limit->p2.p2_fast;
 830         }
 831
 832         memset (best_clock, 0, sizeof (*best_clock));
 833
 834         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 835              clock.m1++) {
 836                 for (clock.m2 = limit->m2.min;
 837                      clock.m2 <= limit->m2.max; clock.m2++) {
 838                         /* m1 is always 0 in Pineview */
 839                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 840                                 break;
 841                         for (clock.n = limit->n.min;
 842                              clock.n <= limit->n.max; clock.n++) {
 843                                 for (clock.p1 = limit->p1.min;
 844                                         clock.p1 <= limit->p1.max; clock.p1++) {
 845                                         int this_err;
 846
 847                                         intel_clock(dev, refclk, &clock);
 848                                         if (!intel_PLL_is_valid(dev, limit,
 849                                                                 &clock))
 850                                                 continue;
 851
 852                                         this_err = abs(clock.dot - target);
 853                                         if (this_err < err) {
 854                                                 *best_clock = clock;
 855                                                 err = this_err;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861
 862         return (err != target);
 863 }
 864
 865 static bool
 866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 867                         int target, int refclk, intel_clock_t *best_clock)
 868 {
 869         struct drm_device *dev = crtc->dev;
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         intel_clock_t clock;
 872         int max_n;
 873         bool found;
 874         /* approximately equals target * 0.00585 */
 875         int err_most = (target >> 8) + (target >> 9);
 876         found = false;
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 int lvds_reg;
 880
 881                 if (HAS_PCH_SPLIT(dev))
 882                         lvds_reg = PCH_LVDS;
 883                 else
 884                         lvds_reg = LVDS;
 885                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 886                     LVDS_CLKB_POWER_UP)
 887                         clock.p2 = limit->p2.p2_fast;
 888                 else
 889                         clock.p2 = limit->p2.p2_slow;
 890         } else {
 891                 if (target < limit->p2.dot_limit)
 892                         clock.p2 = limit->p2.p2_slow;
 893                 else
 894                         clock.p2 = limit->p2.p2_fast;
 895         }
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         max_n = limit->n.max;
 899         /* based on hardware requirement, prefer smaller n to precision */
 900         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 901                 /* based on hardware requirement, prefere larger m1,m2 */
 902                 for (clock.m1 = limit->m1.max;
 903                      clock.m1 >= limit->m1.min; clock.m1--) {
 904                         for (clock.m2 = limit->m2.max;
 905                              clock.m2 >= limit->m2.min; clock.m2--) {
 906                                 for (clock.p1 = limit->p1.max;
 907                                      clock.p1 >= limit->p1.min; clock.p1--) {
 908                                         int this_err;
 909
 910                                         intel_clock(dev, refclk, &clock);
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         this_err = abs(clock.dot - target);
 916                                         if (this_err < err_most) {
 917                                                 *best_clock = clock;
 918                                                 err_most = this_err;
 919                                                 max_n = clock.n;
 920                                                 found = true;
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926         return found;
 927 }
 928
 929 static bool
 930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 931                            int target, int refclk, intel_clock_t *best_clock)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         intel_clock_t clock;
 935
 936         if (target < 200000) {
 937                 clock.n = 1;
 938                 clock.p1 = 2;
 939                 clock.p2 = 10;
 940                 clock.m1 = 12;
 941                 clock.m2 = 9;
 942         } else {
 943                 clock.n = 2;
 944                 clock.p1 = 1;
 945                 clock.p2 = 10;
 946                 clock.m1 = 14;
 947                 clock.m2 = 8;
 948         }
 949         intel_clock(dev, refclk, &clock);
 950         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 951         return true;
 952 }
 953
 954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 955 static bool
 956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 957                       int target, int refclk, intel_clock_t *best_clock)
 958 {
 959         intel_clock_t clock;
 960         if (target < 200000) {
 961                 clock.p1 = 2;
 962                 clock.p2 = 10;
 963                 clock.n = 2;
 964                 clock.m1 = 23;
 965                 clock.m2 = 8;
 966         } else {
 967                 clock.p1 = 1;
 968                 clock.p2 = 10;
 969                 clock.n = 1;
 970                 clock.m1 = 14;
 971                 clock.m2 = 2;
 972         }
 973         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 974         clock.p = (clock.p1 * clock.p2);
 975         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 976         clock.vco = 0;
 977         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 978         return true;
 979 }
 980
 981 /**
 982  * intel_wait_for_vblank - wait for vblank on a given pipe
 983  * @dev: drm device
 984  * @pipe: pipe to wait for
 985  *
 986  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 987  * mode setting code.
 988  */
 989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         int pipestat_reg = PIPESTAT(pipe);
 993
 994         /* Clear existing vblank status. Note this will clear any other
 995          * sticky status fields as well.
 996          *
 997          * This races with i915_driver_irq_handler() with the result
 998          * that either function could miss a vblank event.  Here it is not
 999          * fatal, as we will either wait upon the next vblank interrupt or
1000          * timeout.  Generally speaking intel_wait_for_vblank() is only
1001          * called during modeset at which time the GPU should be idle and
1002          * should *not* be performing page flips and thus not waiting on
1003          * vblanks...
1004          * Currently, the result of us stealing a vblank from the irq
1005          * handler is that a single frame will be skipped during swapbuffers.
1006          */
1007         I915_WRITE(pipestat_reg,
1008                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010         /* Wait for vblank interrupt bit to set */
1011         if (wait_for(I915_READ(pipestat_reg) &
1012                      PIPE_VBLANK_INTERRUPT_STATUS,
1013                      50))
1014                 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018  * intel_wait_for_pipe_off - wait for pipe to turn off
1019  * @dev: drm device
1020  * @pipe: pipe to wait for
1021  *
1022  * After disabling a pipe, we can't wait for vblank in the usual way,
1023  * spinning on the vblank interrupt status bit, since we won't actually
1024  * see an interrupt when the pipe is disabled.
1025  *
1026  * On Gen4 and above:
1027  *   wait for the pipe register state bit to turn off
1028  *
1029  * Otherwise:
1030  *   wait for the display line value to settle (it usually
1031  *   ends up stopping at the start of the next frame).
1032  *
1033  */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         if (INTEL_INFO(dev)->gen >= 4) {
1039                 int reg = PIPECONF(pipe);
1040
1041                 /* Wait for the Pipe State to go off */
1042                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043                              100))
1044                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045         } else {
1046                 u32 last_line;
1047                 int reg = PIPEDSL(pipe);
1048                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050                 /* Wait for the display line to settle */
1051                 do {
1052                         last_line = I915_READ(reg) & DSL_LINEMASK;
1053                         mdelay(5);
1054                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055                          time_after(timeout, jiffies));
1056                 if (time_after(jiffies, timeout))
1057                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058         }
1059 }
1060
1061 static const char *state_string(bool enabled)
1062 {
1063         return enabled ? "on" : "off";
1064 }
1065
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private *dev_priv,
1068                        enum pipe pipe, bool state)
1069 {
1070         int reg;
1071         u32 val;
1072         bool cur_state;
1073
1074         reg = DPLL(pipe);
1075         val = I915_READ(reg);
1076         cur_state = !!(val & DPLL_VCO_ENABLE);
1077         WARN(cur_state != state,
1078              "PLL state assertion failure (expected %s, current %s)\n",
1079              state_string(state), state_string(cur_state));
1080 }
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
1084 /* For ILK+ */
1085 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086                            enum pipe pipe, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = PCH_DPLL(pipe);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state assertion failure (expected %s, current %s)\n",
1097              state_string(state), state_string(cur_state));
1098 }
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103                           enum pipe pipe, bool state)
1104 {
1105         int reg;
1106         u32 val;
1107         bool cur_state;
1108
1109         reg = FDI_TX_CTL(pipe);
1110         val = I915_READ(reg);
1111         cur_state = !!(val & FDI_TX_ENABLE);
1112         WARN(cur_state != state,
1113              "FDI TX state assertion failure (expected %s, current %s)\n",
1114              state_string(state), state_string(cur_state));
1115 }
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125
1126         reg = FDI_RX_CTL(pipe);
1127         val = I915_READ(reg);
1128         cur_state = !!(val & FDI_RX_ENABLE);
1129         WARN(cur_state != state,
1130              "FDI RX state assertion failure (expected %s, current %s)\n",
1131              state_string(state), state_string(cur_state));
1132 }
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137                                       enum pipe pipe)
1138 {
1139         int reg;
1140         u32 val;
1141
1142         /* ILK FDI PLL is always enabled */
1143         if (dev_priv->info->gen == 5)
1144                 return;
1145
1146         reg = FDI_TX_CTL(pipe);
1147         val = I915_READ(reg);
1148         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149 }
1150
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152                                       enum pipe pipe)
1153 {
1154         int reg;
1155         u32 val;
1156
1157         reg = FDI_RX_CTL(pipe);
1158         val = I915_READ(reg);
1159         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160 }
1161
1162 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163                                   enum pipe pipe)
1164 {
1165         int pp_reg, lvds_reg;
1166         u32 val;
1167         enum pipe panel_pipe = PIPE_A;
1168         bool locked = locked;
1169
1170         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171                 pp_reg = PCH_PP_CONTROL;
1172                 lvds_reg = PCH_LVDS;
1173         } else {
1174                 pp_reg = PP_CONTROL;
1175                 lvds_reg = LVDS;
1176         }
1177
1178         val = I915_READ(pp_reg);
1179         if (!(val & PANEL_POWER_ON) ||
1180             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181                 locked = false;
1182
1183         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184                 panel_pipe = PIPE_B;
1185
1186         WARN(panel_pipe == pipe && locked,
1187              "panel assertion failure, pipe %c regs locked\n",
1188              pipe_name(pipe));
1189 }
1190
1191 static void assert_pipe(struct drm_i915_private *dev_priv,
1192                         enum pipe pipe, bool state)
1193 {
1194         int reg;
1195         u32 val;
1196         bool cur_state;
1197
1198         reg = PIPECONF(pipe);
1199         val = I915_READ(reg);
1200         cur_state = !!(val & PIPECONF_ENABLE);
1201         WARN(cur_state != state,
1202              "pipe %c assertion failure (expected %s, current %s)\n",
1203              pipe_name(pipe), state_string(state), state_string(cur_state));
1204 }
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1207
1208 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209                                  enum plane plane)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         reg = DSPCNTR(plane);
1215         val = I915_READ(reg);
1216         WARN(!(val & DISPLAY_PLANE_ENABLE),
1217              "plane %c assertion failure, should be active but is disabled\n",
1218              plane_name(plane));
1219 }
1220
1221 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222                                    enum pipe pipe)
1223 {
1224         int reg, i;
1225         u32 val;
1226         int cur_pipe;
1227
1228         /* Planes are fixed to pipes on ILK+ */
1229         if (HAS_PCH_SPLIT(dev_priv->dev))
1230                 return;
1231
1232         /* Need to check both planes against the pipe */
1233         for (i = 0; i < 2; i++) {
1234                 reg = DSPCNTR(i);
1235                 val = I915_READ(reg);
1236                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237                         DISPPLANE_SEL_PIPE_SHIFT;
1238                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1239                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240                      plane_name(i), pipe_name(pipe));
1241         }
1242 }
1243
1244 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1245 {
1246         u32 val;
1247         bool enabled;
1248
1249         val = I915_READ(PCH_DREF_CONTROL);
1250         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1251                             DREF_SUPERSPREAD_SOURCE_MASK));
1252         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1253 }
1254
1255 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1256                                        enum pipe pipe)
1257 {
1258         int reg;
1259         u32 val;
1260         bool enabled;
1261
1262         reg = TRANSCONF(pipe);
1263         val = I915_READ(reg);
1264         enabled = !!(val & TRANS_ENABLE);
1265         WARN(enabled,
1266              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1267              pipe_name(pipe));
1268 }
1269
1270 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271                                    enum pipe pipe, int reg)
1272 {
1273         u32 val = I915_READ(reg);
1274         WARN(DP_PIPE_ENABLED(val, pipe),
1275              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276              reg, pipe_name(pipe));
1277 }
1278
1279 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1280                                      enum pipe pipe, int reg)
1281 {
1282         u32 val = I915_READ(reg);
1283         WARN(HDMI_PIPE_ENABLED(val, pipe),
1284              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1285              reg, pipe_name(pipe));
1286 }
1287
1288 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1289                                       enum pipe pipe)
1290 {
1291         int reg;
1292         u32 val;
1293
1294         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1295         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1296         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1297
1298         reg = PCH_ADPA;
1299         val = I915_READ(reg);
1300         WARN(ADPA_PIPE_ENABLED(val, pipe),
1301              "PCH VGA enabled on transcoder %c, should be disabled\n",
1302              pipe_name(pipe));
1303
1304         reg = PCH_LVDS;
1305         val = I915_READ(reg);
1306         WARN(LVDS_PIPE_ENABLED(val, pipe),
1307              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1308              pipe_name(pipe));
1309
1310         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1311         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1312         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1313 }
1314
1315 /**
1316  * intel_enable_pll - enable a PLL
1317  * @dev_priv: i915 private structure
1318  * @pipe: pipe PLL to enable
1319  *
1320  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1321  * make sure the PLL reg is writable first though, since the panel write
1322  * protect mechanism may be enabled.
1323  *
1324  * Note!  This is for pre-ILK only.
1325  */
1326 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1327 {
1328         int reg;
1329         u32 val;
1330
1331         /* No really, not for ILK+ */
1332         BUG_ON(dev_priv->info->gen >= 5);
1333
1334         /* PLL is protected by panel, make sure we can write it */
1335         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336                 assert_panel_unlocked(dev_priv, pipe);
1337
1338         reg = DPLL(pipe);
1339         val = I915_READ(reg);
1340         val |= DPLL_VCO_ENABLE;
1341
1342         /* We do this three times for luck */
1343         I915_WRITE(reg, val);
1344         POSTING_READ(reg);
1345         udelay(150); /* wait for warmup */
1346         I915_WRITE(reg, val);
1347         POSTING_READ(reg);
1348         udelay(150); /* wait for warmup */
1349         I915_WRITE(reg, val);
1350         POSTING_READ(reg);
1351         udelay(150); /* wait for warmup */
1352 }
1353
1354 /**
1355  * intel_disable_pll - disable a PLL
1356  * @dev_priv: i915 private structure
1357  * @pipe: pipe PLL to disable
1358  *
1359  * Disable the PLL for @pipe, making sure the pipe is off first.
1360  *
1361  * Note!  This is for pre-ILK only.
1362  */
1363 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1364 {
1365         int reg;
1366         u32 val;
1367
1368         /* Don't disable pipe A or pipe A PLLs if needed */
1369         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1370                 return;
1371
1372         /* Make sure the pipe isn't still relying on us */
1373         assert_pipe_disabled(dev_priv, pipe);
1374
1375         reg = DPLL(pipe);
1376         val = I915_READ(reg);
1377         val &= ~DPLL_VCO_ENABLE;
1378         I915_WRITE(reg, val);
1379         POSTING_READ(reg);
1380 }
1381
1382 /**
1383  * intel_enable_pch_pll - enable PCH PLL
1384  * @dev_priv: i915 private structure
1385  * @pipe: pipe PLL to enable
1386  *
1387  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1388  * drives the transcoder clock.
1389  */
1390 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1391                                  enum pipe pipe)
1392 {
1393         int reg;
1394         u32 val;
1395
1396         /* PCH only available on ILK+ */
1397         BUG_ON(dev_priv->info->gen < 5);
1398
1399         /* PCH refclock must be enabled first */
1400         assert_pch_refclk_enabled(dev_priv);
1401
1402         reg = PCH_DPLL(pipe);
1403         val = I915_READ(reg);
1404         val |= DPLL_VCO_ENABLE;
1405         I915_WRITE(reg, val);
1406         POSTING_READ(reg);
1407         udelay(200);
1408 }
1409
1410 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1411                                   enum pipe pipe)
1412 {
1413         int reg;
1414         u32 val;
1415
1416         /* PCH only available on ILK+ */
1417         BUG_ON(dev_priv->info->gen < 5);
1418
1419         /* Make sure transcoder isn't still depending on us */
1420         assert_transcoder_disabled(dev_priv, pipe);
1421
1422         reg = PCH_DPLL(pipe);
1423         val = I915_READ(reg);
1424         val &= ~DPLL_VCO_ENABLE;
1425         I915_WRITE(reg, val);
1426         POSTING_READ(reg);
1427         udelay(200);
1428 }
1429
1430 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1431                                     enum pipe pipe)
1432 {
1433         int reg;
1434         u32 val;
1435
1436         /* PCH only available on ILK+ */
1437         BUG_ON(dev_priv->info->gen < 5);
1438
1439         /* Make sure PCH DPLL is enabled */
1440         assert_pch_pll_enabled(dev_priv, pipe);
1441
1442         /* FDI must be feeding us bits for PCH ports */
1443         assert_fdi_tx_enabled(dev_priv, pipe);
1444         assert_fdi_rx_enabled(dev_priv, pipe);
1445
1446         reg = TRANSCONF(pipe);
1447         val = I915_READ(reg);
1448         /*
1449          * make the BPC in transcoder be consistent with
1450          * that in pipeconf reg.
1451          */
1452         val &= ~PIPE_BPC_MASK;
1453         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1454         I915_WRITE(reg, val | TRANS_ENABLE);
1455         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1456                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1457 }
1458
1459 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1460                                      enum pipe pipe)
1461 {
1462         int reg;
1463         u32 val;
1464
1465         /* FDI relies on the transcoder */
1466         assert_fdi_tx_disabled(dev_priv, pipe);
1467         assert_fdi_rx_disabled(dev_priv, pipe);
1468
1469         /* Ports must be off as well */
1470         assert_pch_ports_disabled(dev_priv, pipe);
1471
1472         reg = TRANSCONF(pipe);
1473         val = I915_READ(reg);
1474         val &= ~TRANS_ENABLE;
1475         I915_WRITE(reg, val);
1476         /* wait for PCH transcoder off, transcoder state */
1477         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1478                 DRM_ERROR("failed to disable transcoder\n");
1479 }
1480
1481 /**
1482  * intel_enable_pipe - enable a pipe, asserting requirements
1483  * @dev_priv: i915 private structure
1484  * @pipe: pipe to enable
1485  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1486  *
1487  * Enable @pipe, making sure that various hardware specific requirements
1488  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1489  *
1490  * @pipe should be %PIPE_A or %PIPE_B.
1491  *
1492  * Will wait until the pipe is actually running (i.e. first vblank) before
1493  * returning.
1494  */
1495 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1496                               bool pch_port)
1497 {
1498         int reg;
1499         u32 val;
1500
1501         /*
1502          * A pipe without a PLL won't actually be able to drive bits from
1503          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1504          * need the check.
1505          */
1506         if (!HAS_PCH_SPLIT(dev_priv->dev))
1507                 assert_pll_enabled(dev_priv, pipe);
1508         else {
1509                 if (pch_port) {
1510                         /* if driving the PCH, we need FDI enabled */
1511                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1512                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1513                 }
1514                 /* FIXME: assert CPU port conditions for SNB+ */
1515         }
1516
1517         reg = PIPECONF(pipe);
1518         val = I915_READ(reg);
1519         if (val & PIPECONF_ENABLE)
1520                 return;
1521
1522         I915_WRITE(reg, val | PIPECONF_ENABLE);
1523         intel_wait_for_vblank(dev_priv->dev, pipe);
1524 }
1525
1526 /**
1527  * intel_disable_pipe - disable a pipe, asserting requirements
1528  * @dev_priv: i915 private structure
1529  * @pipe: pipe to disable
1530  *
1531  * Disable @pipe, making sure that various hardware specific requirements
1532  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1533  *
1534  * @pipe should be %PIPE_A or %PIPE_B.
1535  *
1536  * Will wait until the pipe has shut down before returning.
1537  */
1538 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1539                                enum pipe pipe)
1540 {
1541         int reg;
1542         u32 val;
1543
1544         /*
1545          * Make sure planes won't keep trying to pump pixels to us,
1546          * or we might hang the display.
1547          */
1548         assert_planes_disabled(dev_priv, pipe);
1549
1550         /* Don't disable pipe A or pipe A PLLs if needed */
1551         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1552                 return;
1553
1554         reg = PIPECONF(pipe);
1555         val = I915_READ(reg);
1556         if ((val & PIPECONF_ENABLE) == 0)
1557                 return;
1558
1559         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1560         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1561 }
1562
1563 /**
1564  * intel_enable_plane - enable a display plane on a given pipe
1565  * @dev_priv: i915 private structure
1566  * @plane: plane to enable
1567  * @pipe: pipe being fed
1568  *
1569  * Enable @plane on @pipe, making sure that @pipe is running first.
1570  */
1571 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1572                                enum plane plane, enum pipe pipe)
1573 {
1574         int reg;
1575         u32 val;
1576
1577         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1578         assert_pipe_enabled(dev_priv, pipe);
1579
1580         reg = DSPCNTR(plane);
1581         val = I915_READ(reg);
1582         if (val & DISPLAY_PLANE_ENABLE)
1583                 return;
1584
1585         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1586         intel_wait_for_vblank(dev_priv->dev, pipe);
1587 }
1588
1589 /*
1590  * Plane regs are double buffered, going from enabled->disabled needs a
1591  * trigger in order to latch.  The display address reg provides this.
1592  */
1593 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1594                                       enum plane plane)
1595 {
1596         u32 reg = DSPADDR(plane);
1597         I915_WRITE(reg, I915_READ(reg));
1598 }
1599
1600 /**
1601  * intel_disable_plane - disable a display plane
1602  * @dev_priv: i915 private structure
1603  * @plane: plane to disable
1604  * @pipe: pipe consuming the data
1605  *
1606  * Disable @plane; should be an independent operation.
1607  */
1608 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1609                                 enum plane plane, enum pipe pipe)
1610 {
1611         int reg;
1612         u32 val;
1613
1614         reg = DSPCNTR(plane);
1615         val = I915_READ(reg);
1616         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1617                 return;
1618
1619         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1620         intel_flush_display_plane(dev_priv, plane);
1621         intel_wait_for_vblank(dev_priv->dev, pipe);
1622 }
1623
1624 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1625                            enum pipe pipe, int reg)
1626 {
1627         u32 val = I915_READ(reg);
1628         if (DP_PIPE_ENABLED(val, pipe))
1629                 I915_WRITE(reg, val & ~DP_PORT_EN);
1630 }
1631
1632 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1633                              enum pipe pipe, int reg)
1634 {
1635         u32 val = I915_READ(reg);
1636         if (HDMI_PIPE_ENABLED(val, pipe))
1637                 I915_WRITE(reg, val & ~PORT_ENABLE);
1638 }
1639
1640 /* Disable any ports connected to this transcoder */
1641 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1642                                     enum pipe pipe)
1643 {
1644         u32 reg, val;
1645
1646         val = I915_READ(PCH_PP_CONTROL);
1647         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1648
1649         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1650         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1651         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1652
1653         reg = PCH_ADPA;
1654         val = I915_READ(reg);
1655         if (ADPA_PIPE_ENABLED(val, pipe))
1656                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1657
1658         reg = PCH_LVDS;
1659         val = I915_READ(reg);
1660         if (LVDS_PIPE_ENABLED(val, pipe)) {
1661                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1662                 POSTING_READ(reg);
1663                 udelay(100);
1664         }
1665
1666         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1667         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1668         disable_pch_hdmi(dev_priv, pipe, HDMID);
1669 }
1670
1671 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1672 {
1673         struct drm_device *dev = crtc->dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         struct drm_framebuffer *fb = crtc->fb;
1676         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1677         struct drm_i915_gem_object *obj = intel_fb->obj;
1678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1679         int plane, i;
1680         u32 fbc_ctl, fbc_ctl2;
1681
1682         if (fb->pitch == dev_priv->cfb_pitch &&
1683             obj->fence_reg == dev_priv->cfb_fence &&
1684             intel_crtc->plane == dev_priv->cfb_plane &&
1685             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1686                 return;
1687
1688         i8xx_disable_fbc(dev);
1689
1690         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1691
1692         if (fb->pitch < dev_priv->cfb_pitch)
1693                 dev_priv->cfb_pitch = fb->pitch;
1694
1695         /* FBC_CTL wants 64B units */
1696         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1697         dev_priv->cfb_fence = obj->fence_reg;
1698         dev_priv->cfb_plane = intel_crtc->plane;
1699         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1700
1701         /* Clear old tags */
1702         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1703                 I915_WRITE(FBC_TAG + (i * 4), 0);
1704
1705         /* Set it up... */
1706         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1707         if (obj->tiling_mode != I915_TILING_NONE)
1708                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1709         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1710         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1711
1712         /* enable it... */
1713         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1714         if (IS_I945GM(dev))
1715                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1716         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1717         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1718         if (obj->tiling_mode != I915_TILING_NONE)
1719                 fbc_ctl |= dev_priv->cfb_fence;
1720         I915_WRITE(FBC_CONTROL, fbc_ctl);
1721
1722         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1723                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1724 }
1725
1726 void i8xx_disable_fbc(struct drm_device *dev)
1727 {
1728         struct drm_i915_private *dev_priv = dev->dev_private;
1729         u32 fbc_ctl;
1730
1731         /* Disable compression */
1732         fbc_ctl = I915_READ(FBC_CONTROL);
1733         if ((fbc_ctl & FBC_CTL_EN) == 0)
1734                 return;
1735
1736         fbc_ctl &= ~FBC_CTL_EN;
1737         I915_WRITE(FBC_CONTROL, fbc_ctl);
1738
1739         /* Wait for compressing bit to clear */
1740         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1741                 DRM_DEBUG_KMS("FBC idle timed out\n");
1742                 return;
1743         }
1744
1745         DRM_DEBUG_KMS("disabled FBC\n");
1746 }
1747
1748 static bool i8xx_fbc_enabled(struct drm_device *dev)
1749 {
1750         struct drm_i915_private *dev_priv = dev->dev_private;
1751
1752         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1753 }
1754
1755 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1756 {
1757         struct drm_device *dev = crtc->dev;
1758         struct drm_i915_private *dev_priv = dev->dev_private;
1759         struct drm_framebuffer *fb = crtc->fb;
1760         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1761         struct drm_i915_gem_object *obj = intel_fb->obj;
1762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1763         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1764         unsigned long stall_watermark = 200;
1765         u32 dpfc_ctl;
1766
1767         dpfc_ctl = I915_READ(DPFC_CONTROL);
1768         if (dpfc_ctl & DPFC_CTL_EN) {
1769                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1770                     dev_priv->cfb_fence == obj->fence_reg &&
1771                     dev_priv->cfb_plane == intel_crtc->plane &&
1772                     dev_priv->cfb_y == crtc->y)
1773                         return;
1774
1775                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1776                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1777         }
1778
1779         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1780         dev_priv->cfb_fence = obj->fence_reg;
1781         dev_priv->cfb_plane = intel_crtc->plane;
1782         dev_priv->cfb_y = crtc->y;
1783
1784         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1785         if (obj->tiling_mode != I915_TILING_NONE) {
1786                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1787                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1788         } else {
1789                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1790         }
1791
1792         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1793                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1794                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1795         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1796
1797         /* enable it... */
1798         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1799
1800         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1801 }
1802
1803 void g4x_disable_fbc(struct drm_device *dev)
1804 {
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806         u32 dpfc_ctl;
1807
1808         /* Disable compression */
1809         dpfc_ctl = I915_READ(DPFC_CONTROL);
1810         if (dpfc_ctl & DPFC_CTL_EN) {
1811                 dpfc_ctl &= ~DPFC_CTL_EN;
1812                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1813
1814                 DRM_DEBUG_KMS("disabled FBC\n");
1815         }
1816 }
1817
1818 static bool g4x_fbc_enabled(struct drm_device *dev)
1819 {
1820         struct drm_i915_private *dev_priv = dev->dev_private;
1821
1822         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1823 }
1824
1825 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1826 {
1827         struct drm_i915_private *dev_priv = dev->dev_private;
1828         u32 blt_ecoskpd;
1829
1830         /* Make sure blitter notifies FBC of writes */
1831         __gen6_gt_force_wake_get(dev_priv);
1832         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1833         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1834                 GEN6_BLITTER_LOCK_SHIFT;
1835         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1836         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1837         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1838         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1839                          GEN6_BLITTER_LOCK_SHIFT);
1840         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1841         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1842         __gen6_gt_force_wake_put(dev_priv);
1843 }
1844
1845 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1846 {
1847         struct drm_device *dev = crtc->dev;
1848         struct drm_i915_private *dev_priv = dev->dev_private;
1849         struct drm_framebuffer *fb = crtc->fb;
1850         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1851         struct drm_i915_gem_object *obj = intel_fb->obj;
1852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1854         unsigned long stall_watermark = 200;
1855         u32 dpfc_ctl;
1856
1857         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1858         if (dpfc_ctl & DPFC_CTL_EN) {
1859                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1860                     dev_priv->cfb_fence == obj->fence_reg &&
1861                     dev_priv->cfb_plane == intel_crtc->plane &&
1862                     dev_priv->cfb_offset == obj->gtt_offset &&
1863                     dev_priv->cfb_y == crtc->y)
1864                         return;
1865
1866                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1867                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1868         }
1869
1870         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1871         dev_priv->cfb_fence = obj->fence_reg;
1872         dev_priv->cfb_plane = intel_crtc->plane;
1873         dev_priv->cfb_offset = obj->gtt_offset;
1874         dev_priv->cfb_y = crtc->y;
1875
1876         dpfc_ctl &= DPFC_RESERVED;
1877         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1878         if (obj->tiling_mode != I915_TILING_NONE) {
1879                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1880                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1881         } else {
1882                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1883         }
1884
1885         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1886                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1887                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1888         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1889         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1890         /* enable it... */
1891         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1892
1893         if (IS_GEN6(dev)) {
1894                 I915_WRITE(SNB_DPFC_CTL_SA,
1895                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1896                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1897                 sandybridge_blit_fbc_update(dev);
1898         }
1899
1900         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1901 }
1902
1903 void ironlake_disable_fbc(struct drm_device *dev)
1904 {
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         u32 dpfc_ctl;
1907
1908         /* Disable compression */
1909         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1910         if (dpfc_ctl & DPFC_CTL_EN) {
1911                 dpfc_ctl &= ~DPFC_CTL_EN;
1912                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1913
1914                 DRM_DEBUG_KMS("disabled FBC\n");
1915         }
1916 }
1917
1918 static bool ironlake_fbc_enabled(struct drm_device *dev)
1919 {
1920         struct drm_i915_private *dev_priv = dev->dev_private;
1921
1922         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1923 }
1924
1925 bool intel_fbc_enabled(struct drm_device *dev)
1926 {
1927         struct drm_i915_private *dev_priv = dev->dev_private;
1928
1929         if (!dev_priv->display.fbc_enabled)
1930                 return false;
1931
1932         return dev_priv->display.fbc_enabled(dev);
1933 }
1934
1935 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1936 {
1937         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1938
1939         if (!dev_priv->display.enable_fbc)
1940                 return;
1941
1942         dev_priv->display.enable_fbc(crtc, interval);
1943 }
1944
1945 void intel_disable_fbc(struct drm_device *dev)
1946 {
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948
1949         if (!dev_priv->display.disable_fbc)
1950                 return;
1951
1952         dev_priv->display.disable_fbc(dev);
1953 }
1954
1955 /**
1956  * intel_update_fbc - enable/disable FBC as needed
1957  * @dev: the drm_device
1958  *
1959  * Set up the framebuffer compression hardware at mode set time.  We
1960  * enable it if possible:
1961  *   - plane A only (on pre-965)
1962  *   - no pixel mulitply/line duplication
1963  *   - no alpha buffer discard
1964  *   - no dual wide
1965  *   - framebuffer <= 2048 in width, 1536 in height
1966  *
1967  * We can't assume that any compression will take place (worst case),
1968  * so the compressed buffer has to be the same size as the uncompressed
1969  * one.  It also must reside (along with the line length buffer) in
1970  * stolen memory.
1971  *
1972  * We need to enable/disable FBC on a global basis.
1973  */
1974 static void intel_update_fbc(struct drm_device *dev)
1975 {
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         struct drm_crtc *crtc = NULL, *tmp_crtc;
1978         struct intel_crtc *intel_crtc;
1979         struct drm_framebuffer *fb;
1980         struct intel_framebuffer *intel_fb;
1981         struct drm_i915_gem_object *obj;
1982
1983         DRM_DEBUG_KMS("\n");
1984
1985         if (!i915_powersave)
1986                 return;
1987
1988         if (!I915_HAS_FBC(dev))
1989                 return;
1990
1991         /*
1992          * If FBC is already on, we just have to verify that we can
1993          * keep it that way...
1994          * Need to disable if:
1995          *   - more than one pipe is active
1996          *   - changing FBC params (stride, fence, mode)
1997          *   - new fb is too large to fit in compressed buffer
1998          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1999          */
2000         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
2001                 if (tmp_crtc->enabled && tmp_crtc->fb) {
2002                         if (crtc) {
2003                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
2004                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
2005                                 goto out_disable;
2006                         }
2007                         crtc = tmp_crtc;
2008                 }
2009         }
2010
2011         if (!crtc || crtc->fb == NULL) {
2012                 DRM_DEBUG_KMS("no output, disabling\n");
2013                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2014                 goto out_disable;
2015         }
2016
2017         intel_crtc = to_intel_crtc(crtc);
2018         fb = crtc->fb;
2019         intel_fb = to_intel_framebuffer(fb);
2020         obj = intel_fb->obj;
2021
2022         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2023                 DRM_DEBUG_KMS("framebuffer too large, disabling "
2024                               "compression\n");
2025                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2026                 goto out_disable;
2027         }
2028         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2029             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2030                 DRM_DEBUG_KMS("mode incompatible with compression, "
2031                               "disabling\n");
2032                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2033                 goto out_disable;
2034         }
2035         if ((crtc->mode.hdisplay > 2048) ||
2036             (crtc->mode.vdisplay > 1536)) {
2037                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2038                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2039                 goto out_disable;
2040         }
2041         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
2042                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2043                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2044                 goto out_disable;
2045         }
2046         if (obj->tiling_mode != I915_TILING_X) {
2047                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
2048                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
2049                 goto out_disable;
2050         }
2051
2052         /* If the kernel debugger is active, always disable compression */
2053         if (in_dbg_master())
2054                 goto out_disable;
2055
2056         intel_enable_fbc(crtc, 500);
2057         return;
2058
2059 out_disable:
2060         /* Multiple disables should be harmless */
2061         if (intel_fbc_enabled(dev)) {
2062                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2063                 intel_disable_fbc(dev);
2064         }
2065 }
2066
2067 int
2068 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2069                            struct drm_i915_gem_object *obj,
2070                            struct intel_ring_buffer *pipelined)
2071 {
2072         struct drm_i915_private *dev_priv = dev->dev_private;
2073         u32 alignment;
2074         int ret;
2075
2076         switch (obj->tiling_mode) {
2077         case I915_TILING_NONE:
2078                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2079                         alignment = 128 * 1024;
2080                 else if (INTEL_INFO(dev)->gen >= 4)
2081                         alignment = 4 * 1024;
2082                 else
2083                         alignment = 64 * 1024;
2084                 break;
2085         case I915_TILING_X:
2086                 /* pin() will align the object as required by fence */
2087                 alignment = 0;
2088                 break;
2089         case I915_TILING_Y:
2090                 /* FIXME: Is this true? */
2091                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2092                 return -EINVAL;
2093         default:
2094                 BUG();
2095         }
2096
2097         dev_priv->mm.interruptible = false;
2098         ret = i915_gem_object_pin(obj, alignment, true);
2099         if (ret)
2100                 goto err_interruptible;
2101
2102         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
2103         if (ret)
2104                 goto err_unpin;
2105
2106         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2107          * fence, whereas 965+ only requires a fence if using
2108          * framebuffer compression.  For simplicity, we always install
2109          * a fence as the cost is not that onerous.
2110          */
2111         if (obj->tiling_mode != I915_TILING_NONE) {
2112                 ret = i915_gem_object_get_fence(obj, pipelined);
2113                 if (ret)
2114                         goto err_unpin;
2115         }
2116
2117         dev_priv->mm.interruptible = true;
2118         return 0;
2119
2120 err_unpin:
2121         i915_gem_object_unpin(obj);
2122 err_interruptible:
2123         dev_priv->mm.interruptible = true;
2124         return ret;
2125 }
2126
2127 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2128 static int
2129 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2130                            int x, int y, enum mode_set_atomic state)
2131 {
2132         struct drm_device *dev = crtc->dev;
2133         struct drm_i915_private *dev_priv = dev->dev_private;
2134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2135         struct intel_framebuffer *intel_fb;
2136         struct drm_i915_gem_object *obj;
2137         int plane = intel_crtc->plane;
2138         unsigned long Start, Offset;
2139         u32 dspcntr;
2140         u32 reg;
2141
2142         switch (plane) {
2143         case 0:
2144         case 1:
2145                 break;
2146         default:
2147                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2148                 return -EINVAL;
2149         }
2150
2151         intel_fb = to_intel_framebuffer(fb);
2152         obj = intel_fb->obj;
2153
2154         reg = DSPCNTR(plane);
2155         dspcntr = I915_READ(reg);
2156         /* Mask out pixel format bits in case we change it */
2157         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2158         switch (fb->bits_per_pixel) {
2159         case 8:
2160                 dspcntr |= DISPPLANE_8BPP;
2161                 break;
2162         case 16:
2163                 if (fb->depth == 15)
2164                         dspcntr |= DISPPLANE_15_16BPP;
2165                 else
2166                         dspcntr |= DISPPLANE_16BPP;
2167                 break;
2168         case 24:
2169         case 32:
2170                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2171                 break;
2172         default:
2173                 DRM_ERROR("Unknown color depth\n");
2174                 return -EINVAL;
2175         }
2176         if (INTEL_INFO(dev)->gen >= 4) {
2177                 if (obj->tiling_mode != I915_TILING_NONE)
2178                         dspcntr |= DISPPLANE_TILED;
2179                 else
2180                         dspcntr &= ~DISPPLANE_TILED;
2181         }
2182
2183         if (HAS_PCH_SPLIT(dev))
2184                 /* must disable */
2185                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2186
2187         I915_WRITE(reg, dspcntr);
2188
2189         Start = obj->gtt_offset;
2190         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2191
2192         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2193                       Start, Offset, x, y, fb->pitch);
2194         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2195         if (INTEL_INFO(dev)->gen >= 4) {
2196                 I915_WRITE(DSPSURF(plane), Start);
2197                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2198                 I915_WRITE(DSPADDR(plane), Offset);
2199         } else
2200                 I915_WRITE(DSPADDR(plane), Start + Offset);
2201         POSTING_READ(reg);
2202
2203         intel_update_fbc(dev);
2204         intel_increase_pllclock(crtc);
2205
2206         return 0;
2207 }
2208
2209 static int
2210 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2211                     struct drm_framebuffer *old_fb)
2212 {
2213         struct drm_device *dev = crtc->dev;
2214         struct drm_i915_master_private *master_priv;
2215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216         int ret;
2217
2218         /* no fb bound */
2219         if (!crtc->fb) {
2220                 DRM_DEBUG_KMS("No FB bound\n");
2221                 return 0;
2222         }
2223
2224         switch (intel_crtc->plane) {
2225         case 0:
2226         case 1:
2227                 break;
2228         default:
2229                 return -EINVAL;
2230         }
2231
2232         mutex_lock(&dev->struct_mutex);
2233         ret = intel_pin_and_fence_fb_obj(dev,
2234                                          to_intel_framebuffer(crtc->fb)->obj,
2235                                          NULL);
2236         if (ret != 0) {
2237                 mutex_unlock(&dev->struct_mutex);
2238                 return ret;
2239         }
2240
2241         if (old_fb) {
2242                 struct drm_i915_private *dev_priv = dev->dev_private;
2243                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2244
2245                 wait_event(dev_priv->pending_flip_queue,
2246                            atomic_read(&dev_priv->mm.wedged) ||
2247                            atomic_read(&obj->pending_flip) == 0);
2248
2249                 /* Big Hammer, we also need to ensure that any pending
2250                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251                  * current scanout is retired before unpinning the old
2252                  * framebuffer.
2253                  *
2254                  * This should only fail upon a hung GPU, in which case we
2255                  * can safely continue.
2256                  */
2257                 ret = i915_gem_object_flush_gpu(obj);
2258                 (void) ret;
2259         }
2260
2261         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2262                                          LEAVE_ATOMIC_MODE_SET);
2263         if (ret) {
2264                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2265                 mutex_unlock(&dev->struct_mutex);
2266                 return ret;
2267         }
2268
2269         if (old_fb) {
2270                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2271                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2272         }
2273
2274         mutex_unlock(&dev->struct_mutex);
2275
2276         if (!dev->primary->master)
2277                 return 0;
2278
2279         master_priv = dev->primary->master->driver_priv;
2280         if (!master_priv->sarea_priv)
2281                 return 0;
2282
2283         if (intel_crtc->pipe) {
2284                 master_priv->sarea_priv->pipeB_x = x;
2285                 master_priv->sarea_priv->pipeB_y = y;
2286         } else {
2287                 master_priv->sarea_priv->pipeA_x = x;
2288                 master_priv->sarea_priv->pipeA_y = y;
2289         }
2290
2291         return 0;
2292 }
2293
2294 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2295 {
2296         struct drm_device *dev = crtc->dev;
2297         struct drm_i915_private *dev_priv = dev->dev_private;
2298         u32 dpa_ctl;
2299
2300         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2301         dpa_ctl = I915_READ(DP_A);
2302         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2303
2304         if (clock < 200000) {
2305                 u32 temp;
2306                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2307                 /* workaround for 160Mhz:
2308                    1) program 0x4600c bits 15:0 = 0x8124
2309                    2) program 0x46010 bit 0 = 1
2310                    3) program 0x46034 bit 24 = 1
2311                    4) program 0x64000 bit 14 = 1
2312                    */
2313                 temp = I915_READ(0x4600c);
2314                 temp &= 0xffff0000;
2315                 I915_WRITE(0x4600c, temp | 0x8124);
2316
2317                 temp = I915_READ(0x46010);
2318                 I915_WRITE(0x46010, temp | 1);
2319
2320                 temp = I915_READ(0x46034);
2321                 I915_WRITE(0x46034, temp | (1 << 24));
2322         } else {
2323                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2324         }
2325         I915_WRITE(DP_A, dpa_ctl);
2326
2327         POSTING_READ(DP_A);
2328         udelay(500);
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         temp &= ~FDI_LINK_TRAIN_NONE;
2343         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2344         I915_WRITE(reg, temp);
2345
2346         reg = FDI_RX_CTL(pipe);
2347         temp = I915_READ(reg);
2348         if (HAS_PCH_CPT(dev)) {
2349                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2350                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2351         } else {
2352                 temp &= ~FDI_LINK_TRAIN_NONE;
2353                 temp |= FDI_LINK_TRAIN_NONE;
2354         }
2355         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2356
2357         /* wait one idle pattern time */
2358         POSTING_READ(reg);
2359         udelay(1000);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365         struct drm_device *dev = crtc->dev;
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368         int pipe = intel_crtc->pipe;
2369         int plane = intel_crtc->plane;
2370         u32 reg, temp, tries;
2371
2372         /* FDI needs bits from pipe & plane first */
2373         assert_pipe_enabled(dev_priv, pipe);
2374         assert_plane_enabled(dev_priv, plane);
2375
2376         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377            for train result */
2378         reg = FDI_RX_IMR(pipe);
2379         temp = I915_READ(reg);
2380         temp &= ~FDI_RX_SYMBOL_LOCK;
2381         temp &= ~FDI_RX_BIT_LOCK;
2382         I915_WRITE(reg, temp);
2383         I915_READ(reg);
2384         udelay(150);
2385
2386         /* enable CPU FDI TX and PCH FDI RX */
2387         reg = FDI_TX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~(7 << 19);
2390         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395         reg = FDI_RX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         temp &= ~FDI_LINK_TRAIN_NONE;
2398         temp |= FDI_LINK_TRAIN_PATTERN_1;
2399         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401         POSTING_READ(reg);
2402         udelay(150);
2403
2404         /* Ironlake workaround, enable clock pointer after FDI enable*/
2405         if (HAS_PCH_IBX(dev)) {
2406                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408                            FDI_RX_PHASE_SYNC_POINTER_EN);
2409         }
2410
2411         reg = FDI_RX_IIR(pipe);
2412         for (tries = 0; tries < 5; tries++) {
2413                 temp = I915_READ(reg);
2414                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416                 if ((temp & FDI_RX_BIT_LOCK)) {
2417                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2418                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419                         break;
2420                 }
2421         }
2422         if (tries == 5)
2423                 DRM_ERROR("FDI train 1 fail!\n");
2424
2425         /* Train 2 */
2426         reg = FDI_TX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_LINK_TRAIN_NONE;
2429         temp |= FDI_LINK_TRAIN_PATTERN_2;
2430         I915_WRITE(reg, temp);
2431
2432         reg = FDI_RX_CTL(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_LINK_TRAIN_NONE;
2435         temp |= FDI_LINK_TRAIN_PATTERN_2;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         reg = FDI_RX_IIR(pipe);
2442         for (tries = 0; tries < 5; tries++) {
2443                 temp = I915_READ(reg);
2444                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446                 if (temp & FDI_RX_SYMBOL_LOCK) {
2447                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2449                         break;
2450                 }
2451         }
2452         if (tries == 5)
2453                 DRM_ERROR("FDI train 2 fail!\n");
2454
2455         DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param [] = {
2460         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469         struct drm_device *dev = crtc->dev;
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472         int pipe = intel_crtc->pipe;
2473         u32 reg, temp, i;
2474
2475         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476            for train result */
2477         reg = FDI_RX_IMR(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_RX_SYMBOL_LOCK;
2480         temp &= ~FDI_RX_BIT_LOCK;
2481         I915_WRITE(reg, temp);
2482
2483         POSTING_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494         /* SNB-B */
2495         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498         reg = FDI_RX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         if (HAS_PCH_CPT(dev)) {
2501                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503         } else {
2504                 temp &= ~FDI_LINK_TRAIN_NONE;
2505                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506         }
2507         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509         POSTING_READ(reg);
2510         udelay(150);
2511
2512         for (i = 0; i < 4; i++ ) {
2513                 reg = FDI_TX_CTL(pipe);
2514                 temp = I915_READ(reg);
2515                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516                 temp |= snb_b_fdi_train_param[i];
2517                 I915_WRITE(reg, temp);
2518
2519                 POSTING_READ(reg);
2520                 udelay(500);
2521
2522                 reg = FDI_RX_IIR(pipe);
2523                 temp = I915_READ(reg);
2524                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2525
2526                 if (temp & FDI_RX_BIT_LOCK) {
2527                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2528                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2529                         break;
2530                 }
2531         }
2532         if (i == 4)
2533                 DRM_ERROR("FDI train 1 fail!\n");
2534
2535         /* Train 2 */
2536         reg = FDI_TX_CTL(pipe);
2537         temp = I915_READ(reg);
2538         temp &= ~FDI_LINK_TRAIN_NONE;
2539         temp |= FDI_LINK_TRAIN_PATTERN_2;
2540         if (IS_GEN6(dev)) {
2541                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2542                 /* SNB-B */
2543                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2544         }
2545         I915_WRITE(reg, temp);
2546
2547         reg = FDI_RX_CTL(pipe);
2548         temp = I915_READ(reg);
2549         if (HAS_PCH_CPT(dev)) {
2550                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2551                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2552         } else {
2553                 temp &= ~FDI_LINK_TRAIN_NONE;
2554                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2555         }
2556         I915_WRITE(reg, temp);
2557
2558         POSTING_READ(reg);
2559         udelay(150);
2560
2561         for (i = 0; i < 4; i++ ) {
2562                 reg = FDI_TX_CTL(pipe);
2563                 temp = I915_READ(reg);
2564                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565                 temp |= snb_b_fdi_train_param[i];
2566                 I915_WRITE(reg, temp);
2567
2568                 POSTING_READ(reg);
2569                 udelay(500);
2570
2571                 reg = FDI_RX_IIR(pipe);
2572                 temp = I915_READ(reg);
2573                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574
2575                 if (temp & FDI_RX_SYMBOL_LOCK) {
2576                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2577                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2578                         break;
2579                 }
2580         }
2581         if (i == 4)
2582                 DRM_ERROR("FDI train 2 fail!\n");
2583
2584         DRM_DEBUG_KMS("FDI train done.\n");
2585 }
2586
2587 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2588 {
2589         struct drm_device *dev = crtc->dev;
2590         struct drm_i915_private *dev_priv = dev->dev_private;
2591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2592         int pipe = intel_crtc->pipe;
2593         u32 reg, temp;
2594
2595         /* Write the TU size bits so error detection works */
2596         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2597                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2598
2599         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2600         reg = FDI_RX_CTL(pipe);
2601         temp = I915_READ(reg);
2602         temp &= ~((0x7 << 19) | (0x7 << 16));
2603         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2604         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2605         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2606
2607         POSTING_READ(reg);
2608         udelay(200);
2609
2610         /* Switch from Rawclk to PCDclk */
2611         temp = I915_READ(reg);
2612         I915_WRITE(reg, temp | FDI_PCDCLK);
2613
2614         POSTING_READ(reg);
2615         udelay(200);
2616
2617         /* Enable CPU FDI TX PLL, always on for Ironlake */
2618         reg = FDI_TX_CTL(pipe);
2619         temp = I915_READ(reg);
2620         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2621                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2622
2623                 POSTING_READ(reg);
2624                 udelay(100);
2625         }
2626 }
2627
2628 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2629 {
2630         struct drm_device *dev = crtc->dev;
2631         struct drm_i915_private *dev_priv = dev->dev_private;
2632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2633         int pipe = intel_crtc->pipe;
2634         u32 reg, temp;
2635
2636         /* disable CPU FDI tx and PCH FDI rx */
2637         reg = FDI_TX_CTL(pipe);
2638         temp = I915_READ(reg);
2639         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2640         POSTING_READ(reg);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~(0x7 << 16);
2645         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2646         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2647
2648         POSTING_READ(reg);
2649         udelay(100);
2650
2651         /* Ironlake workaround, disable clock pointer after downing FDI */
2652         if (HAS_PCH_IBX(dev)) {
2653                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2654                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2655                            I915_READ(FDI_RX_CHICKEN(pipe) &
2656                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2657         }
2658
2659         /* still set train pattern 1 */
2660         reg = FDI_TX_CTL(pipe);
2661         temp = I915_READ(reg);
2662         temp &= ~FDI_LINK_TRAIN_NONE;
2663         temp |= FDI_LINK_TRAIN_PATTERN_1;
2664         I915_WRITE(reg, temp);
2665
2666         reg = FDI_RX_CTL(pipe);
2667         temp = I915_READ(reg);
2668         if (HAS_PCH_CPT(dev)) {
2669                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2670                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2671         } else {
2672                 temp &= ~FDI_LINK_TRAIN_NONE;
2673                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2674         }
2675         /* BPC in FDI rx is consistent with that in PIPECONF */
2676         temp &= ~(0x07 << 16);
2677         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2678         I915_WRITE(reg, temp);
2679
2680         POSTING_READ(reg);
2681         udelay(100);
2682 }
2683
2684 /*
2685  * When we disable a pipe, we need to clear any pending scanline wait events
2686  * to avoid hanging the ring, which we assume we are waiting on.
2687  */
2688 static void intel_clear_scanline_wait(struct drm_device *dev)
2689 {
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         struct intel_ring_buffer *ring;
2692         u32 tmp;
2693
2694         if (IS_GEN2(dev))
2695                 /* Can't break the hang on i8xx */
2696                 return;
2697
2698         ring = LP_RING(dev_priv);
2699         tmp = I915_READ_CTL(ring);
2700         if (tmp & RING_WAIT)
2701                 I915_WRITE_CTL(ring, tmp);
2702 }
2703
2704 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2705 {
2706         struct drm_i915_gem_object *obj;
2707         struct drm_i915_private *dev_priv;
2708
2709         if (crtc->fb == NULL)
2710                 return;
2711
2712         obj = to_intel_framebuffer(crtc->fb)->obj;
2713         dev_priv = crtc->dev->dev_private;
2714         wait_event(dev_priv->pending_flip_queue,
2715                    atomic_read(&obj->pending_flip) == 0);
2716 }
2717
2718 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2719 {
2720         struct drm_device *dev = crtc->dev;
2721         struct drm_mode_config *mode_config = &dev->mode_config;
2722         struct intel_encoder *encoder;
2723
2724         /*
2725          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2726          * must be driven by its own crtc; no sharing is possible.
2727          */
2728         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2729                 if (encoder->base.crtc != crtc)
2730                         continue;
2731
2732                 switch (encoder->type) {
2733                 case INTEL_OUTPUT_EDP:
2734                         if (!intel_encoder_is_pch_edp(&encoder->base))
2735                                 return false;
2736                         continue;
2737                 }
2738         }
2739
2740         return true;
2741 }
2742
2743 /*
2744  * Enable PCH resources required for PCH ports:
2745  *   - PCH PLLs
2746  *   - FDI training & RX/TX
2747  *   - update transcoder timings
2748  *   - DP transcoding bits
2749  *   - transcoder
2750  */
2751 static void ironlake_pch_enable(struct drm_crtc *crtc)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756         int pipe = intel_crtc->pipe;
2757         u32 reg, temp;
2758
2759         /* For PCH output, training FDI link */
2760         if (IS_GEN6(dev))
2761                 gen6_fdi_link_train(crtc);
2762         else
2763                 ironlake_fdi_link_train(crtc);
2764
2765         intel_enable_pch_pll(dev_priv, pipe);
2766
2767         if (HAS_PCH_CPT(dev)) {
2768                 /* Be sure PCH DPLL SEL is set */
2769                 temp = I915_READ(PCH_DPLL_SEL);
2770                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2771                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2772                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2773                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2774                 I915_WRITE(PCH_DPLL_SEL, temp);
2775         }
2776
2777         /* set transcoder timing, panel must allow it */
2778         assert_panel_unlocked(dev_priv, pipe);
2779         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2780         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2781         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2782
2783         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2784         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2785         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2786
2787         intel_fdi_normal_train(crtc);
2788
2789         /* For PCH DP, enable TRANS_DP_CTL */
2790         if (HAS_PCH_CPT(dev) &&
2791             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2792                 reg = TRANS_DP_CTL(pipe);
2793                 temp = I915_READ(reg);
2794                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2795                           TRANS_DP_SYNC_MASK |
2796                           TRANS_DP_BPC_MASK);
2797                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2798                          TRANS_DP_ENH_FRAMING);
2799                 temp |= TRANS_DP_8BPC;
2800
2801                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2802                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2803                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2804                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2805
2806                 switch (intel_trans_dp_port_sel(crtc)) {
2807                 case PCH_DP_B:
2808                         temp |= TRANS_DP_PORT_SEL_B;
2809                         break;
2810                 case PCH_DP_C:
2811                         temp |= TRANS_DP_PORT_SEL_C;
2812                         break;
2813                 case PCH_DP_D:
2814                         temp |= TRANS_DP_PORT_SEL_D;
2815                         break;
2816                 default:
2817                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2818                         temp |= TRANS_DP_PORT_SEL_B;
2819                         break;
2820                 }
2821
2822                 I915_WRITE(reg, temp);
2823         }
2824
2825         intel_enable_transcoder(dev_priv, pipe);
2826 }
2827
2828 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2829 {
2830         struct drm_device *dev = crtc->dev;
2831         struct drm_i915_private *dev_priv = dev->dev_private;
2832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2833         int pipe = intel_crtc->pipe;
2834         int plane = intel_crtc->plane;
2835         u32 temp;
2836         bool is_pch_port;
2837
2838         if (intel_crtc->active)
2839                 return;
2840
2841         intel_crtc->active = true;
2842         intel_update_watermarks(dev);
2843
2844         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2845                 temp = I915_READ(PCH_LVDS);
2846                 if ((temp & LVDS_PORT_EN) == 0)
2847                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2848         }
2849
2850         is_pch_port = intel_crtc_driving_pch(crtc);
2851
2852         if (is_pch_port)
2853                 ironlake_fdi_enable(crtc);
2854         else
2855                 ironlake_fdi_disable(crtc);
2856
2857         /* Enable panel fitting for LVDS */
2858         if (dev_priv->pch_pf_size &&
2859             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2860                 /* Force use of hard-coded filter coefficients
2861                  * as some pre-programmed values are broken,
2862                  * e.g. x201.
2863                  */
2864                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2865                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2866                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2867         }
2868
2869         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2870         intel_enable_plane(dev_priv, plane, pipe);
2871
2872         if (is_pch_port)
2873                 ironlake_pch_enable(crtc);
2874
2875         intel_crtc_load_lut(crtc);
2876         intel_update_fbc(dev);
2877         intel_crtc_update_cursor(crtc, true);
2878 }
2879
2880 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2881 {
2882         struct drm_device *dev = crtc->dev;
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885         int pipe = intel_crtc->pipe;
2886         int plane = intel_crtc->plane;
2887         u32 reg, temp;
2888
2889         if (!intel_crtc->active)
2890                 return;
2891
2892         intel_crtc_wait_for_pending_flips(crtc);
2893         drm_vblank_off(dev, pipe);
2894         intel_crtc_update_cursor(crtc, false);
2895
2896         intel_disable_plane(dev_priv, plane, pipe);
2897
2898         if (dev_priv->cfb_plane == plane &&
2899             dev_priv->display.disable_fbc)
2900                 dev_priv->display.disable_fbc(dev);
2901
2902         intel_disable_pipe(dev_priv, pipe);
2903
2904         /* Disable PF */
2905         I915_WRITE(PF_CTL(pipe), 0);
2906         I915_WRITE(PF_WIN_SZ(pipe), 0);
2907
2908         ironlake_fdi_disable(crtc);
2909
2910         /* This is a horrible layering violation; we should be doing this in
2911          * the connector/encoder ->prepare instead, but we don't always have
2912          * enough information there about the config to know whether it will
2913          * actually be necessary or just cause undesired flicker.
2914          */
2915         intel_disable_pch_ports(dev_priv, pipe);
2916
2917         intel_disable_transcoder(dev_priv, pipe);
2918
2919         if (HAS_PCH_CPT(dev)) {
2920                 /* disable TRANS_DP_CTL */
2921                 reg = TRANS_DP_CTL(pipe);
2922                 temp = I915_READ(reg);
2923                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2924                 temp |= TRANS_DP_PORT_SEL_NONE;
2925                 I915_WRITE(reg, temp);
2926
2927                 /* disable DPLL_SEL */
2928                 temp = I915_READ(PCH_DPLL_SEL);
2929                 switch (pipe) {
2930                 case 0:
2931                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2932                         break;
2933                 case 1:
2934                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2935                         break;
2936                 case 2:
2937                         /* FIXME: manage transcoder PLLs? */
2938                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2939                         break;
2940                 default:
2941                         BUG(); /* wtf */
2942                 }
2943                 I915_WRITE(PCH_DPLL_SEL, temp);
2944         }
2945
2946         /* disable PCH DPLL */
2947         intel_disable_pch_pll(dev_priv, pipe);
2948
2949         /* Switch from PCDclk to Rawclk */
2950         reg = FDI_RX_CTL(pipe);
2951         temp = I915_READ(reg);
2952         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2953
2954         /* Disable CPU FDI TX PLL */
2955         reg = FDI_TX_CTL(pipe);
2956         temp = I915_READ(reg);
2957         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2958
2959         POSTING_READ(reg);
2960         udelay(100);
2961
2962         reg = FDI_RX_CTL(pipe);
2963         temp = I915_READ(reg);
2964         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2965
2966         /* Wait for the clocks to turn off. */
2967         POSTING_READ(reg);
2968         udelay(100);
2969
2970         intel_crtc->active = false;
2971         intel_update_watermarks(dev);
2972         intel_update_fbc(dev);
2973         intel_clear_scanline_wait(dev);
2974 }
2975
2976 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2977 {
2978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979         int pipe = intel_crtc->pipe;
2980         int plane = intel_crtc->plane;
2981
2982         /* XXX: When our outputs are all unaware of DPMS modes other than off
2983          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2984          */
2985         switch (mode) {
2986         case DRM_MODE_DPMS_ON:
2987         case DRM_MODE_DPMS_STANDBY:
2988         case DRM_MODE_DPMS_SUSPEND:
2989                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2990                 ironlake_crtc_enable(crtc);
2991                 break;
2992
2993         case DRM_MODE_DPMS_OFF:
2994                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2995                 ironlake_crtc_disable(crtc);
2996                 break;
2997         }
2998 }
2999
3000 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3001 {
3002         if (!enable && intel_crtc->overlay) {
3003                 struct drm_device *dev = intel_crtc->base.dev;
3004                 struct drm_i915_private *dev_priv = dev->dev_private;
3005
3006                 mutex_lock(&dev->struct_mutex);
3007                 dev_priv->mm.interruptible = false;
3008                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3009                 dev_priv->mm.interruptible = true;
3010                 mutex_unlock(&dev->struct_mutex);
3011         }
3012
3013         /* Let userspace switch the overlay on again. In most cases userspace
3014          * has to recompute where to put it anyway.
3015          */
3016 }
3017
3018 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3019 {
3020         struct drm_device *dev = crtc->dev;
3021         struct drm_i915_private *dev_priv = dev->dev_private;
3022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3023         int pipe = intel_crtc->pipe;
3024         int plane = intel_crtc->plane;
3025
3026         if (intel_crtc->active)
3027                 return;
3028
3029         intel_crtc->active = true;
3030         intel_update_watermarks(dev);
3031
3032         intel_enable_pll(dev_priv, pipe);
3033         intel_enable_pipe(dev_priv, pipe, false);
3034         intel_enable_plane(dev_priv, plane, pipe);
3035
3036         intel_crtc_load_lut(crtc);
3037         intel_update_fbc(dev);
3038
3039         /* Give the overlay scaler a chance to enable if it's on this pipe */
3040         intel_crtc_dpms_overlay(intel_crtc, true);
3041         intel_crtc_update_cursor(crtc, true);
3042 }
3043
3044 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3045 {
3046         struct drm_device *dev = crtc->dev;
3047         struct drm_i915_private *dev_priv = dev->dev_private;
3048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3049         int pipe = intel_crtc->pipe;
3050         int plane = intel_crtc->plane;
3051
3052         if (!intel_crtc->active)
3053                 return;
3054
3055         /* Give the overlay scaler a chance to disable if it's on this pipe */
3056         intel_crtc_wait_for_pending_flips(crtc);
3057         drm_vblank_off(dev, pipe);
3058         intel_crtc_dpms_overlay(intel_crtc, false);
3059         intel_crtc_update_cursor(crtc, false);
3060
3061         if (dev_priv->cfb_plane == plane &&
3062             dev_priv->display.disable_fbc)
3063                 dev_priv->display.disable_fbc(dev);
3064
3065         intel_disable_plane(dev_priv, plane, pipe);
3066         intel_disable_pipe(dev_priv, pipe);
3067         intel_disable_pll(dev_priv, pipe);
3068
3069         intel_crtc->active = false;
3070         intel_update_fbc(dev);
3071         intel_update_watermarks(dev);
3072         intel_clear_scanline_wait(dev);
3073 }
3074
3075 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3076 {
3077         /* XXX: When our outputs are all unaware of DPMS modes other than off
3078          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3079          */
3080         switch (mode) {
3081         case DRM_MODE_DPMS_ON:
3082         case DRM_MODE_DPMS_STANDBY:
3083         case DRM_MODE_DPMS_SUSPEND:
3084                 i9xx_crtc_enable(crtc);
3085                 break;
3086         case DRM_MODE_DPMS_OFF:
3087                 i9xx_crtc_disable(crtc);
3088                 break;
3089         }
3090 }
3091
3092 /**
3093  * Sets the power management mode of the pipe and plane.
3094  */
3095 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3096 {
3097         struct drm_device *dev = crtc->dev;
3098         struct drm_i915_private *dev_priv = dev->dev_private;
3099         struct drm_i915_master_private *master_priv;
3100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101         int pipe = intel_crtc->pipe;
3102         bool enabled;
3103
3104         if (intel_crtc->dpms_mode == mode)
3105                 return;
3106
3107         intel_crtc->dpms_mode = mode;
3108
3109         dev_priv->display.dpms(crtc, mode);
3110
3111         if (!dev->primary->master)
3112                 return;
3113
3114         master_priv = dev->primary->master->driver_priv;
3115         if (!master_priv->sarea_priv)
3116                 return;
3117
3118         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3119
3120         switch (pipe) {
3121         case 0:
3122                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3123                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3124                 break;
3125         case 1:
3126                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3127                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3128                 break;
3129         default:
3130                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3131                 break;
3132         }
3133 }
3134
3135 static void intel_crtc_disable(struct drm_crtc *crtc)
3136 {
3137         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3138         struct drm_device *dev = crtc->dev;
3139
3140         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3141
3142         if (crtc->fb) {
3143                 mutex_lock(&dev->struct_mutex);
3144                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3145                 mutex_unlock(&dev->struct_mutex);
3146         }
3147 }
3148
3149 /* Prepare for a mode set.
3150  *
3151  * Note we could be a lot smarter here.  We need to figure out which outputs
3152  * will be enabled, which disabled (in short, how the config will changes)
3153  * and perform the minimum necessary steps to accomplish that, e.g. updating
3154  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3155  * panel fitting is in the proper state, etc.
3156  */
3157 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3158 {
3159         i9xx_crtc_disable(crtc);
3160 }
3161
3162 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3163 {
3164         i9xx_crtc_enable(crtc);
3165 }
3166
3167 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3168 {
3169         ironlake_crtc_disable(crtc);
3170 }
3171
3172 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3173 {
3174         ironlake_crtc_enable(crtc);
3175 }
3176
3177 void intel_encoder_prepare (struct drm_encoder *encoder)
3178 {
3179         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3180         /* lvds has its own version of prepare see intel_lvds_prepare */
3181         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3182 }
3183
3184 void intel_encoder_commit (struct drm_encoder *encoder)
3185 {
3186         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3187         /* lvds has its own version of commit see intel_lvds_commit */
3188         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3189 }
3190
3191 void intel_encoder_destroy(struct drm_encoder *encoder)
3192 {
3193         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3194
3195         drm_encoder_cleanup(encoder);
3196         kfree(intel_encoder);
3197 }
3198
3199 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3200                                   struct drm_display_mode *mode,
3201                                   struct drm_display_mode *adjusted_mode)
3202 {
3203         struct drm_device *dev = crtc->dev;
3204
3205         if (HAS_PCH_SPLIT(dev)) {
3206                 /* FDI link clock is fixed at 2.7G */
3207                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3208                         return false;
3209         }
3210
3211         /* XXX some encoders set the crtcinfo, others don't.
3212          * Obviously we need some form of conflict resolution here...
3213          */
3214         if (adjusted_mode->crtc_htotal == 0)
3215                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3216
3217         return true;
3218 }
3219
3220 static int i945_get_display_clock_speed(struct drm_device *dev)
3221 {
3222         return 400000;
3223 }
3224
3225 static int i915_get_display_clock_speed(struct drm_device *dev)
3226 {
3227         return 333000;
3228 }
3229
3230 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3231 {
3232         return 200000;
3233 }
3234
3235 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3236 {
3237         u16 gcfgc = 0;
3238
3239         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3240
3241         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3242                 return 133000;
3243         else {
3244                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3245                 case GC_DISPLAY_CLOCK_333_MHZ:
3246                         return 333000;
3247                 default:
3248                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3249                         return 190000;
3250                 }
3251         }
3252 }
3253
3254 static int i865_get_display_clock_speed(struct drm_device *dev)
3255 {
3256         return 266000;
3257 }
3258
3259 static int i855_get_display_clock_speed(struct drm_device *dev)
3260 {
3261         u16 hpllcc = 0;
3262         /* Assume that the hardware is in the high speed state.  This
3263          * should be the default.
3264          */
3265         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3266         case GC_CLOCK_133_200:
3267         case GC_CLOCK_100_200:
3268                 return 200000;
3269         case GC_CLOCK_166_250:
3270                 return 250000;
3271         case GC_CLOCK_100_133:
3272                 return 133000;
3273         }
3274
3275         /* Shouldn't happen */
3276         return 0;
3277 }
3278
3279 static int i830_get_display_clock_speed(struct drm_device *dev)
3280 {
3281         return 133000;
3282 }
3283
3284 struct fdi_m_n {
3285         u32        tu;
3286         u32        gmch_m;
3287         u32        gmch_n;
3288         u32        link_m;
3289         u32        link_n;
3290 };
3291
3292 static void
3293 fdi_reduce_ratio(u32 *num, u32 *den)
3294 {
3295         while (*num > 0xffffff || *den > 0xffffff) {
3296                 *num >>= 1;
3297                 *den >>= 1;
3298         }
3299 }
3300
3301 static void
3302 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3303                      int link_clock, struct fdi_m_n *m_n)
3304 {
3305         m_n->tu = 64; /* default size */
3306
3307         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3308         m_n->gmch_m = bits_per_pixel * pixel_clock;
3309         m_n->gmch_n = link_clock * nlanes * 8;
3310         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3311
3312         m_n->link_m = pixel_clock;
3313         m_n->link_n = link_clock;
3314         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3315 }
3316
3317
3318 struct intel_watermark_params {
3319         unsigned long fifo_size;
3320         unsigned long max_wm;
3321         unsigned long default_wm;
3322         unsigned long guard_size;
3323         unsigned long cacheline_size;
3324 };
3325
3326 /* Pineview has different values for various configs */
3327 static const struct intel_watermark_params pineview_display_wm = {
3328         PINEVIEW_DISPLAY_FIFO,
3329         PINEVIEW_MAX_WM,
3330         PINEVIEW_DFT_WM,
3331         PINEVIEW_GUARD_WM,
3332         PINEVIEW_FIFO_LINE_SIZE
3333 };
3334 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3335         PINEVIEW_DISPLAY_FIFO,
3336         PINEVIEW_MAX_WM,
3337         PINEVIEW_DFT_HPLLOFF_WM,
3338         PINEVIEW_GUARD_WM,
3339         PINEVIEW_FIFO_LINE_SIZE
3340 };
3341 static const struct intel_watermark_params pineview_cursor_wm = {
3342         PINEVIEW_CURSOR_FIFO,
3343         PINEVIEW_CURSOR_MAX_WM,
3344         PINEVIEW_CURSOR_DFT_WM,
3345         PINEVIEW_CURSOR_GUARD_WM,
3346         PINEVIEW_FIFO_LINE_SIZE,
3347 };
3348 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3349         PINEVIEW_CURSOR_FIFO,
3350         PINEVIEW_CURSOR_MAX_WM,
3351         PINEVIEW_CURSOR_DFT_WM,
3352         PINEVIEW_CURSOR_GUARD_WM,
3353         PINEVIEW_FIFO_LINE_SIZE
3354 };
3355 static const struct intel_watermark_params g4x_wm_info = {
3356         G4X_FIFO_SIZE,
3357         G4X_MAX_WM,
3358         G4X_MAX_WM,
3359         2,
3360         G4X_FIFO_LINE_SIZE,
3361 };
3362 static const struct intel_watermark_params g4x_cursor_wm_info = {
3363         I965_CURSOR_FIFO,
3364         I965_CURSOR_MAX_WM,
3365         I965_CURSOR_DFT_WM,
3366         2,
3367         G4X_FIFO_LINE_SIZE,
3368 };
3369 static const struct intel_watermark_params i965_cursor_wm_info = {
3370         I965_CURSOR_FIFO,
3371         I965_CURSOR_MAX_WM,
3372         I965_CURSOR_DFT_WM,
3373         2,
3374         I915_FIFO_LINE_SIZE,
3375 };
3376 static const struct intel_watermark_params i945_wm_info = {
3377         I945_FIFO_SIZE,
3378         I915_MAX_WM,
3379         1,
3380         2,
3381         I915_FIFO_LINE_SIZE
3382 };
3383 static const struct intel_watermark_params i915_wm_info = {
3384         I915_FIFO_SIZE,
3385         I915_MAX_WM,
3386         1,
3387         2,
3388         I915_FIFO_LINE_SIZE
3389 };
3390 static const struct intel_watermark_params i855_wm_info = {
3391         I855GM_FIFO_SIZE,
3392         I915_MAX_WM,
3393         1,
3394         2,
3395         I830_FIFO_LINE_SIZE
3396 };
3397 static const struct intel_watermark_params i830_wm_info = {
3398         I830_FIFO_SIZE,
3399         I915_MAX_WM,
3400         1,
3401         2,
3402         I830_FIFO_LINE_SIZE
3403 };
3404
3405 static const struct intel_watermark_params ironlake_display_wm_info = {
3406         ILK_DISPLAY_FIFO,
3407         ILK_DISPLAY_MAXWM,
3408         ILK_DISPLAY_DFTWM,
3409         2,
3410         ILK_FIFO_LINE_SIZE
3411 };
3412 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3413         ILK_CURSOR_FIFO,
3414         ILK_CURSOR_MAXWM,
3415         ILK_CURSOR_DFTWM,
3416         2,
3417         ILK_FIFO_LINE_SIZE
3418 };
3419 static const struct intel_watermark_params ironlake_display_srwm_info = {
3420         ILK_DISPLAY_SR_FIFO,
3421         ILK_DISPLAY_MAX_SRWM,
3422         ILK_DISPLAY_DFT_SRWM,
3423         2,
3424         ILK_FIFO_LINE_SIZE
3425 };
3426 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3427         ILK_CURSOR_SR_FIFO,
3428         ILK_CURSOR_MAX_SRWM,
3429         ILK_CURSOR_DFT_SRWM,
3430         2,
3431         ILK_FIFO_LINE_SIZE
3432 };
3433
3434 static const struct intel_watermark_params sandybridge_display_wm_info = {
3435         SNB_DISPLAY_FIFO,
3436         SNB_DISPLAY_MAXWM,
3437         SNB_DISPLAY_DFTWM,
3438         2,
3439         SNB_FIFO_LINE_SIZE
3440 };
3441 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3442         SNB_CURSOR_FIFO,
3443         SNB_CURSOR_MAXWM,
3444         SNB_CURSOR_DFTWM,
3445         2,
3446         SNB_FIFO_LINE_SIZE
3447 };
3448 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3449         SNB_DISPLAY_SR_FIFO,
3450         SNB_DISPLAY_MAX_SRWM,
3451         SNB_DISPLAY_DFT_SRWM,
3452         2,
3453         SNB_FIFO_LINE_SIZE
3454 };
3455 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3456         SNB_CURSOR_SR_FIFO,
3457         SNB_CURSOR_MAX_SRWM,
3458         SNB_CURSOR_DFT_SRWM,
3459         2,
3460         SNB_FIFO_LINE_SIZE
3461 };
3462
3463
3464 /**
3465  * intel_calculate_wm - calculate watermark level
3466  * @clock_in_khz: pixel clock
3467  * @wm: chip FIFO params
3468  * @pixel_size: display pixel size
3469  * @latency_ns: memory latency for the platform
3470  *
3471  * Calculate the watermark level (the level at which the display plane will
3472  * start fetching from memory again).  Each chip has a different display
3473  * FIFO size and allocation, so the caller needs to figure that out and pass
3474  * in the correct intel_watermark_params structure.
3475  *
3476  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3477  * on the pixel size.  When it reaches the watermark level, it'll start
3478  * fetching FIFO line sized based chunks from memory until the FIFO fills
3479  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3480  * will occur, and a display engine hang could result.
3481  */
3482 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3483                                         const struct intel_watermark_params *wm,
3484                                         int fifo_size,
3485                                         int pixel_size,
3486                                         unsigned long latency_ns)
3487 {
3488         long entries_required, wm_size;
3489
3490         /*
3491          * Note: we need to make sure we don't overflow for various clock &
3492          * latency values.
3493          * clocks go from a few thousand to several hundred thousand.
3494          * latency is usually a few thousand
3495          */
3496         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3497                 1000;
3498         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3499
3500         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3501
3502         wm_size = fifo_size - (entries_required + wm->guard_size);
3503
3504         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3505
3506         /* Don't promote wm_size to unsigned... */
3507         if (wm_size > (long)wm->max_wm)
3508                 wm_size = wm->max_wm;
3509         if (wm_size <= 0)
3510                 wm_size = wm->default_wm;
3511         return wm_size;
3512 }
3513
3514 struct cxsr_latency {
3515         int is_desktop;
3516         int is_ddr3;
3517         unsigned long fsb_freq;
3518         unsigned long mem_freq;
3519         unsigned long display_sr;
3520         unsigned long display_hpll_disable;
3521         unsigned long cursor_sr;
3522         unsigned long cursor_hpll_disable;
3523 };
3524
3525 static const struct cxsr_latency cxsr_latency_table[] = {
3526         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3527         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3528         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3529         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3530         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3531
3532         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3533         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3534         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3535         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3536         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3537
3538         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3539         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3540         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3541         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3542         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3543
3544         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3545         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3546         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3547         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3548         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3549
3550         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3551         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3552         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3553         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3554         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3555
3556         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3557         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3558         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3559         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3560         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3561 };
3562
3563 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3564                                                          int is_ddr3,
3565                                                          int fsb,
3566                                                          int mem)
3567 {
3568         const struct cxsr_latency *latency;
3569         int i;
3570
3571         if (fsb == 0 || mem == 0)
3572                 return NULL;
3573
3574         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3575                 latency = &cxsr_latency_table[i];
3576                 if (is_desktop == latency->is_desktop &&
3577                     is_ddr3 == latency->is_ddr3 &&
3578                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3579                         return latency;
3580         }
3581
3582         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3583
3584         return NULL;
3585 }
3586
3587 static void pineview_disable_cxsr(struct drm_device *dev)
3588 {
3589         struct drm_i915_private *dev_priv = dev->dev_private;
3590
3591         /* deactivate cxsr */
3592         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3593 }
3594
3595 /*
3596  * Latency for FIFO fetches is dependent on several factors:
3597  *   - memory configuration (speed, channels)
3598  *   - chipset
3599  *   - current MCH state
3600  * It can be fairly high in some situations, so here we assume a fairly
3601  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3602  * set this value too high, the FIFO will fetch frequently to stay full)
3603  * and power consumption (set it too low to save power and we might see
3604  * FIFO underruns and display "flicker").
3605  *
3606  * A value of 5us seems to be a good balance; safe for very low end
3607  * platforms but not overly aggressive on lower latency configs.
3608  */
3609 static const int latency_ns = 5000;
3610
3611 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3612 {
3613         struct drm_i915_private *dev_priv = dev->dev_private;
3614         uint32_t dsparb = I915_READ(DSPARB);
3615         int size;
3616
3617         size = dsparb & 0x7f;
3618         if (plane)
3619                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3620
3621         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3622                       plane ? "B" : "A", size);
3623
3624         return size;
3625 }
3626
3627 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3628 {
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         uint32_t dsparb = I915_READ(DSPARB);
3631         int size;
3632
3633         size = dsparb & 0x1ff;
3634         if (plane)
3635                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3636         size >>= 1; /* Convert to cachelines */
3637
3638         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3639                       plane ? "B" : "A", size);
3640
3641         return size;
3642 }
3643
3644 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3645 {
3646         struct drm_i915_private *dev_priv = dev->dev_private;
3647         uint32_t dsparb = I915_READ(DSPARB);
3648         int size;
3649
3650         size = dsparb & 0x7f;
3651         size >>= 2; /* Convert to cachelines */
3652
3653         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3654                       plane ? "B" : "A",
3655                       size);
3656
3657         return size;
3658 }
3659
3660 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3661 {
3662         struct drm_i915_private *dev_priv = dev->dev_private;
3663         uint32_t dsparb = I915_READ(DSPARB);
3664         int size;
3665
3666         size = dsparb & 0x7f;
3667         size >>= 1; /* Convert to cachelines */
3668
3669         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3670                       plane ? "B" : "A", size);
3671
3672         return size;
3673 }
3674
3675 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3676 {
3677         struct drm_crtc *crtc, *enabled = NULL;
3678
3679         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3680                 if (crtc->enabled && crtc->fb) {
3681                         if (enabled)
3682                                 return NULL;
3683                         enabled = crtc;
3684                 }
3685         }
3686
3687         return enabled;
3688 }
3689
3690 static void pineview_update_wm(struct drm_device *dev)
3691 {
3692         struct drm_i915_private *dev_priv = dev->dev_private;
3693         struct drm_crtc *crtc;
3694         const struct cxsr_latency *latency;
3695         u32 reg;
3696         unsigned long wm;
3697
3698         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3699                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3700         if (!latency) {
3701                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3702                 pineview_disable_cxsr(dev);
3703                 return;
3704         }
3705
3706         crtc = single_enabled_crtc(dev);
3707         if (crtc) {
3708                 int clock = crtc->mode.clock;
3709                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3710
3711                 /* Display SR */
3712                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3713                                         pineview_display_wm.fifo_size,
3714                                         pixel_size, latency->display_sr);
3715                 reg = I915_READ(DSPFW1);
3716                 reg &= ~DSPFW_SR_MASK;
3717                 reg |= wm << DSPFW_SR_SHIFT;
3718                 I915_WRITE(DSPFW1, reg);
3719                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3720
3721                 /* cursor SR */
3722                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3723                                         pineview_display_wm.fifo_size,
3724                                         pixel_size, latency->cursor_sr);
3725                 reg = I915_READ(DSPFW3);
3726                 reg &= ~DSPFW_CURSOR_SR_MASK;
3727                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3728                 I915_WRITE(DSPFW3, reg);
3729
3730                 /* Display HPLL off SR */
3731                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3732                                         pineview_display_hplloff_wm.fifo_size,
3733                                         pixel_size, latency->display_hpll_disable);
3734                 reg = I915_READ(DSPFW3);
3735                 reg &= ~DSPFW_HPLL_SR_MASK;
3736                 reg |= wm & DSPFW_HPLL_SR_MASK;
3737                 I915_WRITE(DSPFW3, reg);
3738
3739                 /* cursor HPLL off SR */
3740                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3741                                         pineview_display_hplloff_wm.fifo_size,
3742                                         pixel_size, latency->cursor_hpll_disable);
3743                 reg = I915_READ(DSPFW3);
3744                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3745                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3746                 I915_WRITE(DSPFW3, reg);
3747                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3748
3749                 /* activate cxsr */
3750                 I915_WRITE(DSPFW3,
3751                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3752                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3753         } else {
3754                 pineview_disable_cxsr(dev);
3755                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3756         }
3757 }
3758
3759 static bool g4x_compute_wm0(struct drm_device *dev,
3760                             int plane,
3761                             const struct intel_watermark_params *display,
3762                             int display_latency_ns,
3763                             const struct intel_watermark_params *cursor,
3764                             int cursor_latency_ns,
3765                             int *plane_wm,
3766                             int *cursor_wm)
3767 {
3768         struct drm_crtc *crtc;
3769         int htotal, hdisplay, clock, pixel_size;
3770         int line_time_us, line_count;
3771         int entries, tlb_miss;
3772
3773         crtc = intel_get_crtc_for_plane(dev, plane);
3774         if (crtc->fb == NULL || !crtc->enabled)
3775                 return false;
3776
3777         htotal = crtc->mode.htotal;
3778         hdisplay = crtc->mode.hdisplay;
3779         clock = crtc->mode.clock;
3780         pixel_size = crtc->fb->bits_per_pixel / 8;
3781
3782         /* Use the small buffer method to calculate plane watermark */
3783         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3784         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3785         if (tlb_miss > 0)
3786                 entries += tlb_miss;
3787         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3788         *plane_wm = entries + display->guard_size;
3789         if (*plane_wm > (int)display->max_wm)
3790                 *plane_wm = display->max_wm;
3791
3792         /* Use the large buffer method to calculate cursor watermark */
3793         line_time_us = ((htotal * 1000) / clock);
3794         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3795         entries = line_count * 64 * pixel_size;
3796         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3797         if (tlb_miss > 0)
3798                 entries += tlb_miss;
3799         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3800         *cursor_wm = entries + cursor->guard_size;
3801         if (*cursor_wm > (int)cursor->max_wm)
3802                 *cursor_wm = (int)cursor->max_wm;
3803
3804         return true;
3805 }
3806
3807 /*
3808  * Check the wm result.
3809  *
3810  * If any calculated watermark values is larger than the maximum value that
3811  * can be programmed into the associated watermark register, that watermark
3812  * must be disabled.
3813  */
3814 static bool g4x_check_srwm(struct drm_device *dev,
3815                            int display_wm, int cursor_wm,
3816                            const struct intel_watermark_params *display,
3817                            const struct intel_watermark_params *cursor)
3818 {
3819         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3820                       display_wm, cursor_wm);
3821
3822         if (display_wm > display->max_wm) {
3823                 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3824                               display_wm, display->max_wm);
3825                 return false;
3826         }
3827
3828         if (cursor_wm > cursor->max_wm) {
3829                 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3830                               cursor_wm, cursor->max_wm);
3831                 return false;
3832         }
3833
3834         if (!(display_wm || cursor_wm)) {
3835                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3836                 return false;
3837         }
3838
3839         return true;
3840 }
3841
3842 static bool g4x_compute_srwm(struct drm_device *dev,
3843                              int plane,
3844                              int latency_ns,
3845                              const struct intel_watermark_params *display,
3846                              const struct intel_watermark_params *cursor,
3847                              int *display_wm, int *cursor_wm)
3848 {
3849         struct drm_crtc *crtc;
3850         int hdisplay, htotal, pixel_size, clock;
3851         unsigned long line_time_us;
3852         int line_count, line_size;
3853         int small, large;
3854         int entries;
3855
3856         if (!latency_ns) {
3857                 *display_wm = *cursor_wm = 0;
3858                 return false;
3859         }
3860
3861         crtc = intel_get_crtc_for_plane(dev, plane);
3862         hdisplay = crtc->mode.hdisplay;
3863         htotal = crtc->mode.htotal;
3864         clock = crtc->mode.clock;
3865         pixel_size = crtc->fb->bits_per_pixel / 8;
3866
3867         line_time_us = (htotal * 1000) / clock;
3868         line_count = (latency_ns / line_time_us + 1000) / 1000;
3869         line_size = hdisplay * pixel_size;
3870
3871         /* Use the minimum of the small and large buffer method for primary */
3872         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3873         large = line_count * line_size;
3874
3875         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3876         *display_wm = entries + display->guard_size;
3877
3878         /* calculate the self-refresh watermark for display cursor */
3879         entries = line_count * pixel_size * 64;
3880         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3881         *cursor_wm = entries + cursor->guard_size;
3882
3883         return g4x_check_srwm(dev,
3884                               *display_wm, *cursor_wm,
3885                               display, cursor);
3886 }
3887
3888 #define single_plane_enabled(mask) is_power_of_2(mask)
3889
3890 static void g4x_update_wm(struct drm_device *dev)
3891 {
3892         static const int sr_latency_ns = 12000;
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3895         int plane_sr, cursor_sr;
3896         unsigned int enabled = 0;
3897
3898         if (g4x_compute_wm0(dev, 0,
3899                             &g4x_wm_info, latency_ns,
3900                             &g4x_cursor_wm_info, latency_ns,
3901                             &planea_wm, &cursora_wm))
3902                 enabled |= 1;
3903
3904         if (g4x_compute_wm0(dev, 1,
3905                             &g4x_wm_info, latency_ns,
3906                             &g4x_cursor_wm_info, latency_ns,
3907                             &planeb_wm, &cursorb_wm))
3908                 enabled |= 2;
3909
3910         plane_sr = cursor_sr = 0;
3911         if (single_plane_enabled(enabled) &&
3912             g4x_compute_srwm(dev, ffs(enabled) - 1,
3913                              sr_latency_ns,
3914                              &g4x_wm_info,
3915                              &g4x_cursor_wm_info,
3916                              &plane_sr, &cursor_sr))
3917                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3918         else
3919                 I915_WRITE(FW_BLC_SELF,
3920                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3921
3922         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3923                       planea_wm, cursora_wm,
3924                       planeb_wm, cursorb_wm,
3925                       plane_sr, cursor_sr);
3926
3927         I915_WRITE(DSPFW1,
3928                    (plane_sr << DSPFW_SR_SHIFT) |
3929                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3930                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3931                    planea_wm);
3932         I915_WRITE(DSPFW2,
3933                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3934                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3935         /* HPLL off in SR has some issues on G4x... disable it */
3936         I915_WRITE(DSPFW3,
3937                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3938                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3939 }
3940
3941 static void i965_update_wm(struct drm_device *dev)
3942 {
3943         struct drm_i915_private *dev_priv = dev->dev_private;
3944         struct drm_crtc *crtc;
3945         int srwm = 1;
3946         int cursor_sr = 16;
3947
3948         /* Calc sr entries for one plane configs */
3949         crtc = single_enabled_crtc(dev);
3950         if (crtc) {
3951                 /* self-refresh has much higher latency */
3952                 static const int sr_latency_ns = 12000;
3953                 int clock = crtc->mode.clock;
3954                 int htotal = crtc->mode.htotal;
3955                 int hdisplay = crtc->mode.hdisplay;
3956                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3957                 unsigned long line_time_us;
3958                 int entries;
3959
3960                 line_time_us = ((htotal * 1000) / clock);
3961
3962                 /* Use ns/us then divide to preserve precision */
3963                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3964                         pixel_size * hdisplay;
3965                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3966                 srwm = I965_FIFO_SIZE - entries;
3967                 if (srwm < 0)
3968                         srwm = 1;
3969                 srwm &= 0x1ff;
3970                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3971                               entries, srwm);
3972
3973                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3974                         pixel_size * 64;
3975                 entries = DIV_ROUND_UP(entries,
3976                                           i965_cursor_wm_info.cacheline_size);
3977                 cursor_sr = i965_cursor_wm_info.fifo_size -
3978                         (entries + i965_cursor_wm_info.guard_size);
3979
3980                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3981                         cursor_sr = i965_cursor_wm_info.max_wm;
3982
3983                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3984                               "cursor %d\n", srwm, cursor_sr);
3985
3986                 if (IS_CRESTLINE(dev))
3987                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3988         } else {
3989                 /* Turn off self refresh if both pipes are enabled */
3990                 if (IS_CRESTLINE(dev))
3991                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3992                                    & ~FW_BLC_SELF_EN);
3993         }
3994
3995         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3996                       srwm);
3997
3998         /* 965 has limitations... */
3999         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4000                    (8 << 16) | (8 << 8) | (8 << 0));
4001         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4002         /* update cursor SR watermark */
4003         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4004 }
4005
4006 static void i9xx_update_wm(struct drm_device *dev)
4007 {
4008         struct drm_i915_private *dev_priv = dev->dev_private;
4009         const struct intel_watermark_params *wm_info;
4010         uint32_t fwater_lo;
4011         uint32_t fwater_hi;
4012         int cwm, srwm = 1;
4013         int fifo_size;
4014         int planea_wm, planeb_wm;
4015         struct drm_crtc *crtc, *enabled = NULL;
4016
4017         if (IS_I945GM(dev))
4018                 wm_info = &i945_wm_info;
4019         else if (!IS_GEN2(dev))
4020                 wm_info = &i915_wm_info;
4021         else
4022                 wm_info = &i855_wm_info;
4023
4024         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4025         crtc = intel_get_crtc_for_plane(dev, 0);
4026         if (crtc->enabled && crtc->fb) {
4027                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4028                                                wm_info, fifo_size,
4029                                                crtc->fb->bits_per_pixel / 8,
4030                                                latency_ns);
4031                 enabled = crtc;
4032         } else
4033                 planea_wm = fifo_size - wm_info->guard_size;
4034
4035         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4036         crtc = intel_get_crtc_for_plane(dev, 1);
4037         if (crtc->enabled && crtc->fb) {
4038                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4039                                                wm_info, fifo_size,
4040                                                crtc->fb->bits_per_pixel / 8,
4041                                                latency_ns);
4042                 if (enabled == NULL)
4043                         enabled = crtc;
4044                 else
4045                         enabled = NULL;
4046         } else
4047                 planeb_wm = fifo_size - wm_info->guard_size;
4048
4049         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4050
4051         /*
4052          * Overlay gets an aggressive default since video jitter is bad.
4053          */
4054         cwm = 2;
4055
4056         /* Play safe and disable self-refresh before adjusting watermarks. */
4057         if (IS_I945G(dev) || IS_I945GM(dev))
4058                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4059         else if (IS_I915GM(dev))
4060                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4061
4062         /* Calc sr entries for one plane configs */
4063         if (HAS_FW_BLC(dev) && enabled) {
4064                 /* self-refresh has much higher latency */
4065                 static const int sr_latency_ns = 6000;
4066                 int clock = enabled->mode.clock;
4067                 int htotal = enabled->mode.htotal;
4068                 int hdisplay = enabled->mode.hdisplay;
4069                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4070                 unsigned long line_time_us;
4071                 int entries;
4072
4073                 line_time_us = (htotal * 1000) / clock;
4074
4075                 /* Use ns/us then divide to preserve precision */
4076                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4077                         pixel_size * hdisplay;
4078                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4079                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4080                 srwm = wm_info->fifo_size - entries;
4081                 if (srwm < 0)
4082                         srwm = 1;
4083
4084                 if (IS_I945G(dev) || IS_I945GM(dev))
4085                         I915_WRITE(FW_BLC_SELF,
4086                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4087                 else if (IS_I915GM(dev))
4088                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4089         }
4090
4091         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4092                       planea_wm, planeb_wm, cwm, srwm);
4093
4094         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4095         fwater_hi = (cwm & 0x1f);
4096
4097         /* Set request length to 8 cachelines per fetch */
4098         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4099         fwater_hi = fwater_hi | (1 << 8);
4100
4101         I915_WRITE(FW_BLC, fwater_lo);
4102         I915_WRITE(FW_BLC2, fwater_hi);
4103
4104         if (HAS_FW_BLC(dev)) {
4105                 if (enabled) {
4106                         if (IS_I945G(dev) || IS_I945GM(dev))
4107                                 I915_WRITE(FW_BLC_SELF,
4108                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4109                         else if (IS_I915GM(dev))
4110                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4111                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4112                 } else
4113                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4114         }
4115 }
4116
4117 static void i830_update_wm(struct drm_device *dev)
4118 {
4119         struct drm_i915_private *dev_priv = dev->dev_private;
4120         struct drm_crtc *crtc;
4121         uint32_t fwater_lo;
4122         int planea_wm;
4123
4124         crtc = single_enabled_crtc(dev);
4125         if (crtc == NULL)
4126                 return;
4127
4128         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4129                                        dev_priv->display.get_fifo_size(dev, 0),
4130                                        crtc->fb->bits_per_pixel / 8,
4131                                        latency_ns);
4132         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4133         fwater_lo |= (3<<8) | planea_wm;
4134
4135         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4136
4137         I915_WRITE(FW_BLC, fwater_lo);
4138 }
4139
4140 #define ILK_LP0_PLANE_LATENCY           700
4141 #define ILK_LP0_CURSOR_LATENCY          1300
4142
4143 static bool ironlake_compute_wm0(struct drm_device *dev,
4144                                  int pipe,
4145                                  const struct intel_watermark_params *display,
4146                                  int display_latency_ns,
4147                                  const struct intel_watermark_params *cursor,
4148                                  int cursor_latency_ns,
4149                                  int *plane_wm,
4150                                  int *cursor_wm)
4151 {
4152         struct drm_crtc *crtc;
4153         int htotal, hdisplay, clock, pixel_size;
4154         int line_time_us, line_count;
4155         int entries, tlb_miss;
4156
4157         crtc = intel_get_crtc_for_pipe(dev, pipe);
4158         if (crtc->fb == NULL || !crtc->enabled)
4159                 return false;
4160
4161         htotal = crtc->mode.htotal;
4162         hdisplay = crtc->mode.hdisplay;
4163         clock = crtc->mode.clock;
4164         pixel_size = crtc->fb->bits_per_pixel / 8;
4165
4166         /* Use the small buffer method to calculate plane watermark */
4167         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4168         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4169         if (tlb_miss > 0)
4170                 entries += tlb_miss;
4171         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4172         *plane_wm = entries + display->guard_size;
4173         if (*plane_wm > (int)display->max_wm)
4174                 *plane_wm = display->max_wm;
4175
4176         /* Use the large buffer method to calculate cursor watermark */
4177         line_time_us = ((htotal * 1000) / clock);
4178         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4179         entries = line_count * 64 * pixel_size;
4180         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4181         if (tlb_miss > 0)
4182                 entries += tlb_miss;
4183         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4184         *cursor_wm = entries + cursor->guard_size;
4185         if (*cursor_wm > (int)cursor->max_wm)
4186                 *cursor_wm = (int)cursor->max_wm;
4187
4188         return true;
4189 }
4190
4191 /*
4192  * Check the wm result.
4193  *
4194  * If any calculated watermark values is larger than the maximum value that
4195  * can be programmed into the associated watermark register, that watermark
4196  * must be disabled.
4197  */
4198 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4199                                 int fbc_wm, int display_wm, int cursor_wm,
4200                                 const struct intel_watermark_params *display,
4201                                 const struct intel_watermark_params *cursor)
4202 {
4203         struct drm_i915_private *dev_priv = dev->dev_private;
4204
4205         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4206                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4207
4208         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4209                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4210                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4211
4212                 /* fbc has it's own way to disable FBC WM */
4213                 I915_WRITE(DISP_ARB_CTL,
4214                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4215                 return false;
4216         }
4217
4218         if (display_wm > display->max_wm) {
4219                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4220                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4221                 return false;
4222         }
4223
4224         if (cursor_wm > cursor->max_wm) {
4225                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4226                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4227                 return false;
4228         }
4229
4230         if (!(fbc_wm || display_wm || cursor_wm)) {
4231                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4232                 return false;
4233         }
4234
4235         return true;
4236 }
4237
4238 /*
4239  * Compute watermark values of WM[1-3],
4240  */
4241 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4242                                   int latency_ns,
4243                                   const struct intel_watermark_params *display,
4244                                   const struct intel_watermark_params *cursor,
4245                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4246 {
4247         struct drm_crtc *crtc;
4248         unsigned long line_time_us;
4249         int hdisplay, htotal, pixel_size, clock;
4250         int line_count, line_size;
4251         int small, large;
4252         int entries;
4253
4254         if (!latency_ns) {
4255                 *fbc_wm = *display_wm = *cursor_wm = 0;
4256                 return false;
4257         }
4258
4259         crtc = intel_get_crtc_for_plane(dev, plane);
4260         hdisplay = crtc->mode.hdisplay;
4261         htotal = crtc->mode.htotal;
4262         clock = crtc->mode.clock;
4263         pixel_size = crtc->fb->bits_per_pixel / 8;
4264
4265         line_time_us = (htotal * 1000) / clock;
4266         line_count = (latency_ns / line_time_us + 1000) / 1000;
4267         line_size = hdisplay * pixel_size;
4268
4269         /* Use the minimum of the small and large buffer method for primary */
4270         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4271         large = line_count * line_size;
4272
4273         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4274         *display_wm = entries + display->guard_size;
4275
4276         /*
4277          * Spec says:
4278          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4279          */
4280         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4281
4282         /* calculate the self-refresh watermark for display cursor */
4283         entries = line_count * pixel_size * 64;
4284         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4285         *cursor_wm = entries + cursor->guard_size;
4286
4287         return ironlake_check_srwm(dev, level,
4288                                    *fbc_wm, *display_wm, *cursor_wm,
4289                                    display, cursor);
4290 }
4291
4292 static void ironlake_update_wm(struct drm_device *dev)
4293 {
4294         struct drm_i915_private *dev_priv = dev->dev_private;
4295         int fbc_wm, plane_wm, cursor_wm;
4296         unsigned int enabled;
4297
4298         enabled = 0;
4299         if (ironlake_compute_wm0(dev, 0,
4300                                  &ironlake_display_wm_info,
4301                                  ILK_LP0_PLANE_LATENCY,
4302                                  &ironlake_cursor_wm_info,
4303                                  ILK_LP0_CURSOR_LATENCY,
4304                                  &plane_wm, &cursor_wm)) {
4305                 I915_WRITE(WM0_PIPEA_ILK,
4306                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4307                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4308                               " plane %d, " "cursor: %d\n",
4309                               plane_wm, cursor_wm);
4310                 enabled |= 1;
4311         }
4312
4313         if (ironlake_compute_wm0(dev, 1,
4314                                  &ironlake_display_wm_info,
4315                                  ILK_LP0_PLANE_LATENCY,
4316                                  &ironlake_cursor_wm_info,
4317                                  ILK_LP0_CURSOR_LATENCY,
4318                                  &plane_wm, &cursor_wm)) {
4319                 I915_WRITE(WM0_PIPEB_ILK,
4320                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4321                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4322                               " plane %d, cursor: %d\n",
4323                               plane_wm, cursor_wm);
4324                 enabled |= 2;
4325         }
4326
4327         /*
4328          * Calculate and update the self-refresh watermark only when one
4329          * display plane is used.
4330          */
4331         I915_WRITE(WM3_LP_ILK, 0);
4332         I915_WRITE(WM2_LP_ILK, 0);
4333         I915_WRITE(WM1_LP_ILK, 0);
4334
4335         if (!single_plane_enabled(enabled))
4336                 return;
4337         enabled = ffs(enabled) - 1;
4338
4339         /* WM1 */
4340         if (!ironlake_compute_srwm(dev, 1, enabled,
4341                                    ILK_READ_WM1_LATENCY() * 500,
4342                                    &ironlake_display_srwm_info,
4343                                    &ironlake_cursor_srwm_info,
4344                                    &fbc_wm, &plane_wm, &cursor_wm))
4345                 return;
4346
4347         I915_WRITE(WM1_LP_ILK,
4348                    WM1_LP_SR_EN |
4349                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4350                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4351                    (plane_wm << WM1_LP_SR_SHIFT) |
4352                    cursor_wm);
4353
4354         /* WM2 */
4355         if (!ironlake_compute_srwm(dev, 2, enabled,
4356                                    ILK_READ_WM2_LATENCY() * 500,
4357                                    &ironlake_display_srwm_info,
4358                                    &ironlake_cursor_srwm_info,
4359                                    &fbc_wm, &plane_wm, &cursor_wm))
4360                 return;
4361
4362         I915_WRITE(WM2_LP_ILK,
4363                    WM2_LP_EN |
4364                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4365                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4366                    (plane_wm << WM1_LP_SR_SHIFT) |
4367                    cursor_wm);
4368
4369         /*
4370          * WM3 is unsupported on ILK, probably because we don't have latency
4371          * data for that power state
4372          */
4373 }
4374
4375 static void sandybridge_update_wm(struct drm_device *dev)
4376 {
4377         struct drm_i915_private *dev_priv = dev->dev_private;
4378         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4379         int fbc_wm, plane_wm, cursor_wm;
4380         unsigned int enabled;
4381
4382         enabled = 0;
4383         if (ironlake_compute_wm0(dev, 0,
4384                                  &sandybridge_display_wm_info, latency,
4385                                  &sandybridge_cursor_wm_info, latency,
4386                                  &plane_wm, &cursor_wm)) {
4387                 I915_WRITE(WM0_PIPEA_ILK,
4388                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4389                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4390                               " plane %d, " "cursor: %d\n",
4391                               plane_wm, cursor_wm);
4392                 enabled |= 1;
4393         }
4394
4395         if (ironlake_compute_wm0(dev, 1,
4396                                  &sandybridge_display_wm_info, latency,
4397                                  &sandybridge_cursor_wm_info, latency,
4398                                  &plane_wm, &cursor_wm)) {
4399                 I915_WRITE(WM0_PIPEB_ILK,
4400                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4401                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4402                               " plane %d, cursor: %d\n",
4403                               plane_wm, cursor_wm);
4404                 enabled |= 2;
4405         }
4406
4407         /*
4408          * Calculate and update the self-refresh watermark only when one
4409          * display plane is used.
4410          *
4411          * SNB support 3 levels of watermark.
4412          *
4413          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4414          * and disabled in the descending order
4415          *
4416          */
4417         I915_WRITE(WM3_LP_ILK, 0);
4418         I915_WRITE(WM2_LP_ILK, 0);
4419         I915_WRITE(WM1_LP_ILK, 0);
4420
4421         if (!single_plane_enabled(enabled))
4422                 return;
4423         enabled = ffs(enabled) - 1;
4424
4425         /* WM1 */
4426         if (!ironlake_compute_srwm(dev, 1, enabled,
4427                                    SNB_READ_WM1_LATENCY() * 500,
4428                                    &sandybridge_display_srwm_info,
4429                                    &sandybridge_cursor_srwm_info,
4430                                    &fbc_wm, &plane_wm, &cursor_wm))
4431                 return;
4432
4433         I915_WRITE(WM1_LP_ILK,
4434                    WM1_LP_SR_EN |
4435                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4436                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4437                    (plane_wm << WM1_LP_SR_SHIFT) |
4438                    cursor_wm);
4439
4440         /* WM2 */
4441         if (!ironlake_compute_srwm(dev, 2, enabled,
4442                                    SNB_READ_WM2_LATENCY() * 500,
4443                                    &sandybridge_display_srwm_info,
4444                                    &sandybridge_cursor_srwm_info,
4445                                    &fbc_wm, &plane_wm, &cursor_wm))
4446                 return;
4447
4448         I915_WRITE(WM2_LP_ILK,
4449                    WM2_LP_EN |
4450                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4451                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4452                    (plane_wm << WM1_LP_SR_SHIFT) |
4453                    cursor_wm);
4454
4455         /* WM3 */
4456         if (!ironlake_compute_srwm(dev, 3, enabled,
4457                                    SNB_READ_WM3_LATENCY() * 500,
4458                                    &sandybridge_display_srwm_info,
4459                                    &sandybridge_cursor_srwm_info,
4460                                    &fbc_wm, &plane_wm, &cursor_wm))
4461                 return;
4462
4463         I915_WRITE(WM3_LP_ILK,
4464                    WM3_LP_EN |
4465                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4466                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4467                    (plane_wm << WM1_LP_SR_SHIFT) |
4468                    cursor_wm);
4469 }
4470
4471 /**
4472  * intel_update_watermarks - update FIFO watermark values based on current modes
4473  *
4474  * Calculate watermark values for the various WM regs based on current mode
4475  * and plane configuration.
4476  *
4477  * There are several cases to deal with here:
4478  *   - normal (i.e. non-self-refresh)
4479  *   - self-refresh (SR) mode
4480  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4481  *   - lines are small relative to FIFO size (buffer can hold more than 2
4482  *     lines), so need to account for TLB latency
4483  *
4484  *   The normal calculation is:
4485  *     watermark = dotclock * bytes per pixel * latency
4486  *   where latency is platform & configuration dependent (we assume pessimal
4487  *   values here).
4488  *
4489  *   The SR calculation is:
4490  *     watermark = (trunc(latency/line time)+1) * surface width *
4491  *       bytes per pixel
4492  *   where
4493  *     line time = htotal / dotclock
4494  *     surface width = hdisplay for normal plane and 64 for cursor
4495  *   and latency is assumed to be high, as above.
4496  *
4497  * The final value programmed to the register should always be rounded up,
4498  * and include an extra 2 entries to account for clock crossings.
4499  *
4500  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4501  * to set the non-SR watermarks to 8.
4502  */
4503 static void intel_update_watermarks(struct drm_device *dev)
4504 {
4505         struct drm_i915_private *dev_priv = dev->dev_private;
4506
4507         if (dev_priv->display.update_wm)
4508                 dev_priv->display.update_wm(dev);
4509 }
4510
4511 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4512 {
4513         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4514 }
4515
4516 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4517                                struct drm_display_mode *mode,
4518                                struct drm_display_mode *adjusted_mode,
4519                                int x, int y,
4520                                struct drm_framebuffer *old_fb)
4521 {
4522         struct drm_device *dev = crtc->dev;
4523         struct drm_i915_private *dev_priv = dev->dev_private;
4524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4525         int pipe = intel_crtc->pipe;
4526         int plane = intel_crtc->plane;
4527         u32 fp_reg, dpll_reg;
4528         int refclk, num_connectors = 0;
4529         intel_clock_t clock, reduced_clock;
4530         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4531         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4532         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4533         struct intel_encoder *has_edp_encoder = NULL;
4534         struct drm_mode_config *mode_config = &dev->mode_config;
4535         struct intel_encoder *encoder;
4536         const intel_limit_t *limit;
4537         int ret;
4538         struct fdi_m_n m_n = {0};
4539         u32 reg, temp;
4540         u32 lvds_sync = 0;
4541         int target_clock;
4542
4543         drm_vblank_pre_modeset(dev, pipe);
4544
4545         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4546                 if (encoder->base.crtc != crtc)
4547                         continue;
4548
4549                 switch (encoder->type) {
4550                 case INTEL_OUTPUT_LVDS:
4551                         is_lvds = true;
4552                         break;
4553                 case INTEL_OUTPUT_SDVO:
4554                 case INTEL_OUTPUT_HDMI:
4555                         is_sdvo = true;
4556                         if (encoder->needs_tv_clock)
4557                                 is_tv = true;
4558                         break;
4559                 case INTEL_OUTPUT_DVO:
4560                         is_dvo = true;
4561                         break;
4562                 case INTEL_OUTPUT_TVOUT:
4563                         is_tv = true;
4564                         break;
4565                 case INTEL_OUTPUT_ANALOG:
4566                         is_crt = true;
4567                         break;
4568                 case INTEL_OUTPUT_DISPLAYPORT:
4569                         is_dp = true;
4570                         break;
4571                 case INTEL_OUTPUT_EDP:
4572                         has_edp_encoder = encoder;
4573                         break;
4574                 }
4575
4576                 num_connectors++;
4577         }
4578
4579         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4580                 refclk = dev_priv->lvds_ssc_freq * 1000;
4581                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4582                               refclk / 1000);
4583         } else if (!IS_GEN2(dev)) {
4584                 refclk = 96000;
4585                 if (HAS_PCH_SPLIT(dev) &&
4586                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4587                         refclk = 120000; /* 120Mhz refclk */
4588         } else {
4589                 refclk = 48000;
4590         }
4591
4592         /*
4593          * Returns a set of divisors for the desired target clock with the given
4594          * refclk, or FALSE.  The returned values represent the clock equation:
4595          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4596          */
4597         limit = intel_limit(crtc, refclk);
4598         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4599         if (!ok) {
4600                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4601                 drm_vblank_post_modeset(dev, pipe);
4602                 return -EINVAL;
4603         }
4604
4605         /* Ensure that the cursor is valid for the new mode before changing... */
4606         intel_crtc_update_cursor(crtc, true);
4607
4608         if (is_lvds && dev_priv->lvds_downclock_avail) {
4609                 has_reduced_clock = limit->find_pll(limit, crtc,
4610                                                     dev_priv->lvds_downclock,
4611                                                     refclk,
4612                                                     &reduced_clock);
4613                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4614                         /*
4615                          * If the different P is found, it means that we can't
4616                          * switch the display clock by using the FP0/FP1.
4617                          * In such case we will disable the LVDS downclock
4618                          * feature.
4619                          */
4620                         DRM_DEBUG_KMS("Different P is found for "
4621                                       "LVDS clock/downclock\n");
4622                         has_reduced_clock = 0;
4623                 }
4624         }
4625         /* SDVO TV has fixed PLL values depend on its clock range,
4626            this mirrors vbios setting. */
4627         if (is_sdvo && is_tv) {
4628                 if (adjusted_mode->clock >= 100000
4629                     && adjusted_mode->clock < 140500) {
4630                         clock.p1 = 2;
4631                         clock.p2 = 10;
4632                         clock.n = 3;
4633                         clock.m1 = 16;
4634                         clock.m2 = 8;
4635                 } else if (adjusted_mode->clock >= 140500
4636                            && adjusted_mode->clock <= 200000) {
4637                         clock.p1 = 1;
4638                         clock.p2 = 10;
4639                         clock.n = 6;
4640                         clock.m1 = 12;
4641                         clock.m2 = 8;
4642                 }
4643         }
4644
4645         /* FDI link */
4646         if (HAS_PCH_SPLIT(dev)) {
4647                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4648                 int lane = 0, link_bw, bpp;
4649                 /* CPU eDP doesn't require FDI link, so just set DP M/N
4650                    according to current link config */
4651                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4652                         target_clock = mode->clock;
4653                         intel_edp_link_config(has_edp_encoder,
4654                                               &lane, &link_bw);
4655                 } else {
4656                         /* [e]DP over FDI requires target mode clock
4657                            instead of link clock */
4658                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4659                                 target_clock = mode->clock;
4660                         else
4661                                 target_clock = adjusted_mode->clock;
4662
4663                         /* FDI is a binary signal running at ~2.7GHz, encoding
4664                          * each output octet as 10 bits. The actual frequency
4665                          * is stored as a divider into a 100MHz clock, and the
4666                          * mode pixel clock is stored in units of 1KHz.
4667                          * Hence the bw of each lane in terms of the mode signal
4668                          * is:
4669                          */
4670                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4671                 }
4672
4673                 /* determine panel color depth */
4674                 temp = I915_READ(PIPECONF(pipe));
4675                 temp &= ~PIPE_BPC_MASK;
4676                 if (is_lvds) {
4677                         /* the BPC will be 6 if it is 18-bit LVDS panel */
4678                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4679                                 temp |= PIPE_8BPC;
4680                         else
4681                                 temp |= PIPE_6BPC;
4682                 } else if (has_edp_encoder) {
4683                         switch (dev_priv->edp.bpp/3) {
4684                         case 8:
4685                                 temp |= PIPE_8BPC;
4686                                 break;
4687                         case 10:
4688                                 temp |= PIPE_10BPC;
4689                                 break;
4690                         case 6:
4691                                 temp |= PIPE_6BPC;
4692                                 break;
4693                         case 12:
4694                                 temp |= PIPE_12BPC;
4695                                 break;
4696                         }
4697                 } else
4698                         temp |= PIPE_8BPC;
4699                 I915_WRITE(PIPECONF(pipe), temp);
4700
4701                 switch (temp & PIPE_BPC_MASK) {
4702                 case PIPE_8BPC:
4703                         bpp = 24;
4704                         break;
4705                 case PIPE_10BPC:
4706                         bpp = 30;
4707                         break;
4708                 case PIPE_6BPC:
4709                         bpp = 18;
4710                         break;
4711                 case PIPE_12BPC:
4712                         bpp = 36;
4713                         break;
4714                 default:
4715                         DRM_ERROR("unknown pipe bpc value\n");
4716                         bpp = 24;
4717                 }
4718
4719                 if (!lane) {
4720                         /*
4721                          * Account for spread spectrum to avoid
4722                          * oversubscribing the link. Max center spread
4723                          * is 2.5%; use 5% for safety's sake.
4724                          */
4725                         u32 bps = target_clock * bpp * 21 / 20;
4726                         lane = bps / (link_bw * 8) + 1;
4727                 }
4728
4729                 intel_crtc->fdi_lanes = lane;
4730
4731                 if (pixel_multiplier > 1)
4732                         link_bw *= pixel_multiplier;
4733                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4734         }
4735
4736         /* Ironlake: try to setup display ref clock before DPLL
4737          * enabling. This is only under driver's control after
4738          * PCH B stepping, previous chipset stepping should be
4739          * ignoring this setting.
4740          */
4741         if (HAS_PCH_SPLIT(dev)) {
4742                 temp = I915_READ(PCH_DREF_CONTROL);
4743                 /* Always enable nonspread source */
4744                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4745                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4746                 temp &= ~DREF_SSC_SOURCE_MASK;
4747                 temp |= DREF_SSC_SOURCE_ENABLE;
4748                 I915_WRITE(PCH_DREF_CONTROL, temp);
4749
4750                 POSTING_READ(PCH_DREF_CONTROL);
4751                 udelay(200);
4752
4753                 if (has_edp_encoder) {
4754                         if (intel_panel_use_ssc(dev_priv)) {
4755                                 temp |= DREF_SSC1_ENABLE;
4756                                 I915_WRITE(PCH_DREF_CONTROL, temp);
4757
4758                                 POSTING_READ(PCH_DREF_CONTROL);
4759                                 udelay(200);
4760                         }
4761                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4762
4763                         /* Enable CPU source on CPU attached eDP */
4764                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4765                                 if (intel_panel_use_ssc(dev_priv))
4766                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4767                                 else
4768                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4769                         } else {
4770                                 /* Enable SSC on PCH eDP if needed */
4771                                 if (intel_panel_use_ssc(dev_priv)) {
4772                                         DRM_ERROR("enabling SSC on PCH\n");
4773                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4774                                 }
4775                         }
4776                         I915_WRITE(PCH_DREF_CONTROL, temp);
4777                         POSTING_READ(PCH_DREF_CONTROL);
4778                         udelay(200);
4779                 }
4780         }
4781
4782         if (IS_PINEVIEW(dev)) {
4783                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4784                 if (has_reduced_clock)
4785                         fp2 = (1 << reduced_clock.n) << 16 |
4786                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4787         } else {
4788                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4789                 if (has_reduced_clock)
4790                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4791                                 reduced_clock.m2;
4792         }
4793
4794         /* Enable autotuning of the PLL clock (if permissible) */
4795         if (HAS_PCH_SPLIT(dev)) {
4796                 int factor = 21;
4797
4798                 if (is_lvds) {
4799                         if ((intel_panel_use_ssc(dev_priv) &&
4800                              dev_priv->lvds_ssc_freq == 100) ||
4801                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4802                                 factor = 25;
4803                 } else if (is_sdvo && is_tv)
4804                         factor = 20;
4805
4806                 if (clock.m1 < factor * clock.n)
4807                         fp |= FP_CB_TUNE;
4808         }
4809
4810         dpll = 0;
4811         if (!HAS_PCH_SPLIT(dev))
4812                 dpll = DPLL_VGA_MODE_DIS;
4813
4814         if (!IS_GEN2(dev)) {
4815                 if (is_lvds)
4816                         dpll |= DPLLB_MODE_LVDS;
4817                 else
4818                         dpll |= DPLLB_MODE_DAC_SERIAL;
4819                 if (is_sdvo) {
4820                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4821                         if (pixel_multiplier > 1) {
4822                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4823                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4824                                 else if (HAS_PCH_SPLIT(dev))
4825                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4826                         }
4827                         dpll |= DPLL_DVO_HIGH_SPEED;
4828                 }
4829                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4830                         dpll |= DPLL_DVO_HIGH_SPEED;
4831
4832                 /* compute bitmask from p1 value */
4833                 if (IS_PINEVIEW(dev))
4834                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4835                 else {
4836                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4837                         /* also FPA1 */
4838                         if (HAS_PCH_SPLIT(dev))
4839                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4840                         if (IS_G4X(dev) && has_reduced_clock)
4841                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4842                 }
4843                 switch (clock.p2) {
4844                 case 5:
4845                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4846                         break;
4847                 case 7:
4848                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4849                         break;
4850                 case 10:
4851                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4852                         break;
4853                 case 14:
4854                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4855                         break;
4856                 }
4857                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4858                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4859         } else {
4860                 if (is_lvds) {
4861                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4862                 } else {
4863                         if (clock.p1 == 2)
4864                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4865                         else
4866                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4867                         if (clock.p2 == 4)
4868                                 dpll |= PLL_P2_DIVIDE_BY_4;
4869                 }
4870         }
4871
4872         if (is_sdvo && is_tv)
4873                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4874         else if (is_tv)
4875                 /* XXX: just matching BIOS for now */
4876                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4877                 dpll |= 3;
4878         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4879                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4880         else
4881                 dpll |= PLL_REF_INPUT_DREFCLK;
4882
4883         /* setup pipeconf */
4884         pipeconf = I915_READ(PIPECONF(pipe));
4885
4886         /* Set up the display plane register */
4887         dspcntr = DISPPLANE_GAMMA_ENABLE;
4888
4889         /* Ironlake's plane is forced to pipe, bit 24 is to
4890            enable color space conversion */
4891         if (!HAS_PCH_SPLIT(dev)) {
4892                 if (pipe == 0)
4893                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4894                 else
4895                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4896         }
4897
4898         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4899                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4900                  * core speed.
4901                  *
4902                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4903                  * pipe == 0 check?
4904                  */
4905                 if (mode->clock >
4906                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4907                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4908                 else
4909                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4910         }
4911
4912         if (!HAS_PCH_SPLIT(dev))
4913                 dpll |= DPLL_VCO_ENABLE;
4914
4915         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4916         drm_mode_debug_printmodeline(mode);
4917
4918         /* assign to Ironlake registers */
4919         if (HAS_PCH_SPLIT(dev)) {
4920                 fp_reg = PCH_FP0(pipe);
4921                 dpll_reg = PCH_DPLL(pipe);
4922         } else {
4923                 fp_reg = FP0(pipe);
4924                 dpll_reg = DPLL(pipe);
4925         }
4926
4927         /* PCH eDP needs FDI, but CPU eDP does not */
4928         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4929                 I915_WRITE(fp_reg, fp);
4930                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4931
4932                 POSTING_READ(dpll_reg);
4933                 udelay(150);
4934         }
4935
4936         /* enable transcoder DPLL */
4937         if (HAS_PCH_CPT(dev)) {
4938                 temp = I915_READ(PCH_DPLL_SEL);
4939                 switch (pipe) {
4940                 case 0:
4941                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4942                         break;
4943                 case 1:
4944                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4945                         break;
4946                 case 2:
4947                         /* FIXME: manage transcoder PLLs? */
4948                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4949                         break;
4950                 default:
4951                         BUG();
4952                 }
4953                 I915_WRITE(PCH_DPLL_SEL, temp);
4954
4955                 POSTING_READ(PCH_DPLL_SEL);
4956                 udelay(150);
4957         }
4958
4959         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4960          * This is an exception to the general rule that mode_set doesn't turn
4961          * things on.
4962          */
4963         if (is_lvds) {
4964                 reg = LVDS;
4965                 if (HAS_PCH_SPLIT(dev))
4966                         reg = PCH_LVDS;
4967
4968                 temp = I915_READ(reg);
4969                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4970                 if (pipe == 1) {
4971                         if (HAS_PCH_CPT(dev))
4972                                 temp |= PORT_TRANS_B_SEL_CPT;
4973                         else
4974                                 temp |= LVDS_PIPEB_SELECT;
4975                 } else {
4976                         if (HAS_PCH_CPT(dev))
4977                                 temp &= ~PORT_TRANS_SEL_MASK;
4978                         else
4979                                 temp &= ~LVDS_PIPEB_SELECT;
4980                 }
4981                 /* set the corresponsding LVDS_BORDER bit */
4982                 temp |= dev_priv->lvds_border_bits;
4983                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4984                  * set the DPLLs for dual-channel mode or not.
4985                  */
4986                 if (clock.p2 == 7)
4987                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4988                 else
4989                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4990
4991                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4992                  * appropriately here, but we need to look more thoroughly into how
4993                  * panels behave in the two modes.
4994                  */
4995                 /* set the dithering flag on non-PCH LVDS as needed */
4996                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4997                         if (dev_priv->lvds_dither)
4998                                 temp |= LVDS_ENABLE_DITHER;
4999                         else
5000                                 temp &= ~LVDS_ENABLE_DITHER;
5001                 }
5002                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5003                         lvds_sync |= LVDS_HSYNC_POLARITY;
5004                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5005                         lvds_sync |= LVDS_VSYNC_POLARITY;
5006                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5007                     != lvds_sync) {
5008                         char flags[2] = "-+";
5009                         DRM_INFO("Changing LVDS panel from "
5010                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5011                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5012                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5013                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5014                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5015                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5016                         temp |= lvds_sync;
5017                 }
5018                 I915_WRITE(reg, temp);
5019         }
5020
5021         /* set the dithering flag and clear for anything other than a panel. */
5022         if (HAS_PCH_SPLIT(dev)) {
5023                 pipeconf &= ~PIPECONF_DITHER_EN;
5024                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5025                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5026                         pipeconf |= PIPECONF_DITHER_EN;
5027                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5028                 }
5029         }
5030
5031         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5032                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5033         } else if (HAS_PCH_SPLIT(dev)) {
5034                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5035                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5036                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5037                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5038                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5039         }
5040
5041         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5042                 I915_WRITE(dpll_reg, dpll);
5043
5044                 /* Wait for the clocks to stabilize. */
5045                 POSTING_READ(dpll_reg);
5046                 udelay(150);
5047
5048                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5049                         temp = 0;
5050                         if (is_sdvo) {
5051                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5052                                 if (temp > 1)
5053                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5054                                 else
5055                                         temp = 0;
5056                         }
5057                         I915_WRITE(DPLL_MD(pipe), temp);
5058                 } else {
5059                         /* The pixel multiplier can only be updated once the
5060                          * DPLL is enabled and the clocks are stable.
5061                          *
5062                          * So write it again.
5063                          */
5064                         I915_WRITE(dpll_reg, dpll);
5065                 }
5066         }
5067
5068         intel_crtc->lowfreq_avail = false;
5069         if (is_lvds && has_reduced_clock && i915_powersave) {
5070                 I915_WRITE(fp_reg + 4, fp2);
5071                 intel_crtc->lowfreq_avail = true;
5072                 if (HAS_PIPE_CXSR(dev)) {
5073                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5074                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5075                 }
5076         } else {
5077                 I915_WRITE(fp_reg + 4, fp);
5078                 if (HAS_PIPE_CXSR(dev)) {
5079                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5080                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5081                 }
5082         }
5083
5084         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5085                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5086                 /* the chip adds 2 halflines automatically */
5087                 adjusted_mode->crtc_vdisplay -= 1;
5088                 adjusted_mode->crtc_vtotal -= 1;
5089                 adjusted_mode->crtc_vblank_start -= 1;
5090                 adjusted_mode->crtc_vblank_end -= 1;
5091                 adjusted_mode->crtc_vsync_end -= 1;
5092                 adjusted_mode->crtc_vsync_start -= 1;
5093         } else
5094                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5095
5096         I915_WRITE(HTOTAL(pipe),
5097                    (adjusted_mode->crtc_hdisplay - 1) |
5098                    ((adjusted_mode->crtc_htotal - 1) << 16));
5099         I915_WRITE(HBLANK(pipe),
5100                    (adjusted_mode->crtc_hblank_start - 1) |
5101                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5102         I915_WRITE(HSYNC(pipe),
5103                    (adjusted_mode->crtc_hsync_start - 1) |
5104                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5105
5106         I915_WRITE(VTOTAL(pipe),
5107                    (adjusted_mode->crtc_vdisplay - 1) |
5108                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5109         I915_WRITE(VBLANK(pipe),
5110                    (adjusted_mode->crtc_vblank_start - 1) |
5111                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5112         I915_WRITE(VSYNC(pipe),
5113                    (adjusted_mode->crtc_vsync_start - 1) |
5114                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5115
5116         /* pipesrc and dspsize control the size that is scaled from,
5117          * which should always be the user's requested size.
5118          */
5119         if (!HAS_PCH_SPLIT(dev)) {
5120                 I915_WRITE(DSPSIZE(plane),
5121                            ((mode->vdisplay - 1) << 16) |
5122                            (mode->hdisplay - 1));
5123                 I915_WRITE(DSPPOS(plane), 0);
5124         }
5125         I915_WRITE(PIPESRC(pipe),
5126                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5127
5128         if (HAS_PCH_SPLIT(dev)) {
5129                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5130                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5131                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5132                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5133
5134                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5135                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5136                 }
5137         }
5138
5139         I915_WRITE(PIPECONF(pipe), pipeconf);
5140         POSTING_READ(PIPECONF(pipe));
5141         if (!HAS_PCH_SPLIT(dev))
5142                 intel_enable_pipe(dev_priv, pipe, false);
5143
5144         intel_wait_for_vblank(dev, pipe);
5145
5146         if (IS_GEN5(dev)) {
5147                 /* enable address swizzle for tiling buffer */
5148                 temp = I915_READ(DISP_ARB_CTL);
5149                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5150         }
5151
5152         I915_WRITE(DSPCNTR(plane), dspcntr);
5153         POSTING_READ(DSPCNTR(plane));
5154         if (!HAS_PCH_SPLIT(dev))
5155                 intel_enable_plane(dev_priv, plane, pipe);
5156
5157         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5158
5159         intel_update_watermarks(dev);
5160
5161         drm_vblank_post_modeset(dev, pipe);
5162
5163         return ret;
5164 }
5165
5166 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5167 void intel_crtc_load_lut(struct drm_crtc *crtc)
5168 {
5169         struct drm_device *dev = crtc->dev;
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172         int palreg = PALETTE(intel_crtc->pipe);
5173         int i;
5174
5175         /* The clocks have to be on to load the palette. */
5176         if (!crtc->enabled)
5177                 return;
5178
5179         /* use legacy palette for Ironlake */
5180         if (HAS_PCH_SPLIT(dev))
5181                 palreg = LGC_PALETTE(intel_crtc->pipe);
5182
5183         for (i = 0; i < 256; i++) {
5184                 I915_WRITE(palreg + 4 * i,
5185                            (intel_crtc->lut_r[i] << 16) |
5186                            (intel_crtc->lut_g[i] << 8) |
5187                            intel_crtc->lut_b[i]);
5188         }
5189 }
5190
5191 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5192 {
5193         struct drm_device *dev = crtc->dev;
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5196         bool visible = base != 0;
5197         u32 cntl;
5198
5199         if (intel_crtc->cursor_visible == visible)
5200                 return;
5201
5202         cntl = I915_READ(_CURACNTR);
5203         if (visible) {
5204                 /* On these chipsets we can only modify the base whilst
5205                  * the cursor is disabled.
5206                  */
5207                 I915_WRITE(_CURABASE, base);
5208
5209                 cntl &= ~(CURSOR_FORMAT_MASK);
5210                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5211                 cntl |= CURSOR_ENABLE |
5212                         CURSOR_GAMMA_ENABLE |
5213                         CURSOR_FORMAT_ARGB;
5214         } else
5215                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5216         I915_WRITE(_CURACNTR, cntl);
5217
5218         intel_crtc->cursor_visible = visible;
5219 }
5220
5221 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5222 {
5223         struct drm_device *dev = crtc->dev;
5224         struct drm_i915_private *dev_priv = dev->dev_private;
5225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226         int pipe = intel_crtc->pipe;
5227         bool visible = base != 0;
5228
5229         if (intel_crtc->cursor_visible != visible) {
5230                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5231                 if (base) {
5232                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5233                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5234                         cntl |= pipe << 28; /* Connect to correct pipe */
5235                 } else {
5236                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5237                         cntl |= CURSOR_MODE_DISABLE;
5238                 }
5239                 I915_WRITE(CURCNTR(pipe), cntl);
5240
5241                 intel_crtc->cursor_visible = visible;
5242         }
5243         /* and commit changes on next vblank */
5244         I915_WRITE(CURBASE(pipe), base);
5245 }
5246
5247 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5248 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5249                                      bool on)
5250 {
5251         struct drm_device *dev = crtc->dev;
5252         struct drm_i915_private *dev_priv = dev->dev_private;
5253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254         int pipe = intel_crtc->pipe;
5255         int x = intel_crtc->cursor_x;
5256         int y = intel_crtc->cursor_y;
5257         u32 base, pos;
5258         bool visible;
5259
5260         pos = 0;
5261
5262         if (on && crtc->enabled && crtc->fb) {
5263                 base = intel_crtc->cursor_addr;
5264                 if (x > (int) crtc->fb->width)
5265                         base = 0;
5266
5267                 if (y > (int) crtc->fb->height)
5268                         base = 0;
5269         } else
5270                 base = 0;
5271
5272         if (x < 0) {
5273                 if (x + intel_crtc->cursor_width < 0)
5274                         base = 0;
5275
5276                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5277                 x = -x;
5278         }
5279         pos |= x << CURSOR_X_SHIFT;
5280
5281         if (y < 0) {
5282                 if (y + intel_crtc->cursor_height < 0)
5283                         base = 0;
5284
5285                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5286                 y = -y;
5287         }
5288         pos |= y << CURSOR_Y_SHIFT;
5289
5290         visible = base != 0;
5291         if (!visible && !intel_crtc->cursor_visible)
5292                 return;
5293
5294         I915_WRITE(CURPOS(pipe), pos);
5295         if (IS_845G(dev) || IS_I865G(dev))
5296                 i845_update_cursor(crtc, base);
5297         else
5298                 i9xx_update_cursor(crtc, base);
5299
5300         if (visible)
5301                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5302 }
5303
5304 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5305                                  struct drm_file *file,
5306                                  uint32_t handle,
5307                                  uint32_t width, uint32_t height)
5308 {
5309         struct drm_device *dev = crtc->dev;
5310         struct drm_i915_private *dev_priv = dev->dev_private;
5311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5312         struct drm_i915_gem_object *obj;
5313         uint32_t addr;
5314         int ret;
5315
5316         DRM_DEBUG_KMS("\n");
5317
5318         /* if we want to turn off the cursor ignore width and height */
5319         if (!handle) {
5320                 DRM_DEBUG_KMS("cursor off\n");
5321                 addr = 0;
5322                 obj = NULL;
5323                 mutex_lock(&dev->struct_mutex);
5324                 goto finish;
5325         }
5326
5327         /* Currently we only support 64x64 cursors */
5328         if (width != 64 || height != 64) {
5329                 DRM_ERROR("we currently only support 64x64 cursors\n");
5330                 return -EINVAL;
5331         }
5332
5333         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5334         if (&obj->base == NULL)
5335                 return -ENOENT;
5336
5337         if (obj->base.size < width * height * 4) {
5338                 DRM_ERROR("buffer is to small\n");
5339                 ret = -ENOMEM;
5340                 goto fail;
5341         }
5342
5343         /* we only need to pin inside GTT if cursor is non-phy */
5344         mutex_lock(&dev->struct_mutex);
5345         if (!dev_priv->info->cursor_needs_physical) {
5346                 if (obj->tiling_mode) {
5347                         DRM_ERROR("cursor cannot be tiled\n");
5348                         ret = -EINVAL;
5349                         goto fail_locked;
5350                 }
5351
5352                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5353                 if (ret) {
5354                         DRM_ERROR("failed to pin cursor bo\n");
5355                         goto fail_locked;
5356                 }
5357
5358                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5359                 if (ret) {
5360                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5361                         goto fail_unpin;
5362                 }
5363
5364                 ret = i915_gem_object_put_fence(obj);
5365                 if (ret) {
5366                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5367                         goto fail_unpin;
5368                 }
5369
5370                 addr = obj->gtt_offset;
5371         } else {
5372                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5373                 ret = i915_gem_attach_phys_object(dev, obj,
5374                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5375                                                   align);
5376                 if (ret) {
5377                         DRM_ERROR("failed to attach phys object\n");
5378                         goto fail_locked;
5379                 }
5380                 addr = obj->phys_obj->handle->busaddr;
5381         }
5382
5383         if (IS_GEN2(dev))
5384                 I915_WRITE(CURSIZE, (height << 12) | width);
5385
5386  finish:
5387         if (intel_crtc->cursor_bo) {
5388                 if (dev_priv->info->cursor_needs_physical) {
5389                         if (intel_crtc->cursor_bo != obj)
5390                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5391                 } else
5392                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5393                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5394         }
5395
5396         mutex_unlock(&dev->struct_mutex);
5397
5398         intel_crtc->cursor_addr = addr;
5399         intel_crtc->cursor_bo = obj;
5400         intel_crtc->cursor_width = width;
5401         intel_crtc->cursor_height = height;
5402
5403         intel_crtc_update_cursor(crtc, true);
5404
5405         return 0;
5406 fail_unpin:
5407         i915_gem_object_unpin(obj);
5408 fail_locked:
5409         mutex_unlock(&dev->struct_mutex);
5410 fail:
5411         drm_gem_object_unreference_unlocked(&obj->base);
5412         return ret;
5413 }
5414
5415 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5416 {
5417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5418
5419         intel_crtc->cursor_x = x;
5420         intel_crtc->cursor_y = y;
5421
5422         intel_crtc_update_cursor(crtc, true);
5423
5424         return 0;
5425 }
5426
5427 /** Sets the color ramps on behalf of RandR */
5428 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5429                                  u16 blue, int regno)
5430 {
5431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5432
5433         intel_crtc->lut_r[regno] = red >> 8;
5434         intel_crtc->lut_g[regno] = green >> 8;
5435         intel_crtc->lut_b[regno] = blue >> 8;
5436 }
5437
5438 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5439                              u16 *blue, int regno)
5440 {
5441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5442
5443         *red = intel_crtc->lut_r[regno] << 8;
5444         *green = intel_crtc->lut_g[regno] << 8;
5445         *blue = intel_crtc->lut_b[regno] << 8;
5446 }
5447
5448 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5449                                  u16 *blue, uint32_t start, uint32_t size)
5450 {
5451         int end = (start + size > 256) ? 256 : start + size, i;
5452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5453
5454         for (i = start; i < end; i++) {
5455                 intel_crtc->lut_r[i] = red[i] >> 8;
5456                 intel_crtc->lut_g[i] = green[i] >> 8;
5457                 intel_crtc->lut_b[i] = blue[i] >> 8;
5458         }
5459
5460         intel_crtc_load_lut(crtc);
5461 }
5462
5463 /**
5464  * Get a pipe with a simple mode set on it for doing load-based monitor
5465  * detection.
5466  *
5467  * It will be up to the load-detect code to adjust the pipe as appropriate for
5468  * its requirements.  The pipe will be connected to no other encoders.
5469  *
5470  * Currently this code will only succeed if there is a pipe with no encoders
5471  * configured for it.  In the future, it could choose to temporarily disable
5472  * some outputs to free up a pipe for its use.
5473  *
5474  * \return crtc, or NULL if no pipes are available.
5475  */
5476
5477 /* VESA 640x480x72Hz mode to set on the pipe */
5478 static struct drm_display_mode load_detect_mode = {
5479         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5480                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5481 };
5482
5483 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5484                                             struct drm_connector *connector,
5485                                             struct drm_display_mode *mode,
5486                                             int *dpms_mode)
5487 {
5488         struct intel_crtc *intel_crtc;
5489         struct drm_crtc *possible_crtc;
5490         struct drm_crtc *supported_crtc =NULL;
5491         struct drm_encoder *encoder = &intel_encoder->base;
5492         struct drm_crtc *crtc = NULL;
5493         struct drm_device *dev = encoder->dev;
5494         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5495         struct drm_crtc_helper_funcs *crtc_funcs;
5496         int i = -1;
5497
5498         /*
5499          * Algorithm gets a little messy:
5500          *   - if the connector already has an assigned crtc, use it (but make
5501          *     sure it's on first)
5502          *   - try to find the first unused crtc that can drive this connector,
5503          *     and use that if we find one
5504          *   - if there are no unused crtcs available, try to use the first
5505          *     one we found that supports the connector
5506          */
5507
5508         /* See if we already have a CRTC for this connector */
5509         if (encoder->crtc) {
5510                 crtc = encoder->crtc;
5511                 /* Make sure the crtc and connector are running */
5512                 intel_crtc = to_intel_crtc(crtc);
5513                 *dpms_mode = intel_crtc->dpms_mode;
5514                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5515                         crtc_funcs = crtc->helper_private;
5516                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5517                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5518                 }
5519                 return crtc;
5520         }
5521
5522         /* Find an unused one (if possible) */
5523         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5524                 i++;
5525                 if (!(encoder->possible_crtcs & (1 << i)))
5526                         continue;
5527                 if (!possible_crtc->enabled) {
5528                         crtc = possible_crtc;
5529                         break;
5530                 }
5531                 if (!supported_crtc)
5532                         supported_crtc = possible_crtc;
5533         }
5534
5535         /*
5536          * If we didn't find an unused CRTC, don't use any.
5537          */
5538         if (!crtc) {
5539                 return NULL;
5540         }
5541
5542         encoder->crtc = crtc;
5543         connector->encoder = encoder;
5544         intel_encoder->load_detect_temp = true;
5545
5546         intel_crtc = to_intel_crtc(crtc);
5547         *dpms_mode = intel_crtc->dpms_mode;
5548
5549         if (!crtc->enabled) {
5550                 if (!mode)
5551                         mode = &load_detect_mode;
5552                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5553         } else {
5554                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5555                         crtc_funcs = crtc->helper_private;
5556                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5557                 }
5558
5559                 /* Add this connector to the crtc */
5560                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5561                 encoder_funcs->commit(encoder);
5562         }
5563         /* let the connector get through one full cycle before testing */
5564         intel_wait_for_vblank(dev, intel_crtc->pipe);
5565
5566         return crtc;
5567 }
5568
5569 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5570                                     struct drm_connector *connector, int dpms_mode)
5571 {
5572         struct drm_encoder *encoder = &intel_encoder->base;
5573         struct drm_device *dev = encoder->dev;
5574         struct drm_crtc *crtc = encoder->crtc;
5575         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5576         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5577
5578         if (intel_encoder->load_detect_temp) {
5579                 encoder->crtc = NULL;
5580                 connector->encoder = NULL;
5581                 intel_encoder->load_detect_temp = false;
5582                 crtc->enabled = drm_helper_crtc_in_use(crtc);
5583                 drm_helper_disable_unused_functions(dev);
5584         }
5585
5586         /* Switch crtc and encoder back off if necessary */
5587         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5588                 if (encoder->crtc == crtc)
5589                         encoder_funcs->dpms(encoder, dpms_mode);
5590                 crtc_funcs->dpms(crtc, dpms_mode);
5591         }
5592 }
5593
5594 /* Returns the clock of the currently programmed mode of the given pipe. */
5595 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5596 {
5597         struct drm_i915_private *dev_priv = dev->dev_private;
5598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5599         int pipe = intel_crtc->pipe;
5600         u32 dpll = I915_READ(DPLL(pipe));
5601         u32 fp;
5602         intel_clock_t clock;
5603
5604         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5605                 fp = FP0(pipe);
5606         else
5607                 fp = FP1(pipe);
5608
5609         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5610         if (IS_PINEVIEW(dev)) {
5611                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5612                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5613         } else {
5614                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5615                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5616         }
5617
5618         if (!IS_GEN2(dev)) {
5619                 if (IS_PINEVIEW(dev))
5620                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5621                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5622                 else
5623                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5624                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5625
5626                 switch (dpll & DPLL_MODE_MASK) {
5627                 case DPLLB_MODE_DAC_SERIAL:
5628                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5629                                 5 : 10;
5630                         break;
5631                 case DPLLB_MODE_LVDS:
5632                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5633                                 7 : 14;
5634                         break;
5635                 default:
5636                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5637                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5638                         return 0;
5639                 }
5640
5641                 /* XXX: Handle the 100Mhz refclk */
5642                 intel_clock(dev, 96000, &clock);
5643         } else {
5644                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5645
5646                 if (is_lvds) {
5647                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5648                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5649                         clock.p2 = 14;
5650
5651                         if ((dpll & PLL_REF_INPUT_MASK) ==
5652                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5653                                 /* XXX: might not be 66MHz */
5654                                 intel_clock(dev, 66000, &clock);
5655                         } else
5656                                 intel_clock(dev, 48000, &clock);
5657                 } else {
5658                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5659                                 clock.p1 = 2;
5660                         else {
5661                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5662                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5663                         }
5664                         if (dpll & PLL_P2_DIVIDE_BY_4)
5665                                 clock.p2 = 4;
5666                         else
5667                                 clock.p2 = 2;
5668
5669                         intel_clock(dev, 48000, &clock);
5670                 }
5671         }
5672
5673         /* XXX: It would be nice to validate the clocks, but we can't reuse
5674          * i830PllIsValid() because it relies on the xf86_config connector
5675          * configuration being accurate, which it isn't necessarily.
5676          */
5677
5678         return clock.dot;
5679 }
5680
5681 /** Returns the currently programmed mode of the given pipe. */
5682 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5683                                              struct drm_crtc *crtc)
5684 {
5685         struct drm_i915_private *dev_priv = dev->dev_private;
5686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5687         int pipe = intel_crtc->pipe;
5688         struct drm_display_mode *mode;
5689         int htot = I915_READ(HTOTAL(pipe));
5690         int hsync = I915_READ(HSYNC(pipe));
5691         int vtot = I915_READ(VTOTAL(pipe));
5692         int vsync = I915_READ(VSYNC(pipe));
5693
5694         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5695         if (!mode)
5696                 return NULL;
5697
5698         mode->clock = intel_crtc_clock_get(dev, crtc);
5699         mode->hdisplay = (htot & 0xffff) + 1;
5700         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5701         mode->hsync_start = (hsync & 0xffff) + 1;
5702         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5703         mode->vdisplay = (vtot & 0xffff) + 1;
5704         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5705         mode->vsync_start = (vsync & 0xffff) + 1;
5706         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5707
5708         drm_mode_set_name(mode);
5709         drm_mode_set_crtcinfo(mode, 0);
5710
5711         return mode;
5712 }
5713
5714 #define GPU_IDLE_TIMEOUT 500 /* ms */
5715
5716 /* When this timer fires, we've been idle for awhile */
5717 static void intel_gpu_idle_timer(unsigned long arg)
5718 {
5719         struct drm_device *dev = (struct drm_device *)arg;
5720         drm_i915_private_t *dev_priv = dev->dev_private;
5721
5722         if (!list_empty(&dev_priv->mm.active_list)) {
5723                 /* Still processing requests, so just re-arm the timer. */
5724                 mod_timer(&dev_priv->idle_timer, jiffies +
5725                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5726                 return;
5727         }
5728
5729         dev_priv->busy = false;
5730         queue_work(dev_priv->wq, &dev_priv->idle_work);
5731 }
5732
5733 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5734
5735 static void intel_crtc_idle_timer(unsigned long arg)
5736 {
5737         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5738         struct drm_crtc *crtc = &intel_crtc->base;
5739         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5740         struct intel_framebuffer *intel_fb;
5741
5742         intel_fb = to_intel_framebuffer(crtc->fb);
5743         if (intel_fb && intel_fb->obj->active) {
5744                 /* The framebuffer is still being accessed by the GPU. */
5745                 mod_timer(&intel_crtc->idle_timer, jiffies +
5746                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5747                 return;
5748         }
5749
5750         intel_crtc->busy = false;
5751         queue_work(dev_priv->wq, &dev_priv->idle_work);
5752 }
5753
5754 static void intel_increase_pllclock(struct drm_crtc *crtc)
5755 {
5756         struct drm_device *dev = crtc->dev;
5757         drm_i915_private_t *dev_priv = dev->dev_private;
5758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5759         int pipe = intel_crtc->pipe;
5760         int dpll_reg = DPLL(pipe);
5761         int dpll;
5762
5763         if (HAS_PCH_SPLIT(dev))
5764                 return;
5765
5766         if (!dev_priv->lvds_downclock_avail)
5767                 return;
5768
5769         dpll = I915_READ(dpll_reg);
5770         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5771                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5772
5773                 /* Unlock panel regs */
5774                 I915_WRITE(PP_CONTROL,
5775                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5776
5777                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5778                 I915_WRITE(dpll_reg, dpll);
5779                 intel_wait_for_vblank(dev, pipe);
5780
5781                 dpll = I915_READ(dpll_reg);
5782                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5783                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5784
5785                 /* ...and lock them again */
5786                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5787         }
5788
5789         /* Schedule downclock */
5790         mod_timer(&intel_crtc->idle_timer, jiffies +
5791                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5792 }
5793
5794 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5795 {
5796         struct drm_device *dev = crtc->dev;
5797         drm_i915_private_t *dev_priv = dev->dev_private;
5798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799         int pipe = intel_crtc->pipe;
5800         int dpll_reg = DPLL(pipe);
5801         int dpll = I915_READ(dpll_reg);
5802
5803         if (HAS_PCH_SPLIT(dev))
5804                 return;
5805
5806         if (!dev_priv->lvds_downclock_avail)
5807                 return;
5808
5809         /*
5810          * Since this is called by a timer, we should never get here in
5811          * the manual case.
5812          */
5813         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5814                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5815
5816                 /* Unlock panel regs */
5817                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5818                            PANEL_UNLOCK_REGS);
5819
5820                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5821                 I915_WRITE(dpll_reg, dpll);
5822                 intel_wait_for_vblank(dev, pipe);
5823                 dpll = I915_READ(dpll_reg);
5824                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5825                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5826
5827                 /* ...and lock them again */
5828                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5829         }
5830
5831 }
5832
5833 /**
5834  * intel_idle_update - adjust clocks for idleness
5835  * @work: work struct
5836  *
5837  * Either the GPU or display (or both) went idle.  Check the busy status
5838  * here and adjust the CRTC and GPU clocks as necessary.
5839  */
5840 static void intel_idle_update(struct work_struct *work)
5841 {
5842         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5843                                                     idle_work);
5844         struct drm_device *dev = dev_priv->dev;
5845         struct drm_crtc *crtc;
5846         struct intel_crtc *intel_crtc;
5847
5848         if (!i915_powersave)
5849                 return;
5850
5851         mutex_lock(&dev->struct_mutex);
5852
5853         i915_update_gfx_val(dev_priv);
5854
5855         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5856                 /* Skip inactive CRTCs */
5857                 if (!crtc->fb)
5858                         continue;
5859
5860                 intel_crtc = to_intel_crtc(crtc);
5861                 if (!intel_crtc->busy)
5862                         intel_decrease_pllclock(crtc);
5863         }
5864
5865
5866         mutex_unlock(&dev->struct_mutex);
5867 }
5868
5869 /**
5870  * intel_mark_busy - mark the GPU and possibly the display busy
5871  * @dev: drm device
5872  * @obj: object we're operating on
5873  *
5874  * Callers can use this function to indicate that the GPU is busy processing
5875  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5876  * buffer), we'll also mark the display as busy, so we know to increase its
5877  * clock frequency.
5878  */
5879 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5880 {
5881         drm_i915_private_t *dev_priv = dev->dev_private;
5882         struct drm_crtc *crtc = NULL;
5883         struct intel_framebuffer *intel_fb;
5884         struct intel_crtc *intel_crtc;
5885
5886         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5887                 return;
5888
5889         if (!dev_priv->busy)
5890                 dev_priv->busy = true;
5891         else
5892                 mod_timer(&dev_priv->idle_timer, jiffies +
5893                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5894
5895         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5896                 if (!crtc->fb)
5897                         continue;
5898
5899                 intel_crtc = to_intel_crtc(crtc);
5900                 intel_fb = to_intel_framebuffer(crtc->fb);
5901                 if (intel_fb->obj == obj) {
5902                         if (!intel_crtc->busy) {
5903                                 /* Non-busy -> busy, upclock */
5904                                 intel_increase_pllclock(crtc);
5905                                 intel_crtc->busy = true;
5906                         } else {
5907                                 /* Busy -> busy, put off timer */
5908                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5909                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5910                         }
5911                 }
5912         }
5913 }
5914
5915 static void intel_crtc_destroy(struct drm_crtc *crtc)
5916 {
5917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5918         struct drm_device *dev = crtc->dev;
5919         struct intel_unpin_work *work;
5920         unsigned long flags;
5921
5922         spin_lock_irqsave(&dev->event_lock, flags);
5923         work = intel_crtc->unpin_work;
5924         intel_crtc->unpin_work = NULL;
5925         spin_unlock_irqrestore(&dev->event_lock, flags);
5926
5927         if (work) {
5928                 cancel_work_sync(&work->work);
5929                 kfree(work);
5930         }
5931
5932         drm_crtc_cleanup(crtc);
5933
5934         kfree(intel_crtc);
5935 }
5936
5937 static void intel_unpin_work_fn(struct work_struct *__work)
5938 {
5939         struct intel_unpin_work *work =
5940                 container_of(__work, struct intel_unpin_work, work);
5941
5942         mutex_lock(&work->dev->struct_mutex);
5943         i915_gem_object_unpin(work->old_fb_obj);
5944         drm_gem_object_unreference(&work->pending_flip_obj->base);
5945         drm_gem_object_unreference(&work->old_fb_obj->base);
5946
5947         mutex_unlock(&work->dev->struct_mutex);
5948         kfree(work);
5949 }
5950
5951 static void do_intel_finish_page_flip(struct drm_device *dev,
5952                                       struct drm_crtc *crtc)
5953 {
5954         drm_i915_private_t *dev_priv = dev->dev_private;
5955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5956         struct intel_unpin_work *work;
5957         struct drm_i915_gem_object *obj;
5958         struct drm_pending_vblank_event *e;
5959         struct timeval tnow, tvbl;
5960         unsigned long flags;
5961
5962         /* Ignore early vblank irqs */
5963         if (intel_crtc == NULL)
5964                 return;
5965
5966         do_gettimeofday(&tnow);
5967
5968         spin_lock_irqsave(&dev->event_lock, flags);
5969         work = intel_crtc->unpin_work;
5970         if (work == NULL || !work->pending) {
5971                 spin_unlock_irqrestore(&dev->event_lock, flags);
5972                 return;
5973         }
5974
5975         intel_crtc->unpin_work = NULL;
5976
5977         if (work->event) {
5978                 e = work->event;
5979                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5980
5981                 /* Called before vblank count and timestamps have
5982                  * been updated for the vblank interval of flip
5983                  * completion? Need to increment vblank count and
5984                  * add one videorefresh duration to returned timestamp
5985                  * to account for this. We assume this happened if we
5986                  * get called over 0.9 frame durations after the last
5987                  * timestamped vblank.
5988                  *
5989                  * This calculation can not be used with vrefresh rates
5990                  * below 5Hz (10Hz to be on the safe side) without
5991                  * promoting to 64 integers.
5992                  */
5993                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5994                     9 * crtc->framedur_ns) {
5995                         e->event.sequence++;
5996                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5997                                              crtc->framedur_ns);
5998                 }
5999
6000                 e->event.tv_sec = tvbl.tv_sec;
6001                 e->event.tv_usec = tvbl.tv_usec;
6002
6003                 list_add_tail(&e->base.link,
6004                               &e->base.file_priv->event_list);
6005                 wake_up_interruptible(&e->base.file_priv->event_wait);
6006         }
6007
6008         drm_vblank_put(dev, intel_crtc->pipe);
6009
6010         spin_unlock_irqrestore(&dev->event_lock, flags);
6011
6012         obj = work->old_fb_obj;
6013
6014         atomic_clear_mask(1 << intel_crtc->plane,
6015                           &obj->pending_flip.counter);
6016         if (atomic_read(&obj->pending_flip) == 0)
6017                 wake_up(&dev_priv->pending_flip_queue);
6018
6019         schedule_work(&work->work);
6020
6021         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6022 }
6023
6024 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6025 {
6026         drm_i915_private_t *dev_priv = dev->dev_private;
6027         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6028
6029         do_intel_finish_page_flip(dev, crtc);
6030 }
6031
6032 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6033 {
6034         drm_i915_private_t *dev_priv = dev->dev_private;
6035         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6036
6037         do_intel_finish_page_flip(dev, crtc);
6038 }
6039
6040 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6041 {
6042         drm_i915_private_t *dev_priv = dev->dev_private;
6043         struct intel_crtc *intel_crtc =
6044                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6045         unsigned long flags;
6046
6047         spin_lock_irqsave(&dev->event_lock, flags);
6048         if (intel_crtc->unpin_work) {
6049                 if ((++intel_crtc->unpin_work->pending) > 1)
6050                         DRM_ERROR("Prepared flip multiple times\n");
6051         } else {
6052                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6053         }
6054         spin_unlock_irqrestore(&dev->event_lock, flags);
6055 }
6056
6057 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6058                                 struct drm_framebuffer *fb,
6059                                 struct drm_pending_vblank_event *event)
6060 {
6061         struct drm_device *dev = crtc->dev;
6062         struct drm_i915_private *dev_priv = dev->dev_private;
6063         struct intel_framebuffer *intel_fb;
6064         struct drm_i915_gem_object *obj;
6065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6066         struct intel_unpin_work *work;
6067         unsigned long flags, offset;
6068         int pipe = intel_crtc->pipe;
6069         u32 pf, pipesrc;
6070         int ret;
6071
6072         work = kzalloc(sizeof *work, GFP_KERNEL);
6073         if (work == NULL)
6074                 return -ENOMEM;
6075
6076         work->event = event;
6077         work->dev = crtc->dev;
6078         intel_fb = to_intel_framebuffer(crtc->fb);
6079         work->old_fb_obj = intel_fb->obj;
6080         INIT_WORK(&work->work, intel_unpin_work_fn);
6081
6082         /* We borrow the event spin lock for protecting unpin_work */
6083         spin_lock_irqsave(&dev->event_lock, flags);
6084         if (intel_crtc->unpin_work) {
6085                 spin_unlock_irqrestore(&dev->event_lock, flags);
6086                 kfree(work);
6087
6088                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6089                 return -EBUSY;
6090         }
6091         intel_crtc->unpin_work = work;
6092         spin_unlock_irqrestore(&dev->event_lock, flags);
6093
6094         intel_fb = to_intel_framebuffer(fb);
6095         obj = intel_fb->obj;
6096
6097         mutex_lock(&dev->struct_mutex);
6098         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6099         if (ret)
6100                 goto cleanup_work;
6101
6102         /* Reference the objects for the scheduled work. */
6103         drm_gem_object_reference(&work->old_fb_obj->base);
6104         drm_gem_object_reference(&obj->base);
6105
6106         crtc->fb = fb;
6107
6108         ret = drm_vblank_get(dev, intel_crtc->pipe);
6109         if (ret)
6110                 goto cleanup_objs;
6111
6112         if (IS_GEN3(dev) || IS_GEN2(dev)) {
6113                 u32 flip_mask;
6114
6115                 /* Can't queue multiple flips, so wait for the previous
6116                  * one to finish before executing the next.
6117                  */
6118                 ret = BEGIN_LP_RING(2);
6119                 if (ret)
6120                         goto cleanup_objs;
6121
6122                 if (intel_crtc->plane)
6123                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6124                 else
6125                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6126                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6127                 OUT_RING(MI_NOOP);
6128                 ADVANCE_LP_RING();
6129         }
6130
6131         work->pending_flip_obj = obj;
6132
6133         work->enable_stall_check = true;
6134
6135         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6136         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6137
6138         ret = BEGIN_LP_RING(4);
6139         if (ret)
6140                 goto cleanup_objs;
6141
6142         /* Block clients from rendering to the new back buffer until
6143          * the flip occurs and the object is no longer visible.
6144          */
6145         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6146
6147         switch (INTEL_INFO(dev)->gen) {
6148         case 2:
6149                 OUT_RING(MI_DISPLAY_FLIP |
6150                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6151                 OUT_RING(fb->pitch);
6152                 OUT_RING(obj->gtt_offset + offset);
6153                 OUT_RING(MI_NOOP);
6154                 break;
6155
6156         case 3:
6157                 OUT_RING(MI_DISPLAY_FLIP_I915 |
6158                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6159                 OUT_RING(fb->pitch);
6160                 OUT_RING(obj->gtt_offset + offset);
6161                 OUT_RING(MI_NOOP);
6162                 break;
6163
6164         case 4:
6165         case 5:
6166                 /* i965+ uses the linear or tiled offsets from the
6167                  * Display Registers (which do not change across a page-flip)
6168                  * so we need only reprogram the base address.
6169                  */
6170                 OUT_RING(MI_DISPLAY_FLIP |
6171                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6172                 OUT_RING(fb->pitch);
6173                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6174
6175                 /* XXX Enabling the panel-fitter across page-flip is so far
6176                  * untested on non-native modes, so ignore it for now.
6177                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6178                  */
6179                 pf = 0;
6180                 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6181                 OUT_RING(pf | pipesrc);
6182                 break;
6183
6184         case 6:
6185                 OUT_RING(MI_DISPLAY_FLIP |
6186                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6187                 OUT_RING(fb->pitch | obj->tiling_mode);
6188                 OUT_RING(obj->gtt_offset);
6189
6190                 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6191                 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6192                 OUT_RING(pf | pipesrc);
6193                 break;
6194         }
6195         ADVANCE_LP_RING();
6196
6197         mutex_unlock(&dev->struct_mutex);
6198
6199         trace_i915_flip_request(intel_crtc->plane, obj);
6200
6201         return 0;
6202
6203 cleanup_objs:
6204         drm_gem_object_unreference(&work->old_fb_obj->base);
6205         drm_gem_object_unreference(&obj->base);
6206 cleanup_work:
6207         mutex_unlock(&dev->struct_mutex);
6208
6209         spin_lock_irqsave(&dev->event_lock, flags);
6210         intel_crtc->unpin_work = NULL;
6211         spin_unlock_irqrestore(&dev->event_lock, flags);
6212
6213         kfree(work);
6214
6215         return ret;
6216 }
6217
6218 static void intel_crtc_reset(struct drm_crtc *crtc)
6219 {
6220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6221
6222         /* Reset flags back to the 'unknown' status so that they
6223          * will be correctly set on the initial modeset.
6224          */
6225         intel_crtc->dpms_mode = -1;
6226 }
6227
6228 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6229         .dpms = intel_crtc_dpms,
6230         .mode_fixup = intel_crtc_mode_fixup,
6231         .mode_set = intel_crtc_mode_set,
6232         .mode_set_base = intel_pipe_set_base,
6233         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6234         .load_lut = intel_crtc_load_lut,
6235         .disable = intel_crtc_disable,
6236 };
6237
6238 static const struct drm_crtc_funcs intel_crtc_funcs = {
6239         .reset = intel_crtc_reset,
6240         .cursor_set = intel_crtc_cursor_set,
6241         .cursor_move = intel_crtc_cursor_move,
6242         .gamma_set = intel_crtc_gamma_set,
6243         .set_config = drm_crtc_helper_set_config,
6244         .destroy = intel_crtc_destroy,
6245         .page_flip = intel_crtc_page_flip,
6246 };
6247
6248 static void intel_sanitize_modesetting(struct drm_device *dev,
6249                                        int pipe, int plane)
6250 {
6251         struct drm_i915_private *dev_priv = dev->dev_private;
6252         u32 reg, val;
6253
6254         if (HAS_PCH_SPLIT(dev))
6255                 return;
6256
6257         /* Who knows what state these registers were left in by the BIOS or
6258          * grub?
6259          *
6260          * If we leave the registers in a conflicting state (e.g. with the
6261          * display plane reading from the other pipe than the one we intend
6262          * to use) then when we attempt to teardown the active mode, we will
6263          * not disable the pipes and planes in the correct order -- leaving
6264          * a plane reading from a disabled pipe and possibly leading to
6265          * undefined behaviour.
6266          */
6267
6268         reg = DSPCNTR(plane);
6269         val = I915_READ(reg);
6270
6271         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6272                 return;
6273         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6274                 return;
6275
6276         /* This display plane is active and attached to the other CPU pipe. */
6277         pipe = !pipe;
6278
6279         /* Disable the plane and wait for it to stop reading from the pipe. */
6280         intel_disable_plane(dev_priv, plane, pipe);
6281         intel_disable_pipe(dev_priv, pipe);
6282 }
6283
6284 static void intel_crtc_init(struct drm_device *dev, int pipe)
6285 {
6286         drm_i915_private_t *dev_priv = dev->dev_private;
6287         struct intel_crtc *intel_crtc;
6288         int i;
6289
6290         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6291         if (intel_crtc == NULL)
6292                 return;
6293
6294         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6295
6296         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6297         for (i = 0; i < 256; i++) {
6298                 intel_crtc->lut_r[i] = i;
6299                 intel_crtc->lut_g[i] = i;
6300                 intel_crtc->lut_b[i] = i;
6301         }
6302
6303         /* Swap pipes & planes for FBC on pre-965 */
6304         intel_crtc->pipe = pipe;
6305         intel_crtc->plane = pipe;
6306         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6307                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6308                 intel_crtc->plane = !pipe;
6309         }
6310
6311         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6312                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6313         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6314         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6315
6316         intel_crtc_reset(&intel_crtc->base);
6317         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6318
6319         if (HAS_PCH_SPLIT(dev)) {
6320                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6321                 intel_helper_funcs.commit = ironlake_crtc_commit;
6322         } else {
6323                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6324                 intel_helper_funcs.commit = i9xx_crtc_commit;
6325         }
6326
6327         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6328
6329         intel_crtc->busy = false;
6330
6331         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6332                     (unsigned long)intel_crtc);
6333
6334         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6335 }
6336
6337 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6338                                 struct drm_file *file)
6339 {
6340         drm_i915_private_t *dev_priv = dev->dev_private;
6341         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6342         struct drm_mode_object *drmmode_obj;
6343         struct intel_crtc *crtc;
6344
6345         if (!dev_priv) {
6346                 DRM_ERROR("called with no initialization\n");
6347                 return -EINVAL;
6348         }
6349
6350         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6351                         DRM_MODE_OBJECT_CRTC);
6352
6353         if (!drmmode_obj) {
6354                 DRM_ERROR("no such CRTC id\n");
6355                 return -EINVAL;
6356         }
6357
6358         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6359         pipe_from_crtc_id->pipe = crtc->pipe;
6360
6361         return 0;
6362 }
6363
6364 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6365 {
6366         struct intel_encoder *encoder;
6367         int index_mask = 0;
6368         int entry = 0;
6369
6370         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6371                 if (type_mask & encoder->clone_mask)
6372                         index_mask |= (1 << entry);
6373                 entry++;
6374         }
6375
6376         return index_mask;
6377 }
6378
6379 static bool has_edp_a(struct drm_device *dev)
6380 {
6381         struct drm_i915_private *dev_priv = dev->dev_private;
6382
6383         if (!IS_MOBILE(dev))
6384                 return false;
6385
6386         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6387                 return false;
6388
6389         if (IS_GEN5(dev) &&
6390             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6391                 return false;
6392
6393         return true;
6394 }
6395
6396 static void intel_setup_outputs(struct drm_device *dev)
6397 {
6398         struct drm_i915_private *dev_priv = dev->dev_private;
6399         struct intel_encoder *encoder;
6400         bool dpd_is_edp = false;
6401         bool has_lvds = false;
6402
6403         if (IS_MOBILE(dev) && !IS_I830(dev))
6404                 has_lvds = intel_lvds_init(dev);
6405         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6406                 /* disable the panel fitter on everything but LVDS */
6407                 I915_WRITE(PFIT_CONTROL, 0);
6408         }
6409
6410         if (HAS_PCH_SPLIT(dev)) {
6411                 dpd_is_edp = intel_dpd_is_edp(dev);
6412
6413                 if (has_edp_a(dev))
6414                         intel_dp_init(dev, DP_A);
6415
6416                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6417                         intel_dp_init(dev, PCH_DP_D);
6418         }
6419
6420         intel_crt_init(dev);
6421
6422         if (HAS_PCH_SPLIT(dev)) {
6423                 int found;
6424
6425                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6426                         /* PCH SDVOB multiplex with HDMIB */
6427                         found = intel_sdvo_init(dev, PCH_SDVOB);
6428                         if (!found)
6429                                 intel_hdmi_init(dev, HDMIB);
6430                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6431                                 intel_dp_init(dev, PCH_DP_B);
6432                 }
6433
6434                 if (I915_READ(HDMIC) & PORT_DETECTED)
6435                         intel_hdmi_init(dev, HDMIC);
6436
6437                 if (I915_READ(HDMID) & PORT_DETECTED)
6438                         intel_hdmi_init(dev, HDMID);
6439
6440                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6441                         intel_dp_init(dev, PCH_DP_C);
6442
6443                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6444                         intel_dp_init(dev, PCH_DP_D);
6445
6446         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6447                 bool found = false;
6448
6449                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6450                         DRM_DEBUG_KMS("probing SDVOB\n");
6451                         found = intel_sdvo_init(dev, SDVOB);
6452                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6453                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6454                                 intel_hdmi_init(dev, SDVOB);
6455                         }
6456
6457                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6458                                 DRM_DEBUG_KMS("probing DP_B\n");
6459                                 intel_dp_init(dev, DP_B);
6460                         }
6461                 }
6462
6463                 /* Before G4X SDVOC doesn't have its own detect register */
6464
6465                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6466                         DRM_DEBUG_KMS("probing SDVOC\n");
6467                         found = intel_sdvo_init(dev, SDVOC);
6468                 }
6469
6470                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6471
6472                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6473                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6474                                 intel_hdmi_init(dev, SDVOC);
6475                         }
6476                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6477                                 DRM_DEBUG_KMS("probing DP_C\n");
6478                                 intel_dp_init(dev, DP_C);
6479                         }
6480                 }
6481
6482                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6483                     (I915_READ(DP_D) & DP_DETECTED)) {
6484                         DRM_DEBUG_KMS("probing DP_D\n");
6485                         intel_dp_init(dev, DP_D);
6486                 }
6487         } else if (IS_GEN2(dev))
6488                 intel_dvo_init(dev);
6489
6490         if (SUPPORTS_TV(dev))
6491                 intel_tv_init(dev);
6492
6493         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6494                 encoder->base.possible_crtcs = encoder->crtc_mask;
6495                 encoder->base.possible_clones =
6496                         intel_encoder_clones(dev, encoder->clone_mask);
6497         }
6498
6499         intel_panel_setup_backlight(dev);
6500 }
6501
6502 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6503 {
6504         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6505
6506         drm_framebuffer_cleanup(fb);
6507         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6508
6509         kfree(intel_fb);
6510 }
6511
6512 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6513                                                 struct drm_file *file,
6514                                                 unsigned int *handle)
6515 {
6516         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6517         struct drm_i915_gem_object *obj = intel_fb->obj;
6518
6519         return drm_gem_handle_create(file, &obj->base, handle);
6520 }
6521
6522 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6523         .destroy = intel_user_framebuffer_destroy,
6524         .create_handle = intel_user_framebuffer_create_handle,
6525 };
6526
6527 int intel_framebuffer_init(struct drm_device *dev,
6528                            struct intel_framebuffer *intel_fb,
6529                            struct drm_mode_fb_cmd *mode_cmd,
6530                            struct drm_i915_gem_object *obj)
6531 {
6532         int ret;
6533
6534         if (obj->tiling_mode == I915_TILING_Y)
6535                 return -EINVAL;
6536
6537         if (mode_cmd->pitch & 63)
6538                 return -EINVAL;
6539
6540         switch (mode_cmd->bpp) {
6541         case 8:
6542         case 16:
6543         case 24:
6544         case 32:
6545                 break;
6546         default:
6547                 return -EINVAL;
6548         }
6549
6550         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6551         if (ret) {
6552                 DRM_ERROR("framebuffer init failed %d\n", ret);
6553                 return ret;
6554         }
6555
6556         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6557         intel_fb->obj = obj;
6558         return 0;
6559 }
6560
6561 static struct drm_framebuffer *
6562 intel_user_framebuffer_create(struct drm_device *dev,
6563                               struct drm_file *filp,
6564                               struct drm_mode_fb_cmd *mode_cmd)
6565 {
6566         struct drm_i915_gem_object *obj;
6567         struct intel_framebuffer *intel_fb;
6568         int ret;
6569
6570         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6571         if (&obj->base == NULL)
6572                 return ERR_PTR(-ENOENT);
6573
6574         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6575         if (!intel_fb)
6576                 return ERR_PTR(-ENOMEM);
6577
6578         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6579         if (ret) {
6580                 drm_gem_object_unreference_unlocked(&obj->base);
6581                 kfree(intel_fb);
6582                 return ERR_PTR(ret);
6583         }
6584
6585         return &intel_fb->base;
6586 }
6587
6588 static const struct drm_mode_config_funcs intel_mode_funcs = {
6589         .fb_create = intel_user_framebuffer_create,
6590         .output_poll_changed = intel_fb_output_poll_changed,
6591 };
6592
6593 static struct drm_i915_gem_object *
6594 intel_alloc_context_page(struct drm_device *dev)
6595 {
6596         struct drm_i915_gem_object *ctx;
6597         int ret;
6598
6599         ctx = i915_gem_alloc_object(dev, 4096);
6600         if (!ctx) {
6601                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6602                 return NULL;
6603         }
6604
6605         mutex_lock(&dev->struct_mutex);
6606         ret = i915_gem_object_pin(ctx, 4096, true);
6607         if (ret) {
6608                 DRM_ERROR("failed to pin power context: %d\n", ret);
6609                 goto err_unref;
6610         }
6611
6612         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6613         if (ret) {
6614                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6615                 goto err_unpin;
6616         }
6617         mutex_unlock(&dev->struct_mutex);
6618
6619         return ctx;
6620
6621 err_unpin:
6622         i915_gem_object_unpin(ctx);
6623 err_unref:
6624         drm_gem_object_unreference(&ctx->base);
6625         mutex_unlock(&dev->struct_mutex);
6626         return NULL;
6627 }
6628
6629 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6630 {
6631         struct drm_i915_private *dev_priv = dev->dev_private;
6632         u16 rgvswctl;
6633
6634         rgvswctl = I915_READ16(MEMSWCTL);
6635         if (rgvswctl & MEMCTL_CMD_STS) {
6636                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6637                 return false; /* still busy with another command */
6638         }
6639
6640         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6641                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6642         I915_WRITE16(MEMSWCTL, rgvswctl);
6643         POSTING_READ16(MEMSWCTL);
6644
6645         rgvswctl |= MEMCTL_CMD_STS;
6646         I915_WRITE16(MEMSWCTL, rgvswctl);
6647
6648         return true;
6649 }
6650
6651 void ironlake_enable_drps(struct drm_device *dev)
6652 {
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654         u32 rgvmodectl = I915_READ(MEMMODECTL);
6655         u8 fmax, fmin, fstart, vstart;
6656
6657         /* Enable temp reporting */
6658         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6659         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6660
6661         /* 100ms RC evaluation intervals */
6662         I915_WRITE(RCUPEI, 100000);
6663         I915_WRITE(RCDNEI, 100000);
6664
6665         /* Set max/min thresholds to 90ms and 80ms respectively */
6666         I915_WRITE(RCBMAXAVG, 90000);
6667         I915_WRITE(RCBMINAVG, 80000);
6668
6669         I915_WRITE(MEMIHYST, 1);
6670
6671         /* Set up min, max, and cur for interrupt handling */
6672         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6673         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6674         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6675                 MEMMODE_FSTART_SHIFT;
6676
6677         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6678                 PXVFREQ_PX_SHIFT;
6679
6680         dev_priv->fmax = fmax; /* IPS callback will increase this */
6681         dev_priv->fstart = fstart;
6682
6683         dev_priv->max_delay = fstart;
6684         dev_priv->min_delay = fmin;
6685         dev_priv->cur_delay = fstart;
6686
6687         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6688                          fmax, fmin, fstart);
6689
6690         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6691
6692         /*
6693          * Interrupts will be enabled in ironlake_irq_postinstall
6694          */
6695
6696         I915_WRITE(VIDSTART, vstart);
6697         POSTING_READ(VIDSTART);
6698
6699         rgvmodectl |= MEMMODE_SWMODE_EN;
6700         I915_WRITE(MEMMODECTL, rgvmodectl);
6701
6702         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6703                 DRM_ERROR("stuck trying to change perf mode\n");
6704         msleep(1);
6705
6706         ironlake_set_drps(dev, fstart);
6707
6708         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6709                 I915_READ(0x112e0);
6710         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6711         dev_priv->last_count2 = I915_READ(0x112f4);
6712         getrawmonotonic(&dev_priv->last_time2);
6713 }
6714
6715 void ironlake_disable_drps(struct drm_device *dev)
6716 {
6717         struct drm_i915_private *dev_priv = dev->dev_private;
6718         u16 rgvswctl = I915_READ16(MEMSWCTL);
6719
6720         /* Ack interrupts, disable EFC interrupt */
6721         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6722         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6723         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6724         I915_WRITE(DEIIR, DE_PCU_EVENT);
6725         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6726
6727         /* Go back to the starting frequency */
6728         ironlake_set_drps(dev, dev_priv->fstart);
6729         msleep(1);
6730         rgvswctl |= MEMCTL_CMD_STS;
6731         I915_WRITE(MEMSWCTL, rgvswctl);
6732         msleep(1);
6733
6734 }
6735
6736 void gen6_set_rps(struct drm_device *dev, u8 val)
6737 {
6738         struct drm_i915_private *dev_priv = dev->dev_private;
6739         u32 swreq;
6740
6741         swreq = (val & 0x3ff) << 25;
6742         I915_WRITE(GEN6_RPNSWREQ, swreq);
6743 }
6744
6745 void gen6_disable_rps(struct drm_device *dev)
6746 {
6747         struct drm_i915_private *dev_priv = dev->dev_private;
6748
6749         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6750         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6751         I915_WRITE(GEN6_PMIER, 0);
6752         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6753 }
6754
6755 static unsigned long intel_pxfreq(u32 vidfreq)
6756 {
6757         unsigned long freq;
6758         int div = (vidfreq & 0x3f0000) >> 16;
6759         int post = (vidfreq & 0x3000) >> 12;
6760         int pre = (vidfreq & 0x7);
6761
6762         if (!pre)
6763                 return 0;
6764
6765         freq = ((div * 133333) / ((1<<post) * pre));
6766
6767         return freq;
6768 }
6769
6770 void intel_init_emon(struct drm_device *dev)
6771 {
6772         struct drm_i915_private *dev_priv = dev->dev_private;
6773         u32 lcfuse;
6774         u8 pxw[16];
6775         int i;
6776
6777         /* Disable to program */
6778         I915_WRITE(ECR, 0);
6779         POSTING_READ(ECR);
6780
6781         /* Program energy weights for various events */
6782         I915_WRITE(SDEW, 0x15040d00);
6783         I915_WRITE(CSIEW0, 0x007f0000);
6784         I915_WRITE(CSIEW1, 0x1e220004);
6785         I915_WRITE(CSIEW2, 0x04000004);
6786
6787         for (i = 0; i < 5; i++)
6788                 I915_WRITE(PEW + (i * 4), 0);
6789         for (i = 0; i < 3; i++)
6790                 I915_WRITE(DEW + (i * 4), 0);
6791
6792         /* Program P-state weights to account for frequency power adjustment */
6793         for (i = 0; i < 16; i++) {
6794                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6795                 unsigned long freq = intel_pxfreq(pxvidfreq);
6796                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6797                         PXVFREQ_PX_SHIFT;
6798                 unsigned long val;
6799
6800                 val = vid * vid;
6801                 val *= (freq / 1000);
6802                 val *= 255;
6803                 val /= (127*127*900);
6804                 if (val > 0xff)
6805                         DRM_ERROR("bad pxval: %ld\n", val);
6806                 pxw[i] = val;
6807         }
6808         /* Render standby states get 0 weight */
6809         pxw[14] = 0;
6810         pxw[15] = 0;
6811
6812         for (i = 0; i < 4; i++) {
6813                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6814                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6815                 I915_WRITE(PXW + (i * 4), val);
6816         }
6817
6818         /* Adjust magic regs to magic values (more experimental results) */
6819         I915_WRITE(OGW0, 0);
6820         I915_WRITE(OGW1, 0);
6821         I915_WRITE(EG0, 0x00007f00);
6822         I915_WRITE(EG1, 0x0000000e);
6823         I915_WRITE(EG2, 0x000e0000);
6824         I915_WRITE(EG3, 0x68000300);
6825         I915_WRITE(EG4, 0x42000000);
6826         I915_WRITE(EG5, 0x00140031);
6827         I915_WRITE(EG6, 0);
6828         I915_WRITE(EG7, 0);
6829
6830         for (i = 0; i < 8; i++)
6831                 I915_WRITE(PXWL + (i * 4), 0);
6832
6833         /* Enable PMON + select events */
6834         I915_WRITE(ECR, 0x80000019);
6835
6836         lcfuse = I915_READ(LCFUSE02);
6837
6838         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6839 }
6840
6841 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6842 {
6843         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6844         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6845         u32 pcu_mbox;
6846         int cur_freq, min_freq, max_freq;
6847         int i;
6848
6849         /* Here begins a magic sequence of register writes to enable
6850          * auto-downclocking.
6851          *
6852          * Perhaps there might be some value in exposing these to
6853          * userspace...
6854          */
6855         I915_WRITE(GEN6_RC_STATE, 0);
6856         __gen6_gt_force_wake_get(dev_priv);
6857
6858         /* disable the counters and set deterministic thresholds */
6859         I915_WRITE(GEN6_RC_CONTROL, 0);
6860
6861         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6862         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6863         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6864         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6865         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6866
6867         for (i = 0; i < I915_NUM_RINGS; i++)
6868                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6869
6870         I915_WRITE(GEN6_RC_SLEEP, 0);
6871         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6872         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6873         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6874         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6875
6876         I915_WRITE(GEN6_RC_CONTROL,
6877                    GEN6_RC_CTL_RC6p_ENABLE |
6878                    GEN6_RC_CTL_RC6_ENABLE |
6879                    GEN6_RC_CTL_EI_MODE(1) |
6880                    GEN6_RC_CTL_HW_ENABLE);
6881
6882         I915_WRITE(GEN6_RPNSWREQ,
6883                    GEN6_FREQUENCY(10) |
6884                    GEN6_OFFSET(0) |
6885                    GEN6_AGGRESSIVE_TURBO);
6886         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6887                    GEN6_FREQUENCY(12));
6888
6889         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6890         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6891                    18 << 24 |
6892                    6 << 16);
6893         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6894         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
6895         I915_WRITE(GEN6_RP_UP_EI, 100000);
6896         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
6897         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6898         I915_WRITE(GEN6_RP_CONTROL,
6899                    GEN6_RP_MEDIA_TURBO |
6900                    GEN6_RP_USE_NORMAL_FREQ |
6901                    GEN6_RP_MEDIA_IS_GFX |
6902                    GEN6_RP_ENABLE |
6903                    GEN6_RP_UP_BUSY_AVG |
6904                    GEN6_RP_DOWN_IDLE_CONT);
6905
6906         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6907                      500))
6908                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6909
6910         I915_WRITE(GEN6_PCODE_DATA, 0);
6911         I915_WRITE(GEN6_PCODE_MAILBOX,
6912                    GEN6_PCODE_READY |
6913                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6914         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6915                      500))
6916                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6917
6918         min_freq = (rp_state_cap & 0xff0000) >> 16;
6919         max_freq = rp_state_cap & 0xff;
6920         cur_freq = (gt_perf_status & 0xff00) >> 8;
6921
6922         /* Check for overclock support */
6923         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6924                      500))
6925                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6926         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6927         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6928         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6929                      500))
6930                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6931         if (pcu_mbox & (1<<31)) { /* OC supported */
6932                 max_freq = pcu_mbox & 0xff;
6933                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
6934         }
6935
6936         /* In units of 100MHz */
6937         dev_priv->max_delay = max_freq;
6938         dev_priv->min_delay = min_freq;
6939         dev_priv->cur_delay = cur_freq;
6940
6941         /* requires MSI enabled */
6942         I915_WRITE(GEN6_PMIER,
6943                    GEN6_PM_MBOX_EVENT |
6944                    GEN6_PM_THERMAL_EVENT |
6945                    GEN6_PM_RP_DOWN_TIMEOUT |
6946                    GEN6_PM_RP_UP_THRESHOLD |
6947                    GEN6_PM_RP_DOWN_THRESHOLD |
6948                    GEN6_PM_RP_UP_EI_EXPIRED |
6949                    GEN6_PM_RP_DOWN_EI_EXPIRED);
6950         I915_WRITE(GEN6_PMIMR, 0);
6951         /* enable all PM interrupts */
6952         I915_WRITE(GEN6_PMINTRMSK, 0);
6953
6954         __gen6_gt_force_wake_put(dev_priv);
6955 }
6956
6957 void intel_enable_clock_gating(struct drm_device *dev)
6958 {
6959         struct drm_i915_private *dev_priv = dev->dev_private;
6960         int pipe;
6961
6962         /*
6963          * Disable clock gating reported to work incorrectly according to the
6964          * specs, but enable as much else as we can.
6965          */
6966         if (HAS_PCH_SPLIT(dev)) {
6967                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6968
6969                 if (IS_GEN5(dev)) {
6970                         /* Required for FBC */
6971                         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6972                                 DPFCRUNIT_CLOCK_GATE_DISABLE |
6973                                 DPFDUNIT_CLOCK_GATE_DISABLE;
6974                         /* Required for CxSR */
6975                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6976
6977                         I915_WRITE(PCH_3DCGDIS0,
6978                                    MARIUNIT_CLOCK_GATE_DISABLE |
6979                                    SVSMUNIT_CLOCK_GATE_DISABLE);
6980                         I915_WRITE(PCH_3DCGDIS1,
6981                                    VFMUNIT_CLOCK_GATE_DISABLE);
6982                 }
6983
6984                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6985
6986                 /*
6987                  * On Ibex Peak and Cougar Point, we need to disable clock
6988                  * gating for the panel power sequencer or it will fail to
6989                  * start up when no ports are active.
6990                  */
6991                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6992
6993                 /*
6994                  * According to the spec the following bits should be set in
6995                  * order to enable memory self-refresh
6996                  * The bit 22/21 of 0x42004
6997                  * The bit 5 of 0x42020
6998                  * The bit 15 of 0x45000
6999                  */
7000                 if (IS_GEN5(dev)) {
7001                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7002                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
7003                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7004                         I915_WRITE(ILK_DSPCLK_GATE,
7005                                         (I915_READ(ILK_DSPCLK_GATE) |
7006                                                 ILK_DPARB_CLK_GATE));
7007                         I915_WRITE(DISP_ARB_CTL,
7008                                         (I915_READ(DISP_ARB_CTL) |
7009                                                 DISP_FBC_WM_DIS));
7010                         I915_WRITE(WM3_LP_ILK, 0);
7011                         I915_WRITE(WM2_LP_ILK, 0);
7012                         I915_WRITE(WM1_LP_ILK, 0);
7013                 }
7014                 /*
7015                  * Based on the document from hardware guys the following bits
7016                  * should be set unconditionally in order to enable FBC.
7017                  * The bit 22 of 0x42000
7018                  * The bit 22 of 0x42004
7019                  * The bit 7,8,9 of 0x42020.
7020                  */
7021                 if (IS_IRONLAKE_M(dev)) {
7022                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7023                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7024                                    ILK_FBCQ_DIS);
7025                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7026                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7027                                    ILK_DPARB_GATE);
7028                         I915_WRITE(ILK_DSPCLK_GATE,
7029                                    I915_READ(ILK_DSPCLK_GATE) |
7030                                    ILK_DPFC_DIS1 |
7031                                    ILK_DPFC_DIS2 |
7032                                    ILK_CLK_FBC);
7033                 }
7034
7035                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7036                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7037                            ILK_ELPIN_409_SELECT);
7038
7039                 if (IS_GEN5(dev)) {
7040                         I915_WRITE(_3D_CHICKEN2,
7041                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7042                                    _3D_CHICKEN2_WM_READ_PIPELINED);
7043                 }
7044
7045                 if (IS_GEN6(dev)) {
7046                         I915_WRITE(WM3_LP_ILK, 0);
7047                         I915_WRITE(WM2_LP_ILK, 0);
7048                         I915_WRITE(WM1_LP_ILK, 0);
7049
7050                         /*
7051                          * According to the spec the following bits should be
7052                          * set in order to enable memory self-refresh and fbc:
7053                          * The bit21 and bit22 of 0x42000
7054                          * The bit21 and bit22 of 0x42004
7055                          * The bit5 and bit7 of 0x42020
7056                          * The bit14 of 0x70180
7057                          * The bit14 of 0x71180
7058                          */
7059                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7060                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7061                                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7062                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7063                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7064                                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7065                         I915_WRITE(ILK_DSPCLK_GATE,
7066                                    I915_READ(ILK_DSPCLK_GATE) |
7067                                    ILK_DPARB_CLK_GATE  |
7068                                    ILK_DPFD_CLK_GATE);
7069
7070                         for_each_pipe(pipe)
7071                                 I915_WRITE(DSPCNTR(pipe),
7072                                            I915_READ(DSPCNTR(pipe)) |
7073                                            DISPPLANE_TRICKLE_FEED_DISABLE);
7074                 }
7075         } else if (IS_G4X(dev)) {
7076                 uint32_t dspclk_gate;
7077                 I915_WRITE(RENCLK_GATE_D1, 0);
7078                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7079                        GS_UNIT_CLOCK_GATE_DISABLE |
7080                        CL_UNIT_CLOCK_GATE_DISABLE);
7081                 I915_WRITE(RAMCLK_GATE_D, 0);
7082                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7083                         OVRUNIT_CLOCK_GATE_DISABLE |
7084                         OVCUNIT_CLOCK_GATE_DISABLE;
7085                 if (IS_GM45(dev))
7086                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7087                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7088         } else if (IS_CRESTLINE(dev)) {
7089                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7090                 I915_WRITE(RENCLK_GATE_D2, 0);
7091                 I915_WRITE(DSPCLK_GATE_D, 0);
7092                 I915_WRITE(RAMCLK_GATE_D, 0);
7093                 I915_WRITE16(DEUC, 0);
7094         } else if (IS_BROADWATER(dev)) {
7095                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7096                        I965_RCC_CLOCK_GATE_DISABLE |
7097                        I965_RCPB_CLOCK_GATE_DISABLE |
7098                        I965_ISC_CLOCK_GATE_DISABLE |
7099                        I965_FBC_CLOCK_GATE_DISABLE);
7100                 I915_WRITE(RENCLK_GATE_D2, 0);
7101         } else if (IS_GEN3(dev)) {
7102                 u32 dstate = I915_READ(D_STATE);
7103
7104                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7105                         DSTATE_DOT_CLOCK_GATING;
7106                 I915_WRITE(D_STATE, dstate);
7107         } else if (IS_I85X(dev) || IS_I865G(dev)) {
7108                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7109         } else if (IS_I830(dev)) {
7110                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7111         }
7112 }
7113
7114 static void ironlake_teardown_rc6(struct drm_device *dev)
7115 {
7116         struct drm_i915_private *dev_priv = dev->dev_private;
7117
7118         if (dev_priv->renderctx) {
7119                 i915_gem_object_unpin(dev_priv->renderctx);
7120                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7121                 dev_priv->renderctx = NULL;
7122         }
7123
7124         if (dev_priv->pwrctx) {
7125                 i915_gem_object_unpin(dev_priv->pwrctx);
7126                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7127                 dev_priv->pwrctx = NULL;
7128         }
7129 }
7130
7131 static void ironlake_disable_rc6(struct drm_device *dev)
7132 {
7133         struct drm_i915_private *dev_priv = dev->dev_private;
7134
7135         if (I915_READ(PWRCTXA)) {
7136                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7137                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7138                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7139                          50);
7140
7141                 I915_WRITE(PWRCTXA, 0);
7142                 POSTING_READ(PWRCTXA);
7143
7144                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7145                 POSTING_READ(RSTDBYCTL);
7146         }
7147
7148         ironlake_teardown_rc6(dev);
7149 }
7150
7151 static int ironlake_setup_rc6(struct drm_device *dev)
7152 {
7153         struct drm_i915_private *dev_priv = dev->dev_private;
7154
7155         if (dev_priv->renderctx == NULL)
7156                 dev_priv->renderctx = intel_alloc_context_page(dev);
7157         if (!dev_priv->renderctx)
7158                 return -ENOMEM;
7159
7160         if (dev_priv->pwrctx == NULL)
7161                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7162         if (!dev_priv->pwrctx) {
7163                 ironlake_teardown_rc6(dev);
7164                 return -ENOMEM;
7165         }
7166
7167         return 0;
7168 }
7169
7170 void ironlake_enable_rc6(struct drm_device *dev)
7171 {
7172         struct drm_i915_private *dev_priv = dev->dev_private;
7173         int ret;
7174
7175         /* rc6 disabled by default due to repeated reports of hanging during
7176          * boot and resume.
7177          */
7178         if (!i915_enable_rc6)
7179                 return;
7180
7181         ret = ironlake_setup_rc6(dev);
7182         if (ret)
7183                 return;
7184
7185         /*
7186          * GPU can automatically power down the render unit if given a page
7187          * to save state.
7188          */
7189         ret = BEGIN_LP_RING(6);
7190         if (ret) {
7191                 ironlake_teardown_rc6(dev);
7192                 return;
7193         }
7194
7195         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7196         OUT_RING(MI_SET_CONTEXT);
7197         OUT_RING(dev_priv->renderctx->gtt_offset |
7198                  MI_MM_SPACE_GTT |
7199                  MI_SAVE_EXT_STATE_EN |
7200                  MI_RESTORE_EXT_STATE_EN |
7201                  MI_RESTORE_INHIBIT);
7202         OUT_RING(MI_SUSPEND_FLUSH);
7203         OUT_RING(MI_NOOP);
7204         OUT_RING(MI_FLUSH);
7205         ADVANCE_LP_RING();
7206
7207         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7208         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7209 }
7210
7211
7212 /* Set up chip specific display functions */
7213 static void intel_init_display(struct drm_device *dev)
7214 {
7215         struct drm_i915_private *dev_priv = dev->dev_private;
7216
7217         /* We always want a DPMS function */
7218         if (HAS_PCH_SPLIT(dev))
7219                 dev_priv->display.dpms = ironlake_crtc_dpms;
7220         else
7221                 dev_priv->display.dpms = i9xx_crtc_dpms;
7222
7223         if (I915_HAS_FBC(dev)) {
7224                 if (HAS_PCH_SPLIT(dev)) {
7225                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7226                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7227                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7228                 } else if (IS_GM45(dev)) {
7229                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7230                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7231                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7232                 } else if (IS_CRESTLINE(dev)) {
7233                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7234                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7235                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7236                 }
7237                 /* 855GM needs testing */
7238         }
7239
7240         /* Returns the core display clock speed */
7241         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7242                 dev_priv->display.get_display_clock_speed =
7243                         i945_get_display_clock_speed;
7244         else if (IS_I915G(dev))
7245                 dev_priv->display.get_display_clock_speed =
7246                         i915_get_display_clock_speed;
7247         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7248                 dev_priv->display.get_display_clock_speed =
7249                         i9xx_misc_get_display_clock_speed;
7250         else if (IS_I915GM(dev))
7251                 dev_priv->display.get_display_clock_speed =
7252                         i915gm_get_display_clock_speed;
7253         else if (IS_I865G(dev))
7254                 dev_priv->display.get_display_clock_speed =
7255                         i865_get_display_clock_speed;
7256         else if (IS_I85X(dev))
7257                 dev_priv->display.get_display_clock_speed =
7258                         i855_get_display_clock_speed;
7259         else /* 852, 830 */
7260                 dev_priv->display.get_display_clock_speed =
7261                         i830_get_display_clock_speed;
7262
7263         /* For FIFO watermark updates */
7264         if (HAS_PCH_SPLIT(dev)) {
7265                 if (IS_GEN5(dev)) {
7266                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7267                                 dev_priv->display.update_wm = ironlake_update_wm;
7268                         else {
7269                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7270                                               "Disable CxSR\n");
7271                                 dev_priv->display.update_wm = NULL;
7272                         }
7273                 } else if (IS_GEN6(dev)) {
7274                         if (SNB_READ_WM0_LATENCY()) {
7275                                 dev_priv->display.update_wm = sandybridge_update_wm;
7276                         } else {
7277                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7278                                               "Disable CxSR\n");
7279                                 dev_priv->display.update_wm = NULL;
7280                         }
7281                 } else
7282                         dev_priv->display.update_wm = NULL;
7283         } else if (IS_PINEVIEW(dev)) {
7284                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7285                                             dev_priv->is_ddr3,
7286                                             dev_priv->fsb_freq,
7287                                             dev_priv->mem_freq)) {
7288                         DRM_INFO("failed to find known CxSR latency "
7289                                  "(found ddr%s fsb freq %d, mem freq %d), "
7290                                  "disabling CxSR\n",
7291                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7292                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7293                         /* Disable CxSR and never update its watermark again */
7294                         pineview_disable_cxsr(dev);
7295                         dev_priv->display.update_wm = NULL;
7296                 } else
7297                         dev_priv->display.update_wm = pineview_update_wm;
7298         } else if (IS_G4X(dev))
7299                 dev_priv->display.update_wm = g4x_update_wm;
7300         else if (IS_GEN4(dev))
7301                 dev_priv->display.update_wm = i965_update_wm;
7302         else if (IS_GEN3(dev)) {
7303                 dev_priv->display.update_wm = i9xx_update_wm;
7304                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7305         } else if (IS_I85X(dev)) {
7306                 dev_priv->display.update_wm = i9xx_update_wm;
7307                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7308         } else {
7309                 dev_priv->display.update_wm = i830_update_wm;
7310                 if (IS_845G(dev))
7311                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7312                 else
7313                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7314         }
7315 }
7316
7317 /*
7318  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7319  * resume, or other times.  This quirk makes sure that's the case for
7320  * affected systems.
7321  */
7322 static void quirk_pipea_force (struct drm_device *dev)
7323 {
7324         struct drm_i915_private *dev_priv = dev->dev_private;
7325
7326         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7327         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7328 }
7329
7330 struct intel_quirk {
7331         int device;
7332         int subsystem_vendor;
7333         int subsystem_device;
7334         void (*hook)(struct drm_device *dev);
7335 };
7336
7337 struct intel_quirk intel_quirks[] = {
7338         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7339         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7340         /* HP Mini needs pipe A force quirk (LP: #322104) */
7341         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7342
7343         /* Thinkpad R31 needs pipe A force quirk */
7344         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7345         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7346         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7347
7348         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7349         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7350         /* ThinkPad X40 needs pipe A force quirk */
7351
7352         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7353         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7354
7355         /* 855 & before need to leave pipe A & dpll A up */
7356         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7357         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7358 };
7359
7360 static void intel_init_quirks(struct drm_device *dev)
7361 {
7362         struct pci_dev *d = dev->pdev;
7363         int i;
7364
7365         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7366                 struct intel_quirk *q = &intel_quirks[i];
7367
7368                 if (d->device == q->device &&
7369                     (d->subsystem_vendor == q->subsystem_vendor ||
7370                      q->subsystem_vendor == PCI_ANY_ID) &&
7371                     (d->subsystem_device == q->subsystem_device ||
7372                      q->subsystem_device == PCI_ANY_ID))
7373                         q->hook(dev);
7374         }
7375 }
7376
7377 /* Disable the VGA plane that we never use */
7378 static void i915_disable_vga(struct drm_device *dev)
7379 {
7380         struct drm_i915_private *dev_priv = dev->dev_private;
7381         u8 sr1;
7382         u32 vga_reg;
7383
7384         if (HAS_PCH_SPLIT(dev))
7385                 vga_reg = CPU_VGACNTRL;
7386         else
7387                 vga_reg = VGACNTRL;
7388
7389         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7390         outb(1, VGA_SR_INDEX);
7391         sr1 = inb(VGA_SR_DATA);
7392         outb(sr1 | 1<<5, VGA_SR_DATA);
7393         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7394         udelay(300);
7395
7396         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7397         POSTING_READ(vga_reg);
7398 }
7399
7400 void intel_modeset_init(struct drm_device *dev)
7401 {
7402         struct drm_i915_private *dev_priv = dev->dev_private;
7403         int i;
7404
7405         drm_mode_config_init(dev);
7406
7407         dev->mode_config.min_width = 0;
7408         dev->mode_config.min_height = 0;
7409
7410         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7411
7412         intel_init_quirks(dev);
7413
7414         intel_init_display(dev);
7415
7416         if (IS_GEN2(dev)) {
7417                 dev->mode_config.max_width = 2048;
7418                 dev->mode_config.max_height = 2048;
7419         } else if (IS_GEN3(dev)) {
7420                 dev->mode_config.max_width = 4096;
7421                 dev->mode_config.max_height = 4096;
7422         } else {
7423                 dev->mode_config.max_width = 8192;
7424                 dev->mode_config.max_height = 8192;
7425         }
7426         dev->mode_config.fb_base = dev->agp->base;
7427
7428         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7429                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7430
7431         for (i = 0; i < dev_priv->num_pipe; i++) {
7432                 intel_crtc_init(dev, i);
7433         }
7434
7435         intel_setup_outputs(dev);
7436
7437         intel_enable_clock_gating(dev);
7438
7439         /* Just disable it once at startup */
7440         i915_disable_vga(dev);
7441
7442         if (IS_IRONLAKE_M(dev)) {
7443                 ironlake_enable_drps(dev);
7444                 intel_init_emon(dev);
7445         }
7446
7447         if (IS_GEN6(dev))
7448                 gen6_enable_rps(dev_priv);
7449
7450         if (IS_IRONLAKE_M(dev))
7451                 ironlake_enable_rc6(dev);
7452
7453         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7454         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7455                     (unsigned long)dev);
7456
7457         intel_setup_overlay(dev);
7458 }
7459
7460 void intel_modeset_cleanup(struct drm_device *dev)
7461 {
7462         struct drm_i915_private *dev_priv = dev->dev_private;
7463         struct drm_crtc *crtc;
7464         struct intel_crtc *intel_crtc;
7465
7466         drm_kms_helper_poll_fini(dev);
7467         mutex_lock(&dev->struct_mutex);
7468
7469         intel_unregister_dsm_handler();
7470
7471
7472         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7473                 /* Skip inactive CRTCs */
7474                 if (!crtc->fb)
7475                         continue;
7476
7477                 intel_crtc = to_intel_crtc(crtc);
7478                 intel_increase_pllclock(crtc);
7479         }
7480
7481         if (dev_priv->display.disable_fbc)
7482                 dev_priv->display.disable_fbc(dev);
7483
7484         if (IS_IRONLAKE_M(dev))
7485                 ironlake_disable_drps(dev);
7486         if (IS_GEN6(dev))
7487                 gen6_disable_rps(dev);
7488
7489         if (IS_IRONLAKE_M(dev))
7490                 ironlake_disable_rc6(dev);
7491
7492         mutex_unlock(&dev->struct_mutex);
7493
7494         /* Disable the irq before mode object teardown, for the irq might
7495          * enqueue unpin/hotplug work. */
7496         drm_irq_uninstall(dev);
7497         cancel_work_sync(&dev_priv->hotplug_work);
7498
7499         /* Shut off idle work before the crtcs get freed. */
7500         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7501                 intel_crtc = to_intel_crtc(crtc);
7502                 del_timer_sync(&intel_crtc->idle_timer);
7503         }
7504         del_timer_sync(&dev_priv->idle_timer);
7505         cancel_work_sync(&dev_priv->idle_work);
7506
7507         drm_mode_config_cleanup(dev);
7508 }
7509
7510 /*
7511  * Return which encoder is currently attached for connector.
7512  */
7513 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7514 {
7515         return &intel_attached_encoder(connector)->base;
7516 }
7517
7518 void intel_connector_attach_encoder(struct intel_connector *connector,
7519                                     struct intel_encoder *encoder)
7520 {
7521         connector->encoder = encoder;
7522         drm_mode_connector_attach_encoder(&connector->base,
7523                                           &encoder->base);
7524 }
7525
7526 /*
7527  * set vga decode state - true == enable VGA decode
7528  */
7529 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7530 {
7531         struct drm_i915_private *dev_priv = dev->dev_private;
7532         u16 gmch_ctrl;
7533
7534         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7535         if (state)
7536                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7537         else
7538                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7539         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7540         return 0;
7541 }
7542
7543 #ifdef CONFIG_DEBUG_FS
7544 #include <linux/seq_file.h>
7545
7546 struct intel_display_error_state {
7547         struct intel_cursor_error_state {
7548                 u32 control;
7549                 u32 position;
7550                 u32 base;
7551                 u32 size;
7552         } cursor[2];
7553
7554         struct intel_pipe_error_state {
7555                 u32 conf;
7556                 u32 source;
7557
7558                 u32 htotal;
7559                 u32 hblank;
7560                 u32 hsync;
7561                 u32 vtotal;
7562                 u32 vblank;
7563                 u32 vsync;
7564         } pipe[2];
7565
7566         struct intel_plane_error_state {
7567                 u32 control;
7568                 u32 stride;
7569                 u32 size;
7570                 u32 pos;
7571                 u32 addr;
7572                 u32 surface;
7573                 u32 tile_offset;
7574         } plane[2];
7575 };
7576
7577 struct intel_display_error_state *
7578 intel_display_capture_error_state(struct drm_device *dev)
7579 {
7580         drm_i915_private_t *dev_priv = dev->dev_private;
7581         struct intel_display_error_state *error;
7582         int i;
7583
7584         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7585         if (error == NULL)
7586                 return NULL;
7587
7588         for (i = 0; i < 2; i++) {
7589                 error->cursor[i].control = I915_READ(CURCNTR(i));
7590                 error->cursor[i].position = I915_READ(CURPOS(i));
7591                 error->cursor[i].base = I915_READ(CURBASE(i));
7592
7593                 error->plane[i].control = I915_READ(DSPCNTR(i));
7594                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7595                 error->plane[i].size = I915_READ(DSPSIZE(i));
7596                 error->plane[i].pos= I915_READ(DSPPOS(i));
7597                 error->plane[i].addr = I915_READ(DSPADDR(i));
7598                 if (INTEL_INFO(dev)->gen >= 4) {
7599                         error->plane[i].surface = I915_READ(DSPSURF(i));
7600                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7601                 }
7602
7603                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7604                 error->pipe[i].source = I915_READ(PIPESRC(i));
7605                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7606                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7607                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7608                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7609                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7610                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7611         }
7612
7613         return error;
7614 }
7615
7616 void
7617 intel_display_print_error_state(struct seq_file *m,
7618                                 struct drm_device *dev,
7619                                 struct intel_display_error_state *error)
7620 {
7621         int i;
7622
7623         for (i = 0; i < 2; i++) {
7624                 seq_printf(m, "Pipe [%d]:\n", i);
7625                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7626                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7627                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7628                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7629                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7630                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7631                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7632                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7633
7634                 seq_printf(m, "Plane [%d]:\n", i);
7635                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7636                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7637                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7638                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7639                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7640                 if (INTEL_INFO(dev)->gen >= 4) {
7641                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7642                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7643                 }
7644
7645                 seq_printf(m, "Cursor [%d]:\n", i);
7646                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7647                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7648                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7649         }
7650 }
7651 #endif