drm/radeon/kms: add thermal chip quirk for asus 9600xt
[pandora-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include "drmP.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include "drm_dp_helper.h"
40
41 #include "drm_crtc_helper.h"
42
43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
46 static void intel_update_watermarks(struct drm_device *dev);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51     /* given values */
52     int n;
53     int m1, m2;
54     int p1, p2;
55     /* derived values */
56     int dot;
57     int vco;
58     int m;
59     int p;
60 } intel_clock_t;
61
62 typedef struct {
63     int min, max;
64 } intel_range_t;
65
66 typedef struct {
67     int dot_limit;
68     int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM                  2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
75     intel_p2_t      p2;
76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77                       int, int, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85                     int target, int refclk, intel_clock_t *best_clock);
86 static bool
87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88                         int target, int refclk, intel_clock_t *best_clock);
89
90 static bool
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92                       int target, int refclk, intel_clock_t *best_clock);
93 static bool
94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95                            int target, int refclk, intel_clock_t *best_clock);
96
97 static inline u32 /* units of 100MHz */
98 intel_fdi_link_freq(struct drm_device *dev)
99 {
100         if (IS_GEN5(dev)) {
101                 struct drm_i915_private *dev_priv = dev->dev_private;
102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103         } else
104                 return 27;
105 }
106
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108         .dot = { .min = 25000, .max = 350000 },
109         .vco = { .min = 930000, .max = 1400000 },
110         .n = { .min = 3, .max = 16 },
111         .m = { .min = 96, .max = 140 },
112         .m1 = { .min = 18, .max = 26 },
113         .m2 = { .min = 6, .max = 16 },
114         .p = { .min = 4, .max = 128 },
115         .p1 = { .min = 2, .max = 33 },
116         .p2 = { .dot_limit = 165000,
117                 .p2_slow = 4, .p2_fast = 2 },
118         .find_pll = intel_find_best_PLL,
119 };
120
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122         .dot = { .min = 25000, .max = 350000 },
123         .vco = { .min = 930000, .max = 1400000 },
124         .n = { .min = 3, .max = 16 },
125         .m = { .min = 96, .max = 140 },
126         .m1 = { .min = 18, .max = 26 },
127         .m2 = { .min = 6, .max = 16 },
128         .p = { .min = 4, .max = 128 },
129         .p1 = { .min = 1, .max = 6 },
130         .p2 = { .dot_limit = 165000,
131                 .p2_slow = 14, .p2_fast = 7 },
132         .find_pll = intel_find_best_PLL,
133 };
134
135 static const intel_limit_t intel_limits_i9xx_sdvo = {
136         .dot = { .min = 20000, .max = 400000 },
137         .vco = { .min = 1400000, .max = 2800000 },
138         .n = { .min = 1, .max = 6 },
139         .m = { .min = 70, .max = 120 },
140         .m1 = { .min = 10, .max = 22 },
141         .m2 = { .min = 5, .max = 9 },
142         .p = { .min = 5, .max = 80 },
143         .p1 = { .min = 1, .max = 8 },
144         .p2 = { .dot_limit = 200000,
145                 .p2_slow = 10, .p2_fast = 5 },
146         .find_pll = intel_find_best_PLL,
147 };
148
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150         .dot = { .min = 20000, .max = 400000 },
151         .vco = { .min = 1400000, .max = 2800000 },
152         .n = { .min = 1, .max = 6 },
153         .m = { .min = 70, .max = 120 },
154         .m1 = { .min = 10, .max = 22 },
155         .m2 = { .min = 5, .max = 9 },
156         .p = { .min = 7, .max = 98 },
157         .p1 = { .min = 1, .max = 8 },
158         .p2 = { .dot_limit = 112000,
159                 .p2_slow = 14, .p2_fast = 7 },
160         .find_pll = intel_find_best_PLL,
161 };
162
163
164 static const intel_limit_t intel_limits_g4x_sdvo = {
165         .dot = { .min = 25000, .max = 270000 },
166         .vco = { .min = 1750000, .max = 3500000},
167         .n = { .min = 1, .max = 4 },
168         .m = { .min = 104, .max = 138 },
169         .m1 = { .min = 17, .max = 23 },
170         .m2 = { .min = 5, .max = 11 },
171         .p = { .min = 10, .max = 30 },
172         .p1 = { .min = 1, .max = 3},
173         .p2 = { .dot_limit = 270000,
174                 .p2_slow = 10,
175                 .p2_fast = 10
176         },
177         .find_pll = intel_g4x_find_best_PLL,
178 };
179
180 static const intel_limit_t intel_limits_g4x_hdmi = {
181         .dot = { .min = 22000, .max = 400000 },
182         .vco = { .min = 1750000, .max = 3500000},
183         .n = { .min = 1, .max = 4 },
184         .m = { .min = 104, .max = 138 },
185         .m1 = { .min = 16, .max = 23 },
186         .m2 = { .min = 5, .max = 11 },
187         .p = { .min = 5, .max = 80 },
188         .p1 = { .min = 1, .max = 8},
189         .p2 = { .dot_limit = 165000,
190                 .p2_slow = 10, .p2_fast = 5 },
191         .find_pll = intel_g4x_find_best_PLL,
192 };
193
194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
195         .dot = { .min = 20000, .max = 115000 },
196         .vco = { .min = 1750000, .max = 3500000 },
197         .n = { .min = 1, .max = 3 },
198         .m = { .min = 104, .max = 138 },
199         .m1 = { .min = 17, .max = 23 },
200         .m2 = { .min = 5, .max = 11 },
201         .p = { .min = 28, .max = 112 },
202         .p1 = { .min = 2, .max = 8 },
203         .p2 = { .dot_limit = 0,
204                 .p2_slow = 14, .p2_fast = 14
205         },
206         .find_pll = intel_g4x_find_best_PLL,
207 };
208
209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
210         .dot = { .min = 80000, .max = 224000 },
211         .vco = { .min = 1750000, .max = 3500000 },
212         .n = { .min = 1, .max = 3 },
213         .m = { .min = 104, .max = 138 },
214         .m1 = { .min = 17, .max = 23 },
215         .m2 = { .min = 5, .max = 11 },
216         .p = { .min = 14, .max = 42 },
217         .p1 = { .min = 2, .max = 6 },
218         .p2 = { .dot_limit = 0,
219                 .p2_slow = 7, .p2_fast = 7
220         },
221         .find_pll = intel_g4x_find_best_PLL,
222 };
223
224 static const intel_limit_t intel_limits_g4x_display_port = {
225         .dot = { .min = 161670, .max = 227000 },
226         .vco = { .min = 1750000, .max = 3500000},
227         .n = { .min = 1, .max = 2 },
228         .m = { .min = 97, .max = 108 },
229         .m1 = { .min = 0x10, .max = 0x12 },
230         .m2 = { .min = 0x05, .max = 0x06 },
231         .p = { .min = 10, .max = 20 },
232         .p1 = { .min = 1, .max = 2},
233         .p2 = { .dot_limit = 0,
234                 .p2_slow = 10, .p2_fast = 10 },
235         .find_pll = intel_find_pll_g4x_dp,
236 };
237
238 static const intel_limit_t intel_limits_pineview_sdvo = {
239         .dot = { .min = 20000, .max = 400000},
240         .vco = { .min = 1700000, .max = 3500000 },
241         /* Pineview's Ncounter is a ring counter */
242         .n = { .min = 3, .max = 6 },
243         .m = { .min = 2, .max = 256 },
244         /* Pineview only has one combined m divider, which we treat as m2. */
245         .m1 = { .min = 0, .max = 0 },
246         .m2 = { .min = 0, .max = 254 },
247         .p = { .min = 5, .max = 80 },
248         .p1 = { .min = 1, .max = 8 },
249         .p2 = { .dot_limit = 200000,
250                 .p2_slow = 10, .p2_fast = 5 },
251         .find_pll = intel_find_best_PLL,
252 };
253
254 static const intel_limit_t intel_limits_pineview_lvds = {
255         .dot = { .min = 20000, .max = 400000 },
256         .vco = { .min = 1700000, .max = 3500000 },
257         .n = { .min = 3, .max = 6 },
258         .m = { .min = 2, .max = 256 },
259         .m1 = { .min = 0, .max = 0 },
260         .m2 = { .min = 0, .max = 254 },
261         .p = { .min = 7, .max = 112 },
262         .p1 = { .min = 1, .max = 8 },
263         .p2 = { .dot_limit = 112000,
264                 .p2_slow = 14, .p2_fast = 14 },
265         .find_pll = intel_find_best_PLL,
266 };
267
268 /* Ironlake / Sandybridge
269  *
270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
271  * the range value for them is (actual_value - 2).
272  */
273 static const intel_limit_t intel_limits_ironlake_dac = {
274         .dot = { .min = 25000, .max = 350000 },
275         .vco = { .min = 1760000, .max = 3510000 },
276         .n = { .min = 1, .max = 5 },
277         .m = { .min = 79, .max = 127 },
278         .m1 = { .min = 12, .max = 22 },
279         .m2 = { .min = 5, .max = 9 },
280         .p = { .min = 5, .max = 80 },
281         .p1 = { .min = 1, .max = 8 },
282         .p2 = { .dot_limit = 225000,
283                 .p2_slow = 10, .p2_fast = 5 },
284         .find_pll = intel_g4x_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
288         .dot = { .min = 25000, .max = 350000 },
289         .vco = { .min = 1760000, .max = 3510000 },
290         .n = { .min = 1, .max = 3 },
291         .m = { .min = 79, .max = 118 },
292         .m1 = { .min = 12, .max = 22 },
293         .m2 = { .min = 5, .max = 9 },
294         .p = { .min = 28, .max = 112 },
295         .p1 = { .min = 2, .max = 8 },
296         .p2 = { .dot_limit = 225000,
297                 .p2_slow = 14, .p2_fast = 14 },
298         .find_pll = intel_g4x_find_best_PLL,
299 };
300
301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
302         .dot = { .min = 25000, .max = 350000 },
303         .vco = { .min = 1760000, .max = 3510000 },
304         .n = { .min = 1, .max = 3 },
305         .m = { .min = 79, .max = 127 },
306         .m1 = { .min = 12, .max = 22 },
307         .m2 = { .min = 5, .max = 9 },
308         .p = { .min = 14, .max = 56 },
309         .p1 = { .min = 2, .max = 8 },
310         .p2 = { .dot_limit = 225000,
311                 .p2_slow = 7, .p2_fast = 7 },
312         .find_pll = intel_g4x_find_best_PLL,
313 };
314
315 /* LVDS 100mhz refclk limits. */
316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
317         .dot = { .min = 25000, .max = 350000 },
318         .vco = { .min = 1760000, .max = 3510000 },
319         .n = { .min = 1, .max = 2 },
320         .m = { .min = 79, .max = 126 },
321         .m1 = { .min = 12, .max = 22 },
322         .m2 = { .min = 5, .max = 9 },
323         .p = { .min = 28, .max = 112 },
324         .p1 = { .min = 2,.max = 8 },
325         .p2 = { .dot_limit = 225000,
326                 .p2_slow = 14, .p2_fast = 14 },
327         .find_pll = intel_g4x_find_best_PLL,
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
331         .dot = { .min = 25000, .max = 350000 },
332         .vco = { .min = 1760000, .max = 3510000 },
333         .n = { .min = 1, .max = 3 },
334         .m = { .min = 79, .max = 126 },
335         .m1 = { .min = 12, .max = 22 },
336         .m2 = { .min = 5, .max = 9 },
337         .p = { .min = 14, .max = 42 },
338         .p1 = { .min = 2,.max = 6 },
339         .p2 = { .dot_limit = 225000,
340                 .p2_slow = 7, .p2_fast = 7 },
341         .find_pll = intel_g4x_find_best_PLL,
342 };
343
344 static const intel_limit_t intel_limits_ironlake_display_port = {
345         .dot = { .min = 25000, .max = 350000 },
346         .vco = { .min = 1760000, .max = 3510000},
347         .n = { .min = 1, .max = 2 },
348         .m = { .min = 81, .max = 90 },
349         .m1 = { .min = 12, .max = 22 },
350         .m2 = { .min = 5, .max = 9 },
351         .p = { .min = 10, .max = 20 },
352         .p1 = { .min = 1, .max = 2},
353         .p2 = { .dot_limit = 0,
354                 .p2_slow = 10, .p2_fast = 10 },
355         .find_pll = intel_find_pll_ironlake_dp,
356 };
357
358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359                                                 int refclk)
360 {
361         struct drm_device *dev = crtc->dev;
362         struct drm_i915_private *dev_priv = dev->dev_private;
363         const intel_limit_t *limit;
364
365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367                     LVDS_CLKB_POWER_UP) {
368                         /* LVDS dual channel */
369                         if (refclk == 100000)
370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
371                         else
372                                 limit = &intel_limits_ironlake_dual_lvds;
373                 } else {
374                         if (refclk == 100000)
375                                 limit = &intel_limits_ironlake_single_lvds_100m;
376                         else
377                                 limit = &intel_limits_ironlake_single_lvds;
378                 }
379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
380                         HAS_eDP)
381                 limit = &intel_limits_ironlake_display_port;
382         else
383                 limit = &intel_limits_ironlake_dac;
384
385         return limit;
386 }
387
388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389 {
390         struct drm_device *dev = crtc->dev;
391         struct drm_i915_private *dev_priv = dev->dev_private;
392         const intel_limit_t *limit;
393
394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396                     LVDS_CLKB_POWER_UP)
397                         /* LVDS with dual channel */
398                         limit = &intel_limits_g4x_dual_channel_lvds;
399                 else
400                         /* LVDS with dual channel */
401                         limit = &intel_limits_g4x_single_channel_lvds;
402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
404                 limit = &intel_limits_g4x_hdmi;
405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406                 limit = &intel_limits_g4x_sdvo;
407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408                 limit = &intel_limits_g4x_display_port;
409         } else /* The option is for other outputs */
410                 limit = &intel_limits_i9xx_sdvo;
411
412         return limit;
413 }
414
415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
416 {
417         struct drm_device *dev = crtc->dev;
418         const intel_limit_t *limit;
419
420         if (HAS_PCH_SPLIT(dev))
421                 limit = intel_ironlake_limit(crtc, refclk);
422         else if (IS_G4X(dev)) {
423                 limit = intel_g4x_limit(crtc);
424         } else if (IS_PINEVIEW(dev)) {
425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
426                         limit = &intel_limits_pineview_lvds;
427                 else
428                         limit = &intel_limits_pineview_sdvo;
429         } else if (!IS_GEN2(dev)) {
430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431                         limit = &intel_limits_i9xx_lvds;
432                 else
433                         limit = &intel_limits_i9xx_sdvo;
434         } else {
435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436                         limit = &intel_limits_i8xx_lvds;
437                 else
438                         limit = &intel_limits_i8xx_dvo;
439         }
440         return limit;
441 }
442
443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
444 static void pineview_clock(int refclk, intel_clock_t *clock)
445 {
446         clock->m = clock->m2 + 2;
447         clock->p = clock->p1 * clock->p2;
448         clock->vco = refclk * clock->m / clock->n;
449         clock->dot = clock->vco / clock->p;
450 }
451
452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453 {
454         if (IS_PINEVIEW(dev)) {
455                 pineview_clock(refclk, clock);
456                 return;
457         }
458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459         clock->p = clock->p1 * clock->p2;
460         clock->vco = refclk * clock->m / (clock->n + 2);
461         clock->dot = clock->vco / clock->p;
462 }
463
464 /**
465  * Returns whether any output on the specified pipe is of the specified type
466  */
467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
468 {
469         struct drm_device *dev = crtc->dev;
470         struct drm_mode_config *mode_config = &dev->mode_config;
471         struct intel_encoder *encoder;
472
473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474                 if (encoder->base.crtc == crtc && encoder->type == type)
475                         return true;
476
477         return false;
478 }
479
480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
481 /**
482  * Returns whether the given set of divisors are valid for a given refclk with
483  * the given connectors.
484  */
485
486 static bool intel_PLL_is_valid(struct drm_device *dev,
487                                const intel_limit_t *limit,
488                                const intel_clock_t *clock)
489 {
490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
491                 INTELPllInvalid ("p1 out of range\n");
492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
493                 INTELPllInvalid ("p out of range\n");
494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
495                 INTELPllInvalid ("m2 out of range\n");
496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
497                 INTELPllInvalid ("m1 out of range\n");
498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499                 INTELPllInvalid ("m1 <= m2\n");
500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
501                 INTELPllInvalid ("m out of range\n");
502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
503                 INTELPllInvalid ("n out of range\n");
504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505                 INTELPllInvalid ("vco out of range\n");
506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507          * connector, etc., rather than just a single range.
508          */
509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510                 INTELPllInvalid ("dot out of range\n");
511
512         return true;
513 }
514
515 static bool
516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517                     int target, int refclk, intel_clock_t *best_clock)
518
519 {
520         struct drm_device *dev = crtc->dev;
521         struct drm_i915_private *dev_priv = dev->dev_private;
522         intel_clock_t clock;
523         int err = target;
524
525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
526             (I915_READ(LVDS)) != 0) {
527                 /*
528                  * For LVDS, if the panel is on, just rely on its current
529                  * settings for dual-channel.  We haven't figured out how to
530                  * reliably set up different single/dual channel state, if we
531                  * even can.
532                  */
533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534                     LVDS_CLKB_POWER_UP)
535                         clock.p2 = limit->p2.p2_fast;
536                 else
537                         clock.p2 = limit->p2.p2_slow;
538         } else {
539                 if (target < limit->p2.dot_limit)
540                         clock.p2 = limit->p2.p2_slow;
541                 else
542                         clock.p2 = limit->p2.p2_fast;
543         }
544
545         memset (best_clock, 0, sizeof (*best_clock));
546
547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548              clock.m1++) {
549                 for (clock.m2 = limit->m2.min;
550                      clock.m2 <= limit->m2.max; clock.m2++) {
551                         /* m1 is always 0 in Pineview */
552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
553                                 break;
554                         for (clock.n = limit->n.min;
555                              clock.n <= limit->n.max; clock.n++) {
556                                 for (clock.p1 = limit->p1.min;
557                                         clock.p1 <= limit->p1.max; clock.p1++) {
558                                         int this_err;
559
560                                         intel_clock(dev, refclk, &clock);
561                                         if (!intel_PLL_is_valid(dev, limit,
562                                                                 &clock))
563                                                 continue;
564
565                                         this_err = abs(clock.dot - target);
566                                         if (this_err < err) {
567                                                 *best_clock = clock;
568                                                 err = this_err;
569                                         }
570                                 }
571                         }
572                 }
573         }
574
575         return (err != target);
576 }
577
578 static bool
579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580                         int target, int refclk, intel_clock_t *best_clock)
581 {
582         struct drm_device *dev = crtc->dev;
583         struct drm_i915_private *dev_priv = dev->dev_private;
584         intel_clock_t clock;
585         int max_n;
586         bool found;
587         /* approximately equals target * 0.00585 */
588         int err_most = (target >> 8) + (target >> 9);
589         found = false;
590
591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592                 int lvds_reg;
593
594                 if (HAS_PCH_SPLIT(dev))
595                         lvds_reg = PCH_LVDS;
596                 else
597                         lvds_reg = LVDS;
598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
599                     LVDS_CLKB_POWER_UP)
600                         clock.p2 = limit->p2.p2_fast;
601                 else
602                         clock.p2 = limit->p2.p2_slow;
603         } else {
604                 if (target < limit->p2.dot_limit)
605                         clock.p2 = limit->p2.p2_slow;
606                 else
607                         clock.p2 = limit->p2.p2_fast;
608         }
609
610         memset(best_clock, 0, sizeof(*best_clock));
611         max_n = limit->n.max;
612         /* based on hardware requirement, prefer smaller n to precision */
613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
614                 /* based on hardware requirement, prefere larger m1,m2 */
615                 for (clock.m1 = limit->m1.max;
616                      clock.m1 >= limit->m1.min; clock.m1--) {
617                         for (clock.m2 = limit->m2.max;
618                              clock.m2 >= limit->m2.min; clock.m2--) {
619                                 for (clock.p1 = limit->p1.max;
620                                      clock.p1 >= limit->p1.min; clock.p1--) {
621                                         int this_err;
622
623                                         intel_clock(dev, refclk, &clock);
624                                         if (!intel_PLL_is_valid(dev, limit,
625                                                                 &clock))
626                                                 continue;
627
628                                         this_err = abs(clock.dot - target);
629                                         if (this_err < err_most) {
630                                                 *best_clock = clock;
631                                                 err_most = this_err;
632                                                 max_n = clock.n;
633                                                 found = true;
634                                         }
635                                 }
636                         }
637                 }
638         }
639         return found;
640 }
641
642 static bool
643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644                            int target, int refclk, intel_clock_t *best_clock)
645 {
646         struct drm_device *dev = crtc->dev;
647         intel_clock_t clock;
648
649         if (target < 200000) {
650                 clock.n = 1;
651                 clock.p1 = 2;
652                 clock.p2 = 10;
653                 clock.m1 = 12;
654                 clock.m2 = 9;
655         } else {
656                 clock.n = 2;
657                 clock.p1 = 1;
658                 clock.p2 = 10;
659                 clock.m1 = 14;
660                 clock.m2 = 8;
661         }
662         intel_clock(dev, refclk, &clock);
663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
664         return true;
665 }
666
667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
668 static bool
669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670                       int target, int refclk, intel_clock_t *best_clock)
671 {
672         intel_clock_t clock;
673         if (target < 200000) {
674                 clock.p1 = 2;
675                 clock.p2 = 10;
676                 clock.n = 2;
677                 clock.m1 = 23;
678                 clock.m2 = 8;
679         } else {
680                 clock.p1 = 1;
681                 clock.p2 = 10;
682                 clock.n = 1;
683                 clock.m1 = 14;
684                 clock.m2 = 2;
685         }
686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687         clock.p = (clock.p1 * clock.p2);
688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689         clock.vco = 0;
690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
691         return true;
692 }
693
694 /**
695  * intel_wait_for_vblank - wait for vblank on a given pipe
696  * @dev: drm device
697  * @pipe: pipe to wait for
698  *
699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
700  * mode setting code.
701  */
702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
703 {
704         struct drm_i915_private *dev_priv = dev->dev_private;
705         int pipestat_reg = PIPESTAT(pipe);
706
707         /* Clear existing vblank status. Note this will clear any other
708          * sticky status fields as well.
709          *
710          * This races with i915_driver_irq_handler() with the result
711          * that either function could miss a vblank event.  Here it is not
712          * fatal, as we will either wait upon the next vblank interrupt or
713          * timeout.  Generally speaking intel_wait_for_vblank() is only
714          * called during modeset at which time the GPU should be idle and
715          * should *not* be performing page flips and thus not waiting on
716          * vblanks...
717          * Currently, the result of us stealing a vblank from the irq
718          * handler is that a single frame will be skipped during swapbuffers.
719          */
720         I915_WRITE(pipestat_reg,
721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
723         /* Wait for vblank interrupt bit to set */
724         if (wait_for(I915_READ(pipestat_reg) &
725                      PIPE_VBLANK_INTERRUPT_STATUS,
726                      50))
727                 DRM_DEBUG_KMS("vblank wait timed out\n");
728 }
729
730 /*
731  * intel_wait_for_pipe_off - wait for pipe to turn off
732  * @dev: drm device
733  * @pipe: pipe to wait for
734  *
735  * After disabling a pipe, we can't wait for vblank in the usual way,
736  * spinning on the vblank interrupt status bit, since we won't actually
737  * see an interrupt when the pipe is disabled.
738  *
739  * On Gen4 and above:
740  *   wait for the pipe register state bit to turn off
741  *
742  * Otherwise:
743  *   wait for the display line value to settle (it usually
744  *   ends up stopping at the start of the next frame).
745  *
746  */
747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
748 {
749         struct drm_i915_private *dev_priv = dev->dev_private;
750
751         if (INTEL_INFO(dev)->gen >= 4) {
752                 int reg = PIPECONF(pipe);
753
754                 /* Wait for the Pipe State to go off */
755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756                              100))
757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
758         } else {
759                 u32 last_line;
760                 int reg = PIPEDSL(pipe);
761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763                 /* Wait for the display line to settle */
764                 do {
765                         last_line = I915_READ(reg) & DSL_LINEMASK;
766                         mdelay(5);
767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
768                          time_after(timeout, jiffies));
769                 if (time_after(jiffies, timeout))
770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
771         }
772 }
773
774 static const char *state_string(bool enabled)
775 {
776         return enabled ? "on" : "off";
777 }
778
779 /* Only for pre-ILK configs */
780 static void assert_pll(struct drm_i915_private *dev_priv,
781                        enum pipe pipe, bool state)
782 {
783         int reg;
784         u32 val;
785         bool cur_state;
786
787         reg = DPLL(pipe);
788         val = I915_READ(reg);
789         cur_state = !!(val & DPLL_VCO_ENABLE);
790         WARN(cur_state != state,
791              "PLL state assertion failure (expected %s, current %s)\n",
792              state_string(state), state_string(cur_state));
793 }
794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
797 /* For ILK+ */
798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
799                            enum pipe pipe, bool state)
800 {
801         int reg;
802         u32 val;
803         bool cur_state;
804
805         reg = PCH_DPLL(pipe);
806         val = I915_READ(reg);
807         cur_state = !!(val & DPLL_VCO_ENABLE);
808         WARN(cur_state != state,
809              "PCH PLL state assertion failure (expected %s, current %s)\n",
810              state_string(state), state_string(cur_state));
811 }
812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816                           enum pipe pipe, bool state)
817 {
818         int reg;
819         u32 val;
820         bool cur_state;
821
822         reg = FDI_TX_CTL(pipe);
823         val = I915_READ(reg);
824         cur_state = !!(val & FDI_TX_ENABLE);
825         WARN(cur_state != state,
826              "FDI TX state assertion failure (expected %s, current %s)\n",
827              state_string(state), state_string(cur_state));
828 }
829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833                           enum pipe pipe, bool state)
834 {
835         int reg;
836         u32 val;
837         bool cur_state;
838
839         reg = FDI_RX_CTL(pipe);
840         val = I915_READ(reg);
841         cur_state = !!(val & FDI_RX_ENABLE);
842         WARN(cur_state != state,
843              "FDI RX state assertion failure (expected %s, current %s)\n",
844              state_string(state), state_string(cur_state));
845 }
846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850                                       enum pipe pipe)
851 {
852         int reg;
853         u32 val;
854
855         /* ILK FDI PLL is always enabled */
856         if (dev_priv->info->gen == 5)
857                 return;
858
859         reg = FDI_TX_CTL(pipe);
860         val = I915_READ(reg);
861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862 }
863
864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865                                       enum pipe pipe)
866 {
867         int reg;
868         u32 val;
869
870         reg = FDI_RX_CTL(pipe);
871         val = I915_READ(reg);
872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873 }
874
875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876                                   enum pipe pipe)
877 {
878         int pp_reg, lvds_reg;
879         u32 val;
880         enum pipe panel_pipe = PIPE_A;
881         bool locked = locked;
882
883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
884                 pp_reg = PCH_PP_CONTROL;
885                 lvds_reg = PCH_LVDS;
886         } else {
887                 pp_reg = PP_CONTROL;
888                 lvds_reg = LVDS;
889         }
890
891         val = I915_READ(pp_reg);
892         if (!(val & PANEL_POWER_ON) ||
893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894                 locked = false;
895
896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897                 panel_pipe = PIPE_B;
898
899         WARN(panel_pipe == pipe && locked,
900              "panel assertion failure, pipe %c regs locked\n",
901              pipe_name(pipe));
902 }
903
904 static void assert_pipe(struct drm_i915_private *dev_priv,
905                         enum pipe pipe, bool state)
906 {
907         int reg;
908         u32 val;
909         bool cur_state;
910
911         reg = PIPECONF(pipe);
912         val = I915_READ(reg);
913         cur_state = !!(val & PIPECONF_ENABLE);
914         WARN(cur_state != state,
915              "pipe %c assertion failure (expected %s, current %s)\n",
916              pipe_name(pipe), state_string(state), state_string(cur_state));
917 }
918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
920
921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922                                  enum plane plane)
923 {
924         int reg;
925         u32 val;
926
927         reg = DSPCNTR(plane);
928         val = I915_READ(reg);
929         WARN(!(val & DISPLAY_PLANE_ENABLE),
930              "plane %c assertion failure, should be active but is disabled\n",
931              plane_name(plane));
932 }
933
934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935                                    enum pipe pipe)
936 {
937         int reg, i;
938         u32 val;
939         int cur_pipe;
940
941         /* Planes are fixed to pipes on ILK+ */
942         if (HAS_PCH_SPLIT(dev_priv->dev))
943                 return;
944
945         /* Need to check both planes against the pipe */
946         for (i = 0; i < 2; i++) {
947                 reg = DSPCNTR(i);
948                 val = I915_READ(reg);
949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950                         DISPPLANE_SEL_PIPE_SHIFT;
951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
953                      plane_name(i), pipe_name(pipe));
954         }
955 }
956
957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958 {
959         u32 val;
960         bool enabled;
961
962         val = I915_READ(PCH_DREF_CONTROL);
963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964                             DREF_SUPERSPREAD_SOURCE_MASK));
965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966 }
967
968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969                                        enum pipe pipe)
970 {
971         int reg;
972         u32 val;
973         bool enabled;
974
975         reg = TRANSCONF(pipe);
976         val = I915_READ(reg);
977         enabled = !!(val & TRANS_ENABLE);
978         WARN(enabled,
979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
980              pipe_name(pipe));
981 }
982
983 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984                                    enum pipe pipe, int reg)
985 {
986         u32 val = I915_READ(reg);
987         WARN(DP_PIPE_ENABLED(val, pipe),
988              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
989              reg, pipe_name(pipe));
990 }
991
992 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993                                      enum pipe pipe, int reg)
994 {
995         u32 val = I915_READ(reg);
996         WARN(HDMI_PIPE_ENABLED(val, pipe),
997              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
998              reg, pipe_name(pipe));
999 }
1000
1001 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011         reg = PCH_ADPA;
1012         val = I915_READ(reg);
1013         WARN(ADPA_PIPE_ENABLED(val, pipe),
1014              "PCH VGA enabled on transcoder %c, should be disabled\n",
1015              pipe_name(pipe));
1016
1017         reg = PCH_LVDS;
1018         val = I915_READ(reg);
1019         WARN(LVDS_PIPE_ENABLED(val, pipe),
1020              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1021              pipe_name(pipe));
1022
1023         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026 }
1027
1028 /**
1029  * intel_enable_pll - enable a PLL
1030  * @dev_priv: i915 private structure
1031  * @pipe: pipe PLL to enable
1032  *
1033  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1034  * make sure the PLL reg is writable first though, since the panel write
1035  * protect mechanism may be enabled.
1036  *
1037  * Note!  This is for pre-ILK only.
1038  */
1039 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040 {
1041         int reg;
1042         u32 val;
1043
1044         /* No really, not for ILK+ */
1045         BUG_ON(dev_priv->info->gen >= 5);
1046
1047         /* PLL is protected by panel, make sure we can write it */
1048         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049                 assert_panel_unlocked(dev_priv, pipe);
1050
1051         reg = DPLL(pipe);
1052         val = I915_READ(reg);
1053         val |= DPLL_VCO_ENABLE;
1054
1055         /* We do this three times for luck */
1056         I915_WRITE(reg, val);
1057         POSTING_READ(reg);
1058         udelay(150); /* wait for warmup */
1059         I915_WRITE(reg, val);
1060         POSTING_READ(reg);
1061         udelay(150); /* wait for warmup */
1062         I915_WRITE(reg, val);
1063         POSTING_READ(reg);
1064         udelay(150); /* wait for warmup */
1065 }
1066
1067 /**
1068  * intel_disable_pll - disable a PLL
1069  * @dev_priv: i915 private structure
1070  * @pipe: pipe PLL to disable
1071  *
1072  * Disable the PLL for @pipe, making sure the pipe is off first.
1073  *
1074  * Note!  This is for pre-ILK only.
1075  */
1076 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077 {
1078         int reg;
1079         u32 val;
1080
1081         /* Don't disable pipe A or pipe A PLLs if needed */
1082         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083                 return;
1084
1085         /* Make sure the pipe isn't still relying on us */
1086         assert_pipe_disabled(dev_priv, pipe);
1087
1088         reg = DPLL(pipe);
1089         val = I915_READ(reg);
1090         val &= ~DPLL_VCO_ENABLE;
1091         I915_WRITE(reg, val);
1092         POSTING_READ(reg);
1093 }
1094
1095 /**
1096  * intel_enable_pch_pll - enable PCH PLL
1097  * @dev_priv: i915 private structure
1098  * @pipe: pipe PLL to enable
1099  *
1100  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101  * drives the transcoder clock.
1102  */
1103 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104                                  enum pipe pipe)
1105 {
1106         int reg;
1107         u32 val;
1108
1109         /* PCH only available on ILK+ */
1110         BUG_ON(dev_priv->info->gen < 5);
1111
1112         /* PCH refclock must be enabled first */
1113         assert_pch_refclk_enabled(dev_priv);
1114
1115         reg = PCH_DPLL(pipe);
1116         val = I915_READ(reg);
1117         val |= DPLL_VCO_ENABLE;
1118         I915_WRITE(reg, val);
1119         POSTING_READ(reg);
1120         udelay(200);
1121 }
1122
1123 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124                                   enum pipe pipe)
1125 {
1126         int reg;
1127         u32 val;
1128
1129         /* PCH only available on ILK+ */
1130         BUG_ON(dev_priv->info->gen < 5);
1131
1132         /* Make sure transcoder isn't still depending on us */
1133         assert_transcoder_disabled(dev_priv, pipe);
1134
1135         reg = PCH_DPLL(pipe);
1136         val = I915_READ(reg);
1137         val &= ~DPLL_VCO_ENABLE;
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(200);
1141 }
1142
1143 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144                                     enum pipe pipe)
1145 {
1146         int reg;
1147         u32 val;
1148
1149         /* PCH only available on ILK+ */
1150         BUG_ON(dev_priv->info->gen < 5);
1151
1152         /* Make sure PCH DPLL is enabled */
1153         assert_pch_pll_enabled(dev_priv, pipe);
1154
1155         /* FDI must be feeding us bits for PCH ports */
1156         assert_fdi_tx_enabled(dev_priv, pipe);
1157         assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159         reg = TRANSCONF(pipe);
1160         val = I915_READ(reg);
1161
1162         if (HAS_PCH_IBX(dev_priv->dev)) {
1163                 /*
1164                  * make the BPC in transcoder be consistent with
1165                  * that in pipeconf reg.
1166                  */
1167                 val &= ~PIPE_BPC_MASK;
1168                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169         }
1170         I915_WRITE(reg, val | TRANS_ENABLE);
1171         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173 }
1174
1175 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176                                      enum pipe pipe)
1177 {
1178         int reg;
1179         u32 val;
1180
1181         /* FDI relies on the transcoder */
1182         assert_fdi_tx_disabled(dev_priv, pipe);
1183         assert_fdi_rx_disabled(dev_priv, pipe);
1184
1185         /* Ports must be off as well */
1186         assert_pch_ports_disabled(dev_priv, pipe);
1187
1188         reg = TRANSCONF(pipe);
1189         val = I915_READ(reg);
1190         val &= ~TRANS_ENABLE;
1191         I915_WRITE(reg, val);
1192         /* wait for PCH transcoder off, transcoder state */
1193         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194                 DRM_ERROR("failed to disable transcoder\n");
1195 }
1196
1197 /**
1198  * intel_enable_pipe - enable a pipe, asserting requirements
1199  * @dev_priv: i915 private structure
1200  * @pipe: pipe to enable
1201  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1202  *
1203  * Enable @pipe, making sure that various hardware specific requirements
1204  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205  *
1206  * @pipe should be %PIPE_A or %PIPE_B.
1207  *
1208  * Will wait until the pipe is actually running (i.e. first vblank) before
1209  * returning.
1210  */
1211 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212                               bool pch_port)
1213 {
1214         int reg;
1215         u32 val;
1216
1217         /*
1218          * A pipe without a PLL won't actually be able to drive bits from
1219          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1220          * need the check.
1221          */
1222         if (!HAS_PCH_SPLIT(dev_priv->dev))
1223                 assert_pll_enabled(dev_priv, pipe);
1224         else {
1225                 if (pch_port) {
1226                         /* if driving the PCH, we need FDI enabled */
1227                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229                 }
1230                 /* FIXME: assert CPU port conditions for SNB+ */
1231         }
1232
1233         reg = PIPECONF(pipe);
1234         val = I915_READ(reg);
1235         if (val & PIPECONF_ENABLE)
1236                 return;
1237
1238         I915_WRITE(reg, val | PIPECONF_ENABLE);
1239         intel_wait_for_vblank(dev_priv->dev, pipe);
1240 }
1241
1242 /**
1243  * intel_disable_pipe - disable a pipe, asserting requirements
1244  * @dev_priv: i915 private structure
1245  * @pipe: pipe to disable
1246  *
1247  * Disable @pipe, making sure that various hardware specific requirements
1248  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249  *
1250  * @pipe should be %PIPE_A or %PIPE_B.
1251  *
1252  * Will wait until the pipe has shut down before returning.
1253  */
1254 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255                                enum pipe pipe)
1256 {
1257         int reg;
1258         u32 val;
1259
1260         /*
1261          * Make sure planes won't keep trying to pump pixels to us,
1262          * or we might hang the display.
1263          */
1264         assert_planes_disabled(dev_priv, pipe);
1265
1266         /* Don't disable pipe A or pipe A PLLs if needed */
1267         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268                 return;
1269
1270         reg = PIPECONF(pipe);
1271         val = I915_READ(reg);
1272         if ((val & PIPECONF_ENABLE) == 0)
1273                 return;
1274
1275         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1276         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277 }
1278
1279 /**
1280  * intel_enable_plane - enable a display plane on a given pipe
1281  * @dev_priv: i915 private structure
1282  * @plane: plane to enable
1283  * @pipe: pipe being fed
1284  *
1285  * Enable @plane on @pipe, making sure that @pipe is running first.
1286  */
1287 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288                                enum plane plane, enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val;
1292
1293         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294         assert_pipe_enabled(dev_priv, pipe);
1295
1296         reg = DSPCNTR(plane);
1297         val = I915_READ(reg);
1298         if (val & DISPLAY_PLANE_ENABLE)
1299                 return;
1300
1301         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1302         intel_wait_for_vblank(dev_priv->dev, pipe);
1303 }
1304
1305 /*
1306  * Plane regs are double buffered, going from enabled->disabled needs a
1307  * trigger in order to latch.  The display address reg provides this.
1308  */
1309 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310                                       enum plane plane)
1311 {
1312         u32 reg = DSPADDR(plane);
1313         I915_WRITE(reg, I915_READ(reg));
1314 }
1315
1316 /**
1317  * intel_disable_plane - disable a display plane
1318  * @dev_priv: i915 private structure
1319  * @plane: plane to disable
1320  * @pipe: pipe consuming the data
1321  *
1322  * Disable @plane; should be an independent operation.
1323  */
1324 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325                                 enum plane plane, enum pipe pipe)
1326 {
1327         int reg;
1328         u32 val;
1329
1330         reg = DSPCNTR(plane);
1331         val = I915_READ(reg);
1332         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333                 return;
1334
1335         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1336         intel_flush_display_plane(dev_priv, plane);
1337         intel_wait_for_vblank(dev_priv->dev, pipe);
1338 }
1339
1340 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341                            enum pipe pipe, int reg)
1342 {
1343         u32 val = I915_READ(reg);
1344         if (DP_PIPE_ENABLED(val, pipe))
1345                 I915_WRITE(reg, val & ~DP_PORT_EN);
1346 }
1347
1348 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349                              enum pipe pipe, int reg)
1350 {
1351         u32 val = I915_READ(reg);
1352         if (HDMI_PIPE_ENABLED(val, pipe))
1353                 I915_WRITE(reg, val & ~PORT_ENABLE);
1354 }
1355
1356 /* Disable any ports connected to this transcoder */
1357 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358                                     enum pipe pipe)
1359 {
1360         u32 reg, val;
1361
1362         val = I915_READ(PCH_PP_CONTROL);
1363         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369         reg = PCH_ADPA;
1370         val = I915_READ(reg);
1371         if (ADPA_PIPE_ENABLED(val, pipe))
1372                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374         reg = PCH_LVDS;
1375         val = I915_READ(reg);
1376         if (LVDS_PIPE_ENABLED(val, pipe)) {
1377                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378                 POSTING_READ(reg);
1379                 udelay(100);
1380         }
1381
1382         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384         disable_pch_hdmi(dev_priv, pipe, HDMID);
1385 }
1386
1387 static void i8xx_disable_fbc(struct drm_device *dev)
1388 {
1389         struct drm_i915_private *dev_priv = dev->dev_private;
1390         u32 fbc_ctl;
1391
1392         /* Disable compression */
1393         fbc_ctl = I915_READ(FBC_CONTROL);
1394         if ((fbc_ctl & FBC_CTL_EN) == 0)
1395                 return;
1396
1397         fbc_ctl &= ~FBC_CTL_EN;
1398         I915_WRITE(FBC_CONTROL, fbc_ctl);
1399
1400         /* Wait for compressing bit to clear */
1401         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402                 DRM_DEBUG_KMS("FBC idle timed out\n");
1403                 return;
1404         }
1405
1406         DRM_DEBUG_KMS("disabled FBC\n");
1407 }
1408
1409 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1410 {
1411         struct drm_device *dev = crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_framebuffer *fb = crtc->fb;
1414         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1415         struct drm_i915_gem_object *obj = intel_fb->obj;
1416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1417         int cfb_pitch;
1418         int plane, i;
1419         u32 fbc_ctl, fbc_ctl2;
1420
1421         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1422         if (fb->pitch < cfb_pitch)
1423                 cfb_pitch = fb->pitch;
1424
1425         /* FBC_CTL wants 64B units */
1426         cfb_pitch = (cfb_pitch / 64) - 1;
1427         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1428
1429         /* Clear old tags */
1430         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1431                 I915_WRITE(FBC_TAG + (i * 4), 0);
1432
1433         /* Set it up... */
1434         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1435         fbc_ctl2 |= plane;
1436         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1437         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1438
1439         /* enable it... */
1440         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1441         if (IS_I945GM(dev))
1442                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1443         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1444         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1445         fbc_ctl |= obj->fence_reg;
1446         I915_WRITE(FBC_CONTROL, fbc_ctl);
1447
1448         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1449                       cfb_pitch, crtc->y, intel_crtc->plane);
1450 }
1451
1452 static bool i8xx_fbc_enabled(struct drm_device *dev)
1453 {
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455
1456         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1457 }
1458
1459 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1460 {
1461         struct drm_device *dev = crtc->dev;
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463         struct drm_framebuffer *fb = crtc->fb;
1464         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1465         struct drm_i915_gem_object *obj = intel_fb->obj;
1466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1467         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1468         unsigned long stall_watermark = 200;
1469         u32 dpfc_ctl;
1470
1471         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1472         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1473         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1474
1475         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1476                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1477                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1478         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1479
1480         /* enable it... */
1481         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1482
1483         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1484 }
1485
1486 static void g4x_disable_fbc(struct drm_device *dev)
1487 {
1488         struct drm_i915_private *dev_priv = dev->dev_private;
1489         u32 dpfc_ctl;
1490
1491         /* Disable compression */
1492         dpfc_ctl = I915_READ(DPFC_CONTROL);
1493         if (dpfc_ctl & DPFC_CTL_EN) {
1494                 dpfc_ctl &= ~DPFC_CTL_EN;
1495                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1496
1497                 DRM_DEBUG_KMS("disabled FBC\n");
1498         }
1499 }
1500
1501 static bool g4x_fbc_enabled(struct drm_device *dev)
1502 {
1503         struct drm_i915_private *dev_priv = dev->dev_private;
1504
1505         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1506 }
1507
1508 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1509 {
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         u32 blt_ecoskpd;
1512
1513         /* Make sure blitter notifies FBC of writes */
1514         gen6_gt_force_wake_get(dev_priv);
1515         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1516         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1517                 GEN6_BLITTER_LOCK_SHIFT;
1518         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1519         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1520         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1521         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1522                          GEN6_BLITTER_LOCK_SHIFT);
1523         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1524         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1525         gen6_gt_force_wake_put(dev_priv);
1526 }
1527
1528 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1529 {
1530         struct drm_device *dev = crtc->dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct drm_framebuffer *fb = crtc->fb;
1533         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1534         struct drm_i915_gem_object *obj = intel_fb->obj;
1535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1536         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1537         unsigned long stall_watermark = 200;
1538         u32 dpfc_ctl;
1539
1540         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1541         dpfc_ctl &= DPFC_RESERVED;
1542         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1543         /* Set persistent mode for front-buffer rendering, ala X. */
1544         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1545         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1546         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1547
1548         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1549                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1550                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1551         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1552         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1553         /* enable it... */
1554         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1555
1556         if (IS_GEN6(dev)) {
1557                 I915_WRITE(SNB_DPFC_CTL_SA,
1558                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1559                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1560                 sandybridge_blit_fbc_update(dev);
1561         }
1562
1563         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1564 }
1565
1566 static void ironlake_disable_fbc(struct drm_device *dev)
1567 {
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         u32 dpfc_ctl;
1570
1571         /* Disable compression */
1572         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1573         if (dpfc_ctl & DPFC_CTL_EN) {
1574                 dpfc_ctl &= ~DPFC_CTL_EN;
1575                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1576
1577                 DRM_DEBUG_KMS("disabled FBC\n");
1578         }
1579 }
1580
1581 static bool ironlake_fbc_enabled(struct drm_device *dev)
1582 {
1583         struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1586 }
1587
1588 bool intel_fbc_enabled(struct drm_device *dev)
1589 {
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592         if (!dev_priv->display.fbc_enabled)
1593                 return false;
1594
1595         return dev_priv->display.fbc_enabled(dev);
1596 }
1597
1598 static void intel_fbc_work_fn(struct work_struct *__work)
1599 {
1600         struct intel_fbc_work *work =
1601                 container_of(to_delayed_work(__work),
1602                              struct intel_fbc_work, work);
1603         struct drm_device *dev = work->crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605
1606         mutex_lock(&dev->struct_mutex);
1607         if (work == dev_priv->fbc_work) {
1608                 /* Double check that we haven't switched fb without cancelling
1609                  * the prior work.
1610                  */
1611                 if (work->crtc->fb == work->fb) {
1612                         dev_priv->display.enable_fbc(work->crtc,
1613                                                      work->interval);
1614
1615                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1616                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1617                         dev_priv->cfb_y = work->crtc->y;
1618                 }
1619
1620                 dev_priv->fbc_work = NULL;
1621         }
1622         mutex_unlock(&dev->struct_mutex);
1623
1624         kfree(work);
1625 }
1626
1627 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1628 {
1629         if (dev_priv->fbc_work == NULL)
1630                 return;
1631
1632         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1633
1634         /* Synchronisation is provided by struct_mutex and checking of
1635          * dev_priv->fbc_work, so we can perform the cancellation
1636          * entirely asynchronously.
1637          */
1638         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1639                 /* tasklet was killed before being run, clean up */
1640                 kfree(dev_priv->fbc_work);
1641
1642         /* Mark the work as no longer wanted so that if it does
1643          * wake-up (because the work was already running and waiting
1644          * for our mutex), it will discover that is no longer
1645          * necessary to run.
1646          */
1647         dev_priv->fbc_work = NULL;
1648 }
1649
1650 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1651 {
1652         struct intel_fbc_work *work;
1653         struct drm_device *dev = crtc->dev;
1654         struct drm_i915_private *dev_priv = dev->dev_private;
1655
1656         if (!dev_priv->display.enable_fbc)
1657                 return;
1658
1659         intel_cancel_fbc_work(dev_priv);
1660
1661         work = kzalloc(sizeof *work, GFP_KERNEL);
1662         if (work == NULL) {
1663                 dev_priv->display.enable_fbc(crtc, interval);
1664                 return;
1665         }
1666
1667         work->crtc = crtc;
1668         work->fb = crtc->fb;
1669         work->interval = interval;
1670         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1671
1672         dev_priv->fbc_work = work;
1673
1674         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1675
1676         /* Delay the actual enabling to let pageflipping cease and the
1677          * display to settle before starting the compression. Note that
1678          * this delay also serves a second purpose: it allows for a
1679          * vblank to pass after disabling the FBC before we attempt
1680          * to modify the control registers.
1681          *
1682          * A more complicated solution would involve tracking vblanks
1683          * following the termination of the page-flipping sequence
1684          * and indeed performing the enable as a co-routine and not
1685          * waiting synchronously upon the vblank.
1686          */
1687         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1688 }
1689
1690 void intel_disable_fbc(struct drm_device *dev)
1691 {
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693
1694         intel_cancel_fbc_work(dev_priv);
1695
1696         if (!dev_priv->display.disable_fbc)
1697                 return;
1698
1699         dev_priv->display.disable_fbc(dev);
1700         dev_priv->cfb_plane = -1;
1701 }
1702
1703 /**
1704  * intel_update_fbc - enable/disable FBC as needed
1705  * @dev: the drm_device
1706  *
1707  * Set up the framebuffer compression hardware at mode set time.  We
1708  * enable it if possible:
1709  *   - plane A only (on pre-965)
1710  *   - no pixel mulitply/line duplication
1711  *   - no alpha buffer discard
1712  *   - no dual wide
1713  *   - framebuffer <= 2048 in width, 1536 in height
1714  *
1715  * We can't assume that any compression will take place (worst case),
1716  * so the compressed buffer has to be the same size as the uncompressed
1717  * one.  It also must reside (along with the line length buffer) in
1718  * stolen memory.
1719  *
1720  * We need to enable/disable FBC on a global basis.
1721  */
1722 static void intel_update_fbc(struct drm_device *dev)
1723 {
1724         struct drm_i915_private *dev_priv = dev->dev_private;
1725         struct drm_crtc *crtc = NULL, *tmp_crtc;
1726         struct intel_crtc *intel_crtc;
1727         struct drm_framebuffer *fb;
1728         struct intel_framebuffer *intel_fb;
1729         struct drm_i915_gem_object *obj;
1730
1731         DRM_DEBUG_KMS("\n");
1732
1733         if (!i915_powersave)
1734                 return;
1735
1736         if (!I915_HAS_FBC(dev))
1737                 return;
1738
1739         /*
1740          * If FBC is already on, we just have to verify that we can
1741          * keep it that way...
1742          * Need to disable if:
1743          *   - more than one pipe is active
1744          *   - changing FBC params (stride, fence, mode)
1745          *   - new fb is too large to fit in compressed buffer
1746          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1747          */
1748         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1749                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1750                         if (crtc) {
1751                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1752                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1753                                 goto out_disable;
1754                         }
1755                         crtc = tmp_crtc;
1756                 }
1757         }
1758
1759         if (!crtc || crtc->fb == NULL) {
1760                 DRM_DEBUG_KMS("no output, disabling\n");
1761                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1762                 goto out_disable;
1763         }
1764
1765         intel_crtc = to_intel_crtc(crtc);
1766         fb = crtc->fb;
1767         intel_fb = to_intel_framebuffer(fb);
1768         obj = intel_fb->obj;
1769
1770         if (!i915_enable_fbc) {
1771                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1772                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1773                 goto out_disable;
1774         }
1775         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1776                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1777                               "compression\n");
1778                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1779                 goto out_disable;
1780         }
1781         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1782             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1783                 DRM_DEBUG_KMS("mode incompatible with compression, "
1784                               "disabling\n");
1785                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1786                 goto out_disable;
1787         }
1788         if ((crtc->mode.hdisplay > 2048) ||
1789             (crtc->mode.vdisplay > 1536)) {
1790                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1791                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1792                 goto out_disable;
1793         }
1794         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1795                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1796                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1797                 goto out_disable;
1798         }
1799
1800         /* The use of a CPU fence is mandatory in order to detect writes
1801          * by the CPU to the scanout and trigger updates to the FBC.
1802          */
1803         if (obj->tiling_mode != I915_TILING_X ||
1804             obj->fence_reg == I915_FENCE_REG_NONE) {
1805                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1806                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1807                 goto out_disable;
1808         }
1809
1810         /* If the kernel debugger is active, always disable compression */
1811         if (in_dbg_master())
1812                 goto out_disable;
1813
1814         /* If the scanout has not changed, don't modify the FBC settings.
1815          * Note that we make the fundamental assumption that the fb->obj
1816          * cannot be unpinned (and have its GTT offset and fence revoked)
1817          * without first being decoupled from the scanout and FBC disabled.
1818          */
1819         if (dev_priv->cfb_plane == intel_crtc->plane &&
1820             dev_priv->cfb_fb == fb->base.id &&
1821             dev_priv->cfb_y == crtc->y)
1822                 return;
1823
1824         if (intel_fbc_enabled(dev)) {
1825                 /* We update FBC along two paths, after changing fb/crtc
1826                  * configuration (modeswitching) and after page-flipping
1827                  * finishes. For the latter, we know that not only did
1828                  * we disable the FBC at the start of the page-flip
1829                  * sequence, but also more than one vblank has passed.
1830                  *
1831                  * For the former case of modeswitching, it is possible
1832                  * to switch between two FBC valid configurations
1833                  * instantaneously so we do need to disable the FBC
1834                  * before we can modify its control registers. We also
1835                  * have to wait for the next vblank for that to take
1836                  * effect. However, since we delay enabling FBC we can
1837                  * assume that a vblank has passed since disabling and
1838                  * that we can safely alter the registers in the deferred
1839                  * callback.
1840                  *
1841                  * In the scenario that we go from a valid to invalid
1842                  * and then back to valid FBC configuration we have
1843                  * no strict enforcement that a vblank occurred since
1844                  * disabling the FBC. However, along all current pipe
1845                  * disabling paths we do need to wait for a vblank at
1846                  * some point. And we wait before enabling FBC anyway.
1847                  */
1848                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1849                 intel_disable_fbc(dev);
1850         }
1851
1852         intel_enable_fbc(crtc, 500);
1853         return;
1854
1855 out_disable:
1856         /* Multiple disables should be harmless */
1857         if (intel_fbc_enabled(dev)) {
1858                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1859                 intel_disable_fbc(dev);
1860         }
1861 }
1862
1863 int
1864 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1865                            struct drm_i915_gem_object *obj,
1866                            struct intel_ring_buffer *pipelined)
1867 {
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         u32 alignment;
1870         int ret;
1871
1872         switch (obj->tiling_mode) {
1873         case I915_TILING_NONE:
1874                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1875                         alignment = 128 * 1024;
1876                 else if (INTEL_INFO(dev)->gen >= 4)
1877                         alignment = 4 * 1024;
1878                 else
1879                         alignment = 64 * 1024;
1880                 break;
1881         case I915_TILING_X:
1882                 /* pin() will align the object as required by fence */
1883                 alignment = 0;
1884                 break;
1885         case I915_TILING_Y:
1886                 /* FIXME: Is this true? */
1887                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1888                 return -EINVAL;
1889         default:
1890                 BUG();
1891         }
1892
1893         dev_priv->mm.interruptible = false;
1894         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1895         if (ret)
1896                 goto err_interruptible;
1897
1898         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1899          * fence, whereas 965+ only requires a fence if using
1900          * framebuffer compression.  For simplicity, we always install
1901          * a fence as the cost is not that onerous.
1902          */
1903         if (obj->tiling_mode != I915_TILING_NONE) {
1904                 ret = i915_gem_object_get_fence(obj, pipelined);
1905                 if (ret)
1906                         goto err_unpin;
1907         }
1908
1909         dev_priv->mm.interruptible = true;
1910         return 0;
1911
1912 err_unpin:
1913         i915_gem_object_unpin(obj);
1914 err_interruptible:
1915         dev_priv->mm.interruptible = true;
1916         return ret;
1917 }
1918
1919 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1920                              int x, int y)
1921 {
1922         struct drm_device *dev = crtc->dev;
1923         struct drm_i915_private *dev_priv = dev->dev_private;
1924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1925         struct intel_framebuffer *intel_fb;
1926         struct drm_i915_gem_object *obj;
1927         int plane = intel_crtc->plane;
1928         unsigned long Start, Offset;
1929         u32 dspcntr;
1930         u32 reg;
1931
1932         switch (plane) {
1933         case 0:
1934         case 1:
1935                 break;
1936         default:
1937                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1938                 return -EINVAL;
1939         }
1940
1941         intel_fb = to_intel_framebuffer(fb);
1942         obj = intel_fb->obj;
1943
1944         reg = DSPCNTR(plane);
1945         dspcntr = I915_READ(reg);
1946         /* Mask out pixel format bits in case we change it */
1947         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1948         switch (fb->bits_per_pixel) {
1949         case 8:
1950                 dspcntr |= DISPPLANE_8BPP;
1951                 break;
1952         case 16:
1953                 if (fb->depth == 15)
1954                         dspcntr |= DISPPLANE_15_16BPP;
1955                 else
1956                         dspcntr |= DISPPLANE_16BPP;
1957                 break;
1958         case 24:
1959         case 32:
1960                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1961                 break;
1962         default:
1963                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1964                 return -EINVAL;
1965         }
1966         if (INTEL_INFO(dev)->gen >= 4) {
1967                 if (obj->tiling_mode != I915_TILING_NONE)
1968                         dspcntr |= DISPPLANE_TILED;
1969                 else
1970                         dspcntr &= ~DISPPLANE_TILED;
1971         }
1972
1973         I915_WRITE(reg, dspcntr);
1974
1975         Start = obj->gtt_offset;
1976         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1977
1978         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1979                       Start, Offset, x, y, fb->pitch);
1980         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1981         if (INTEL_INFO(dev)->gen >= 4) {
1982                 I915_WRITE(DSPSURF(plane), Start);
1983                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1984                 I915_WRITE(DSPADDR(plane), Offset);
1985         } else
1986                 I915_WRITE(DSPADDR(plane), Start + Offset);
1987         POSTING_READ(reg);
1988
1989         return 0;
1990 }
1991
1992 static int ironlake_update_plane(struct drm_crtc *crtc,
1993                                  struct drm_framebuffer *fb, int x, int y)
1994 {
1995         struct drm_device *dev = crtc->dev;
1996         struct drm_i915_private *dev_priv = dev->dev_private;
1997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998         struct intel_framebuffer *intel_fb;
1999         struct drm_i915_gem_object *obj;
2000         int plane = intel_crtc->plane;
2001         unsigned long Start, Offset;
2002         u32 dspcntr;
2003         u32 reg;
2004
2005         switch (plane) {
2006         case 0:
2007         case 1:
2008                 break;
2009         default:
2010                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011                 return -EINVAL;
2012         }
2013
2014         intel_fb = to_intel_framebuffer(fb);
2015         obj = intel_fb->obj;
2016
2017         reg = DSPCNTR(plane);
2018         dspcntr = I915_READ(reg);
2019         /* Mask out pixel format bits in case we change it */
2020         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021         switch (fb->bits_per_pixel) {
2022         case 8:
2023                 dspcntr |= DISPPLANE_8BPP;
2024                 break;
2025         case 16:
2026                 if (fb->depth != 16)
2027                         return -EINVAL;
2028
2029                 dspcntr |= DISPPLANE_16BPP;
2030                 break;
2031         case 24:
2032         case 32:
2033                 if (fb->depth == 24)
2034                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2035                 else if (fb->depth == 30)
2036                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2037                 else
2038                         return -EINVAL;
2039                 break;
2040         default:
2041                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2042                 return -EINVAL;
2043         }
2044
2045         if (obj->tiling_mode != I915_TILING_NONE)
2046                 dspcntr |= DISPPLANE_TILED;
2047         else
2048                 dspcntr &= ~DISPPLANE_TILED;
2049
2050         /* must disable */
2051         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2052
2053         I915_WRITE(reg, dspcntr);
2054
2055         Start = obj->gtt_offset;
2056         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2057
2058         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059                       Start, Offset, x, y, fb->pitch);
2060         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2061         I915_WRITE(DSPSURF(plane), Start);
2062         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2063         I915_WRITE(DSPADDR(plane), Offset);
2064         POSTING_READ(reg);
2065
2066         return 0;
2067 }
2068
2069 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2070 static int
2071 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2072                            int x, int y, enum mode_set_atomic state)
2073 {
2074         struct drm_device *dev = crtc->dev;
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         int ret;
2077
2078         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2079         if (ret)
2080                 return ret;
2081
2082         intel_update_fbc(dev);
2083         intel_increase_pllclock(crtc);
2084
2085         return 0;
2086 }
2087
2088 static int
2089 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2090                     struct drm_framebuffer *old_fb)
2091 {
2092         struct drm_device *dev = crtc->dev;
2093         struct drm_i915_master_private *master_priv;
2094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095         int ret;
2096
2097         /* no fb bound */
2098         if (!crtc->fb) {
2099                 DRM_DEBUG_KMS("No FB bound\n");
2100                 return 0;
2101         }
2102
2103         switch (intel_crtc->plane) {
2104         case 0:
2105         case 1:
2106                 break;
2107         default:
2108                 return -EINVAL;
2109         }
2110
2111         mutex_lock(&dev->struct_mutex);
2112         ret = intel_pin_and_fence_fb_obj(dev,
2113                                          to_intel_framebuffer(crtc->fb)->obj,
2114                                          NULL);
2115         if (ret != 0) {
2116                 mutex_unlock(&dev->struct_mutex);
2117                 return ret;
2118         }
2119
2120         if (old_fb) {
2121                 struct drm_i915_private *dev_priv = dev->dev_private;
2122                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2123
2124                 wait_event(dev_priv->pending_flip_queue,
2125                            atomic_read(&dev_priv->mm.wedged) ||
2126                            atomic_read(&obj->pending_flip) == 0);
2127
2128                 /* Big Hammer, we also need to ensure that any pending
2129                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2130                  * current scanout is retired before unpinning the old
2131                  * framebuffer.
2132                  *
2133                  * This should only fail upon a hung GPU, in which case we
2134                  * can safely continue.
2135                  */
2136                 ret = i915_gem_object_finish_gpu(obj);
2137                 (void) ret;
2138         }
2139
2140         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2141                                          LEAVE_ATOMIC_MODE_SET);
2142         if (ret) {
2143                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2144                 mutex_unlock(&dev->struct_mutex);
2145                 return ret;
2146         }
2147
2148         if (old_fb) {
2149                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2150                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2151         }
2152
2153         mutex_unlock(&dev->struct_mutex);
2154
2155         if (!dev->primary->master)
2156                 return 0;
2157
2158         master_priv = dev->primary->master->driver_priv;
2159         if (!master_priv->sarea_priv)
2160                 return 0;
2161
2162         if (intel_crtc->pipe) {
2163                 master_priv->sarea_priv->pipeB_x = x;
2164                 master_priv->sarea_priv->pipeB_y = y;
2165         } else {
2166                 master_priv->sarea_priv->pipeA_x = x;
2167                 master_priv->sarea_priv->pipeA_y = y;
2168         }
2169
2170         return 0;
2171 }
2172
2173 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         u32 dpa_ctl;
2178
2179         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2180         dpa_ctl = I915_READ(DP_A);
2181         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2182
2183         if (clock < 200000) {
2184                 u32 temp;
2185                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2186                 /* workaround for 160Mhz:
2187                    1) program 0x4600c bits 15:0 = 0x8124
2188                    2) program 0x46010 bit 0 = 1
2189                    3) program 0x46034 bit 24 = 1
2190                    4) program 0x64000 bit 14 = 1
2191                    */
2192                 temp = I915_READ(0x4600c);
2193                 temp &= 0xffff0000;
2194                 I915_WRITE(0x4600c, temp | 0x8124);
2195
2196                 temp = I915_READ(0x46010);
2197                 I915_WRITE(0x46010, temp | 1);
2198
2199                 temp = I915_READ(0x46034);
2200                 I915_WRITE(0x46034, temp | (1 << 24));
2201         } else {
2202                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2203         }
2204         I915_WRITE(DP_A, dpa_ctl);
2205
2206         POSTING_READ(DP_A);
2207         udelay(500);
2208 }
2209
2210 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2211 {
2212         struct drm_device *dev = crtc->dev;
2213         struct drm_i915_private *dev_priv = dev->dev_private;
2214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215         int pipe = intel_crtc->pipe;
2216         u32 reg, temp;
2217
2218         /* enable normal train */
2219         reg = FDI_TX_CTL(pipe);
2220         temp = I915_READ(reg);
2221         if (IS_IVYBRIDGE(dev)) {
2222                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2223                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2224         } else {
2225                 temp &= ~FDI_LINK_TRAIN_NONE;
2226                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2227         }
2228         I915_WRITE(reg, temp);
2229
2230         reg = FDI_RX_CTL(pipe);
2231         temp = I915_READ(reg);
2232         if (HAS_PCH_CPT(dev)) {
2233                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2234                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2235         } else {
2236                 temp &= ~FDI_LINK_TRAIN_NONE;
2237                 temp |= FDI_LINK_TRAIN_NONE;
2238         }
2239         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2240
2241         /* wait one idle pattern time */
2242         POSTING_READ(reg);
2243         udelay(1000);
2244
2245         /* IVB wants error correction enabled */
2246         if (IS_IVYBRIDGE(dev))
2247                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2248                            FDI_FE_ERRC_ENABLE);
2249 }
2250
2251 /* The FDI link training functions for ILK/Ibexpeak. */
2252 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2253 {
2254         struct drm_device *dev = crtc->dev;
2255         struct drm_i915_private *dev_priv = dev->dev_private;
2256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257         int pipe = intel_crtc->pipe;
2258         int plane = intel_crtc->plane;
2259         u32 reg, temp, tries;
2260
2261         /* FDI needs bits from pipe & plane first */
2262         assert_pipe_enabled(dev_priv, pipe);
2263         assert_plane_enabled(dev_priv, plane);
2264
2265         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2266            for train result */
2267         reg = FDI_RX_IMR(pipe);
2268         temp = I915_READ(reg);
2269         temp &= ~FDI_RX_SYMBOL_LOCK;
2270         temp &= ~FDI_RX_BIT_LOCK;
2271         I915_WRITE(reg, temp);
2272         I915_READ(reg);
2273         udelay(150);
2274
2275         /* enable CPU FDI TX and PCH FDI RX */
2276         reg = FDI_TX_CTL(pipe);
2277         temp = I915_READ(reg);
2278         temp &= ~(7 << 19);
2279         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2280         temp &= ~FDI_LINK_TRAIN_NONE;
2281         temp |= FDI_LINK_TRAIN_PATTERN_1;
2282         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2283
2284         reg = FDI_RX_CTL(pipe);
2285         temp = I915_READ(reg);
2286         temp &= ~FDI_LINK_TRAIN_NONE;
2287         temp |= FDI_LINK_TRAIN_PATTERN_1;
2288         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2289
2290         POSTING_READ(reg);
2291         udelay(150);
2292
2293         /* Ironlake workaround, enable clock pointer after FDI enable*/
2294         if (HAS_PCH_IBX(dev)) {
2295                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2296                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2297                            FDI_RX_PHASE_SYNC_POINTER_EN);
2298         }
2299
2300         reg = FDI_RX_IIR(pipe);
2301         for (tries = 0; tries < 5; tries++) {
2302                 temp = I915_READ(reg);
2303                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2304
2305                 if ((temp & FDI_RX_BIT_LOCK)) {
2306                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2307                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2308                         break;
2309                 }
2310         }
2311         if (tries == 5)
2312                 DRM_ERROR("FDI train 1 fail!\n");
2313
2314         /* Train 2 */
2315         reg = FDI_TX_CTL(pipe);
2316         temp = I915_READ(reg);
2317         temp &= ~FDI_LINK_TRAIN_NONE;
2318         temp |= FDI_LINK_TRAIN_PATTERN_2;
2319         I915_WRITE(reg, temp);
2320
2321         reg = FDI_RX_CTL(pipe);
2322         temp = I915_READ(reg);
2323         temp &= ~FDI_LINK_TRAIN_NONE;
2324         temp |= FDI_LINK_TRAIN_PATTERN_2;
2325         I915_WRITE(reg, temp);
2326
2327         POSTING_READ(reg);
2328         udelay(150);
2329
2330         reg = FDI_RX_IIR(pipe);
2331         for (tries = 0; tries < 5; tries++) {
2332                 temp = I915_READ(reg);
2333                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2334
2335                 if (temp & FDI_RX_SYMBOL_LOCK) {
2336                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2337                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2338                         break;
2339                 }
2340         }
2341         if (tries == 5)
2342                 DRM_ERROR("FDI train 2 fail!\n");
2343
2344         DRM_DEBUG_KMS("FDI train done\n");
2345
2346 }
2347
2348 static const int snb_b_fdi_train_param [] = {
2349         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2350         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2351         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2352         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2353 };
2354
2355 /* The FDI link training functions for SNB/Cougarpoint. */
2356 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2357 {
2358         struct drm_device *dev = crtc->dev;
2359         struct drm_i915_private *dev_priv = dev->dev_private;
2360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2361         int pipe = intel_crtc->pipe;
2362         u32 reg, temp, i;
2363
2364         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2365            for train result */
2366         reg = FDI_RX_IMR(pipe);
2367         temp = I915_READ(reg);
2368         temp &= ~FDI_RX_SYMBOL_LOCK;
2369         temp &= ~FDI_RX_BIT_LOCK;
2370         I915_WRITE(reg, temp);
2371
2372         POSTING_READ(reg);
2373         udelay(150);
2374
2375         /* enable CPU FDI TX and PCH FDI RX */
2376         reg = FDI_TX_CTL(pipe);
2377         temp = I915_READ(reg);
2378         temp &= ~(7 << 19);
2379         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2380         temp &= ~FDI_LINK_TRAIN_NONE;
2381         temp |= FDI_LINK_TRAIN_PATTERN_1;
2382         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2383         /* SNB-B */
2384         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2385         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2386
2387         reg = FDI_RX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         if (HAS_PCH_CPT(dev)) {
2390                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2392         } else {
2393                 temp &= ~FDI_LINK_TRAIN_NONE;
2394                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2395         }
2396         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2397
2398         POSTING_READ(reg);
2399         udelay(150);
2400
2401         for (i = 0; i < 4; i++ ) {
2402                 reg = FDI_TX_CTL(pipe);
2403                 temp = I915_READ(reg);
2404                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2405                 temp |= snb_b_fdi_train_param[i];
2406                 I915_WRITE(reg, temp);
2407
2408                 POSTING_READ(reg);
2409                 udelay(500);
2410
2411                 reg = FDI_RX_IIR(pipe);
2412                 temp = I915_READ(reg);
2413                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2414
2415                 if (temp & FDI_RX_BIT_LOCK) {
2416                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2417                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2418                         break;
2419                 }
2420         }
2421         if (i == 4)
2422                 DRM_ERROR("FDI train 1 fail!\n");
2423
2424         /* Train 2 */
2425         reg = FDI_TX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_LINK_TRAIN_NONE;
2428         temp |= FDI_LINK_TRAIN_PATTERN_2;
2429         if (IS_GEN6(dev)) {
2430                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2431                 /* SNB-B */
2432                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2433         }
2434         I915_WRITE(reg, temp);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         if (HAS_PCH_CPT(dev)) {
2439                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2440                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2441         } else {
2442                 temp &= ~FDI_LINK_TRAIN_NONE;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2444         }
2445         I915_WRITE(reg, temp);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         for (i = 0; i < 4; i++ ) {
2451                 reg = FDI_TX_CTL(pipe);
2452                 temp = I915_READ(reg);
2453                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2454                 temp |= snb_b_fdi_train_param[i];
2455                 I915_WRITE(reg, temp);
2456
2457                 POSTING_READ(reg);
2458                 udelay(500);
2459
2460                 reg = FDI_RX_IIR(pipe);
2461                 temp = I915_READ(reg);
2462                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2463
2464                 if (temp & FDI_RX_SYMBOL_LOCK) {
2465                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2466                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2467                         break;
2468                 }
2469         }
2470         if (i == 4)
2471                 DRM_ERROR("FDI train 2 fail!\n");
2472
2473         DRM_DEBUG_KMS("FDI train done.\n");
2474 }
2475
2476 /* Manual link training for Ivy Bridge A0 parts */
2477 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2478 {
2479         struct drm_device *dev = crtc->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482         int pipe = intel_crtc->pipe;
2483         u32 reg, temp, i;
2484
2485         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2486            for train result */
2487         reg = FDI_RX_IMR(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~FDI_RX_SYMBOL_LOCK;
2490         temp &= ~FDI_RX_BIT_LOCK;
2491         I915_WRITE(reg, temp);
2492
2493         POSTING_READ(reg);
2494         udelay(150);
2495
2496         /* enable CPU FDI TX and PCH FDI RX */
2497         reg = FDI_TX_CTL(pipe);
2498         temp = I915_READ(reg);
2499         temp &= ~(7 << 19);
2500         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2501         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2502         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2503         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2506
2507         reg = FDI_RX_CTL(pipe);
2508         temp = I915_READ(reg);
2509         temp &= ~FDI_LINK_TRAIN_AUTO;
2510         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2513
2514         POSTING_READ(reg);
2515         udelay(150);
2516
2517         for (i = 0; i < 4; i++ ) {
2518                 reg = FDI_TX_CTL(pipe);
2519                 temp = I915_READ(reg);
2520                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2521                 temp |= snb_b_fdi_train_param[i];
2522                 I915_WRITE(reg, temp);
2523
2524                 POSTING_READ(reg);
2525                 udelay(500);
2526
2527                 reg = FDI_RX_IIR(pipe);
2528                 temp = I915_READ(reg);
2529                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2530
2531                 if (temp & FDI_RX_BIT_LOCK ||
2532                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2533                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2534                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2535                         break;
2536                 }
2537         }
2538         if (i == 4)
2539                 DRM_ERROR("FDI train 1 fail!\n");
2540
2541         /* Train 2 */
2542         reg = FDI_TX_CTL(pipe);
2543         temp = I915_READ(reg);
2544         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2545         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2546         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2548         I915_WRITE(reg, temp);
2549
2550         reg = FDI_RX_CTL(pipe);
2551         temp = I915_READ(reg);
2552         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2554         I915_WRITE(reg, temp);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         for (i = 0; i < 4; i++ ) {
2560                 reg = FDI_TX_CTL(pipe);
2561                 temp = I915_READ(reg);
2562                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563                 temp |= snb_b_fdi_train_param[i];
2564                 I915_WRITE(reg, temp);
2565
2566                 POSTING_READ(reg);
2567                 udelay(500);
2568
2569                 reg = FDI_RX_IIR(pipe);
2570                 temp = I915_READ(reg);
2571                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573                 if (temp & FDI_RX_SYMBOL_LOCK) {
2574                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2576                         break;
2577                 }
2578         }
2579         if (i == 4)
2580                 DRM_ERROR("FDI train 2 fail!\n");
2581
2582         DRM_DEBUG_KMS("FDI train done.\n");
2583 }
2584
2585 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2586 {
2587         struct drm_device *dev = crtc->dev;
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2590         int pipe = intel_crtc->pipe;
2591         u32 reg, temp;
2592
2593         /* Write the TU size bits so error detection works */
2594         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2595                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2596
2597         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2598         reg = FDI_RX_CTL(pipe);
2599         temp = I915_READ(reg);
2600         temp &= ~((0x7 << 19) | (0x7 << 16));
2601         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2602         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2603         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2604
2605         POSTING_READ(reg);
2606         udelay(200);
2607
2608         /* Switch from Rawclk to PCDclk */
2609         temp = I915_READ(reg);
2610         I915_WRITE(reg, temp | FDI_PCDCLK);
2611
2612         POSTING_READ(reg);
2613         udelay(200);
2614
2615         /* Enable CPU FDI TX PLL, always on for Ironlake */
2616         reg = FDI_TX_CTL(pipe);
2617         temp = I915_READ(reg);
2618         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2619                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2620
2621                 POSTING_READ(reg);
2622                 udelay(100);
2623         }
2624 }
2625
2626 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2627 {
2628         struct drm_device *dev = crtc->dev;
2629         struct drm_i915_private *dev_priv = dev->dev_private;
2630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2631         int pipe = intel_crtc->pipe;
2632         u32 reg, temp;
2633
2634         /* disable CPU FDI tx and PCH FDI rx */
2635         reg = FDI_TX_CTL(pipe);
2636         temp = I915_READ(reg);
2637         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2638         POSTING_READ(reg);
2639
2640         reg = FDI_RX_CTL(pipe);
2641         temp = I915_READ(reg);
2642         temp &= ~(0x7 << 16);
2643         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2644         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2645
2646         POSTING_READ(reg);
2647         udelay(100);
2648
2649         /* Ironlake workaround, disable clock pointer after downing FDI */
2650         if (HAS_PCH_IBX(dev)) {
2651                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2652                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2653                            I915_READ(FDI_RX_CHICKEN(pipe) &
2654                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2655         }
2656
2657         /* still set train pattern 1 */
2658         reg = FDI_TX_CTL(pipe);
2659         temp = I915_READ(reg);
2660         temp &= ~FDI_LINK_TRAIN_NONE;
2661         temp |= FDI_LINK_TRAIN_PATTERN_1;
2662         I915_WRITE(reg, temp);
2663
2664         reg = FDI_RX_CTL(pipe);
2665         temp = I915_READ(reg);
2666         if (HAS_PCH_CPT(dev)) {
2667                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2669         } else {
2670                 temp &= ~FDI_LINK_TRAIN_NONE;
2671                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2672         }
2673         /* BPC in FDI rx is consistent with that in PIPECONF */
2674         temp &= ~(0x07 << 16);
2675         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2676         I915_WRITE(reg, temp);
2677
2678         POSTING_READ(reg);
2679         udelay(100);
2680 }
2681
2682 /*
2683  * When we disable a pipe, we need to clear any pending scanline wait events
2684  * to avoid hanging the ring, which we assume we are waiting on.
2685  */
2686 static void intel_clear_scanline_wait(struct drm_device *dev)
2687 {
2688         struct drm_i915_private *dev_priv = dev->dev_private;
2689         struct intel_ring_buffer *ring;
2690         u32 tmp;
2691
2692         if (IS_GEN2(dev))
2693                 /* Can't break the hang on i8xx */
2694                 return;
2695
2696         ring = LP_RING(dev_priv);
2697         tmp = I915_READ_CTL(ring);
2698         if (tmp & RING_WAIT)
2699                 I915_WRITE_CTL(ring, tmp);
2700 }
2701
2702 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2703 {
2704         struct drm_i915_gem_object *obj;
2705         struct drm_i915_private *dev_priv;
2706
2707         if (crtc->fb == NULL)
2708                 return;
2709
2710         obj = to_intel_framebuffer(crtc->fb)->obj;
2711         dev_priv = crtc->dev->dev_private;
2712         wait_event(dev_priv->pending_flip_queue,
2713                    atomic_read(&obj->pending_flip) == 0);
2714 }
2715
2716 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2717 {
2718         struct drm_device *dev = crtc->dev;
2719         struct drm_mode_config *mode_config = &dev->mode_config;
2720         struct intel_encoder *encoder;
2721
2722         /*
2723          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2724          * must be driven by its own crtc; no sharing is possible.
2725          */
2726         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2727                 if (encoder->base.crtc != crtc)
2728                         continue;
2729
2730                 switch (encoder->type) {
2731                 case INTEL_OUTPUT_EDP:
2732                         if (!intel_encoder_is_pch_edp(&encoder->base))
2733                                 return false;
2734                         continue;
2735                 }
2736         }
2737
2738         return true;
2739 }
2740
2741 /*
2742  * Enable PCH resources required for PCH ports:
2743  *   - PCH PLLs
2744  *   - FDI training & RX/TX
2745  *   - update transcoder timings
2746  *   - DP transcoding bits
2747  *   - transcoder
2748  */
2749 static void ironlake_pch_enable(struct drm_crtc *crtc)
2750 {
2751         struct drm_device *dev = crtc->dev;
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754         int pipe = intel_crtc->pipe;
2755         u32 reg, temp;
2756
2757         /* For PCH output, training FDI link */
2758         dev_priv->display.fdi_link_train(crtc);
2759
2760         intel_enable_pch_pll(dev_priv, pipe);
2761
2762         if (HAS_PCH_CPT(dev)) {
2763                 /* Be sure PCH DPLL SEL is set */
2764                 temp = I915_READ(PCH_DPLL_SEL);
2765                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2766                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2767                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2768                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2769                 I915_WRITE(PCH_DPLL_SEL, temp);
2770         }
2771
2772         /* set transcoder timing, panel must allow it */
2773         assert_panel_unlocked(dev_priv, pipe);
2774         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2775         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2776         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2777
2778         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2779         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2780         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2781
2782         intel_fdi_normal_train(crtc);
2783
2784         /* For PCH DP, enable TRANS_DP_CTL */
2785         if (HAS_PCH_CPT(dev) &&
2786             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2787                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2788                 reg = TRANS_DP_CTL(pipe);
2789                 temp = I915_READ(reg);
2790                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2791                           TRANS_DP_SYNC_MASK |
2792                           TRANS_DP_BPC_MASK);
2793                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2794                          TRANS_DP_ENH_FRAMING);
2795                 temp |= bpc << 9; /* same format but at 11:9 */
2796
2797                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2798                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2799                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2800                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2801
2802                 switch (intel_trans_dp_port_sel(crtc)) {
2803                 case PCH_DP_B:
2804                         temp |= TRANS_DP_PORT_SEL_B;
2805                         break;
2806                 case PCH_DP_C:
2807                         temp |= TRANS_DP_PORT_SEL_C;
2808                         break;
2809                 case PCH_DP_D:
2810                         temp |= TRANS_DP_PORT_SEL_D;
2811                         break;
2812                 default:
2813                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2814                         temp |= TRANS_DP_PORT_SEL_B;
2815                         break;
2816                 }
2817
2818                 I915_WRITE(reg, temp);
2819         }
2820
2821         intel_enable_transcoder(dev_priv, pipe);
2822 }
2823
2824 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2825 {
2826         struct drm_device *dev = crtc->dev;
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2829         int pipe = intel_crtc->pipe;
2830         int plane = intel_crtc->plane;
2831         u32 temp;
2832         bool is_pch_port;
2833
2834         if (intel_crtc->active)
2835                 return;
2836
2837         intel_crtc->active = true;
2838         intel_update_watermarks(dev);
2839
2840         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2841                 temp = I915_READ(PCH_LVDS);
2842                 if ((temp & LVDS_PORT_EN) == 0)
2843                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2844         }
2845
2846         is_pch_port = intel_crtc_driving_pch(crtc);
2847
2848         if (is_pch_port)
2849                 ironlake_fdi_pll_enable(crtc);
2850         else
2851                 ironlake_fdi_disable(crtc);
2852
2853         /* Enable panel fitting for LVDS */
2854         if (dev_priv->pch_pf_size &&
2855             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2856                 /* Force use of hard-coded filter coefficients
2857                  * as some pre-programmed values are broken,
2858                  * e.g. x201.
2859                  */
2860                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2861                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2862                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2863         }
2864
2865         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2866         intel_enable_plane(dev_priv, plane, pipe);
2867
2868         if (is_pch_port)
2869                 ironlake_pch_enable(crtc);
2870
2871         intel_crtc_load_lut(crtc);
2872
2873         mutex_lock(&dev->struct_mutex);
2874         intel_update_fbc(dev);
2875         mutex_unlock(&dev->struct_mutex);
2876
2877         intel_crtc_update_cursor(crtc, true);
2878 }
2879
2880 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2881 {
2882         struct drm_device *dev = crtc->dev;
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885         int pipe = intel_crtc->pipe;
2886         int plane = intel_crtc->plane;
2887         u32 reg, temp;
2888
2889         if (!intel_crtc->active)
2890                 return;
2891
2892         intel_crtc_wait_for_pending_flips(crtc);
2893         drm_vblank_off(dev, pipe);
2894         intel_crtc_update_cursor(crtc, false);
2895
2896         intel_disable_plane(dev_priv, plane, pipe);
2897
2898         if (dev_priv->cfb_plane == plane)
2899                 intel_disable_fbc(dev);
2900
2901         intel_disable_pipe(dev_priv, pipe);
2902
2903         /* Disable PF */
2904         I915_WRITE(PF_CTL(pipe), 0);
2905         I915_WRITE(PF_WIN_SZ(pipe), 0);
2906
2907         ironlake_fdi_disable(crtc);
2908
2909         /* This is a horrible layering violation; we should be doing this in
2910          * the connector/encoder ->prepare instead, but we don't always have
2911          * enough information there about the config to know whether it will
2912          * actually be necessary or just cause undesired flicker.
2913          */
2914         intel_disable_pch_ports(dev_priv, pipe);
2915
2916         intel_disable_transcoder(dev_priv, pipe);
2917
2918         if (HAS_PCH_CPT(dev)) {
2919                 /* disable TRANS_DP_CTL */
2920                 reg = TRANS_DP_CTL(pipe);
2921                 temp = I915_READ(reg);
2922                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2923                 temp |= TRANS_DP_PORT_SEL_NONE;
2924                 I915_WRITE(reg, temp);
2925
2926                 /* disable DPLL_SEL */
2927                 temp = I915_READ(PCH_DPLL_SEL);
2928                 switch (pipe) {
2929                 case 0:
2930                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2931                         break;
2932                 case 1:
2933                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2934                         break;
2935                 case 2:
2936                         /* FIXME: manage transcoder PLLs? */
2937                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2938                         break;
2939                 default:
2940                         BUG(); /* wtf */
2941                 }
2942                 I915_WRITE(PCH_DPLL_SEL, temp);
2943         }
2944
2945         /* disable PCH DPLL */
2946         intel_disable_pch_pll(dev_priv, pipe);
2947
2948         /* Switch from PCDclk to Rawclk */
2949         reg = FDI_RX_CTL(pipe);
2950         temp = I915_READ(reg);
2951         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2952
2953         /* Disable CPU FDI TX PLL */
2954         reg = FDI_TX_CTL(pipe);
2955         temp = I915_READ(reg);
2956         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2957
2958         POSTING_READ(reg);
2959         udelay(100);
2960
2961         reg = FDI_RX_CTL(pipe);
2962         temp = I915_READ(reg);
2963         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2964
2965         /* Wait for the clocks to turn off. */
2966         POSTING_READ(reg);
2967         udelay(100);
2968
2969         intel_crtc->active = false;
2970         intel_update_watermarks(dev);
2971
2972         mutex_lock(&dev->struct_mutex);
2973         intel_update_fbc(dev);
2974         intel_clear_scanline_wait(dev);
2975         mutex_unlock(&dev->struct_mutex);
2976 }
2977
2978 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2979 {
2980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2981         int pipe = intel_crtc->pipe;
2982         int plane = intel_crtc->plane;
2983
2984         /* XXX: When our outputs are all unaware of DPMS modes other than off
2985          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2986          */
2987         switch (mode) {
2988         case DRM_MODE_DPMS_ON:
2989         case DRM_MODE_DPMS_STANDBY:
2990         case DRM_MODE_DPMS_SUSPEND:
2991                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2992                 ironlake_crtc_enable(crtc);
2993                 break;
2994
2995         case DRM_MODE_DPMS_OFF:
2996                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2997                 ironlake_crtc_disable(crtc);
2998                 break;
2999         }
3000 }
3001
3002 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3003 {
3004         if (!enable && intel_crtc->overlay) {
3005                 struct drm_device *dev = intel_crtc->base.dev;
3006                 struct drm_i915_private *dev_priv = dev->dev_private;
3007
3008                 mutex_lock(&dev->struct_mutex);
3009                 dev_priv->mm.interruptible = false;
3010                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3011                 dev_priv->mm.interruptible = true;
3012                 mutex_unlock(&dev->struct_mutex);
3013         }
3014
3015         /* Let userspace switch the overlay on again. In most cases userspace
3016          * has to recompute where to put it anyway.
3017          */
3018 }
3019
3020 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3021 {
3022         struct drm_device *dev = crtc->dev;
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3025         int pipe = intel_crtc->pipe;
3026         int plane = intel_crtc->plane;
3027
3028         if (intel_crtc->active)
3029                 return;
3030
3031         intel_crtc->active = true;
3032         intel_update_watermarks(dev);
3033
3034         intel_enable_pll(dev_priv, pipe);
3035         intel_enable_pipe(dev_priv, pipe, false);
3036         intel_enable_plane(dev_priv, plane, pipe);
3037
3038         intel_crtc_load_lut(crtc);
3039         intel_update_fbc(dev);
3040
3041         /* Give the overlay scaler a chance to enable if it's on this pipe */
3042         intel_crtc_dpms_overlay(intel_crtc, true);
3043         intel_crtc_update_cursor(crtc, true);
3044 }
3045
3046 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3047 {
3048         struct drm_device *dev = crtc->dev;
3049         struct drm_i915_private *dev_priv = dev->dev_private;
3050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3051         int pipe = intel_crtc->pipe;
3052         int plane = intel_crtc->plane;
3053
3054         if (!intel_crtc->active)
3055                 return;
3056
3057         /* Give the overlay scaler a chance to disable if it's on this pipe */
3058         intel_crtc_wait_for_pending_flips(crtc);
3059         drm_vblank_off(dev, pipe);
3060         intel_crtc_dpms_overlay(intel_crtc, false);
3061         intel_crtc_update_cursor(crtc, false);
3062
3063         if (dev_priv->cfb_plane == plane)
3064                 intel_disable_fbc(dev);
3065
3066         intel_disable_plane(dev_priv, plane, pipe);
3067         intel_disable_pipe(dev_priv, pipe);
3068         intel_disable_pll(dev_priv, pipe);
3069
3070         intel_crtc->active = false;
3071         intel_update_fbc(dev);
3072         intel_update_watermarks(dev);
3073         intel_clear_scanline_wait(dev);
3074 }
3075
3076 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3077 {
3078         /* XXX: When our outputs are all unaware of DPMS modes other than off
3079          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3080          */
3081         switch (mode) {
3082         case DRM_MODE_DPMS_ON: