drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include "drmP.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "drm_dp_helper.h"
  40
  41 #include "drm_crtc_helper.h"
  42
  43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  44
  45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  46 static void intel_update_watermarks(struct drm_device *dev);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51     /* given values */
  52     int n;
  53     int m1, m2;
  54     int p1, p2;
  55     /* derived values */
  56     int dot;
  57     int vco;
  58     int m;
  59     int p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63     int min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67     int dot_limit;
  68     int p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75     intel_p2_t      p2;
  76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                       int, int, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *best_clock);
  86 static bool
  87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  88                         int target, int refclk, intel_clock_t *best_clock);
  89
  90 static bool
  91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  92                       int target, int refclk, intel_clock_t *best_clock);
  93 static bool
  94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                            int target, int refclk, intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2,.max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2,.max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 359                                                 int refclk)
 360 {
 361         struct drm_device *dev = crtc->dev;
 362         struct drm_i915_private *dev_priv = dev->dev_private;
 363         const intel_limit_t *limit;
 364
 365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 367                     LVDS_CLKB_POWER_UP) {
 368                         /* LVDS dual channel */
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_dual_lvds;
 373                 } else {
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_single_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_single_lvds;
 378                 }
 379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 380                         HAS_eDP)
 381                 limit = &intel_limits_ironlake_display_port;
 382         else
 383                 limit = &intel_limits_ironlake_dac;
 384
 385         return limit;
 386 }
 387
 388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 389 {
 390         struct drm_device *dev = crtc->dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         const intel_limit_t *limit;
 393
 394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 396                     LVDS_CLKB_POWER_UP)
 397                         /* LVDS with dual channel */
 398                         limit = &intel_limits_g4x_dual_channel_lvds;
 399                 else
 400                         /* LVDS with dual channel */
 401                         limit = &intel_limits_g4x_single_channel_lvds;
 402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 404                 limit = &intel_limits_g4x_hdmi;
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 406                 limit = &intel_limits_g4x_sdvo;
 407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 408                 limit = &intel_limits_g4x_display_port;
 409         } else /* The option is for other outputs */
 410                 limit = &intel_limits_i9xx_sdvo;
 411
 412         return limit;
 413 }
 414
 415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 416 {
 417         struct drm_device *dev = crtc->dev;
 418         const intel_limit_t *limit;
 419
 420         if (HAS_PCH_SPLIT(dev))
 421                 limit = intel_ironlake_limit(crtc, refclk);
 422         else if (IS_G4X(dev)) {
 423                 limit = intel_g4x_limit(crtc);
 424         } else if (IS_PINEVIEW(dev)) {
 425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 426                         limit = &intel_limits_pineview_lvds;
 427                 else
 428                         limit = &intel_limits_pineview_sdvo;
 429         } else if (!IS_GEN2(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_i9xx_lvds;
 432                 else
 433                         limit = &intel_limits_i9xx_sdvo;
 434         } else {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i8xx_lvds;
 437                 else
 438                         limit = &intel_limits_i8xx_dvo;
 439         }
 440         return limit;
 441 }
 442
 443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 444 static void pineview_clock(int refclk, intel_clock_t *clock)
 445 {
 446         clock->m = clock->m2 + 2;
 447         clock->p = clock->p1 * clock->p2;
 448         clock->vco = refclk * clock->m / clock->n;
 449         clock->dot = clock->vco / clock->p;
 450 }
 451
 452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 453 {
 454         if (IS_PINEVIEW(dev)) {
 455                 pineview_clock(refclk, clock);
 456                 return;
 457         }
 458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 459         clock->p = clock->p1 * clock->p2;
 460         clock->vco = refclk * clock->m / (clock->n + 2);
 461         clock->dot = clock->vco / clock->p;
 462 }
 463
 464 /**
 465  * Returns whether any output on the specified pipe is of the specified type
 466  */
 467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_mode_config *mode_config = &dev->mode_config;
 471         struct intel_encoder *encoder;
 472
 473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 474                 if (encoder->base.crtc == crtc && encoder->type == type)
 475                         return true;
 476
 477         return false;
 478 }
 479
 480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 481 /**
 482  * Returns whether the given set of divisors are valid for a given refclk with
 483  * the given connectors.
 484  */
 485
 486 static bool intel_PLL_is_valid(struct drm_device *dev,
 487                                const intel_limit_t *limit,
 488                                const intel_clock_t *clock)
 489 {
 490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 491                 INTELPllInvalid ("p1 out of range\n");
 492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 493                 INTELPllInvalid ("p out of range\n");
 494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 495                 INTELPllInvalid ("m2 out of range\n");
 496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 497                 INTELPllInvalid ("m1 out of range\n");
 498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 499                 INTELPllInvalid ("m1 <= m2\n");
 500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 501                 INTELPllInvalid ("m out of range\n");
 502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 503                 INTELPllInvalid ("n out of range\n");
 504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 505                 INTELPllInvalid ("vco out of range\n");
 506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 507          * connector, etc., rather than just a single range.
 508          */
 509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 510                 INTELPllInvalid ("dot out of range\n");
 511
 512         return true;
 513 }
 514
 515 static bool
 516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 517                     int target, int refclk, intel_clock_t *best_clock)
 518
 519 {
 520         struct drm_device *dev = crtc->dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         intel_clock_t clock;
 523         int err = target;
 524
 525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 526             (I915_READ(LVDS)) != 0) {
 527                 /*
 528                  * For LVDS, if the panel is on, just rely on its current
 529                  * settings for dual-channel.  We haven't figured out how to
 530                  * reliably set up different single/dual channel state, if we
 531                  * even can.
 532                  */
 533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 534                     LVDS_CLKB_POWER_UP)
 535                         clock.p2 = limit->p2.p2_fast;
 536                 else
 537                         clock.p2 = limit->p2.p2_slow;
 538         } else {
 539                 if (target < limit->p2.dot_limit)
 540                         clock.p2 = limit->p2.p2_slow;
 541                 else
 542                         clock.p2 = limit->p2.p2_fast;
 543         }
 544
 545         memset (best_clock, 0, sizeof (*best_clock));
 546
 547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 548              clock.m1++) {
 549                 for (clock.m2 = limit->m2.min;
 550                      clock.m2 <= limit->m2.max; clock.m2++) {
 551                         /* m1 is always 0 in Pineview */
 552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 553                                 break;
 554                         for (clock.n = limit->n.min;
 555                              clock.n <= limit->n.max; clock.n++) {
 556                                 for (clock.p1 = limit->p1.min;
 557                                         clock.p1 <= limit->p1.max; clock.p1++) {
 558                                         int this_err;
 559
 560                                         intel_clock(dev, refclk, &clock);
 561                                         if (!intel_PLL_is_valid(dev, limit,
 562                                                                 &clock))
 563                                                 continue;
 564
 565                                         this_err = abs(clock.dot - target);
 566                                         if (this_err < err) {
 567                                                 *best_clock = clock;
 568                                                 err = this_err;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573         }
 574
 575         return (err != target);
 576 }
 577
 578 static bool
 579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                         int target, int refclk, intel_clock_t *best_clock)
 581 {
 582         struct drm_device *dev = crtc->dev;
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         intel_clock_t clock;
 585         int max_n;
 586         bool found;
 587         /* approximately equals target * 0.00585 */
 588         int err_most = (target >> 8) + (target >> 9);
 589         found = false;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 int lvds_reg;
 593
 594                 if (HAS_PCH_SPLIT(dev))
 595                         lvds_reg = PCH_LVDS;
 596                 else
 597                         lvds_reg = LVDS;
 598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 599                     LVDS_CLKB_POWER_UP)
 600                         clock.p2 = limit->p2.p2_fast;
 601                 else
 602                         clock.p2 = limit->p2.p2_slow;
 603         } else {
 604                 if (target < limit->p2.dot_limit)
 605                         clock.p2 = limit->p2.p2_slow;
 606                 else
 607                         clock.p2 = limit->p2.p2_fast;
 608         }
 609
 610         memset(best_clock, 0, sizeof(*best_clock));
 611         max_n = limit->n.max;
 612         /* based on hardware requirement, prefer smaller n to precision */
 613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 614                 /* based on hardware requirement, prefere larger m1,m2 */
 615                 for (clock.m1 = limit->m1.max;
 616                      clock.m1 >= limit->m1.min; clock.m1--) {
 617                         for (clock.m2 = limit->m2.max;
 618                              clock.m2 >= limit->m2.min; clock.m2--) {
 619                                 for (clock.p1 = limit->p1.max;
 620                                      clock.p1 >= limit->p1.min; clock.p1--) {
 621                                         int this_err;
 622
 623                                         intel_clock(dev, refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err_most) {
 630                                                 *best_clock = clock;
 631                                                 err_most = this_err;
 632                                                 max_n = clock.n;
 633                                                 found = true;
 634                                         }
 635                                 }
 636                         }
 637                 }
 638         }
 639         return found;
 640 }
 641
 642 static bool
 643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 644                            int target, int refclk, intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         intel_clock_t clock;
 648
 649         if (target < 200000) {
 650                 clock.n = 1;
 651                 clock.p1 = 2;
 652                 clock.p2 = 10;
 653                 clock.m1 = 12;
 654                 clock.m2 = 9;
 655         } else {
 656                 clock.n = 2;
 657                 clock.p1 = 1;
 658                 clock.p2 = 10;
 659                 clock.m1 = 14;
 660                 clock.m2 = 8;
 661         }
 662         intel_clock(dev, refclk, &clock);
 663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 664         return true;
 665 }
 666
 667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 668 static bool
 669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                       int target, int refclk, intel_clock_t *best_clock)
 671 {
 672         intel_clock_t clock;
 673         if (target < 200000) {
 674                 clock.p1 = 2;
 675                 clock.p2 = 10;
 676                 clock.n = 2;
 677                 clock.m1 = 23;
 678                 clock.m2 = 8;
 679         } else {
 680                 clock.p1 = 1;
 681                 clock.p2 = 10;
 682                 clock.n = 1;
 683                 clock.m1 = 14;
 684                 clock.m2 = 2;
 685         }
 686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 687         clock.p = (clock.p1 * clock.p2);
 688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 689         clock.vco = 0;
 690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 691         return true;
 692 }
 693
 694 /**
 695  * intel_wait_for_vblank - wait for vblank on a given pipe
 696  * @dev: drm device
 697  * @pipe: pipe to wait for
 698  *
 699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 700  * mode setting code.
 701  */
 702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 703 {
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         int pipestat_reg = PIPESTAT(pipe);
 706
 707         /* Clear existing vblank status. Note this will clear any other
 708          * sticky status fields as well.
 709          *
 710          * This races with i915_driver_irq_handler() with the result
 711          * that either function could miss a vblank event.  Here it is not
 712          * fatal, as we will either wait upon the next vblank interrupt or
 713          * timeout.  Generally speaking intel_wait_for_vblank() is only
 714          * called during modeset at which time the GPU should be idle and
 715          * should *not* be performing page flips and thus not waiting on
 716          * vblanks...
 717          * Currently, the result of us stealing a vblank from the irq
 718          * handler is that a single frame will be skipped during swapbuffers.
 719          */
 720         I915_WRITE(pipestat_reg,
 721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 722
 723         /* Wait for vblank interrupt bit to set */
 724         if (wait_for(I915_READ(pipestat_reg) &
 725                      PIPE_VBLANK_INTERRUPT_STATUS,
 726                      50))
 727                 DRM_DEBUG_KMS("vblank wait timed out\n");
 728 }
 729
 730 /*
 731  * intel_wait_for_pipe_off - wait for pipe to turn off
 732  * @dev: drm device
 733  * @pipe: pipe to wait for
 734  *
 735  * After disabling a pipe, we can't wait for vblank in the usual way,
 736  * spinning on the vblank interrupt status bit, since we won't actually
 737  * see an interrupt when the pipe is disabled.
 738  *
 739  * On Gen4 and above:
 740  *   wait for the pipe register state bit to turn off
 741  *
 742  * Otherwise:
 743  *   wait for the display line value to settle (it usually
 744  *   ends up stopping at the start of the next frame).
 745  *
 746  */
 747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750
 751         if (INTEL_INFO(dev)->gen >= 4) {
 752                 int reg = PIPECONF(pipe);
 753
 754                 /* Wait for the Pipe State to go off */
 755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 756                              100))
 757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 758         } else {
 759                 u32 last_line;
 760                 int reg = PIPEDSL(pipe);
 761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 762
 763                 /* Wait for the display line to settle */
 764                 do {
 765                         last_line = I915_READ(reg) & DSL_LINEMASK;
 766                         mdelay(5);
 767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 768                          time_after(timeout, jiffies));
 769                 if (time_after(jiffies, timeout))
 770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 771         }
 772 }
 773
 774 static const char *state_string(bool enabled)
 775 {
 776         return enabled ? "on" : "off";
 777 }
 778
 779 /* Only for pre-ILK configs */
 780 static void assert_pll(struct drm_i915_private *dev_priv,
 781                        enum pipe pipe, bool state)
 782 {
 783         int reg;
 784         u32 val;
 785         bool cur_state;
 786
 787         reg = DPLL(pipe);
 788         val = I915_READ(reg);
 789         cur_state = !!(val & DPLL_VCO_ENABLE);
 790         WARN(cur_state != state,
 791              "PLL state assertion failure (expected %s, current %s)\n",
 792              state_string(state), state_string(cur_state));
 793 }
 794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 796
 797 /* For ILK+ */
 798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 799                            enum pipe pipe, bool state)
 800 {
 801         int reg;
 802         u32 val;
 803         bool cur_state;
 804
 805         reg = PCH_DPLL(pipe);
 806         val = I915_READ(reg);
 807         cur_state = !!(val & DPLL_VCO_ENABLE);
 808         WARN(cur_state != state,
 809              "PCH PLL state assertion failure (expected %s, current %s)\n",
 810              state_string(state), state_string(cur_state));
 811 }
 812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 814
 815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 816                           enum pipe pipe, bool state)
 817 {
 818         int reg;
 819         u32 val;
 820         bool cur_state;
 821
 822         reg = FDI_TX_CTL(pipe);
 823         val = I915_READ(reg);
 824         cur_state = !!(val & FDI_TX_ENABLE);
 825         WARN(cur_state != state,
 826              "FDI TX state assertion failure (expected %s, current %s)\n",
 827              state_string(state), state_string(cur_state));
 828 }
 829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 831
 832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 833                           enum pipe pipe, bool state)
 834 {
 835         int reg;
 836         u32 val;
 837         bool cur_state;
 838
 839         reg = FDI_RX_CTL(pipe);
 840         val = I915_READ(reg);
 841         cur_state = !!(val & FDI_RX_ENABLE);
 842         WARN(cur_state != state,
 843              "FDI RX state assertion failure (expected %s, current %s)\n",
 844              state_string(state), state_string(cur_state));
 845 }
 846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 848
 849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 850                                       enum pipe pipe)
 851 {
 852         int reg;
 853         u32 val;
 854
 855         /* ILK FDI PLL is always enabled */
 856         if (dev_priv->info->gen == 5)
 857                 return;
 858
 859         reg = FDI_TX_CTL(pipe);
 860         val = I915_READ(reg);
 861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 862 }
 863
 864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 865                                       enum pipe pipe)
 866 {
 867         int reg;
 868         u32 val;
 869
 870         reg = FDI_RX_CTL(pipe);
 871         val = I915_READ(reg);
 872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 873 }
 874
 875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 876                                   enum pipe pipe)
 877 {
 878         int pp_reg, lvds_reg;
 879         u32 val;
 880         enum pipe panel_pipe = PIPE_A;
 881         bool locked = locked;
 882
 883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 884                 pp_reg = PCH_PP_CONTROL;
 885                 lvds_reg = PCH_LVDS;
 886         } else {
 887                 pp_reg = PP_CONTROL;
 888                 lvds_reg = LVDS;
 889         }
 890
 891         val = I915_READ(pp_reg);
 892         if (!(val & PANEL_POWER_ON) ||
 893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 894                 locked = false;
 895
 896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 897                 panel_pipe = PIPE_B;
 898
 899         WARN(panel_pipe == pipe && locked,
 900              "panel assertion failure, pipe %c regs locked\n",
 901              pipe_name(pipe));
 902 }
 903
 904 static void assert_pipe(struct drm_i915_private *dev_priv,
 905                         enum pipe pipe, bool state)
 906 {
 907         int reg;
 908         u32 val;
 909         bool cur_state;
 910
 911         reg = PIPECONF(pipe);
 912         val = I915_READ(reg);
 913         cur_state = !!(val & PIPECONF_ENABLE);
 914         WARN(cur_state != state,
 915              "pipe %c assertion failure (expected %s, current %s)\n",
 916              pipe_name(pipe), state_string(state), state_string(cur_state));
 917 }
 918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 920
 921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 922                                  enum plane plane)
 923 {
 924         int reg;
 925         u32 val;
 926
 927         reg = DSPCNTR(plane);
 928         val = I915_READ(reg);
 929         WARN(!(val & DISPLAY_PLANE_ENABLE),
 930              "plane %c assertion failure, should be active but is disabled\n",
 931              plane_name(plane));
 932 }
 933
 934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 935                                    enum pipe pipe)
 936 {
 937         int reg, i;
 938         u32 val;
 939         int cur_pipe;
 940
 941         /* Planes are fixed to pipes on ILK+ */
 942         if (HAS_PCH_SPLIT(dev_priv->dev))
 943                 return;
 944
 945         /* Need to check both planes against the pipe */
 946         for (i = 0; i < 2; i++) {
 947                 reg = DSPCNTR(i);
 948                 val = I915_READ(reg);
 949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 950                         DISPPLANE_SEL_PIPE_SHIFT;
 951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 953                      plane_name(i), pipe_name(pipe));
 954         }
 955 }
 956
 957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 958 {
 959         u32 val;
 960         bool enabled;
 961
 962         val = I915_READ(PCH_DREF_CONTROL);
 963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 964                             DREF_SUPERSPREAD_SOURCE_MASK));
 965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 966 }
 967
 968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 969                                        enum pipe pipe)
 970 {
 971         int reg;
 972         u32 val;
 973         bool enabled;
 974
 975         reg = TRANSCONF(pipe);
 976         val = I915_READ(reg);
 977         enabled = !!(val & TRANS_ENABLE);
 978         WARN(enabled,
 979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 980              pipe_name(pipe));
 981 }
 982
 983 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
 984                             int reg, u32 port_sel, u32 val)
 985 {
 986         if ((val & DP_PORT_EN) == 0)
 987                 return false;
 988
 989         if (HAS_PCH_CPT(dev_priv->dev)) {
 990                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
 991                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
 992                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 993                         return false;
 994         } else {
 995                 if ((val & DP_PIPE_MASK) != (pipe << 30))
 996                         return false;
 997         }
 998         return true;
 999 }
1000
1001 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1002                                    enum pipe pipe, int reg, u32 port_sel)
1003 {
1004         u32 val = I915_READ(reg);
1005         WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
1006              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1007              reg, pipe_name(pipe));
1008 }
1009
1010 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1011                                      enum pipe pipe, int reg)
1012 {
1013         u32 val = I915_READ(reg);
1014         WARN(HDMI_PIPE_ENABLED(val, pipe),
1015              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1016              reg, pipe_name(pipe));
1017 }
1018
1019 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1020                                       enum pipe pipe)
1021 {
1022         int reg;
1023         u32 val;
1024
1025         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1026         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1027         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1028
1029         reg = PCH_ADPA;
1030         val = I915_READ(reg);
1031         WARN(ADPA_PIPE_ENABLED(val, pipe),
1032              "PCH VGA enabled on transcoder %c, should be disabled\n",
1033              pipe_name(pipe));
1034
1035         reg = PCH_LVDS;
1036         val = I915_READ(reg);
1037         WARN(LVDS_PIPE_ENABLED(val, pipe),
1038              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1039              pipe_name(pipe));
1040
1041         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1042         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1043         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1044 }
1045
1046 /**
1047  * intel_enable_pll - enable a PLL
1048  * @dev_priv: i915 private structure
1049  * @pipe: pipe PLL to enable
1050  *
1051  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1052  * make sure the PLL reg is writable first though, since the panel write
1053  * protect mechanism may be enabled.
1054  *
1055  * Note!  This is for pre-ILK only.
1056  */
1057 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1058 {
1059         int reg;
1060         u32 val;
1061
1062         /* No really, not for ILK+ */
1063         BUG_ON(dev_priv->info->gen >= 5);
1064
1065         /* PLL is protected by panel, make sure we can write it */
1066         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1067                 assert_panel_unlocked(dev_priv, pipe);
1068
1069         reg = DPLL(pipe);
1070         val = I915_READ(reg);
1071         val |= DPLL_VCO_ENABLE;
1072
1073         /* We do this three times for luck */
1074         I915_WRITE(reg, val);
1075         POSTING_READ(reg);
1076         udelay(150); /* wait for warmup */
1077         I915_WRITE(reg, val);
1078         POSTING_READ(reg);
1079         udelay(150); /* wait for warmup */
1080         I915_WRITE(reg, val);
1081         POSTING_READ(reg);
1082         udelay(150); /* wait for warmup */
1083 }
1084
1085 /**
1086  * intel_disable_pll - disable a PLL
1087  * @dev_priv: i915 private structure
1088  * @pipe: pipe PLL to disable
1089  *
1090  * Disable the PLL for @pipe, making sure the pipe is off first.
1091  *
1092  * Note!  This is for pre-ILK only.
1093  */
1094 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1095 {
1096         int reg;
1097         u32 val;
1098
1099         /* Don't disable pipe A or pipe A PLLs if needed */
1100         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1101                 return;
1102
1103         /* Make sure the pipe isn't still relying on us */
1104         assert_pipe_disabled(dev_priv, pipe);
1105
1106         reg = DPLL(pipe);
1107         val = I915_READ(reg);
1108         val &= ~DPLL_VCO_ENABLE;
1109         I915_WRITE(reg, val);
1110         POSTING_READ(reg);
1111 }
1112
1113 /**
1114  * intel_enable_pch_pll - enable PCH PLL
1115  * @dev_priv: i915 private structure
1116  * @pipe: pipe PLL to enable
1117  *
1118  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1119  * drives the transcoder clock.
1120  */
1121 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1122                                  enum pipe pipe)
1123 {
1124         int reg;
1125         u32 val;
1126
1127         /* PCH only available on ILK+ */
1128         BUG_ON(dev_priv->info->gen < 5);
1129
1130         /* PCH refclock must be enabled first */
1131         assert_pch_refclk_enabled(dev_priv);
1132
1133         reg = PCH_DPLL(pipe);
1134         val = I915_READ(reg);
1135         val |= DPLL_VCO_ENABLE;
1136         I915_WRITE(reg, val);
1137         POSTING_READ(reg);
1138         udelay(200);
1139 }
1140
1141 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1142                                   enum pipe pipe)
1143 {
1144         int reg;
1145         u32 val;
1146
1147         /* PCH only available on ILK+ */
1148         BUG_ON(dev_priv->info->gen < 5);
1149
1150         /* Make sure transcoder isn't still depending on us */
1151         assert_transcoder_disabled(dev_priv, pipe);
1152
1153         reg = PCH_DPLL(pipe);
1154         val = I915_READ(reg);
1155         val &= ~DPLL_VCO_ENABLE;
1156         I915_WRITE(reg, val);
1157         POSTING_READ(reg);
1158         udelay(200);
1159 }
1160
1161 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1162                                     enum pipe pipe)
1163 {
1164         int reg;
1165         u32 val;
1166
1167         /* PCH only available on ILK+ */
1168         BUG_ON(dev_priv->info->gen < 5);
1169
1170         /* Make sure PCH DPLL is enabled */
1171         assert_pch_pll_enabled(dev_priv, pipe);
1172
1173         /* FDI must be feeding us bits for PCH ports */
1174         assert_fdi_tx_enabled(dev_priv, pipe);
1175         assert_fdi_rx_enabled(dev_priv, pipe);
1176
1177         reg = TRANSCONF(pipe);
1178         val = I915_READ(reg);
1179
1180         if (HAS_PCH_IBX(dev_priv->dev)) {
1181                 /*
1182                  * make the BPC in transcoder be consistent with
1183                  * that in pipeconf reg.
1184                  */
1185                 val &= ~PIPE_BPC_MASK;
1186                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1187         }
1188         I915_WRITE(reg, val | TRANS_ENABLE);
1189         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1190                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1191 }
1192
1193 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1194                                      enum pipe pipe)
1195 {
1196         int reg;
1197         u32 val;
1198
1199         /* FDI relies on the transcoder */
1200         assert_fdi_tx_disabled(dev_priv, pipe);
1201         assert_fdi_rx_disabled(dev_priv, pipe);
1202
1203         /* Ports must be off as well */
1204         assert_pch_ports_disabled(dev_priv, pipe);
1205
1206         reg = TRANSCONF(pipe);
1207         val = I915_READ(reg);
1208         val &= ~TRANS_ENABLE;
1209         I915_WRITE(reg, val);
1210         /* wait for PCH transcoder off, transcoder state */
1211         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1212                 DRM_ERROR("failed to disable transcoder\n");
1213 }
1214
1215 /**
1216  * intel_enable_pipe - enable a pipe, asserting requirements
1217  * @dev_priv: i915 private structure
1218  * @pipe: pipe to enable
1219  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1220  *
1221  * Enable @pipe, making sure that various hardware specific requirements
1222  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1223  *
1224  * @pipe should be %PIPE_A or %PIPE_B.
1225  *
1226  * Will wait until the pipe is actually running (i.e. first vblank) before
1227  * returning.
1228  */
1229 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1230                               bool pch_port)
1231 {
1232         int reg;
1233         u32 val;
1234
1235         /*
1236          * A pipe without a PLL won't actually be able to drive bits from
1237          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1238          * need the check.
1239          */
1240         if (!HAS_PCH_SPLIT(dev_priv->dev))
1241                 assert_pll_enabled(dev_priv, pipe);
1242         else {
1243                 if (pch_port) {
1244                         /* if driving the PCH, we need FDI enabled */
1245                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1246                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1247                 }
1248                 /* FIXME: assert CPU port conditions for SNB+ */
1249         }
1250
1251         reg = PIPECONF(pipe);
1252         val = I915_READ(reg);
1253         if (val & PIPECONF_ENABLE)
1254                 return;
1255
1256         I915_WRITE(reg, val | PIPECONF_ENABLE);
1257         intel_wait_for_vblank(dev_priv->dev, pipe);
1258 }
1259
1260 /**
1261  * intel_disable_pipe - disable a pipe, asserting requirements
1262  * @dev_priv: i915 private structure
1263  * @pipe: pipe to disable
1264  *
1265  * Disable @pipe, making sure that various hardware specific requirements
1266  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1267  *
1268  * @pipe should be %PIPE_A or %PIPE_B.
1269  *
1270  * Will wait until the pipe has shut down before returning.
1271  */
1272 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1273                                enum pipe pipe)
1274 {
1275         int reg;
1276         u32 val;
1277
1278         /*
1279          * Make sure planes won't keep trying to pump pixels to us,
1280          * or we might hang the display.
1281          */
1282         assert_planes_disabled(dev_priv, pipe);
1283
1284         /* Don't disable pipe A or pipe A PLLs if needed */
1285         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1286                 return;
1287
1288         reg = PIPECONF(pipe);
1289         val = I915_READ(reg);
1290         if ((val & PIPECONF_ENABLE) == 0)
1291                 return;
1292
1293         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1294         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1295 }
1296
1297 /*
1298  * Plane regs are double buffered, going from enabled->disabled needs a
1299  * trigger in order to latch.  The display address reg provides this.
1300  */
1301 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1302                                       enum plane plane)
1303 {
1304         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1305         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1306 }
1307
1308 /**
1309  * intel_enable_plane - enable a display plane on a given pipe
1310  * @dev_priv: i915 private structure
1311  * @plane: plane to enable
1312  * @pipe: pipe being fed
1313  *
1314  * Enable @plane on @pipe, making sure that @pipe is running first.
1315  */
1316 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1317                                enum plane plane, enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321
1322         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1323         assert_pipe_enabled(dev_priv, pipe);
1324
1325         reg = DSPCNTR(plane);
1326         val = I915_READ(reg);
1327         if (val & DISPLAY_PLANE_ENABLE)
1328                 return;
1329
1330         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1331         intel_flush_display_plane(dev_priv, plane);
1332         intel_wait_for_vblank(dev_priv->dev, pipe);
1333 }
1334
1335 /**
1336  * intel_disable_plane - disable a display plane
1337  * @dev_priv: i915 private structure
1338  * @plane: plane to disable
1339  * @pipe: pipe consuming the data
1340  *
1341  * Disable @plane; should be an independent operation.
1342  */
1343 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1344                                 enum plane plane, enum pipe pipe)
1345 {
1346         int reg;
1347         u32 val;
1348
1349         reg = DSPCNTR(plane);
1350         val = I915_READ(reg);
1351         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1352                 return;
1353
1354         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1355         intel_flush_display_plane(dev_priv, plane);
1356         intel_wait_for_vblank(dev_priv->dev, pipe);
1357 }
1358
1359 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1360                            enum pipe pipe, int reg, u32 port_sel)
1361 {
1362         u32 val = I915_READ(reg);
1363         if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1364                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1365                 I915_WRITE(reg, val & ~DP_PORT_EN);
1366         }
1367 }
1368
1369 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1370                              enum pipe pipe, int reg)
1371 {
1372         u32 val = I915_READ(reg);
1373         if (HDMI_PIPE_ENABLED(val, pipe)) {
1374                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1375                               reg, pipe);
1376                 I915_WRITE(reg, val & ~PORT_ENABLE);
1377         }
1378 }
1379
1380 /* Disable any ports connected to this transcoder */
1381 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1382                                     enum pipe pipe)
1383 {
1384         u32 reg, val;
1385
1386         val = I915_READ(PCH_PP_CONTROL);
1387         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1388
1389         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1390         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1391         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1392
1393         reg = PCH_ADPA;
1394         val = I915_READ(reg);
1395         if (ADPA_PIPE_ENABLED(val, pipe))
1396                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1397
1398         reg = PCH_LVDS;
1399         val = I915_READ(reg);
1400         if (LVDS_PIPE_ENABLED(val, pipe)) {
1401                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1402                 POSTING_READ(reg);
1403                 udelay(100);
1404         }
1405
1406         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1407         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1408         disable_pch_hdmi(dev_priv, pipe, HDMID);
1409 }
1410
1411 static void i8xx_disable_fbc(struct drm_device *dev)
1412 {
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         u32 fbc_ctl;
1415
1416         /* Disable compression */
1417         fbc_ctl = I915_READ(FBC_CONTROL);
1418         if ((fbc_ctl & FBC_CTL_EN) == 0)
1419                 return;
1420
1421         fbc_ctl &= ~FBC_CTL_EN;
1422         I915_WRITE(FBC_CONTROL, fbc_ctl);
1423
1424         /* Wait for compressing bit to clear */
1425         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1426                 DRM_DEBUG_KMS("FBC idle timed out\n");
1427                 return;
1428         }
1429
1430         DRM_DEBUG_KMS("disabled FBC\n");
1431 }
1432
1433 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1434 {
1435         struct drm_device *dev = crtc->dev;
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437         struct drm_framebuffer *fb = crtc->fb;
1438         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1439         struct drm_i915_gem_object *obj = intel_fb->obj;
1440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1441         int cfb_pitch;
1442         int plane, i;
1443         u32 fbc_ctl, fbc_ctl2;
1444
1445         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1446         if (fb->pitch < cfb_pitch)
1447                 cfb_pitch = fb->pitch;
1448
1449         /* FBC_CTL wants 64B units */
1450         cfb_pitch = (cfb_pitch / 64) - 1;
1451         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1452
1453         /* Clear old tags */
1454         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1455                 I915_WRITE(FBC_TAG + (i * 4), 0);
1456
1457         /* Set it up... */
1458         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1459         fbc_ctl2 |= plane;
1460         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1461         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1462
1463         /* enable it... */
1464         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1465         if (IS_I945GM(dev))
1466                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1467         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1468         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1469         fbc_ctl |= obj->fence_reg;
1470         I915_WRITE(FBC_CONTROL, fbc_ctl);
1471
1472         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1473                       cfb_pitch, crtc->y, intel_crtc->plane);
1474 }
1475
1476 static bool i8xx_fbc_enabled(struct drm_device *dev)
1477 {
1478         struct drm_i915_private *dev_priv = dev->dev_private;
1479
1480         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1481 }
1482
1483 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1484 {
1485         struct drm_device *dev = crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         struct drm_framebuffer *fb = crtc->fb;
1488         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1489         struct drm_i915_gem_object *obj = intel_fb->obj;
1490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1491         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1492         unsigned long stall_watermark = 200;
1493         u32 dpfc_ctl;
1494
1495         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1496         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1497         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1498
1499         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1500                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1501                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1502         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1503
1504         /* enable it... */
1505         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1506
1507         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1508 }
1509
1510 static void g4x_disable_fbc(struct drm_device *dev)
1511 {
1512         struct drm_i915_private *dev_priv = dev->dev_private;
1513         u32 dpfc_ctl;
1514
1515         /* Disable compression */
1516         dpfc_ctl = I915_READ(DPFC_CONTROL);
1517         if (dpfc_ctl & DPFC_CTL_EN) {
1518                 dpfc_ctl &= ~DPFC_CTL_EN;
1519                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1520
1521                 DRM_DEBUG_KMS("disabled FBC\n");
1522         }
1523 }
1524
1525 static bool g4x_fbc_enabled(struct drm_device *dev)
1526 {
1527         struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1530 }
1531
1532 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1533 {
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         u32 blt_ecoskpd;
1536
1537         /* Make sure blitter notifies FBC of writes */
1538         gen6_gt_force_wake_get(dev_priv);
1539         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1540         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1541                 GEN6_BLITTER_LOCK_SHIFT;
1542         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1543         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1544         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1545         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1546                          GEN6_BLITTER_LOCK_SHIFT);
1547         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1549         gen6_gt_force_wake_put(dev_priv);
1550 }
1551
1552 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1553 {
1554         struct drm_device *dev = crtc->dev;
1555         struct drm_i915_private *dev_priv = dev->dev_private;
1556         struct drm_framebuffer *fb = crtc->fb;
1557         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1558         struct drm_i915_gem_object *obj = intel_fb->obj;
1559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1560         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1561         unsigned long stall_watermark = 200;
1562         u32 dpfc_ctl;
1563
1564         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1565         dpfc_ctl &= DPFC_RESERVED;
1566         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1567         /* Set persistent mode for front-buffer rendering, ala X. */
1568         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1569         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1570         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1571
1572         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1573                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1574                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1575         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1576         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1577         /* enable it... */
1578         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1579
1580         if (IS_GEN6(dev)) {
1581                 I915_WRITE(SNB_DPFC_CTL_SA,
1582                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1583                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1584                 sandybridge_blit_fbc_update(dev);
1585         }
1586
1587         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1588 }
1589
1590 static void ironlake_disable_fbc(struct drm_device *dev)
1591 {
1592         struct drm_i915_private *dev_priv = dev->dev_private;
1593         u32 dpfc_ctl;
1594
1595         /* Disable compression */
1596         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1597         if (dpfc_ctl & DPFC_CTL_EN) {
1598                 dpfc_ctl &= ~DPFC_CTL_EN;
1599                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1600
1601                 DRM_DEBUG_KMS("disabled FBC\n");
1602         }
1603 }
1604
1605 static bool ironlake_fbc_enabled(struct drm_device *dev)
1606 {
1607         struct drm_i915_private *dev_priv = dev->dev_private;
1608
1609         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1610 }
1611
1612 bool intel_fbc_enabled(struct drm_device *dev)
1613 {
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615
1616         if (!dev_priv->display.fbc_enabled)
1617                 return false;
1618
1619         return dev_priv->display.fbc_enabled(dev);
1620 }
1621
1622 static void intel_fbc_work_fn(struct work_struct *__work)
1623 {
1624         struct intel_fbc_work *work =
1625                 container_of(to_delayed_work(__work),
1626                              struct intel_fbc_work, work);
1627         struct drm_device *dev = work->crtc->dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630         mutex_lock(&dev->struct_mutex);
1631         if (work == dev_priv->fbc_work) {
1632                 /* Double check that we haven't switched fb without cancelling
1633                  * the prior work.
1634                  */
1635                 if (work->crtc->fb == work->fb) {
1636                         dev_priv->display.enable_fbc(work->crtc,
1637                                                      work->interval);
1638
1639                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1640                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1641                         dev_priv->cfb_y = work->crtc->y;
1642                 }
1643
1644                 dev_priv->fbc_work = NULL;
1645         }
1646         mutex_unlock(&dev->struct_mutex);
1647
1648         kfree(work);
1649 }
1650
1651 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1652 {
1653         if (dev_priv->fbc_work == NULL)
1654                 return;
1655
1656         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1657
1658         /* Synchronisation is provided by struct_mutex and checking of
1659          * dev_priv->fbc_work, so we can perform the cancellation
1660          * entirely asynchronously.
1661          */
1662         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1663                 /* tasklet was killed before being run, clean up */
1664                 kfree(dev_priv->fbc_work);
1665
1666         /* Mark the work as no longer wanted so that if it does
1667          * wake-up (because the work was already running and waiting
1668          * for our mutex), it will discover that is no longer
1669          * necessary to run.
1670          */
1671         dev_priv->fbc_work = NULL;
1672 }
1673
1674 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1675 {
1676         struct intel_fbc_work *work;
1677         struct drm_device *dev = crtc->dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679
1680         if (!dev_priv->display.enable_fbc)
1681                 return;
1682
1683         intel_cancel_fbc_work(dev_priv);
1684
1685         work = kzalloc(sizeof *work, GFP_KERNEL);
1686         if (work == NULL) {
1687                 dev_priv->display.enable_fbc(crtc, interval);
1688                 return;
1689         }
1690
1691         work->crtc = crtc;
1692         work->fb = crtc->fb;
1693         work->interval = interval;
1694         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1695
1696         dev_priv->fbc_work = work;
1697
1698         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1699
1700         /* Delay the actual enabling to let pageflipping cease and the
1701          * display to settle before starting the compression. Note that
1702          * this delay also serves a second purpose: it allows for a
1703          * vblank to pass after disabling the FBC before we attempt
1704          * to modify the control registers.
1705          *
1706          * A more complicated solution would involve tracking vblanks
1707          * following the termination of the page-flipping sequence
1708          * and indeed performing the enable as a co-routine and not
1709          * waiting synchronously upon the vblank.
1710          */
1711         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1712 }
1713
1714 void intel_disable_fbc(struct drm_device *dev)
1715 {
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718         intel_cancel_fbc_work(dev_priv);
1719
1720         if (!dev_priv->display.disable_fbc)
1721                 return;
1722
1723         dev_priv->display.disable_fbc(dev);
1724         dev_priv->cfb_plane = -1;
1725 }
1726
1727 /**
1728  * intel_update_fbc - enable/disable FBC as needed
1729  * @dev: the drm_device
1730  *
1731  * Set up the framebuffer compression hardware at mode set time.  We
1732  * enable it if possible:
1733  *   - plane A only (on pre-965)
1734  *   - no pixel mulitply/line duplication
1735  *   - no alpha buffer discard
1736  *   - no dual wide
1737  *   - framebuffer <= 2048 in width, 1536 in height
1738  *
1739  * We can't assume that any compression will take place (worst case),
1740  * so the compressed buffer has to be the same size as the uncompressed
1741  * one.  It also must reside (along with the line length buffer) in
1742  * stolen memory.
1743  *
1744  * We need to enable/disable FBC on a global basis.
1745  */
1746 static void intel_update_fbc(struct drm_device *dev)
1747 {
1748         struct drm_i915_private *dev_priv = dev->dev_private;
1749         struct drm_crtc *crtc = NULL, *tmp_crtc;
1750         struct intel_crtc *intel_crtc;
1751         struct drm_framebuffer *fb;
1752         struct intel_framebuffer *intel_fb;
1753         struct drm_i915_gem_object *obj;
1754
1755         DRM_DEBUG_KMS("\n");
1756
1757         if (!i915_powersave)
1758                 return;
1759
1760         if (!I915_HAS_FBC(dev))
1761                 return;
1762
1763         /*
1764          * If FBC is already on, we just have to verify that we can
1765          * keep it that way...
1766          * Need to disable if:
1767          *   - more than one pipe is active
1768          *   - changing FBC params (stride, fence, mode)
1769          *   - new fb is too large to fit in compressed buffer
1770          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1771          */
1772         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1773                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1774                         if (crtc) {
1775                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1776                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1777                                 goto out_disable;
1778                         }
1779                         crtc = tmp_crtc;
1780                 }
1781         }
1782
1783         if (!crtc || crtc->fb == NULL) {
1784                 DRM_DEBUG_KMS("no output, disabling\n");
1785                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1786                 goto out_disable;
1787         }
1788
1789         intel_crtc = to_intel_crtc(crtc);
1790         fb = crtc->fb;
1791         intel_fb = to_intel_framebuffer(fb);
1792         obj = intel_fb->obj;
1793
1794         if (!i915_enable_fbc) {
1795                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1796                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1797                 goto out_disable;
1798         }
1799         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1800                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1801                               "compression\n");
1802                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1803                 goto out_disable;
1804         }
1805         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1806             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1807                 DRM_DEBUG_KMS("mode incompatible with compression, "
1808                               "disabling\n");
1809                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1810                 goto out_disable;
1811         }
1812         if ((crtc->mode.hdisplay > 2048) ||
1813             (crtc->mode.vdisplay > 1536)) {
1814                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1815                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1816                 goto out_disable;
1817         }
1818         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1819                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1820                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1821                 goto out_disable;
1822         }
1823
1824         /* The use of a CPU fence is mandatory in order to detect writes
1825          * by the CPU to the scanout and trigger updates to the FBC.
1826          */
1827         if (obj->tiling_mode != I915_TILING_X ||
1828             obj->fence_reg == I915_FENCE_REG_NONE) {
1829                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1830                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1831                 goto out_disable;
1832         }
1833
1834         /* If the kernel debugger is active, always disable compression */
1835         if (in_dbg_master())
1836                 goto out_disable;
1837
1838         /* If the scanout has not changed, don't modify the FBC settings.
1839          * Note that we make the fundamental assumption that the fb->obj
1840          * cannot be unpinned (and have its GTT offset and fence revoked)
1841          * without first being decoupled from the scanout and FBC disabled.
1842          */
1843         if (dev_priv->cfb_plane == intel_crtc->plane &&
1844             dev_priv->cfb_fb == fb->base.id &&
1845             dev_priv->cfb_y == crtc->y)
1846                 return;
1847
1848         if (intel_fbc_enabled(dev)) {
1849                 /* We update FBC along two paths, after changing fb/crtc
1850                  * configuration (modeswitching) and after page-flipping
1851                  * finishes. For the latter, we know that not only did
1852                  * we disable the FBC at the start of the page-flip
1853                  * sequence, but also more than one vblank has passed.
1854                  *
1855                  * For the former case of modeswitching, it is possible
1856                  * to switch between two FBC valid configurations
1857                  * instantaneously so we do need to disable the FBC
1858                  * before we can modify its control registers. We also
1859                  * have to wait for the next vblank for that to take
1860                  * effect. However, since we delay enabling FBC we can
1861                  * assume that a vblank has passed since disabling and
1862                  * that we can safely alter the registers in the deferred
1863                  * callback.
1864                  *
1865                  * In the scenario that we go from a valid to invalid
1866                  * and then back to valid FBC configuration we have
1867                  * no strict enforcement that a vblank occurred since
1868                  * disabling the FBC. However, along all current pipe
1869                  * disabling paths we do need to wait for a vblank at
1870                  * some point. And we wait before enabling FBC anyway.
1871                  */
1872                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1873                 intel_disable_fbc(dev);
1874         }
1875
1876         intel_enable_fbc(crtc, 500);
1877         return;
1878
1879 out_disable:
1880         /* Multiple disables should be harmless */
1881         if (intel_fbc_enabled(dev)) {
1882                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1883                 intel_disable_fbc(dev);
1884         }
1885 }
1886
1887 int
1888 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1889                            struct drm_i915_gem_object *obj,
1890                            struct intel_ring_buffer *pipelined)
1891 {
1892         struct drm_i915_private *dev_priv = dev->dev_private;
1893         u32 alignment;
1894         int ret;
1895
1896         switch (obj->tiling_mode) {
1897         case I915_TILING_NONE:
1898                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1899                         alignment = 128 * 1024;
1900                 else if (INTEL_INFO(dev)->gen >= 4)
1901                         alignment = 4 * 1024;
1902                 else
1903                         alignment = 64 * 1024;
1904                 break;
1905         case I915_TILING_X:
1906                 /* pin() will align the object as required by fence */
1907                 alignment = 0;
1908                 break;
1909         case I915_TILING_Y:
1910                 /* FIXME: Is this true? */
1911                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1912                 return -EINVAL;
1913         default:
1914                 BUG();
1915         }
1916
1917         dev_priv->mm.interruptible = false;
1918         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1919         if (ret)
1920                 goto err_interruptible;
1921
1922         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1923          * fence, whereas 965+ only requires a fence if using
1924          * framebuffer compression.  For simplicity, we always install
1925          * a fence as the cost is not that onerous.
1926          */
1927         if (obj->tiling_mode != I915_TILING_NONE) {
1928                 ret = i915_gem_object_get_fence(obj, pipelined);
1929                 if (ret)
1930                         goto err_unpin;
1931         }
1932
1933         dev_priv->mm.interruptible = true;
1934         return 0;
1935
1936 err_unpin:
1937         i915_gem_object_unpin(obj);
1938 err_interruptible:
1939         dev_priv->mm.interruptible = true;
1940         return ret;
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944                              int x, int y)
1945 {
1946         struct drm_device *dev = crtc->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949         struct intel_framebuffer *intel_fb;
1950         struct drm_i915_gem_object *obj;
1951         int plane = intel_crtc->plane;
1952         unsigned long Start, Offset;
1953         u32 dspcntr;
1954         u32 reg;
1955
1956         switch (plane) {
1957         case 0:
1958         case 1:
1959                 break;
1960         default:
1961                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962                 return -EINVAL;
1963         }
1964
1965         intel_fb = to_intel_framebuffer(fb);
1966         obj = intel_fb->obj;
1967
1968         reg = DSPCNTR(plane);
1969         dspcntr = I915_READ(reg);
1970         /* Mask out pixel format bits in case we change it */
1971         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972         switch (fb->bits_per_pixel) {
1973         case 8:
1974                 dspcntr |= DISPPLANE_8BPP;
1975                 break;
1976         case 16:
1977                 if (fb->depth == 15)
1978                         dspcntr |= DISPPLANE_15_16BPP;
1979                 else
1980                         dspcntr |= DISPPLANE_16BPP;
1981                 break;
1982         case 24:
1983         case 32:
1984                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985                 break;
1986         default:
1987                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988                 return -EINVAL;
1989         }
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 if (obj->tiling_mode != I915_TILING_NONE)
1992                         dspcntr |= DISPPLANE_TILED;
1993                 else
1994                         dspcntr &= ~DISPPLANE_TILED;
1995         }
1996
1997         I915_WRITE(reg, dspcntr);
1998
1999         Start = obj->gtt_offset;
2000         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2001
2002         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003                       Start, Offset, x, y, fb->pitch);
2004         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2005         if (INTEL_INFO(dev)->gen >= 4) {
2006                 I915_WRITE(DSPSURF(plane), Start);
2007                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2008                 I915_WRITE(DSPADDR(plane), Offset);
2009         } else
2010                 I915_WRITE(DSPADDR(plane), Start + Offset);
2011         POSTING_READ(reg);
2012
2013         return 0;
2014 }
2015
2016 static int ironlake_update_plane(struct drm_crtc *crtc,
2017                                  struct drm_framebuffer *fb, int x, int y)
2018 {
2019         struct drm_device *dev = crtc->dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022         struct intel_framebuffer *intel_fb;
2023         struct drm_i915_gem_object *obj;
2024         int plane = intel_crtc->plane;
2025         unsigned long Start, Offset;
2026         u32 dspcntr;
2027         u32 reg;
2028
2029         switch (plane) {
2030         case 0:
2031         case 1:
2032                 break;
2033         default:
2034                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2035                 return -EINVAL;
2036         }
2037
2038         intel_fb = to_intel_framebuffer(fb);
2039         obj = intel_fb->obj;
2040
2041         reg = DSPCNTR(plane);
2042         dspcntr = I915_READ(reg);
2043         /* Mask out pixel format bits in case we change it */
2044         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2045         switch (fb->bits_per_pixel) {
2046         case 8:
2047                 dspcntr |= DISPPLANE_8BPP;
2048                 break;
2049         case 16:
2050                 if (fb->depth != 16)
2051                         return -EINVAL;
2052
2053                 dspcntr |= DISPPLANE_16BPP;
2054                 break;
2055         case 24:
2056         case 32:
2057                 if (fb->depth == 24)
2058                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2059                 else if (fb->depth == 30)
2060                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2061                 else
2062                         return -EINVAL;
2063                 break;
2064         default:
2065                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2066                 return -EINVAL;
2067         }
2068
2069         if (obj->tiling_mode != I915_TILING_NONE)
2070                 dspcntr |= DISPPLANE_TILED;
2071         else
2072                 dspcntr &= ~DISPPLANE_TILED;
2073
2074         /* must disable */
2075         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2076
2077         I915_WRITE(reg, dspcntr);
2078
2079         Start = obj->gtt_offset;
2080         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2081
2082         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2083                       Start, Offset, x, y, fb->pitch);
2084         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2085         I915_WRITE(DSPSURF(plane), Start);
2086         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2087         I915_WRITE(DSPADDR(plane), Offset);
2088         POSTING_READ(reg);
2089
2090         return 0;
2091 }
2092
2093 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2094 static int
2095 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2096                            int x, int y, enum mode_set_atomic state)
2097 {
2098         struct drm_device *dev = crtc->dev;
2099         struct drm_i915_private *dev_priv = dev->dev_private;
2100         int ret;
2101
2102         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2103         if (ret)
2104                 return ret;
2105
2106         intel_update_fbc(dev);
2107         intel_increase_pllclock(crtc);
2108
2109         return 0;
2110 }
2111
2112 static int
2113 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2114                     struct drm_framebuffer *old_fb)
2115 {
2116         struct drm_device *dev = crtc->dev;
2117         struct drm_i915_master_private *master_priv;
2118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119         int ret;
2120
2121         /* no fb bound */
2122         if (!crtc->fb) {
2123                 DRM_ERROR("No FB bound\n");
2124                 return 0;
2125         }
2126
2127         switch (intel_crtc->plane) {
2128         case 0:
2129         case 1:
2130                 break;
2131         default:
2132                 DRM_ERROR("no plane for crtc\n");
2133                 return -EINVAL;
2134         }
2135
2136         mutex_lock(&dev->struct_mutex);
2137         ret = intel_pin_and_fence_fb_obj(dev,
2138                                          to_intel_framebuffer(crtc->fb)->obj,
2139                                          NULL);
2140         if (ret != 0) {
2141                 mutex_unlock(&dev->struct_mutex);
2142                 DRM_ERROR("pin & fence failed\n");
2143                 return ret;
2144         }
2145
2146         if (old_fb) {
2147                 struct drm_i915_private *dev_priv = dev->dev_private;
2148                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2149
2150                 wait_event(dev_priv->pending_flip_queue,
2151                            atomic_read(&dev_priv->mm.wedged) ||
2152                            atomic_read(&obj->pending_flip) == 0);
2153
2154                 /* Big Hammer, we also need to ensure that any pending
2155                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2156                  * current scanout is retired before unpinning the old
2157                  * framebuffer.
2158                  *
2159                  * This should only fail upon a hung GPU, in which case we
2160                  * can safely continue.
2161                  */
2162                 ret = i915_gem_object_finish_gpu(obj);
2163                 (void) ret;
2164         }
2165
2166         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2167                                          LEAVE_ATOMIC_MODE_SET);
2168         if (ret) {
2169                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2170                 mutex_unlock(&dev->struct_mutex);
2171                 DRM_ERROR("failed to update base address\n");
2172                 return ret;
2173         }
2174
2175         if (old_fb) {
2176                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2177                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2178         }
2179
2180         mutex_unlock(&dev->struct_mutex);
2181
2182         if (!dev->primary->master)
2183                 return 0;
2184
2185         master_priv = dev->primary->master->driver_priv;
2186         if (!master_priv->sarea_priv)
2187                 return 0;
2188
2189         if (intel_crtc->pipe) {
2190                 master_priv->sarea_priv->pipeB_x = x;
2191                 master_priv->sarea_priv->pipeB_y = y;
2192         } else {
2193                 master_priv->sarea_priv->pipeA_x = x;
2194                 master_priv->sarea_priv->pipeA_y = y;
2195         }
2196
2197         return 0;
2198 }
2199
2200 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2201 {
2202         struct drm_device *dev = crtc->dev;
2203         struct drm_i915_private *dev_priv = dev->dev_private;
2204         u32 dpa_ctl;
2205
2206         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2207         dpa_ctl = I915_READ(DP_A);
2208         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2209
2210         if (clock < 200000) {
2211                 u32 temp;
2212                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2213                 /* workaround for 160Mhz:
2214                    1) program 0x4600c bits 15:0 = 0x8124
2215                    2) program 0x46010 bit 0 = 1
2216                    3) program 0x46034 bit 24 = 1
2217                    4) program 0x64000 bit 14 = 1
2218                    */
2219                 temp = I915_READ(0x4600c);
2220                 temp &= 0xffff0000;
2221                 I915_WRITE(0x4600c, temp | 0x8124);
2222
2223                 temp = I915_READ(0x46010);
2224                 I915_WRITE(0x46010, temp | 1);
2225
2226                 temp = I915_READ(0x46034);
2227                 I915_WRITE(0x46034, temp | (1 << 24));
2228         } else {
2229                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2230         }
2231         I915_WRITE(DP_A, dpa_ctl);
2232
2233         POSTING_READ(DP_A);
2234         udelay(500);
2235 }
2236
2237 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242         int pipe = intel_crtc->pipe;
2243         u32 reg, temp;
2244
2245         /* enable normal train */
2246         reg = FDI_TX_CTL(pipe);
2247         temp = I915_READ(reg);
2248         if (IS_IVYBRIDGE(dev)) {
2249                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2250                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2251         } else {
2252                 temp &= ~FDI_LINK_TRAIN_NONE;
2253                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2254         }
2255         I915_WRITE(reg, temp);
2256
2257         reg = FDI_RX_CTL(pipe);
2258         temp = I915_READ(reg);
2259         if (HAS_PCH_CPT(dev)) {
2260                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2261                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2262         } else {
2263                 temp &= ~FDI_LINK_TRAIN_NONE;
2264                 temp |= FDI_LINK_TRAIN_NONE;
2265         }
2266         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2267
2268         /* wait one idle pattern time */
2269         POSTING_READ(reg);
2270         udelay(1000);
2271
2272         /* IVB wants error correction enabled */
2273         if (IS_IVYBRIDGE(dev))
2274                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2275                            FDI_FE_ERRC_ENABLE);
2276 }
2277
2278 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2279 {
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281         u32 flags = I915_READ(SOUTH_CHICKEN1);
2282
2283         flags |= FDI_PHASE_SYNC_OVR(pipe);
2284         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2285         flags |= FDI_PHASE_SYNC_EN(pipe);
2286         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2287         POSTING_READ(SOUTH_CHICKEN1);
2288 }
2289
2290 /* The FDI link training functions for ILK/Ibexpeak. */
2291 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2292 {
2293         struct drm_device *dev = crtc->dev;
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296         int pipe = intel_crtc->pipe;
2297         int plane = intel_crtc->plane;
2298         u32 reg, temp, tries;
2299
2300         /* FDI needs bits from pipe & plane first */
2301         assert_pipe_enabled(dev_priv, pipe);
2302         assert_plane_enabled(dev_priv, plane);
2303
2304         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2305            for train result */
2306         reg = FDI_RX_IMR(pipe);
2307         temp = I915_READ(reg);
2308         temp &= ~FDI_RX_SYMBOL_LOCK;
2309         temp &= ~FDI_RX_BIT_LOCK;
2310         I915_WRITE(reg, temp);
2311         I915_READ(reg);
2312         udelay(150);
2313
2314         /* enable CPU FDI TX and PCH FDI RX */
2315         reg = FDI_TX_CTL(pipe);
2316         temp = I915_READ(reg);
2317         temp &= ~(7 << 19);
2318         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2319         temp &= ~FDI_LINK_TRAIN_NONE;
2320         temp |= FDI_LINK_TRAIN_PATTERN_1;
2321         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2322
2323         reg = FDI_RX_CTL(pipe);
2324         temp = I915_READ(reg);
2325         temp &= ~FDI_LINK_TRAIN_NONE;
2326         temp |= FDI_LINK_TRAIN_PATTERN_1;
2327         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2328
2329         POSTING_READ(reg);
2330         udelay(150);
2331
2332         /* Ironlake workaround, enable clock pointer after FDI enable*/
2333         if (HAS_PCH_IBX(dev)) {
2334                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2335                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2336                            FDI_RX_PHASE_SYNC_POINTER_EN);
2337         }
2338
2339         reg = FDI_RX_IIR(pipe);
2340         for (tries = 0; tries < 5; tries++) {
2341                 temp = I915_READ(reg);
2342                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2343
2344                 if ((temp & FDI_RX_BIT_LOCK)) {
2345                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2346                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2347                         break;
2348                 }
2349         }
2350         if (tries == 5)
2351                 DRM_ERROR("FDI train 1 fail!\n");
2352
2353         /* Train 2 */
2354         reg = FDI_TX_CTL(pipe);
2355         temp = I915_READ(reg);
2356         temp &= ~FDI_LINK_TRAIN_NONE;
2357         temp |= FDI_LINK_TRAIN_PATTERN_2;
2358         I915_WRITE(reg, temp);
2359
2360         reg = FDI_RX_CTL(pipe);
2361         temp = I915_READ(reg);
2362         temp &= ~FDI_LINK_TRAIN_NONE;
2363         temp |= FDI_LINK_TRAIN_PATTERN_2;
2364         I915_WRITE(reg, temp);
2365
2366         POSTING_READ(reg);
2367         udelay(150);
2368
2369         reg = FDI_RX_IIR(pipe);
2370         for (tries = 0; tries < 5; tries++) {
2371                 temp = I915_READ(reg);
2372                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2373
2374                 if (temp & FDI_RX_SYMBOL_LOCK) {
2375                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2376                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2377                         break;
2378                 }
2379         }
2380         if (tries == 5)
2381                 DRM_ERROR("FDI train 2 fail!\n");
2382
2383         DRM_DEBUG_KMS("FDI train done\n");
2384
2385 }
2386
2387 static const int snb_b_fdi_train_param [] = {
2388         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2389         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2390         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2391         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2392 };
2393
2394 /* The FDI link training functions for SNB/Cougarpoint. */
2395 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2396 {
2397         struct drm_device *dev = crtc->dev;
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400         int pipe = intel_crtc->pipe;
2401         u32 reg, temp, i;
2402
2403         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2404            for train result */
2405         reg = FDI_RX_IMR(pipe);
2406         temp = I915_READ(reg);
2407         temp &= ~FDI_RX_SYMBOL_LOCK;
2408         temp &= ~FDI_RX_BIT_LOCK;
2409         I915_WRITE(reg, temp);
2410
2411         POSTING_READ(reg);
2412         udelay(150);
2413
2414         /* enable CPU FDI TX and PCH FDI RX */
2415         reg = FDI_TX_CTL(pipe);
2416         temp = I915_READ(reg);
2417         temp &= ~(7 << 19);
2418         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2419         temp &= ~FDI_LINK_TRAIN_NONE;
2420         temp |= FDI_LINK_TRAIN_PATTERN_1;
2421         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2422         /* SNB-B */
2423         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2424         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2425
2426         reg = FDI_RX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         if (HAS_PCH_CPT(dev)) {
2429                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2430                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2431         } else {
2432                 temp &= ~FDI_LINK_TRAIN_NONE;
2433                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         }
2435         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437         POSTING_READ(reg);
2438         udelay(150);
2439
2440         if (HAS_PCH_CPT(dev))
2441                 cpt_phase_pointer_enable(dev, pipe);
2442
2443         for (i = 0; i < 4; i++ ) {
2444                 reg = FDI_TX_CTL(pipe);
2445                 temp = I915_READ(reg);
2446                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447                 temp |= snb_b_fdi_train_param[i];
2448                 I915_WRITE(reg, temp);
2449
2450                 POSTING_READ(reg);
2451                 udelay(500);
2452
2453                 reg = FDI_RX_IIR(pipe);
2454                 temp = I915_READ(reg);
2455                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2456
2457                 if (temp & FDI_RX_BIT_LOCK) {
2458                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2459                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2460                         break;
2461                 }
2462         }
2463         if (i == 4)
2464                 DRM_ERROR("FDI train 1 fail!\n");
2465
2466         /* Train 2 */
2467         reg = FDI_TX_CTL(pipe);
2468         temp = I915_READ(reg);
2469         temp &= ~FDI_LINK_TRAIN_NONE;
2470         temp |= FDI_LINK_TRAIN_PATTERN_2;
2471         if (IS_GEN6(dev)) {
2472                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473                 /* SNB-B */
2474                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2475         }
2476         I915_WRITE(reg, temp);
2477
2478         reg = FDI_RX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         if (HAS_PCH_CPT(dev)) {
2481                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2482                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2483         } else {
2484                 temp &= ~FDI_LINK_TRAIN_NONE;
2485                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2486         }
2487         I915_WRITE(reg, temp);
2488
2489         POSTING_READ(reg);
2490         udelay(150);
2491
2492         for (i = 0; i < 4; i++ ) {
2493                 reg = FDI_TX_CTL(pipe);
2494                 temp = I915_READ(reg);
2495                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2496                 temp |= snb_b_fdi_train_param[i];
2497                 I915_WRITE(reg, temp);
2498
2499                 POSTING_READ(reg);
2500                 udelay(500);
2501
2502                 reg = FDI_RX_IIR(pipe);
2503                 temp = I915_READ(reg);
2504                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505
2506                 if (temp & FDI_RX_SYMBOL_LOCK) {
2507                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2508                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2509                         break;
2510                 }
2511         }
2512         if (i == 4)
2513                 DRM_ERROR("FDI train 2 fail!\n");
2514
2515         DRM_DEBUG_KMS("FDI train done.\n");
2516 }
2517
2518 /* Manual link training for Ivy Bridge A0 parts */
2519 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2520 {
2521         struct drm_device *dev = crtc->dev;
2522         struct drm_i915_private *dev_priv = dev->dev_private;
2523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2524         int pipe = intel_crtc->pipe;
2525         u32 reg, temp, i;
2526
2527         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2528            for train result */
2529         reg = FDI_RX_IMR(pipe);
2530         temp = I915_READ(reg);
2531         temp &= ~FDI_RX_SYMBOL_LOCK;
2532         temp &= ~FDI_RX_BIT_LOCK;
2533         I915_WRITE(reg, temp);
2534
2535         POSTING_READ(reg);
2536         udelay(150);
2537
2538         /* enable CPU FDI TX and PCH FDI RX */
2539         reg = FDI_TX_CTL(pipe);
2540         temp = I915_READ(reg);
2541         temp &= ~(7 << 19);
2542         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2543         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2544         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2545         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2546         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2547         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2548
2549         reg = FDI_RX_CTL(pipe);
2550         temp = I915_READ(reg);
2551         temp &= ~FDI_LINK_TRAIN_AUTO;
2552         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2554         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         if (HAS_PCH_CPT(dev))
2560                 cpt_phase_pointer_enable(dev, pipe);
2561
2562         for (i = 0; i < 4; i++ ) {
2563                 reg = FDI_TX_CTL(pipe);
2564                 temp = I915_READ(reg);
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 temp |= snb_b_fdi_train_param[i];
2567                 I915_WRITE(reg, temp);
2568
2569                 POSTING_READ(reg);
2570                 udelay(500);
2571
2572                 reg = FDI_RX_IIR(pipe);
2573                 temp = I915_READ(reg);
2574                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575
2576                 if (temp & FDI_RX_BIT_LOCK ||
2577                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2578                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2579                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2580                         break;
2581                 }
2582         }
2583         if (i == 4)
2584                 DRM_ERROR("FDI train 1 fail!\n");
2585
2586         /* Train 2 */
2587         reg = FDI_TX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2590         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2591         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2593         I915_WRITE(reg, temp);
2594
2595         reg = FDI_RX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2599         I915_WRITE(reg, temp);
2600
2601         POSTING_READ(reg);
2602         udelay(150);
2603
2604         for (i = 0; i < 4; i++ ) {
2605                 reg = FDI_TX_CTL(pipe);
2606                 temp = I915_READ(reg);
2607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608                 temp |= snb_b_fdi_train_param[i];
2609                 I915_WRITE(reg, temp);
2610
2611                 POSTING_READ(reg);
2612                 udelay(500);
2613
2614                 reg = FDI_RX_IIR(pipe);
2615                 temp = I915_READ(reg);
2616                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617
2618                 if (temp & FDI_RX_SYMBOL_LOCK) {
2619                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2620                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2621                         break;
2622                 }
2623         }
2624         if (i == 4)
2625                 DRM_ERROR("FDI train 2 fail!\n");
2626
2627         DRM_DEBUG_KMS("FDI train done.\n");
2628 }
2629
2630 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2631 {
2632         struct drm_device *dev = crtc->dev;
2633         struct drm_i915_private *dev_priv = dev->dev_private;
2634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635         int pipe = intel_crtc->pipe;
2636         u32 reg, temp;
2637
2638         /* Write the TU size bits so error detection works */
2639         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2640                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2641
2642         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~((0x7 << 19) | (0x7 << 16));
2646         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2647         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2648         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2649
2650         POSTING_READ(reg);
2651         udelay(200);
2652
2653         /* Switch from Rawclk to PCDclk */
2654         temp = I915_READ(reg);
2655         I915_WRITE(reg, temp | FDI_PCDCLK);
2656
2657         POSTING_READ(reg);
2658         udelay(200);
2659
2660         /* Enable CPU FDI TX PLL, always on for Ironlake */
2661         reg = FDI_TX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2664                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2665
2666                 POSTING_READ(reg);
2667                 udelay(100);
2668         }
2669 }
2670
2671 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2672 {
2673         struct drm_i915_private *dev_priv = dev->dev_private;
2674         u32 flags = I915_READ(SOUTH_CHICKEN1);
2675
2676         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2677         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2678         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2679         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2680         POSTING_READ(SOUTH_CHICKEN1);
2681 }
2682 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2683 {
2684         struct drm_device *dev = crtc->dev;
2685         struct drm_i915_private *dev_priv = dev->dev_private;
2686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687         int pipe = intel_crtc->pipe;
2688         u32 reg, temp;
2689
2690         /* disable CPU FDI tx and PCH FDI rx */
2691         reg = FDI_TX_CTL(pipe);
2692         temp = I915_READ(reg);
2693         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2694         POSTING_READ(reg);
2695
2696         reg = FDI_RX_CTL(pipe);
2697         temp = I915_READ(reg);
2698         temp &= ~(0x7 << 16);
2699         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2700         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2701
2702         POSTING_READ(reg);
2703         udelay(100);
2704
2705         /* Ironlake workaround, disable clock pointer after downing FDI */
2706         if (HAS_PCH_IBX(dev)) {
2707                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2708                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2709                            I915_READ(FDI_RX_CHICKEN(pipe) &
2710                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2711         } else if (HAS_PCH_CPT(dev)) {
2712                 cpt_phase_pointer_disable(dev, pipe);
2713         }
2714
2715         /* still set train pattern 1 */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_LINK_TRAIN_NONE;
2719         temp |= FDI_LINK_TRAIN_PATTERN_1;
2720         I915_WRITE(reg, temp);
2721
2722         reg = FDI_RX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         if (HAS_PCH_CPT(dev)) {
2725                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2727         } else {
2728                 temp &= ~FDI_LINK_TRAIN_NONE;
2729                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2730         }
2731         /* BPC in FDI rx is consistent with that in PIPECONF */
2732         temp &= ~(0x07 << 16);
2733         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2734         I915_WRITE(reg, temp);
2735
2736         POSTING_READ(reg);
2737         udelay(100);
2738 }
2739
2740 /*
2741  * When we disable a pipe, we need to clear any pending scanline wait events
2742  * to avoid hanging the ring, which we assume we are waiting on.
2743  */
2744 static void intel_clear_scanline_wait(struct drm_device *dev)
2745 {
2746         struct drm_i915_private *dev_priv = dev->dev_private;
2747         struct intel_ring_buffer *ring;
2748         u32 tmp;
2749
2750         if (IS_GEN2(dev))
2751                 /* Can't break the hang on i8xx */
2752                 return;
2753
2754         ring = LP_RING(dev_priv);
2755         tmp = I915_READ_CTL(ring);
2756         if (tmp & RING_WAIT)
2757                 I915_WRITE_CTL(ring, tmp);
2758 }
2759
2760 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2761 {
2762         struct drm_i915_gem_object *obj;
2763         struct drm_i915_private *dev_priv;
2764
2765         if (crtc->fb == NULL)
2766                 return;
2767
2768         obj = to_intel_framebuffer(crtc->fb)->obj;
2769         dev_priv = crtc->dev->dev_private;
2770         wait_event(dev_priv->pending_flip_queue,
2771                    atomic_read(&obj->pending_flip) == 0);
2772 }
2773
2774 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2775 {
2776         struct drm_device *dev = crtc->dev;
2777         struct drm_mode_config *mode_config = &dev->mode_config;
2778         struct intel_encoder *encoder;
2779
2780         /*
2781          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2782          * must be driven by its own crtc; no sharing is possible.
2783          */
2784         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2785                 if (encoder->base.crtc != crtc)
2786                         continue;
2787
2788                 switch (encoder->type) {
2789                 case INTEL_OUTPUT_EDP:
2790                         if (!intel_encoder_is_pch_edp(&encoder->base))
2791                                 return false;
2792                         continue;
2793                 }
2794         }
2795
2796         return true;
2797 }
2798
2799 /*
2800  * Enable PCH resources required for PCH ports:
2801  *   - PCH PLLs
2802  *   - FDI training & RX/TX
2803  *   - update transcoder timings
2804  *   - DP transcoding bits
2805  *   - transcoder
2806  */
2807 static void ironlake_pch_enable(struct drm_crtc *crtc)
2808 {
2809         struct drm_device *dev = crtc->dev;
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2812         int pipe = intel_crtc->pipe;
2813         u32 reg, temp;
2814
2815         /* For PCH output, training FDI link */
2816         dev_priv->display.fdi_link_train(crtc);
2817
2818         intel_enable_pch_pll(dev_priv, pipe);
2819
2820         if (HAS_PCH_CPT(dev)) {
2821                 /* Be sure PCH DPLL SEL is set */
2822                 temp = I915_READ(PCH_DPLL_SEL);
2823                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2824                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2825                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2826                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2827                 I915_WRITE(PCH_DPLL_SEL, temp);
2828         }
2829
2830         /* set transcoder timing, panel must allow it */
2831         assert_panel_unlocked(dev_priv, pipe);
2832         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2833         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2834         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2835
2836         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2837         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2838         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2839
2840         intel_fdi_normal_train(crtc);
2841
2842         /* For PCH DP, enable TRANS_DP_CTL */
2843         if (HAS_PCH_CPT(dev) &&
2844             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2845                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2846                 reg = TRANS_DP_CTL(pipe);
2847                 temp = I915_READ(reg);
2848                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2849                           TRANS_DP_SYNC_MASK |
2850                           TRANS_DP_BPC_MASK);
2851                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2852                          TRANS_DP_ENH_FRAMING);
2853                 temp |= bpc << 9; /* same format but at 11:9 */
2854
2855                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2856                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2857                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2858                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2859
2860                 switch (intel_trans_dp_port_sel(crtc)) {
2861                 case PCH_DP_B:
2862                         temp |= TRANS_DP_PORT_SEL_B;
2863                         break;
2864                 case PCH_DP_C:
2865                         temp |= TRANS_DP_PORT_SEL_C;
2866                         break;
2867                 case PCH_DP_D:
2868                         temp |= TRANS_DP_PORT_SEL_D;
2869                         break;
2870                 default:
2871                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2872                         temp |= TRANS_DP_PORT_SEL_B;
2873                         break;
2874                 }
2875
2876                 I915_WRITE(reg, temp);
2877         }
2878
2879         intel_enable_transcoder(dev_priv, pipe);
2880 }
2881
2882 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2883 {
2884         struct drm_device *dev = crtc->dev;
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2887         int pipe = intel_crtc->pipe;
2888         int plane = intel_crtc->plane;
2889         u32 temp;
2890         bool is_pch_port;
2891
2892         if (intel_crtc->active)
2893                 return;
2894
2895         intel_crtc->active = true;
2896         intel_update_watermarks(dev);
2897
2898         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2899                 temp = I915_READ(PCH_LVDS);
2900                 if ((temp & LVDS_PORT_EN) == 0)
2901                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2902         }
2903
2904         is_pch_port = intel_crtc_driving_pch(crtc);
2905
2906         if (is_pch_port)
2907                 ironlake_fdi_pll_enable(crtc);
2908         else
2909                 ironlake_fdi_disable(crtc);
2910
2911         /* Enable panel fitting for LVDS */
2912         if (dev_priv->pch_pf_size &&
2913             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2914                 /* Force use of hard-coded filter coefficients
2915                  * as some pre-programmed values are broken,
2916                  * e.g. x201.
2917                  */
2918                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2919                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2920                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2921         }
2922
2923         /*
2924          * On ILK+ LUT must be loaded before the pipe is running but with
2925          * clocks enabled
2926          */
2927         intel_crtc_load_lut(crtc);
2928
2929         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2930         intel_enable_plane(dev_priv, plane, pipe);
2931
2932         if (is_pch_port)
2933                 ironlake_pch_enable(crtc);
2934
2935         mutex_lock(&dev->struct_mutex);
2936         intel_update_fbc(dev);
2937         mutex_unlock(&dev->struct_mutex);
2938
2939         intel_crtc_update_cursor(crtc, true);
2940 }
2941
2942 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2943 {
2944         struct drm_device *dev = crtc->dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947         int pipe = intel_crtc->pipe;
2948         int plane = intel_crtc->plane;
2949         u32 reg, temp;
2950
2951         if (!intel_crtc->active)
2952                 return;
2953
2954         intel_crtc_wait_for_pending_flips(crtc);
2955         drm_vblank_off(dev, pipe);
2956         intel_crtc_update_cursor(crtc, false);
2957
2958         intel_disable_plane(dev_priv, plane, pipe);
2959
2960         if (dev_priv->cfb_plane == plane)
2961                 intel_disable_fbc(dev);
2962
2963         intel_disable_pipe(dev_priv, pipe);
2964
2965         /* Disable PF */
2966         I915_WRITE(PF_CTL(pipe), 0);
2967         I915_WRITE(PF_WIN_SZ(pipe), 0);
2968
2969         ironlake_fdi_disable(crtc);
2970
2971         /* This is a horrible layering violation; we should be doing this in
2972          * the connector/encoder ->prepare instead, but we don't always have
2973          * enough information there about the config to know whether it will
2974          * actually be necessary or just cause undesired flicker.
2975          */
2976         intel_disable_pch_ports(dev_priv, pipe);
2977
2978         intel_disable_transcoder(dev_priv, pipe);
2979
2980         if (HAS_PCH_CPT(dev)) {
2981                 /* disable TRANS_DP_CTL */
2982                 reg = TRANS_DP_CTL(pipe);
2983                 temp = I915_READ(reg);
2984                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2985                 temp |= TRANS_DP_PORT_SEL_NONE;
2986                 I915_WRITE(reg, temp);
2987
2988                 /* disable DPLL_SEL */
2989                 temp = I915_READ(PCH_DPLL_SEL);
2990                 switch (pipe) {
2991                 case 0:
2992                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2993                         break;
2994                 case 1:
2995                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2996                         break;
2997                 case 2:
2998                         /* FIXME: manage transcoder PLLs? */
2999                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3000                         break;
3001                 default:
3002                         BUG(); /* wtf */
3003                 }
3004                 I915_WRITE(PCH_DPLL_SEL, temp);
3005         }
3006
3007         /* disable PCH DPLL */
3008         intel_disable_pch_pll(dev_priv, pipe);
3009
3010         /* Switch from PCDclk to Rawclk */
3011         reg = FDI_RX_CTL(pipe);
3012         temp = I915_READ(reg);
3013         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3014
3015         /* Disable CPU FDI TX PLL */
3016         reg = FDI_TX_CTL(pipe);
3017         temp = I915_READ(reg);
3018         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3019
3020         POSTING_READ(reg);
3021         udelay(100);
3022
3023         reg = FDI_RX_CTL(pipe);
3024         temp = I915_READ(reg);
3025         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3026
3027         /* Wait for the clocks to turn off. */
3028         POSTING_READ(reg);
3029         udelay(100);
3030
3031         intel_crtc->active = false;
3032         intel_update_watermarks(dev);
3033
3034         mutex_lock(&dev->struct_mutex);
3035         intel_update_fbc(dev);
3036         intel_clear_scanline_wait(dev);
3037         mutex_unlock(&dev->struct_mutex);
3038 }
3039
3040 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3041 {
3042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043         int pipe = intel_crtc->pipe;
3044         int plane = intel_crtc->plane;
3045
3046         /* XXX: When our outputs are all unaware of DPMS modes other than off
3047          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3048          */
3049         switch (mode) {
3050         case DRM_MODE_DPMS_ON:
3051         case DRM_MODE_DPMS_STANDBY:
3052         case DRM_MODE_DPMS_SUSPEND:
3053                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3054                 ironlake_crtc_enable(crtc);
3055                 break;
3056
3057         case DRM_MODE_DPMS_OFF:
3058                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3059                 ironlake_crtc_disable(crtc);
3060                 break;
3061         }
3062 }
3063
3064 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3065 {
3066         if (!enable && intel_crtc->overlay) {
3067                 struct drm_device *dev = intel_crtc->base.dev;
3068                 struct drm_i915_private *dev_priv = dev->dev_private;
3069
3070                 mutex_lock(&dev->struct_mutex);
3071                 dev_priv->mm.interruptible = false;
3072                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3073                 dev_priv->mm.interruptible = true;
3074                 mutex_unlock(&dev->struct_mutex);
3075         }
3076