drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static const intel_limit_t intel_limits_i8xx_dvo = {
 346         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 347         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 348         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 349         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 350         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 351         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 352         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 353         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 354         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 355                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 356         .find_pll = intel_find_best_PLL,
 357 };
 358
 359 static const intel_limit_t intel_limits_i8xx_lvds = {
 360         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 361         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 362         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 363         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 364         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 365         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 366         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 367         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 368         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 369                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 370         .find_pll = intel_find_best_PLL,
 371 };
 372
 373 static const intel_limit_t intel_limits_i9xx_sdvo = {
 374         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 375         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 376         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 377         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 378         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 379         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 380         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 381         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 382         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 383                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 384         .find_pll = intel_find_best_PLL,
 385 };
 386
 387 static const intel_limit_t intel_limits_i9xx_lvds = {
 388         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 389         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 390         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 391         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 392         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 393         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 394         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 395         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 396         /* The single-channel range is 25-112Mhz, and dual-channel
 397          * is 80-224Mhz.  Prefer single channel as much as possible.
 398          */
 399         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 400                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 401         .find_pll = intel_find_best_PLL,
 402 };
 403
 404     /* below parameter and function is for G4X Chipset Family*/
 405 static const intel_limit_t intel_limits_g4x_sdvo = {
 406         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 407         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 408         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 409         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 410         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 411         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 412         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 413         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 414         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 415                  .p2_slow = G4X_P2_SDVO_SLOW,
 416                  .p2_fast = G4X_P2_SDVO_FAST
 417         },
 418         .find_pll = intel_g4x_find_best_PLL,
 419 };
 420
 421 static const intel_limit_t intel_limits_g4x_hdmi = {
 422         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 423         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 424         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 425         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 426         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 427         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 428         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 429         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 430         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 431                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 432                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 433         },
 434         .find_pll = intel_g4x_find_best_PLL,
 435 };
 436
 437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 438         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 440         .vco = { .min = G4X_VCO_MIN,
 441                  .max = G4X_VCO_MAX },
 442         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 444         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 446         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 448         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 450         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 452         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 454         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 455                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 456                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 457         },
 458         .find_pll = intel_g4x_find_best_PLL,
 459 };
 460
 461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 462         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 464         .vco = { .min = G4X_VCO_MIN,
 465                  .max = G4X_VCO_MAX },
 466         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 468         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 470         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 472         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 474         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 476         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 478         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 479                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 480                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 481         },
 482         .find_pll = intel_g4x_find_best_PLL,
 483 };
 484
 485 static const intel_limit_t intel_limits_g4x_display_port = {
 486         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 487                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 488         .vco = { .min = G4X_VCO_MIN,
 489                  .max = G4X_VCO_MAX},
 490         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 491                  .max = G4X_N_DISPLAY_PORT_MAX },
 492         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 493                  .max = G4X_M_DISPLAY_PORT_MAX },
 494         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 495                  .max = G4X_M1_DISPLAY_PORT_MAX },
 496         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 497                  .max = G4X_M2_DISPLAY_PORT_MAX },
 498         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 499                  .max = G4X_P_DISPLAY_PORT_MAX },
 500         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 501                  .max = G4X_P1_DISPLAY_PORT_MAX},
 502         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 503                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 504                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 505         .find_pll = intel_find_pll_g4x_dp,
 506 };
 507
 508 static const intel_limit_t intel_limits_pineview_sdvo = {
 509         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 510         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 511         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 512         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 513         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 514         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 515         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 516         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 517         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 518                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 519         .find_pll = intel_find_best_PLL,
 520 };
 521
 522 static const intel_limit_t intel_limits_pineview_lvds = {
 523         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 524         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 525         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 526         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 527         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 528         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 529         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 530         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 531         /* Pineview only supports single-channel mode. */
 532         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 533                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 534         .find_pll = intel_find_best_PLL,
 535 };
 536
 537 static const intel_limit_t intel_limits_ironlake_dac = {
 538         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 539         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 540         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 541         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 542         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 543         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 544         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 545         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 546         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 547                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 548                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 549         .find_pll = intel_g4x_find_best_PLL,
 550 };
 551
 552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 553         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 554         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 555         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 556         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 557         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 558         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 559         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 560         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 561         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 562                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 563                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 564         .find_pll = intel_g4x_find_best_PLL,
 565 };
 566
 567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 568         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 569         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 570         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 571         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 572         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 573         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 574         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 575         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 576         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 577                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 578                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 579         .find_pll = intel_g4x_find_best_PLL,
 580 };
 581
 582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 583         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 584         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 585         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 586         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 587         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 588         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 589         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 590         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 591         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 592                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 593                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 594         .find_pll = intel_g4x_find_best_PLL,
 595 };
 596
 597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 598         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 599         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 600         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 601         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 602         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 603         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 604         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 605         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 606         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 607                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 608                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 609         .find_pll = intel_g4x_find_best_PLL,
 610 };
 611
 612 static const intel_limit_t intel_limits_ironlake_display_port = {
 613         .dot = { .min = IRONLAKE_DOT_MIN,
 614                  .max = IRONLAKE_DOT_MAX },
 615         .vco = { .min = IRONLAKE_VCO_MIN,
 616                  .max = IRONLAKE_VCO_MAX},
 617         .n   = { .min = IRONLAKE_DP_N_MIN,
 618                  .max = IRONLAKE_DP_N_MAX },
 619         .m   = { .min = IRONLAKE_DP_M_MIN,
 620                  .max = IRONLAKE_DP_M_MAX },
 621         .m1  = { .min = IRONLAKE_M1_MIN,
 622                  .max = IRONLAKE_M1_MAX },
 623         .m2  = { .min = IRONLAKE_M2_MIN,
 624                  .max = IRONLAKE_M2_MAX },
 625         .p   = { .min = IRONLAKE_DP_P_MIN,
 626                  .max = IRONLAKE_DP_P_MAX },
 627         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 628                  .max = IRONLAKE_DP_P1_MAX},
 629         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 630                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 631                  .p2_fast = IRONLAKE_DP_P2_FAST },
 632         .find_pll = intel_find_pll_ironlake_dp,
 633 };
 634
 635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 636 {
 637         struct drm_device *dev = crtc->dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         const intel_limit_t *limit;
 640         int refclk = 120;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 644                         refclk = 100;
 645
 646                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 647                     LVDS_CLKB_POWER_UP) {
 648                         /* LVDS dual channel */
 649                         if (refclk == 100)
 650                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 651                         else
 652                                 limit = &intel_limits_ironlake_dual_lvds;
 653                 } else {
 654                         if (refclk == 100)
 655                                 limit = &intel_limits_ironlake_single_lvds_100m;
 656                         else
 657                                 limit = &intel_limits_ironlake_single_lvds;
 658                 }
 659         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 660                         HAS_eDP)
 661                 limit = &intel_limits_ironlake_display_port;
 662         else
 663                 limit = &intel_limits_ironlake_dac;
 664
 665         return limit;
 666 }
 667
 668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         const intel_limit_t *limit;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 676                     LVDS_CLKB_POWER_UP)
 677                         /* LVDS with dual channel */
 678                         limit = &intel_limits_g4x_dual_channel_lvds;
 679                 else
 680                         /* LVDS with dual channel */
 681                         limit = &intel_limits_g4x_single_channel_lvds;
 682         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 683                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 684                 limit = &intel_limits_g4x_hdmi;
 685         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 686                 limit = &intel_limits_g4x_sdvo;
 687         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 688                 limit = &intel_limits_g4x_display_port;
 689         } else /* The option is for other outputs */
 690                 limit = &intel_limits_i9xx_sdvo;
 691
 692         return limit;
 693 }
 694
 695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 696 {
 697         struct drm_device *dev = crtc->dev;
 698         const intel_limit_t *limit;
 699
 700         if (HAS_PCH_SPLIT(dev))
 701                 limit = intel_ironlake_limit(crtc);
 702         else if (IS_G4X(dev)) {
 703                 limit = intel_g4x_limit(crtc);
 704         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 705                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 706                         limit = &intel_limits_i9xx_lvds;
 707                 else
 708                         limit = &intel_limits_i9xx_sdvo;
 709         } else if (IS_PINEVIEW(dev)) {
 710                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 711                         limit = &intel_limits_pineview_lvds;
 712                 else
 713                         limit = &intel_limits_pineview_sdvo;
 714         } else {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_i8xx_lvds;
 717                 else
 718                         limit = &intel_limits_i8xx_dvo;
 719         }
 720         return limit;
 721 }
 722
 723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 724 static void pineview_clock(int refclk, intel_clock_t *clock)
 725 {
 726         clock->m = clock->m2 + 2;
 727         clock->p = clock->p1 * clock->p2;
 728         clock->vco = refclk * clock->m / clock->n;
 729         clock->dot = clock->vco / clock->p;
 730 }
 731
 732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 733 {
 734         if (IS_PINEVIEW(dev)) {
 735                 pineview_clock(refclk, clock);
 736                 return;
 737         }
 738         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 739         clock->p = clock->p1 * clock->p2;
 740         clock->vco = refclk * clock->m / (clock->n + 2);
 741         clock->dot = clock->vco / clock->p;
 742 }
 743
 744 /**
 745  * Returns whether any output on the specified pipe is of the specified type
 746  */
 747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 748 {
 749     struct drm_device *dev = crtc->dev;
 750     struct drm_mode_config *mode_config = &dev->mode_config;
 751     struct drm_encoder *l_entry;
 752
 753     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 754             if (l_entry && l_entry->crtc == crtc) {
 755                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 756                     if (intel_encoder->type == type)
 757                             return true;
 758             }
 759     }
 760     return false;
 761 }
 762
 763 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 764 /**
 765  * Returns whether the given set of divisors are valid for a given refclk with
 766  * the given connectors.
 767  */
 768
 769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 770 {
 771         const intel_limit_t *limit = intel_limit (crtc);
 772         struct drm_device *dev = crtc->dev;
 773
 774         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 775                 INTELPllInvalid ("p1 out of range\n");
 776         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 777                 INTELPllInvalid ("p out of range\n");
 778         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 779                 INTELPllInvalid ("m2 out of range\n");
 780         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 781                 INTELPllInvalid ("m1 out of range\n");
 782         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 783                 INTELPllInvalid ("m1 <= m2\n");
 784         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 785                 INTELPllInvalid ("m out of range\n");
 786         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 787                 INTELPllInvalid ("n out of range\n");
 788         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 789                 INTELPllInvalid ("vco out of range\n");
 790         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 791          * connector, etc., rather than just a single range.
 792          */
 793         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 794                 INTELPllInvalid ("dot out of range\n");
 795
 796         return true;
 797 }
 798
 799 static bool
 800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 801                     int target, int refclk, intel_clock_t *best_clock)
 802
 803 {
 804         struct drm_device *dev = crtc->dev;
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         intel_clock_t clock;
 807         int err = target;
 808
 809         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 810             (I915_READ(LVDS)) != 0) {
 811                 /*
 812                  * For LVDS, if the panel is on, just rely on its current
 813                  * settings for dual-channel.  We haven't figured out how to
 814                  * reliably set up different single/dual channel state, if we
 815                  * even can.
 816                  */
 817                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 818                     LVDS_CLKB_POWER_UP)
 819                         clock.p2 = limit->p2.p2_fast;
 820                 else
 821                         clock.p2 = limit->p2.p2_slow;
 822         } else {
 823                 if (target < limit->p2.dot_limit)
 824                         clock.p2 = limit->p2.p2_slow;
 825                 else
 826                         clock.p2 = limit->p2.p2_fast;
 827         }
 828
 829         memset (best_clock, 0, sizeof (*best_clock));
 830
 831         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 832              clock.m1++) {
 833                 for (clock.m2 = limit->m2.min;
 834                      clock.m2 <= limit->m2.max; clock.m2++) {
 835                         /* m1 is always 0 in Pineview */
 836                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 837                                 break;
 838                         for (clock.n = limit->n.min;
 839                              clock.n <= limit->n.max; clock.n++) {
 840                                 for (clock.p1 = limit->p1.min;
 841                                         clock.p1 <= limit->p1.max; clock.p1++) {
 842                                         int this_err;
 843
 844                                         intel_clock(dev, refclk, &clock);
 845
 846                                         if (!intel_PLL_is_valid(crtc, &clock))
 847                                                 continue;
 848
 849                                         this_err = abs(clock.dot - target);
 850                                         if (this_err < err) {
 851                                                 *best_clock = clock;
 852                                                 err = this_err;
 853                                         }
 854                                 }
 855                         }
 856                 }
 857         }
 858
 859         return (err != target);
 860 }
 861
 862 static bool
 863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 864                         int target, int refclk, intel_clock_t *best_clock)
 865 {
 866         struct drm_device *dev = crtc->dev;
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868         intel_clock_t clock;
 869         int max_n;
 870         bool found;
 871         /* approximately equals target * 0.00585 */
 872         int err_most = (target >> 8) + (target >> 9);
 873         found = false;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 876                 int lvds_reg;
 877
 878                 if (HAS_PCH_SPLIT(dev))
 879                         lvds_reg = PCH_LVDS;
 880                 else
 881                         lvds_reg = LVDS;
 882                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 883                     LVDS_CLKB_POWER_UP)
 884                         clock.p2 = limit->p2.p2_fast;
 885                 else
 886                         clock.p2 = limit->p2.p2_slow;
 887         } else {
 888                 if (target < limit->p2.dot_limit)
 889                         clock.p2 = limit->p2.p2_slow;
 890                 else
 891                         clock.p2 = limit->p2.p2_fast;
 892         }
 893
 894         memset(best_clock, 0, sizeof(*best_clock));
 895         max_n = limit->n.max;
 896         /* based on hardware requirement, prefer smaller n to precision */
 897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 898                 /* based on hardware requirement, prefere larger m1,m2 */
 899                 for (clock.m1 = limit->m1.max;
 900                      clock.m1 >= limit->m1.min; clock.m1--) {
 901                         for (clock.m2 = limit->m2.max;
 902                              clock.m2 >= limit->m2.min; clock.m2--) {
 903                                 for (clock.p1 = limit->p1.max;
 904                                      clock.p1 >= limit->p1.min; clock.p1--) {
 905                                         int this_err;
 906
 907                                         intel_clock(dev, refclk, &clock);
 908                                         if (!intel_PLL_is_valid(crtc, &clock))
 909                                                 continue;
 910                                         this_err = abs(clock.dot - target) ;
 911                                         if (this_err < err_most) {
 912                                                 *best_clock = clock;
 913                                                 err_most = this_err;
 914                                                 max_n = clock.n;
 915                                                 found = true;
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         return found;
 922 }
 923
 924 static bool
 925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 926                            int target, int refclk, intel_clock_t *best_clock)
 927 {
 928         struct drm_device *dev = crtc->dev;
 929         intel_clock_t clock;
 930
 931         /* return directly when it is eDP */
 932         if (HAS_eDP)
 933                 return true;
 934
 935         if (target < 200000) {
 936                 clock.n = 1;
 937                 clock.p1 = 2;
 938                 clock.p2 = 10;
 939                 clock.m1 = 12;
 940                 clock.m2 = 9;
 941         } else {
 942                 clock.n = 2;
 943                 clock.p1 = 1;
 944                 clock.p2 = 10;
 945                 clock.m1 = 14;
 946                 clock.m2 = 8;
 947         }
 948         intel_clock(dev, refclk, &clock);
 949         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 950         return true;
 951 }
 952
 953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 954 static bool
 955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 956                       int target, int refclk, intel_clock_t *best_clock)
 957 {
 958     intel_clock_t clock;
 959     if (target < 200000) {
 960         clock.p1 = 2;
 961         clock.p2 = 10;
 962         clock.n = 2;
 963         clock.m1 = 23;
 964         clock.m2 = 8;
 965     } else {
 966         clock.p1 = 1;
 967         clock.p2 = 10;
 968         clock.n = 1;
 969         clock.m1 = 14;
 970         clock.m2 = 2;
 971     }
 972     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 973     clock.p = (clock.p1 * clock.p2);
 974     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 975     clock.vco = 0;
 976     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 977     return true;
 978 }
 979
 980 /**
 981  * intel_wait_for_vblank - wait for vblank on a given pipe
 982  * @dev: drm device
 983  * @pipe: pipe to wait for
 984  *
 985  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 986  * mode setting code.
 987  */
 988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 989 {
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 992
 993         /* Clear existing vblank status. Note this will clear any other
 994          * sticky status fields as well.
 995          *
 996          * This races with i915_driver_irq_handler() with the result
 997          * that either function could miss a vblank event.  Here it is not
 998          * fatal, as we will either wait upon the next vblank interrupt or
 999          * timeout.  Generally speaking intel_wait_for_vblank() is only
1000          * called during modeset at which time the GPU should be idle and
1001          * should *not* be performing page flips and thus not waiting on
1002          * vblanks...
1003          * Currently, the result of us stealing a vblank from the irq
1004          * handler is that a single frame will be skipped during swapbuffers.
1005          */
1006         I915_WRITE(pipestat_reg,
1007                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009         /* Wait for vblank interrupt bit to set */
1010         if (wait_for((I915_READ(pipestat_reg) &
1011                       PIPE_VBLANK_INTERRUPT_STATUS),
1012                      50, 0))
1013                 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 }
1015
1016 /**
1017  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1018  * @dev: drm device
1019  * @pipe: pipe to wait for
1020  *
1021  * After disabling a pipe, we can't wait for vblank in the usual way,
1022  * spinning on the vblank interrupt status bit, since we won't actually
1023  * see an interrupt when the pipe is disabled.
1024  *
1025  * So this function waits for the display line value to settle (it
1026  * usually ends up stopping at the start of the next frame).
1027  */
1028 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1029 {
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1032         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033         u32 last_line;
1034
1035         /* Wait for the display line to settle */
1036         do {
1037                 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1038                 mdelay(5);
1039         } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1040                  time_after(timeout, jiffies));
1041
1042         if (time_after(jiffies, timeout))
1043                 DRM_DEBUG_KMS("vblank wait timed out\n");
1044 }
1045
1046 /* Parameters have changed, update FBC info */
1047 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1048 {
1049         struct drm_device *dev = crtc->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         struct drm_framebuffer *fb = crtc->fb;
1052         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1053         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1055         int plane, i;
1056         u32 fbc_ctl, fbc_ctl2;
1057
1058         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1059
1060         if (fb->pitch < dev_priv->cfb_pitch)
1061                 dev_priv->cfb_pitch = fb->pitch;
1062
1063         /* FBC_CTL wants 64B units */
1064         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1065         dev_priv->cfb_fence = obj_priv->fence_reg;
1066         dev_priv->cfb_plane = intel_crtc->plane;
1067         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1068
1069         /* Clear old tags */
1070         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1071                 I915_WRITE(FBC_TAG + (i * 4), 0);
1072
1073         /* Set it up... */
1074         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1075         if (obj_priv->tiling_mode != I915_TILING_NONE)
1076                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1077         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1078         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1079
1080         /* enable it... */
1081         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1082         if (IS_I945GM(dev))
1083                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1084         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1085         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1086         if (obj_priv->tiling_mode != I915_TILING_NONE)
1087                 fbc_ctl |= dev_priv->cfb_fence;
1088         I915_WRITE(FBC_CONTROL, fbc_ctl);
1089
1090         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1091                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1092 }
1093
1094 void i8xx_disable_fbc(struct drm_device *dev)
1095 {
1096         struct drm_i915_private *dev_priv = dev->dev_private;
1097         u32 fbc_ctl;
1098
1099         if (!I915_HAS_FBC(dev))
1100                 return;
1101
1102         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1103                 return; /* Already off, just return */
1104
1105         /* Disable compression */
1106         fbc_ctl = I915_READ(FBC_CONTROL);
1107         fbc_ctl &= ~FBC_CTL_EN;
1108         I915_WRITE(FBC_CONTROL, fbc_ctl);
1109
1110         /* Wait for compressing bit to clear */
1111         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1112                 DRM_DEBUG_KMS("FBC idle timed out\n");
1113                 return;
1114         }
1115
1116         DRM_DEBUG_KMS("disabled FBC\n");
1117 }
1118
1119 static bool i8xx_fbc_enabled(struct drm_device *dev)
1120 {
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122
1123         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1124 }
1125
1126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127 {
1128         struct drm_device *dev = crtc->dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130         struct drm_framebuffer *fb = crtc->fb;
1131         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1132         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1135                      DPFC_CTL_PLANEB);
1136         unsigned long stall_watermark = 200;
1137         u32 dpfc_ctl;
1138
1139         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1140         dev_priv->cfb_fence = obj_priv->fence_reg;
1141         dev_priv->cfb_plane = intel_crtc->plane;
1142
1143         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1144         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1145                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1146                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1147         } else {
1148                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1149         }
1150
1151         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1152         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1153                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1154                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1155         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1156
1157         /* enable it... */
1158         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1159
1160         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1161 }
1162
1163 void g4x_disable_fbc(struct drm_device *dev)
1164 {
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         u32 dpfc_ctl;
1167
1168         /* Disable compression */
1169         dpfc_ctl = I915_READ(DPFC_CONTROL);
1170         dpfc_ctl &= ~DPFC_CTL_EN;
1171         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1172
1173         DRM_DEBUG_KMS("disabled FBC\n");
1174 }
1175
1176 static bool g4x_fbc_enabled(struct drm_device *dev)
1177 {
1178         struct drm_i915_private *dev_priv = dev->dev_private;
1179
1180         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1181 }
1182
1183 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1184 {
1185         struct drm_device *dev = crtc->dev;
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         struct drm_framebuffer *fb = crtc->fb;
1188         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1189         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1191         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1192                                                DPFC_CTL_PLANEB;
1193         unsigned long stall_watermark = 200;
1194         u32 dpfc_ctl;
1195
1196         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1197         dev_priv->cfb_fence = obj_priv->fence_reg;
1198         dev_priv->cfb_plane = intel_crtc->plane;
1199
1200         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1201         dpfc_ctl &= DPFC_RESERVED;
1202         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1203         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1204                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1205                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1206         } else {
1207                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1208         }
1209
1210         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1211         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1212                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1213                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1214         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1215         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1216         /* enable it... */
1217         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1218                    DPFC_CTL_EN);
1219
1220         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1221 }
1222
1223 void ironlake_disable_fbc(struct drm_device *dev)
1224 {
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226         u32 dpfc_ctl;
1227
1228         /* Disable compression */
1229         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1230         dpfc_ctl &= ~DPFC_CTL_EN;
1231         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1232
1233         DRM_DEBUG_KMS("disabled FBC\n");
1234 }
1235
1236 static bool ironlake_fbc_enabled(struct drm_device *dev)
1237 {
1238         struct drm_i915_private *dev_priv = dev->dev_private;
1239
1240         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1241 }
1242
1243 bool intel_fbc_enabled(struct drm_device *dev)
1244 {
1245         struct drm_i915_private *dev_priv = dev->dev_private;
1246
1247         if (!dev_priv->display.fbc_enabled)
1248                 return false;
1249
1250         return dev_priv->display.fbc_enabled(dev);
1251 }
1252
1253 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1254 {
1255         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1256
1257         if (!dev_priv->display.enable_fbc)
1258                 return;
1259
1260         dev_priv->display.enable_fbc(crtc, interval);
1261 }
1262
1263 void intel_disable_fbc(struct drm_device *dev)
1264 {
1265         struct drm_i915_private *dev_priv = dev->dev_private;
1266
1267         if (!dev_priv->display.disable_fbc)
1268                 return;
1269
1270         dev_priv->display.disable_fbc(dev);
1271 }
1272
1273 /**
1274  * intel_update_fbc - enable/disable FBC as needed
1275  * @crtc: CRTC to point the compressor at
1276  * @mode: mode in use
1277  *
1278  * Set up the framebuffer compression hardware at mode set time.  We
1279  * enable it if possible:
1280  *   - plane A only (on pre-965)
1281  *   - no pixel mulitply/line duplication
1282  *   - no alpha buffer discard
1283  *   - no dual wide
1284  *   - framebuffer <= 2048 in width, 1536 in height
1285  *
1286  * We can't assume that any compression will take place (worst case),
1287  * so the compressed buffer has to be the same size as the uncompressed
1288  * one.  It also must reside (along with the line length buffer) in
1289  * stolen memory.
1290  *
1291  * We need to enable/disable FBC on a global basis.
1292  */
1293 static void intel_update_fbc(struct drm_crtc *crtc,
1294                              struct drm_display_mode *mode)
1295 {
1296         struct drm_device *dev = crtc->dev;
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         struct drm_framebuffer *fb = crtc->fb;
1299         struct intel_framebuffer *intel_fb;
1300         struct drm_i915_gem_object *obj_priv;
1301         struct drm_crtc *tmp_crtc;
1302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1303         int plane = intel_crtc->plane;
1304         int crtcs_enabled = 0;
1305
1306         DRM_DEBUG_KMS("\n");
1307
1308         if (!i915_powersave)
1309                 return;
1310
1311         if (!I915_HAS_FBC(dev))
1312                 return;
1313
1314         if (!crtc->fb)
1315                 return;
1316
1317         intel_fb = to_intel_framebuffer(fb);
1318         obj_priv = to_intel_bo(intel_fb->obj);
1319
1320         /*
1321          * If FBC is already on, we just have to verify that we can
1322          * keep it that way...
1323          * Need to disable if:
1324          *   - more than one pipe is active
1325          *   - changing FBC params (stride, fence, mode)
1326          *   - new fb is too large to fit in compressed buffer
1327          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1328          */
1329         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1330                 if (tmp_crtc->enabled)
1331                         crtcs_enabled++;
1332         }
1333         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1334         if (crtcs_enabled > 1) {
1335                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1336                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1337                 goto out_disable;
1338         }
1339         if (intel_fb->obj->size > dev_priv->cfb_size) {
1340                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1341                                 "compression\n");
1342                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1343                 goto out_disable;
1344         }
1345         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1346             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1347                 DRM_DEBUG_KMS("mode incompatible with compression, "
1348                                 "disabling\n");
1349                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1350                 goto out_disable;
1351         }
1352         if ((mode->hdisplay > 2048) ||
1353             (mode->vdisplay > 1536)) {
1354                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1355                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1356                 goto out_disable;
1357         }
1358         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1359                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1360                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1361                 goto out_disable;
1362         }
1363         if (obj_priv->tiling_mode != I915_TILING_X) {
1364                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1365                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1366                 goto out_disable;
1367         }
1368
1369         /* If the kernel debugger is active, always disable compression */
1370         if (in_dbg_master())
1371                 goto out_disable;
1372
1373         if (intel_fbc_enabled(dev)) {
1374                 /* We can re-enable it in this case, but need to update pitch */
1375                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1376                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1377                     (plane != dev_priv->cfb_plane))
1378                         intel_disable_fbc(dev);
1379         }
1380
1381         /* Now try to turn it back on if possible */
1382         if (!intel_fbc_enabled(dev))
1383                 intel_enable_fbc(crtc, 500);
1384
1385         return;
1386
1387 out_disable:
1388         /* Multiple disables should be harmless */
1389         if (intel_fbc_enabled(dev)) {
1390                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1391                 intel_disable_fbc(dev);
1392         }
1393 }
1394
1395 int
1396 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1397 {
1398         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1399         u32 alignment;
1400         int ret;
1401
1402         switch (obj_priv->tiling_mode) {
1403         case I915_TILING_NONE:
1404                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1405                         alignment = 128 * 1024;
1406                 else if (IS_I965G(dev))
1407                         alignment = 4 * 1024;
1408                 else
1409                         alignment = 64 * 1024;
1410                 break;
1411         case I915_TILING_X:
1412                 /* pin() will align the object as required by fence */
1413                 alignment = 0;
1414                 break;
1415         case I915_TILING_Y:
1416                 /* FIXME: Is this true? */
1417                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1418                 return -EINVAL;
1419         default:
1420                 BUG();
1421         }
1422
1423         ret = i915_gem_object_pin(obj, alignment);
1424         if (ret != 0)
1425                 return ret;
1426
1427         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1428          * fence, whereas 965+ only requires a fence if using
1429          * framebuffer compression.  For simplicity, we always install
1430          * a fence as the cost is not that onerous.
1431          */
1432         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1433             obj_priv->tiling_mode != I915_TILING_NONE) {
1434                 ret = i915_gem_object_get_fence_reg(obj);
1435                 if (ret != 0) {
1436                         i915_gem_object_unpin(obj);
1437                         return ret;
1438                 }
1439         }
1440
1441         return 0;
1442 }
1443
1444 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1445 static int
1446 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1447                            int x, int y)
1448 {
1449         struct drm_device *dev = crtc->dev;
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1452         struct intel_framebuffer *intel_fb;
1453         struct drm_i915_gem_object *obj_priv;
1454         struct drm_gem_object *obj;
1455         int plane = intel_crtc->plane;
1456         unsigned long Start, Offset;
1457         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1458         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1459         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1460         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1461         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1462         u32 dspcntr;
1463
1464         switch (plane) {
1465         case 0:
1466         case 1:
1467                 break;
1468         default:
1469                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1470                 return -EINVAL;
1471         }
1472
1473         intel_fb = to_intel_framebuffer(fb);
1474         obj = intel_fb->obj;
1475         obj_priv = to_intel_bo(obj);
1476
1477         dspcntr = I915_READ(dspcntr_reg);
1478         /* Mask out pixel format bits in case we change it */
1479         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1480         switch (fb->bits_per_pixel) {
1481         case 8:
1482                 dspcntr |= DISPPLANE_8BPP;
1483                 break;
1484         case 16:
1485                 if (fb->depth == 15)
1486                         dspcntr |= DISPPLANE_15_16BPP;
1487                 else
1488                         dspcntr |= DISPPLANE_16BPP;
1489                 break;
1490         case 24:
1491         case 32:
1492                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1493                 break;
1494         default:
1495                 DRM_ERROR("Unknown color depth\n");
1496                 return -EINVAL;
1497         }
1498         if (IS_I965G(dev)) {
1499                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1500                         dspcntr |= DISPPLANE_TILED;
1501                 else
1502                         dspcntr &= ~DISPPLANE_TILED;
1503         }
1504
1505         if (HAS_PCH_SPLIT(dev))
1506                 /* must disable */
1507                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1508
1509         I915_WRITE(dspcntr_reg, dspcntr);
1510
1511         Start = obj_priv->gtt_offset;
1512         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1513
1514         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515                       Start, Offset, x, y, fb->pitch);
1516         I915_WRITE(dspstride, fb->pitch);
1517         if (IS_I965G(dev)) {
1518                 I915_WRITE(dspsurf, Start);
1519                 I915_WRITE(dsptileoff, (y << 16) | x);
1520                 I915_WRITE(dspbase, Offset);
1521         } else {
1522                 I915_WRITE(dspbase, Start + Offset);
1523         }
1524         POSTING_READ(dspbase);
1525
1526         if (IS_I965G(dev) || plane == 0)
1527                 intel_update_fbc(crtc, &crtc->mode);
1528
1529         intel_wait_for_vblank(dev, intel_crtc->pipe);
1530         intel_increase_pllclock(crtc, true);
1531
1532         return 0;
1533 }
1534
1535 static int
1536 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1537                     struct drm_framebuffer *old_fb)
1538 {
1539         struct drm_device *dev = crtc->dev;
1540         struct drm_i915_master_private *master_priv;
1541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1542         struct intel_framebuffer *intel_fb;
1543         struct drm_i915_gem_object *obj_priv;
1544         struct drm_gem_object *obj;
1545         int pipe = intel_crtc->pipe;
1546         int plane = intel_crtc->plane;
1547         int ret;
1548
1549         /* no fb bound */
1550         if (!crtc->fb) {
1551                 DRM_DEBUG_KMS("No FB bound\n");
1552                 return 0;
1553         }
1554
1555         switch (plane) {
1556         case 0:
1557         case 1:
1558                 break;
1559         default:
1560                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1561                 return -EINVAL;
1562         }
1563
1564         intel_fb = to_intel_framebuffer(crtc->fb);
1565         obj = intel_fb->obj;
1566         obj_priv = to_intel_bo(obj);
1567
1568         mutex_lock(&dev->struct_mutex);
1569         ret = intel_pin_and_fence_fb_obj(dev, obj);
1570         if (ret != 0) {
1571                 mutex_unlock(&dev->struct_mutex);
1572                 return ret;
1573         }
1574
1575         ret = i915_gem_object_set_to_display_plane(obj);
1576         if (ret != 0) {
1577                 i915_gem_object_unpin(obj);
1578                 mutex_unlock(&dev->struct_mutex);
1579                 return ret;
1580         }
1581
1582         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1583         if (ret) {
1584                 i915_gem_object_unpin(obj);
1585                 mutex_unlock(&dev->struct_mutex);
1586                 return ret;
1587         }
1588
1589         if (old_fb) {
1590                 intel_fb = to_intel_framebuffer(old_fb);
1591                 obj_priv = to_intel_bo(intel_fb->obj);
1592                 i915_gem_object_unpin(intel_fb->obj);
1593         }
1594
1595         mutex_unlock(&dev->struct_mutex);
1596
1597         if (!dev->primary->master)
1598                 return 0;
1599
1600         master_priv = dev->primary->master->driver_priv;
1601         if (!master_priv->sarea_priv)
1602                 return 0;
1603
1604         if (pipe) {
1605                 master_priv->sarea_priv->pipeB_x = x;
1606                 master_priv->sarea_priv->pipeB_y = y;
1607         } else {
1608                 master_priv->sarea_priv->pipeA_x = x;
1609                 master_priv->sarea_priv->pipeA_y = y;
1610         }
1611
1612         return 0;
1613 }
1614
1615 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1616 {
1617         struct drm_device *dev = crtc->dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619         u32 dpa_ctl;
1620
1621         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1622         dpa_ctl = I915_READ(DP_A);
1623         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1624
1625         if (clock < 200000) {
1626                 u32 temp;
1627                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1628                 /* workaround for 160Mhz:
1629                    1) program 0x4600c bits 15:0 = 0x8124
1630                    2) program 0x46010 bit 0 = 1
1631                    3) program 0x46034 bit 24 = 1
1632                    4) program 0x64000 bit 14 = 1
1633                    */
1634                 temp = I915_READ(0x4600c);
1635                 temp &= 0xffff0000;
1636                 I915_WRITE(0x4600c, temp | 0x8124);
1637
1638                 temp = I915_READ(0x46010);
1639                 I915_WRITE(0x46010, temp | 1);
1640
1641                 temp = I915_READ(0x46034);
1642                 I915_WRITE(0x46034, temp | (1 << 24));
1643         } else {
1644                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1645         }
1646         I915_WRITE(DP_A, dpa_ctl);
1647
1648         udelay(500);
1649 }
1650
1651 /* The FDI link training functions for ILK/Ibexpeak. */
1652 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1653 {
1654         struct drm_device *dev = crtc->dev;
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1657         int pipe = intel_crtc->pipe;
1658         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1659         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1660         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1661         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1662         u32 temp, tries = 0;
1663
1664         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1665            for train result */
1666         temp = I915_READ(fdi_rx_imr_reg);
1667         temp &= ~FDI_RX_SYMBOL_LOCK;
1668         temp &= ~FDI_RX_BIT_LOCK;
1669         I915_WRITE(fdi_rx_imr_reg, temp);
1670         I915_READ(fdi_rx_imr_reg);
1671         udelay(150);
1672
1673         /* enable CPU FDI TX and PCH FDI RX */
1674         temp = I915_READ(fdi_tx_reg);
1675         temp |= FDI_TX_ENABLE;
1676         temp &= ~(7 << 19);
1677         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1678         temp &= ~FDI_LINK_TRAIN_NONE;
1679         temp |= FDI_LINK_TRAIN_PATTERN_1;
1680         I915_WRITE(fdi_tx_reg, temp);
1681         I915_READ(fdi_tx_reg);
1682
1683         temp = I915_READ(fdi_rx_reg);
1684         temp &= ~FDI_LINK_TRAIN_NONE;
1685         temp |= FDI_LINK_TRAIN_PATTERN_1;
1686         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1687         I915_READ(fdi_rx_reg);
1688         udelay(150);
1689
1690         for (tries = 0; tries < 5; tries++) {
1691                 temp = I915_READ(fdi_rx_iir_reg);
1692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1693
1694                 if ((temp & FDI_RX_BIT_LOCK)) {
1695                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1696                         I915_WRITE(fdi_rx_iir_reg,
1697                                    temp | FDI_RX_BIT_LOCK);
1698                         break;
1699                 }
1700         }
1701         if (tries == 5)
1702                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1703
1704         /* Train 2 */
1705         temp = I915_READ(fdi_tx_reg);
1706         temp &= ~FDI_LINK_TRAIN_NONE;
1707         temp |= FDI_LINK_TRAIN_PATTERN_2;
1708         I915_WRITE(fdi_tx_reg, temp);
1709
1710         temp = I915_READ(fdi_rx_reg);
1711         temp &= ~FDI_LINK_TRAIN_NONE;
1712         temp |= FDI_LINK_TRAIN_PATTERN_2;
1713         I915_WRITE(fdi_rx_reg, temp);
1714         udelay(150);
1715
1716         tries = 0;
1717
1718         for (tries = 0; tries < 5; tries++) {
1719                 temp = I915_READ(fdi_rx_iir_reg);
1720                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1721
1722                 if (temp & FDI_RX_SYMBOL_LOCK) {
1723                         I915_WRITE(fdi_rx_iir_reg,
1724                                    temp | FDI_RX_SYMBOL_LOCK);
1725                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1726                         break;
1727                 }
1728         }
1729         if (tries == 5)
1730                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1731
1732         DRM_DEBUG_KMS("FDI train done\n");
1733 }
1734
1735 static int snb_b_fdi_train_param [] = {
1736         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1737         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1738         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1739         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1740 };
1741
1742 /* The FDI link training functions for SNB/Cougarpoint. */
1743 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1744 {
1745         struct drm_device *dev = crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1748         int pipe = intel_crtc->pipe;
1749         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1750         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1751         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1752         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1753         u32 temp, i;
1754
1755         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1756            for train result */
1757         temp = I915_READ(fdi_rx_imr_reg);
1758         temp &= ~FDI_RX_SYMBOL_LOCK;
1759         temp &= ~FDI_RX_BIT_LOCK;
1760         I915_WRITE(fdi_rx_imr_reg, temp);
1761         I915_READ(fdi_rx_imr_reg);
1762         udelay(150);
1763
1764         /* enable CPU FDI TX and PCH FDI RX */
1765         temp = I915_READ(fdi_tx_reg);
1766         temp |= FDI_TX_ENABLE;
1767         temp &= ~(7 << 19);
1768         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1769         temp &= ~FDI_LINK_TRAIN_NONE;
1770         temp |= FDI_LINK_TRAIN_PATTERN_1;
1771         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1772         /* SNB-B */
1773         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1774         I915_WRITE(fdi_tx_reg, temp);
1775         I915_READ(fdi_tx_reg);
1776
1777         temp = I915_READ(fdi_rx_reg);
1778         if (HAS_PCH_CPT(dev)) {
1779                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1780                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1781         } else {
1782                 temp &= ~FDI_LINK_TRAIN_NONE;
1783                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1784         }
1785         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1786         I915_READ(fdi_rx_reg);
1787         udelay(150);
1788
1789         for (i = 0; i < 4; i++ ) {
1790                 temp = I915_READ(fdi_tx_reg);
1791                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1792                 temp |= snb_b_fdi_train_param[i];
1793                 I915_WRITE(fdi_tx_reg, temp);
1794                 udelay(500);
1795
1796                 temp = I915_READ(fdi_rx_iir_reg);
1797                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1798
1799                 if (temp & FDI_RX_BIT_LOCK) {
1800                         I915_WRITE(fdi_rx_iir_reg,
1801                                    temp | FDI_RX_BIT_LOCK);
1802                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1803                         break;
1804                 }
1805         }
1806         if (i == 4)
1807                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1808
1809         /* Train 2 */
1810         temp = I915_READ(fdi_tx_reg);
1811         temp &= ~FDI_LINK_TRAIN_NONE;
1812         temp |= FDI_LINK_TRAIN_PATTERN_2;
1813         if (IS_GEN6(dev)) {
1814                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1815                 /* SNB-B */
1816                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1817         }
1818         I915_WRITE(fdi_tx_reg, temp);
1819
1820         temp = I915_READ(fdi_rx_reg);
1821         if (HAS_PCH_CPT(dev)) {
1822                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1823                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1824         } else {
1825                 temp &= ~FDI_LINK_TRAIN_NONE;
1826                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1827         }
1828         I915_WRITE(fdi_rx_reg, temp);
1829         udelay(150);
1830
1831         for (i = 0; i < 4; i++ ) {
1832                 temp = I915_READ(fdi_tx_reg);
1833                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1834                 temp |= snb_b_fdi_train_param[i];
1835                 I915_WRITE(fdi_tx_reg, temp);
1836                 udelay(500);
1837
1838                 temp = I915_READ(fdi_rx_iir_reg);
1839                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1840
1841                 if (temp & FDI_RX_SYMBOL_LOCK) {
1842                         I915_WRITE(fdi_rx_iir_reg,
1843                                    temp | FDI_RX_SYMBOL_LOCK);
1844                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1845                         break;
1846                 }
1847         }
1848         if (i == 4)
1849                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1850
1851         DRM_DEBUG_KMS("FDI train done.\n");
1852 }
1853
1854 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1855 {
1856         struct drm_device *dev = crtc->dev;
1857         struct drm_i915_private *dev_priv = dev->dev_private;
1858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1859         int pipe = intel_crtc->pipe;
1860         int plane = intel_crtc->plane;
1861         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1862         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1863         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1864         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1865         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1866         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1867         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1868         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1869         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1870         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1871         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1872         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1873         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1874         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1875         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1876         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1877         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1878         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1879         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1880         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1881         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1882         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1883         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1884         u32 temp;
1885         u32 pipe_bpc;
1886
1887         temp = I915_READ(pipeconf_reg);
1888         pipe_bpc = temp & PIPE_BPC_MASK;
1889
1890         /* XXX: When our outputs are all unaware of DPMS modes other than off
1891          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1892          */
1893         switch (mode) {
1894         case DRM_MODE_DPMS_ON:
1895         case DRM_MODE_DPMS_STANDBY:
1896         case DRM_MODE_DPMS_SUSPEND:
1897                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1898
1899                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1900                         temp = I915_READ(PCH_LVDS);
1901                         if ((temp & LVDS_PORT_EN) == 0) {
1902                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1903                                 POSTING_READ(PCH_LVDS);
1904                         }
1905                 }
1906
1907                 if (!HAS_eDP) {
1908
1909                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1910                         temp = I915_READ(fdi_rx_reg);
1911                         /*
1912                          * make the BPC in FDI Rx be consistent with that in
1913                          * pipeconf reg.
1914                          */
1915                         temp &= ~(0x7 << 16);
1916                         temp |= (pipe_bpc << 11);
1917                         temp &= ~(7 << 19);
1918                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1919                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1920                         I915_READ(fdi_rx_reg);
1921                         udelay(200);
1922
1923                         /* Switch from Rawclk to PCDclk */
1924                         temp = I915_READ(fdi_rx_reg);
1925                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1926                         I915_READ(fdi_rx_reg);
1927                         udelay(200);
1928
1929                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1930                         temp = I915_READ(fdi_tx_reg);
1931                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1932                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1933                                 I915_READ(fdi_tx_reg);
1934                                 udelay(100);
1935                         }
1936                 }
1937
1938                 /* Enable panel fitting for LVDS */
1939                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1940                     || HAS_eDP || intel_pch_has_edp(crtc)) {
1941                         if (dev_priv->pch_pf_size) {
1942                                 temp = I915_READ(pf_ctl_reg);
1943                                 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1944                                 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
1945                                 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
1946                         } else
1947                                 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1948                 }
1949
1950                 /* Enable CPU pipe */
1951                 temp = I915_READ(pipeconf_reg);
1952                 if ((temp & PIPEACONF_ENABLE) == 0) {
1953                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1954                         I915_READ(pipeconf_reg);
1955                         udelay(100);
1956                 }
1957
1958                 /* configure and enable CPU plane */
1959                 temp = I915_READ(dspcntr_reg);
1960                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1961                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1962                         /* Flush the plane changes */
1963                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1964                 }
1965
1966                 if (!HAS_eDP) {
1967                         /* For PCH output, training FDI link */
1968                         if (IS_GEN6(dev))
1969                                 gen6_fdi_link_train(crtc);
1970                         else
1971                                 ironlake_fdi_link_train(crtc);
1972
1973                         /* enable PCH DPLL */
1974                         temp = I915_READ(pch_dpll_reg);
1975                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1976                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1977                                 I915_READ(pch_dpll_reg);
1978                         }
1979                         udelay(200);
1980
1981                         if (HAS_PCH_CPT(dev)) {
1982                                 /* Be sure PCH DPLL SEL is set */
1983                                 temp = I915_READ(PCH_DPLL_SEL);
1984                                 if (trans_dpll_sel == 0 &&
1985                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1986                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1987                                 else if (trans_dpll_sel == 1 &&
1988                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1989                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1990                                 I915_WRITE(PCH_DPLL_SEL, temp);
1991                                 I915_READ(PCH_DPLL_SEL);
1992                         }
1993
1994                         /* set transcoder timing */
1995                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1996                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1997                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1998
1999                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2000                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2001                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2002
2003                         /* enable normal train */
2004                         temp = I915_READ(fdi_tx_reg);
2005                         temp &= ~FDI_LINK_TRAIN_NONE;
2006                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2007                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2008                         I915_READ(fdi_tx_reg);
2009
2010                         temp = I915_READ(fdi_rx_reg);
2011                         if (HAS_PCH_CPT(dev)) {
2012                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2013                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2014                         } else {
2015                                 temp &= ~FDI_LINK_TRAIN_NONE;
2016                                 temp |= FDI_LINK_TRAIN_NONE;
2017                         }
2018                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2019                         I915_READ(fdi_rx_reg);
2020
2021                         /* wait one idle pattern time */
2022                         udelay(100);
2023
2024                         /* For PCH DP, enable TRANS_DP_CTL */
2025                         if (HAS_PCH_CPT(dev) &&
2026                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2027                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2028                                 int reg;
2029
2030                                 reg = I915_READ(trans_dp_ctl);
2031                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2032                                          TRANS_DP_SYNC_MASK);
2033                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2034                                         TRANS_DP_ENH_FRAMING);
2035
2036                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2037                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2038                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2039                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2040
2041                                 switch (intel_trans_dp_port_sel(crtc)) {
2042                                 case PCH_DP_B:
2043                                         reg |= TRANS_DP_PORT_SEL_B;
2044                                         break;
2045                                 case PCH_DP_C:
2046                                         reg |= TRANS_DP_PORT_SEL_C;
2047                                         break;
2048                                 case PCH_DP_D:
2049                                         reg |= TRANS_DP_PORT_SEL_D;
2050                                         break;
2051                                 default:
2052                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2053                                         reg |= TRANS_DP_PORT_SEL_B;
2054                                         break;
2055                                 }
2056
2057                                 I915_WRITE(trans_dp_ctl, reg);
2058                                 POSTING_READ(trans_dp_ctl);
2059                         }
2060
2061                         /* enable PCH transcoder */
2062                         temp = I915_READ(transconf_reg);
2063                         /*
2064                          * make the BPC in transcoder be consistent with
2065                          * that in pipeconf reg.
2066                          */
2067                         temp &= ~PIPE_BPC_MASK;
2068                         temp |= pipe_bpc;
2069                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2070                         I915_READ(transconf_reg);
2071
2072                         if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2073                                 DRM_ERROR("failed to enable transcoder\n");
2074                 }
2075
2076                 intel_crtc_load_lut(crtc);
2077
2078                 intel_update_fbc(crtc, &crtc->mode);
2079                 break;
2080
2081         case DRM_MODE_DPMS_OFF:
2082                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2083
2084                 drm_vblank_off(dev, pipe);
2085                 /* Disable display plane */
2086                 temp = I915_READ(dspcntr_reg);
2087                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2088                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2089                         /* Flush the plane changes */
2090                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2091                         I915_READ(dspbase_reg);
2092                 }
2093
2094                 if (dev_priv->cfb_plane == plane &&
2095                     dev_priv->display.disable_fbc)
2096                         dev_priv->display.disable_fbc(dev);
2097
2098                 /* disable cpu pipe, disable after all planes disabled */
2099                 temp = I915_READ(pipeconf_reg);
2100                 if ((temp & PIPEACONF_ENABLE) != 0) {
2101                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2102
2103                         /* wait for cpu pipe off, pipe state */
2104                         if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2105                                 DRM_ERROR("failed to turn off cpu pipe\n");
2106                 } else
2107                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2108
2109                 udelay(100);
2110
2111                 /* Disable PF */
2112                 temp = I915_READ(pf_ctl_reg);
2113                 if ((temp & PF_ENABLE) != 0) {
2114                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2115                         I915_READ(pf_ctl_reg);
2116                 }
2117                 I915_WRITE(pf_win_size, 0);
2118                 POSTING_READ(pf_win_size);
2119
2120
2121                 /* disable CPU FDI tx and PCH FDI rx */
2122                 temp = I915_READ(fdi_tx_reg);
2123                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2124                 I915_READ(fdi_tx_reg);
2125
2126                 temp = I915_READ(fdi_rx_reg);
2127                 /* BPC in FDI rx is consistent with that in pipeconf */
2128                 temp &= ~(0x07 << 16);
2129                 temp |= (pipe_bpc << 11);
2130                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2131                 I915_READ(fdi_rx_reg);
2132
2133                 udelay(100);
2134
2135                 /* still set train pattern 1 */
2136                 temp = I915_READ(fdi_tx_reg);
2137                 temp &= ~FDI_LINK_TRAIN_NONE;
2138                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2139                 I915_WRITE(fdi_tx_reg, temp);
2140                 POSTING_READ(fdi_tx_reg);
2141
2142                 temp = I915_READ(fdi_rx_reg);
2143                 if (HAS_PCH_CPT(dev)) {
2144                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2145                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2146                 } else {
2147                         temp &= ~FDI_LINK_TRAIN_NONE;
2148                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2149                 }
2150                 I915_WRITE(fdi_rx_reg, temp);
2151                 POSTING_READ(fdi_rx_reg);
2152
2153                 udelay(100);
2154
2155                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2156                         temp = I915_READ(PCH_LVDS);
2157                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2158                         I915_READ(PCH_LVDS);
2159                         udelay(100);
2160                 }
2161
2162                 /* disable PCH transcoder */
2163                 temp = I915_READ(transconf_reg);
2164                 if ((temp & TRANS_ENABLE) != 0) {
2165                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2166
2167                         /* wait for PCH transcoder off, transcoder state */
2168                         if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2169                                 DRM_ERROR("failed to disable transcoder\n");
2170                 }
2171
2172                 temp = I915_READ(transconf_reg);
2173                 /* BPC in transcoder is consistent with that in pipeconf */
2174                 temp &= ~PIPE_BPC_MASK;
2175                 temp |= pipe_bpc;
2176                 I915_WRITE(transconf_reg, temp);
2177                 I915_READ(transconf_reg);
2178                 udelay(100);
2179
2180                 if (HAS_PCH_CPT(dev)) {
2181                         /* disable TRANS_DP_CTL */
2182                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2183                         int reg;
2184
2185                         reg = I915_READ(trans_dp_ctl);
2186                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2187                         I915_WRITE(trans_dp_ctl, reg);
2188                         POSTING_READ(trans_dp_ctl);
2189
2190                         /* disable DPLL_SEL */
2191                         temp = I915_READ(PCH_DPLL_SEL);
2192                         if (trans_dpll_sel == 0)
2193                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2194                         else
2195                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2196                         I915_WRITE(PCH_DPLL_SEL, temp);
2197                         I915_READ(PCH_DPLL_SEL);
2198
2199                 }
2200
2201                 /* disable PCH DPLL */
2202                 temp = I915_READ(pch_dpll_reg);
2203                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2204                 I915_READ(pch_dpll_reg);
2205
2206                 /* Switch from PCDclk to Rawclk */
2207                 temp = I915_READ(fdi_rx_reg);
2208                 temp &= ~FDI_SEL_PCDCLK;
2209                 I915_WRITE(fdi_rx_reg, temp);
2210                 I915_READ(fdi_rx_reg);
2211
2212                 /* Disable CPU FDI TX PLL */
2213                 temp = I915_READ(fdi_tx_reg);
2214                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2215                 I915_READ(fdi_tx_reg);
2216                 udelay(100);
2217
2218                 temp = I915_READ(fdi_rx_reg);
2219                 temp &= ~FDI_RX_PLL_ENABLE;
2220                 I915_WRITE(fdi_rx_reg, temp);
2221                 I915_READ(fdi_rx_reg);
2222
2223                 /* Wait for the clocks to turn off. */
2224                 udelay(100);
2225                 break;
2226         }
2227 }
2228
2229 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2230 {
2231         struct intel_overlay *overlay;
2232         int ret;
2233
2234         if (!enable && intel_crtc->overlay) {
2235                 overlay = intel_crtc->overlay;
2236                 mutex_lock(&overlay->dev->struct_mutex);
2237                 for (;;) {
2238                         ret = intel_overlay_switch_off(overlay);
2239                         if (ret == 0)
2240                                 break;
2241
2242                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2243                         if (ret != 0) {
2244                                 /* overlay doesn't react anymore. Usually
2245                                  * results in a black screen and an unkillable
2246                                  * X server. */
2247                                 BUG();
2248                                 overlay->hw_wedged = HW_WEDGED;
2249                                 break;
2250                         }
2251                 }
2252                 mutex_unlock(&overlay->dev->struct_mutex);
2253         }
2254         /* Let userspace switch the overlay on again. In most cases userspace
2255          * has to recompute where to put it anyway. */
2256
2257         return;
2258 }
2259
2260 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2261 {
2262         struct drm_device *dev = crtc->dev;
2263         struct drm_i915_private *dev_priv = dev->dev_private;
2264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265         int pipe = intel_crtc->pipe;
2266         int plane = intel_crtc->plane;
2267         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2268         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2269         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2270         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2271         u32 temp;
2272
2273         /* XXX: When our outputs are all unaware of DPMS modes other than off
2274          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2275          */
2276         switch (mode) {
2277         case DRM_MODE_DPMS_ON:
2278         case DRM_MODE_DPMS_STANDBY:
2279         case DRM_MODE_DPMS_SUSPEND:
2280                 /* Enable the DPLL */
2281                 temp = I915_READ(dpll_reg);
2282                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2283                         I915_WRITE(dpll_reg, temp);
2284                         I915_READ(dpll_reg);
2285                         /* Wait for the clocks to stabilize. */
2286                         udelay(150);
2287                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2288                         I915_READ(dpll_reg);
2289                         /* Wait for the clocks to stabilize. */
2290                         udelay(150);
2291                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2292                         I915_READ(dpll_reg);
2293                         /* Wait for the clocks to stabilize. */
2294                         udelay(150);
2295                 }
2296
2297                 /* Enable the pipe */
2298                 temp = I915_READ(pipeconf_reg);
2299                 if ((temp & PIPEACONF_ENABLE) == 0)
2300                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2301
2302                 /* Enable the plane */
2303                 temp = I915_READ(dspcntr_reg);
2304                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2305                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2306                         /* Flush the plane changes */
2307                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2308                 }
2309
2310                 intel_crtc_load_lut(crtc);
2311
2312                 if ((IS_I965G(dev) || plane == 0))
2313                         intel_update_fbc(crtc, &crtc->mode);
2314
2315                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2316                 intel_crtc_dpms_overlay(intel_crtc, true);
2317         break;
2318         case DRM_MODE_DPMS_OFF:
2319                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2320                 intel_crtc_dpms_overlay(intel_crtc, false);
2321                 drm_vblank_off(dev, pipe);
2322
2323                 if (dev_priv->cfb_plane == plane &&
2324                     dev_priv->display.disable_fbc)
2325                         dev_priv->display.disable_fbc(dev);
2326
2327                 /* Disable display plane */
2328                 temp = I915_READ(dspcntr_reg);
2329                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2330                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2331                         /* Flush the plane changes */
2332                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2333                         I915_READ(dspbase_reg);
2334                 }
2335
2336                 /* Wait for vblank for the disable to take effect */
2337                 intel_wait_for_vblank_off(dev, pipe);
2338
2339                 /* Don't disable pipe A or pipe A PLLs if needed */
2340                 if (pipeconf_reg == PIPEACONF &&
2341                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2342                         goto skip_pipe_off;
2343
2344                 /* Next, disable display pipes */
2345                 temp = I915_READ(pipeconf_reg);
2346                 if ((temp & PIPEACONF_ENABLE) != 0) {
2347                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2348                         I915_READ(pipeconf_reg);
2349                 }
2350
2351                 /* Wait for vblank for the disable to take effect. */
2352                 intel_wait_for_vblank_off(dev, pipe);
2353
2354                 temp = I915_READ(dpll_reg);
2355                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2356                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2357                         I915_READ(dpll_reg);
2358                 }
2359         skip_pipe_off:
2360                 /* Wait for the clocks to turn off. */
2361                 udelay(150);
2362                 break;
2363         }
2364 }
2365
2366 /**
2367  * Sets the power management mode of the pipe and plane.
2368  */
2369 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2370 {
2371         struct drm_device *dev = crtc->dev;
2372         struct drm_i915_private *dev_priv = dev->dev_private;
2373         struct drm_i915_master_private *master_priv;
2374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375         int pipe = intel_crtc->pipe;
2376         bool enabled;
2377
2378         intel_crtc->dpms_mode = mode;
2379         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2380
2381         /* When switching on the display, ensure that SR is disabled
2382          * with multiple pipes prior to enabling to new pipe.
2383          *
2384          * When switching off the display, make sure the cursor is
2385          * properly hidden prior to disabling the pipe.
2386          */
2387         if (mode == DRM_MODE_DPMS_ON)
2388                 intel_update_watermarks(dev);
2389         else
2390                 intel_crtc_update_cursor(crtc);
2391
2392         dev_priv->display.dpms(crtc, mode);
2393
2394         if (mode == DRM_MODE_DPMS_ON)
2395                 intel_crtc_update_cursor(crtc);
2396         else
2397                 intel_update_watermarks(dev);
2398
2399         if (!dev->primary->master)
2400                 return;
2401
2402         master_priv = dev->primary->master->driver_priv;
2403         if (!master_priv->sarea_priv)
2404                 return;
2405
2406         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2407
2408         switch (pipe) {
2409         case 0:
2410                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2411                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2412                 break;
2413         case 1:
2414                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2415                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2416                 break;
2417         default:
2418                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2419                 break;
2420         }
2421 }
2422
2423 static void intel_crtc_prepare (struct drm_crtc *crtc)
2424 {
2425         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2426         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2427 }
2428
2429 static void intel_crtc_commit (struct drm_crtc *crtc)
2430 {
2431         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2432         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2433 }
2434
2435 void intel_encoder_prepare (struct drm_encoder *encoder)
2436 {
2437         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2438         /* lvds has its own version of prepare see intel_lvds_prepare */
2439         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2440 }
2441
2442 void intel_encoder_commit (struct drm_encoder *encoder)
2443 {
2444         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2445         /* lvds has its own version of commit see intel_lvds_commit */
2446         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2447 }
2448
2449 void intel_encoder_destroy(struct drm_encoder *encoder)
2450 {
2451         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2452
2453         if (intel_encoder->ddc_bus)
2454                 intel_i2c_destroy(intel_encoder->ddc_bus);
2455
2456         if (intel_encoder->i2c_bus)
2457                 intel_i2c_destroy(intel_encoder->i2c_bus);
2458
2459         drm_encoder_cleanup(encoder);
2460         kfree(intel_encoder);
2461 }
2462
2463 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2464                                   struct drm_display_mode *mode,
2465                                   struct drm_display_mode *adjusted_mode)
2466 {
2467         struct drm_device *dev = crtc->dev;
2468         if (HAS_PCH_SPLIT(dev)) {
2469                 /* FDI link clock is fixed at 2.7G */
2470                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2471                         return false;
2472         }
2473         return true;
2474 }
2475
2476 static int i945_get_display_clock_speed(struct drm_device *dev)
2477 {
2478         return 400000;
2479 }
2480
2481 static int i915_get_display_clock_speed(struct drm_device *dev)
2482 {
2483         return 333000;
2484 }
2485
2486 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2487 {
2488         return 200000;
2489 }
2490
2491 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2492 {
2493         u16 gcfgc = 0;
2494
2495         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2496
2497         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2498                 return 133000;
2499         else {
2500                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2501                 case GC_DISPLAY_CLOCK_333_MHZ:
2502                         return 333000;
2503                 default:
2504                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2505                         return 190000;
2506                 }
2507         }
2508 }
2509
2510 static int i865_get_display_clock_speed(struct drm_device *dev)
2511 {
2512         return 266000;
2513 }
2514
2515 static int i855_get_display_clock_speed(struct drm_device *dev)
2516 {
2517         u16 hpllcc = 0;
2518         /* Assume that the hardware is in the high speed state.  This
2519          * should be the default.
2520          */
2521         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2522         case GC_CLOCK_133_200:
2523         case GC_CLOCK_100_200:
2524                 return 200000;
2525         case GC_CLOCK_166_250:
2526                 return 250000;
2527         case GC_CLOCK_100_133:
2528                 return 133000;
2529         }
2530
2531         /* Shouldn't happen */
2532         return 0;
2533 }
2534
2535 static int i830_get_display_clock_speed(struct drm_device *dev)
2536 {
2537         return 133000;
2538 }
2539
2540 /**
2541  * Return the pipe currently connected to the panel fitter,
2542  * or -1 if the panel fitter is not present or not in use
2543  */
2544 int intel_panel_fitter_pipe (struct drm_device *dev)
2545 {
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         u32  pfit_control;
2548
2549         /* i830 doesn't have a panel fitter */
2550         if (IS_I830(dev))
2551                 return -1;
2552
2553         pfit_control = I915_READ(PFIT_CONTROL);
2554
2555         /* See if the panel fitter is in use */
2556         if ((pfit_control & PFIT_ENABLE) == 0)
2557                 return -1;
2558
2559         /* 965 can place panel fitter on either pipe */
2560         if (IS_I965G(dev))
2561                 return (pfit_control >> 29) & 0x3;
2562
2563         /* older chips can only use pipe 1 */
2564         return 1;
2565 }
2566
2567 struct fdi_m_n {
2568         u32        tu;
2569         u32        gmch_m;
2570         u32        gmch_n;
2571         u32        link_m;
2572         u32        link_n;
2573 };
2574
2575 static void
2576 fdi_reduce_ratio(u32 *num, u32 *den)
2577 {
2578         while (*num > 0xffffff || *den > 0xffffff) {
2579                 *num >>= 1;
2580                 *den >>= 1;
2581         }
2582 }
2583
2584 #define DATA_N 0x800000
2585 #define LINK_N 0x80000
2586
2587 static void
2588 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2589                      int link_clock, struct fdi_m_n *m_n)
2590 {
2591         u64 temp;
2592
2593         m_n->tu = 64; /* default size */
2594
2595         temp = (u64) DATA_N * pixel_clock;
2596         temp = div_u64(temp, link_clock);
2597         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2598         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2599         m_n->gmch_n = DATA_N;
2600         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2601
2602         temp = (u64) LINK_N * pixel_clock;
2603         m_n->link_m = div_u64(temp, link_clock);
2604         m_n->link_n = LINK_N;
2605         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2606 }
2607
2608
2609 struct intel_watermark_params {
2610         unsigned long fifo_size;
2611         unsigned long max_wm;
2612         unsigned long default_wm;
2613         unsigned long guard_size;
2614         unsigned long cacheline_size;
2615 };
2616
2617 /* Pineview has different values for various configs */
2618 static struct intel_watermark_params pineview_display_wm = {
2619         PINEVIEW_DISPLAY_FIFO,
2620         PINEVIEW_MAX_WM,
2621         PINEVIEW_DFT_WM,
2622         PINEVIEW_GUARD_WM,
2623         PINEVIEW_FIFO_LINE_SIZE
2624 };
2625 static struct intel_watermark_params pineview_display_hplloff_wm = {
2626         PINEVIEW_DISPLAY_FIFO,
2627         PINEVIEW_MAX_WM,
2628         PINEVIEW_DFT_HPLLOFF_WM,
2629         PINEVIEW_GUARD_WM,
2630         PINEVIEW_FIFO_LINE_SIZE
2631 };
2632 static struct intel_watermark_params pineview_cursor_wm = {
2633         PINEVIEW_CURSOR_FIFO,
2634         PINEVIEW_CURSOR_MAX_WM,
2635         PINEVIEW_CURSOR_DFT_WM,
2636         PINEVIEW_CURSOR_GUARD_WM,
2637         PINEVIEW_FIFO_LINE_SIZE,
2638 };
2639 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2640         PINEVIEW_CURSOR_FIFO,
2641         PINEVIEW_CURSOR_MAX_WM,
2642         PINEVIEW_CURSOR_DFT_WM,
2643         PINEVIEW_CURSOR_GUARD_WM,
2644         PINEVIEW_FIFO_LINE_SIZE
2645 };
2646 static struct intel_watermark_params g4x_wm_info = {
2647         G4X_FIFO_SIZE,
2648         G4X_MAX_WM,
2649         G4X_MAX_WM,
2650         2,
2651         G4X_FIFO_LINE_SIZE,
2652 };
2653 static struct intel_watermark_params g4x_cursor_wm_info = {
2654         I965_CURSOR_FIFO,
2655         I965_CURSOR_MAX_WM,
2656         I965_CURSOR_DFT_WM,
2657         2,
2658         G4X_FIFO_LINE_SIZE,
2659 };
2660 static struct intel_watermark_params i965_cursor_wm_info = {
2661         I965_CURSOR_FIFO,
2662         I965_CURSOR_MAX_WM,
2663         I965_CURSOR_DFT_WM,
2664         2,
2665         I915_FIFO_LINE_SIZE,
2666 };
2667 static struct intel_watermark_params i945_wm_info = {
2668         I945_FIFO_SIZE,
2669         I915_MAX_WM,
2670         1,
2671         2,
2672         I915_FIFO_LINE_SIZE
2673 };
2674 static struct intel_watermark_params i915_wm_info = {
2675         I915_FIFO_SIZE,
2676         I915_MAX_WM,
2677         1,
2678         2,
2679         I915_FIFO_LINE_SIZE
2680 };
2681 static struct intel_watermark_params i855_wm_info = {
2682         I855GM_FIFO_SIZE,
2683         I915_MAX_WM,
2684         1,
2685         2,
2686         I830_FIFO_LINE_SIZE
2687 };
2688 static struct intel_watermark_params i830_wm_info = {
2689         I830_FIFO_SIZE,
2690         I915_MAX_WM,
2691         1,
2692         2,
2693         I830_FIFO_LINE_SIZE
2694 };
2695
2696 static struct intel_watermark_params ironlake_display_wm_info = {
2697         ILK_DISPLAY_FIFO,
2698         ILK_DISPLAY_MAXWM,
2699         ILK_DISPLAY_DFTWM,
2700         2,
2701         ILK_FIFO_LINE_SIZE
2702 };
2703
2704 static struct intel_watermark_params ironlake_cursor_wm_info = {
2705         ILK_CURSOR_FIFO,
2706         ILK_CURSOR_MAXWM,
2707         ILK_CURSOR_DFTWM,
2708         2,
2709         ILK_FIFO_LINE_SIZE
2710 };
2711
2712 static struct intel_watermark_params ironlake_display_srwm_info = {
2713         ILK_DISPLAY_SR_FIFO,
2714         ILK_DISPLAY_MAX_SRWM,
2715         ILK_DISPLAY_DFT_SRWM,
2716         2,
2717         ILK_FIFO_LINE_SIZE
2718 };
2719
2720 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2721         ILK_CURSOR_SR_FIFO,
2722         ILK_CURSOR_MAX_SRWM,
2723         ILK_CURSOR_DFT_SRWM,
2724         2,
2725         ILK_FIFO_LINE_SIZE
2726 };
2727
2728 /**
2729  * intel_calculate_wm - calculate watermark level
2730  * @clock_in_khz: pixel clock
2731  * @wm: chip FIFO params
2732  * @pixel_size: display pixel size
2733  * @latency_ns: memory latency for the platform
2734  *
2735  * Calculate the watermark level (the level at which the display plane will
2736  * start fetching from memory again).  Each chip has a different display
2737  * FIFO size and allocation, so the caller needs to figure that out and pass
2738  * in the correct intel_watermark_params structure.
2739  *
2740  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2741  * on the pixel size.  When it reaches the watermark level, it'll start
2742  * fetching FIFO line sized based chunks from memory until the FIFO fills
2743  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2744  * will occur, and a display engine hang could result.
2745  */
2746 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2747                                         struct intel_watermark_params *wm,
2748                                         int pixel_size,
2749                                         unsigned long latency_ns)
2750 {
2751         long entries_required, wm_size;
2752
2753         /*
2754          * Note: we need to make sure we don't overflow for various clock &
2755          * latency values.
2756          * clocks go from a few thousand to several hundred thousand.
2757          * latency is usually a few thousand
2758          */
2759         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2760                 1000;
2761         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2762
2763         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2764
2765         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2766
2767         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2768
2769         /* Don't promote wm_size to unsigned... */
2770         if (wm_size > (long)wm->max_wm)
2771                 wm_size = wm->max_wm;
2772         if (wm_size <= 0) {
2773                 wm_size = wm->default_wm;
2774                 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2775                           " entries required = %ld, available = %lu.\n",
2776                           entries_required + wm->guard_size,
2777                           wm->fifo_size);
2778         }
2779
2780         return wm_size;
2781 }
2782
2783 struct cxsr_latency {
2784         int is_desktop;
2785         int is_ddr3;
2786         unsigned long fsb_freq;
2787         unsigned long mem_freq;
2788         unsigned long display_sr;
2789         unsigned long display_hpll_disable;
2790         unsigned long cursor_sr;
2791         unsigned long cursor_hpll_disable;
2792 };
2793
2794 static const struct cxsr_latency cxsr_latency_table[] = {
2795         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2796         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2797         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2798         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2799         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2800
2801         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2802         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2803         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2804         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2805         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2806
2807         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2808         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2809         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2810         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2811         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2812
2813         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2814         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2815         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2816         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2817         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2818
2819         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2820         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2821         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2822         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2823         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2824
2825         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2826         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2827         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2828         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2829         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2830 };
2831
2832 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2833                                                          int is_ddr3,
2834                                                          int fsb,
2835                                                          int mem)
2836 {
2837         const struct cxsr_latency *latency;
2838         int i;
2839
2840         if (fsb == 0 || mem == 0)
2841                 return NULL;
2842
2843         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2844                 latency = &cxsr_latency_table[i];
2845                 if (is_desktop == latency->is_desktop &&
2846                     is_ddr3 == latency->is_ddr3 &&
2847                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2848                         return latency;
2849         }
2850
2851         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2852
2853         return NULL;
2854 }
2855
2856 static void pineview_disable_cxsr(struct drm_device *dev)
2857 {
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859
2860         /* deactivate cxsr */
2861         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2862 }
2863
2864 /*
2865  * Latency for FIFO fetches is dependent on several factors:
2866  *   - memory configuration (speed, channels)
2867  *   - chipset
2868  *   - current MCH state
2869  * It can be fairly high in some situations, so here we assume a fairly
2870  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2871  * set this value too high, the FIFO will fetch frequently to stay full)
2872  * and power consumption (set it too low to save power and we might see
2873  * FIFO underruns and display "flicker").
2874  *
2875  * A value of 5us seems to be a good balance; safe for very low end
2876  * platforms but not overly aggressive on lower latency configs.
2877  */
2878 static const int latency_ns = 5000;
2879
2880 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2881 {
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         uint32_t dsparb = I915_READ(DSPARB);
2884         int size;
2885
2886         size = dsparb & 0x7f;
2887         if (plane)
2888                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2889
2890         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2891                         plane ? "B" : "A", size);
2892
2893         return size;
2894 }
2895
2896 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2897 {
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         uint32_t dsparb = I915_READ(DSPARB);
2900         int size;
2901
2902         size = dsparb & 0x1ff;
2903         if (plane)
2904                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2905         size >>= 1; /* Convert to cachelines */
2906
2907         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2908                         plane ? "B" : "A", size);
2909
2910         return size;
2911 }
2912
2913 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2914 {
2915         struct drm_i915_private *dev_priv = dev->dev_private;
2916         uint32_t dsparb = I915_READ(DSPARB);
2917         int size;
2918
2919         size = dsparb & 0x7f;
2920         size >>= 2; /* Convert to cachelines */
2921
2922         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2923                         plane ? "B" : "A",
2924                   size);
2925
2926         return size;
2927 }
2928
2929 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2930 {
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932         uint32_t dsparb = I915_READ(DSPARB);
2933         int size;
2934
2935         size = dsparb & 0x7f;
2936         size >>= 1; /* Convert to cachelines */
2937
2938         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2939                         plane ? "B" : "A", size);
2940
2941         return size;
2942 }
2943
2944 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2945                           int planeb_clock, int sr_hdisplay, int unused,
2946                           int pixel_size)
2947 {
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         const struct cxsr_latency *latency;
2950         u32 reg;
2951         unsigned long wm;
2952         int sr_clock;
2953
2954         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2955                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2956         if (!latency) {
2957                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2958                 pineview_disable_cxsr(dev);
2959                 return;
2960         }
2961
2962         if (!planea_clock || !planeb_clock) {
2963                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2964
2965                 /* Display SR */
2966                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2967                                         pixel_size, latency->display_sr);
2968                 reg = I915_READ(DSPFW1);
2969                 reg &= ~DSPFW_SR_MASK;
2970                 reg |= wm << DSPFW_SR_SHIFT;
2971                 I915_WRITE(DSPFW1, reg);
2972                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2973
2974                 /* cursor SR */
2975                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2976                                         pixel_size, latency->cursor_sr);
2977                 reg = I915_READ(DSPFW3);
2978                 reg &= ~DSPFW_CURSOR_SR_MASK;
2979                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2980                 I915_WRITE(DSPFW3, reg);
2981
2982                 /* Display HPLL off SR */
2983                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2984                                         pixel_size, latency->display_hpll_disable);
2985                 reg = I915_READ(DSPFW3);
2986                 reg &= ~DSPFW_HPLL_SR_MASK;
2987                 reg |= wm & DSPFW_HPLL_SR_MASK;
2988                 I915_WRITE(DSPFW3, reg);
2989
2990                 /* cursor HPLL off SR */
2991                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2992                                         pixel_size, latency->cursor_hpll_disable);
2993                 reg = I915_READ(DSPFW3);
2994                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2995                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2996                 I915_WRITE(DSPFW3, reg);
2997                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2998
2999                 /* activate cxsr */
3000                 I915_WRITE(DSPFW3,
3001                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3002                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3003         } else {
3004                 pineview_disable_cxsr(dev);
3005                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3006         }
3007 }
3008
3009 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3010                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3011                           int pixel_size)
3012 {
3013         struct drm_i915_private *dev_priv = dev->dev_private;
3014         int total_size, cacheline_size;
3015         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3016         struct intel_watermark_params planea_params, planeb_params;
3017         unsigned long line_time_us;
3018         int sr_clock, sr_entries = 0, entries_required;
3019
3020         /* Create copies of the base settings for each pipe */
3021         planea_params = planeb_params = g4x_wm_info;
3022
3023         /* Grab a couple of global values before we overwrite them */
3024         total_size = planea_params.fifo_size;
3025         cacheline_size = planea_params.cacheline_size;
3026
3027         /*
3028          * Note: we need to make sure we don't overflow for various clock &
3029          * latency values.
3030          * clocks go from a few thousand to several hundred thousand.
3031          * latency is usually a few thousand
3032          */
3033         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3034                 1000;
3035         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3036         planea_wm = entries_required + planea_params.guard_size;
3037
3038         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3039                 1000;
3040         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3041         planeb_wm = entries_required + planeb_params.guard_size;
3042
3043         cursora_wm = cursorb_wm = 16;
3044         cursor_sr = 32;
3045
3046         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3047
3048         /* Calc sr entries for one plane configs */
3049         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3050                 /* self-refresh has much higher latency */
3051                 static const int sr_latency_ns = 12000;
3052
3053                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3054                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3055
3056                 /* Use ns/us then divide to preserve precision */
3057                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3058                               pixel_size * sr_hdisplay;
3059                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3060
3061                 entries_required = (((sr_latency_ns / line_time_us) +
3062                                      1000) / 1000) * pixel_size * 64;
3063                 entries_required = DIV_ROUND_UP(entries_required,
3064                                            g4x_cursor_wm_info.cacheline_size);
3065                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3066
3067                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3068                         cursor_sr = g4x_cursor_wm_info.max_wm;
3069                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3070                               "cursor %d\n", sr_entries, cursor_sr);
3071
3072                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3073         } else {
3074                 /* Turn off self refresh if both pipes are enabled */
3075                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3076                                         & ~FW_BLC_SELF_EN);
3077         }
3078
3079         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3080                   planea_wm, planeb_wm, sr_entries);
3081
3082         planea_wm &= 0x3f;
3083         planeb_wm &= 0x3f;
3084
3085         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3086                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3087                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3088         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3089                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3090         /* HPLL off in SR has some issues on G4x... disable it */
3091         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3092                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3093 }
3094
3095 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3096                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3097                            int pixel_size)
3098 {
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100         unsigned long line_time_us;
3101         int sr_clock, sr_entries, srwm = 1;
3102         int cursor_sr = 16;
3103
3104         /* Calc sr entries for one plane configs */
3105         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3106                 /* self-refresh has much higher latency */
3107                 static const int sr_latency_ns = 12000;
3108
3109                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3110                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3111
3112                 /* Use ns/us then divide to preserve precision */
3113                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3114                               pixel_size * sr_hdisplay;
3115                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3116                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3117                 srwm = I965_FIFO_SIZE - sr_entries;
3118                 if (srwm < 0)
3119                         srwm = 1;
3120                 srwm &= 0x1ff;
3121
3122                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3123                              pixel_size * 64;
3124                 sr_entries = DIV_ROUND_UP(sr_entries,
3125                                           i965_cursor_wm_info.cacheline_size);
3126                 cursor_sr = i965_cursor_wm_info.fifo_size -
3127                             (sr_entries + i965_cursor_wm_info.guard_size);
3128
3129                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3130                         cursor_sr = i965_cursor_wm_info.max_wm;
3131
3132                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3133                               "cursor %d\n", srwm, cursor_sr);
3134
3135                 if (IS_I965GM(dev))
3136                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3137         } else {
3138                 /* Turn off self refresh if both pipes are enabled */
3139                 if (IS_I965GM(dev))
3140                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3141                                    & ~FW_BLC_SELF_EN);
3142         }
3143
3144         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3145                       srwm);
3146
3147         /* 965 has limitations... */
3148         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3149                    (8 << 0));
3150         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3151         /* update cursor SR watermark */
3152         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3153 }
3154
3155 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3156                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3157                            int pixel_size)
3158 {
3159         struct drm_i915_private *dev_priv = dev->dev_private;
3160         uint32_t fwater_lo;
3161         uint32_t fwater_hi;
3162         int total_size, cacheline_size, cwm, srwm = 1;
3163         int planea_wm, planeb_wm;
3164         struct intel_watermark_params planea_params, planeb_params;
3165         unsigned long line_time_us;
3166         int sr_clock, sr_entries = 0;
3167
3168         /* Create copies of the base settings for each pipe */
3169         if (IS_I965GM(dev) || IS_I945GM(dev))
3170                 planea_params = planeb_params = i945_wm_info;
3171         else if (IS_I9XX(dev))
3172                 planea_params = planeb_params = i915_wm_info;
3173         else
3174                 planea_params = planeb_params = i855_wm_info;
3175
3176         /* Grab a couple of global values before we overwrite them */
3177         total_size = planea_params.fifo_size;
3178         cacheline_size = planea_params.cacheline_size;
3179
3180         /* Update per-plane FIFO sizes */
3181         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3182         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3183
3184         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3185                                        pixel_size, latency_ns);
3186         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3187                                        pixel_size, latency_ns);
3188         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3189
3190         /*
3191          * Overlay gets an aggressive default since video jitter is bad.
3192          */
3193         cwm = 2;
3194
3195         /* Calc sr entries for one plane configs */
3196         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3197             (!planea_clock || !planeb_clock)) {
3198                 /* self-refresh has much higher latency */
3199                 static const int sr_latency_ns = 6000;
3200
3201                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3202                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3203
3204                 /* Use ns/us then divide to preserve precision */
3205                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3206                               pixel_size * sr_hdisplay;
3207                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3208                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3209                 srwm = total_size - sr_entries;
3210                 if (srwm < 0)
3211                         srwm = 1;
3212
3213                 if (IS_I945G(dev) || IS_I945GM(dev))
3214                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3215                 else if (IS_I915GM(dev)) {
3216                         /* 915M has a smaller SRWM field */
3217                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3218                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3219                 }
3220         } else {
3221                 /* Turn off self refresh if both pipes are enabled */
3222                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3223                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3224                                    & ~FW_BLC_SELF_EN);
3225                 } else if (IS_I915GM(dev)) {
3226                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3227                 }
3228         }
3229
3230         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3231                   planea_wm, planeb_wm, cwm, srwm);
3232
3233         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3234         fwater_hi = (cwm & 0x1f);
3235
3236         /* Set request length to 8 cachelines per fetch */
3237         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3238         fwater_hi = fwater_hi | (1 << 8);
3239
3240         I915_WRITE(FW_BLC, fwater_lo);
3241         I915_WRITE(FW_BLC2, fwater_hi);
3242 }
3243
3244 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3245                            int unused2, int unused3, int pixel_size)
3246 {
3247         struct drm_i915_private *dev_priv = dev->dev_private;
3248         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3249         int planea_wm;
3250
3251         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3252
3253         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3254                                        pixel_size, latency_ns);
3255         fwater_lo |= (3<<8) | planea_wm;
3256
3257         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3258
3259         I915_WRITE(FW_BLC, fwater_lo);
3260 }
3261
3262 #define ILK_LP0_PLANE_LATENCY           700
3263 #define ILK_LP0_CURSOR_LATENCY          1300
3264
3265 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3266                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3267                        int pixel_size)
3268 {
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3271         int sr_wm, cursor_wm;
3272         unsigned long line_time_us;
3273         int sr_clock, entries_required;
3274         u32 reg_value;
3275         int line_count;
3276         int planea_htotal = 0, planeb_htotal = 0;
3277         struct drm_crtc *crtc;
3278
3279         /* Need htotal for all active display plane */
3280         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3281                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3283                         if (intel_crtc->plane == 0)
3284                                 planea_htotal = crtc->mode.htotal;
3285                         else
3286                                 planeb_htotal = crtc->mode.htotal;
3287                 }
3288         }
3289
3290         /* Calculate and update the watermark for plane A */
3291         if (planea_clock) {
3292                 entries_required = ((planea_clock / 1000) * pixel_size *
3293                                      ILK_LP0_PLANE_LATENCY) / 1000;
3294                 entries_required = DIV_ROUND_UP(entries_required,
3295                                                 ironlake_display_wm_info.cacheline_size);
3296                 planea_wm = entries_required +
3297                             ironlake_display_wm_info.guard_size;
3298
3299                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3300                         planea_wm = ironlake_display_wm_info.max_wm;
3301
3302                 /* Use the large buffer method to calculate cursor watermark */
3303                 line_time_us = (planea_htotal * 1000) / planea_clock;
3304
3305                 /* Use ns/us then divide to preserve precision */
3306                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3307
3308                 /* calculate the cursor watermark for cursor A */
3309                 entries_required = line_count * 64 * pixel_size;
3310                 entries_required = DIV_ROUND_UP(entries_required,
3311                                                 ironlake_cursor_wm_info.cacheline_size);
3312                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3313                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3314                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3315
3316                 reg_value = I915_READ(WM0_PIPEA_ILK);
3317                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3318                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3319                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3320                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3321                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3322                                 "cursor: %d\n", planea_wm, cursora_wm);
3323         }
3324         /* Calculate and update the watermark for plane B */
3325         if (planeb_clock) {
3326                 entries_required = ((planeb_clock / 1000) * pixel_size *
3327                                      ILK_LP0_PLANE_LATENCY) / 1000;
3328                 entries_required = DIV_ROUND_UP(entries_required,
3329                                                 ironlake_display_wm_info.cacheline_size);
3330                 planeb_wm = entries_required +
3331                             ironlake_display_wm_info.guard_size;
3332
3333                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3334                         planeb_wm = ironlake_display_wm_info.max_wm;
3335
3336                 /* Use the large buffer method to calculate cursor watermark */
3337                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3338
3339                 /* Use ns/us then divide to preserve precision */
3340                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3341
3342                 /* calculate the cursor watermark for cursor B */
3343                 entries_required = line_count * 64 * pixel_size;
3344                 entries_required = DIV_ROUND_UP(entries_required,
3345                                                 ironlake_cursor_wm_info.cacheline_size);
3346                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3347                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3348                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3349
3350                 reg_value = I915_READ(WM0_PIPEB_ILK);
3351                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3352                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3353                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3354                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3355                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3356                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3357         }
3358
3359         /*
3360          * Calculate and update the self-refresh watermark only when one
3361          * display plane is used.
3362          */
3363         if (!planea_clock || !planeb_clock) {
3364
3365                 /* Read the self-refresh latency. The unit is 0.5us */
3366                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3367
3368                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3369                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3370
3371                 /* Use ns/us then divide to preserve precision */
3372                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3373                                / 1000;
3374
3375                 /* calculate the self-refresh watermark for display plane */
3376                 entries_required = line_count * sr_hdisplay * pixel_size;
3377                 entries_required = DIV_ROUND_UP(entries_required,
3378                                                 ironlake_display_srwm_info.cacheline_size);
3379                 sr_wm = entries_required +
3380                         ironlake_display_srwm_info.guard_size;
3381
3382                 /* calculate the self-refresh watermark for display cursor */
3383                 entries_required = line_count * pixel_size * 64;
3384                 entries_required = DIV_ROUND_UP(entries_required,
3385                                                 ironlake_cursor_srwm_info.cacheline_size);
3386                 cursor_wm = entries_required +
3387                             ironlake_cursor_srwm_info.guard_size;
3388
3389                 /* configure watermark and enable self-refresh */
3390                 reg_value = I915_READ(WM1_LP_ILK);
3391                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3392                                WM1_LP_CURSOR_MASK);
3393                 reg_value |= WM1_LP_SR_EN |
3394                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3395                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3396
3397                 I915_WRITE(WM1_LP_ILK, reg_value);
3398                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3399                                 "cursor %d\n", sr_wm, cursor_wm);
3400
3401         } else {
3402                 /* Turn off self refresh if both pipes are enabled */
3403                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3404         }
3405 }
3406 /**
3407  * intel_update_watermarks - update FIFO watermark values based on current modes
3408  *
3409  * Calculate watermark values for the various WM regs based on current mode
3410  * and plane configuration.
3411  *
3412  * There are several cases to deal with here:
3413  *   - normal (i.e. non-self-refresh)
3414  *   - self-refresh (SR) mode
3415  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3416  *   - lines are small relative to FIFO size (buffer can hold more than 2
3417  *     lines), so need to account for TLB latency
3418  *
3419  *   The normal calculation is:
3420  *     watermark = dotclock * bytes per pixel * latency
3421  *   where latency is platform & configuration dependent (we assume pessimal
3422  *   values here).
3423  *
3424  *   The SR calculation is:
3425  *     watermark = (trunc(latency/line time)+1) * surface width *
3426  *       bytes per pixel
3427  *   where
3428  *     line time = htotal / dotclock
3429  *     surface width = hdisplay for normal plane and 64 for cursor
3430  *   and latency is assumed to be high, as above.
3431  *
3432  * The final value programmed to the register should always be rounded up,
3433  * and include an extra 2 entries to account for clock crossings.
3434  *
3435  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3436  * to set the non-SR watermarks to 8.
3437   */
3438 static void intel_update_watermarks(struct drm_device *dev)
3439 {
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct drm_crtc *crtc;
3442         int sr_hdisplay = 0;
3443         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3444         int enabled = 0, pixel_size = 0;
3445         int sr_htotal = 0;
3446
3447         if (!dev_priv->display.update_wm)
3448                 return;
3449
3450         /* Get the clock config from both planes */
3451         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3452                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3454                         enabled++;
3455                         if (intel_crtc->plane == 0) {
3456                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3457                                           intel_crtc->pipe, crtc->mode.clock);
3458                                 planea_clock = crtc->mode.clock;
3459                         } else {
3460                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3461                                           intel_crtc->pipe, crtc->mode.clock);
3462                                 planeb_clock = crtc->mode.clock;
3463                         }
3464                         sr_hdisplay = crtc->mode.hdisplay;
3465                         sr_clock = crtc->mode.clock;
3466                         sr_htotal = crtc->mode.htotal;
3467                         if (crtc->fb)
3468                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3469                         else
3470                                 pixel_size = 4; /* by default */
3471                 }
3472         }
3473
3474         if (enabled <= 0)
3475                 return;
3476
3477         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3478                                     sr_hdisplay, sr_htotal, pixel_size);
3479 }
3480
3481 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3482                                struct drm_display_mode *mode,
3483                                struct drm_display_mode *adjusted_mode,
3484                                int x, int y,
3485                                struct drm_framebuffer *old_fb)
3486 {
3487         struct drm_device *dev = crtc->dev;
3488         struct drm_i915_private *dev_priv = dev->dev_private;
3489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490         int pipe = intel_crtc->pipe;
3491         int plane = intel_crtc->plane;
3492         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3493         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3494         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3495         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3496         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3497         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3498         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3499         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3500         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3501         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3502         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3503         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3504         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3505         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3506         int refclk, num_connectors = 0;
3507         intel_clock_t clock, reduced_clock;
3508         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3509         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3510         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3511         struct intel_encoder *has_edp_encoder = NULL;
3512         struct drm_mode_config *mode_config = &dev->mode_config;
3513         struct drm_encoder *encoder;
3514         const intel_limit_t *limit;
3515         int ret;
3516         struct fdi_m_n m_n = {0};
3517         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3518         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3519         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3520         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3521         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3522         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3523         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3524         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3525         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3526         int lvds_reg = LVDS;
3527         u32 temp;
3528         int sdvo_pixel_multiply;
3529         int target_clock;
3530
3531         drm_vblank_pre_modeset(dev, pipe);
3532
3533         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3534                 struct intel_encoder *intel_encoder;
3535
3536                 if (encoder->crtc != crtc)
3537                         continue;
3538
3539                 intel_encoder = enc_to_intel_encoder(encoder);
3540                 switch (intel_encoder->type) {
3541                 case INTEL_OUTPUT_LVDS:
3542                         is_lvds = true;
3543                         break;
3544                 case INTEL_OUTPUT_SDVO:
3545                 case INTEL_OUTPUT_HDMI:
3546                         is_sdvo = true;
3547                         if (intel_encoder->needs_tv_clock)
3548                                 is_tv = true;
3549                         break;
3550                 case INTEL_OUTPUT_DVO:
3551                         is_dvo = true;
3552                         break;
3553                 case INTEL_OUTPUT_TVOUT:
3554                         is_tv = true;
3555                         break;
3556                 case INTEL_OUTPUT_ANALOG:
3557                         is_crt = true;
3558                         break;
3559                 case INTEL_OUTPUT_DISPLAYPORT:
3560                         is_dp = true;
3561                         break;
3562                 case INTEL_OUTPUT_EDP:
3563                         has_edp_encoder = intel_encoder;
3564                         break;
3565                 }
3566
3567                 num_connectors++;
3568         }
3569
3570         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3571                 refclk = dev_priv->lvds_ssc_freq * 1000;
3572                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3573                                         refclk / 1000);
3574         } else if (IS_I9XX(dev)) {
3575                 refclk = 96000;
3576                 if (HAS_PCH_SPLIT(dev))
3577                         refclk = 120000; /* 120Mhz refclk */
3578         } else {
3579                 refclk = 48000;
3580         }
3581
3582
3583         /*
3584          * Returns a set of divisors for the desired target clock with the given
3585          * refclk, or FALSE.  The returned values represent the clock equation:
3586          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3587          */
3588         limit = intel_limit(crtc);
3589         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3590         if (!ok) {
3591                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3592                 drm_vblank_post_modeset(dev, pipe);
3593                 return -EINVAL;
3594         }
3595
3596         /* Ensure that the cursor is valid for the new mode before changing... */
3597         intel_crtc_update_cursor(crtc);
3598
3599         if (is_lvds && dev_priv->lvds_downclock_avail) {
3600                 has_reduced_clock = limit->find_pll(limit, crtc,
3601                                                             dev_priv->lvds_downclock,
3602                                                             refclk,
3603                                                             &reduced_clock);
3604                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3605                         /*
3606                          * If the different P is found, it means that we can't
3607                          * switch the display clock by using the FP0/FP1.
3608                          * In such case we will disable the LVDS downclock
3609                          * feature.
3610                          */
3611                         DRM_DEBUG_KMS("Different P is found for "
3612                                                 "LVDS clock/downclock\n");
3613                         has_reduced_clock = 0;
3614                 }
3615         }
3616         /* SDVO TV has fixed PLL values depend on its clock range,
3617            this mirrors vbios setting. */
3618         if (is_sdvo && is_tv) {
3619                 if (adjusted_mode->clock >= 100000
3620                                 && adjusted_mode->clock < 140500) {
3621                         clock.p1 = 2;
3622                         clock.p2 = 10;
3623                         clock.n = 3;
3624                         clock.m1 = 16;
3625                         clock.m2 = 8;
3626                 } else if (adjusted_mode->clock >= 140500
3627                                 && adjusted_mode->clock <= 200000) {
3628                         clock.p1 = 1;
3629                         clock.p2 = 10;
3630                         clock.n = 6;
3631                         clock.m1 = 12;
3632                         clock.m2 = 8;
3633                 }
3634         }
3635
3636         /* FDI link */
3637         if (HAS_PCH_SPLIT(dev)) {
3638                 int lane = 0, link_bw, bpp;
3639                 /* eDP doesn't require FDI link, so just set DP M/N
3640                    according to current link config */
3641                 if (has_edp_encoder) {
3642                         target_clock = mode->clock;
3643                         intel_edp_link_config(has_edp_encoder,
3644                                               &lane, &link_bw);
3645                 } else {
3646                         /* DP over FDI requires target mode clock
3647                            instead of link clock */
3648                         if (is_dp)
3649                                 target_clock = mode->clock;
3650                         else
3651                                 target_clock = adjusted_mode->clock;
3652                         link_bw = 270000;
3653                 }
3654
3655                 /* determine panel color depth */
3656                 temp = I915_READ(pipeconf_reg);
3657                 temp &= ~PIPE_BPC_MASK;
3658                 if (is_lvds) {
3659                         int lvds_reg = I915_READ(PCH_LVDS);
3660                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3661                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3662                                 temp |= PIPE_8BPC;
3663                         else
3664                                 temp |= PIPE_6BPC;
3665                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3666                         switch (dev_priv->edp_bpp/3) {
3667                         case 8:
3668                                 temp |= PIPE_8BPC;
3669                                 break;
3670                         case 10:
3671                                 temp |= PIPE_10BPC;
3672                                 break;
3673                         case 6:
3674                                 temp |= PIPE_6BPC;
3675                                 break;
3676                         case 12:
3677                                 temp |= PIPE_12BPC;
3678                                 break;
3679                         }
3680                 } else
3681                         temp |= PIPE_8BPC;
3682                 I915_WRITE(pipeconf_reg, temp);
3683                 I915_READ(pipeconf_reg);
3684
3685                 switch (temp & PIPE_BPC_MASK) {
3686                 case PIPE_8BPC:
3687                         bpp = 24;
3688                         break;
3689                 case PIPE_10BPC:
3690                         bpp = 30;
3691                         break;
3692                 case PIPE_6BPC:
3693                         bpp = 18;
3694                         break;
3695                 case PIPE_12BPC:
3696                         bpp = 36;
3697                         break;
3698                 default:
3699                         DRM_ERROR("unknown pipe bpc value\n");
3700                         bpp = 24;
3701                 }
3702
3703                 if (!lane) {
3704                         /*
3705                          * Account for spread spectrum to avoid
3706                          * oversubscribing the link. Max center spread
3707                          * is 2.5%; use 5% for safety's sake.
3708                          */
3709                         u32 bps = target_clock * bpp * 21 / 20;
3710                         lane = bps / (link_bw * 8) + 1;
3711                 }
3712
3713                 intel_crtc->fdi_lanes = lane;
3714
3715                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3716         }
3717
3718         /* Ironlake: try to setup display ref clock before DPLL
3719          * enabling. This is only under driver's control after
3720          * PCH B stepping, previous chipset stepping should be
3721          * ignoring this setting.
3722          */
3723         if (HAS_PCH_SPLIT(dev)) {
3724                 temp = I915_READ(PCH_DREF_CONTROL);
3725                 /* Always enable nonspread source */
3726                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3727                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3728                 I915_WRITE(PCH_DREF_CONTROL, temp);
3729                 POSTING_READ(PCH_DREF_CONTROL);
3730
3731                 temp &= ~DREF_SSC_SOURCE_MASK;
3732                 temp |= DREF_SSC_SOURCE_ENABLE;
3733                 I915_WRITE(PCH_DREF_CONTROL, temp);
3734                 POSTING_READ(PCH_DREF_CONTROL);
3735
3736                 udelay(200);
3737
3738                 if (has_edp_encoder) {
3739                         if (dev_priv->lvds_use_ssc) {
3740                                 temp |= DREF_SSC1_ENABLE;
3741                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3742                                 POSTING_READ(PCH_DREF_CONTROL);
3743
3744                                 udelay(200);
3745
3746                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3747                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3748                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3749                                 POSTING_READ(PCH_DREF_CONTROL);
3750                         } else {
3751                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3752                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3753                                 POSTING_READ(PCH_DREF_CONTROL);
3754                         }
3755                 }
3756         }
3757
3758         if (IS_PINEVIEW(dev)) {
3759                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3760                 if (has_reduced_clock)
3761                         fp2 = (1 << reduced_clock.n) << 16 |
3762                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3763         } else {
3764                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3765                 if (has_reduced_clock)
3766                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3767                                 reduced_clock.m2;
3768         }
3769
3770         if (!HAS_PCH_SPLIT(dev))
3771                 dpll = DPLL_VGA_MODE_DIS;
3772
3773         if (IS_I9XX(dev)) {
3774                 if (is_lvds)
3775                         dpll |= DPLLB_MODE_LVDS;
3776                 else
3777                         dpll |= DPLLB_MODE_DAC_SERIAL;
3778                 if (is_sdvo) {
3779                         dpll |= DPLL_DVO_HIGH_SPEED;
3780                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3781                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3782                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3783                         else if (HAS_PCH_SPLIT(dev))
3784                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3785                 }
3786                 if (is_dp)
3787                         dpll |= DPLL_DVO_HIGH_SPEED;
3788
3789                 /* compute bitmask from p1 value */
3790                 if (IS_PINEVIEW(dev))
3791                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3792                 else {
3793                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3794                         /* also FPA1 */
3795                         if (HAS_PCH_SPLIT(dev))
3796                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3797                         if (IS_G4X(dev) && has_reduced_clock)
3798                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3799                 }
3800                 switch (clock.p2) {
3801                 case 5:
3802                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3803                         break;
3804                 case 7:
3805                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3806                         break;
3807                 case 10:
3808                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3809                         break;
3810                 case 14:
3811                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3812                         break;
3813                 }
3814                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3815                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3816         } else {
3817                 if (is_lvds) {
3818                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3819                 } else {
3820                         if (clock.p1 == 2)
3821                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3822                         else
3823                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3824                         if (clock.p2 == 4)
3825                                 dpll |= PLL_P2_DIVIDE_BY_4;
3826                 }
3827         }
3828
3829         if (is_sdvo && is_tv)
3830                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3831         else if (is_tv)
3832                 /* XXX: just matching BIOS for now */
3833                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3834                 dpll |= 3;
3835         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3836                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3837         else
3838                 dpll |= PLL_REF_INPUT_DREFCLK;
3839
3840         /* setup pipeconf */
3841         pipeconf = I915_READ(pipeconf_reg);
3842
3843         /* Set up the display plane register */
3844         dspcntr = DISPPLANE_GAMMA_ENABLE;
3845
3846         /* Ironlake's plane is forced to pipe, bit 24 is to
3847            enable color space conversion */
3848         if (!HAS_PCH_SPLIT(dev)) {
3849                 if (pipe == 0)
3850                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3851                 else
3852                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3853         }
3854
3855         if (pipe == 0 && !IS_I965G(dev)) {
3856                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3857                  * core speed.
3858                  *
3859                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3860                  * pipe == 0 check?
3861                  */
3862                 if (mode->clock >
3863                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3864                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3865                 else
3866                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3867         }
3868
3869         dspcntr |= DISPLAY_PLANE_ENABLE;
3870         pipeconf |= PIPEACONF_ENABLE;
3871         dpll |= DPLL_VCO_ENABLE;
3872
3873
3874         /* Disable the panel fitter if it was on our pipe */
3875         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3876                 I915_WRITE(PFIT_CONTROL, 0);
3877
3878         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3879         drm_mode_debug_printmodeline(mode);
3880
3881         /* assign to Ironlake registers */
3882         if (HAS_PCH_SPLIT(dev)) {
3883                 fp_reg = pch_fp_reg;
3884                 dpll_reg = pch_dpll_reg;
3885         }
3886
3887         if (!has_edp_encoder) {
3888                 I915_WRITE(fp_reg, fp);
3889                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3890                 I915_READ(dpll_reg);
3891                 udelay(150);
3892         }
3893
3894         /* enable transcoder DPLL */
3895         if (HAS_PCH_CPT(dev)) {
3896                 temp = I915_READ(PCH_DPLL_SEL);
3897                 if (trans_dpll_sel == 0)
3898                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3899                 else
3900                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3901                 I915_WRITE(PCH_DPLL_SEL, temp);
3902                 I915_READ(PCH_DPLL_SEL);
3903                 udelay(150);
3904         }
3905
3906         if (HAS_PCH_SPLIT(dev)) {
3907                 pipeconf &= ~PIPE_ENABLE_DITHER;
3908                 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3909         }
3910
3911         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3912          * This is an exception to the general rule that mode_set doesn't turn
3913          * things on.
3914          */
3915         if (is_lvds) {
3916                 u32 lvds;
3917
3918                 if (HAS_PCH_SPLIT(dev))
3919                         lvds_reg = PCH_LVDS;
3920
3921                 lvds = I915_READ(lvds_reg);
3922                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3923                 if (pipe == 1) {
3924                         if (HAS_PCH_CPT(dev))
3925                                 lvds |= PORT_TRANS_B_SEL_CPT;
3926                         else
3927                                 lvds |= LVDS_PIPEB_SELECT;
3928                 } else {
3929                         if (HAS_PCH_CPT(dev))
3930                                 lvds &= ~PORT_TRANS_SEL_MASK;
3931                         else
3932                                 lvds &= ~LVDS_PIPEB_SELECT;
3933                 }
3934                 /* set the corresponsding LVDS_BORDER bit */
3935                 lvds |= dev_priv->lvds_border_bits;
3936                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3937                  * set the DPLLs for dual-channel mode or not.
3938                  */
3939                 if (clock.p2 == 7)
3940                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3941                 else
3942                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3943
3944                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3945                  * appropriately here, but we need to look more thoroughly into how
3946                  * panels behave in the two modes.
3947                  */
3948                 /* set the dithering flag */
3949                 if (IS_I965G(dev)) {
3950                         if (dev_priv->lvds_dither) {
3951                                 if (HAS_PCH_SPLIT(dev)) {
3952                                         pipeconf |= PIPE_ENABLE_DITHER;
3953                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3954                                 } else
3955                                         lvds |= LVDS_ENABLE_DITHER;
3956                         } else {
3957                                 if (!HAS_PCH_SPLIT(dev)) {
3958                                         lvds &= ~LVDS_ENABLE_DITHER;
3959                                 }
3960                         }
3961                 }
3962                 I915_WRITE(lvds_reg, lvds);
3963                 I915_READ(lvds_reg);
3964         }
3965         if (is_dp)
3966                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3967         else if (HAS_PCH_SPLIT(dev)) {
3968                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3969                 if (pipe == 0) {
3970                         I915_WRITE(TRANSA_DATA_M1, 0);
3971                         I915_WRITE(TRANSA_DATA_N1, 0);
3972                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3973                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3974                 } else {
3975                         I915_WRITE(TRANSB_DATA_M1, 0);
3976                         I915_WRITE(TRANSB_DATA_N1, 0);
3977                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3978                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3979                 }
3980         }
3981
3982         if (!has_edp_encoder) {
3983                 I915_WRITE(fp_reg, fp);
3984                 I915_WRITE(dpll_reg, dpll);
3985                 I915_READ(dpll_reg);
3986                 /* Wait for the clocks to stabilize. */
3987                 udelay(150);
3988
3989                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3990                         if (is_sdvo) {
3991                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3992                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3993                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3994                         } else
3995                                 I915_WRITE(dpll_md_reg, 0);
3996                 } else {
3997                         /* write it again -- the BIOS does, after all */
3998                         I915_WRITE(dpll_reg, dpll);
3999                 }
4000                 I915_READ(dpll_reg);
4001                 /* Wait for the clocks to stabilize. */
4002                 udelay(150);
4003         }
4004
4005         if (is_lvds && has_reduced_clock && i915_powersave) {
4006                 I915_WRITE(fp_reg + 4, fp2);
4007                 intel_crtc->lowfreq_avail = true;
4008                 if (HAS_PIPE_CXSR(dev)) {
4009                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4010                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4011                 }
4012         } else {
4013                 I915_WRITE(fp_reg + 4, fp);
4014                 intel_crtc->lowfreq_avail = false;
4015                 if (HAS_PIPE_CXSR(dev)) {
4016                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4017                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4018                 }
4019         }
4020
4021         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4022                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4023                 /* the chip adds 2 halflines automatically */
4024                 adjusted_mode->crtc_vdisplay -= 1;
4025                 adjusted_mode->crtc_vtotal -= 1;
4026                 adjusted_mode->crtc_vblank_start -= 1;
4027                 adjusted_mode->crtc_vblank_end -= 1;
4028                 adjusted_mode->crtc_vsync_end -= 1;
4029                 adjusted_mode->crtc_vsync_start -= 1;
4030         } else
4031                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4032
4033         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4034                    ((adjusted_mode->crtc_htotal - 1) << 16));
4035         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4036                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4037         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4038                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4039         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4040                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4041         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4042                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4043         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4044                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4045         /* pipesrc and dspsize control the size that is scaled from, which should
4046          * always be the user's requested size.
4047          */
4048         if (!HAS_PCH_SPLIT(dev)) {
4049                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4050                                 (mode->hdisplay - 1));
4051                 I915_WRITE(dsppos_reg, 0);
4052         }
4053         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4054
4055         if (HAS_PCH_SPLIT(dev)) {
4056                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4057                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4058                 I915_WRITE(link_m1_reg, m_n.link_m);
4059                 I915_WRITE(link_n1_reg, m_n.link_n);
4060
4061                 if (has_edp_encoder) {
4062                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4063                 } else {
4064                         /* enable FDI RX PLL too */
4065                         temp = I915_READ(fdi_rx_reg);
4066                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4067                         I915_READ(fdi_rx_reg);
4068                         udelay(200);
4069
4070                         /* enable FDI TX PLL too */
4071                         temp = I915_READ(fdi_tx_reg);
4072                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4073                         I915_READ(fdi_tx_reg);
4074
4075                         /* enable FDI RX PCDCLK */
4076                         temp = I915_READ(fdi_rx_reg);
4077                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4078                         I915_READ(fdi_rx_reg);
4079                         udelay(200);
4080                 }
4081         }
4082
4083         I915_WRITE(pipeconf_reg, pipeconf);
4084         I915_READ(pipeconf_reg);
4085
4086         intel_wait_for_vblank(dev, pipe);
4087
4088         if (IS_IRONLAKE(dev)) {
4089                 /* enable address swizzle for tiling buffer */
4090                 temp = I915_READ(DISP_ARB_CTL);
4091                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4092         }
4093
4094         I915_WRITE(dspcntr_reg, dspcntr);
4095
4096         /* Flush the plane changes */
4097         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4098
4099         intel_update_watermarks(dev);
4100
4101         drm_vblank_post_modeset(dev, pipe);
4102
4103         return ret;
4104 }
4105
4106 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4107 void intel_crtc_load_lut(struct drm_crtc *crtc)
4108 {
4109         struct drm_device *dev = crtc->dev;
4110         struct drm_i915_private *dev_priv = dev->dev_private;
4111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4112         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4113         int i;
4114
4115         /* The clocks have to be on to load the palette. */
4116         if (!crtc->enabled)
4117                 return;
4118
4119         /* use legacy palette for Ironlake */
4120         if (HAS_PCH_SPLIT(dev))
4121                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4122                                                    LGC_PALETTE_B;
4123
4124         for (i = 0; i < 256; i++) {
4125                 I915_WRITE(palreg + 4 * i,
4126                            (intel_crtc->lut_r[i] << 16) |
4127                            (intel_crtc->lut_g[i] << 8) |
4128                            intel_crtc->lut_b[i]);
4129         }
4130 }
4131
4132 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4133 {
4134         struct drm_device *dev = crtc->dev;
4135         struct drm_i915_private *dev_priv = dev->dev_private;
4136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4137         bool visible = base != 0;
4138         u32 cntl;
4139
4140         if (intel_crtc->cursor_visible == visible)
4141                 return;
4142
4143         cntl = I915_READ(CURACNTR);
4144         if (visible) {
4145                 /* On these chipsets we can only modify the base whilst
4146                  * the cursor is disabled.
4147                  */
4148                 I915_WRITE(CURABASE, base);
4149
4150                 cntl &= ~(CURSOR_FORMAT_MASK);
4151                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4152                 cntl |= CURSOR_ENABLE |
4153                         CURSOR_GAMMA_ENABLE |
4154                         CURSOR_FORMAT_ARGB;
4155         } else
4156                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4157         I915_WRITE(CURACNTR, cntl);
4158
4159         intel_crtc->cursor_visible = visible;
4160 }
4161
4162 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4163 {
4164         struct drm_device *dev = crtc->dev;
4165         struct drm_i915_private *dev_priv = dev->dev_private;
4166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4167         int pipe = intel_crtc->pipe;
4168         bool visible = base != 0;
4169
4170         if (intel_crtc->cursor_visible != visible) {
4171                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4172                 if (base) {
4173                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4174                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4175                         cntl |= pipe << 28; /* Connect to correct pipe */
4176                 } else {
4177                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4178                         cntl |= CURSOR_MODE_DISABLE;
4179                 }
4180                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4181
4182                 intel_crtc->cursor_visible = visible;
4183         }
4184         /* and commit changes on next vblank */
4185         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4186 }
4187
4188 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4189 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4190 {
4191         struct drm_device *dev = crtc->dev;
4192         struct drm_i915_private *dev_priv = dev->dev_private;
4193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4194         int pipe = intel_crtc->pipe;
4195         int x = intel_crtc->cursor_x;
4196         int y = intel_crtc->cursor_y;
4197         u32 base, pos;
4198         bool visible;
4199
4200         pos = 0;
4201
4202         if (intel_crtc->cursor_on && crtc->fb) {
4203                 base = intel_crtc->cursor_addr;
4204                 if (x > (int) crtc->fb->width)
4205                         base = 0;
4206
4207                 if (y > (int) crtc->fb->height)
4208                         base = 0;
4209         } else
4210                 base = 0;
4211
4212         if (x < 0) {
4213                 if (x + intel_crtc->cursor_width < 0)
4214                         base = 0;
4215
4216                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4217                 x = -x;
4218         }
4219         pos |= x << CURSOR_X_SHIFT;
4220
4221         if (y < 0) {
4222                 if (y + intel_crtc->cursor_height < 0)
4223                         base = 0;
4224
4225                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4226                 y = -y;
4227         }
4228         pos |= y << CURSOR_Y_SHIFT;
4229
4230         visible = base != 0;
4231         if (!visible && !intel_crtc->cursor_visible)
4232                 return;
4233
4234         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4235         if (IS_845G(dev) || IS_I865G(dev))
4236                 i845_update_cursor(crtc, base);
4237         else
4238                 i9xx_update_cursor(crtc, base);
4239
4240         if (visible)
4241                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4242 }
4243
4244 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4245                                  struct drm_file *file_priv,
4246                                  uint32_t handle,
4247                                  uint32_t width, uint32_t height)
4248 {
4249         struct drm_device *dev = crtc->dev;
4250         struct drm_i915_private *dev_priv = dev->dev_private;
4251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252         struct drm_gem_object *bo;
4253         struct drm_i915_gem_object *obj_priv;
4254         uint32_t addr;
4255         int ret;
4256
4257         DRM_DEBUG_KMS("\n");
4258
4259         /* if we want to turn off the cursor ignore width and height */
4260         if (!handle) {
4261                 DRM_DEBUG_KMS("cursor off\n");
4262                 addr = 0;
4263                 bo = NULL;
4264                 mutex_lock(&dev->struct_mutex);
4265                 goto finish;
4266         }
4267
4268         /* Currently we only support 64x64 cursors */
4269         if (width != 64 || height != 64) {
4270                 DRM_ERROR("we currently only support 64x64 cursors\n");
4271                 return -EINVAL;
4272         }
4273
4274         bo = drm_gem_object_lookup(dev, file_priv, handle);
4275         if (!bo)
4276                 return -ENOENT;
4277
4278         obj_priv = to_intel_bo(bo);
4279
4280         if (bo->size < width * height * 4) {
4281                 DRM_ERROR("buffer is to small\n");
4282                 ret = -ENOMEM;
4283                 goto fail;
4284         }
4285
4286         /* we only need to pin inside GTT if cursor is non-phy */
4287         mutex_lock(&dev->struct_mutex);
4288         if (!dev_priv->info->cursor_needs_physical) {
4289                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4290                 if (ret) {
4291                         DRM_ERROR("failed to pin cursor bo\n");
4292                         goto fail_locked;
4293                 }
4294
4295                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4296                 if (ret) {
4297                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4298                         goto fail_unpin;
4299                 }
4300
4301                 addr = obj_priv->gtt_offset;
4302         } else {
4303                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4304                 ret = i915_gem_attach_phys_object(dev, bo,
4305                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4306                                                   align);
4307                 if (ret) {
4308                         DRM_ERROR("failed to attach phys object\n");
4309                         goto fail_locked;
4310                 }
4311                 addr = obj_priv->phys_obj->handle->busaddr;
4312         }
4313
4314         if (!IS_I9XX(dev))
4315                 I915_WRITE(CURSIZE, (height << 12) | width);
4316
4317  finish:
4318         if (intel_crtc->cursor_bo) {
4319                 if (dev_priv->info->cursor_needs_physical) {
4320                         if (intel_crtc->cursor_bo != bo)
4321                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4322                 } else
4323                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4324                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4325         }
4326
4327         mutex_unlock(&dev->struct_mutex);
4328
4329         intel_crtc->cursor_addr = addr;
4330         intel_crtc->cursor_bo = bo;
4331         intel_crtc->cursor_width = width;
4332         intel_crtc->cursor_height = height;
4333
4334         intel_crtc_update_cursor(crtc);
4335
4336         return 0;
4337 fail_unpin:
4338         i915_gem_object_unpin(bo);
4339 fail_locked:
4340         mutex_unlock(&dev->struct_mutex);
4341 fail:
4342         drm_gem_object_unreference_unlocked(bo);
4343         return ret;
4344 }
4345
4346 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4347 {
4348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4349
4350         intel_crtc->cursor_x = x;
4351         intel_crtc->cursor_y = y;
4352
4353         intel_crtc_update_cursor(crtc);
4354
4355         return 0;
4356 }
4357
4358 /** Sets the color ramps on behalf of RandR */
4359 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4360                                  u16 blue, int regno)
4361 {
4362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4363
4364         intel_crtc->lut_r[regno] = red >> 8;
4365         intel_crtc->lut_g[regno] = green >> 8;
4366         intel_crtc->lut_b[regno] = blue >> 8;
4367 }
4368
4369 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4370                              u16 *blue, int regno)
4371 {
4372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4373
4374         *red = intel_crtc->lut_r[regno] << 8;
4375         *green = intel_crtc->lut_g[regno] << 8;
4376         *blue = intel_crtc->lut_b[regno] << 8;
4377 }
4378
4379 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4380                                  u16 *blue, uint32_t start, uint32_t size)
4381 {
4382         int end = (start + size > 256) ? 256 : start + size, i;
4383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4384
4385         for (i = start; i < end; i++) {
4386                 intel_crtc->lut_r[i] = red[i] >> 8;
4387                 intel_crtc->lut_g[i] = green[i] >> 8;
4388                 intel_crtc->lut_b[i] = blue[i] >> 8;
4389         }
4390
4391         intel_crtc_load_lut(crtc);
4392 }
4393
4394 /**
4395  * Get a pipe with a simple mode set on it for doing load-based monitor
4396  * detection.
4397  *
4398  * It will be up to the load-detect code to adjust the pipe as appropriate for
4399  * its requirements.  The pipe will be connected to no other encoders.
4400  *
4401  * Currently this code will only succeed if there is a pipe with no encoders
4402  * configured for it.  In the future, it could choose to temporarily disable
4403  * some outputs to free up a pipe for its use.
4404  *
4405  * \return crtc, or NULL if no pipes are available.
4406  */
4407
4408 /* VESA 640x480x72Hz mode to set on the pipe */
4409 static struct drm_display_mode load_detect_mode = {
4410         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4411                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4412 };
4413
4414 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4415                                             struct drm_connector *connector,
4416                                             struct drm_display_mode *mode,
4417                                             int *dpms_mode)
4418 {
4419         struct intel_crtc *intel_crtc;
4420         struct drm_crtc *possible_crtc;
4421         struct drm_crtc *supported_crtc =NULL;
4422         struct drm_encoder *encoder = &intel_encoder->enc;
4423         struct drm_crtc *crtc = NULL;
4424         struct drm_device *dev = encoder->dev;
4425         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4426         struct drm_crtc_helper_funcs *crtc_funcs;
4427         int i = -1;
4428
4429         /*
4430          * Algorithm gets a little messy:
4431          *   - if the connector already has an assigned crtc, use it (but make
4432          *     sure it's on first)
4433          *   - try to find the first unused crtc that can drive this connector,
4434          *     and use that if we find one
4435          *   - if there are no unused crtcs available, try to use the first
4436          *     one we found that supports the connector
4437          */
4438
4439         /* See if we already have a CRTC for this connector */
4440         if (encoder->crtc) {
4441                 crtc = encoder->crtc;
4442                 /* Make sure the crtc and connector are running */
4443                 intel_crtc = to_intel_crtc(crtc);
4444                 *dpms_mode = intel_crtc->dpms_mode;
4445                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4446                         crtc_funcs = crtc->helper_private;
4447                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4448                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4449                 }
4450                 return crtc;
4451         }
4452
4453         /* Find an unused one (if possible) */
4454         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4455                 i++;
4456                 if (!(encoder->possible_crtcs & (1 << i)))
4457                         continue;
4458                 if (!possible_crtc->enabled) {
4459                         crtc = possible_crtc;
4460                         break;
4461                 }
4462                 if (!supported_crtc)
4463                         supported_crtc = possible_crtc;
4464         }
4465
4466         /*
4467          * If we didn't find an unused CRTC, don't use any.
4468          */
4469         if (!crtc) {
4470                 return NULL;
4471         }
4472
4473         encoder->crtc = crtc;
4474         connector->encoder = encoder;
4475         intel_encoder->load_detect_temp = true;
4476
4477         intel_crtc = to_intel_crtc(crtc);
4478         *dpms_mode = intel_crtc->dpms_mode;
4479
4480         if (!crtc->enabled) {
4481                 if (!mode)
4482                         mode = &load_detect_mode;
4483                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4484         } else {
4485                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4486                         crtc_funcs = crtc->helper_private;
4487                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4488                 }
4489
4490                 /* Add this connector to the crtc */
4491                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4492                 encoder_funcs->commit(encoder);
4493         }
4494         /* let the connector get through one full cycle before testing */
4495         intel_wait_for_vblank(dev, intel_crtc->pipe);
4496
4497         return crtc;
4498 }
4499
4500 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4501                                     struct drm_connector *connector, int dpms_mode)
4502 {
4503         struct drm_encoder *encoder = &intel_encoder->enc;
4504         struct drm_device *dev = encoder->dev;
4505         struct drm_crtc *crtc = encoder->crtc;
4506         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4507         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4508
4509         if (intel_encoder->load_detect_temp) {
4510                 encoder->crtc = NULL;
4511                 connector->encoder = NULL;
4512                 intel_encoder->load_detect_temp = false;
4513                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4514                 drm_helper_disable_unused_functions(dev);
4515         }
4516
4517         /* Switch crtc and encoder back off if necessary */
4518         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4519                 if (encoder->crtc == crtc)
4520                         encoder_funcs->dpms(encoder, dpms_mode);
4521                 crtc_funcs->dpms(crtc, dpms_mode);
4522         }
4523 }
4524
4525 /* Returns the clock of the currently programmed mode of the given pipe. */
4526 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4527 {
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4530         int pipe = intel_crtc->pipe;
4531         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4532         u32 fp;
4533         intel_clock_t clock;
4534
4535         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4536                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4537         else
4538                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4539
4540         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4541         if (IS_PINEVIEW(dev)) {
4542                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4543                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4544         } else {
4545                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4546                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4547         }
4548
4549         if (IS_I9XX(dev)) {
4550                 if (IS_PINEVIEW(dev))
4551                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4552                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4553                 else
4554                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4555                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4556
4557                 switch (dpll & DPLL_MODE_MASK) {
4558                 case DPLLB_MODE_DAC_SERIAL:
4559                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4560                                 5 : 10;
4561                         break;
4562                 case DPLLB_MODE_LVDS:
4563                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4564                                 7 : 14;
4565                         break;
4566                 default:
4567                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4568                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4569                         return 0;
4570                 }
4571
4572                 /* XXX: Handle the 100Mhz refclk */
4573                 intel_clock(dev, 96000, &clock);
4574         } else {
4575                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4576
4577                 if (is_lvds) {
4578                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4579                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4580                         clock.p2 = 14;
4581
4582                         if ((dpll & PLL_REF_INPUT_MASK) ==
4583                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4584                                 /* XXX: might not be 66MHz */
4585                                 intel_clock(dev, 66000, &clock);
4586                         } else
4587                                 intel_clock(dev, 48000, &clock);
4588                 } else {
4589                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4590                                 clock.p1 = 2;
4591                         else {
4592                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4593                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4594                         }
4595                         if (dpll & PLL_P2_DIVIDE_BY_4)
4596                                 clock.p2 = 4;
4597                         else
4598                                 clock.p2 = 2;
4599
4600                         intel_clock(dev, 48000, &clock);
4601                 }
4602         }
4603
4604         /* XXX: It would be nice to validate the clocks, but we can't reuse
4605          * i830PllIsValid() because it relies on the xf86_config connector
4606          * configuration being accurate, which it isn't necessarily.
4607          */
4608
4609         return clock.dot;
4610 }
4611
4612 /** Returns the currently programmed mode of the given pipe. */
4613 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4614                                              struct drm_crtc *crtc)
4615 {
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4618         int pipe = intel_crtc->pipe;
4619         struct drm_display_mode *mode;
4620         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4621         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4622         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4623         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4624
4625         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4626         if (!mode)
4627                 return NULL;
4628
4629         mode->clock = intel_crtc_clock_get(dev, crtc);
4630         mode->hdisplay = (htot & 0xffff) + 1;
4631         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4632         mode->hsync_start = (hsync & 0xffff) + 1;
4633         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4634         mode->vdisplay = (vtot & 0xffff) + 1;
4635         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4636         mode->vsync_start = (vsync & 0xffff) + 1;
4637         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4638
4639         drm_mode_set_name(mode);
4640         drm_mode_set_crtcinfo(mode, 0);
4641
4642         return mode;
4643 }
4644
4645 #define GPU_IDLE_TIMEOUT 500 /* ms */
4646
4647 /* When this timer fires, we've been idle for awhile */
4648 static void intel_gpu_idle_timer(unsigned long arg)
4649 {
4650         struct drm_device *dev = (struct drm_device *)arg;
4651         drm_i915_private_t *dev_priv = dev->dev_private;
4652
4653         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4654
4655         dev_priv->busy = false;
4656
4657         queue_work(dev_priv->wq, &dev_priv->idle_work);
4658 }
4659
4660 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4661
4662 static void intel_crtc_idle_timer(unsigned long arg)
4663 {
4664         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4665         struct drm_crtc *crtc = &intel_crtc->base;
4666         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4667
4668         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4669
4670         intel_crtc->busy = false;
4671
4672         queue_work(dev_priv->wq, &dev_priv->idle_work);
4673 }
4674
4675 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4676 {
4677         struct drm_device *dev = crtc->dev;
4678         drm_i915_private_t *dev_priv = dev->dev_private;
4679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4680         int pipe = intel_crtc->pipe;
4681         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4682         int dpll = I915_READ(dpll_reg);
4683
4684         if (HAS_PCH_SPLIT(dev))
4685                 return;
4686
4687         if (!dev_priv->lvds_downclock_avail)
4688                 return;
4689
4690         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4691                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4692
4693                 /* Unlock panel regs */
4694                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4695                            PANEL_UNLOCK_REGS);
4696
4697                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4698                 I915_WRITE(dpll_reg, dpll);
4699                 dpll = I915_READ(dpll_reg);
4700                 intel_wait_for_vblank(dev, pipe);
4701                 dpll = I915_READ(dpll_reg);
4702                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4703                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4704
4705                 /* ...and lock them again */
4706                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4707         }
4708
4709         /* Schedule downclock */
4710         if (schedule)
4711                 mod_timer(&intel_crtc->idle_timer, jiffies +
4712                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4713 }
4714
4715 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4716 {
4717         struct drm_device *dev = crtc->dev;
4718         drm_i915_private_t *dev_priv = dev->dev_private;
4719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720         int pipe = intel_crtc->pipe;
4721         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4722         int dpll = I915_READ(dpll_reg);
4723
4724         if (HAS_PCH_SPLIT(dev))
4725                 return;
4726
4727         if (!dev_priv->lvds_downclock_avail)
4728                 return;
4729
4730         /*
4731          * Since this is called by a timer, we should never get here in
4732          * the manual case.
4733          */
4734         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4735                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4736
4737                 /* Unlock panel regs */
4738                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4739                            PANEL_UNLOCK_REGS);
4740
4741                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4742                 I915_WRITE(dpll_reg, dpll);
4743                 dpll = I915_READ(dpll_reg);
4744                 intel_wait_for_vblank(dev, pipe);
4745                 dpll = I915_READ(dpll_reg);
4746                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4747                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4748
4749                 /* ...and lock them again */
4750                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4751         }
4752
4753 }
4754
4755 /**
4756  * intel_idle_update - adjust clocks for idleness
4757  * @work: work struct
4758  *
4759  * Either the GPU or display (or both) went idle.  Check the busy status
4760  * here and adjust the CRTC and GPU clocks as necessary.
4761  */
4762 static void intel_idle_update(struct work_struct *work)
4763 {
4764         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4765                                                     idle_work);
4766         struct drm_device *dev = dev_priv->dev;
4767         struct drm_crtc *crtc;
4768         struct intel_crtc *intel_crtc;
4769         int enabled = 0;
4770
4771         if (!i915_powersave)
4772                 return;
4773
4774         mutex_lock(&dev->struct_mutex);
4775
4776         i915_update_gfx_val(dev_priv);
4777
4778         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4779                 /* Skip inactive CRTCs */
4780                 if (!crtc->fb)
4781                         continue;
4782
4783                 enabled++;
4784                 intel_crtc = to_intel_crtc(crtc);
4785                 if (!intel_crtc->busy)
4786                         intel_decrease_pllclock(crtc);
4787         }
4788
4789         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4790                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4791                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4792         }
4793
4794         mutex_unlock(&dev->struct_mutex);
4795 }
4796
4797 /**
4798  * intel_mark_busy - mark the GPU and possibly the display busy
4799  * @dev: drm device
4800  * @obj: object we're operating on
4801  *
4802  * Callers can use this function to indicate that the GPU is busy processing
4803  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4804  * buffer), we'll also mark the display as busy, so we know to increase its
4805  * clock frequency.
4806  */
4807 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4808 {
4809         drm_i915_private_t *dev_priv = dev->dev_private;
4810         struct drm_crtc *crtc = NULL;
4811         struct intel_framebuffer *intel_fb;
4812         struct intel_crtc *intel_crtc;
4813
4814         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4815                 return;
4816
4817         if (!dev_priv->busy) {
4818                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4819                         u32 fw_blc_self;
4820
4821                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4822                         fw_blc_self = I915_READ(FW_BLC_SELF);
4823                         fw_blc_self &= ~FW_BLC_SELF_EN;
4824                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4825                 }
4826                 dev_priv->busy = true;
4827         } else
4828                 mod_timer(&dev_priv->idle_timer, jiffies +
4829                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4830
4831         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4832                 if (!crtc->fb)
4833                         continue;
4834
4835                 intel_crtc = to_intel_crtc(crtc);
4836                 intel_fb = to_intel_framebuffer(crtc->fb);
4837                 if (intel_fb->obj == obj) {
4838                         if (!intel_crtc->busy) {
4839                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4840                                         u32 fw_blc_self;
4841
4842                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4843                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4844                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4845                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4846                                 }
4847                                 /* Non-busy -> busy, upclock */
4848                                 intel_increase_pllclock(crtc, true);
4849                                 intel_crtc->busy = true;
4850                         } else {
4851                                 /* Busy -> busy, put off timer */
4852                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4853                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4854                         }
4855                 }
4856         }
4857 }
4858
4859 static void intel_crtc_destroy(struct drm_crtc *crtc)
4860 {
4861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4862
4863         drm_crtc_cleanup(crtc);
4864         kfree(intel_crtc);
4865 }
4866
4867 struct intel_unpin_work {
4868         struct work_struct work;
4869         struct drm_device *dev;
4870         struct drm_gem_object *old_fb_obj;
4871         struct drm_gem_object *pending_flip_obj;
4872         struct drm_pending_vblank_event *event;
4873         int pending;
4874 };
4875
4876 static void intel_unpin_work_fn(struct work_struct *__work)
4877 {
4878         struct intel_unpin_work *work =
4879                 container_of(__work, struct intel_unpin_work, work);
4880
4881         mutex_lock(&work->dev->struct_mutex);
4882         i915_gem_object_unpin(work->old_fb_obj);
4883         drm_gem_object_unreference(work->pending_flip_obj);
4884         drm_gem_object_unreference(work->old_fb_obj);
4885         mutex_unlock(&work->dev->struct_mutex);
4886         kfree(work);
4887 }
4888
4889 static void do_intel_finish_page_flip(struct drm_device *dev,
4890                                       struct drm_crtc *crtc)
4891 {
4892         drm_i915_private_t *dev_priv = dev->dev_private;
4893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894         struct intel_unpin_work *work;
4895         struct drm_i915_gem_object *obj_priv;
4896         struct drm_pending_vblank_event *e;
4897         struct timeval now;
4898         unsigned long flags;
4899
4900         /* Ignore early vblank irqs */
4901         if (intel_crtc == NULL)
4902                 return;
4903
4904         spin_lock_irqsave(&dev->event_lock, flags);
4905         work = intel_crtc->unpin_work;
4906         if (work == NULL || !work->pending) {
4907                 spin_unlock_irqrestore(&dev->event_lock, flags);
4908                 return;
4909         }
4910
4911         intel_crtc->unpin_work = NULL;
4912         drm_vblank_put(dev, intel_crtc->pipe);
4913
4914         if (work->event) {
4915                 e = work->event;
4916                 do_gettimeofday(&now);
4917                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4918                 e->event.tv_sec = now.tv_sec;
4919                 e->event.tv_usec = now.tv_usec;
4920                 list_add_tail(&e->base.link,
4921                               &e->base.file_priv->event_list);
4922                 wake_up_interruptible(&e->base.file_priv->event_wait);
4923         }
4924
4925         spin_unlock_irqrestore(&dev->event_lock, flags);
4926
4927         obj_priv = to_intel_bo(work->pending_flip_obj);
4928
4929         /* Initial scanout buffer will have a 0 pending flip count */
4930         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4931             atomic_dec_and_test(&obj_priv->pending_flip))
4932                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4933         schedule_work(&work->work);
4934
4935         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4936 }
4937
4938 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4939 {
4940         drm_i915_private_t *dev_priv = dev->dev_private;
4941         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4942
4943         do_intel_finish_page_flip(dev, crtc);
4944 }
4945
4946 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4947 {
4948         drm_i915_private_t *dev_priv = dev->dev_private;
4949         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4950
4951         do_intel_finish_page_flip(dev, crtc);
4952 }
4953
4954 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4955 {
4956         drm_i915_private_t *dev_priv = dev->dev_private;
4957         struct intel_crtc *intel_crtc =
4958                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4959         unsigned long flags;
4960
4961         spin_lock_irqsave(&dev->event_lock, flags);
4962         if (intel_crtc->unpin_work) {
4963                 intel_crtc->unpin_work->pending = 1;
4964         } else {
4965                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4966         }
4967         spin_unlock_irqrestore(&dev->event_lock, flags);
4968 }
4969
4970 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4971                                 struct drm_framebuffer *fb,
4972                                 struct drm_pending_vblank_event *event)
4973 {
4974         struct drm_device *dev = crtc->dev;
4975         struct drm_i915_private *dev_priv = dev->dev_private;
4976         struct intel_framebuffer *intel_fb;
4977         struct drm_i915_gem_object *obj_priv;
4978         struct drm_gem_object *obj;
4979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980         struct intel_unpin_work *work;
4981         unsigned long flags, offset;
4982         int pipe = intel_crtc->pipe;
4983         u32 pf, pipesrc;
4984         int ret;
4985
4986         work = kzalloc(sizeof *work, GFP_KERNEL);
4987         if (work == NULL)
4988                 return -ENOMEM;
4989
4990         work->event = event;
4991         work->dev = crtc->dev;
4992         intel_fb = to_intel_framebuffer(crtc->fb);
4993         work->old_fb_obj = intel_fb->obj;
4994         INIT_WORK(&work->work, intel_unpin_work_fn);
4995
4996         /* We borrow the event spin lock for protecting unpin_work */
4997         spin_lock_irqsave(&dev->event_lock, flags);
4998         if (intel_crtc->unpin_work) {
4999                 spin_unlock_irqrestore(&dev->event_lock, flags);
5000                 kfree(work);
5001
5002                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5003                 return -EBUSY;
5004         }
5005         intel_crtc->unpin_work = work;
5006         spin_unlock_irqrestore(&dev->event_lock, flags);
5007
5008         intel_fb = to_intel_framebuffer(fb);
5009         obj = intel_fb->obj;
5010
5011         mutex_lock(&dev->struct_mutex);
5012         ret = intel_pin_and_fence_fb_obj(dev, obj);
5013         if (ret)
5014                 goto cleanup_work;
5015
5016         /* Reference the objects for the scheduled work. */
5017         drm_gem_object_reference(work->old_fb_obj);
5018         drm_gem_object_reference(obj);
5019
5020         crtc->fb = fb;
5021         ret = i915_gem_object_flush_write_domain(obj);
5022         if (ret)
5023                 goto cleanup_objs;
5024
5025         ret = drm_vblank_get(dev, intel_crtc->pipe);
5026         if (ret)
5027                 goto cleanup_objs;
5028
5029         obj_priv = to_intel_bo(obj);
5030         atomic_inc(&obj_priv->pending_flip);
5031         work->pending_flip_obj = obj;
5032
5033         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5034                 u32 flip_mask;
5035
5036                 if (intel_crtc->plane)
5037                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5038                 else
5039                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5040
5041                 BEGIN_LP_RING(2);
5042                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5043                 OUT_RING(0);
5044                 ADVANCE_LP_RING();
5045         }
5046
5047         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5048         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5049
5050         BEGIN_LP_RING(4);
5051         switch(INTEL_INFO(dev)->gen) {
5052         case 2:
5053                 OUT_RING(MI_DISPLAY_FLIP |
5054                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5055                 OUT_RING(fb->pitch);
5056                 OUT_RING(obj_priv->gtt_offset + offset);
5057                 OUT_RING(MI_NOOP);
5058                 break;
5059
5060         case 3:
5061                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5062                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5063                 OUT_RING(fb->pitch);
5064                 OUT_RING(obj_priv->gtt_offset + offset);
5065                 OUT_RING(MI_NOOP);
5066                 break;
5067
5068         case 4:
5069         case 5:
5070                 /* i965+ uses the linear or tiled offsets from the
5071                  * Display Registers (which do not change across a page-flip)
5072                  * so we need only reprogram the base address.
5073                  */
5074                 OUT_RING(MI_DISPLAY_FLIP |
5075                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5076                 OUT_RING(fb->pitch);
5077                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5078
5079                 /* XXX Enabling the panel-fitter across page-flip is so far
5080                  * untested on non-native modes, so ignore it for now.
5081                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5082                  */
5083                 pf = 0;
5084                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5085                 OUT_RING(pf | pipesrc);
5086                 break;
5087
5088         case 6:
5089                 OUT_RING(MI_DISPLAY_FLIP |
5090                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5091                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5092                 OUT_RING(obj_priv->gtt_offset);
5093
5094                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5095                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5096                 OUT_RING(pf | pipesrc);
5097                 break;
5098         }
5099         ADVANCE_LP_RING();
5100
5101         mutex_unlock(&dev->struct_mutex);
5102
5103         trace_i915_flip_request(intel_crtc->plane, obj);
5104
5105         return 0;
5106
5107 cleanup_objs:
5108         drm_gem_object_unreference(work->old_fb_obj);
5109         drm_gem_object_unreference(obj);
5110 cleanup_work:
5111         mutex_unlock(&dev->struct_mutex);
5112
5113         spin_lock_irqsave(&dev->event_lock, flags);
5114         intel_crtc->unpin_work = NULL;
5115         spin_unlock_irqrestore(&dev->event_lock, flags);
5116
5117         kfree(work);
5118
5119         return ret;
5120 }
5121
5122 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5123         .dpms = intel_crtc_dpms,
5124         .mode_fixup = intel_crtc_mode_fixup,
5125         .mode_set = intel_crtc_mode_set,
5126         .mode_set_base = intel_pipe_set_base,
5127         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5128         .prepare = intel_crtc_prepare,
5129         .commit = intel_crtc_commit,
5130         .load_lut = intel_crtc_load_lut,
5131 };
5132
5133 static const struct drm_crtc_funcs intel_crtc_funcs = {
5134         .cursor_set = intel_crtc_cursor_set,
5135         .cursor_move = intel_crtc_cursor_move,
5136         .gamma_set = intel_crtc_gamma_set,
5137         .set_config = drm_crtc_helper_set_config,
5138         .destroy = intel_crtc_destroy,
5139         .page_flip = intel_crtc_page_flip,
5140 };
5141
5142
5143 static void intel_crtc_init(struct drm_device *dev, int pipe)
5144 {
5145         drm_i915_private_t *dev_priv = dev->dev_private;
5146         struct intel_crtc *intel_crtc;
5147         int i;
5148
5149         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5150         if (intel_crtc == NULL)
5151                 return;
5152
5153         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5154
5155         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5156         intel_crtc->pipe = pipe;
5157         intel_crtc->plane = pipe;
5158         for (i = 0; i < 256; i++) {
5159                 intel_crtc->lut_r[i] = i;
5160                 intel_crtc->lut_g[i] = i;
5161                 intel_crtc->lut_b[i] = i;
5162         }
5163
5164         /* Swap pipes & planes for FBC on pre-965 */
5165         intel_crtc->pipe = pipe;
5166         intel_crtc->plane = pipe;
5167         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5168                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5169                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5170         }
5171
5172         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5173                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5174         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5175         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5176
5177         intel_crtc->cursor_addr = 0;
5178         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5179         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5180
5181         intel_crtc->busy = false;
5182
5183         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5184                     (unsigned long)intel_crtc);
5185 }
5186
5187 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5188                                 struct drm_file *file_priv)
5189 {
5190         drm_i915_private_t *dev_priv = dev->dev_private;
5191         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5192         struct drm_mode_object *drmmode_obj;
5193         struct intel_crtc *crtc;
5194
5195         if (!dev_priv) {
5196                 DRM_ERROR("called with no initialization\n");
5197                 return -EINVAL;
5198         }
5199
5200         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5201                         DRM_MODE_OBJECT_CRTC);
5202
5203         if (!drmmode_obj) {
5204                 DRM_ERROR("no such CRTC id\n");
5205                 return -EINVAL;
5206         }
5207
5208         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5209         pipe_from_crtc_id->pipe = crtc->pipe;
5210
5211         return 0;
5212 }
5213
5214 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5215 {
5216         struct drm_crtc *crtc = NULL;
5217
5218         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5219                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5220                 if (intel_crtc->pipe == pipe)
5221                         break;
5222         }
5223         return crtc;
5224 }
5225
5226 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5227 {
5228         int index_mask = 0;
5229         struct drm_encoder *encoder;
5230         int entry = 0;
5231
5232         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5233                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5234                 if (type_mask & intel_encoder->clone_mask)
5235                         index_mask |= (1 << entry);
5236                 entry++;
5237         }
5238         return index_mask;
5239 }
5240
5241
5242 static void intel_setup_outputs(struct drm_device *dev)
5243 {
5244         struct drm_i915_private *dev_priv = dev->dev_private;
5245         struct drm_encoder *encoder;
5246         bool dpd_is_edp = false;
5247
5248         if (IS_MOBILE(dev) && !IS_I830(dev))
5249                 intel_lvds_init(dev);
5250
5251         if (HAS_PCH_SPLIT(dev)) {
5252                 dpd_is_edp = intel_dpd_is_edp(dev);
5253
5254                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5255                         intel_dp_init(dev, DP_A);
5256
5257                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5258                         intel_dp_init(dev, PCH_DP_D);
5259         }
5260
5261         intel_crt_init(dev);
5262
5263         if (HAS_PCH_SPLIT(dev)) {
5264                 int found;
5265
5266                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5267                         /* PCH SDVOB multiplex with HDMIB */
5268                         found = intel_sdvo_init(dev, PCH_SDVOB);
5269                         if (!found)
5270                                 intel_hdmi_init(dev, HDMIB);
5271                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5272                                 intel_dp_init(dev, PCH_DP_B);
5273                 }
5274
5275                 if (I915_READ(HDMIC) & PORT_DETECTED)
5276                         intel_hdmi_init(dev, HDMIC);
5277
5278                 if (I915_READ(HDMID) & PORT_DETECTED)
5279                         intel_hdmi_init(dev, HDMID);
5280
5281                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5282                         intel_dp_init(dev, PCH_DP_C);
5283
5284                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5285                         intel_dp_init(dev, PCH_DP_D);
5286
5287         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5288                 bool found = false;
5289
5290                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5291                         DRM_DEBUG_KMS("probing SDVOB\n");
5292                         found = intel_sdvo_init(dev, SDVOB);
5293                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5294                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5295                                 intel_hdmi_init(dev, SDVOB);
5296                         }
5297
5298                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5299                                 DRM_DEBUG_KMS("probing DP_B\n");
5300                                 intel_dp_init(dev, DP_B);
5301                         }
5302                 }
5303
5304                 /* Before G4X SDVOC doesn't have its own detect register */
5305
5306                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5307                         DRM_DEBUG_KMS("probing SDVOC\n");
5308                         found = intel_sdvo_init(dev, SDVOC);
5309                 }
5310
5311                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5312
5313                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5314                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5315                                 intel_hdmi_init(dev, SDVOC);
5316                         }
5317                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5318                                 DRM_DEBUG_KMS("probing DP_C\n");
5319                                 intel_dp_init(dev, DP_C);
5320                         }
5321                 }
5322
5323                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5324                     (I915_READ(DP_D) & DP_DETECTED)) {
5325                         DRM_DEBUG_KMS("probing DP_D\n");
5326                         intel_dp_init(dev, DP_D);
5327                 }
5328         } else if (IS_GEN2(dev))
5329                 intel_dvo_init(dev);
5330
5331         if (SUPPORTS_TV(dev))
5332                 intel_tv_init(dev);
5333
5334         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5335                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5336
5337                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5338                 encoder->possible_clones = intel_encoder_clones(dev,
5339                                                 intel_encoder->clone_mask);
5340         }
5341 }
5342
5343 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5344 {
5345         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5346
5347         drm_framebuffer_cleanup(fb);
5348         drm_gem_object_unreference_unlocked(intel_fb->obj);
5349
5350         kfree(intel_fb);
5351 }
5352
5353 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5354                                                 struct drm_file *file_priv,
5355                                                 unsigned int *handle)
5356 {
5357         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5358         struct drm_gem_object *object = intel_fb->obj;
5359
5360         return drm_gem_handle_create(file_priv, object, handle);
5361 }
5362
5363 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5364         .destroy = intel_user_framebuffer_destroy,
5365         .create_handle = intel_user_framebuffer_create_handle,
5366 };
5367
5368 int intel_framebuffer_init(struct drm_device *dev,
5369                            struct intel_framebuffer *intel_fb,
5370                            struct drm_mode_fb_cmd *mode_cmd,
5371                            struct drm_gem_object *obj)
5372 {
5373         int ret;
5374
5375         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5376         if (ret) {
5377                 DRM_ERROR("framebuffer init failed %d\n", ret);
5378                 return ret;
5379         }
5380
5381         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5382         intel_fb->obj = obj;
5383         return 0;
5384 }
5385
5386 static struct drm_framebuffer *
5387 intel_user_framebuffer_create(struct drm_device *dev,
5388                               struct drm_file *filp,
5389                               struct drm_mode_fb_cmd *mode_cmd)
5390 {
5391         struct drm_gem_object *obj;
5392         struct intel_framebuffer *intel_fb;
5393         int ret;
5394
5395         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5396         if (!obj)
5397                 return ERR_PTR(-ENOENT);
5398
5399         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5400         if (!intel_fb)
5401                 return ERR_PTR(-ENOMEM);
5402
5403         ret = intel_framebuffer_init(dev, intel_fb,
5404                                      mode_cmd, obj);
5405         if (ret) {
5406                 drm_gem_object_unreference_unlocked(obj);
5407                 kfree(intel_fb);
5408                 return ERR_PTR(ret);
5409         }
5410
5411         return &intel_fb->base;
5412 }
5413
5414 static const struct drm_mode_config_funcs intel_mode_funcs = {
5415         .fb_create = intel_user_framebuffer_create,
5416         .output_poll_changed = intel_fb_output_poll_changed,
5417 };
5418
5419 static struct drm_gem_object *
5420 intel_alloc_context_page(struct drm_device *dev)
5421 {
5422         struct drm_gem_object *ctx;
5423         int ret;
5424
5425         ctx = i915_gem_alloc_object(dev, 4096);
5426         if (!ctx) {
5427                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5428                 return NULL;
5429         }
5430
5431         mutex_lock(&dev->struct_mutex);
5432         ret = i915_gem_object_pin(ctx, 4096);
5433         if (ret) {
5434                 DRM_ERROR("failed to pin power context: %d\n", ret);
5435                 goto err_unref;
5436         }
5437
5438         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5439         if (ret) {
5440                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5441                 goto err_unpin;
5442         }
5443         mutex_unlock(&dev->struct_mutex);
5444
5445         return ctx;
5446
5447 err_unpin:
5448         i915_gem_object_unpin(ctx);
5449 err_unref:
5450         drm_gem_object_unreference(ctx);
5451         mutex_unlock(&dev->struct_mutex);
5452         return NULL;
5453 }
5454
5455 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5456 {
5457         struct drm_i915_private *dev_priv = dev->dev_private;
5458         u16 rgvswctl;
5459
5460         rgvswctl = I915_READ16(MEMSWCTL);
5461         if (rgvswctl & MEMCTL_CMD_STS) {
5462                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5463                 return false; /* still busy with another command */
5464         }
5465
5466         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5467                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5468         I915_WRITE16(MEMSWCTL, rgvswctl);
5469         POSTING_READ16(MEMSWCTL);
5470
5471         rgvswctl |= MEMCTL_CMD_STS;
5472         I915_WRITE16(MEMSWCTL, rgvswctl);
5473
5474         return true;
5475 }
5476
5477 void ironlake_enable_drps(struct drm_device *dev)
5478 {
5479         struct drm_i915_private *dev_priv = dev->dev_private;
5480         u32 rgvmodectl = I915_READ(MEMMODECTL);
5481         u8 fmax, fmin, fstart, vstart;
5482
5483         /* 100ms RC evaluation intervals */
5484         I915_WRITE(RCUPEI, 100000);
5485         I915_WRITE(RCDNEI, 100000);
5486
5487         /* Set max/min thresholds to 90ms and 80ms respectively */
5488         I915_WRITE(RCBMAXAVG, 90000);
5489         I915_WRITE(RCBMINAVG, 80000);
5490
5491         I915_WRITE(MEMIHYST, 1);
5492
5493         /* Set up min, max, and cur for interrupt handling */
5494         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5495         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5496         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5497                 MEMMODE_FSTART_SHIFT;
5498         fstart = fmax;
5499
5500         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5501                 PXVFREQ_PX_SHIFT;
5502
5503         dev_priv->fmax = fstart; /* IPS callback will increase this */
5504         dev_priv->fstart = fstart;
5505
5506         dev_priv->max_delay = fmax;
5507         dev_priv->min_delay = fmin;
5508         dev_priv->cur_delay = fstart;
5509
5510         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5511                          fstart);
5512
5513         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5514
5515         /*
5516          * Interrupts will be enabled in ironlake_irq_postinstall
5517          */
5518
5519         I915_WRITE(VIDSTART, vstart);
5520         POSTING_READ(VIDSTART);
5521
5522         rgvmodectl |= MEMMODE_SWMODE_EN;
5523         I915_WRITE(MEMMODECTL, rgvmodectl);
5524
5525         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5526                 DRM_ERROR("stuck trying to change perf mode\n");
5527         msleep(1);
5528
5529         ironlake_set_drps(dev, fstart);
5530
5531         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5532                 I915_READ(0x112e0);
5533         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5534         dev_priv->last_count2 = I915_READ(0x112f4);
5535         getrawmonotonic(&dev_priv->last_time2);
5536 }
5537
5538 void ironlake_disable_drps(struct drm_device *dev)
5539 {
5540         struct drm_i915_private *dev_priv = dev->dev_private;
5541         u16 rgvswctl = I915_READ16(MEMSWCTL);
5542
5543         /* Ack interrupts, disable EFC interrupt */
5544         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5545         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5546         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5547         I915_WRITE(DEIIR, DE_PCU_EVENT);
5548         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5549
5550         /* Go back to the starting frequency */
5551         ironlake_set_drps(dev, dev_priv->fstart);
5552         msleep(1);
5553         rgvswctl |= MEMCTL_CMD_STS;
5554         I915_WRITE(MEMSWCTL, rgvswctl);
5555         msleep(1);
5556
5557 }
5558
5559 static unsigned long intel_pxfreq(u32 vidfreq)
5560 {
5561         unsigned long freq;
5562         int div = (vidfreq & 0x3f0000) >> 16;
5563         int post = (vidfreq & 0x3000) >> 12;
5564         int pre = (vidfreq & 0x7);
5565
5566         if (!pre)
5567                 return 0;
5568
5569         freq = ((div * 133333) / ((1<<post) * pre));
5570
5571         return freq;
5572 }
5573
5574 void intel_init_emon(struct drm_device *dev)
5575 {
5576         struct drm_i915_private *dev_priv = dev->dev_private;
5577         u32 lcfuse;
5578         u8 pxw[16];
5579         int i;
5580
5581         /* Disable to program */
5582         I915_WRITE(ECR, 0);
5583         POSTING_READ(ECR);
5584
5585         /* Program energy weights for various events */
5586         I915_WRITE(SDEW, 0x15040d00);
5587         I915_WRITE(CSIEW0, 0x007f0000);
5588         I915_WRITE(CSIEW1, 0x1e220004);
5589         I915_WRITE(CSIEW2, 0x04000004);
5590
5591         for (i = 0; i < 5; i++)
5592                 I915_WRITE(PEW + (i * 4), 0);
5593         for (i = 0; i < 3; i++)
5594                 I915_WRITE(DEW + (i * 4), 0);
5595
5596         /* Program P-state weights to account for frequency power adjustment */
5597         for (i = 0; i < 16; i++) {
5598                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5599                 unsigned long freq = intel_pxfreq(pxvidfreq);
5600                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5601                         PXVFREQ_PX_SHIFT;
5602                 unsigned long val;
5603
5604                 val = vid * vid;
5605                 val *= (freq / 1000);
5606                 val *= 255;
5607                 val /= (127*127*900);
5608                 if (val > 0xff)
5609                         DRM_ERROR("bad pxval: %ld\n", val);
5610                 pxw[i] = val;
5611         }
5612         /* Render standby states get 0 weight */
5613         pxw[14] = 0;
5614         pxw[15] = 0;
5615
5616         for (i = 0; i < 4; i++) {
5617                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5618                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5619                 I915_WRITE(PXW + (i * 4), val);
5620         }
5621
5622         /* Adjust magic regs to magic values (more experimental results) */
5623         I915_WRITE(OGW0, 0);
5624         I915_WRITE(OGW1, 0);
5625         I915_WRITE(EG0, 0x00007f00);
5626         I915_WRITE(EG1, 0x0000000e);
5627         I915_WRITE(EG2, 0x000e0000);
5628         I915_WRITE(EG3, 0x68000300);
5629         I915_WRITE(EG4, 0x42000000);
5630         I915_WRITE(EG5, 0x00140031);
5631         I915_WRITE(EG6, 0);
5632         I915_WRITE(EG7, 0);
5633
5634         for (i = 0; i < 8; i++)
5635                 I915_WRITE(PXWL + (i * 4), 0);
5636
5637         /* Enable PMON + select events */
5638         I915_WRITE(ECR, 0x80000019);
5639
5640         lcfuse = I915_READ(LCFUSE02);
5641
5642         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5643 }
5644
5645 void intel_init_clock_gating(struct drm_device *dev)
5646 {
5647         struct drm_i915_private *dev_priv = dev->dev_private;
5648
5649         /*
5650          * Disable clock gating reported to work incorrectly according to the
5651          * specs, but enable as much else as we can.
5652          */
5653         if (HAS_PCH_SPLIT(dev)) {
5654                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5655
5656                 if (IS_IRONLAKE(dev)) {
5657                         /* Required for FBC */
5658                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5659                         /* Required for CxSR */
5660                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5661
5662                         I915_WRITE(PCH_3DCGDIS0,
5663                                    MARIUNIT_CLOCK_GATE_DISABLE |
5664                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5665                 }
5666
5667                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5668
5669                 /*
5670                  * According to the spec the following bits should be set in
5671                  * order to enable memory self-refresh
5672                  * The bit 22/21 of 0x42004
5673                  * The bit 5 of 0x42020
5674                  * The bit 15 of 0x45000
5675                  */
5676                 if (IS_IRONLAKE(dev)) {
5677                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5678                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5679                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5680                         I915_WRITE(ILK_DSPCLK_GATE,
5681                                         (I915_READ(ILK_DSPCLK_GATE) |
5682                                                 ILK_DPARB_CLK_GATE));
5683                         I915_WRITE(DISP_ARB_CTL,
5684                                         (I915_READ(DISP_ARB_CTL) |
5685                                                 DISP_FBC_WM_DIS));
5686                 }
5687                 /*
5688                  * Based on the document from hardware guys the following bits
5689                  * should be set unconditionally in order to enable FBC.
5690                  * The bit 22 of 0x42000
5691                  * The bit 22 of 0x42004
5692                  * The bit 7,8,9 of 0x42020.
5693                  */
5694                 if (IS_IRONLAKE_M(dev)) {
5695                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5696                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5697                                    ILK_FBCQ_DIS);
5698                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5699                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5700                                    ILK_DPARB_GATE);
5701                         I915_WRITE(ILK_DSPCLK_GATE,
5702                                    I915_READ(ILK_DSPCLK_GATE) |
5703                                    ILK_DPFC_DIS1 |
5704                                    ILK_DPFC_DIS2 |
5705                                    ILK_CLK_FBC);
5706                 }
5707                 if (IS_GEN6(dev))
5708                         return;
5709         } else if (IS_G4X(dev)) {
5710                 uint32_t dspclk_gate;
5711                 I915_WRITE(RENCLK_GATE_D1, 0);
5712                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5713                        GS_UNIT_CLOCK_GATE_DISABLE |
5714                        CL_UNIT_CLOCK_GATE_DISABLE);
5715                 I915_WRITE(RAMCLK_GATE_D, 0);
5716                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5717                         OVRUNIT_CLOCK_GATE_DISABLE |
5718                         OVCUNIT_CLOCK_GATE_DISABLE;
5719                 if (IS_GM45(dev))
5720                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5721                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5722         } else if (IS_I965GM(dev)) {
5723                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5724                 I915_WRITE(RENCLK_GATE_D2, 0);
5725                 I915_WRITE(DSPCLK_GATE_D, 0);
5726                 I915_WRITE(RAMCLK_GATE_D, 0);
5727                 I915_WRITE16(DEUC, 0);
5728         } else if (IS_I965G(dev)) {
5729                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5730                        I965_RCC_CLOCK_GATE_DISABLE |
5731                        I965_RCPB_CLOCK_GATE_DISABLE |
5732                        I965_ISC_CLOCK_GATE_DISABLE |
5733                        I965_FBC_CLOCK_GATE_DISABLE);
5734                 I915_WRITE(RENCLK_GATE_D2, 0);
5735         } else if (IS_I9XX(dev)) {
5736                 u32 dstate = I915_READ(D_STATE);
5737
5738                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5739                         DSTATE_DOT_CLOCK_GATING;
5740                 I915_WRITE(D_STATE, dstate);
5741         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5742                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5743         } else if (IS_I830(dev)) {
5744                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5745         }
5746
5747         /*
5748          * GPU can automatically power down the render unit if given a page
5749          * to save state.
5750          */
5751         if (IS_IRONLAKE_M(dev)) {
5752                 if (dev_priv->renderctx == NULL)
5753                         dev_priv->renderctx = intel_alloc_context_page(dev);
5754                 if (dev_priv->renderctx) {
5755                         struct drm_i915_gem_object *obj_priv;
5756                         obj_priv = to_intel_bo(dev_priv->renderctx);
5757                         if (obj_priv) {
5758                                 BEGIN_LP_RING(4);
5759                                 OUT_RING(MI_SET_CONTEXT);
5760                                 OUT_RING(obj_priv->gtt_offset |
5761                                                 MI_MM_SPACE_GTT |
5762                                                 MI_SAVE_EXT_STATE_EN |
5763                                                 MI_RESTORE_EXT_STATE_EN |
5764                                                 MI_RESTORE_INHIBIT);
5765                                 OUT_RING(MI_NOOP);
5766                                 OUT_RING(MI_FLUSH);
5767                                 ADVANCE_LP_RING();
5768                         }
5769                 } else {
5770                         DRM_DEBUG_KMS("Failed to allocate render context."
5771                                       "Disable RC6\n");
5772                         return;
5773                 }
5774         }
5775
5776         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5777                 struct drm_i915_gem_object *obj_priv = NULL;
5778
5779                 if (dev_priv->pwrctx) {
5780                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5781                 } else {
5782                         struct drm_gem_object *pwrctx;
5783
5784                         pwrctx = intel_alloc_context_page(dev);
5785                         if (pwrctx) {
5786                                 dev_priv->pwrctx = pwrctx;
5787                                 obj_priv = to_intel_bo(pwrctx);
5788                         }
5789                 }
5790
5791                 if (obj_priv) {
5792                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5793                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5794                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5795                 }
5796         }
5797 }
5798
5799 /* Set up chip specific display functions */
5800 static void intel_init_display(struct drm_device *dev)
5801 {
5802         struct drm_i915_private *dev_priv = dev->dev_private;
5803
5804         /* We always want a DPMS function */
5805         if (HAS_PCH_SPLIT(dev))
5806                 dev_priv->display.dpms = ironlake_crtc_dpms;
5807         else
5808                 dev_priv->display.dpms = i9xx_crtc_dpms;
5809
5810         if (I915_HAS_FBC(dev)) {
5811                 if (IS_IRONLAKE_M(dev)) {
5812                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5813                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5814                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5815                 } else if (IS_GM45(dev)) {
5816                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5817                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5818                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5819                 } else if (IS_I965GM(dev)) {
5820                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5821                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5822                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5823                 }
5824                 /* 855GM needs testing */
5825         }
5826
5827         /* Returns the core display clock speed */
5828         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5829                 dev_priv->display.get_display_clock_speed =
5830                         i945_get_display_clock_speed;
5831         else if (IS_I915G(dev))
5832                 dev_priv->display.get_display_clock_speed =
5833                         i915_get_display_clock_speed;
5834         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5835                 dev_priv->display.get_display_clock_speed =
5836                         i9xx_misc_get_display_clock_speed;
5837         else if (IS_I915GM(dev))
5838                 dev_priv->display.get_display_clock_speed =
5839                         i915gm_get_display_clock_speed;
5840         else if (IS_I865G(dev))
5841                 dev_priv->display.get_display_clock_speed =
5842                         i865_get_display_clock_speed;
5843         else if (IS_I85X(dev))
5844                 dev_priv->display.get_display_clock_speed =
5845                         i855_get_display_clock_speed;
5846         else /* 852, 830 */
5847                 dev_priv->display.get_display_clock_speed =
5848                         i830_get_display_clock_speed;
5849
5850         /* For FIFO watermark updates */
5851         if (HAS_PCH_SPLIT(dev)) {
5852                 if (IS_IRONLAKE(dev)) {
5853                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5854                                 dev_priv->display.update_wm = ironlake_update_wm;
5855                         else {
5856                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5857                                               "Disable CxSR\n");
5858                                 dev_priv->display.update_wm = NULL;
5859                         }
5860                 } else
5861                         dev_priv->display.update_wm = NULL;
5862         } else if (IS_PINEVIEW(dev)) {
5863                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5864                                             dev_priv->is_ddr3,
5865                                             dev_priv->fsb_freq,
5866                                             dev_priv->mem_freq)) {
5867                         DRM_INFO("failed to find known CxSR latency "
5868                                  "(found ddr%s fsb freq %d, mem freq %d), "
5869                                  "disabling CxSR\n",
5870                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5871                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5872                         /* Disable CxSR and never update its watermark again */
5873                         pineview_disable_cxsr(dev);
5874                         dev_priv->display.update_wm = NULL;
5875                 } else
5876                         dev_priv->display.update_wm = pineview_update_wm;
5877         } else if (IS_G4X(dev))
5878                 dev_priv->display.update_wm = g4x_update_wm;
5879         else if (IS_I965G(dev))
5880                 dev_priv->display.update_wm = i965_update_wm;
5881         else if (IS_I9XX(dev)) {
5882                 dev_priv->display.update_wm = i9xx_update_wm;
5883                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5884         } else if (IS_I85X(dev)) {
5885                 dev_priv->display.update_wm = i9xx_update_wm;
5886                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5887         } else {
5888                 dev_priv->display.update_wm = i830_update_wm;
5889                 if (IS_845G(dev))
5890                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5891                 else
5892                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5893         }
5894 }
5895
5896 /*
5897  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5898  * resume, or other times.  This quirk makes sure that's the case for
5899  * affected systems.
5900  */
5901 static void quirk_pipea_force (struct drm_device *dev)
5902 {
5903         struct drm_i915_private *dev_priv = dev->dev_private;
5904
5905         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5906         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5907 }
5908
5909 struct intel_quirk {
5910         int device;
5911         int subsystem_vendor;
5912         int subsystem_device;
5913         void (*hook)(struct drm_device *dev);
5914 };
5915
5916 struct intel_quirk intel_quirks[] = {
5917         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5918         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5919         /* HP Mini needs pipe A force quirk (LP: #322104) */
5920         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5921
5922         /* Thinkpad R31 needs pipe A force quirk */
5923         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5924         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5925         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5926
5927         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5928         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5929         /* ThinkPad X40 needs pipe A force quirk */
5930
5931         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5932         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5933
5934         /* 855 & before need to leave pipe A & dpll A up */
5935         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5936         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5937 };
5938
5939 static void intel_init_quirks(struct drm_device *dev)
5940 {
5941         struct pci_dev *d = dev->pdev;
5942         int i;
5943
5944         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5945                 struct intel_quirk *q = &intel_quirks[i];
5946
5947                 if (d->device == q->device &&
5948                     (d->subsystem_vendor == q->subsystem_vendor ||
5949                      q->subsystem_vendor == PCI_ANY_ID) &&
5950                     (d->subsystem_device == q->subsystem_device ||
5951                      q->subsystem_device == PCI_ANY_ID))
5952                         q->hook(dev);
5953         }
5954 }
5955
5956 /* Disable the VGA plane that we never use */
5957 static void i915_disable_vga(struct drm_device *dev)
5958 {
5959         struct drm_i915_private *dev_priv = dev->dev_private;
5960         u8 sr1;
5961         u32 vga_reg;
5962
5963         if (HAS_PCH_SPLIT(dev))
5964                 vga_reg = CPU_VGACNTRL;
5965         else
5966                 vga_reg = VGACNTRL;
5967
5968         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5969         outb(1, VGA_SR_INDEX);
5970         sr1 = inb(VGA_SR_DATA);
5971         outb(sr1 | 1<<5, VGA_SR_DATA);
5972         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5973         udelay(300);
5974
5975         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5976         POSTING_READ(vga_reg);
5977 }
5978
5979 void intel_modeset_init(struct drm_device *dev)
5980 {
5981         struct drm_i915_private *dev_priv = dev->dev_private;
5982         int i;
5983
5984         drm_mode_config_init(dev);
5985
5986         dev->mode_config.min_width = 0;
5987         dev->mode_config.min_height = 0;
5988
5989         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5990
5991         intel_init_quirks(dev);
5992
5993         intel_init_display(dev);
5994
5995         if (IS_I965G(dev)) {
5996                 dev->mode_config.max_width = 8192;
5997                 dev->mode_config.max_height = 8192;
5998         } else if (IS_I9XX(dev)) {
5999                 dev->mode_config.max_width = 4096;
6000                 dev->mode_config.max_height = 4096;
6001         } else {
6002                 dev->mode_config.max_width = 2048;
6003                 dev->mode_config.max_height = 2048;
6004         }
6005
6006         /* set memory base */
6007         if (IS_I9XX(dev))
6008                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6009         else
6010                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6011
6012         if (IS_MOBILE(dev) || IS_I9XX(dev))
6013                 dev_priv->num_pipe = 2;
6014         else
6015                 dev_priv->num_pipe = 1;
6016         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6017                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6018
6019         for (i = 0; i < dev_priv->num_pipe; i++) {
6020                 intel_crtc_init(dev, i);
6021         }
6022
6023         intel_setup_outputs(dev);
6024
6025         intel_init_clock_gating(dev);
6026
6027         /* Just disable it once at startup */
6028         i915_disable_vga(dev);
6029
6030         if (IS_IRONLAKE_M(dev)) {
6031                 ironlake_enable_drps(dev);
6032                 intel_init_emon(dev);
6033         }
6034
6035         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6036         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6037                     (unsigned long)dev);
6038
6039         intel_setup_overlay(dev);
6040 }
6041
6042 void intel_modeset_cleanup(struct drm_device *dev)
6043 {
6044         struct drm_i915_private *dev_priv = dev->dev_private;
6045         struct drm_crtc *crtc;
6046         struct intel_crtc *intel_crtc;
6047
6048         mutex_lock(&dev->struct_mutex);
6049
6050         drm_kms_helper_poll_fini(dev);
6051         intel_fbdev_fini(dev);
6052
6053         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6054                 /* Skip inactive CRTCs */
6055                 if (!crtc->fb)
6056                         continue;
6057
6058                 intel_crtc = to_intel_crtc(crtc);
6059                 intel_increase_pllclock(crtc, false);
6060                 del_timer_sync(&intel_crtc->idle_timer);
6061         }
6062
6063         del_timer_sync(&dev_priv->idle_timer);
6064
6065         if (dev_priv->display.disable_fbc)
6066                 dev_priv->display.disable_fbc(dev);
6067
6068         if (dev_priv->renderctx) {
6069                 struct drm_i915_gem_object *obj_priv;
6070
6071                 obj_priv = to_intel_bo(dev_priv->renderctx);
6072                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6073                 I915_READ(CCID);
6074                 i915_gem_object_unpin(dev_priv->renderctx);
6075                 drm_gem_object_unreference(dev_priv->renderctx);
6076         }
6077
6078         if (dev_priv->pwrctx) {
6079                 struct drm_i915_gem_object *obj_priv;
6080
6081                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6082                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6083                 I915_READ(PWRCTXA);
6084                 i915_gem_object_unpin(dev_priv->pwrctx);
6085                 drm_gem_object_unreference(dev_priv->pwrctx);
6086         }
6087
6088         if (IS_IRONLAKE_M(dev))
6089                 ironlake_disable_drps(dev);
6090
6091         mutex_unlock(&dev->struct_mutex);
6092
6093         drm_mode_config_cleanup(dev);
6094 }
6095
6096
6097 /*
6098  * Return which encoder is currently attached for connector.
6099  */
6100 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6101 {
6102         struct drm_mode_object *obj;
6103         struct drm_encoder *encoder;
6104         int i;
6105
6106         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6107                 if (connector->encoder_ids[i] == 0)
6108                         break;
6109
6110                 obj = drm_mode_object_find(connector->dev,
6111                                            connector->encoder_ids[i],
6112                                            DRM_MODE_OBJECT_ENCODER);
6113                 if (!obj)
6114                         continue;
6115
6116                 encoder = obj_to_encoder(obj);
6117                 return encoder;
6118         }
6119         return NULL;
6120 }
6121
6122 /*
6123  * set vga decode state - true == enable VGA decode
6124  */
6125 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6126 {
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128         u16 gmch_ctrl;
6129
6130         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6131         if (state)
6132                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6133         else
6134                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6135         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6136         return 0;
6137 }