drivers/gpu/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include "intel_drv.h"
  29 #include "i915_drv.h"
  30
  31 static const struct {
  32         int clock;
  33         u32 config;
  34 } hdmi_audio_clock[] = {
  35         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  36         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  37         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  38         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  39         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  40         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  41         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  42         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  43         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  44         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
  45 };
  46
  47 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
  48 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
  49 {
  50         int i;
  51
  52         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
  53                 if (mode->clock == hdmi_audio_clock[i].clock)
  54                         break;
  55         }
  56
  57         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
  58                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
  59                 i = 1;
  60         }
  61
  62         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
  63                       hdmi_audio_clock[i].clock,
  64                       hdmi_audio_clock[i].config);
  65
  66         return hdmi_audio_clock[i].config;
  67 }
  68
  69 static bool intel_eld_uptodate(struct drm_connector *connector,
  70                                int reg_eldv, uint32_t bits_eldv,
  71                                int reg_elda, uint32_t bits_elda,
  72                                int reg_edid)
  73 {
  74         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  75         uint8_t *eld = connector->eld;
  76         uint32_t tmp;
  77         int i;
  78
  79         tmp = I915_READ(reg_eldv);
  80         tmp &= bits_eldv;
  81
  82         if (!eld[0])
  83                 return !tmp;
  84
  85         if (!tmp)
  86                 return false;
  87
  88         tmp = I915_READ(reg_elda);
  89         tmp &= ~bits_elda;
  90         I915_WRITE(reg_elda, tmp);
  91
  92         for (i = 0; i < eld[2]; i++)
  93                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  94                         return false;
  95
  96         return true;
  97 }
  98
  99 static void g4x_audio_codec_enable(struct drm_connector *connector,
 100                                    struct intel_encoder *encoder,
 101                                    struct drm_display_mode *mode)
 102 {
 103         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 104         uint8_t *eld = connector->eld;
 105         uint32_t eldv;
 106         uint32_t tmp;
 107         int len, i;
 108
 109         tmp = I915_READ(G4X_AUD_VID_DID);
 110         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 111                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 112         else
 113                 eldv = G4X_ELDV_DEVCTG;
 114
 115         if (intel_eld_uptodate(connector,
 116                                G4X_AUD_CNTL_ST, eldv,
 117                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
 118                                G4X_HDMIW_HDMIEDID))
 119                 return;
 120
 121         tmp = I915_READ(G4X_AUD_CNTL_ST);
 122         tmp &= ~(eldv | G4X_ELD_ADDR);
 123         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 124         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 125
 126         if (!eld[0])
 127                 return;
 128
 129         len = min_t(int, eld[2], len);
 130         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 131         for (i = 0; i < len; i++)
 132                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 133
 134         tmp = I915_READ(G4X_AUD_CNTL_ST);
 135         tmp |= eldv;
 136         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 137 }
 138
 139 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
 140 {
 141         struct drm_device *dev = encoder->base.dev;
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         struct drm_crtc *crtc = encoder->base.crtc;
 144         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 145         uint32_t tmp;
 146
 147         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 148         tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
 149         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 150 }
 151
 152 static void hsw_audio_codec_enable(struct drm_connector *connector,
 153                                    struct intel_encoder *encoder,
 154                                    struct drm_display_mode *mode)
 155 {
 156         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 157         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 158         uint8_t *eld = connector->eld;
 159         uint32_t eldv;
 160         uint32_t tmp;
 161         int len, i;
 162         enum pipe pipe = intel_crtc->pipe;
 163         enum port port;
 164         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
 165         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
 166         int aud_config = HSW_AUD_CFG(pipe);
 167         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
 168
 169         /* Audio output enable */
 170         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
 171         tmp = I915_READ(aud_cntrl_st2);
 172         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
 173         I915_WRITE(aud_cntrl_st2, tmp);
 174         POSTING_READ(aud_cntrl_st2);
 175
 176         /* Set ELD valid state */
 177         tmp = I915_READ(aud_cntrl_st2);
 178         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
 179         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
 180         I915_WRITE(aud_cntrl_st2, tmp);
 181         tmp = I915_READ(aud_cntrl_st2);
 182         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
 183
 184         /* Enable HDMI mode */
 185         tmp = I915_READ(aud_config);
 186         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
 187         /* clear N_programing_enable and N_value_index */
 188         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
 189         I915_WRITE(aud_config, tmp);
 190
 191         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 192
 193         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
 194
 195         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 196                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
 197         else
 198                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
 199
 200         if (intel_eld_uptodate(connector,
 201                                aud_cntrl_st2, eldv,
 202                                aud_cntl_st, IBX_ELD_ADDRESS,
 203                                hdmiw_hdmiedid))
 204                 return;
 205
 206         tmp = I915_READ(aud_cntrl_st2);
 207         tmp &= ~eldv;
 208         I915_WRITE(aud_cntrl_st2, tmp);
 209
 210         if (!eld[0])
 211                 return;
 212
 213         tmp = I915_READ(aud_cntl_st);
 214         tmp &= ~IBX_ELD_ADDRESS;
 215         I915_WRITE(aud_cntl_st, tmp);
 216         port = (tmp >> 29) & DIP_PORT_SEL_MASK;         /* DIP_Port_Select, 0x1 = PortB */
 217         DRM_DEBUG_DRIVER("port num:%d\n", port);
 218
 219         len = min_t(int, eld[2], 21);   /* 84 bytes of hw ELD buffer */
 220         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 221         for (i = 0; i < len; i++)
 222                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 223
 224         tmp = I915_READ(aud_cntrl_st2);
 225         tmp |= eldv;
 226         I915_WRITE(aud_cntrl_st2, tmp);
 227
 228         /* XXX: Transitional */
 229         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 230         tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
 231         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 232 }
 233
 234 static void ilk_audio_codec_enable(struct drm_connector *connector,
 235                                    struct intel_encoder *encoder,
 236                                    struct drm_display_mode *mode)
 237 {
 238         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 239         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 240         uint8_t *eld = connector->eld;
 241         uint32_t eldv;
 242         uint32_t tmp;
 243         int len, i;
 244         int hdmiw_hdmiedid;
 245         int aud_config;
 246         int aud_cntl_st;
 247         int aud_cntrl_st2;
 248         enum pipe pipe = intel_crtc->pipe;
 249         enum port port;
 250
 251         if (HAS_PCH_IBX(connector->dev)) {
 252                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 253                 aud_config = IBX_AUD_CFG(pipe);
 254                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 255                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 256         } else if (IS_VALLEYVIEW(connector->dev)) {
 257                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 258                 aud_config = VLV_AUD_CFG(pipe);
 259                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 260                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 261         } else {
 262                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 263                 aud_config = CPT_AUD_CFG(pipe);
 264                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 265                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 266         }
 267
 268         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 269
 270         if (IS_VALLEYVIEW(connector->dev))  {
 271                 struct intel_digital_port *intel_dig_port;
 272
 273                 intel_dig_port = enc_to_dig_port(&encoder->base);
 274                 port = intel_dig_port->port;
 275         } else {
 276                 tmp = I915_READ(aud_cntl_st);
 277                 port = (tmp >> 29) & DIP_PORT_SEL_MASK;
 278                 /* DIP_Port_Select, 0x1 = PortB */
 279         }
 280
 281         if (!port) {
 282                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
 283                 /* operate blindly on all ports */
 284                 eldv = IBX_ELD_VALIDB;
 285                 eldv |= IBX_ELD_VALIDB << 4;
 286                 eldv |= IBX_ELD_VALIDB << 8;
 287         } else {
 288                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(port));
 289                 eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
 290         }
 291
 292         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 293                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
 294         else
 295                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
 296
 297         if (intel_eld_uptodate(connector,
 298                                aud_cntrl_st2, eldv,
 299                                aud_cntl_st, IBX_ELD_ADDRESS,
 300                                hdmiw_hdmiedid))
 301                 return;
 302
 303         tmp = I915_READ(aud_cntrl_st2);
 304         tmp &= ~eldv;
 305         I915_WRITE(aud_cntrl_st2, tmp);
 306
 307         if (!eld[0])
 308                 return;
 309
 310         tmp = I915_READ(aud_cntl_st);
 311         tmp &= ~IBX_ELD_ADDRESS;
 312         I915_WRITE(aud_cntl_st, tmp);
 313
 314         len = min_t(int, eld[2], 21);   /* 84 bytes of hw ELD buffer */
 315         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 316         for (i = 0; i < len; i++)
 317                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 318
 319         tmp = I915_READ(aud_cntrl_st2);
 320         tmp |= eldv;
 321         I915_WRITE(aud_cntrl_st2, tmp);
 322 }
 323
 324 /**
 325  * intel_audio_codec_enable - Enable the audio codec for HD audio
 326  * @intel_encoder: encoder on which to enable audio
 327  *
 328  * The enable sequences may only be performed after enabling the transcoder and
 329  * port, and after completed link training.
 330  */
 331 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 332 {
 333         struct drm_encoder *encoder = &intel_encoder->base;
 334         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 335         struct drm_display_mode *mode = &crtc->config.adjusted_mode;
 336         struct drm_connector *connector;
 337         struct drm_device *dev = encoder->dev;
 338         struct drm_i915_private *dev_priv = dev->dev_private;
 339
 340         connector = drm_select_eld(encoder, mode);
 341         if (!connector)
 342                 return;
 343
 344         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 345                          connector->base.id,
 346                          connector->name,
 347                          connector->encoder->base.id,
 348                          connector->encoder->name);
 349
 350         /* ELD Conn_Type */
 351         connector->eld[5] &= ~(3 << 2);
 352         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 353                 connector->eld[5] |= (1 << 2);
 354
 355         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
 356
 357         if (dev_priv->display.audio_codec_enable)
 358                 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
 359 }
 360
 361 /**
 362  * intel_audio_codec_disable - Disable the audio codec for HD audio
 363  * @encoder: encoder on which to disable audio
 364  *
 365  * The disable sequences must be performed before disabling the transcoder or
 366  * port.
 367  */
 368 void intel_audio_codec_disable(struct intel_encoder *encoder)
 369 {
 370         struct drm_device *dev = encoder->base.dev;
 371         struct drm_i915_private *dev_priv = dev->dev_private;
 372
 373         if (dev_priv->display.audio_codec_disable)
 374                 dev_priv->display.audio_codec_disable(encoder);
 375 }
 376
 377 /**
 378  * intel_init_audio - Set up chip specific audio functions
 379  * @dev: drm device
 380  */
 381 void intel_init_audio(struct drm_device *dev)
 382 {
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384
 385         if (IS_G4X(dev)) {
 386                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 387         } else if (IS_VALLEYVIEW(dev)) {
 388                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 389         } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
 390                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 391                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 392         } else if (HAS_PCH_SPLIT(dev)) {
 393                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 394         }
 395 }