drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #define MAX_NOPID ((u32)~0)
  38
  39 /**
  40  * Interrupts that are always left unmasked.
  41  *
  42  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  43  * we leave them always unmasked in IMR and then control enabling them through
  44  * PIPESTAT alone.
  45  */
  46 #define I915_INTERRUPT_ENABLE_FIX                       \
  47         (I915_ASLE_INTERRUPT |                          \
  48          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  49          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  51          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  52          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  53
  54 /** Interrupts that we mask and unmask at runtime. */
  55 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  56
  57 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  58                                  PIPE_VBLANK_INTERRUPT_STATUS)
  59
  60 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  61                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  62
  63 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  64                                          DRM_I915_VBLANK_PIPE_B)
  65
  66 void
  67 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  68 {
  69         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  70                 dev_priv->gt_irq_mask_reg &= ~mask;
  71                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  72                 (void) I915_READ(GTIMR);
  73         }
  74 }
  75
  76 static inline void
  77 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  78 {
  79         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  80                 dev_priv->gt_irq_mask_reg |= mask;
  81                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  82                 (void) I915_READ(GTIMR);
  83         }
  84 }
  85
  86 /* For display hotplug interrupt */
  87 void
  88 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  89 {
  90         if ((dev_priv->irq_mask_reg & mask) != 0) {
  91                 dev_priv->irq_mask_reg &= ~mask;
  92                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  93                 (void) I915_READ(DEIMR);
  94         }
  95 }
  96
  97 static inline void
  98 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  99 {
 100         if ((dev_priv->irq_mask_reg & mask) != mask) {
 101                 dev_priv->irq_mask_reg |= mask;
 102                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 103                 (void) I915_READ(DEIMR);
 104         }
 105 }
 106
 107 void
 108 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 109 {
 110         if ((dev_priv->irq_mask_reg & mask) != 0) {
 111                 dev_priv->irq_mask_reg &= ~mask;
 112                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 113                 (void) I915_READ(IMR);
 114         }
 115 }
 116
 117 static inline void
 118 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 119 {
 120         if ((dev_priv->irq_mask_reg & mask) != mask) {
 121                 dev_priv->irq_mask_reg |= mask;
 122                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 123                 (void) I915_READ(IMR);
 124         }
 125 }
 126
 127 static inline u32
 128 i915_pipestat(int pipe)
 129 {
 130         if (pipe == 0)
 131                 return PIPEASTAT;
 132         if (pipe == 1)
 133                 return PIPEBSTAT;
 134         BUG();
 135 }
 136
 137 void
 138 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 139 {
 140         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 141                 u32 reg = i915_pipestat(pipe);
 142
 143                 dev_priv->pipestat[pipe] |= mask;
 144                 /* Enable the interrupt, clear any pending status */
 145                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 146                 (void) I915_READ(reg);
 147         }
 148 }
 149
 150 void
 151 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 152 {
 153         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 154                 u32 reg = i915_pipestat(pipe);
 155
 156                 dev_priv->pipestat[pipe] &= ~mask;
 157                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 158                 (void) I915_READ(reg);
 159         }
 160 }
 161
 162 /**
 163  * intel_enable_asle - enable ASLE interrupt for OpRegion
 164  */
 165 void intel_enable_asle (struct drm_device *dev)
 166 {
 167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 168
 169         if (IS_IRONLAKE(dev))
 170                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 171         else
 172                 i915_enable_pipestat(dev_priv, 1,
 173                                      I915_LEGACY_BLC_EVENT_ENABLE);
 174 }
 175
 176 /**
 177  * i915_pipe_enabled - check if a pipe is enabled
 178  * @dev: DRM device
 179  * @pipe: pipe to check
 180  *
 181  * Reading certain registers when the pipe is disabled can hang the chip.
 182  * Use this routine to make sure the PLL is running and the pipe is active
 183  * before reading such registers if unsure.
 184  */
 185 static int
 186 i915_pipe_enabled(struct drm_device *dev, int pipe)
 187 {
 188         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 189         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 190
 191         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 192                 return 1;
 193
 194         return 0;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low, count;
 206
 207         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 208         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 212                                 "pipe %d\n", pipe);
 213                 return 0;
 214         }
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 223                          PIPE_FRAME_HIGH_SHIFT);
 224                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 225                         PIPE_FRAME_LOW_SHIFT);
 226                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 227                          PIPE_FRAME_HIGH_SHIFT);
 228         } while (high1 != high2);
 229
 230         count = (high1 << 8) | low;
 231
 232         return count;
 233 }
 234
 235 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 236 {
 237         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 238         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 239
 240         if (!i915_pipe_enabled(dev, pipe)) {
 241                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 242                                         "pipe %d\n", pipe);
 243                 return 0;
 244         }
 245
 246         return I915_READ(reg);
 247 }
 248
 249 /*
 250  * Handle hotplug events outside the interrupt handler proper.
 251  */
 252 static void i915_hotplug_work_func(struct work_struct *work)
 253 {
 254         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 255                                                     hotplug_work);
 256         struct drm_device *dev = dev_priv->dev;
 257         struct drm_mode_config *mode_config = &dev->mode_config;
 258         struct drm_connector *connector;
 259
 260         if (mode_config->num_connector) {
 261                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 262                         struct intel_output *intel_output = to_intel_output(connector);
 263
 264                         if (intel_output->hot_plug)
 265                                 (*intel_output->hot_plug) (intel_output);
 266                 }
 267         }
 268         /* Just fire off a uevent and let userspace tell us what to do */
 269         drm_sysfs_hotplug_event(dev);
 270 }
 271
 272 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 273 {
 274         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 275         int ret = IRQ_NONE;
 276         u32 de_iir, gt_iir, de_ier, pch_iir;
 277         struct drm_i915_master_private *master_priv;
 278
 279         /* disable master interrupt before clearing iir  */
 280         de_ier = I915_READ(DEIER);
 281         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 282         (void)I915_READ(DEIER);
 283
 284         de_iir = I915_READ(DEIIR);
 285         gt_iir = I915_READ(GTIIR);
 286         pch_iir = I915_READ(SDEIIR);
 287
 288         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 289                 goto done;
 290
 291         ret = IRQ_HANDLED;
 292
 293         if (dev->primary->master) {
 294                 master_priv = dev->primary->master->driver_priv;
 295                 if (master_priv->sarea_priv)
 296                         master_priv->sarea_priv->last_dispatch =
 297                                 READ_BREADCRUMB(dev_priv);
 298         }
 299
 300         if (gt_iir & GT_USER_INTERRUPT) {
 301                 u32 seqno = i915_get_gem_seqno(dev);
 302                 dev_priv->mm.irq_gem_seqno = seqno;
 303                 trace_i915_gem_request_complete(dev, seqno);
 304                 DRM_WAKEUP(&dev_priv->irq_queue);
 305                 dev_priv->hangcheck_count = 0;
 306                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 307         }
 308
 309         if (de_iir & DE_GSE)
 310                 ironlake_opregion_gse_intr(dev);
 311
 312         if (de_iir & DE_PLANEA_FLIP_DONE) {
 313                 intel_prepare_page_flip(dev, 0);
 314                 intel_finish_page_flip(dev, 0);
 315         }
 316
 317         if (de_iir & DE_PLANEB_FLIP_DONE) {
 318                 intel_prepare_page_flip(dev, 1);
 319                 intel_finish_page_flip(dev, 1);
 320         }
 321
 322         if (de_iir & DE_PIPEA_VBLANK)
 323                 drm_handle_vblank(dev, 0);
 324
 325         if (de_iir & DE_PIPEB_VBLANK)
 326                 drm_handle_vblank(dev, 1);
 327
 328         /* check event from PCH */
 329         if ((de_iir & DE_PCH_EVENT) &&
 330             (pch_iir & SDE_HOTPLUG_MASK)) {
 331                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 332         }
 333
 334         /* should clear PCH hotplug event before clear CPU irq */
 335         I915_WRITE(SDEIIR, pch_iir);
 336         I915_WRITE(GTIIR, gt_iir);
 337         I915_WRITE(DEIIR, de_iir);
 338
 339 done:
 340         I915_WRITE(DEIER, de_ier);
 341         (void)I915_READ(DEIER);
 342
 343         return ret;
 344 }
 345
 346 /**
 347  * i915_error_work_func - do process context error handling work
 348  * @work: work struct
 349  *
 350  * Fire an error uevent so userspace can see that a hang or error
 351  * was detected.
 352  */
 353 static void i915_error_work_func(struct work_struct *work)
 354 {
 355         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 356                                                     error_work);
 357         struct drm_device *dev = dev_priv->dev;
 358         char *error_event[] = { "ERROR=1", NULL };
 359         char *reset_event[] = { "RESET=1", NULL };
 360         char *reset_done_event[] = { "ERROR=0", NULL };
 361
 362         DRM_DEBUG_DRIVER("generating error event\n");
 363         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 364
 365         if (atomic_read(&dev_priv->mm.wedged)) {
 366                 if (IS_I965G(dev)) {
 367                         DRM_DEBUG_DRIVER("resetting chip\n");
 368                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 369                         if (!i965_reset(dev, GDRST_RENDER)) {
 370                                 atomic_set(&dev_priv->mm.wedged, 0);
 371                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 372                         }
 373                 } else {
 374                         DRM_DEBUG_DRIVER("reboot required\n");
 375                 }
 376         }
 377 }
 378
 379 /**
 380  * i915_capture_error_state - capture an error record for later analysis
 381  * @dev: drm device
 382  *
 383  * Should be called when an error is detected (either a hang or an error
 384  * interrupt) to capture error state from the time of the error.  Fills
 385  * out a structure which becomes available in debugfs for user level tools
 386  * to pick up.
 387  */
 388 static void i915_capture_error_state(struct drm_device *dev)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         struct drm_i915_error_state *error;
 392         unsigned long flags;
 393
 394         spin_lock_irqsave(&dev_priv->error_lock, flags);
 395         if (dev_priv->first_error)
 396                 goto out;
 397
 398         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 399         if (!error) {
 400                 DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
 401                 goto out;
 402         }
 403
 404         error->eir = I915_READ(EIR);
 405         error->pgtbl_er = I915_READ(PGTBL_ER);
 406         error->pipeastat = I915_READ(PIPEASTAT);
 407         error->pipebstat = I915_READ(PIPEBSTAT);
 408         error->instpm = I915_READ(INSTPM);
 409         if (!IS_I965G(dev)) {
 410                 error->ipeir = I915_READ(IPEIR);
 411                 error->ipehr = I915_READ(IPEHR);
 412                 error->instdone = I915_READ(INSTDONE);
 413                 error->acthd = I915_READ(ACTHD);
 414         } else {
 415                 error->ipeir = I915_READ(IPEIR_I965);
 416                 error->ipehr = I915_READ(IPEHR_I965);
 417                 error->instdone = I915_READ(INSTDONE_I965);
 418                 error->instps = I915_READ(INSTPS);
 419                 error->instdone1 = I915_READ(INSTDONE1);
 420                 error->acthd = I915_READ(ACTHD_I965);
 421         }
 422
 423         do_gettimeofday(&error->time);
 424
 425         dev_priv->first_error = error;
 426
 427 out:
 428         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 429 }
 430
 431 /**
 432  * i915_handle_error - handle an error interrupt
 433  * @dev: drm device
 434  *
 435  * Do some basic checking of regsiter state at error interrupt time and
 436  * dump it to the syslog.  Also call i915_capture_error_state() to make
 437  * sure we get a record and make it available in debugfs.  Fire a uevent
 438  * so userspace knows something bad happened (should trigger collection
 439  * of a ring dump etc.).
 440  */
 441 static void i915_handle_error(struct drm_device *dev, bool wedged)
 442 {
 443         struct drm_i915_private *dev_priv = dev->dev_private;
 444         u32 eir = I915_READ(EIR);
 445         u32 pipea_stats = I915_READ(PIPEASTAT);
 446         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 447
 448         i915_capture_error_state(dev);
 449
 450         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 451                eir);
 452
 453         if (IS_G4X(dev)) {
 454                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 455                         u32 ipeir = I915_READ(IPEIR_I965);
 456
 457                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 458                                I915_READ(IPEIR_I965));
 459                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 460                                I915_READ(IPEHR_I965));
 461                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 462                                I915_READ(INSTDONE_I965));
 463                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 464                                I915_READ(INSTPS));
 465                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 466                                I915_READ(INSTDONE1));
 467                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 468                                I915_READ(ACTHD_I965));
 469                         I915_WRITE(IPEIR_I965, ipeir);
 470                         (void)I915_READ(IPEIR_I965);
 471                 }
 472                 if (eir & GM45_ERROR_PAGE_TABLE) {
 473                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 474                         printk(KERN_ERR "page table error\n");
 475                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 476                                pgtbl_err);
 477                         I915_WRITE(PGTBL_ER, pgtbl_err);
 478                         (void)I915_READ(PGTBL_ER);
 479                 }
 480         }
 481
 482         if (IS_I9XX(dev)) {
 483                 if (eir & I915_ERROR_PAGE_TABLE) {
 484                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 485                         printk(KERN_ERR "page table error\n");
 486                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 487                                pgtbl_err);
 488                         I915_WRITE(PGTBL_ER, pgtbl_err);
 489                         (void)I915_READ(PGTBL_ER);
 490                 }
 491         }
 492
 493         if (eir & I915_ERROR_MEMORY_REFRESH) {
 494                 printk(KERN_ERR "memory refresh error\n");
 495                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 496                        pipea_stats);
 497                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 498                        pipeb_stats);
 499                 /* pipestat has already been acked */
 500         }
 501         if (eir & I915_ERROR_INSTRUCTION) {
 502                 printk(KERN_ERR "instruction error\n");
 503                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 504                        I915_READ(INSTPM));
 505                 if (!IS_I965G(dev)) {
 506                         u32 ipeir = I915_READ(IPEIR);
 507
 508                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 509                                I915_READ(IPEIR));
 510                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 511                                I915_READ(IPEHR));
 512                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 513                                I915_READ(INSTDONE));
 514                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 515                                I915_READ(ACTHD));
 516                         I915_WRITE(IPEIR, ipeir);
 517                         (void)I915_READ(IPEIR);
 518                 } else {
 519                         u32 ipeir = I915_READ(IPEIR_I965);
 520
 521                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 522                                I915_READ(IPEIR_I965));
 523                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 524                                I915_READ(IPEHR_I965));
 525                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 526                                I915_READ(INSTDONE_I965));
 527                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 528                                I915_READ(INSTPS));
 529                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 530                                I915_READ(INSTDONE1));
 531                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 532                                I915_READ(ACTHD_I965));
 533                         I915_WRITE(IPEIR_I965, ipeir);
 534                         (void)I915_READ(IPEIR_I965);
 535                 }
 536         }
 537
 538         I915_WRITE(EIR, eir);
 539         (void)I915_READ(EIR);
 540         eir = I915_READ(EIR);
 541         if (eir) {
 542                 /*
 543                  * some errors might have become stuck,
 544                  * mask them.
 545                  */
 546                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 547                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 548                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 549         }
 550
 551         if (wedged) {
 552                 atomic_set(&dev_priv->mm.wedged, 1);
 553
 554                 /*
 555                  * Wakeup waiting processes so they don't hang
 556                  */
 557                 DRM_WAKEUP(&dev_priv->irq_queue);
 558         }
 559
 560         queue_work(dev_priv->wq, &dev_priv->error_work);
 561 }
 562
 563 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 564 {
 565         struct drm_device *dev = (struct drm_device *) arg;
 566         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 567         struct drm_i915_master_private *master_priv;
 568         u32 iir, new_iir;
 569         u32 pipea_stats, pipeb_stats;
 570         u32 vblank_status;
 571         u32 vblank_enable;
 572         int vblank = 0;
 573         unsigned long irqflags;
 574         int irq_received;
 575         int ret = IRQ_NONE;
 576
 577         atomic_inc(&dev_priv->irq_received);
 578
 579         if (IS_IRONLAKE(dev))
 580                 return ironlake_irq_handler(dev);
 581
 582         iir = I915_READ(IIR);
 583
 584         if (IS_I965G(dev)) {
 585                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 586                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 587         } else {
 588                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 589                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 590         }
 591
 592         for (;;) {
 593                 irq_received = iir != 0;
 594
 595                 /* Can't rely on pipestat interrupt bit in iir as it might
 596                  * have been cleared after the pipestat interrupt was received.
 597                  * It doesn't set the bit in iir again, but it still produces
 598                  * interrupts (for non-MSI).
 599                  */
 600                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 601                 pipea_stats = I915_READ(PIPEASTAT);
 602                 pipeb_stats = I915_READ(PIPEBSTAT);
 603
 604                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 605                         i915_handle_error(dev, false);
 606
 607                 /*
 608                  * Clear the PIPE(A|B)STAT regs before the IIR
 609                  */
 610                 if (pipea_stats & 0x8000ffff) {
 611                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 612                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 613                         I915_WRITE(PIPEASTAT, pipea_stats);
 614                         irq_received = 1;
 615                 }
 616
 617                 if (pipeb_stats & 0x8000ffff) {
 618                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 619                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 620                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 621                         irq_received = 1;
 622                 }
 623                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 624
 625                 if (!irq_received)
 626                         break;
 627
 628                 ret = IRQ_HANDLED;
 629
 630                 /* Consume port.  Then clear IIR or we'll miss events */
 631                 if ((I915_HAS_HOTPLUG(dev)) &&
 632                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 633                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 634
 635                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 636                                   hotplug_status);
 637                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 638                                 queue_work(dev_priv->wq,
 639                                            &dev_priv->hotplug_work);
 640
 641                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 642                         I915_READ(PORT_HOTPLUG_STAT);
 643                 }
 644
 645                 I915_WRITE(IIR, iir);
 646                 new_iir = I915_READ(IIR); /* Flush posted writes */
 647
 648                 if (dev->primary->master) {
 649                         master_priv = dev->primary->master->driver_priv;
 650                         if (master_priv->sarea_priv)
 651                                 master_priv->sarea_priv->last_dispatch =
 652                                         READ_BREADCRUMB(dev_priv);
 653                 }
 654
 655                 if (iir & I915_USER_INTERRUPT) {
 656                         u32 seqno = i915_get_gem_seqno(dev);
 657                         dev_priv->mm.irq_gem_seqno = seqno;
 658                         trace_i915_gem_request_complete(dev, seqno);
 659                         DRM_WAKEUP(&dev_priv->irq_queue);
 660                         dev_priv->hangcheck_count = 0;
 661                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 662                 }
 663
 664                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 665                         intel_prepare_page_flip(dev, 0);
 666
 667                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 668                         intel_prepare_page_flip(dev, 1);
 669
 670                 if (pipea_stats & vblank_status) {
 671                         vblank++;
 672                         drm_handle_vblank(dev, 0);
 673                         intel_finish_page_flip(dev, 0);
 674                 }
 675
 676                 if (pipeb_stats & vblank_status) {
 677                         vblank++;
 678                         drm_handle_vblank(dev, 1);
 679                         intel_finish_page_flip(dev, 1);
 680                 }
 681
 682                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 683                     (iir & I915_ASLE_INTERRUPT))
 684                         opregion_asle_intr(dev);
 685
 686                 /* With MSI, interrupts are only generated when iir
 687                  * transitions from zero to nonzero.  If another bit got
 688                  * set while we were handling the existing iir bits, then
 689                  * we would never get another interrupt.
 690                  *
 691                  * This is fine on non-MSI as well, as if we hit this path
 692                  * we avoid exiting the interrupt handler only to generate
 693                  * another one.
 694                  *
 695                  * Note that for MSI this could cause a stray interrupt report
 696                  * if an interrupt landed in the time between writing IIR and
 697                  * the posting read.  This should be rare enough to never
 698                  * trigger the 99% of 100,000 interrupts test for disabling
 699                  * stray interrupts.
 700                  */
 701                 iir = new_iir;
 702         }
 703
 704         return ret;
 705 }
 706
 707 static int i915_emit_irq(struct drm_device * dev)
 708 {
 709         drm_i915_private_t *dev_priv = dev->dev_private;
 710         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 711         RING_LOCALS;
 712
 713         i915_kernel_lost_context(dev);
 714
 715         DRM_DEBUG_DRIVER("\n");
 716
 717         dev_priv->counter++;
 718         if (dev_priv->counter > 0x7FFFFFFFUL)
 719                 dev_priv->counter = 1;
 720         if (master_priv->sarea_priv)
 721                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 722
 723         BEGIN_LP_RING(4);
 724         OUT_RING(MI_STORE_DWORD_INDEX);
 725         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 726         OUT_RING(dev_priv->counter);
 727         OUT_RING(MI_USER_INTERRUPT);
 728         ADVANCE_LP_RING();
 729
 730         return dev_priv->counter;
 731 }
 732
 733 void i915_user_irq_get(struct drm_device *dev)
 734 {
 735         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 736         unsigned long irqflags;
 737
 738         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 739         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 740                 if (IS_IRONLAKE(dev))
 741                         ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 742                 else
 743                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 744         }
 745         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 746 }
 747
 748 void i915_user_irq_put(struct drm_device *dev)
 749 {
 750         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 751         unsigned long irqflags;
 752
 753         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 754         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 755         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 756                 if (IS_IRONLAKE(dev))
 757                         ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 758                 else
 759                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 760         }
 761         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 762 }
 763
 764 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
 765 {
 766         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 767
 768         if (dev_priv->trace_irq_seqno == 0)
 769                 i915_user_irq_get(dev);
 770
 771         dev_priv->trace_irq_seqno = seqno;
 772 }
 773
 774 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 775 {
 776         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 777         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 778         int ret = 0;
 779
 780         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 781                   READ_BREADCRUMB(dev_priv));
 782
 783         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 784                 if (master_priv->sarea_priv)
 785                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 786                 return 0;
 787         }
 788
 789         if (master_priv->sarea_priv)
 790                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 791
 792         i915_user_irq_get(dev);
 793         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 794                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 795         i915_user_irq_put(dev);
 796
 797         if (ret == -EBUSY) {
 798                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 799                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 800         }
 801
 802         return ret;
 803 }
 804
 805 /* Needs the lock as it touches the ring.
 806  */
 807 int i915_irq_emit(struct drm_device *dev, void *data,
 808                          struct drm_file *file_priv)
 809 {
 810         drm_i915_private_t *dev_priv = dev->dev_private;
 811         drm_i915_irq_emit_t *emit = data;
 812         int result;
 813
 814         if (!dev_priv || !dev_priv->ring.virtual_start) {
 815                 DRM_ERROR("called with no initialization\n");
 816                 return -EINVAL;
 817         }
 818
 819         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 820
 821         mutex_lock(&dev->struct_mutex);
 822         result = i915_emit_irq(dev);
 823         mutex_unlock(&dev->struct_mutex);
 824
 825         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 826                 DRM_ERROR("copy_to_user\n");
 827                 return -EFAULT;
 828         }
 829
 830         return 0;
 831 }
 832
 833 /* Doesn't need the hardware lock.
 834  */
 835 int i915_irq_wait(struct drm_device *dev, void *data,
 836                          struct drm_file *file_priv)
 837 {
 838         drm_i915_private_t *dev_priv = dev->dev_private;
 839         drm_i915_irq_wait_t *irqwait = data;
 840
 841         if (!dev_priv) {
 842                 DRM_ERROR("called with no initialization\n");
 843                 return -EINVAL;
 844         }
 845
 846         return i915_wait_irq(dev, irqwait->irq_seq);
 847 }
 848
 849 /* Called from drm generic code, passed 'crtc' which
 850  * we use as a pipe index
 851  */
 852 int i915_enable_vblank(struct drm_device *dev, int pipe)
 853 {
 854         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 855         unsigned long irqflags;
 856         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 857         u32 pipeconf;
 858
 859         pipeconf = I915_READ(pipeconf_reg);
 860         if (!(pipeconf & PIPEACONF_ENABLE))
 861                 return -EINVAL;
 862
 863         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 864         if (IS_IRONLAKE(dev))
 865                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
 866                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
 867         else if (IS_I965G(dev))
 868                 i915_enable_pipestat(dev_priv, pipe,
 869                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 870         else
 871                 i915_enable_pipestat(dev_priv, pipe,
 872                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 873         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 874         return 0;
 875 }
 876
 877 /* Called from drm generic code, passed 'crtc' which
 878  * we use as a pipe index
 879  */
 880 void i915_disable_vblank(struct drm_device *dev, int pipe)
 881 {
 882         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 883         unsigned long irqflags;
 884
 885         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 886         if (IS_IRONLAKE(dev))
 887                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
 888                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
 889         else
 890                 i915_disable_pipestat(dev_priv, pipe,
 891                                       PIPE_VBLANK_INTERRUPT_ENABLE |
 892                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
 893         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 894 }
 895
 896 void i915_enable_interrupt (struct drm_device *dev)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899
 900         if (!IS_IRONLAKE(dev))
 901                 opregion_enable_asle(dev);
 902         dev_priv->irq_enabled = 1;
 903 }
 904
 905
 906 /* Set the vblank monitor pipe
 907  */
 908 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 909                          struct drm_file *file_priv)
 910 {
 911         drm_i915_private_t *dev_priv = dev->dev_private;
 912
 913         if (!dev_priv) {
 914                 DRM_ERROR("called with no initialization\n");
 915                 return -EINVAL;
 916         }
 917
 918         return 0;
 919 }
 920
 921 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 922                          struct drm_file *file_priv)
 923 {
 924         drm_i915_private_t *dev_priv = dev->dev_private;
 925         drm_i915_vblank_pipe_t *pipe = data;
 926
 927         if (!dev_priv) {
 928                 DRM_ERROR("called with no initialization\n");
 929                 return -EINVAL;
 930         }
 931
 932         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 933
 934         return 0;
 935 }
 936
 937 /**
 938  * Schedule buffer swap at given vertical blank.
 939  */
 940 int i915_vblank_swap(struct drm_device *dev, void *data,
 941                      struct drm_file *file_priv)
 942 {
 943         /* The delayed swap mechanism was fundamentally racy, and has been
 944          * removed.  The model was that the client requested a delayed flip/swap
 945          * from the kernel, then waited for vblank before continuing to perform
 946          * rendering.  The problem was that the kernel might wake the client
 947          * up before it dispatched the vblank swap (since the lock has to be
 948          * held while touching the ringbuffer), in which case the client would
 949          * clear and start the next frame before the swap occurred, and
 950          * flicker would occur in addition to likely missing the vblank.
 951          *
 952          * In the absence of this ioctl, userland falls back to a correct path
 953          * of waiting for a vblank, then dispatching the swap on its own.
 954          * Context switching to userland and back is plenty fast enough for
 955          * meeting the requirements of vblank swapping.
 956          */
 957         return -EINVAL;
 958 }
 959
 960 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
 961         drm_i915_private_t *dev_priv = dev->dev_private;
 962         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
 963 }
 964
 965 /**
 966  * This is called when the chip hasn't reported back with completed
 967  * batchbuffers in a long time. The first time this is called we simply record
 968  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
 969  * again, we assume the chip is wedged and try to fix it.
 970  */
 971 void i915_hangcheck_elapsed(unsigned long data)
 972 {
 973         struct drm_device *dev = (struct drm_device *)data;
 974         drm_i915_private_t *dev_priv = dev->dev_private;
 975         uint32_t acthd;
 976
 977         if (!IS_I965G(dev))
 978                 acthd = I915_READ(ACTHD);
 979         else
 980                 acthd = I915_READ(ACTHD_I965);
 981
 982         /* If all work is done then ACTHD clearly hasn't advanced. */
 983         if (list_empty(&dev_priv->mm.request_list) ||
 984                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
 985                 dev_priv->hangcheck_count = 0;
 986                 return;
 987         }
 988
 989         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
 990                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
 991                 i915_handle_error(dev, true);
 992                 return;
 993         }
 994
 995         /* Reset timer case chip hangs without another request being added */
 996         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 997
 998         if (acthd != dev_priv->last_acthd)
 999                 dev_priv->hangcheck_count = 0;
1000         else
1001                 dev_priv->hangcheck_count++;
1002
1003         dev_priv->last_acthd = acthd;
1004 }
1005
1006 /* drm_dma.h hooks
1007 */
1008 static void ironlake_irq_preinstall(struct drm_device *dev)
1009 {
1010         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1011
1012         I915_WRITE(HWSTAM, 0xeffe);
1013
1014         /* XXX hotplug from PCH */
1015
1016         I915_WRITE(DEIMR, 0xffffffff);
1017         I915_WRITE(DEIER, 0x0);
1018         (void) I915_READ(DEIER);
1019
1020         /* and GT */
1021         I915_WRITE(GTIMR, 0xffffffff);
1022         I915_WRITE(GTIER, 0x0);
1023         (void) I915_READ(GTIER);
1024
1025         /* south display irq */
1026         I915_WRITE(SDEIMR, 0xffffffff);
1027         I915_WRITE(SDEIER, 0x0);
1028         (void) I915_READ(SDEIER);
1029 }
1030
1031 static int ironlake_irq_postinstall(struct drm_device *dev)
1032 {
1033         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1034         /* enable kind of interrupts always enabled */
1035         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1036                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1037         u32 render_mask = GT_USER_INTERRUPT;
1038         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1039                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1040
1041         dev_priv->irq_mask_reg = ~display_mask;
1042         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1043
1044         /* should always can generate irq */
1045         I915_WRITE(DEIIR, I915_READ(DEIIR));
1046         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1047         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1048         (void) I915_READ(DEIER);
1049
1050         /* user interrupt should be enabled, but masked initial */
1051         dev_priv->gt_irq_mask_reg = 0xffffffff;
1052         dev_priv->gt_irq_enable_reg = render_mask;
1053
1054         I915_WRITE(GTIIR, I915_READ(GTIIR));
1055         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1056         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1057         (void) I915_READ(GTIER);
1058
1059         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1060         dev_priv->pch_irq_enable_reg = hotplug_mask;
1061
1062         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1063         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1064         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1065         (void) I915_READ(SDEIER);
1066
1067         return 0;
1068 }
1069
1070 void i915_driver_irq_preinstall(struct drm_device * dev)
1071 {
1072         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1073
1074         atomic_set(&dev_priv->irq_received, 0);
1075
1076         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1077         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1078
1079         if (IS_IRONLAKE(dev)) {
1080                 ironlake_irq_preinstall(dev);
1081                 return;
1082         }
1083
1084         if (I915_HAS_HOTPLUG(dev)) {
1085                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1086                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1087         }
1088
1089         I915_WRITE(HWSTAM, 0xeffe);
1090         I915_WRITE(PIPEASTAT, 0);
1091         I915_WRITE(PIPEBSTAT, 0);
1092         I915_WRITE(IMR, 0xffffffff);
1093         I915_WRITE(IER, 0x0);
1094         (void) I915_READ(IER);
1095 }
1096
1097 /*
1098  * Must be called after intel_modeset_init or hotplug interrupts won't be
1099  * enabled correctly.
1100  */
1101 int i915_driver_irq_postinstall(struct drm_device *dev)
1102 {
1103         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1104         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1105         u32 error_mask;
1106
1107         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1108
1109         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1110
1111         if (IS_IRONLAKE(dev))
1112                 return ironlake_irq_postinstall(dev);
1113
1114         /* Unmask the interrupts that we always want on. */
1115         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1116
1117         dev_priv->pipestat[0] = 0;
1118         dev_priv->pipestat[1] = 0;
1119
1120         if (I915_HAS_HOTPLUG(dev)) {
1121                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1122
1123                 /* Note HDMI and DP share bits */
1124                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1125                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1126                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1127                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1128                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1129                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1130                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1131                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1132                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1133                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1134                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1135                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1136                 /* Ignore TV since it's buggy */
1137
1138                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1139
1140                 /* Enable in IER... */
1141                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1142                 /* and unmask in IMR */
1143                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1144         }
1145
1146         /*
1147          * Enable some error detection, note the instruction error mask
1148          * bit is reserved, so we leave it masked.
1149          */
1150         if (IS_G4X(dev)) {
1151                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1152                                GM45_ERROR_MEM_PRIV |
1153                                GM45_ERROR_CP_PRIV |
1154                                I915_ERROR_MEMORY_REFRESH);
1155         } else {
1156                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1157                                I915_ERROR_MEMORY_REFRESH);
1158         }
1159         I915_WRITE(EMR, error_mask);
1160
1161         /* Disable pipe interrupt enables, clear pending pipe status */
1162         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1163         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1164         /* Clear pending interrupt status */
1165         I915_WRITE(IIR, I915_READ(IIR));
1166
1167         I915_WRITE(IER, enable_mask);
1168         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1169         (void) I915_READ(IER);
1170
1171         opregion_enable_asle(dev);
1172
1173         return 0;
1174 }
1175
1176 static void ironlake_irq_uninstall(struct drm_device *dev)
1177 {
1178         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1179         I915_WRITE(HWSTAM, 0xffffffff);
1180
1181         I915_WRITE(DEIMR, 0xffffffff);
1182         I915_WRITE(DEIER, 0x0);
1183         I915_WRITE(DEIIR, I915_READ(DEIIR));
1184
1185         I915_WRITE(GTIMR, 0xffffffff);
1186         I915_WRITE(GTIER, 0x0);
1187         I915_WRITE(GTIIR, I915_READ(GTIIR));
1188 }
1189
1190 void i915_driver_irq_uninstall(struct drm_device * dev)
1191 {
1192         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1193
1194         if (!dev_priv)
1195                 return;
1196
1197         dev_priv->vblank_pipe = 0;
1198
1199         if (IS_IRONLAKE(dev)) {
1200                 ironlake_irq_uninstall(dev);
1201                 return;
1202         }
1203
1204         if (I915_HAS_HOTPLUG(dev)) {
1205                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1206                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1207         }
1208
1209         I915_WRITE(HWSTAM, 0xffffffff);
1210         I915_WRITE(PIPEASTAT, 0);
1211         I915_WRITE(PIPEBSTAT, 0);
1212         I915_WRITE(IMR, 0xffffffff);
1213         I915_WRITE(IER, 0x0);
1214
1215         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1216         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1217         I915_WRITE(IIR, I915_READ(IIR));
1218 }