drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (IS_I965G(dev))
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 195
 196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 197                 return 1;
 198
 199         return 0;
 200 }
 201
 202 /* Called from drm generic code, passed a 'crtc', which
 203  * we use as a pipe index
 204  */
 205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         unsigned long high_frame;
 209         unsigned long low_frame;
 210         u32 high1, high2, low, count;
 211
 212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 214
 215         if (!i915_pipe_enabled(dev, pipe)) {
 216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 217                                 "pipe %d\n", pipe);
 218                 return 0;
 219         }
 220
 221         /*
 222          * High & low register fields aren't synchronized, so make sure
 223          * we get a low value that's stable across two reads of the high
 224          * register.
 225          */
 226         do {
 227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 230                         PIPE_FRAME_LOW_SHIFT);
 231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 232                          PIPE_FRAME_HIGH_SHIFT);
 233         } while (high1 != high2);
 234
 235         count = (high1 << 8) | low;
 236
 237         return count;
 238 }
 239
 240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 244
 245         if (!i915_pipe_enabled(dev, pipe)) {
 246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 247                                         "pipe %d\n", pipe);
 248                 return 0;
 249         }
 250
 251         return I915_READ(reg);
 252 }
 253
 254 /*
 255  * Handle hotplug events outside the interrupt handler proper.
 256  */
 257 static void i915_hotplug_work_func(struct work_struct *work)
 258 {
 259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 260                                                     hotplug_work);
 261         struct drm_device *dev = dev_priv->dev;
 262         struct drm_mode_config *mode_config = &dev->mode_config;
 263         struct drm_encoder *encoder;
 264
 265         if (mode_config->num_encoder) {
 266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 268
 269                         if (intel_encoder->hot_plug)
 270                                 (*intel_encoder->hot_plug) (intel_encoder);
 271                 }
 272         }
 273         /* Just fire off a uevent and let userspace tell us what to do */
 274         drm_helper_hpd_irq_event(dev);
 275 }
 276
 277 static void i915_handle_rps_change(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         u32 busy_up, busy_down, max_avg, min_avg;
 281         u8 new_delay = dev_priv->cur_delay;
 282
 283         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 284         busy_up = I915_READ(RCPREVBSYTUPAVG);
 285         busy_down = I915_READ(RCPREVBSYTDNAVG);
 286         max_avg = I915_READ(RCBMAXAVG);
 287         min_avg = I915_READ(RCBMINAVG);
 288
 289         /* Handle RCS change request from hw */
 290         if (busy_up > max_avg) {
 291                 if (dev_priv->cur_delay != dev_priv->max_delay)
 292                         new_delay = dev_priv->cur_delay - 1;
 293                 if (new_delay < dev_priv->max_delay)
 294                         new_delay = dev_priv->max_delay;
 295         } else if (busy_down < min_avg) {
 296                 if (dev_priv->cur_delay != dev_priv->min_delay)
 297                         new_delay = dev_priv->cur_delay + 1;
 298                 if (new_delay > dev_priv->min_delay)
 299                         new_delay = dev_priv->min_delay;
 300         }
 301
 302         if (ironlake_set_drps(dev, new_delay))
 303                 dev_priv->cur_delay = new_delay;
 304
 305         return;
 306 }
 307
 308 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 309 {
 310         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 311         int ret = IRQ_NONE;
 312         u32 de_iir, gt_iir, de_ier, pch_iir;
 313         struct drm_i915_master_private *master_priv;
 314         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 315
 316         /* disable master interrupt before clearing iir  */
 317         de_ier = I915_READ(DEIER);
 318         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 319         (void)I915_READ(DEIER);
 320
 321         de_iir = I915_READ(DEIIR);
 322         gt_iir = I915_READ(GTIIR);
 323         pch_iir = I915_READ(SDEIIR);
 324
 325         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 326                 goto done;
 327
 328         ret = IRQ_HANDLED;
 329
 330         if (dev->primary->master) {
 331                 master_priv = dev->primary->master->driver_priv;
 332                 if (master_priv->sarea_priv)
 333                         master_priv->sarea_priv->last_dispatch =
 334                                 READ_BREADCRUMB(dev_priv);
 335         }
 336
 337         if (gt_iir & GT_PIPE_NOTIFY) {
 338                 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
 339                 render_ring->irq_gem_seqno = seqno;
 340                 trace_i915_gem_request_complete(dev, seqno);
 341                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 344         }
 345         if (gt_iir & GT_BSD_USER_INTERRUPT)
 346                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 347
 348
 349         if (de_iir & DE_GSE)
 350                 ironlake_opregion_gse_intr(dev);
 351
 352         if (de_iir & DE_PLANEA_FLIP_DONE) {
 353                 intel_prepare_page_flip(dev, 0);
 354                 intel_finish_page_flip(dev, 0);
 355         }
 356
 357         if (de_iir & DE_PLANEB_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 1);
 359                 intel_finish_page_flip(dev, 1);
 360         }
 361
 362         if (de_iir & DE_PIPEA_VBLANK)
 363                 drm_handle_vblank(dev, 0);
 364
 365         if (de_iir & DE_PIPEB_VBLANK)
 366                 drm_handle_vblank(dev, 1);
 367
 368         /* check event from PCH */
 369         if ((de_iir & DE_PCH_EVENT) &&
 370             (pch_iir & SDE_HOTPLUG_MASK)) {
 371                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 372         }
 373
 374         if (de_iir & DE_PCU_EVENT) {
 375                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 376                 i915_handle_rps_change(dev);
 377         }
 378
 379         /* should clear PCH hotplug event before clear CPU irq */
 380         I915_WRITE(SDEIIR, pch_iir);
 381         I915_WRITE(GTIIR, gt_iir);
 382         I915_WRITE(DEIIR, de_iir);
 383
 384 done:
 385         I915_WRITE(DEIER, de_ier);
 386         (void)I915_READ(DEIER);
 387
 388         return ret;
 389 }
 390
 391 /**
 392  * i915_error_work_func - do process context error handling work
 393  * @work: work struct
 394  *
 395  * Fire an error uevent so userspace can see that a hang or error
 396  * was detected.
 397  */
 398 static void i915_error_work_func(struct work_struct *work)
 399 {
 400         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 401                                                     error_work);
 402         struct drm_device *dev = dev_priv->dev;
 403         char *error_event[] = { "ERROR=1", NULL };
 404         char *reset_event[] = { "RESET=1", NULL };
 405         char *reset_done_event[] = { "ERROR=0", NULL };
 406
 407         DRM_DEBUG_DRIVER("generating error event\n");
 408         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 409
 410         if (atomic_read(&dev_priv->mm.wedged)) {
 411                 if (IS_I965G(dev)) {
 412                         DRM_DEBUG_DRIVER("resetting chip\n");
 413                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 414                         if (!i965_reset(dev, GDRST_RENDER)) {
 415                                 atomic_set(&dev_priv->mm.wedged, 0);
 416                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 417                         }
 418                 } else {
 419                         DRM_DEBUG_DRIVER("reboot required\n");
 420                 }
 421         }
 422 }
 423
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_gem_object *src)
 427 {
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         struct drm_i915_error_object *dst;
 430         struct drm_i915_gem_object *src_priv;
 431         int page, page_count;
 432         u32 reloc_offset;
 433
 434         if (src == NULL)
 435                 return NULL;
 436
 437         src_priv = to_intel_bo(src);
 438         if (src_priv->pages == NULL)
 439                 return NULL;
 440
 441         page_count = src->size / PAGE_SIZE;
 442
 443         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 444         if (dst == NULL)
 445                 return NULL;
 446
 447         reloc_offset = src_priv->gtt_offset;
 448         for (page = 0; page < page_count; page++) {
 449                 unsigned long flags;
 450                 void __iomem *s;
 451                 void *d;
 452
 453                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 454                 if (d == NULL)
 455                         goto unwind;
 456
 457                 local_irq_save(flags);
 458                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 459                                              reloc_offset);
 460                 memcpy_fromio(d, s, PAGE_SIZE);
 461                 io_mapping_unmap_atomic(s);
 462                 local_irq_restore(flags);
 463
 464                 dst->pages[page] = d;
 465
 466                 reloc_offset += PAGE_SIZE;
 467         }
 468         dst->page_count = page_count;
 469         dst->gtt_offset = src_priv->gtt_offset;
 470
 471         return dst;
 472
 473 unwind:
 474         while (page--)
 475                 kfree(dst->pages[page]);
 476         kfree(dst);
 477         return NULL;
 478 }
 479
 480 static void
 481 i915_error_object_free(struct drm_i915_error_object *obj)
 482 {
 483         int page;
 484
 485         if (obj == NULL)
 486                 return;
 487
 488         for (page = 0; page < obj->page_count; page++)
 489                 kfree(obj->pages[page]);
 490
 491         kfree(obj);
 492 }
 493
 494 static void
 495 i915_error_state_free(struct drm_device *dev,
 496                       struct drm_i915_error_state *error)
 497 {
 498         i915_error_object_free(error->batchbuffer[0]);
 499         i915_error_object_free(error->batchbuffer[1]);
 500         i915_error_object_free(error->ringbuffer);
 501         kfree(error->active_bo);
 502         kfree(error->overlay);
 503         kfree(error);
 504 }
 505
 506 static u32
 507 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 508 {
 509         u32 cmd;
 510
 511         if (IS_I830(dev) || IS_845G(dev))
 512                 cmd = MI_BATCH_BUFFER;
 513         else if (IS_I965G(dev))
 514                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 515                        MI_BATCH_NON_SECURE_I965);
 516         else
 517                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 518
 519         return ring[0] == cmd ? ring[1] : 0;
 520 }
 521
 522 static u32
 523 i915_ringbuffer_last_batch(struct drm_device *dev)
 524 {
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         u32 head, bbaddr;
 527         u32 *ring;
 528
 529         /* Locate the current position in the ringbuffer and walk back
 530          * to find the most recently dispatched batch buffer.
 531          */
 532         bbaddr = 0;
 533         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 534         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 535
 536         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 537                 bbaddr = i915_get_bbaddr(dev, ring);
 538                 if (bbaddr)
 539                         break;
 540         }
 541
 542         if (bbaddr == 0) {
 543                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 544                                 + dev_priv->render_ring.size);
 545                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 546                         bbaddr = i915_get_bbaddr(dev, ring);
 547                         if (bbaddr)
 548                                 break;
 549                 }
 550         }
 551
 552         return bbaddr;
 553 }
 554
 555 /**
 556  * i915_capture_error_state - capture an error record for later analysis
 557  * @dev: drm device
 558  *
 559  * Should be called when an error is detected (either a hang or an error
 560  * interrupt) to capture error state from the time of the error.  Fills
 561  * out a structure which becomes available in debugfs for user level tools
 562  * to pick up.
 563  */
 564 static void i915_capture_error_state(struct drm_device *dev)
 565 {
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct drm_i915_gem_object *obj_priv;
 568         struct drm_i915_error_state *error;
 569         struct drm_gem_object *batchbuffer[2];
 570         unsigned long flags;
 571         u32 bbaddr;
 572         int count;
 573
 574         spin_lock_irqsave(&dev_priv->error_lock, flags);
 575         error = dev_priv->first_error;
 576         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 577         if (error)
 578                 return;
 579
 580         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 581         if (!error) {
 582                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 583                 return;
 584         }
 585
 586         error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
 587         error->eir = I915_READ(EIR);
 588         error->pgtbl_er = I915_READ(PGTBL_ER);
 589         error->pipeastat = I915_READ(PIPEASTAT);
 590         error->pipebstat = I915_READ(PIPEBSTAT);
 591         error->instpm = I915_READ(INSTPM);
 592         if (!IS_I965G(dev)) {
 593                 error->ipeir = I915_READ(IPEIR);
 594                 error->ipehr = I915_READ(IPEHR);
 595                 error->instdone = I915_READ(INSTDONE);
 596                 error->acthd = I915_READ(ACTHD);
 597                 error->bbaddr = 0;
 598         } else {
 599                 error->ipeir = I915_READ(IPEIR_I965);
 600                 error->ipehr = I915_READ(IPEHR_I965);
 601                 error->instdone = I915_READ(INSTDONE_I965);
 602                 error->instps = I915_READ(INSTPS);
 603                 error->instdone1 = I915_READ(INSTDONE1);
 604                 error->acthd = I915_READ(ACTHD_I965);
 605                 error->bbaddr = I915_READ64(BB_ADDR);
 606         }
 607
 608         bbaddr = i915_ringbuffer_last_batch(dev);
 609
 610         /* Grab the current batchbuffer, most likely to have crashed. */
 611         batchbuffer[0] = NULL;
 612         batchbuffer[1] = NULL;
 613         count = 0;
 614         list_for_each_entry(obj_priv,
 615                         &dev_priv->render_ring.active_list, list) {
 616
 617                 struct drm_gem_object *obj = &obj_priv->base;
 618
 619                 if (batchbuffer[0] == NULL &&
 620                     bbaddr >= obj_priv->gtt_offset &&
 621                     bbaddr < obj_priv->gtt_offset + obj->size)
 622                         batchbuffer[0] = obj;
 623
 624                 if (batchbuffer[1] == NULL &&
 625                     error->acthd >= obj_priv->gtt_offset &&
 626                     error->acthd < obj_priv->gtt_offset + obj->size)
 627                         batchbuffer[1] = obj;
 628
 629                 count++;
 630         }
 631         /* Scan the other lists for completeness for those bizarre errors. */
 632         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 633                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
 634                         struct drm_gem_object *obj = &obj_priv->base;
 635
 636                         if (batchbuffer[0] == NULL &&
 637                             bbaddr >= obj_priv->gtt_offset &&
 638                             bbaddr < obj_priv->gtt_offset + obj->size)
 639                                 batchbuffer[0] = obj;
 640
 641                         if (batchbuffer[1] == NULL &&
 642                             error->acthd >= obj_priv->gtt_offset &&
 643                             error->acthd < obj_priv->gtt_offset + obj->size)
 644                                 batchbuffer[1] = obj;
 645
 646                         if (batchbuffer[0] && batchbuffer[1])
 647                                 break;
 648                 }
 649         }
 650         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 651                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 652                         struct drm_gem_object *obj = &obj_priv->base;
 653
 654                         if (batchbuffer[0] == NULL &&
 655                             bbaddr >= obj_priv->gtt_offset &&
 656                             bbaddr < obj_priv->gtt_offset + obj->size)
 657                                 batchbuffer[0] = obj;
 658
 659                         if (batchbuffer[1] == NULL &&
 660                             error->acthd >= obj_priv->gtt_offset &&
 661                             error->acthd < obj_priv->gtt_offset + obj->size)
 662                                 batchbuffer[1] = obj;
 663
 664                         if (batchbuffer[0] && batchbuffer[1])
 665                                 break;
 666                 }
 667         }
 668
 669         /* We need to copy these to an anonymous buffer as the simplest
 670          * method to avoid being overwritten by userpace.
 671          */
 672         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 673         if (batchbuffer[1] != batchbuffer[0])
 674                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 675         else
 676                 error->batchbuffer[1] = NULL;
 677
 678         /* Record the ringbuffer */
 679         error->ringbuffer = i915_error_object_create(dev,
 680                         dev_priv->render_ring.gem_object);
 681
 682         /* Record buffers on the active list. */
 683         error->active_bo = NULL;
 684         error->active_bo_count = 0;
 685
 686         if (count)
 687                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 688                                            GFP_ATOMIC);
 689
 690         if (error->active_bo) {
 691                 int i = 0;
 692                 list_for_each_entry(obj_priv,
 693                                 &dev_priv->render_ring.active_list, list) {
 694                         struct drm_gem_object *obj = &obj_priv->base;
 695
 696                         error->active_bo[i].size = obj->size;
 697                         error->active_bo[i].name = obj->name;
 698                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 699                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 700                         error->active_bo[i].read_domains = obj->read_domains;
 701                         error->active_bo[i].write_domain = obj->write_domain;
 702                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 703                         error->active_bo[i].pinned = 0;
 704                         if (obj_priv->pin_count > 0)
 705                                 error->active_bo[i].pinned = 1;
 706                         if (obj_priv->user_pin_count > 0)
 707                                 error->active_bo[i].pinned = -1;
 708                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 709                         error->active_bo[i].dirty = obj_priv->dirty;
 710                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 711
 712                         if (++i == count)
 713                                 break;
 714                 }
 715                 error->active_bo_count = i;
 716         }
 717
 718         do_gettimeofday(&error->time);
 719
 720         error->overlay = intel_overlay_capture_error_state(dev);
 721
 722         spin_lock_irqsave(&dev_priv->error_lock, flags);
 723         if (dev_priv->first_error == NULL) {
 724                 dev_priv->first_error = error;
 725                 error = NULL;
 726         }
 727         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 728
 729         if (error)
 730                 i915_error_state_free(dev, error);
 731 }
 732
 733 void i915_destroy_error_state(struct drm_device *dev)
 734 {
 735         struct drm_i915_private *dev_priv = dev->dev_private;
 736         struct drm_i915_error_state *error;
 737
 738         spin_lock(&dev_priv->error_lock);
 739         error = dev_priv->first_error;
 740         dev_priv->first_error = NULL;
 741         spin_unlock(&dev_priv->error_lock);
 742
 743         if (error)
 744                 i915_error_state_free(dev, error);
 745 }
 746
 747 static void i915_report_and_clear_eir(struct drm_device *dev)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750         u32 eir = I915_READ(EIR);
 751
 752         if (!eir)
 753                 return;
 754
 755         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 756                eir);
 757
 758         if (IS_G4X(dev)) {
 759                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 760                         u32 ipeir = I915_READ(IPEIR_I965);
 761
 762                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 763                                I915_READ(IPEIR_I965));
 764                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 765                                I915_READ(IPEHR_I965));
 766                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 767                                I915_READ(INSTDONE_I965));
 768                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 769                                I915_READ(INSTPS));
 770                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 771                                I915_READ(INSTDONE1));
 772                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 773                                I915_READ(ACTHD_I965));
 774                         I915_WRITE(IPEIR_I965, ipeir);
 775                         (void)I915_READ(IPEIR_I965);
 776                 }
 777                 if (eir & GM45_ERROR_PAGE_TABLE) {
 778                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 779                         printk(KERN_ERR "page table error\n");
 780                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 781                                pgtbl_err);
 782                         I915_WRITE(PGTBL_ER, pgtbl_err);
 783                         (void)I915_READ(PGTBL_ER);
 784                 }
 785         }
 786
 787         if (IS_I9XX(dev)) {
 788                 if (eir & I915_ERROR_PAGE_TABLE) {
 789                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 790                         printk(KERN_ERR "page table error\n");
 791                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 792                                pgtbl_err);
 793                         I915_WRITE(PGTBL_ER, pgtbl_err);
 794                         (void)I915_READ(PGTBL_ER);
 795                 }
 796         }
 797
 798         if (eir & I915_ERROR_MEMORY_REFRESH) {
 799                 u32 pipea_stats = I915_READ(PIPEASTAT);
 800                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 801
 802                 printk(KERN_ERR "memory refresh error\n");
 803                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 804                        pipea_stats);
 805                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 806                        pipeb_stats);
 807                 /* pipestat has already been acked */
 808         }
 809         if (eir & I915_ERROR_INSTRUCTION) {
 810                 printk(KERN_ERR "instruction error\n");
 811                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 812                        I915_READ(INSTPM));
 813                 if (!IS_I965G(dev)) {
 814                         u32 ipeir = I915_READ(IPEIR);
 815
 816                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 817                                I915_READ(IPEIR));
 818                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 819                                I915_READ(IPEHR));
 820                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 821                                I915_READ(INSTDONE));
 822                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 823                                I915_READ(ACTHD));
 824                         I915_WRITE(IPEIR, ipeir);
 825                         (void)I915_READ(IPEIR);
 826                 } else {
 827                         u32 ipeir = I915_READ(IPEIR_I965);
 828
 829                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 830                                I915_READ(IPEIR_I965));
 831                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 832                                I915_READ(IPEHR_I965));
 833                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 834                                I915_READ(INSTDONE_I965));
 835                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 836                                I915_READ(INSTPS));
 837                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 838                                I915_READ(INSTDONE1));
 839                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 840                                I915_READ(ACTHD_I965));
 841                         I915_WRITE(IPEIR_I965, ipeir);
 842                         (void)I915_READ(IPEIR_I965);
 843                 }
 844         }
 845
 846         I915_WRITE(EIR, eir);
 847         (void)I915_READ(EIR);
 848         eir = I915_READ(EIR);
 849         if (eir) {
 850                 /*
 851                  * some errors might have become stuck,
 852                  * mask them.
 853                  */
 854                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 855                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 856                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 857         }
 858 }
 859
 860 /**
 861  * i915_handle_error - handle an error interrupt
 862  * @dev: drm device
 863  *
 864  * Do some basic checking of regsiter state at error interrupt time and
 865  * dump it to the syslog.  Also call i915_capture_error_state() to make
 866  * sure we get a record and make it available in debugfs.  Fire a uevent
 867  * so userspace knows something bad happened (should trigger collection
 868  * of a ring dump etc.).
 869  */
 870 static void i915_handle_error(struct drm_device *dev, bool wedged)
 871 {
 872         struct drm_i915_private *dev_priv = dev->dev_private;
 873
 874         i915_capture_error_state(dev);
 875         i915_report_and_clear_eir(dev);
 876
 877         if (wedged) {
 878                 atomic_set(&dev_priv->mm.wedged, 1);
 879
 880                 /*
 881                  * Wakeup waiting processes so they don't hang
 882                  */
 883                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 884         }
 885
 886         queue_work(dev_priv->wq, &dev_priv->error_work);
 887 }
 888
 889 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 890 {
 891         drm_i915_private_t *dev_priv = dev->dev_private;
 892         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 894         struct drm_i915_gem_object *obj_priv;
 895         struct intel_unpin_work *work;
 896         unsigned long flags;
 897         bool stall_detected;
 898
 899         /* Ignore early vblank irqs */
 900         if (intel_crtc == NULL)
 901                 return;
 902
 903         spin_lock_irqsave(&dev->event_lock, flags);
 904         work = intel_crtc->unpin_work;
 905
 906         if (work == NULL || work->pending || !work->enable_stall_check) {
 907                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 908                 spin_unlock_irqrestore(&dev->event_lock, flags);
 909                 return;
 910         }
 911
 912         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 913         obj_priv = to_intel_bo(work->pending_flip_obj);
 914         if(IS_I965G(dev)) {
 915                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 916                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 917         } else {
 918                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 919                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 920                                                         crtc->y * crtc->fb->pitch +
 921                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 922         }
 923
 924         spin_unlock_irqrestore(&dev->event_lock, flags);
 925
 926         if (stall_detected) {
 927                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 928                 intel_prepare_page_flip(dev, intel_crtc->plane);
 929         }
 930 }
 931
 932 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 933 {
 934         struct drm_device *dev = (struct drm_device *) arg;
 935         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 936         struct drm_i915_master_private *master_priv;
 937         u32 iir, new_iir;
 938         u32 pipea_stats, pipeb_stats;
 939         u32 vblank_status;
 940         int vblank = 0;
 941         unsigned long irqflags;
 942         int irq_received;
 943         int ret = IRQ_NONE;
 944         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 945
 946         atomic_inc(&dev_priv->irq_received);
 947
 948         if (HAS_PCH_SPLIT(dev))
 949                 return ironlake_irq_handler(dev);
 950
 951         iir = I915_READ(IIR);
 952
 953         if (IS_I965G(dev))
 954                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 955         else
 956                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 957
 958         for (;;) {
 959                 irq_received = iir != 0;
 960
 961                 /* Can't rely on pipestat interrupt bit in iir as it might
 962                  * have been cleared after the pipestat interrupt was received.
 963                  * It doesn't set the bit in iir again, but it still produces
 964                  * interrupts (for non-MSI).
 965                  */
 966                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 967                 pipea_stats = I915_READ(PIPEASTAT);
 968                 pipeb_stats = I915_READ(PIPEBSTAT);
 969
 970                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 971                         i915_handle_error(dev, false);
 972
 973                 /*
 974                  * Clear the PIPE(A|B)STAT regs before the IIR
 975                  */
 976                 if (pipea_stats & 0x8000ffff) {
 977                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 978                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 979                         I915_WRITE(PIPEASTAT, pipea_stats);
 980                         irq_received = 1;
 981                 }
 982
 983                 if (pipeb_stats & 0x8000ffff) {
 984                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 985                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 986                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 987                         irq_received = 1;
 988                 }
 989                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 990
 991                 if (!irq_received)
 992                         break;
 993
 994                 ret = IRQ_HANDLED;
 995
 996                 /* Consume port.  Then clear IIR or we'll miss events */
 997                 if ((I915_HAS_HOTPLUG(dev)) &&
 998                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 999                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1000
1001                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1002                                   hotplug_status);
1003                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1004                                 queue_work(dev_priv->wq,
1005                                            &dev_priv->hotplug_work);
1006
1007                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1008                         I915_READ(PORT_HOTPLUG_STAT);
1009                 }
1010
1011                 I915_WRITE(IIR, iir);
1012                 new_iir = I915_READ(IIR); /* Flush posted writes */
1013
1014                 if (dev->primary->master) {
1015                         master_priv = dev->primary->master->driver_priv;
1016                         if (master_priv->sarea_priv)
1017                                 master_priv->sarea_priv->last_dispatch =
1018                                         READ_BREADCRUMB(dev_priv);
1019                 }
1020
1021                 if (iir & I915_USER_INTERRUPT) {
1022                         u32 seqno =
1023                                 render_ring->get_gem_seqno(dev, render_ring);
1024                         render_ring->irq_gem_seqno = seqno;
1025                         trace_i915_gem_request_complete(dev, seqno);
1026                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1027                         dev_priv->hangcheck_count = 0;
1028                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1029                 }
1030
1031                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1032                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1033
1034                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1035                         intel_prepare_page_flip(dev, 0);
1036                         if (dev_priv->flip_pending_is_done)
1037                                 intel_finish_page_flip_plane(dev, 0);
1038                 }
1039
1040                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1041                         intel_prepare_page_flip(dev, 1);
1042                         if (dev_priv->flip_pending_is_done)
1043                                 intel_finish_page_flip_plane(dev, 1);
1044                 }
1045
1046                 if (pipea_stats & vblank_status) {
1047                         vblank++;
1048                         drm_handle_vblank(dev, 0);
1049                         if (!dev_priv->flip_pending_is_done) {
1050                                 i915_pageflip_stall_check(dev, 0);
1051                                 intel_finish_page_flip(dev, 0);
1052                         }
1053                 }
1054
1055                 if (pipeb_stats & vblank_status) {
1056                         vblank++;
1057                         drm_handle_vblank(dev, 1);
1058                         if (!dev_priv->flip_pending_is_done) {
1059                                 i915_pageflip_stall_check(dev, 1);
1060                                 intel_finish_page_flip(dev, 1);
1061                         }
1062                 }
1063
1064                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1065                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1066                     (iir & I915_ASLE_INTERRUPT))
1067                         opregion_asle_intr(dev);
1068
1069                 /* With MSI, interrupts are only generated when iir
1070                  * transitions from zero to nonzero.  If another bit got
1071                  * set while we were handling the existing iir bits, then
1072                  * we would never get another interrupt.
1073                  *
1074                  * This is fine on non-MSI as well, as if we hit this path
1075                  * we avoid exiting the interrupt handler only to generate
1076                  * another one.
1077                  *
1078                  * Note that for MSI this could cause a stray interrupt report
1079                  * if an interrupt landed in the time between writing IIR and
1080                  * the posting read.  This should be rare enough to never
1081                  * trigger the 99% of 100,000 interrupts test for disabling
1082                  * stray interrupts.
1083                  */
1084                 iir = new_iir;
1085         }
1086
1087         return ret;
1088 }
1089
1090 static int i915_emit_irq(struct drm_device * dev)
1091 {
1092         drm_i915_private_t *dev_priv = dev->dev_private;
1093         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1094
1095         i915_kernel_lost_context(dev);
1096
1097         DRM_DEBUG_DRIVER("\n");
1098
1099         dev_priv->counter++;
1100         if (dev_priv->counter > 0x7FFFFFFFUL)
1101                 dev_priv->counter = 1;
1102         if (master_priv->sarea_priv)
1103                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1104
1105         BEGIN_LP_RING(4);
1106         OUT_RING(MI_STORE_DWORD_INDEX);
1107         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1108         OUT_RING(dev_priv->counter);
1109         OUT_RING(MI_USER_INTERRUPT);
1110         ADVANCE_LP_RING();
1111
1112         return dev_priv->counter;
1113 }
1114
1115 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1116 {
1117         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1118         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1119
1120         if (dev_priv->trace_irq_seqno == 0)
1121                 render_ring->user_irq_get(dev, render_ring);
1122
1123         dev_priv->trace_irq_seqno = seqno;
1124 }
1125
1126 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1127 {
1128         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1129         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1130         int ret = 0;
1131         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1132
1133         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1134                   READ_BREADCRUMB(dev_priv));
1135
1136         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1137                 if (master_priv->sarea_priv)
1138                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1139                 return 0;
1140         }
1141
1142         if (master_priv->sarea_priv)
1143                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1144
1145         render_ring->user_irq_get(dev, render_ring);
1146         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1147                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1148         render_ring->user_irq_put(dev, render_ring);
1149
1150         if (ret == -EBUSY) {
1151                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1152                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1153         }
1154
1155         return ret;
1156 }
1157
1158 /* Needs the lock as it touches the ring.
1159  */
1160 int i915_irq_emit(struct drm_device *dev, void *data,
1161                          struct drm_file *file_priv)
1162 {
1163         drm_i915_private_t *dev_priv = dev->dev_private;
1164         drm_i915_irq_emit_t *emit = data;
1165         int result;
1166
1167         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1168                 DRM_ERROR("called with no initialization\n");
1169                 return -EINVAL;
1170         }
1171
1172         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1173
1174         mutex_lock(&dev->struct_mutex);
1175         result = i915_emit_irq(dev);
1176         mutex_unlock(&dev->struct_mutex);
1177
1178         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1179                 DRM_ERROR("copy_to_user\n");
1180                 return -EFAULT;
1181         }
1182
1183         return 0;
1184 }
1185
1186 /* Doesn't need the hardware lock.
1187  */
1188 int i915_irq_wait(struct drm_device *dev, void *data,
1189                          struct drm_file *file_priv)
1190 {
1191         drm_i915_private_t *dev_priv = dev->dev_private;
1192         drm_i915_irq_wait_t *irqwait = data;
1193
1194         if (!dev_priv) {
1195                 DRM_ERROR("called with no initialization\n");
1196                 return -EINVAL;
1197         }
1198
1199         return i915_wait_irq(dev, irqwait->irq_seq);
1200 }
1201
1202 /* Called from drm generic code, passed 'crtc' which
1203  * we use as a pipe index
1204  */
1205 int i915_enable_vblank(struct drm_device *dev, int pipe)
1206 {
1207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1208         unsigned long irqflags;
1209         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1210         u32 pipeconf;
1211
1212         pipeconf = I915_READ(pipeconf_reg);
1213         if (!(pipeconf & PIPEACONF_ENABLE))
1214                 return -EINVAL;
1215
1216         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1217         if (HAS_PCH_SPLIT(dev))
1218                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1219                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1220         else if (IS_I965G(dev))
1221                 i915_enable_pipestat(dev_priv, pipe,
1222                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1223         else
1224                 i915_enable_pipestat(dev_priv, pipe,
1225                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1226         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1227         return 0;
1228 }
1229
1230 /* Called from drm generic code, passed 'crtc' which
1231  * we use as a pipe index
1232  */
1233 void i915_disable_vblank(struct drm_device *dev, int pipe)
1234 {
1235         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1236         unsigned long irqflags;
1237
1238         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1239         if (HAS_PCH_SPLIT(dev))
1240                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1241                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1242         else
1243                 i915_disable_pipestat(dev_priv, pipe,
1244                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1245                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1246         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1247 }
1248
1249 void i915_enable_interrupt (struct drm_device *dev)
1250 {
1251         struct drm_i915_private *dev_priv = dev->dev_private;
1252
1253         if (!HAS_PCH_SPLIT(dev))
1254                 opregion_enable_asle(dev);
1255         dev_priv->irq_enabled = 1;
1256 }
1257
1258
1259 /* Set the vblank monitor pipe
1260  */
1261 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1262                          struct drm_file *file_priv)
1263 {
1264         drm_i915_private_t *dev_priv = dev->dev_private;
1265
1266         if (!dev_priv) {
1267                 DRM_ERROR("called with no initialization\n");
1268                 return -EINVAL;
1269         }
1270
1271         return 0;
1272 }
1273
1274 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1275                          struct drm_file *file_priv)
1276 {
1277         drm_i915_private_t *dev_priv = dev->dev_private;
1278         drm_i915_vblank_pipe_t *pipe = data;
1279
1280         if (!dev_priv) {
1281                 DRM_ERROR("called with no initialization\n");
1282                 return -EINVAL;
1283         }
1284
1285         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1286
1287         return 0;
1288 }
1289
1290 /**
1291  * Schedule buffer swap at given vertical blank.
1292  */
1293 int i915_vblank_swap(struct drm_device *dev, void *data,
1294                      struct drm_file *file_priv)
1295 {
1296         /* The delayed swap mechanism was fundamentally racy, and has been
1297          * removed.  The model was that the client requested a delayed flip/swap
1298          * from the kernel, then waited for vblank before continuing to perform
1299          * rendering.  The problem was that the kernel might wake the client
1300          * up before it dispatched the vblank swap (since the lock has to be
1301          * held while touching the ringbuffer), in which case the client would
1302          * clear and start the next frame before the swap occurred, and
1303          * flicker would occur in addition to likely missing the vblank.
1304          *
1305          * In the absence of this ioctl, userland falls back to a correct path
1306          * of waiting for a vblank, then dispatching the swap on its own.
1307          * Context switching to userland and back is plenty fast enough for
1308          * meeting the requirements of vblank swapping.
1309          */
1310         return -EINVAL;
1311 }
1312
1313 struct drm_i915_gem_request *
1314 i915_get_tail_request(struct drm_device *dev)
1315 {
1316         drm_i915_private_t *dev_priv = dev->dev_private;
1317         return list_entry(dev_priv->render_ring.request_list.prev,
1318                         struct drm_i915_gem_request, list);
1319 }
1320
1321 /**
1322  * This is called when the chip hasn't reported back with completed
1323  * batchbuffers in a long time. The first time this is called we simply record
1324  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1325  * again, we assume the chip is wedged and try to fix it.
1326  */
1327 void i915_hangcheck_elapsed(unsigned long data)
1328 {
1329         struct drm_device *dev = (struct drm_device *)data;
1330         drm_i915_private_t *dev_priv = dev->dev_private;
1331         uint32_t acthd, instdone, instdone1;
1332
1333         /* No reset support on this chip yet. */
1334         if (IS_GEN6(dev))
1335                 return;
1336
1337         if (!IS_I965G(dev)) {
1338                 acthd = I915_READ(ACTHD);
1339                 instdone = I915_READ(INSTDONE);
1340                 instdone1 = 0;
1341         } else {
1342                 acthd = I915_READ(ACTHD_I965);
1343                 instdone = I915_READ(INSTDONE_I965);
1344                 instdone1 = I915_READ(INSTDONE1);
1345         }
1346
1347         /* If all work is done then ACTHD clearly hasn't advanced. */
1348         if (list_empty(&dev_priv->render_ring.request_list) ||
1349                 i915_seqno_passed(i915_get_gem_seqno(dev,
1350                                 &dev_priv->render_ring),
1351                         i915_get_tail_request(dev)->seqno)) {
1352                 bool missed_wakeup = false;
1353
1354                 dev_priv->hangcheck_count = 0;
1355
1356                 /* Issue a wake-up to catch stuck h/w. */
1357                 if (dev_priv->render_ring.waiting_gem_seqno &&
1358                     waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1359                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1360                         missed_wakeup = true;
1361                 }
1362
1363                 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1364                     waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1365                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1366                         missed_wakeup = true;
1367                 }
1368
1369                 if (missed_wakeup)
1370                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1371                 return;
1372         }
1373
1374         if (dev_priv->last_acthd == acthd &&
1375             dev_priv->last_instdone == instdone &&
1376             dev_priv->last_instdone1 == instdone1) {
1377                 if (dev_priv->hangcheck_count++ > 1) {
1378                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1379                         i915_handle_error(dev, true);
1380                         return;
1381                 }
1382         } else {
1383                 dev_priv->hangcheck_count = 0;
1384
1385                 dev_priv->last_acthd = acthd;
1386                 dev_priv->last_instdone = instdone;
1387                 dev_priv->last_instdone1 = instdone1;
1388         }
1389
1390         /* Reset timer case chip hangs without another request being added */
1391         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1392 }
1393
1394 /* drm_dma.h hooks
1395 */
1396 static void ironlake_irq_preinstall(struct drm_device *dev)
1397 {
1398         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1399
1400         I915_WRITE(HWSTAM, 0xeffe);
1401
1402         /* XXX hotplug from PCH */
1403
1404         I915_WRITE(DEIMR, 0xffffffff);
1405         I915_WRITE(DEIER, 0x0);
1406         (void) I915_READ(DEIER);
1407
1408         /* and GT */
1409         I915_WRITE(GTIMR, 0xffffffff);
1410         I915_WRITE(GTIER, 0x0);
1411         (void) I915_READ(GTIER);
1412
1413         /* south display irq */
1414         I915_WRITE(SDEIMR, 0xffffffff);
1415         I915_WRITE(SDEIER, 0x0);
1416         (void) I915_READ(SDEIER);
1417 }
1418
1419 static int ironlake_irq_postinstall(struct drm_device *dev)
1420 {
1421         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1422         /* enable kind of interrupts always enabled */
1423         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1424                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1425         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1426         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1427                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1428
1429         dev_priv->irq_mask_reg = ~display_mask;
1430         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1431
1432         /* should always can generate irq */
1433         I915_WRITE(DEIIR, I915_READ(DEIIR));
1434         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1435         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1436         (void) I915_READ(DEIER);
1437
1438         /* Gen6 only needs render pipe_control now */
1439         if (IS_GEN6(dev))
1440                 render_mask = GT_PIPE_NOTIFY;
1441
1442         dev_priv->gt_irq_mask_reg = ~render_mask;
1443         dev_priv->gt_irq_enable_reg = render_mask;
1444
1445         I915_WRITE(GTIIR, I915_READ(GTIIR));
1446         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1447         if (IS_GEN6(dev))
1448                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1449         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1450         (void) I915_READ(GTIER);
1451
1452         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1453         dev_priv->pch_irq_enable_reg = hotplug_mask;
1454
1455         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1456         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1457         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1458         (void) I915_READ(SDEIER);
1459
1460         if (IS_IRONLAKE_M(dev)) {
1461                 /* Clear & enable PCU event interrupts */
1462                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1463                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1464                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1465         }
1466
1467         return 0;
1468 }
1469
1470 void i915_driver_irq_preinstall(struct drm_device * dev)
1471 {
1472         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1473
1474         atomic_set(&dev_priv->irq_received, 0);
1475
1476         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1477         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1478
1479         if (HAS_PCH_SPLIT(dev)) {
1480                 ironlake_irq_preinstall(dev);
1481                 return;
1482         }
1483
1484         if (I915_HAS_HOTPLUG(dev)) {
1485                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1486                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1487         }
1488
1489         I915_WRITE(HWSTAM, 0xeffe);
1490         I915_WRITE(PIPEASTAT, 0);
1491         I915_WRITE(PIPEBSTAT, 0);
1492         I915_WRITE(IMR, 0xffffffff);
1493         I915_WRITE(IER, 0x0);
1494         (void) I915_READ(IER);
1495 }
1496
1497 /*
1498  * Must be called after intel_modeset_init or hotplug interrupts won't be
1499  * enabled correctly.
1500  */
1501 int i915_driver_irq_postinstall(struct drm_device *dev)
1502 {
1503         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1504         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1505         u32 error_mask;
1506
1507         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1508
1509         if (HAS_BSD(dev))
1510                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1511
1512         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1513
1514         if (HAS_PCH_SPLIT(dev))
1515                 return ironlake_irq_postinstall(dev);
1516
1517         /* Unmask the interrupts that we always want on. */
1518         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1519
1520         dev_priv->pipestat[0] = 0;
1521         dev_priv->pipestat[1] = 0;
1522
1523         if (I915_HAS_HOTPLUG(dev)) {
1524                 /* Enable in IER... */
1525                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1526                 /* and unmask in IMR */
1527                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1528         }
1529
1530         /*
1531          * Enable some error detection, note the instruction error mask
1532          * bit is reserved, so we leave it masked.
1533          */
1534         if (IS_G4X(dev)) {
1535                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1536                                GM45_ERROR_MEM_PRIV |
1537                                GM45_ERROR_CP_PRIV |
1538                                I915_ERROR_MEMORY_REFRESH);
1539         } else {
1540                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1541                                I915_ERROR_MEMORY_REFRESH);
1542         }
1543         I915_WRITE(EMR, error_mask);
1544
1545         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1546         I915_WRITE(IER, enable_mask);
1547         (void) I915_READ(IER);
1548
1549         if (I915_HAS_HOTPLUG(dev)) {
1550                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1551
1552                 /* Note HDMI and DP share bits */
1553                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1554                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1555                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1556                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1557                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1558                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1559                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1560                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1561                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1562                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1563                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1564                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1565
1566                         /* Programming the CRT detection parameters tends
1567                            to generate a spurious hotplug event about three
1568                            seconds later.  So just do it once.
1569                         */
1570                         if (IS_G4X(dev))
1571                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1572                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1573                 }
1574
1575                 /* Ignore TV since it's buggy */
1576
1577                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1578         }
1579
1580         opregion_enable_asle(dev);
1581
1582         return 0;
1583 }
1584
1585 static void ironlake_irq_uninstall(struct drm_device *dev)
1586 {
1587         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1588         I915_WRITE(HWSTAM, 0xffffffff);
1589
1590         I915_WRITE(DEIMR, 0xffffffff);
1591         I915_WRITE(DEIER, 0x0);
1592         I915_WRITE(DEIIR, I915_READ(DEIIR));
1593
1594         I915_WRITE(GTIMR, 0xffffffff);
1595         I915_WRITE(GTIER, 0x0);
1596         I915_WRITE(GTIIR, I915_READ(GTIIR));
1597 }
1598
1599 void i915_driver_irq_uninstall(struct drm_device * dev)
1600 {
1601         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1602
1603         if (!dev_priv)
1604                 return;
1605
1606         dev_priv->vblank_pipe = 0;
1607
1608         if (HAS_PCH_SPLIT(dev)) {
1609                 ironlake_irq_uninstall(dev);
1610                 return;
1611         }
1612
1613         if (I915_HAS_HOTPLUG(dev)) {
1614                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1615                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1616         }
1617
1618         I915_WRITE(HWSTAM, 0xffffffff);
1619         I915_WRITE(PIPEASTAT, 0);
1620         I915_WRITE(PIPEBSTAT, 0);
1621         I915_WRITE(IMR, 0xffffffff);
1622         I915_WRITE(IER, 0x0);
1623
1624         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1625         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1626         I915_WRITE(IIR, I915_READ(IIR));
1627 }